Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
1e698235 | 3 | 2001, 2002, 2003 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "symfile.h" | |
30 | #include "gdb_string.h" | |
afd7eef0 | 31 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
a42dd537 | 36 | #include "solib-svr4.h" |
4be87837 | 37 | #include "osabi.h" |
34e8f22d RE |
38 | |
39 | #include "arm-tdep.h" | |
26216b98 | 40 | #include "gdb/sim-arm.h" |
34e8f22d | 41 | |
082fc60d RE |
42 | #include "elf-bfd.h" |
43 | #include "coff/internal.h" | |
97e03143 | 44 | #include "elf/arm.h" |
c906108c | 45 | |
26216b98 AC |
46 | #include "gdb_assert.h" |
47 | ||
6529d2dd AC |
48 | static int arm_debug; |
49 | ||
2a451106 KB |
50 | /* Each OS has a different mechanism for accessing the various |
51 | registers stored in the sigcontext structure. | |
52 | ||
53 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
54 | function pointer) which may be used to determine the addresses | |
55 | of the various saved registers in the sigcontext structure. | |
56 | ||
57 | For the ARM target, there are three parameters to this function. | |
58 | The first is the pc value of the frame under consideration, the | |
59 | second the stack pointer of this frame, and the last is the | |
60 | register number to fetch. | |
61 | ||
62 | If the tm.h file does not define this macro, then it's assumed that | |
63 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
64 | be 0. | |
65 | ||
66 | When it comes time to multi-arching this code, see the identically | |
67 | named machinery in ia64-tdep.c for an example of how it could be | |
68 | done. It should not be necessary to modify the code below where | |
69 | this macro is used. */ | |
70 | ||
3bb04bdd AC |
71 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
72 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
73 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
74 | #endif | |
75 | #else | |
76 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
77 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
78 | #endif |
79 | ||
082fc60d RE |
80 | /* Macros for setting and testing a bit in a minimal symbol that marks |
81 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
82 | is used for this purpose. This field is already being used to store | |
83 | the symbol size, so the assumption is that the symbol size cannot | |
84 | exceed 2^31. | |
85 | ||
86 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
87 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
88 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
89 | i.e. the "info" field with the "special" bit | |
90 | masked out. */ | |
91 | ||
92 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
93 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
94 | | 0x80000000) | |
95 | ||
96 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
97 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
98 | ||
99 | #define MSYMBOL_SIZE(msym) \ | |
100 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
ed9a39eb | 101 | |
afd7eef0 RE |
102 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
103 | static struct cmd_list_element *setarmcmdlist = NULL; | |
104 | static struct cmd_list_element *showarmcmdlist = NULL; | |
105 | ||
94c30b78 | 106 | /* Number of different reg name sets (options). */ |
afd7eef0 | 107 | static int num_disassembly_options; |
bc90b915 FN |
108 | |
109 | /* We have more registers than the disassembler as gdb can print the value | |
110 | of special registers as well. | |
111 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 112 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 113 | |
94c30b78 | 114 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 115 | static char * arm_register_name_strings[] = |
da59e081 JM |
116 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
117 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
118 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
119 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
120 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
121 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 122 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 123 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 124 | |
afd7eef0 RE |
125 | /* Valid register name styles. */ |
126 | static const char **valid_disassembly_styles; | |
ed9a39eb | 127 | |
afd7eef0 RE |
128 | /* Disassembly style to use. Default to "std" register names. */ |
129 | static const char *disassembly_style; | |
94c30b78 | 130 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 131 | static int current_option; |
96baa820 | 132 | |
ed9a39eb | 133 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
134 | style. */ |
135 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 136 | struct cmd_list_element *); |
afd7eef0 | 137 | static void set_disassembly_style (void); |
ed9a39eb | 138 | |
b508a996 RE |
139 | static void convert_from_extended (const struct floatformat *, const void *, |
140 | void *); | |
141 | static void convert_to_extended (const struct floatformat *, void *, | |
142 | const void *); | |
ed9a39eb JM |
143 | |
144 | /* Define other aspects of the stack frame. We keep the offsets of | |
145 | all saved registers, 'cause we need 'em a lot! We also keep the | |
146 | current size of the stack frame, and the offset of the frame | |
147 | pointer from the stack pointer (for frameless functions, and when | |
94c30b78 | 148 | we're still in the prologue of a function with a frame). */ |
ed9a39eb JM |
149 | |
150 | struct frame_extra_info | |
c3b4394c RE |
151 | { |
152 | int framesize; | |
153 | int frameoffset; | |
154 | int framereg; | |
155 | }; | |
ed9a39eb | 156 | |
bc90b915 FN |
157 | /* Addresses for calling Thumb functions have the bit 0 set. |
158 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
159 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
160 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
161 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
162 | ||
39bbf761 | 163 | static int |
ed9a39eb | 164 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 165 | { |
8bedc050 | 166 | return (DEPRECATED_FRAME_SAVED_PC (thisframe) >= LOWEST_PC); |
c906108c SS |
167 | } |
168 | ||
94c30b78 | 169 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
170 | |
171 | int arm_apcs_32 = 1; | |
172 | ||
ed9a39eb JM |
173 | /* Flag set by arm_fix_call_dummy that tells whether the target |
174 | function is a Thumb function. This flag is checked by | |
175 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
176 | its use in valops.c) to pass the function address as an additional | |
177 | parameter. */ | |
c906108c SS |
178 | |
179 | static int target_is_thumb; | |
180 | ||
ed9a39eb JM |
181 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
182 | function is a Thumb function. This flag is checked by | |
183 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
184 | |
185 | static int caller_is_thumb; | |
186 | ||
ed9a39eb JM |
187 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
188 | function. */ | |
c906108c | 189 | |
34e8f22d | 190 | int |
2a451106 | 191 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 192 | { |
c5aa993b | 193 | struct minimal_symbol *sym; |
c906108c | 194 | |
ed9a39eb | 195 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
196 | if (IS_THUMB_ADDR (memaddr)) |
197 | return 1; | |
198 | ||
ed9a39eb | 199 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
200 | sym = lookup_minimal_symbol_by_pc (memaddr); |
201 | if (sym) | |
202 | { | |
c5aa993b | 203 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
204 | } |
205 | else | |
ed9a39eb JM |
206 | { |
207 | return 0; | |
208 | } | |
c906108c SS |
209 | } |
210 | ||
ed9a39eb JM |
211 | /* Determine if the program counter specified in MEMADDR is in a call |
212 | dummy being called from a Thumb function. */ | |
c906108c | 213 | |
34e8f22d | 214 | int |
2a451106 | 215 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 216 | { |
c5aa993b | 217 | CORE_ADDR sp = read_sp (); |
c906108c | 218 | |
dfcd3bfb JM |
219 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
220 | is the best we can do. We are trying to determine if the pc is on | |
221 | the stack, which (hopefully) will only happen in a call dummy. | |
222 | We hope the current stack pointer is not so far alway from the dummy | |
223 | frame location (true if we have not pushed large data structures or | |
224 | gone too many levels deep) and that our 1024 is not enough to consider | |
94c30b78 | 225 | code regions as part of the stack (true for most practical purposes). */ |
ae45cd16 | 226 | if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) |
c906108c SS |
227 | return caller_is_thumb; |
228 | else | |
229 | return 0; | |
230 | } | |
231 | ||
181c1381 | 232 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 233 | static CORE_ADDR |
ed9a39eb | 234 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 235 | { |
a3a2ee65 JT |
236 | if (arm_apcs_32) |
237 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 238 | else |
a3a2ee65 | 239 | return (val & 0x03fffffc); |
c906108c SS |
240 | } |
241 | ||
181c1381 RE |
242 | /* When reading symbols, we need to zap the low bit of the address, |
243 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 244 | static CORE_ADDR |
181c1381 RE |
245 | arm_smash_text_address (CORE_ADDR val) |
246 | { | |
247 | return val & ~1; | |
248 | } | |
249 | ||
34e8f22d RE |
250 | /* Immediately after a function call, return the saved pc. Can't |
251 | always go through the frames for this because on some machines the | |
252 | new frame is not set up until the new function executes some | |
253 | instructions. */ | |
254 | ||
255 | static CORE_ADDR | |
ed9a39eb | 256 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 257 | { |
34e8f22d | 258 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
259 | } |
260 | ||
0defa245 RE |
261 | /* Determine whether the function invocation represented by FI has a |
262 | frame on the stack associated with it. If it does return zero, | |
263 | otherwise return 1. */ | |
264 | ||
148754e5 | 265 | static int |
ed9a39eb | 266 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 267 | { |
392a587b | 268 | CORE_ADDR func_start, after_prologue; |
96baa820 | 269 | int frameless; |
ed9a39eb | 270 | |
0defa245 RE |
271 | /* Sometimes we have functions that do a little setup (like saving the |
272 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
273 | The symbol table will report this as a prologue. However, it is | |
274 | important not to try to parse these partial frames as frames, or we | |
275 | will get really confused. | |
276 | ||
277 | So I will demand 3 instructions between the start & end of the | |
278 | prologue before I call it a real prologue, i.e. at least | |
279 | mov ip, sp, | |
280 | stmdb sp!, {} | |
281 | sub sp, ip, #4. */ | |
282 | ||
50abf9e5 | 283 | func_start = (get_pc_function_start (get_frame_pc (fi)) + FUNCTION_START_OFFSET); |
7be570e7 | 284 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 285 | |
96baa820 | 286 | /* There are some frameless functions whose first two instructions |
ed9a39eb | 287 | follow the standard APCS form, in which case after_prologue will |
94c30b78 | 288 | be func_start + 8. */ |
ed9a39eb | 289 | |
96baa820 | 290 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
291 | return frameless; |
292 | } | |
293 | ||
0defa245 | 294 | /* The address of the arguments in the frame. */ |
148754e5 | 295 | static CORE_ADDR |
0defa245 RE |
296 | arm_frame_args_address (struct frame_info *fi) |
297 | { | |
1e2330ba | 298 | return get_frame_base (fi); |
0defa245 RE |
299 | } |
300 | ||
301 | /* The address of the local variables in the frame. */ | |
148754e5 | 302 | static CORE_ADDR |
0defa245 RE |
303 | arm_frame_locals_address (struct frame_info *fi) |
304 | { | |
1e2330ba | 305 | return get_frame_base (fi); |
0defa245 RE |
306 | } |
307 | ||
308 | /* The number of arguments being passed in the frame. */ | |
148754e5 | 309 | static int |
0defa245 RE |
310 | arm_frame_num_args (struct frame_info *fi) |
311 | { | |
312 | /* We have no way of knowing. */ | |
313 | return -1; | |
314 | } | |
315 | ||
c906108c | 316 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
317 | push {r7, lr} |
318 | add sp, sp, #-28 | |
319 | add r7, sp, #12 | |
c906108c | 320 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
321 | mov r7, sp |
322 | ||
323 | or like this: | |
324 | push {r7, lr} | |
325 | mov r7, sp | |
326 | sub sp, #12 | |
327 | ||
328 | or, on tpcs, like this: | |
329 | sub sp,#16 | |
330 | push {r7, lr} | |
331 | (many instructions) | |
332 | mov r7, sp | |
333 | sub sp, #12 | |
334 | ||
335 | There is always one instruction of three classes: | |
336 | 1 - push | |
337 | 2 - setting of r7 | |
338 | 3 - adjusting of sp | |
339 | ||
340 | When we have found at least one of each class we are done with the prolog. | |
341 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 342 | */ |
c906108c SS |
343 | |
344 | static CORE_ADDR | |
c7885828 | 345 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
346 | { |
347 | CORE_ADDR current_pc; | |
da3c6d4a MS |
348 | /* findmask: |
349 | bit 0 - push { rlist } | |
350 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
351 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
352 | */ | |
353 | int findmask = 0; | |
354 | ||
94c30b78 MS |
355 | for (current_pc = pc; |
356 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 357 | current_pc += 2) |
c906108c SS |
358 | { |
359 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
360 | ||
94c30b78 | 361 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 362 | { |
94c30b78 | 363 | findmask |= 1; /* push found */ |
da59e081 | 364 | } |
da3c6d4a MS |
365 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
366 | sub sp, #simm */ | |
da59e081 | 367 | { |
94c30b78 | 368 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
369 | continue; |
370 | else | |
94c30b78 | 371 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
372 | } |
373 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
374 | { | |
94c30b78 | 375 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
376 | } |
377 | else if (insn == 0x466f) /* mov r7, sp */ | |
378 | { | |
94c30b78 | 379 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 380 | } |
3d74b771 FF |
381 | else if (findmask == (4+2+1)) |
382 | { | |
da3c6d4a MS |
383 | /* We have found one of each type of prologue instruction */ |
384 | break; | |
3d74b771 | 385 | } |
da59e081 | 386 | else |
94c30b78 | 387 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 388 | instruction from outside the prolog scheduled here for |
94c30b78 | 389 | optimization. */ |
da3c6d4a | 390 | continue; |
c906108c SS |
391 | } |
392 | ||
393 | return current_pc; | |
394 | } | |
395 | ||
da3c6d4a MS |
396 | /* Advance the PC across any function entry prologue instructions to |
397 | reach some "real" code. | |
34e8f22d RE |
398 | |
399 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 400 | prologue: |
c906108c | 401 | |
c5aa993b JM |
402 | mov ip, sp |
403 | [stmfd sp!, {a1,a2,a3,a4}] | |
404 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
405 | [stfe f7, [sp, #-12]!] |
406 | [stfe f6, [sp, #-12]!] | |
407 | [stfe f5, [sp, #-12]!] | |
408 | [stfe f4, [sp, #-12]!] | |
409 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 410 | |
34e8f22d | 411 | static CORE_ADDR |
ed9a39eb | 412 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
413 | { |
414 | unsigned long inst; | |
415 | CORE_ADDR skip_pc; | |
b8d5e71d | 416 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 417 | char *func_name; |
c906108c SS |
418 | struct symtab_and_line sal; |
419 | ||
848cfffb | 420 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
ae45cd16 | 421 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
848cfffb AC |
422 | return pc; |
423 | ||
96baa820 | 424 | /* See what the symbol table says. */ |
ed9a39eb | 425 | |
50f6fb4b | 426 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 427 | { |
50f6fb4b CV |
428 | struct symbol *sym; |
429 | ||
430 | /* Found a function. */ | |
431 | sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL); | |
432 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
433 | { | |
94c30b78 | 434 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
435 | sal = find_pc_line (func_addr, 0); |
436 | if ((sal.line != 0) && (sal.end < func_end)) | |
437 | return sal.end; | |
438 | } | |
c906108c SS |
439 | } |
440 | ||
441 | /* Check if this is Thumb code. */ | |
442 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 443 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
444 | |
445 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 446 | by disassembling the instructions. */ |
c906108c | 447 | |
b8d5e71d MS |
448 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
449 | if (func_end == 0 || func_end > pc + 64) | |
450 | func_end = pc + 64; | |
c906108c | 451 | |
b8d5e71d | 452 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 453 | { |
f43845b3 | 454 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 455 | |
b8d5e71d MS |
456 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
457 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
458 | continue; | |
c906108c | 459 | |
b8d5e71d MS |
460 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
461 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
462 | continue; | |
c906108c | 463 | |
b8d5e71d MS |
464 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
465 | continue; | |
c906108c | 466 | |
b8d5e71d MS |
467 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
468 | continue; | |
11d3b27d | 469 | |
b8d5e71d MS |
470 | /* Any insns after this point may float into the code, if it makes |
471 | for better instruction scheduling, so we skip them only if we | |
472 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 473 | |
b8d5e71d MS |
474 | /* We may have either one sfmfd instruction here, or several stfe |
475 | insns, depending on the version of floating point code we | |
476 | support. */ | |
477 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
478 | continue; | |
479 | ||
480 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
481 | continue; | |
482 | ||
483 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
484 | continue; | |
485 | ||
486 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
487 | continue; | |
488 | ||
489 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
490 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
491 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
492 | continue; | |
493 | ||
494 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
495 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
496 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
497 | continue; | |
498 | ||
499 | /* Un-recognized instruction; stop scanning. */ | |
500 | break; | |
f43845b3 | 501 | } |
c906108c | 502 | |
b8d5e71d | 503 | return skip_pc; /* End of prologue */ |
c906108c | 504 | } |
94c30b78 | 505 | |
c5aa993b | 506 | /* *INDENT-OFF* */ |
c906108c SS |
507 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
508 | This function decodes a Thumb function prologue to determine: | |
509 | 1) the size of the stack frame | |
510 | 2) which registers are saved on it | |
511 | 3) the offsets of saved regs | |
512 | 4) the offset from the stack pointer to the frame pointer | |
513 | This information is stored in the "extra" fields of the frame_info. | |
514 | ||
da59e081 JM |
515 | A typical Thumb function prologue would create this stack frame |
516 | (offsets relative to FP) | |
c906108c SS |
517 | old SP -> 24 stack parameters |
518 | 20 LR | |
519 | 16 R7 | |
520 | R7 -> 0 local variables (16 bytes) | |
521 | SP -> -12 additional stack space (12 bytes) | |
522 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
523 | 12 bytes. The frame register is R7. |
524 | ||
da3c6d4a MS |
525 | The comments for thumb_skip_prolog() describe the algorithm we use |
526 | to detect the end of the prolog. */ | |
c5aa993b JM |
527 | /* *INDENT-ON* */ |
528 | ||
c906108c | 529 | static void |
ed9a39eb | 530 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
531 | { |
532 | CORE_ADDR prologue_start; | |
533 | CORE_ADDR prologue_end; | |
534 | CORE_ADDR current_pc; | |
94c30b78 | 535 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
536 | int saved_reg[16]; |
537 | /* findmask: | |
538 | bit 0 - push { rlist } | |
539 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
540 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
541 | */ | |
542 | int findmask = 0; | |
c5aa993b | 543 | int i; |
c906108c | 544 | |
848cfffb | 545 | /* Don't try to scan dummy frames. */ |
07555a72 | 546 | if (fi != NULL |
50abf9e5 | 547 | && DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
848cfffb AC |
548 | return; |
549 | ||
50abf9e5 | 550 | if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end)) |
c906108c SS |
551 | { |
552 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
553 | ||
94c30b78 | 554 | if (sal.line == 0) /* no line info, use current PC */ |
50abf9e5 | 555 | prologue_end = get_frame_pc (fi); |
c906108c | 556 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 557 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
558 | } |
559 | else | |
da3c6d4a MS |
560 | /* We're in the boondocks: allow for |
561 | 16 pushes, an add, and "mv fp,sp". */ | |
562 | prologue_end = prologue_start + 40; | |
c906108c | 563 | |
50abf9e5 | 564 | prologue_end = min (prologue_end, get_frame_pc (fi)); |
c906108c SS |
565 | |
566 | /* Initialize the saved register map. When register H is copied to | |
567 | register L, we will put H in saved_reg[L]. */ | |
568 | for (i = 0; i < 16; i++) | |
569 | saved_reg[i] = i; | |
570 | ||
571 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
572 | frame pointer, adjust the stack pointer, and save registers. |
573 | Do this until all basic prolog instructions are found. */ | |
c906108c | 574 | |
da50a4b7 | 575 | get_frame_extra_info (fi)->framesize = 0; |
da59e081 JM |
576 | for (current_pc = prologue_start; |
577 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
578 | current_pc += 2) | |
c906108c SS |
579 | { |
580 | unsigned short insn; | |
581 | int regno; | |
582 | int offset; | |
583 | ||
584 | insn = read_memory_unsigned_integer (current_pc, 2); | |
585 | ||
c5aa993b | 586 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 587 | { |
da59e081 | 588 | int mask; |
94c30b78 | 589 | findmask |= 1; /* push found */ |
c906108c SS |
590 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
591 | whether to save LR (R14). */ | |
da59e081 | 592 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 593 | |
b8d5e71d | 594 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 595 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 596 | if (mask & (1 << regno)) |
c5aa993b | 597 | { |
da50a4b7 | 598 | get_frame_extra_info (fi)->framesize += 4; |
b2fb4676 | 599 | get_frame_saved_regs (fi)[saved_reg[regno]] = |
da50a4b7 | 600 | -(get_frame_extra_info (fi)->framesize); |
da3c6d4a MS |
601 | /* Reset saved register map. */ |
602 | saved_reg[regno] = regno; | |
c906108c SS |
603 | } |
604 | } | |
da3c6d4a MS |
605 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
606 | sub sp, #simm */ | |
c906108c | 607 | { |
b8d5e71d | 608 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
609 | continue; |
610 | else | |
94c30b78 | 611 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 612 | |
94c30b78 MS |
613 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
614 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 615 | { |
da50a4b7 | 616 | get_frame_extra_info (fi)->frameoffset += offset; |
da59e081 JM |
617 | offset = -offset; |
618 | } | |
da50a4b7 | 619 | get_frame_extra_info (fi)->framesize -= offset; |
c906108c SS |
620 | } |
621 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
622 | { | |
94c30b78 | 623 | findmask |= 2; /* setting of r7 found */ |
da50a4b7 | 624 | get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM; |
c3b4394c | 625 | /* get scaled offset */ |
da50a4b7 | 626 | get_frame_extra_info (fi)->frameoffset = (insn & 0xff) << 2; |
c906108c | 627 | } |
da59e081 | 628 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 629 | { |
94c30b78 | 630 | findmask |= 2; /* setting of r7 found */ |
da50a4b7 AC |
631 | get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM; |
632 | get_frame_extra_info (fi)->frameoffset = 0; | |
34e8f22d | 633 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
634 | } |
635 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
636 | { | |
da3c6d4a | 637 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 638 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 639 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
640 | } |
641 | else | |
da3c6d4a MS |
642 | /* Something in the prolog that we don't care about or some |
643 | instruction from outside the prolog scheduled here for | |
644 | optimization. */ | |
645 | continue; | |
c906108c SS |
646 | } |
647 | } | |
648 | ||
ed9a39eb | 649 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
650 | 1) the size of the stack frame |
651 | 2) which registers are saved on it | |
652 | 3) the offsets of saved regs | |
653 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
654 | This information is stored in the "extra" fields of the frame_info. |
655 | ||
96baa820 JM |
656 | There are two basic forms for the ARM prologue. The fixed argument |
657 | function call will look like: | |
ed9a39eb JM |
658 | |
659 | mov ip, sp | |
660 | stmfd sp!, {fp, ip, lr, pc} | |
661 | sub fp, ip, #4 | |
662 | [sub sp, sp, #4] | |
96baa820 | 663 | |
c906108c | 664 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
665 | IP -> 4 (caller's stack) |
666 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
667 | -4 LR (return address in caller) | |
668 | -8 IP (copy of caller's SP) | |
669 | -12 FP (caller's FP) | |
670 | SP -> -28 Local variables | |
671 | ||
c906108c | 672 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
673 | 28 bytes. The stmfd call can also save any of the vN registers it |
674 | plans to use, which increases the frame size accordingly. | |
675 | ||
676 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
677 | because the ARM Store instructions always store PC + 8 when you read | |
678 | the PC register. | |
ed9a39eb | 679 | |
96baa820 JM |
680 | A variable argument function call will look like: |
681 | ||
ed9a39eb JM |
682 | mov ip, sp |
683 | stmfd sp!, {a1, a2, a3, a4} | |
684 | stmfd sp!, {fp, ip, lr, pc} | |
685 | sub fp, ip, #20 | |
686 | ||
96baa820 | 687 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
688 | IP -> 20 (caller's stack) |
689 | 16 A4 | |
690 | 12 A3 | |
691 | 8 A2 | |
692 | 4 A1 | |
693 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
694 | -4 LR (return address in caller) | |
695 | -8 IP (copy of caller's SP) | |
696 | -12 FP (caller's FP) | |
697 | SP -> -28 Local variables | |
96baa820 JM |
698 | |
699 | The frame size would thus be 48 bytes, and the frame offset would be | |
700 | 28 bytes. | |
701 | ||
702 | There is another potential complication, which is that the optimizer | |
703 | will try to separate the store of fp in the "stmfd" instruction from | |
704 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
705 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
706 | ||
707 | Also, note, the original version of the ARM toolchain claimed that there | |
708 | should be an | |
709 | ||
710 | instruction at the end of the prologue. I have never seen GCC produce | |
711 | this, and the ARM docs don't mention it. We still test for it below in | |
712 | case it happens... | |
ed9a39eb JM |
713 | |
714 | */ | |
c906108c SS |
715 | |
716 | static void | |
ed9a39eb | 717 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
718 | { |
719 | int regno, sp_offset, fp_offset; | |
16a0f3e7 | 720 | LONGEST return_value; |
c906108c SS |
721 | CORE_ADDR prologue_start, prologue_end, current_pc; |
722 | ||
c906108c | 723 | /* Assume there is no frame until proven otherwise. */ |
da50a4b7 AC |
724 | get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM; |
725 | get_frame_extra_info (fi)->framesize = 0; | |
726 | get_frame_extra_info (fi)->frameoffset = 0; | |
c906108c SS |
727 | |
728 | /* Check for Thumb prologue. */ | |
50abf9e5 | 729 | if (arm_pc_is_thumb (get_frame_pc (fi))) |
c906108c SS |
730 | { |
731 | thumb_scan_prologue (fi); | |
c906108c SS |
732 | return; |
733 | } | |
734 | ||
735 | /* Find the function prologue. If we can't find the function in | |
736 | the symbol table, peek in the stack frame to find the PC. */ | |
50abf9e5 | 737 | if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end)) |
c906108c | 738 | { |
2a451106 KB |
739 | /* One way to find the end of the prologue (which works well |
740 | for unoptimized code) is to do the following: | |
741 | ||
742 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
743 | ||
744 | if (sal.line == 0) | |
50abf9e5 | 745 | prologue_end = get_frame_pc (fi); |
2a451106 KB |
746 | else if (sal.end < prologue_end) |
747 | prologue_end = sal.end; | |
748 | ||
749 | This mechanism is very accurate so long as the optimizer | |
750 | doesn't move any instructions from the function body into the | |
751 | prologue. If this happens, sal.end will be the last | |
752 | instruction in the first hunk of prologue code just before | |
753 | the first instruction that the scheduler has moved from | |
754 | the body to the prologue. | |
755 | ||
756 | In order to make sure that we scan all of the prologue | |
757 | instructions, we use a slightly less accurate mechanism which | |
758 | may scan more than necessary. To help compensate for this | |
759 | lack of accuracy, the prologue scanning loop below contains | |
760 | several clauses which'll cause the loop to terminate early if | |
761 | an implausible prologue instruction is encountered. | |
762 | ||
763 | The expression | |
764 | ||
765 | prologue_start + 64 | |
766 | ||
767 | is a suitable endpoint since it accounts for the largest | |
768 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 769 | the scheduler. */ |
2a451106 KB |
770 | |
771 | if (prologue_end > prologue_start + 64) | |
772 | { | |
94c30b78 | 773 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 774 | } |
c906108c SS |
775 | } |
776 | else | |
777 | { | |
94c30b78 MS |
778 | /* Get address of the stmfd in the prologue of the callee; |
779 | the saved PC is the address of the stmfd + 8. */ | |
1e2330ba | 780 | if (!safe_read_memory_integer (get_frame_base (fi), 4, &return_value)) |
16a0f3e7 EZ |
781 | return; |
782 | else | |
783 | { | |
784 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 785 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 786 | } |
c906108c SS |
787 | } |
788 | ||
789 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 790 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 791 | |
96baa820 JM |
792 | Be careful, however, and if it doesn't look like a prologue, |
793 | don't try to scan it. If, for instance, a frameless function | |
794 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 795 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
796 | and other operations that rely on a knowledge of the stack |
797 | traceback. | |
798 | ||
799 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 800 | if we don't see this as the first insn, we will stop. |
c906108c | 801 | |
f43845b3 MS |
802 | [Note: This doesn't seem to be true any longer, so it's now an |
803 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 804 | |
f43845b3 MS |
805 | [Note further: The "mov ip,sp" only seems to be missing in |
806 | frameless functions at optimization level "-O2" or above, | |
807 | in which case it is often (but not always) replaced by | |
b8d5e71d | 808 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 809 | |
f43845b3 MS |
810 | sp_offset = fp_offset = 0; |
811 | ||
94c30b78 MS |
812 | for (current_pc = prologue_start; |
813 | current_pc < prologue_end; | |
f43845b3 | 814 | current_pc += 4) |
96baa820 | 815 | { |
d4473757 KB |
816 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
817 | ||
94c30b78 | 818 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 MS |
819 | { |
820 | continue; | |
821 | } | |
94c30b78 | 822 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 MS |
823 | { |
824 | /* Function is frameless: extra_info defaults OK? */ | |
825 | continue; | |
826 | } | |
827 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
828 | /* stmfd sp!, {..., fp, ip, lr, pc} |
829 | or | |
830 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 831 | { |
d4473757 | 832 | int mask = insn & 0xffff; |
ed9a39eb | 833 | |
94c30b78 | 834 | /* Calculate offsets of saved registers. */ |
34e8f22d | 835 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
836 | if (mask & (1 << regno)) |
837 | { | |
838 | sp_offset -= 4; | |
b2fb4676 | 839 | get_frame_saved_regs (fi)[regno] = sp_offset; |
d4473757 KB |
840 | } |
841 | } | |
b8d5e71d MS |
842 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
843 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
844 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
845 | { | |
846 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
847 | continue; | |
848 | } | |
849 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
850 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
851 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
852 | { |
853 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
854 | continue; | |
855 | } | |
d4473757 KB |
856 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
857 | { | |
94c30b78 MS |
858 | unsigned imm = insn & 0xff; /* immediate value */ |
859 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
860 | imm = (imm >> rot) | (imm << (32 - rot)); |
861 | fp_offset = -imm; | |
da50a4b7 | 862 | get_frame_extra_info (fi)->framereg = ARM_FP_REGNUM; |
d4473757 KB |
863 | } |
864 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
865 | { | |
94c30b78 MS |
866 | unsigned imm = insn & 0xff; /* immediate value */ |
867 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
868 | imm = (imm >> rot) | (imm << (32 - rot)); |
869 | sp_offset -= imm; | |
870 | } | |
871 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
872 | { | |
873 | sp_offset -= 12; | |
34e8f22d | 874 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
b2fb4676 | 875 | get_frame_saved_regs (fi)[regno] = sp_offset; |
d4473757 KB |
876 | } |
877 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
878 | { | |
879 | int n_saved_fp_regs; | |
880 | unsigned int fp_start_reg, fp_bound_reg; | |
881 | ||
94c30b78 | 882 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 883 | { |
d4473757 KB |
884 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
885 | n_saved_fp_regs = 3; | |
886 | else | |
887 | n_saved_fp_regs = 1; | |
96baa820 | 888 | } |
d4473757 | 889 | else |
96baa820 | 890 | { |
d4473757 KB |
891 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
892 | n_saved_fp_regs = 2; | |
893 | else | |
894 | n_saved_fp_regs = 4; | |
96baa820 | 895 | } |
d4473757 | 896 | |
34e8f22d | 897 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
898 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
899 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
900 | { |
901 | sp_offset -= 12; | |
b2fb4676 | 902 | get_frame_saved_regs (fi)[fp_start_reg++] = sp_offset; |
96baa820 | 903 | } |
c906108c | 904 | } |
d4473757 | 905 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 906 | break; /* Condition not true, exit early */ |
b8d5e71d | 907 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 908 | break; /* Don't scan past a block load */ |
d4473757 KB |
909 | else |
910 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 911 | so we just skip what we don't recognize. */ |
d4473757 | 912 | continue; |
c906108c SS |
913 | } |
914 | ||
94c30b78 MS |
915 | /* The frame size is just the negative of the offset (from the |
916 | original SP) of the last thing thing we pushed on the stack. | |
917 | The frame offset is [new FP] - [new SP]. */ | |
da50a4b7 AC |
918 | get_frame_extra_info (fi)->framesize = -sp_offset; |
919 | if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM) | |
920 | get_frame_extra_info (fi)->frameoffset = fp_offset - sp_offset; | |
d4473757 | 921 | else |
da50a4b7 | 922 | get_frame_extra_info (fi)->frameoffset = 0; |
c906108c SS |
923 | } |
924 | ||
ed9a39eb JM |
925 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
926 | One thing we might want to do here is to check REGNUM against the | |
927 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
928 | the stack somewhere. This would provide a graceful failure mode | |
929 | when trying to get the value of caller-saves registers for an inner | |
930 | frame. */ | |
c906108c SS |
931 | |
932 | static CORE_ADDR | |
ed9a39eb | 933 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 934 | { |
848cfffb AC |
935 | /* NOTE: cagney/2002-05-03: This function really shouldn't be |
936 | needed. Instead the (still being written) register unwind | |
937 | function could be called directly. */ | |
11c02a10 | 938 | for (; fi; fi = get_next_frame (fi)) |
848cfffb | 939 | { |
50abf9e5 | 940 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
848cfffb | 941 | { |
1e2330ba AC |
942 | return deprecated_read_register_dummy (get_frame_pc (fi), |
943 | get_frame_base (fi), regnum); | |
848cfffb | 944 | } |
b2fb4676 | 945 | else if (get_frame_saved_regs (fi)[regnum] != 0) |
848cfffb AC |
946 | { |
947 | /* NOTE: cagney/2002-05-03: This would normally need to | |
948 | handle ARM_SP_REGNUM as a special case as, according to | |
949 | the frame.h comments, saved_regs[SP_REGNUM] contains the | |
950 | SP value not its address. It appears that the ARM isn't | |
951 | doing this though. */ | |
b2fb4676 | 952 | return read_memory_integer (get_frame_saved_regs (fi)[regnum], |
848cfffb AC |
953 | REGISTER_RAW_SIZE (regnum)); |
954 | } | |
955 | } | |
c906108c SS |
956 | return read_register (regnum); |
957 | } | |
148754e5 RE |
958 | /* Function: frame_chain Given a GDB frame, determine the address of |
959 | the calling function's frame. This will be used to create a new | |
e9582e71 | 960 | GDB frame struct, and then DEPRECATED_INIT_EXTRA_FRAME_INFO and |
a5afb99f AC |
961 | DEPRECATED_INIT_FRAME_PC will be called for the new frame. For |
962 | ARM, we save the frame size when we initialize the frame_info. */ | |
c5aa993b | 963 | |
148754e5 | 964 | static CORE_ADDR |
ed9a39eb | 965 | arm_frame_chain (struct frame_info *fi) |
c906108c | 966 | { |
848cfffb | 967 | CORE_ADDR caller_pc; |
da50a4b7 | 968 | int framereg = get_frame_extra_info (fi)->framereg; |
c906108c | 969 | |
50abf9e5 | 970 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
848cfffb | 971 | /* A generic call dummy's frame is the same as caller's. */ |
1e2330ba | 972 | return get_frame_base (fi); |
848cfffb | 973 | |
50abf9e5 | 974 | if (get_frame_pc (fi) < LOWEST_PC) |
c906108c SS |
975 | return 0; |
976 | ||
977 | /* If the caller is the startup code, we're at the end of the chain. */ | |
8bedc050 | 978 | caller_pc = DEPRECATED_FRAME_SAVED_PC (fi); |
c906108c SS |
979 | |
980 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
981 | the frame register of the caller is different from ours. | |
982 | So we must scan the prologue of the caller to determine its | |
94c30b78 | 983 | frame register number. */ |
c3b4394c RE |
984 | /* XXX Fixme, we should try to do this without creating a temporary |
985 | caller_fi. */ | |
50abf9e5 | 986 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (get_frame_pc (fi))) |
c906108c | 987 | { |
f6c609c4 AC |
988 | struct cleanup *old_chain = make_cleanup (null_cleanup, NULL); |
989 | struct frame_info *caller_fi = | |
990 | deprecated_frame_xmalloc_with_cleanup (SIZEOF_FRAME_SAVED_REGS, | |
991 | sizeof (struct frame_extra_info)); | |
c3b4394c RE |
992 | |
993 | /* Now, scan the prologue and obtain the frame register. */ | |
f6c609c4 AC |
994 | deprecated_update_frame_pc_hack (caller_fi, caller_pc); |
995 | arm_scan_prologue (caller_fi); | |
da50a4b7 | 996 | framereg = get_frame_extra_info (caller_fi)->framereg; |
c3b4394c RE |
997 | |
998 | /* Deallocate the storage associated with the temporary frame | |
999 | created above. */ | |
1000 | do_cleanups (old_chain); | |
c906108c SS |
1001 | } |
1002 | ||
1003 | /* If the caller used a frame register, return its value. | |
1004 | Otherwise, return the caller's stack pointer. */ | |
34e8f22d | 1005 | if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM) |
c906108c SS |
1006 | return arm_find_callers_reg (fi, framereg); |
1007 | else | |
da50a4b7 | 1008 | return get_frame_base (fi) + get_frame_extra_info (fi)->framesize; |
c906108c SS |
1009 | } |
1010 | ||
ed9a39eb JM |
1011 | /* This function actually figures out the frame address for a given pc |
1012 | and sp. This is tricky because we sometimes don't use an explicit | |
1013 | frame pointer, and the previous stack pointer isn't necessarily | |
1014 | recorded on the stack. The only reliable way to get this info is | |
1015 | to examine the prologue. FROMLEAF is a little confusing, it means | |
1016 | this is the next frame up the chain AFTER a frameless function. If | |
1017 | this is true, then the frame value for this frame is still in the | |
1018 | fp register. */ | |
c906108c | 1019 | |
148754e5 | 1020 | static void |
ed9a39eb | 1021 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1022 | { |
1023 | int reg; | |
f079148d | 1024 | CORE_ADDR sp; |
c906108c | 1025 | |
b2fb4676 | 1026 | if (get_frame_saved_regs (fi) == NULL) |
c3b4394c RE |
1027 | frame_saved_regs_zalloc (fi); |
1028 | ||
a00a19e9 | 1029 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
c3b4394c | 1030 | |
da50a4b7 AC |
1031 | get_frame_extra_info (fi)->framesize = 0; |
1032 | get_frame_extra_info (fi)->frameoffset = 0; | |
1033 | get_frame_extra_info (fi)->framereg = 0; | |
c3b4394c | 1034 | |
11c02a10 | 1035 | if (get_next_frame (fi)) |
8bedc050 | 1036 | deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi))); |
c906108c | 1037 | |
b2fb4676 | 1038 | memset (get_frame_saved_regs (fi), '\000', sizeof get_frame_saved_regs (fi)); |
c906108c | 1039 | |
da3c6d4a MS |
1040 | /* Compute stack pointer for this frame. We use this value for both |
1041 | the sigtramp and call dummy cases. */ | |
11c02a10 | 1042 | if (!get_next_frame (fi)) |
f079148d | 1043 | sp = read_sp(); |
11c02a10 | 1044 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
848cfffb AC |
1045 | /* For generic dummy frames, pull the value direct from the frame. |
1046 | Having an unwind function to do this would be nice. */ | |
11c02a10 AC |
1047 | sp = deprecated_read_register_dummy (get_frame_pc (get_next_frame (fi)), |
1048 | get_frame_base (get_next_frame (fi)), | |
135c175f | 1049 | ARM_SP_REGNUM); |
f079148d | 1050 | else |
da50a4b7 AC |
1051 | sp = (get_frame_base (get_next_frame (fi)) |
1052 | - get_frame_extra_info (get_next_frame (fi))->frameoffset | |
1053 | + get_frame_extra_info (get_next_frame (fi))->framesize); | |
f079148d | 1054 | |
d7bd68ca | 1055 | /* Determine whether or not we're in a sigtramp frame. |
5a203e44 AC |
1056 | Unfortunately, it isn't sufficient to test (get_frame_type (fi) |
1057 | == SIGTRAMP_FRAME) because this value is sometimes set after | |
e9582e71 | 1058 | invoking DEPRECATED_INIT_EXTRA_FRAME_INFO. So we test *both* |
5a203e44 AC |
1059 | (get_frame_type (fi) == SIGTRAMP_FRAME) and PC_IN_SIGTRAMP to |
1060 | determine if we need to use the sigcontext addresses for the | |
1061 | saved registers. | |
2a451106 | 1062 | |
d7bd68ca AC |
1063 | Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare |
1064 | against the name of the function, the code below will have to be | |
1065 | changed to first fetch the name of the function and then pass | |
1066 | this name to PC_IN_SIGTRAMP. */ | |
2a451106 | 1067 | |
5a203e44 AC |
1068 | /* FIXME: cagney/2002-11-18: This problem will go away once |
1069 | frame.c:get_prev_frame() is modified to set the frame's type | |
1070 | before calling functions like this. */ | |
1071 | ||
3bb04bdd | 1072 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
50abf9e5 | 1073 | && ((get_frame_type (fi) == SIGTRAMP_FRAME) || PC_IN_SIGTRAMP (get_frame_pc (fi), (char *)0))) |
2a451106 | 1074 | { |
2a451106 | 1075 | for (reg = 0; reg < NUM_REGS; reg++) |
b2fb4676 | 1076 | get_frame_saved_regs (fi)[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, get_frame_pc (fi), reg); |
2a451106 | 1077 | |
94c30b78 | 1078 | /* FIXME: What about thumb mode? */ |
da50a4b7 AC |
1079 | get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM; |
1080 | deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (fi)[get_frame_extra_info (fi)->framereg], REGISTER_RAW_SIZE (get_frame_extra_info (fi)->framereg))); | |
1081 | get_frame_extra_info (fi)->framesize = 0; | |
1082 | get_frame_extra_info (fi)->frameoffset = 0; | |
2a451106 KB |
1083 | |
1084 | } | |
1085 | else | |
c906108c SS |
1086 | { |
1087 | arm_scan_prologue (fi); | |
1088 | ||
11c02a10 | 1089 | if (!get_next_frame (fi)) |
94c30b78 | 1090 | /* This is the innermost frame? */ |
da50a4b7 | 1091 | deprecated_update_frame_base_hack (fi, read_register (get_frame_extra_info (fi)->framereg)); |
11c02a10 | 1092 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
848cfffb AC |
1093 | /* Next inner most frame is a dummy, just grab its frame. |
1094 | Dummy frames always have the same FP as their caller. */ | |
11c02a10 | 1095 | deprecated_update_frame_base_hack (fi, get_frame_base (get_next_frame (fi))); |
da50a4b7 AC |
1096 | else if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM |
1097 | || get_frame_extra_info (fi)->framereg == THUMB_FP_REGNUM) | |
ed9a39eb JM |
1098 | { |
1099 | /* not the innermost frame */ | |
94c30b78 | 1100 | /* If we have an FP, the callee saved it. */ |
da50a4b7 AC |
1101 | if (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg] != 0) |
1102 | deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg], 4)); | |
ed9a39eb JM |
1103 | else if (fromleaf) |
1104 | /* If we were called by a frameless fn. then our frame is | |
94c30b78 | 1105 | still in the frame pointer register on the board... */ |
b0c6b05c | 1106 | deprecated_update_frame_base_hack (fi, read_fp ()); |
ed9a39eb | 1107 | } |
c906108c | 1108 | |
ed9a39eb JM |
1109 | /* Calculate actual addresses of saved registers using offsets |
1110 | determined by arm_scan_prologue. */ | |
c906108c | 1111 | for (reg = 0; reg < NUM_REGS; reg++) |
b2fb4676 | 1112 | if (get_frame_saved_regs (fi)[reg] != 0) |
da50a4b7 AC |
1113 | get_frame_saved_regs (fi)[reg] |
1114 | += (get_frame_base (fi) | |
1115 | + get_frame_extra_info (fi)->framesize | |
1116 | - get_frame_extra_info (fi)->frameoffset); | |
c906108c SS |
1117 | } |
1118 | } | |
1119 | ||
1120 | ||
34e8f22d | 1121 | /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM |
ed9a39eb JM |
1122 | is saved in the stack anywhere, otherwise we get it from the |
1123 | registers. | |
c906108c SS |
1124 | |
1125 | The old definition of this function was a macro: | |
c5aa993b | 1126 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1127 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c | 1128 | |
148754e5 | 1129 | static CORE_ADDR |
ed9a39eb | 1130 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1131 | { |
848cfffb | 1132 | /* If a dummy frame, pull the PC out of the frame's register buffer. */ |
50abf9e5 | 1133 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
1e2330ba AC |
1134 | return deprecated_read_register_dummy (get_frame_pc (fi), |
1135 | get_frame_base (fi), ARM_PC_REGNUM); | |
848cfffb | 1136 | |
1e2330ba AC |
1137 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), |
1138 | (get_frame_base (fi) | |
da50a4b7 | 1139 | - get_frame_extra_info (fi)->frameoffset), |
1e2330ba | 1140 | get_frame_base (fi))) |
f079148d | 1141 | { |
b2fb4676 | 1142 | return read_memory_integer (get_frame_saved_regs (fi)[ARM_PC_REGNUM], |
34e8f22d | 1143 | REGISTER_RAW_SIZE (ARM_PC_REGNUM)); |
f079148d KB |
1144 | } |
1145 | else | |
c906108c | 1146 | { |
34e8f22d | 1147 | CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM); |
c906108c SS |
1148 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
1149 | } | |
1150 | } | |
1151 | ||
c906108c SS |
1152 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1153 | Examine the Program Status Register to decide which state we're in. */ | |
1154 | ||
148754e5 RE |
1155 | static CORE_ADDR |
1156 | arm_read_fp (void) | |
c906108c | 1157 | { |
34e8f22d | 1158 | if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ |
c906108c SS |
1159 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ |
1160 | else | |
34e8f22d | 1161 | return read_register (ARM_FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1162 | } |
1163 | ||
148754e5 RE |
1164 | /* Store into a struct frame_saved_regs the addresses of the saved |
1165 | registers of frame described by FRAME_INFO. This includes special | |
1166 | registers such as PC and FP saved in special ways in the stack | |
1167 | frame. SP is even more special: the address we return for it IS | |
1168 | the sp for the next frame. */ | |
c906108c | 1169 | |
148754e5 | 1170 | static void |
c3b4394c | 1171 | arm_frame_init_saved_regs (struct frame_info *fip) |
c906108c | 1172 | { |
c3b4394c | 1173 | |
b2fb4676 | 1174 | if (get_frame_saved_regs (fip)) |
c3b4394c RE |
1175 | return; |
1176 | ||
1177 | arm_init_extra_frame_info (0, fip); | |
c906108c SS |
1178 | } |
1179 | ||
848cfffb AC |
1180 | /* Set the return address for a generic dummy frame. ARM uses the |
1181 | entry point. */ | |
1182 | ||
1183 | static CORE_ADDR | |
1184 | arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1185 | { | |
1186 | write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ()); | |
1187 | return sp; | |
1188 | } | |
1189 | ||
148754e5 RE |
1190 | /* Push an empty stack frame, to record the current PC, etc. */ |
1191 | ||
1192 | static void | |
ed9a39eb | 1193 | arm_push_dummy_frame (void) |
c906108c | 1194 | { |
34e8f22d | 1195 | CORE_ADDR old_sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1196 | CORE_ADDR sp = old_sp; |
1197 | CORE_ADDR fp, prologue_start; | |
1198 | int regnum; | |
1199 | ||
1200 | /* Push the two dummy prologue instructions in reverse order, | |
1201 | so that they'll be in the correct low-to-high order in memory. */ | |
1202 | /* sub fp, ip, #4 */ | |
1203 | sp = push_word (sp, 0xe24cb004); | |
1204 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1205 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1206 | ||
ed9a39eb JM |
1207 | /* Push a pointer to the dummy prologue + 12, because when stm |
1208 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1209 | instruction itself plus 12. */ |
1210 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1211 | |
f079148d | 1212 | /* Push the processor status. */ |
34e8f22d | 1213 | sp = push_word (sp, read_register (ARM_PS_REGNUM)); |
f079148d KB |
1214 | |
1215 | /* Push all 16 registers starting with r15. */ | |
34e8f22d | 1216 | for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--) |
c906108c | 1217 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1218 | |
f079148d | 1219 | /* Update fp (for both Thumb and ARM) and sp. */ |
34e8f22d | 1220 | write_register (ARM_FP_REGNUM, fp); |
c906108c | 1221 | write_register (THUMB_FP_REGNUM, fp); |
34e8f22d | 1222 | write_register (ARM_SP_REGNUM, sp); |
c906108c SS |
1223 | } |
1224 | ||
6eb69eab RE |
1225 | /* CALL_DUMMY_WORDS: |
1226 | This sequence of words is the instructions | |
1227 | ||
1228 | mov lr,pc | |
1229 | mov pc,r4 | |
1230 | illegal | |
1231 | ||
1232 | Note this is 12 bytes. */ | |
1233 | ||
34e8f22d | 1234 | static LONGEST arm_call_dummy_words[] = |
6eb69eab RE |
1235 | { |
1236 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe | |
1237 | }; | |
1238 | ||
3fb4b924 RE |
1239 | /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy |
1240 | breakpoint to the proper address in the call dummy, so that | |
1241 | `finish' after a stop in a call dummy works. | |
1242 | ||
d7b486e7 RE |
1243 | FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an |
1244 | optimal solution, but the call to arm_fix_call_dummy is immediately | |
1245 | followed by a call to run_stack_dummy, which is the only function | |
1246 | where call_dummy_breakpoint_offset is actually used. */ | |
3fb4b924 RE |
1247 | |
1248 | ||
1249 | static void | |
1250 | arm_set_call_dummy_breakpoint_offset (void) | |
1251 | { | |
1252 | if (caller_is_thumb) | |
1253 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4); | |
1254 | else | |
1255 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8); | |
1256 | } | |
1257 | ||
c906108c | 1258 | /* Fix up the call dummy, based on whether the processor is currently |
ed9a39eb JM |
1259 | in Thumb or ARM mode, and whether the target function is Thumb or |
1260 | ARM. There are three different situations requiring three | |
c906108c SS |
1261 | different dummies: |
1262 | ||
1263 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1264 | been copied into the dummy parameter to this function. |
c906108c | 1265 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1266 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1267 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1268 | works for calling both ARM and Thumb functions. |
c906108c | 1269 | |
ed9a39eb JM |
1270 | All three call dummies expect to receive the target function |
1271 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c | 1272 | |
34e8f22d | 1273 | static void |
ed9a39eb | 1274 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1275 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1276 | { |
1277 | static short thumb_dummy[4] = | |
1278 | { | |
c5aa993b JM |
1279 | 0xf000, 0xf801, /* bl label */ |
1280 | 0xdf18, /* swi 24 */ | |
1281 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1282 | }; |
1283 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1284 | ||
94c30b78 | 1285 | /* Set flag indicating whether the current PC is in a Thumb function. */ |
c5aa993b | 1286 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
3fb4b924 | 1287 | arm_set_call_dummy_breakpoint_offset (); |
c906108c | 1288 | |
ed9a39eb JM |
1289 | /* If the target function is Thumb, set the low bit of the function |
1290 | address. And if the CPU is currently in ARM mode, patch the | |
1291 | second instruction of call dummy to use a BX instruction to | |
1292 | switch to Thumb mode. */ | |
c906108c SS |
1293 | target_is_thumb = arm_pc_is_thumb (fun); |
1294 | if (target_is_thumb) | |
1295 | { | |
1296 | fun |= 1; | |
1297 | if (!caller_is_thumb) | |
1298 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1299 | } | |
1300 | ||
1301 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1302 | instead of the ARM one that's already been copied. This will | |
1303 | work for both Thumb and ARM target functions. */ | |
1304 | if (caller_is_thumb) | |
1305 | { | |
1306 | int i; | |
1307 | char *p = dummy; | |
1308 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1309 | ||
1310 | for (i = 0; i < len; i++) | |
1311 | { | |
1312 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1313 | p += sizeof (thumb_dummy[0]); | |
1314 | } | |
1315 | } | |
1316 | ||
ed9a39eb | 1317 | /* Put the target address in r4; the call dummy will copy this to |
94c30b78 | 1318 | the PC. */ |
c906108c SS |
1319 | write_register (4, fun); |
1320 | } | |
1321 | ||
ed9a39eb JM |
1322 | /* Note: ScottB |
1323 | ||
1324 | This function does not support passing parameters using the FPA | |
1325 | variant of the APCS. It passes any floating point arguments in the | |
1326 | general registers and/or on the stack. */ | |
c906108c | 1327 | |
39bbf761 | 1328 | static CORE_ADDR |
ea7c478f | 1329 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
ed9a39eb | 1330 | int struct_return, CORE_ADDR struct_addr) |
c906108c | 1331 | { |
6529d2dd AC |
1332 | CORE_ADDR fp; |
1333 | int argnum; | |
1334 | int argreg; | |
1335 | int nstack; | |
1336 | int simd_argreg; | |
1337 | int second_pass; | |
1338 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
ed9a39eb JM |
1339 | |
1340 | /* Walk through the list of args and determine how large a temporary | |
1341 | stack is required. Need to take care here as structs may be | |
6529d2dd AC |
1342 | passed on the stack, and we have to to push them. On the second |
1343 | pass, do the store. */ | |
1344 | nstack = 0; | |
1345 | fp = sp; | |
1346 | for (second_pass = 0; second_pass < 2; second_pass++) | |
c906108c | 1347 | { |
6529d2dd AC |
1348 | /* Compute the FP using the information computed during the |
1349 | first pass. */ | |
1350 | if (second_pass) | |
1351 | fp = sp - nstack; | |
1352 | ||
1353 | simd_argreg = 0; | |
1354 | argreg = ARM_A1_REGNUM; | |
1355 | nstack = 0; | |
1356 | ||
1357 | /* The struct_return pointer occupies the first parameter | |
1358 | passing register. */ | |
1359 | if (struct_return) | |
c906108c | 1360 | { |
6529d2dd AC |
1361 | if (second_pass) |
1362 | { | |
1363 | if (arm_debug) | |
1364 | fprintf_unfiltered (gdb_stdlog, | |
1365 | "struct return in %s = 0x%s\n", | |
1366 | REGISTER_NAME (argreg), | |
1367 | paddr (struct_addr)); | |
1368 | write_register (argreg, struct_addr); | |
1369 | } | |
1370 | argreg++; | |
c906108c | 1371 | } |
ed9a39eb | 1372 | |
6529d2dd AC |
1373 | for (argnum = 0; argnum < nargs; argnum++) |
1374 | { | |
1375 | int len; | |
1376 | struct type *arg_type; | |
1377 | struct type *target_type; | |
1378 | enum type_code typecode; | |
1379 | char *val; | |
1380 | ||
1381 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1382 | len = TYPE_LENGTH (arg_type); | |
1383 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1384 | typecode = TYPE_CODE (arg_type); | |
1385 | val = VALUE_CONTENTS (args[argnum]); | |
1386 | ||
1387 | /* If the argument is a pointer to a function, and it is a | |
1388 | Thumb function, create a LOCAL copy of the value and set | |
1389 | the THUMB bit in it. */ | |
1390 | if (second_pass | |
1391 | && TYPE_CODE_PTR == typecode | |
1392 | && target_type != NULL | |
1393 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1394 | { |
6529d2dd AC |
1395 | CORE_ADDR regval = extract_address (val, len); |
1396 | if (arm_pc_is_thumb (regval)) | |
1397 | { | |
1398 | val = alloca (len); | |
1399 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1400 | } | |
c906108c | 1401 | } |
6529d2dd AC |
1402 | |
1403 | /* Copy the argument to general registers or the stack in | |
1404 | register-sized pieces. Large arguments are split between | |
1405 | registers and stack. */ | |
1406 | while (len > 0) | |
ed9a39eb | 1407 | { |
6529d2dd AC |
1408 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1409 | ||
1410 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1411 | { | |
1412 | /* The argument is being passed in a general purpose | |
1413 | register. */ | |
1414 | if (second_pass) | |
1415 | { | |
1416 | CORE_ADDR regval = extract_address (val, | |
1417 | partial_len); | |
1418 | if (arm_debug) | |
1419 | fprintf_unfiltered (gdb_stdlog, | |
1420 | "arg %d in %s = 0x%s\n", | |
1421 | argnum, | |
1422 | REGISTER_NAME (argreg), | |
1423 | phex (regval, REGISTER_SIZE)); | |
1424 | write_register (argreg, regval); | |
1425 | } | |
1426 | argreg++; | |
1427 | } | |
1428 | else | |
1429 | { | |
1430 | if (second_pass) | |
1431 | { | |
1432 | /* Push the arguments onto the stack. */ | |
1433 | if (arm_debug) | |
1434 | fprintf_unfiltered (gdb_stdlog, | |
1435 | "arg %d @ 0x%s + %d\n", | |
1436 | argnum, paddr (fp), nstack); | |
1437 | write_memory (fp + nstack, val, REGISTER_SIZE); | |
1438 | } | |
1439 | nstack += REGISTER_SIZE; | |
1440 | } | |
1441 | ||
1442 | len -= partial_len; | |
1443 | val += partial_len; | |
ed9a39eb JM |
1444 | } |
1445 | ||
c906108c SS |
1446 | } |
1447 | } | |
c906108c | 1448 | |
f211c6d4 | 1449 | /* Return the bottom of the argument list (pointed to by fp). */ |
6529d2dd | 1450 | return fp; |
c906108c SS |
1451 | } |
1452 | ||
da3c6d4a MS |
1453 | /* Pop the current frame. So long as the frame info has been |
1454 | initialized properly (see arm_init_extra_frame_info), this code | |
1455 | works for dummy frames as well as regular frames. I.e, there's no | |
1456 | need to have a special case for dummy frames. */ | |
148754e5 | 1457 | static void |
ed9a39eb | 1458 | arm_pop_frame (void) |
c906108c | 1459 | { |
c906108c | 1460 | int regnum; |
8b93c638 | 1461 | struct frame_info *frame = get_current_frame (); |
da50a4b7 AC |
1462 | CORE_ADDR old_SP = (get_frame_base (frame) |
1463 | - get_frame_extra_info (frame)->frameoffset | |
1464 | + get_frame_extra_info (frame)->framesize); | |
c906108c | 1465 | |
1e2330ba AC |
1466 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
1467 | get_frame_base (frame), | |
1468 | get_frame_base (frame))) | |
848cfffb AC |
1469 | { |
1470 | generic_pop_dummy_frame (); | |
1471 | flush_cached_frames (); | |
1472 | return; | |
1473 | } | |
1474 | ||
f079148d | 1475 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
b2fb4676 | 1476 | if (get_frame_saved_regs (frame)[regnum] != 0) |
f079148d | 1477 | write_register (regnum, |
b2fb4676 | 1478 | read_memory_integer (get_frame_saved_regs (frame)[regnum], |
f079148d | 1479 | REGISTER_RAW_SIZE (regnum))); |
8b93c638 | 1480 | |
8bedc050 | 1481 | write_register (ARM_PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
34e8f22d | 1482 | write_register (ARM_SP_REGNUM, old_SP); |
c906108c SS |
1483 | |
1484 | flush_cached_frames (); | |
1485 | } | |
1486 | ||
1487 | static void | |
ed9a39eb | 1488 | print_fpu_flags (int flags) |
c906108c | 1489 | { |
c5aa993b JM |
1490 | if (flags & (1 << 0)) |
1491 | fputs ("IVO ", stdout); | |
1492 | if (flags & (1 << 1)) | |
1493 | fputs ("DVZ ", stdout); | |
1494 | if (flags & (1 << 2)) | |
1495 | fputs ("OFL ", stdout); | |
1496 | if (flags & (1 << 3)) | |
1497 | fputs ("UFL ", stdout); | |
1498 | if (flags & (1 << 4)) | |
1499 | fputs ("INX ", stdout); | |
1500 | putchar ('\n'); | |
c906108c SS |
1501 | } |
1502 | ||
5e74b15c RE |
1503 | /* Print interesting information about the floating point processor |
1504 | (if present) or emulator. */ | |
34e8f22d | 1505 | static void |
d855c300 | 1506 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1507 | struct frame_info *frame, const char *args) |
c906108c | 1508 | { |
34e8f22d | 1509 | register unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1510 | int type; |
1511 | ||
1512 | type = (status >> 24) & 127; | |
1513 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1514 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1515 | type); |
1516 | fputs ("mask: ", stdout); | |
1517 | print_fpu_flags (status >> 16); | |
1518 | fputs ("flags: ", stdout); | |
1519 | print_fpu_flags (status); | |
c906108c SS |
1520 | } |
1521 | ||
34e8f22d RE |
1522 | /* Return the GDB type object for the "standard" data type of data in |
1523 | register N. */ | |
1524 | ||
1525 | static struct type * | |
032758dc AC |
1526 | arm_register_type (int regnum) |
1527 | { | |
34e8f22d | 1528 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1529 | { |
d7449b42 | 1530 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1531 | return builtin_type_arm_ext_big; |
1532 | else | |
1533 | return builtin_type_arm_ext_littlebyte_bigword; | |
1534 | } | |
1535 | else | |
1536 | return builtin_type_int32; | |
1537 | } | |
1538 | ||
34e8f22d RE |
1539 | /* Index within `registers' of the first byte of the space for |
1540 | register N. */ | |
1541 | ||
1542 | static int | |
1543 | arm_register_byte (int regnum) | |
1544 | { | |
1545 | if (regnum < ARM_F0_REGNUM) | |
1546 | return regnum * INT_REGISTER_RAW_SIZE; | |
1547 | else if (regnum < ARM_PS_REGNUM) | |
1548 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1549 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE); | |
1550 | else | |
1551 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1552 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
1553 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); | |
1554 | } | |
1555 | ||
1556 | /* Number of bytes of storage in the actual machine representation for | |
1557 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
1558 | 12 bytes in length. */ | |
1559 | ||
1560 | static int | |
1561 | arm_register_raw_size (int regnum) | |
1562 | { | |
1563 | if (regnum < ARM_F0_REGNUM) | |
1564 | return INT_REGISTER_RAW_SIZE; | |
1565 | else if (regnum < ARM_FPS_REGNUM) | |
1566 | return FP_REGISTER_RAW_SIZE; | |
1567 | else | |
1568 | return STATUS_REGISTER_SIZE; | |
1569 | } | |
1570 | ||
1571 | /* Number of bytes of storage in a program's representation | |
1572 | for register N. */ | |
1573 | static int | |
1574 | arm_register_virtual_size (int regnum) | |
1575 | { | |
1576 | if (regnum < ARM_F0_REGNUM) | |
1577 | return INT_REGISTER_VIRTUAL_SIZE; | |
1578 | else if (regnum < ARM_FPS_REGNUM) | |
1579 | return FP_REGISTER_VIRTUAL_SIZE; | |
1580 | else | |
1581 | return STATUS_REGISTER_SIZE; | |
1582 | } | |
1583 | ||
26216b98 AC |
1584 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1585 | static int | |
1586 | arm_register_sim_regno (int regnum) | |
1587 | { | |
1588 | int reg = regnum; | |
1589 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1590 | ||
1591 | if (reg < NUM_GREGS) | |
1592 | return SIM_ARM_R0_REGNUM + reg; | |
1593 | reg -= NUM_GREGS; | |
1594 | ||
1595 | if (reg < NUM_FREGS) | |
1596 | return SIM_ARM_FP0_REGNUM + reg; | |
1597 | reg -= NUM_FREGS; | |
1598 | ||
1599 | if (reg < NUM_SREGS) | |
1600 | return SIM_ARM_FPS_REGNUM + reg; | |
1601 | reg -= NUM_SREGS; | |
1602 | ||
1603 | internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum); | |
1604 | } | |
34e8f22d | 1605 | |
a37b3cc0 AC |
1606 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1607 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1608 | It is thought that this is is the floating-point register format on | |
1609 | little-endian systems. */ | |
c906108c | 1610 | |
ed9a39eb | 1611 | static void |
b508a996 RE |
1612 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1613 | void *dbl) | |
c906108c | 1614 | { |
a37b3cc0 | 1615 | DOUBLEST d; |
d7449b42 | 1616 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1617 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1618 | else | |
1619 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1620 | ptr, &d); | |
b508a996 | 1621 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1622 | } |
1623 | ||
34e8f22d | 1624 | static void |
b508a996 | 1625 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1626 | { |
a37b3cc0 | 1627 | DOUBLEST d; |
b508a996 | 1628 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1629 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1630 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1631 | else | |
1632 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1633 | &d, dbl); | |
c906108c | 1634 | } |
ed9a39eb | 1635 | |
c906108c | 1636 | static int |
ed9a39eb | 1637 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1638 | { |
1639 | if (cond == INST_AL || cond == INST_NV) | |
1640 | return 1; | |
1641 | ||
1642 | switch (cond) | |
1643 | { | |
1644 | case INST_EQ: | |
1645 | return ((status_reg & FLAG_Z) != 0); | |
1646 | case INST_NE: | |
1647 | return ((status_reg & FLAG_Z) == 0); | |
1648 | case INST_CS: | |
1649 | return ((status_reg & FLAG_C) != 0); | |
1650 | case INST_CC: | |
1651 | return ((status_reg & FLAG_C) == 0); | |
1652 | case INST_MI: | |
1653 | return ((status_reg & FLAG_N) != 0); | |
1654 | case INST_PL: | |
1655 | return ((status_reg & FLAG_N) == 0); | |
1656 | case INST_VS: | |
1657 | return ((status_reg & FLAG_V) != 0); | |
1658 | case INST_VC: | |
1659 | return ((status_reg & FLAG_V) == 0); | |
1660 | case INST_HI: | |
1661 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1662 | case INST_LS: | |
1663 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1664 | case INST_GE: | |
1665 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1666 | case INST_LT: | |
1667 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1668 | case INST_GT: | |
1669 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1670 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1671 | case INST_LE: |
1672 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1673 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1674 | } |
1675 | return 1; | |
1676 | } | |
1677 | ||
9512d7fd | 1678 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1679 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1680 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1681 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1682 | #define sbits(obj,st,fn) \ | |
1683 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1684 | #define BranchDest(addr,instr) \ | |
1685 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1686 | #define ARM_PC_32 1 | |
1687 | ||
1688 | static unsigned long | |
ed9a39eb JM |
1689 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1690 | unsigned long status_reg) | |
c906108c SS |
1691 | { |
1692 | unsigned long res, shift; | |
1693 | int rm = bits (inst, 0, 3); | |
1694 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1695 | |
1696 | if (bit (inst, 4)) | |
c906108c SS |
1697 | { |
1698 | int rs = bits (inst, 8, 11); | |
1699 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1700 | } | |
1701 | else | |
1702 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1703 | |
1704 | res = (rm == 15 | |
c906108c | 1705 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1706 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1707 | : read_register (rm)); |
1708 | ||
1709 | switch (shifttype) | |
1710 | { | |
c5aa993b | 1711 | case 0: /* LSL */ |
c906108c SS |
1712 | res = shift >= 32 ? 0 : res << shift; |
1713 | break; | |
c5aa993b JM |
1714 | |
1715 | case 1: /* LSR */ | |
c906108c SS |
1716 | res = shift >= 32 ? 0 : res >> shift; |
1717 | break; | |
1718 | ||
c5aa993b JM |
1719 | case 2: /* ASR */ |
1720 | if (shift >= 32) | |
1721 | shift = 31; | |
c906108c SS |
1722 | res = ((res & 0x80000000L) |
1723 | ? ~((~res) >> shift) : res >> shift); | |
1724 | break; | |
1725 | ||
c5aa993b | 1726 | case 3: /* ROR/RRX */ |
c906108c SS |
1727 | shift &= 31; |
1728 | if (shift == 0) | |
1729 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1730 | else | |
c5aa993b | 1731 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1732 | break; |
1733 | } | |
1734 | ||
1735 | return res & 0xffffffff; | |
1736 | } | |
1737 | ||
c906108c SS |
1738 | /* Return number of 1-bits in VAL. */ |
1739 | ||
1740 | static int | |
ed9a39eb | 1741 | bitcount (unsigned long val) |
c906108c SS |
1742 | { |
1743 | int nbits; | |
1744 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1745 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1746 | return nbits; |
1747 | } | |
1748 | ||
34e8f22d | 1749 | CORE_ADDR |
ed9a39eb | 1750 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1751 | { |
c5aa993b | 1752 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1753 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1754 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1755 | unsigned long offset; |
1756 | ||
1757 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1758 | { | |
1759 | CORE_ADDR sp; | |
1760 | ||
1761 | /* Fetch the saved PC from the stack. It's stored above | |
1762 | all of the other registers. */ | |
1763 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
34e8f22d | 1764 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1765 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1766 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1767 | if (nextpc == pc) | |
1768 | error ("Infinite loop detected"); | |
1769 | } | |
1770 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1771 | { | |
34e8f22d | 1772 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1773 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1774 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1775 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1776 | } | |
1777 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1778 | { | |
1779 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1780 | } | |
1781 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1782 | { | |
1783 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1784 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1785 | nextpc = pc_val + offset; |
1786 | } | |
1787 | ||
1788 | return nextpc; | |
1789 | } | |
1790 | ||
34e8f22d | 1791 | CORE_ADDR |
ed9a39eb | 1792 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1793 | { |
1794 | unsigned long pc_val; | |
1795 | unsigned long this_instr; | |
1796 | unsigned long status; | |
1797 | CORE_ADDR nextpc; | |
1798 | ||
1799 | if (arm_pc_is_thumb (pc)) | |
1800 | return thumb_get_next_pc (pc); | |
1801 | ||
1802 | pc_val = (unsigned long) pc; | |
1803 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1804 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1805 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1806 | |
1807 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1808 | { | |
1809 | switch (bits (this_instr, 24, 27)) | |
1810 | { | |
c5aa993b | 1811 | case 0x0: |
94c30b78 | 1812 | case 0x1: /* data processing */ |
c5aa993b JM |
1813 | case 0x2: |
1814 | case 0x3: | |
c906108c SS |
1815 | { |
1816 | unsigned long operand1, operand2, result = 0; | |
1817 | unsigned long rn; | |
1818 | int c; | |
c5aa993b | 1819 | |
c906108c SS |
1820 | if (bits (this_instr, 12, 15) != 15) |
1821 | break; | |
1822 | ||
1823 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1824 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1825 | error ("Illegal update to pc in instruction"); |
1826 | ||
1827 | /* Multiply into PC */ | |
1828 | c = (status & FLAG_C) ? 1 : 0; | |
1829 | rn = bits (this_instr, 16, 19); | |
1830 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1831 | |
c906108c SS |
1832 | if (bit (this_instr, 25)) |
1833 | { | |
1834 | unsigned long immval = bits (this_instr, 0, 7); | |
1835 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1836 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1837 | & 0xffffffff; | |
c906108c | 1838 | } |
c5aa993b | 1839 | else /* operand 2 is a shifted register */ |
c906108c | 1840 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1841 | |
c906108c SS |
1842 | switch (bits (this_instr, 21, 24)) |
1843 | { | |
c5aa993b | 1844 | case 0x0: /*and */ |
c906108c SS |
1845 | result = operand1 & operand2; |
1846 | break; | |
1847 | ||
c5aa993b | 1848 | case 0x1: /*eor */ |
c906108c SS |
1849 | result = operand1 ^ operand2; |
1850 | break; | |
1851 | ||
c5aa993b | 1852 | case 0x2: /*sub */ |
c906108c SS |
1853 | result = operand1 - operand2; |
1854 | break; | |
1855 | ||
c5aa993b | 1856 | case 0x3: /*rsb */ |
c906108c SS |
1857 | result = operand2 - operand1; |
1858 | break; | |
1859 | ||
c5aa993b | 1860 | case 0x4: /*add */ |
c906108c SS |
1861 | result = operand1 + operand2; |
1862 | break; | |
1863 | ||
c5aa993b | 1864 | case 0x5: /*adc */ |
c906108c SS |
1865 | result = operand1 + operand2 + c; |
1866 | break; | |
1867 | ||
c5aa993b | 1868 | case 0x6: /*sbc */ |
c906108c SS |
1869 | result = operand1 - operand2 + c; |
1870 | break; | |
1871 | ||
c5aa993b | 1872 | case 0x7: /*rsc */ |
c906108c SS |
1873 | result = operand2 - operand1 + c; |
1874 | break; | |
1875 | ||
c5aa993b JM |
1876 | case 0x8: |
1877 | case 0x9: | |
1878 | case 0xa: | |
1879 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1880 | result = (unsigned long) nextpc; |
1881 | break; | |
1882 | ||
c5aa993b | 1883 | case 0xc: /*orr */ |
c906108c SS |
1884 | result = operand1 | operand2; |
1885 | break; | |
1886 | ||
c5aa993b | 1887 | case 0xd: /*mov */ |
c906108c SS |
1888 | /* Always step into a function. */ |
1889 | result = operand2; | |
c5aa993b | 1890 | break; |
c906108c | 1891 | |
c5aa993b | 1892 | case 0xe: /*bic */ |
c906108c SS |
1893 | result = operand1 & ~operand2; |
1894 | break; | |
1895 | ||
c5aa993b | 1896 | case 0xf: /*mvn */ |
c906108c SS |
1897 | result = ~operand2; |
1898 | break; | |
1899 | } | |
1900 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1901 | ||
1902 | if (nextpc == pc) | |
1903 | error ("Infinite loop detected"); | |
1904 | break; | |
1905 | } | |
c5aa993b JM |
1906 | |
1907 | case 0x4: | |
1908 | case 0x5: /* data transfer */ | |
1909 | case 0x6: | |
1910 | case 0x7: | |
c906108c SS |
1911 | if (bit (this_instr, 20)) |
1912 | { | |
1913 | /* load */ | |
1914 | if (bits (this_instr, 12, 15) == 15) | |
1915 | { | |
1916 | /* rd == pc */ | |
c5aa993b | 1917 | unsigned long rn; |
c906108c | 1918 | unsigned long base; |
c5aa993b | 1919 | |
c906108c SS |
1920 | if (bit (this_instr, 22)) |
1921 | error ("Illegal update to pc in instruction"); | |
1922 | ||
1923 | /* byte write to PC */ | |
1924 | rn = bits (this_instr, 16, 19); | |
1925 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1926 | if (bit (this_instr, 24)) | |
1927 | { | |
1928 | /* pre-indexed */ | |
1929 | int c = (status & FLAG_C) ? 1 : 0; | |
1930 | unsigned long offset = | |
c5aa993b | 1931 | (bit (this_instr, 25) |
ed9a39eb | 1932 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1933 | : bits (this_instr, 0, 11)); |
c906108c SS |
1934 | |
1935 | if (bit (this_instr, 23)) | |
1936 | base += offset; | |
1937 | else | |
1938 | base -= offset; | |
1939 | } | |
c5aa993b | 1940 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1941 | 4); |
c5aa993b | 1942 | |
c906108c SS |
1943 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1944 | ||
1945 | if (nextpc == pc) | |
1946 | error ("Infinite loop detected"); | |
1947 | } | |
1948 | } | |
1949 | break; | |
c5aa993b JM |
1950 | |
1951 | case 0x8: | |
1952 | case 0x9: /* block transfer */ | |
c906108c SS |
1953 | if (bit (this_instr, 20)) |
1954 | { | |
1955 | /* LDM */ | |
1956 | if (bit (this_instr, 15)) | |
1957 | { | |
1958 | /* loading pc */ | |
1959 | int offset = 0; | |
1960 | ||
1961 | if (bit (this_instr, 23)) | |
1962 | { | |
1963 | /* up */ | |
1964 | unsigned long reglist = bits (this_instr, 0, 14); | |
1965 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1966 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1967 | offset += 4; |
1968 | } | |
1969 | else if (bit (this_instr, 24)) | |
1970 | offset = -4; | |
c5aa993b | 1971 | |
c906108c | 1972 | { |
c5aa993b JM |
1973 | unsigned long rn_val = |
1974 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1975 | nextpc = |
1976 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1977 | + offset), |
c906108c SS |
1978 | 4); |
1979 | } | |
1980 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1981 | if (nextpc == pc) | |
1982 | error ("Infinite loop detected"); | |
1983 | } | |
1984 | } | |
1985 | break; | |
c5aa993b JM |
1986 | |
1987 | case 0xb: /* branch & link */ | |
1988 | case 0xa: /* branch */ | |
c906108c SS |
1989 | { |
1990 | nextpc = BranchDest (pc, this_instr); | |
1991 | ||
1992 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1993 | if (nextpc == pc) | |
1994 | error ("Infinite loop detected"); | |
1995 | break; | |
1996 | } | |
c5aa993b JM |
1997 | |
1998 | case 0xc: | |
1999 | case 0xd: | |
2000 | case 0xe: /* coproc ops */ | |
2001 | case 0xf: /* SWI */ | |
c906108c SS |
2002 | break; |
2003 | ||
2004 | default: | |
97e03143 | 2005 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
2006 | return (pc); |
2007 | } | |
2008 | } | |
2009 | ||
2010 | return nextpc; | |
2011 | } | |
2012 | ||
9512d7fd FN |
2013 | /* single_step() is called just before we want to resume the inferior, |
2014 | if we want to single-step it but there is no hardware or kernel | |
2015 | single-step support. We find the target of the coming instruction | |
2016 | and breakpoint it. | |
2017 | ||
94c30b78 MS |
2018 | single_step() is also called just after the inferior stops. If we |
2019 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 2020 | |
34e8f22d RE |
2021 | static void |
2022 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 2023 | { |
b8d5e71d | 2024 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
2025 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
2026 | ||
2027 | if (insert_bpt) | |
2028 | { | |
34e8f22d | 2029 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 2030 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
2031 | } |
2032 | else | |
80fcf3f0 | 2033 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 2034 | } |
9512d7fd | 2035 | |
c906108c SS |
2036 | #include "bfd-in2.h" |
2037 | #include "libcoff.h" | |
2038 | ||
2039 | static int | |
ed9a39eb | 2040 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2041 | { |
2042 | if (arm_pc_is_thumb (memaddr)) | |
2043 | { | |
c5aa993b JM |
2044 | static asymbol *asym; |
2045 | static combined_entry_type ce; | |
2046 | static struct coff_symbol_struct csym; | |
27cddce2 | 2047 | static struct bfd fake_bfd; |
c5aa993b | 2048 | static bfd_target fake_target; |
c906108c SS |
2049 | |
2050 | if (csym.native == NULL) | |
2051 | { | |
da3c6d4a MS |
2052 | /* Create a fake symbol vector containing a Thumb symbol. |
2053 | This is solely so that the code in print_insn_little_arm() | |
2054 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2055 | the presence of a Thumb symbol and switch to decoding | |
2056 | Thumb instructions. */ | |
c5aa993b JM |
2057 | |
2058 | fake_target.flavour = bfd_target_coff_flavour; | |
2059 | fake_bfd.xvec = &fake_target; | |
c906108c | 2060 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2061 | csym.native = &ce; |
2062 | csym.symbol.the_bfd = &fake_bfd; | |
2063 | csym.symbol.name = "fake"; | |
2064 | asym = (asymbol *) & csym; | |
c906108c | 2065 | } |
c5aa993b | 2066 | |
c906108c | 2067 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2068 | info->symbols = &asym; |
c906108c SS |
2069 | } |
2070 | else | |
2071 | info->symbols = NULL; | |
c5aa993b | 2072 | |
d7449b42 | 2073 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
2074 | return print_insn_big_arm (memaddr, info); |
2075 | else | |
2076 | return print_insn_little_arm (memaddr, info); | |
2077 | } | |
2078 | ||
66e810cd RE |
2079 | /* The following define instruction sequences that will cause ARM |
2080 | cpu's to take an undefined instruction trap. These are used to | |
2081 | signal a breakpoint to GDB. | |
2082 | ||
2083 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2084 | modes. A different instruction is required for each mode. The ARM | |
2085 | cpu's can also be big or little endian. Thus four different | |
2086 | instructions are needed to support all cases. | |
2087 | ||
2088 | Note: ARMv4 defines several new instructions that will take the | |
2089 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2090 | not in fact add the new instructions. The new undefined | |
2091 | instructions in ARMv4 are all instructions that had no defined | |
2092 | behaviour in earlier chips. There is no guarantee that they will | |
2093 | raise an exception, but may be treated as NOP's. In practice, it | |
2094 | may only safe to rely on instructions matching: | |
2095 | ||
2096 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2097 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2098 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2099 | ||
2100 | Even this may only true if the condition predicate is true. The | |
2101 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2102 | ||
2103 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2104 | and NetBSD all use a software interrupt rather than an undefined | |
2105 | instruction to force a trap. This can be handled by by the | |
2106 | abi-specific code during establishment of the gdbarch vector. */ | |
2107 | ||
2108 | ||
d7b486e7 RE |
2109 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
2110 | override these definitions. */ | |
66e810cd RE |
2111 | #ifndef ARM_LE_BREAKPOINT |
2112 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
2113 | #endif | |
2114 | #ifndef ARM_BE_BREAKPOINT | |
2115 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
2116 | #endif | |
2117 | #ifndef THUMB_LE_BREAKPOINT | |
2118 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
2119 | #endif | |
2120 | #ifndef THUMB_BE_BREAKPOINT | |
2121 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
2122 | #endif | |
2123 | ||
2124 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2125 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2126 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2127 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2128 | ||
34e8f22d RE |
2129 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2130 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2131 | breakpoint should be used. It returns a pointer to a string of |
2132 | bytes that encode a breakpoint instruction, stores the length of | |
2133 | the string to *lenptr, and adjusts the program counter (if | |
2134 | necessary) to point to the actual memory location where the | |
c906108c SS |
2135 | breakpoint should be inserted. */ |
2136 | ||
34e8f22d RE |
2137 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
2138 | breakpoints and storing their handles instread of what was in | |
2139 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 2140 | otherwise remote-rdp will have to change. */ |
34e8f22d | 2141 | |
ab89facf | 2142 | static const unsigned char * |
ed9a39eb | 2143 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2144 | { |
66e810cd RE |
2145 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2146 | ||
c906108c SS |
2147 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
2148 | { | |
66e810cd RE |
2149 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2150 | *lenptr = tdep->thumb_breakpoint_size; | |
2151 | return tdep->thumb_breakpoint; | |
c906108c SS |
2152 | } |
2153 | else | |
2154 | { | |
66e810cd RE |
2155 | *lenptr = tdep->arm_breakpoint_size; |
2156 | return tdep->arm_breakpoint; | |
c906108c SS |
2157 | } |
2158 | } | |
ed9a39eb JM |
2159 | |
2160 | /* Extract from an array REGBUF containing the (raw) register state a | |
2161 | function return value of type TYPE, and copy that, in virtual | |
2162 | format, into VALBUF. */ | |
2163 | ||
34e8f22d | 2164 | static void |
ed9a39eb | 2165 | arm_extract_return_value (struct type *type, |
b508a996 RE |
2166 | struct regcache *regs, |
2167 | void *dst) | |
ed9a39eb | 2168 | { |
b508a996 RE |
2169 | bfd_byte *valbuf = dst; |
2170 | ||
ed9a39eb | 2171 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 RE |
2172 | { |
2173 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2174 | ||
2175 | switch (tdep->fp_model) | |
2176 | { | |
2177 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2178 | { |
2179 | /* The value is in register F0 in internal format. We need to | |
2180 | extract the raw value and then convert it to the desired | |
2181 | internal type. */ | |
2182 | bfd_byte tmpbuf[FP_REGISTER_RAW_SIZE]; | |
2183 | ||
2184 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2185 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2186 | valbuf); | |
2187 | } | |
08216dd7 RE |
2188 | break; |
2189 | ||
2190 | case ARM_FLOAT_SOFT: | |
2191 | case ARM_FLOAT_SOFT_VFP: | |
b508a996 RE |
2192 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2193 | if (TYPE_LENGTH (type) > 4) | |
2194 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
2195 | valbuf + INT_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2196 | break; |
2197 | ||
2198 | default: | |
2199 | internal_error | |
2200 | (__FILE__, __LINE__, | |
2201 | "arm_extract_return_value: Floating point model not supported"); | |
2202 | break; | |
2203 | } | |
2204 | } | |
b508a996 RE |
2205 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2206 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2207 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2208 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2209 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2210 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2211 | { | |
2212 | /* If the the type is a plain integer, then the access is | |
2213 | straight-forward. Otherwise we have to play around a bit more. */ | |
2214 | int len = TYPE_LENGTH (type); | |
2215 | int regno = ARM_A1_REGNUM; | |
2216 | ULONGEST tmp; | |
2217 | ||
2218 | while (len > 0) | |
2219 | { | |
2220 | /* By using store_unsigned_integer we avoid having to do | |
2221 | anything special for small big-endian values. */ | |
2222 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2223 | store_unsigned_integer (valbuf, | |
2224 | (len > INT_REGISTER_RAW_SIZE | |
2225 | ? INT_REGISTER_RAW_SIZE : len), | |
2226 | tmp); | |
2227 | len -= INT_REGISTER_RAW_SIZE; | |
2228 | valbuf += INT_REGISTER_RAW_SIZE; | |
2229 | } | |
2230 | } | |
ed9a39eb | 2231 | else |
b508a996 RE |
2232 | { |
2233 | /* For a structure or union the behaviour is as if the value had | |
2234 | been stored to word-aligned memory and then loaded into | |
2235 | registers with 32-bit load instruction(s). */ | |
2236 | int len = TYPE_LENGTH (type); | |
2237 | int regno = ARM_A1_REGNUM; | |
2238 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2239 | ||
2240 | while (len > 0) | |
2241 | { | |
2242 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2243 | memcpy (valbuf, tmpbuf, | |
2244 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); | |
2245 | len -= INT_REGISTER_RAW_SIZE; | |
2246 | valbuf += INT_REGISTER_RAW_SIZE; | |
2247 | } | |
2248 | } | |
34e8f22d RE |
2249 | } |
2250 | ||
67255d04 RE |
2251 | /* Extract from an array REGBUF containing the (raw) register state |
2252 | the address in which a function should return its structure value. */ | |
2253 | ||
2254 | static CORE_ADDR | |
95f95911 | 2255 | arm_extract_struct_value_address (struct regcache *regcache) |
67255d04 | 2256 | { |
95f95911 MS |
2257 | ULONGEST ret; |
2258 | ||
2259 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); | |
2260 | return ret; | |
67255d04 RE |
2261 | } |
2262 | ||
2263 | /* Will a function return an aggregate type in memory or in a | |
2264 | register? Return 0 if an aggregate type can be returned in a | |
2265 | register, 1 if it must be returned in memory. */ | |
2266 | ||
2267 | static int | |
2268 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2269 | { | |
2270 | int nRc; | |
2271 | register enum type_code code; | |
2272 | ||
2273 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
2274 | registers. For an aggregate type to be integer like, its size | |
2275 | must be less than or equal to REGISTER_SIZE and the offset of | |
2276 | each addressable subfield must be zero. Note that bit fields are | |
2277 | not addressable, and all addressable subfields of unions always | |
2278 | start at offset zero. | |
2279 | ||
2280 | This function is based on the behaviour of GCC 2.95.1. | |
2281 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2282 | ||
2283 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2284 | parameters correctly for a function returning the following | |
2285 | structure: struct { float f;}; This should be returned in memory, | |
2286 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2287 | know of any way to detect if a function like the above has been | |
2288 | compiled with the correct calling convention. */ | |
2289 | ||
2290 | /* All aggregate types that won't fit in a register must be returned | |
2291 | in memory. */ | |
2292 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
2293 | { | |
2294 | return 1; | |
2295 | } | |
2296 | ||
2297 | /* The only aggregate types that can be returned in a register are | |
2298 | structs and unions. Arrays must be returned in memory. */ | |
2299 | code = TYPE_CODE (type); | |
2300 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2301 | { | |
2302 | return 1; | |
2303 | } | |
2304 | ||
2305 | /* Assume all other aggregate types can be returned in a register. | |
2306 | Run a check for structures, unions and arrays. */ | |
2307 | nRc = 0; | |
2308 | ||
2309 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2310 | { | |
2311 | int i; | |
2312 | /* Need to check if this struct/union is "integer" like. For | |
2313 | this to be true, its size must be less than or equal to | |
2314 | REGISTER_SIZE and the offset of each addressable subfield | |
2315 | must be zero. Note that bit fields are not addressable, and | |
2316 | unions always start at offset zero. If any of the subfields | |
2317 | is a floating point type, the struct/union cannot be an | |
2318 | integer type. */ | |
2319 | ||
2320 | /* For each field in the object, check: | |
2321 | 1) Is it FP? --> yes, nRc = 1; | |
2322 | 2) Is it addressable (bitpos != 0) and | |
2323 | not packed (bitsize == 0)? | |
2324 | --> yes, nRc = 1 | |
2325 | */ | |
2326 | ||
2327 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2328 | { | |
2329 | enum type_code field_type_code; | |
2330 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
2331 | ||
2332 | /* Is it a floating point type field? */ | |
2333 | if (field_type_code == TYPE_CODE_FLT) | |
2334 | { | |
2335 | nRc = 1; | |
2336 | break; | |
2337 | } | |
2338 | ||
2339 | /* If bitpos != 0, then we have to care about it. */ | |
2340 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2341 | { | |
2342 | /* Bitfields are not addressable. If the field bitsize is | |
2343 | zero, then the field is not packed. Hence it cannot be | |
2344 | a bitfield or any other packed type. */ | |
2345 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2346 | { | |
2347 | nRc = 1; | |
2348 | break; | |
2349 | } | |
2350 | } | |
2351 | } | |
2352 | } | |
2353 | ||
2354 | return nRc; | |
2355 | } | |
2356 | ||
34e8f22d RE |
2357 | /* Write into appropriate registers a function return value of type |
2358 | TYPE, given in virtual format. */ | |
2359 | ||
2360 | static void | |
b508a996 RE |
2361 | arm_store_return_value (struct type *type, struct regcache *regs, |
2362 | const void *src) | |
34e8f22d | 2363 | { |
b508a996 RE |
2364 | const bfd_byte *valbuf = src; |
2365 | ||
34e8f22d RE |
2366 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2367 | { | |
08216dd7 | 2368 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7bbcf283 | 2369 | char buf[ARM_MAX_REGISTER_RAW_SIZE]; |
34e8f22d | 2370 | |
08216dd7 RE |
2371 | switch (tdep->fp_model) |
2372 | { | |
2373 | case ARM_FLOAT_FPA: | |
2374 | ||
b508a996 RE |
2375 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2376 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2377 | break; |
2378 | ||
2379 | case ARM_FLOAT_SOFT: | |
2380 | case ARM_FLOAT_SOFT_VFP: | |
b508a996 RE |
2381 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2382 | if (TYPE_LENGTH (type) > 4) | |
2383 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
2384 | valbuf + INT_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2385 | break; |
2386 | ||
2387 | default: | |
2388 | internal_error | |
2389 | (__FILE__, __LINE__, | |
2390 | "arm_store_return_value: Floating point model not supported"); | |
2391 | break; | |
2392 | } | |
34e8f22d | 2393 | } |
b508a996 RE |
2394 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2395 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2396 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2397 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2398 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2399 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2400 | { | |
2401 | if (TYPE_LENGTH (type) <= 4) | |
2402 | { | |
2403 | /* Values of one word or less are zero/sign-extended and | |
2404 | returned in r0. */ | |
2405 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2406 | LONGEST val = unpack_long (type, valbuf); | |
2407 | ||
2408 | store_signed_integer (tmpbuf, INT_REGISTER_RAW_SIZE, val); | |
2409 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); | |
2410 | } | |
2411 | else | |
2412 | { | |
2413 | /* Integral values greater than one word are stored in consecutive | |
2414 | registers starting with r0. This will always be a multiple of | |
2415 | the regiser size. */ | |
2416 | int len = TYPE_LENGTH (type); | |
2417 | int regno = ARM_A1_REGNUM; | |
2418 | ||
2419 | while (len > 0) | |
2420 | { | |
2421 | regcache_cooked_write (regs, regno++, valbuf); | |
2422 | len -= INT_REGISTER_RAW_SIZE; | |
2423 | valbuf += INT_REGISTER_RAW_SIZE; | |
2424 | } | |
2425 | } | |
2426 | } | |
34e8f22d | 2427 | else |
b508a996 RE |
2428 | { |
2429 | /* For a structure or union the behaviour is as if the value had | |
2430 | been stored to word-aligned memory and then loaded into | |
2431 | registers with 32-bit load instruction(s). */ | |
2432 | int len = TYPE_LENGTH (type); | |
2433 | int regno = ARM_A1_REGNUM; | |
2434 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2435 | ||
2436 | while (len > 0) | |
2437 | { | |
2438 | memcpy (tmpbuf, valbuf, | |
2439 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); | |
2440 | regcache_cooked_write (regs, regno++, tmpbuf); | |
2441 | len -= INT_REGISTER_RAW_SIZE; | |
2442 | valbuf += INT_REGISTER_RAW_SIZE; | |
2443 | } | |
2444 | } | |
34e8f22d RE |
2445 | } |
2446 | ||
2447 | /* Store the address of the place in which to copy the structure the | |
94c30b78 | 2448 | subroutine will return. This is called from call_function. */ |
34e8f22d RE |
2449 | |
2450 | static void | |
2451 | arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
2452 | { | |
2453 | write_register (ARM_A1_REGNUM, addr); | |
ed9a39eb JM |
2454 | } |
2455 | ||
9df628e0 RE |
2456 | static int |
2457 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2458 | { | |
2459 | CORE_ADDR jb_addr; | |
2460 | char buf[INT_REGISTER_RAW_SIZE]; | |
2461 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2462 | ||
2463 | jb_addr = read_register (ARM_A1_REGNUM); | |
2464 | ||
2465 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2466 | INT_REGISTER_RAW_SIZE)) | |
2467 | return 0; | |
2468 | ||
2469 | *pc = extract_address (buf, INT_REGISTER_RAW_SIZE); | |
2470 | return 1; | |
2471 | } | |
2472 | ||
ed9a39eb | 2473 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2474 | |
2475 | int | |
ed9a39eb | 2476 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2477 | { |
2478 | CORE_ADDR start_addr; | |
2479 | ||
ed9a39eb JM |
2480 | /* Find the starting address of the function containing the PC. If |
2481 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2482 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2483 | &start_addr, NULL)) | |
c906108c SS |
2484 | return 0; |
2485 | ||
2486 | return strncmp (name, "_call_via_r", 11) == 0; | |
2487 | } | |
2488 | ||
ed9a39eb JM |
2489 | /* If PC is in a Thumb call or return stub, return the address of the |
2490 | target PC, which is in a register. The thunk functions are called | |
2491 | _called_via_xx, where x is the register name. The possible names | |
2492 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2493 | |
2494 | CORE_ADDR | |
ed9a39eb | 2495 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2496 | { |
c5aa993b | 2497 | char *name; |
c906108c SS |
2498 | CORE_ADDR start_addr; |
2499 | ||
2500 | /* Find the starting address and name of the function containing the PC. */ | |
2501 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2502 | return 0; | |
2503 | ||
2504 | /* Call thunks always start with "_call_via_". */ | |
2505 | if (strncmp (name, "_call_via_", 10) == 0) | |
2506 | { | |
ed9a39eb JM |
2507 | /* Use the name suffix to determine which register contains the |
2508 | target PC. */ | |
c5aa993b JM |
2509 | static char *table[15] = |
2510 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2511 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2512 | }; | |
c906108c SS |
2513 | int regno; |
2514 | ||
2515 | for (regno = 0; regno <= 14; regno++) | |
2516 | if (strcmp (&name[10], table[regno]) == 0) | |
2517 | return read_register (regno); | |
2518 | } | |
ed9a39eb | 2519 | |
c5aa993b | 2520 | return 0; /* not a stub */ |
c906108c SS |
2521 | } |
2522 | ||
afd7eef0 RE |
2523 | static void |
2524 | set_arm_command (char *args, int from_tty) | |
2525 | { | |
2526 | printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n"); | |
2527 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); | |
2528 | } | |
2529 | ||
2530 | static void | |
2531 | show_arm_command (char *args, int from_tty) | |
2532 | { | |
2533 | help_list (showarmcmdlist, "show arm ", all_commands, gdb_stdout); | |
2534 | } | |
2535 | ||
2536 | /* If the user changes the register disassembly style used for info | |
2537 | register and other commands, we have to also switch the style used | |
2538 | in opcodes for disassembly output. This function is run in the "set | |
2539 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2540 | |
2541 | static void | |
afd7eef0 | 2542 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2543 | struct cmd_list_element *c) |
2544 | { | |
afd7eef0 | 2545 | set_disassembly_style (); |
bc90b915 FN |
2546 | } |
2547 | \f | |
966fbf70 | 2548 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2549 | static const char * |
34e8f22d | 2550 | arm_register_name (int i) |
966fbf70 RE |
2551 | { |
2552 | return arm_register_names[i]; | |
2553 | } | |
2554 | ||
bc90b915 | 2555 | static void |
afd7eef0 | 2556 | set_disassembly_style (void) |
bc90b915 FN |
2557 | { |
2558 | const char *setname, *setdesc, **regnames; | |
2559 | int numregs, j; | |
2560 | ||
afd7eef0 | 2561 | /* Find the style that the user wants in the opcodes table. */ |
bc90b915 FN |
2562 | int current = 0; |
2563 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
afd7eef0 RE |
2564 | while ((disassembly_style != setname) |
2565 | && (current < num_disassembly_options)) | |
bc90b915 FN |
2566 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
2567 | current_option = current; | |
2568 | ||
94c30b78 | 2569 | /* Fill our copy. */ |
bc90b915 FN |
2570 | for (j = 0; j < numregs; j++) |
2571 | arm_register_names[j] = (char *) regnames[j]; | |
2572 | ||
94c30b78 | 2573 | /* Adjust case. */ |
34e8f22d | 2574 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2575 | { |
34e8f22d RE |
2576 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2577 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2578 | } |
2579 | else | |
2580 | { | |
34e8f22d RE |
2581 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2582 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2583 | } |
2584 | ||
94c30b78 | 2585 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2586 | set_arm_regname_option (current); |
2587 | } | |
2588 | ||
afd7eef0 RE |
2589 | /* arm_othernames implements the "othernames" command. This is deprecated |
2590 | by the "set arm disassembly" command. */ | |
bc90b915 FN |
2591 | |
2592 | static void | |
2593 | arm_othernames (char *names, int n) | |
2594 | { | |
94c30b78 | 2595 | /* Circle through the various flavors. */ |
afd7eef0 | 2596 | current_option = (current_option + 1) % num_disassembly_options; |
bc90b915 | 2597 | |
afd7eef0 RE |
2598 | disassembly_style = valid_disassembly_styles[current_option]; |
2599 | set_disassembly_style (); | |
bc90b915 FN |
2600 | } |
2601 | ||
a42dd537 KB |
2602 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
2603 | for ARM linux targets using the struct offsets defined in <link.h>. | |
2604 | Note, however, that link.h is not actually referred to in this file. | |
2605 | Instead, the relevant structs offsets were obtained from examining | |
2606 | link.h. (We can't refer to link.h from this file because the host | |
2607 | system won't necessarily have it, or if it does, the structs which | |
94c30b78 | 2608 | it defines will refer to the host system, not the target). */ |
a42dd537 KB |
2609 | |
2610 | struct link_map_offsets * | |
2611 | arm_linux_svr4_fetch_link_map_offsets (void) | |
2612 | { | |
2613 | static struct link_map_offsets lmo; | |
2614 | static struct link_map_offsets *lmp = 0; | |
2615 | ||
2616 | if (lmp == 0) | |
2617 | { | |
2618 | lmp = &lmo; | |
2619 | ||
2620 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we | |
94c30b78 | 2621 | need. */ |
a42dd537 KB |
2622 | |
2623 | lmo.r_map_offset = 4; | |
2624 | lmo.r_map_size = 4; | |
2625 | ||
2626 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we | |
94c30b78 | 2627 | need. */ |
a42dd537 KB |
2628 | |
2629 | lmo.l_addr_offset = 0; | |
2630 | lmo.l_addr_size = 4; | |
2631 | ||
2632 | lmo.l_name_offset = 4; | |
2633 | lmo.l_name_size = 4; | |
2634 | ||
2635 | lmo.l_next_offset = 12; | |
2636 | lmo.l_next_size = 4; | |
2637 | ||
2638 | lmo.l_prev_offset = 16; | |
2639 | lmo.l_prev_size = 4; | |
2640 | } | |
2641 | ||
2642 | return lmp; | |
2643 | } | |
2644 | ||
082fc60d RE |
2645 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2646 | function. */ | |
2647 | ||
2648 | static int | |
2649 | coff_sym_is_thumb (int val) | |
2650 | { | |
2651 | return (val == C_THUMBEXT || | |
2652 | val == C_THUMBSTAT || | |
2653 | val == C_THUMBEXTFUNC || | |
2654 | val == C_THUMBSTATFUNC || | |
2655 | val == C_THUMBLABEL); | |
2656 | } | |
2657 | ||
2658 | /* arm_coff_make_msymbol_special() | |
2659 | arm_elf_make_msymbol_special() | |
2660 | ||
2661 | These functions test whether the COFF or ELF symbol corresponds to | |
2662 | an address in thumb code, and set a "special" bit in a minimal | |
2663 | symbol to indicate that it does. */ | |
2664 | ||
34e8f22d | 2665 | static void |
082fc60d RE |
2666 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2667 | { | |
2668 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2669 | STT_ARM_TFUNC). */ | |
2670 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2671 | == STT_LOPROC) | |
2672 | MSYMBOL_SET_SPECIAL (msym); | |
2673 | } | |
2674 | ||
34e8f22d | 2675 | static void |
082fc60d RE |
2676 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2677 | { | |
2678 | if (coff_sym_is_thumb (val)) | |
2679 | MSYMBOL_SET_SPECIAL (msym); | |
2680 | } | |
2681 | ||
97e03143 | 2682 | \f |
70f80edf JT |
2683 | static enum gdb_osabi |
2684 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2685 | { |
70f80edf JT |
2686 | unsigned int elfosabi, eflags; |
2687 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2688 | |
70f80edf | 2689 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2690 | |
70f80edf | 2691 | switch (elfosabi) |
97e03143 | 2692 | { |
70f80edf JT |
2693 | case ELFOSABI_NONE: |
2694 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the | |
2695 | file are conforming to the base specification for that machine | |
2696 | (there are no OS-specific extensions). In order to determine the | |
2697 | real OS in use we must look for OS notes that have been added. */ | |
2698 | bfd_map_over_sections (abfd, | |
2699 | generic_elf_osabi_sniff_abi_tag_sections, | |
2700 | &osabi); | |
2701 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2702 | { |
70f80edf JT |
2703 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
2704 | field for more information. */ | |
2705 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); | |
2706 | switch (eflags) | |
97e03143 | 2707 | { |
70f80edf JT |
2708 | case EF_ARM_EABI_VER1: |
2709 | osabi = GDB_OSABI_ARM_EABI_V1; | |
97e03143 RE |
2710 | break; |
2711 | ||
70f80edf JT |
2712 | case EF_ARM_EABI_VER2: |
2713 | osabi = GDB_OSABI_ARM_EABI_V2; | |
97e03143 RE |
2714 | break; |
2715 | ||
70f80edf JT |
2716 | case EF_ARM_EABI_UNKNOWN: |
2717 | /* Assume GNU tools. */ | |
2718 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2719 | break; |
2720 | ||
70f80edf JT |
2721 | default: |
2722 | internal_error (__FILE__, __LINE__, | |
2723 | "arm_elf_osabi_sniffer: Unknown ARM EABI " | |
2724 | "version 0x%x", eflags); | |
97e03143 RE |
2725 | } |
2726 | } | |
70f80edf | 2727 | break; |
97e03143 | 2728 | |
70f80edf JT |
2729 | case ELFOSABI_ARM: |
2730 | /* GNU tools use this value. Check note sections in this case, | |
2731 | as well. */ | |
97e03143 | 2732 | bfd_map_over_sections (abfd, |
70f80edf JT |
2733 | generic_elf_osabi_sniff_abi_tag_sections, |
2734 | &osabi); | |
2735 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2736 | { |
70f80edf JT |
2737 | /* Assume APCS ABI. */ |
2738 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2739 | } |
2740 | break; | |
2741 | ||
97e03143 | 2742 | case ELFOSABI_FREEBSD: |
70f80edf JT |
2743 | osabi = GDB_OSABI_FREEBSD_ELF; |
2744 | break; | |
97e03143 | 2745 | |
70f80edf JT |
2746 | case ELFOSABI_NETBSD: |
2747 | osabi = GDB_OSABI_NETBSD_ELF; | |
2748 | break; | |
97e03143 | 2749 | |
70f80edf JT |
2750 | case ELFOSABI_LINUX: |
2751 | osabi = GDB_OSABI_LINUX; | |
2752 | break; | |
97e03143 RE |
2753 | } |
2754 | ||
70f80edf | 2755 | return osabi; |
97e03143 RE |
2756 | } |
2757 | ||
70f80edf | 2758 | \f |
da3c6d4a MS |
2759 | /* Initialize the current architecture based on INFO. If possible, |
2760 | re-use an architecture from ARCHES, which is a list of | |
2761 | architectures already created during this debugging session. | |
97e03143 | 2762 | |
da3c6d4a MS |
2763 | Called e.g. at program startup, when reading a core file, and when |
2764 | reading a binary file. */ | |
97e03143 | 2765 | |
39bbf761 RE |
2766 | static struct gdbarch * |
2767 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2768 | { | |
97e03143 | 2769 | struct gdbarch_tdep *tdep; |
39bbf761 RE |
2770 | struct gdbarch *gdbarch; |
2771 | ||
97e03143 | 2772 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2773 | |
4be87837 | 2774 | if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) |
97e03143 | 2775 | { |
4be87837 | 2776 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2777 | { |
4be87837 DJ |
2778 | case bfd_target_aout_flavour: |
2779 | /* Assume it's an old APCS-style ABI. */ | |
2780 | info.osabi = GDB_OSABI_ARM_APCS; | |
2781 | break; | |
97e03143 | 2782 | |
4be87837 DJ |
2783 | case bfd_target_coff_flavour: |
2784 | /* Assume it's an old APCS-style ABI. */ | |
2785 | /* XXX WinCE? */ | |
2786 | info.osabi = GDB_OSABI_ARM_APCS; | |
2787 | break; | |
97e03143 | 2788 | |
4be87837 DJ |
2789 | default: |
2790 | /* Leave it as "unknown". */ | |
50ceaba5 | 2791 | break; |
97e03143 RE |
2792 | } |
2793 | } | |
2794 | ||
4be87837 DJ |
2795 | /* If there is already a candidate, use it. */ |
2796 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2797 | if (arches != NULL) | |
2798 | return arches->gdbarch; | |
97e03143 RE |
2799 | |
2800 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2801 | gdbarch = gdbarch_alloc (&info, tdep); | |
2802 | ||
a5afb99f AC |
2803 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is |
2804 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ | |
2805 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); | |
2806 | ||
08216dd7 RE |
2807 | /* This is the way it has always defaulted. */ |
2808 | tdep->fp_model = ARM_FLOAT_FPA; | |
2809 | ||
2810 | /* Breakpoints. */ | |
67255d04 RE |
2811 | switch (info.byte_order) |
2812 | { | |
2813 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2814 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2815 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2816 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2817 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2818 | ||
67255d04 RE |
2819 | break; |
2820 | ||
2821 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2822 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2823 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2824 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2825 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2826 | ||
67255d04 RE |
2827 | break; |
2828 | ||
2829 | default: | |
2830 | internal_error (__FILE__, __LINE__, | |
2831 | "arm_gdbarch_init: bad byte order for float format"); | |
2832 | } | |
2833 | ||
d7b486e7 RE |
2834 | /* On ARM targets char defaults to unsigned. */ |
2835 | set_gdbarch_char_signed (gdbarch, 0); | |
2836 | ||
9df628e0 | 2837 | /* This should be low enough for everything. */ |
97e03143 | 2838 | tdep->lowest_pc = 0x20; |
94c30b78 | 2839 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2840 | |
848cfffb AC |
2841 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); |
2842 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
2843 | ||
2844 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
2845 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
2846 | ||
2847 | set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words); | |
2848 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); | |
2849 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
2850 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
2851 | ||
2852 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
848cfffb AC |
2853 | |
2854 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
2855 | set_gdbarch_push_return_address (gdbarch, arm_push_return_address); | |
39bbf761 | 2856 | |
39bbf761 RE |
2857 | set_gdbarch_push_arguments (gdbarch, arm_push_arguments); |
2858 | ||
148754e5 | 2859 | /* Frame handling. */ |
39bbf761 | 2860 | set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid); |
e9582e71 | 2861 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, arm_init_extra_frame_info); |
148754e5 RE |
2862 | set_gdbarch_read_fp (gdbarch, arm_read_fp); |
2863 | set_gdbarch_frame_chain (gdbarch, arm_frame_chain); | |
2864 | set_gdbarch_frameless_function_invocation | |
2865 | (gdbarch, arm_frameless_function_invocation); | |
8bedc050 | 2866 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, arm_frame_saved_pc); |
148754e5 RE |
2867 | set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address); |
2868 | set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address); | |
2869 | set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args); | |
2870 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
f30ee0bc | 2871 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs); |
749b82f6 | 2872 | set_gdbarch_deprecated_pop_frame (gdbarch, arm_pop_frame); |
148754e5 | 2873 | |
34e8f22d RE |
2874 | /* Address manipulation. */ |
2875 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2876 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2877 | ||
2878 | /* Offset from address of function to start of its code. */ | |
2879 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2880 | ||
2881 | /* Advance PC across function entry code. */ | |
2882 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2883 | ||
2884 | /* Get the PC when a frame might not be available. */ | |
2885 | set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); | |
2886 | ||
2887 | /* The stack grows downward. */ | |
2888 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2889 | ||
2890 | /* Breakpoint manipulation. */ | |
2891 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
2892 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2893 | ||
2894 | /* Information about registers, etc. */ | |
2895 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
94c30b78 | 2896 | set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2897 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2898 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
2899 | set_gdbarch_register_byte (gdbarch, arm_register_byte); | |
2900 | set_gdbarch_register_bytes (gdbarch, | |
2901 | (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
2902 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
2903 | + NUM_SREGS * STATUS_REGISTER_SIZE)); | |
2904 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); | |
2905 | set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size); | |
2906 | set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size); | |
a0ed5532 AC |
2907 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE); |
2908 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE); | |
34e8f22d RE |
2909 | set_gdbarch_register_virtual_type (gdbarch, arm_register_type); |
2910 | ||
26216b98 AC |
2911 | /* Internal <-> external register number maps. */ |
2912 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2913 | ||
34e8f22d RE |
2914 | /* Integer registers are 4 bytes. */ |
2915 | set_gdbarch_register_size (gdbarch, 4); | |
2916 | set_gdbarch_register_name (gdbarch, arm_register_name); | |
2917 | ||
2918 | /* Returning results. */ | |
b508a996 RE |
2919 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
2920 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
34e8f22d | 2921 | set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return); |
67255d04 | 2922 | set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); |
95f95911 | 2923 | set_gdbarch_extract_struct_value_address (gdbarch, |
67255d04 | 2924 | arm_extract_struct_value_address); |
34e8f22d RE |
2925 | |
2926 | /* Single stepping. */ | |
2927 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2928 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2929 | ||
2930 | /* Minsymbol frobbing. */ | |
2931 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2932 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2933 | arm_coff_make_msymbol_special); | |
2934 | ||
97e03143 | 2935 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2936 | gdbarch_init_osabi (info, gdbarch); |
97e03143 RE |
2937 | |
2938 | /* Now we have tuned the configuration, set a few final things, | |
2939 | based on what the OS ABI has told us. */ | |
2940 | ||
9df628e0 RE |
2941 | if (tdep->jb_pc >= 0) |
2942 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2943 | ||
08216dd7 RE |
2944 | /* Floating point sizes and format. */ |
2945 | switch (info.byte_order) | |
2946 | { | |
2947 | case BFD_ENDIAN_BIG: | |
2948 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2949 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2950 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
2951 | ||
2952 | break; | |
2953 | ||
2954 | case BFD_ENDIAN_LITTLE: | |
2955 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
2956 | if (tdep->fp_model == ARM_FLOAT_VFP | |
2957 | || tdep->fp_model == ARM_FLOAT_SOFT_VFP) | |
2958 | { | |
2959 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2960 | set_gdbarch_long_double_format (gdbarch, | |
2961 | &floatformat_ieee_double_little); | |
2962 | } | |
2963 | else | |
2964 | { | |
2965 | set_gdbarch_double_format | |
2966 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2967 | set_gdbarch_long_double_format | |
2968 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2969 | } | |
2970 | break; | |
2971 | ||
2972 | default: | |
2973 | internal_error (__FILE__, __LINE__, | |
2974 | "arm_gdbarch_init: bad byte order for float format"); | |
2975 | } | |
2976 | ||
39bbf761 RE |
2977 | return gdbarch; |
2978 | } | |
2979 | ||
97e03143 RE |
2980 | static void |
2981 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2982 | { | |
2983 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2984 | ||
2985 | if (tdep == NULL) | |
2986 | return; | |
2987 | ||
97e03143 RE |
2988 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", |
2989 | (unsigned long) tdep->lowest_pc); | |
2990 | } | |
2991 | ||
2992 | static void | |
2993 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
2994 | struct gdbarch *gdbarch) | |
2995 | { | |
2996 | /* Place-holder. */ | |
2997 | } | |
2998 | ||
2999 | static void | |
3000 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
3001 | struct gdbarch *gdbarch) | |
3002 | { | |
3003 | /* Place-holder. */ | |
3004 | } | |
3005 | ||
3006 | static void | |
3007 | arm_init_abi_apcs (struct gdbarch_info info, | |
3008 | struct gdbarch *gdbarch) | |
3009 | { | |
3010 | /* Place-holder. */ | |
3011 | } | |
3012 | ||
c906108c | 3013 | void |
ed9a39eb | 3014 | _initialize_arm_tdep (void) |
c906108c | 3015 | { |
bc90b915 FN |
3016 | struct ui_file *stb; |
3017 | long length; | |
96baa820 | 3018 | struct cmd_list_element *new_cmd; |
53904c9e AC |
3019 | const char *setname; |
3020 | const char *setdesc; | |
3021 | const char **regnames; | |
bc90b915 FN |
3022 | int numregs, i, j; |
3023 | static char *helptext; | |
085dd6e6 | 3024 | |
39bbf761 | 3025 | if (GDB_MULTI_ARCH) |
97e03143 RE |
3026 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
3027 | ||
70f80edf JT |
3028 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
3029 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
3030 | bfd_target_elf_flavour, | |
3031 | arm_elf_osabi_sniffer); | |
3032 | ||
97e03143 | 3033 | /* Register some ABI variants for embedded systems. */ |
05816f70 | 3034 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1, |
70f80edf | 3035 | arm_init_abi_eabi_v1); |
05816f70 | 3036 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2, |
70f80edf | 3037 | arm_init_abi_eabi_v2); |
05816f70 | 3038 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS, |
70f80edf | 3039 | arm_init_abi_apcs); |
39bbf761 | 3040 | |
c906108c | 3041 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 3042 | |
94c30b78 | 3043 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
3044 | num_disassembly_options = get_arm_regname_num_options (); |
3045 | ||
3046 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
3047 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
3048 | "Various ARM-specific commands.", | |
3049 | &setarmcmdlist, "set arm ", 0, &setlist); | |
3050 | ||
3051 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
3052 | "Various ARM-specific commands.", | |
3053 | &showarmcmdlist, "show arm ", 0, &showlist); | |
bc90b915 | 3054 | |
94c30b78 | 3055 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3056 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3057 | |
94c30b78 | 3058 | /* Begin creating the help text. */ |
bc90b915 | 3059 | stb = mem_fileopen (); |
afd7eef0 RE |
3060 | fprintf_unfiltered (stb, "Set the disassembly style.\n" |
3061 | "The valid values are:\n"); | |
ed9a39eb | 3062 | |
94c30b78 | 3063 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
afd7eef0 RE |
3064 | valid_disassembly_styles |
3065 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
3066 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
3067 | { |
3068 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 3069 | valid_disassembly_styles[i] = setname; |
bc90b915 FN |
3070 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
3071 | setdesc); | |
94c30b78 | 3072 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
3073 | if (!strcmp (setname, "std")) |
3074 | { | |
afd7eef0 | 3075 | disassembly_style = setname; |
bc90b915 FN |
3076 | current_option = i; |
3077 | for (j = 0; j < numregs; j++) | |
3078 | arm_register_names[j] = (char *) regnames[j]; | |
3079 | set_arm_regname_option (i); | |
3080 | } | |
3081 | } | |
94c30b78 | 3082 | /* Mark the end of valid options. */ |
afd7eef0 | 3083 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 3084 | |
94c30b78 | 3085 | /* Finish the creation of the help text. */ |
bc90b915 FN |
3086 | fprintf_unfiltered (stb, "The default is \"std\"."); |
3087 | helptext = ui_file_xstrdup (stb, &length); | |
3088 | ui_file_delete (stb); | |
ed9a39eb | 3089 | |
afd7eef0 | 3090 | /* Add the deprecated disassembly-flavor command. */ |
96baa820 | 3091 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
afd7eef0 RE |
3092 | valid_disassembly_styles, |
3093 | &disassembly_style, | |
bc90b915 | 3094 | helptext, |
ed9a39eb | 3095 | &setlist); |
afd7eef0 RE |
3096 | set_cmd_sfunc (new_cmd, set_disassembly_style_sfunc); |
3097 | deprecate_cmd (new_cmd, "set arm disassembly"); | |
3098 | deprecate_cmd (add_show_from_set (new_cmd, &showlist), | |
3099 | "show arm disassembly"); | |
3100 | ||
3101 | /* And now add the new interface. */ | |
3102 | new_cmd = add_set_enum_cmd ("disassembly", no_class, valid_disassembly_styles, | |
3103 | &disassembly_style, helptext, &setarmcmdlist); | |
3104 | ||
3105 | add_show_from_set (new_cmd, &showarmcmdlist); | |
ed9a39eb | 3106 | |
c906108c SS |
3107 | /* ??? Maybe this should be a boolean. */ |
3108 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 3109 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 3110 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 3111 | &showlist); |
c906108c | 3112 | |
94c30b78 | 3113 | /* Add the deprecated "othernames" command. */ |
afd7eef0 RE |
3114 | deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames, |
3115 | "Switch to the next set of register names."), | |
3116 | "set arm disassembly"); | |
c3b4394c | 3117 | |
6529d2dd AC |
3118 | /* Debugging flag. */ |
3119 | add_show_from_set (add_set_cmd ("arm", class_maintenance, var_zinteger, | |
afd7eef0 RE |
3120 | &arm_debug, "Set arm debugging.\n" |
3121 | "When non-zero, arm specific debugging is enabled.", | |
3122 | &setdebuglist), &showdebuglist); | |
c906108c | 3123 | } |