Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
c3b4394c | 3 | 2001, 2002 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "symfile.h" | |
30 | #include "gdb_string.h" | |
e8b09175 | 31 | #include "dis-asm.h" /* For register flavors. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
a42dd537 | 36 | #include "solib-svr4.h" |
34e8f22d RE |
37 | |
38 | #include "arm-tdep.h" | |
39 | ||
082fc60d RE |
40 | #include "elf-bfd.h" |
41 | #include "coff/internal.h" | |
97e03143 | 42 | #include "elf/arm.h" |
c906108c | 43 | |
2a451106 KB |
44 | /* Each OS has a different mechanism for accessing the various |
45 | registers stored in the sigcontext structure. | |
46 | ||
47 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
48 | function pointer) which may be used to determine the addresses | |
49 | of the various saved registers in the sigcontext structure. | |
50 | ||
51 | For the ARM target, there are three parameters to this function. | |
52 | The first is the pc value of the frame under consideration, the | |
53 | second the stack pointer of this frame, and the last is the | |
54 | register number to fetch. | |
55 | ||
56 | If the tm.h file does not define this macro, then it's assumed that | |
57 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
58 | be 0. | |
59 | ||
60 | When it comes time to multi-arching this code, see the identically | |
61 | named machinery in ia64-tdep.c for an example of how it could be | |
62 | done. It should not be necessary to modify the code below where | |
63 | this macro is used. */ | |
64 | ||
3bb04bdd AC |
65 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
66 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
67 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
68 | #endif | |
69 | #else | |
70 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
71 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
72 | #endif |
73 | ||
082fc60d RE |
74 | /* Macros for setting and testing a bit in a minimal symbol that marks |
75 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
76 | is used for this purpose. This field is already being used to store | |
77 | the symbol size, so the assumption is that the symbol size cannot | |
78 | exceed 2^31. | |
79 | ||
80 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
81 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
82 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
83 | i.e. the "info" field with the "special" bit | |
84 | masked out. */ | |
85 | ||
86 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
87 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
88 | | 0x80000000) | |
89 | ||
90 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
91 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
92 | ||
93 | #define MSYMBOL_SIZE(msym) \ | |
94 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
ed9a39eb | 95 | |
97e03143 RE |
96 | /* This table matches the indicees assigned to enum arm_abi. Keep |
97 | them in sync. */ | |
98 | ||
99 | static const char * const arm_abi_names[] = | |
100 | { | |
101 | "<unknown>", | |
102 | "ARM EABI (version 1)", | |
103 | "ARM EABI (version 2)", | |
104 | "GNU/Linux", | |
105 | "NetBSD (a.out)", | |
106 | "NetBSD (ELF)", | |
107 | "APCS", | |
108 | "FreeBSD", | |
109 | "Windows CE", | |
110 | NULL | |
111 | }; | |
112 | ||
bc90b915 FN |
113 | /* Number of different reg name sets (options). */ |
114 | static int num_flavor_options; | |
115 | ||
116 | /* We have more registers than the disassembler as gdb can print the value | |
117 | of special registers as well. | |
118 | The general register names are overwritten by whatever is being used by | |
119 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ | |
120 | ||
121 | /* Initial value: Register names used in ARM's ISA documentation. */ | |
122 | static char * arm_register_name_strings[] = | |
da59e081 JM |
123 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
124 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
125 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
126 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
127 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
128 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
bc90b915 | 129 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 130 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 131 | |
bc90b915 | 132 | /* Valid register name flavors. */ |
53904c9e | 133 | static const char **valid_flavors; |
ed9a39eb | 134 | |
bc90b915 | 135 | /* Disassembly flavor to use. Default to "std" register names. */ |
53904c9e | 136 | static const char *disassembly_flavor; |
da3c6d4a MS |
137 | /* Index to that option in the opcodes table. */ |
138 | static int current_option; | |
96baa820 | 139 | |
ed9a39eb JM |
140 | /* This is used to keep the bfd arch_info in sync with the disassembly |
141 | flavor. */ | |
142 | static void set_disassembly_flavor_sfunc(char *, int, | |
143 | struct cmd_list_element *); | |
144 | static void set_disassembly_flavor (void); | |
145 | ||
146 | static void convert_from_extended (void *ptr, void *dbl); | |
147 | ||
148 | /* Define other aspects of the stack frame. We keep the offsets of | |
149 | all saved registers, 'cause we need 'em a lot! We also keep the | |
150 | current size of the stack frame, and the offset of the frame | |
151 | pointer from the stack pointer (for frameless functions, and when | |
152 | we're still in the prologue of a function with a frame) */ | |
153 | ||
154 | struct frame_extra_info | |
c3b4394c RE |
155 | { |
156 | int framesize; | |
157 | int frameoffset; | |
158 | int framereg; | |
159 | }; | |
ed9a39eb | 160 | |
bc90b915 FN |
161 | /* Addresses for calling Thumb functions have the bit 0 set. |
162 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
163 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
164 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
165 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
166 | ||
39bbf761 | 167 | static int |
ed9a39eb | 168 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 169 | { |
c906108c SS |
170 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
171 | } | |
172 | ||
173 | /* Set to true if the 32-bit mode is in use. */ | |
174 | ||
175 | int arm_apcs_32 = 1; | |
176 | ||
ed9a39eb JM |
177 | /* Flag set by arm_fix_call_dummy that tells whether the target |
178 | function is a Thumb function. This flag is checked by | |
179 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
180 | its use in valops.c) to pass the function address as an additional | |
181 | parameter. */ | |
c906108c SS |
182 | |
183 | static int target_is_thumb; | |
184 | ||
ed9a39eb JM |
185 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
186 | function is a Thumb function. This flag is checked by | |
187 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
188 | |
189 | static int caller_is_thumb; | |
190 | ||
ed9a39eb JM |
191 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
192 | function. */ | |
c906108c | 193 | |
34e8f22d | 194 | int |
2a451106 | 195 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 196 | { |
c5aa993b | 197 | struct minimal_symbol *sym; |
c906108c | 198 | |
ed9a39eb | 199 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
200 | if (IS_THUMB_ADDR (memaddr)) |
201 | return 1; | |
202 | ||
ed9a39eb | 203 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
204 | sym = lookup_minimal_symbol_by_pc (memaddr); |
205 | if (sym) | |
206 | { | |
c5aa993b | 207 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
208 | } |
209 | else | |
ed9a39eb JM |
210 | { |
211 | return 0; | |
212 | } | |
c906108c SS |
213 | } |
214 | ||
ed9a39eb JM |
215 | /* Determine if the program counter specified in MEMADDR is in a call |
216 | dummy being called from a Thumb function. */ | |
c906108c | 217 | |
34e8f22d | 218 | int |
2a451106 | 219 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 220 | { |
c5aa993b | 221 | CORE_ADDR sp = read_sp (); |
c906108c | 222 | |
dfcd3bfb JM |
223 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
224 | is the best we can do. We are trying to determine if the pc is on | |
225 | the stack, which (hopefully) will only happen in a call dummy. | |
226 | We hope the current stack pointer is not so far alway from the dummy | |
227 | frame location (true if we have not pushed large data structures or | |
228 | gone too many levels deep) and that our 1024 is not enough to consider | |
229 | code regions as part of the stack (true for most practical purposes) */ | |
230 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) | |
c906108c SS |
231 | return caller_is_thumb; |
232 | else | |
233 | return 0; | |
234 | } | |
235 | ||
181c1381 | 236 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 237 | static CORE_ADDR |
ed9a39eb | 238 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c SS |
239 | { |
240 | if (arm_pc_is_thumb (val)) | |
241 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); | |
242 | else | |
243 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); | |
244 | } | |
245 | ||
181c1381 RE |
246 | /* When reading symbols, we need to zap the low bit of the address, |
247 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 248 | static CORE_ADDR |
181c1381 RE |
249 | arm_smash_text_address (CORE_ADDR val) |
250 | { | |
251 | return val & ~1; | |
252 | } | |
253 | ||
34e8f22d RE |
254 | /* Immediately after a function call, return the saved pc. Can't |
255 | always go through the frames for this because on some machines the | |
256 | new frame is not set up until the new function executes some | |
257 | instructions. */ | |
258 | ||
259 | static CORE_ADDR | |
ed9a39eb | 260 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 261 | { |
34e8f22d | 262 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
263 | } |
264 | ||
0defa245 RE |
265 | /* Determine whether the function invocation represented by FI has a |
266 | frame on the stack associated with it. If it does return zero, | |
267 | otherwise return 1. */ | |
268 | ||
148754e5 | 269 | static int |
ed9a39eb | 270 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 271 | { |
392a587b | 272 | CORE_ADDR func_start, after_prologue; |
96baa820 | 273 | int frameless; |
ed9a39eb | 274 | |
0defa245 RE |
275 | /* Sometimes we have functions that do a little setup (like saving the |
276 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
277 | The symbol table will report this as a prologue. However, it is | |
278 | important not to try to parse these partial frames as frames, or we | |
279 | will get really confused. | |
280 | ||
281 | So I will demand 3 instructions between the start & end of the | |
282 | prologue before I call it a real prologue, i.e. at least | |
283 | mov ip, sp, | |
284 | stmdb sp!, {} | |
285 | sub sp, ip, #4. */ | |
286 | ||
392a587b | 287 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); |
7be570e7 | 288 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 289 | |
96baa820 | 290 | /* There are some frameless functions whose first two instructions |
ed9a39eb JM |
291 | follow the standard APCS form, in which case after_prologue will |
292 | be func_start + 8. */ | |
293 | ||
96baa820 | 294 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
295 | return frameless; |
296 | } | |
297 | ||
0defa245 | 298 | /* The address of the arguments in the frame. */ |
148754e5 | 299 | static CORE_ADDR |
0defa245 RE |
300 | arm_frame_args_address (struct frame_info *fi) |
301 | { | |
302 | return fi->frame; | |
303 | } | |
304 | ||
305 | /* The address of the local variables in the frame. */ | |
148754e5 | 306 | static CORE_ADDR |
0defa245 RE |
307 | arm_frame_locals_address (struct frame_info *fi) |
308 | { | |
309 | return fi->frame; | |
310 | } | |
311 | ||
312 | /* The number of arguments being passed in the frame. */ | |
148754e5 | 313 | static int |
0defa245 RE |
314 | arm_frame_num_args (struct frame_info *fi) |
315 | { | |
316 | /* We have no way of knowing. */ | |
317 | return -1; | |
318 | } | |
319 | ||
c906108c | 320 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
321 | push {r7, lr} |
322 | add sp, sp, #-28 | |
323 | add r7, sp, #12 | |
c906108c | 324 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
325 | mov r7, sp |
326 | ||
327 | or like this: | |
328 | push {r7, lr} | |
329 | mov r7, sp | |
330 | sub sp, #12 | |
331 | ||
332 | or, on tpcs, like this: | |
333 | sub sp,#16 | |
334 | push {r7, lr} | |
335 | (many instructions) | |
336 | mov r7, sp | |
337 | sub sp, #12 | |
338 | ||
339 | There is always one instruction of three classes: | |
340 | 1 - push | |
341 | 2 - setting of r7 | |
342 | 3 - adjusting of sp | |
343 | ||
344 | When we have found at least one of each class we are done with the prolog. | |
345 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 346 | */ |
c906108c SS |
347 | |
348 | static CORE_ADDR | |
c7885828 | 349 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
350 | { |
351 | CORE_ADDR current_pc; | |
da3c6d4a MS |
352 | /* findmask: |
353 | bit 0 - push { rlist } | |
354 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
355 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
356 | */ | |
357 | int findmask = 0; | |
358 | ||
359 | for (current_pc = pc; | |
360 | current_pc + 2 < func_end && current_pc < pc + 40; | |
361 | current_pc += 2) | |
c906108c SS |
362 | { |
363 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
364 | ||
da59e081 JM |
365 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
366 | { | |
367 | findmask |= 1; /* push found */ | |
368 | } | |
da3c6d4a MS |
369 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
370 | sub sp, #simm */ | |
da59e081 JM |
371 | { |
372 | if ((findmask & 1) == 0) /* before push ? */ | |
373 | continue; | |
374 | else | |
375 | findmask |= 4; /* add/sub sp found */ | |
376 | } | |
377 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
378 | { | |
379 | findmask |= 2; /* setting of r7 found */ | |
380 | } | |
381 | else if (insn == 0x466f) /* mov r7, sp */ | |
382 | { | |
383 | findmask |= 2; /* setting of r7 found */ | |
384 | } | |
3d74b771 FF |
385 | else if (findmask == (4+2+1)) |
386 | { | |
da3c6d4a MS |
387 | /* We have found one of each type of prologue instruction */ |
388 | break; | |
3d74b771 | 389 | } |
da59e081 | 390 | else |
da3c6d4a MS |
391 | /* something in the prolog that we don't care about or some |
392 | instruction from outside the prolog scheduled here for | |
393 | optimization */ | |
394 | continue; | |
c906108c SS |
395 | } |
396 | ||
397 | return current_pc; | |
398 | } | |
399 | ||
da3c6d4a MS |
400 | /* Advance the PC across any function entry prologue instructions to |
401 | reach some "real" code. | |
34e8f22d RE |
402 | |
403 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 404 | prologue: |
c906108c | 405 | |
c5aa993b JM |
406 | mov ip, sp |
407 | [stmfd sp!, {a1,a2,a3,a4}] | |
408 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
409 | [stfe f7, [sp, #-12]!] |
410 | [stfe f6, [sp, #-12]!] | |
411 | [stfe f5, [sp, #-12]!] | |
412 | [stfe f4, [sp, #-12]!] | |
413 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 414 | |
34e8f22d | 415 | static CORE_ADDR |
ed9a39eb | 416 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
417 | { |
418 | unsigned long inst; | |
419 | CORE_ADDR skip_pc; | |
420 | CORE_ADDR func_addr, func_end; | |
50f6fb4b | 421 | char *func_name; |
c906108c SS |
422 | struct symtab_and_line sal; |
423 | ||
96baa820 | 424 | /* See what the symbol table says. */ |
ed9a39eb | 425 | |
50f6fb4b | 426 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 427 | { |
50f6fb4b CV |
428 | struct symbol *sym; |
429 | ||
430 | /* Found a function. */ | |
431 | sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL); | |
432 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
433 | { | |
434 | /* Don't use this trick for assembly source files. */ | |
435 | sal = find_pc_line (func_addr, 0); | |
436 | if ((sal.line != 0) && (sal.end < func_end)) | |
437 | return sal.end; | |
438 | } | |
c906108c SS |
439 | } |
440 | ||
441 | /* Check if this is Thumb code. */ | |
442 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 443 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
444 | |
445 | /* Can't find the prologue end in the symbol table, try it the hard way | |
446 | by disassembling the instructions. */ | |
447 | skip_pc = pc; | |
448 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 449 | if (inst != 0xe1a0c00d) /* mov ip, sp */ |
c906108c SS |
450 | return pc; |
451 | ||
452 | skip_pc += 4; | |
453 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 454 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
c906108c SS |
455 | { |
456 | skip_pc += 4; | |
457 | inst = read_memory_integer (skip_pc, 4); | |
458 | } | |
459 | ||
c5aa993b | 460 | if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */ |
c906108c SS |
461 | return pc; |
462 | ||
463 | skip_pc += 4; | |
464 | inst = read_memory_integer (skip_pc, 4); | |
465 | ||
466 | /* Any insns after this point may float into the code, if it makes | |
ed9a39eb JM |
467 | for better instruction scheduling, so we skip them only if we |
468 | find them, but still consdier the function to be frame-ful. */ | |
c906108c | 469 | |
ed9a39eb JM |
470 | /* We may have either one sfmfd instruction here, or several stfe |
471 | insns, depending on the version of floating point code we | |
472 | support. */ | |
c5aa993b | 473 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
c906108c SS |
474 | { |
475 | skip_pc += 4; | |
476 | inst = read_memory_integer (skip_pc, 4); | |
477 | } | |
478 | else | |
479 | { | |
c5aa993b JM |
480 | while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
481 | { | |
482 | skip_pc += 4; | |
483 | inst = read_memory_integer (skip_pc, 4); | |
484 | } | |
c906108c SS |
485 | } |
486 | ||
c5aa993b | 487 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
c906108c SS |
488 | skip_pc += 4; |
489 | ||
490 | return skip_pc; | |
491 | } | |
c5aa993b | 492 | /* *INDENT-OFF* */ |
c906108c SS |
493 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
494 | This function decodes a Thumb function prologue to determine: | |
495 | 1) the size of the stack frame | |
496 | 2) which registers are saved on it | |
497 | 3) the offsets of saved regs | |
498 | 4) the offset from the stack pointer to the frame pointer | |
499 | This information is stored in the "extra" fields of the frame_info. | |
500 | ||
da59e081 JM |
501 | A typical Thumb function prologue would create this stack frame |
502 | (offsets relative to FP) | |
c906108c SS |
503 | old SP -> 24 stack parameters |
504 | 20 LR | |
505 | 16 R7 | |
506 | R7 -> 0 local variables (16 bytes) | |
507 | SP -> -12 additional stack space (12 bytes) | |
508 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
509 | 12 bytes. The frame register is R7. |
510 | ||
da3c6d4a MS |
511 | The comments for thumb_skip_prolog() describe the algorithm we use |
512 | to detect the end of the prolog. */ | |
c5aa993b JM |
513 | /* *INDENT-ON* */ |
514 | ||
c906108c | 515 | static void |
ed9a39eb | 516 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
517 | { |
518 | CORE_ADDR prologue_start; | |
519 | CORE_ADDR prologue_end; | |
520 | CORE_ADDR current_pc; | |
da3c6d4a MS |
521 | /* Which register has been copied to register n? */ |
522 | int saved_reg[16]; | |
523 | /* findmask: | |
524 | bit 0 - push { rlist } | |
525 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
526 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
527 | */ | |
528 | int findmask = 0; | |
c5aa993b | 529 | int i; |
c906108c | 530 | |
c5aa993b | 531 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
532 | { |
533 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
534 | ||
c5aa993b | 535 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
536 | prologue_end = fi->pc; |
537 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
c5aa993b | 538 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
539 | } |
540 | else | |
da3c6d4a MS |
541 | /* We're in the boondocks: allow for |
542 | 16 pushes, an add, and "mv fp,sp". */ | |
543 | prologue_end = prologue_start + 40; | |
c906108c SS |
544 | |
545 | prologue_end = min (prologue_end, fi->pc); | |
546 | ||
547 | /* Initialize the saved register map. When register H is copied to | |
548 | register L, we will put H in saved_reg[L]. */ | |
549 | for (i = 0; i < 16; i++) | |
550 | saved_reg[i] = i; | |
551 | ||
552 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
553 | frame pointer, adjust the stack pointer, and save registers. |
554 | Do this until all basic prolog instructions are found. */ | |
c906108c | 555 | |
c3b4394c | 556 | fi->extra_info->framesize = 0; |
da59e081 JM |
557 | for (current_pc = prologue_start; |
558 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
559 | current_pc += 2) | |
c906108c SS |
560 | { |
561 | unsigned short insn; | |
562 | int regno; | |
563 | int offset; | |
564 | ||
565 | insn = read_memory_unsigned_integer (current_pc, 2); | |
566 | ||
c5aa993b | 567 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 568 | { |
da59e081 JM |
569 | int mask; |
570 | findmask |= 1; /* push found */ | |
c906108c SS |
571 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
572 | whether to save LR (R14). */ | |
da59e081 | 573 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c SS |
574 | |
575 | /* Calculate offsets of saved R0-R7 and LR. */ | |
34e8f22d | 576 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 577 | if (mask & (1 << regno)) |
c5aa993b | 578 | { |
c3b4394c RE |
579 | fi->extra_info->framesize += 4; |
580 | fi->saved_regs[saved_reg[regno]] = | |
581 | -(fi->extra_info->framesize); | |
da3c6d4a MS |
582 | /* Reset saved register map. */ |
583 | saved_reg[regno] = regno; | |
c906108c SS |
584 | } |
585 | } | |
da3c6d4a MS |
586 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
587 | sub sp, #simm */ | |
c906108c | 588 | { |
da59e081 JM |
589 | if ((findmask & 1) == 0) /* before push ? */ |
590 | continue; | |
591 | else | |
592 | findmask |= 4; /* add/sub sp found */ | |
593 | ||
c5aa993b | 594 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
da59e081 JM |
595 | if (insn & 0x80) /* is it signed? (==subtracting) */ |
596 | { | |
c3b4394c | 597 | fi->extra_info->frameoffset += offset; |
da59e081 JM |
598 | offset = -offset; |
599 | } | |
c3b4394c | 600 | fi->extra_info->framesize -= offset; |
c906108c SS |
601 | } |
602 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
603 | { | |
da59e081 | 604 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
605 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
606 | /* get scaled offset */ | |
607 | fi->extra_info->frameoffset = (insn & 0xff) << 2; | |
c906108c | 608 | } |
da59e081 | 609 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 610 | { |
da59e081 | 611 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
612 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
613 | fi->extra_info->frameoffset = 0; | |
34e8f22d | 614 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
615 | } |
616 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
617 | { | |
da3c6d4a | 618 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 619 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
c5aa993b | 620 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
621 | } |
622 | else | |
da3c6d4a MS |
623 | /* Something in the prolog that we don't care about or some |
624 | instruction from outside the prolog scheduled here for | |
625 | optimization. */ | |
626 | continue; | |
c906108c SS |
627 | } |
628 | } | |
629 | ||
ed9a39eb JM |
630 | /* Check if prologue for this frame's PC has already been scanned. If |
631 | it has, copy the relevant information about that prologue and | |
c906108c SS |
632 | return non-zero. Otherwise do not copy anything and return zero. |
633 | ||
634 | The information saved in the cache includes: | |
c5aa993b JM |
635 | * the frame register number; |
636 | * the size of the stack frame; | |
637 | * the offsets of saved regs (relative to the old SP); and | |
638 | * the offset from the stack pointer to the frame pointer | |
c906108c | 639 | |
ed9a39eb JM |
640 | The cache contains only one entry, since this is adequate for the |
641 | typical sequence of prologue scan requests we get. When performing | |
642 | a backtrace, GDB will usually ask to scan the same function twice | |
643 | in a row (once to get the frame chain, and once to fill in the | |
644 | extra frame information). */ | |
c906108c SS |
645 | |
646 | static struct frame_info prologue_cache; | |
647 | ||
648 | static int | |
ed9a39eb | 649 | check_prologue_cache (struct frame_info *fi) |
c906108c SS |
650 | { |
651 | int i; | |
652 | ||
653 | if (fi->pc == prologue_cache.pc) | |
654 | { | |
c3b4394c RE |
655 | fi->extra_info->framereg = prologue_cache.extra_info->framereg; |
656 | fi->extra_info->framesize = prologue_cache.extra_info->framesize; | |
657 | fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset; | |
658 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) | |
659 | fi->saved_regs[i] = prologue_cache.saved_regs[i]; | |
c906108c SS |
660 | return 1; |
661 | } | |
662 | else | |
663 | return 0; | |
664 | } | |
665 | ||
666 | ||
ed9a39eb | 667 | /* Copy the prologue information from fi to the prologue cache. */ |
c906108c SS |
668 | |
669 | static void | |
ed9a39eb | 670 | save_prologue_cache (struct frame_info *fi) |
c906108c SS |
671 | { |
672 | int i; | |
673 | ||
c5aa993b | 674 | prologue_cache.pc = fi->pc; |
c3b4394c RE |
675 | prologue_cache.extra_info->framereg = fi->extra_info->framereg; |
676 | prologue_cache.extra_info->framesize = fi->extra_info->framesize; | |
677 | prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset; | |
c5aa993b | 678 | |
c3b4394c RE |
679 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) |
680 | prologue_cache.saved_regs[i] = fi->saved_regs[i]; | |
c906108c SS |
681 | } |
682 | ||
683 | ||
ed9a39eb | 684 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
685 | 1) the size of the stack frame |
686 | 2) which registers are saved on it | |
687 | 3) the offsets of saved regs | |
688 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
689 | This information is stored in the "extra" fields of the frame_info. |
690 | ||
96baa820 JM |
691 | There are two basic forms for the ARM prologue. The fixed argument |
692 | function call will look like: | |
ed9a39eb JM |
693 | |
694 | mov ip, sp | |
695 | stmfd sp!, {fp, ip, lr, pc} | |
696 | sub fp, ip, #4 | |
697 | [sub sp, sp, #4] | |
96baa820 | 698 | |
c906108c | 699 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
700 | IP -> 4 (caller's stack) |
701 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
702 | -4 LR (return address in caller) | |
703 | -8 IP (copy of caller's SP) | |
704 | -12 FP (caller's FP) | |
705 | SP -> -28 Local variables | |
706 | ||
c906108c | 707 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
708 | 28 bytes. The stmfd call can also save any of the vN registers it |
709 | plans to use, which increases the frame size accordingly. | |
710 | ||
711 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
712 | because the ARM Store instructions always store PC + 8 when you read | |
713 | the PC register. | |
ed9a39eb | 714 | |
96baa820 JM |
715 | A variable argument function call will look like: |
716 | ||
ed9a39eb JM |
717 | mov ip, sp |
718 | stmfd sp!, {a1, a2, a3, a4} | |
719 | stmfd sp!, {fp, ip, lr, pc} | |
720 | sub fp, ip, #20 | |
721 | ||
96baa820 | 722 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
723 | IP -> 20 (caller's stack) |
724 | 16 A4 | |
725 | 12 A3 | |
726 | 8 A2 | |
727 | 4 A1 | |
728 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
729 | -4 LR (return address in caller) | |
730 | -8 IP (copy of caller's SP) | |
731 | -12 FP (caller's FP) | |
732 | SP -> -28 Local variables | |
96baa820 JM |
733 | |
734 | The frame size would thus be 48 bytes, and the frame offset would be | |
735 | 28 bytes. | |
736 | ||
737 | There is another potential complication, which is that the optimizer | |
738 | will try to separate the store of fp in the "stmfd" instruction from | |
739 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
740 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
741 | ||
742 | Also, note, the original version of the ARM toolchain claimed that there | |
743 | should be an | |
744 | ||
745 | instruction at the end of the prologue. I have never seen GCC produce | |
746 | this, and the ARM docs don't mention it. We still test for it below in | |
747 | case it happens... | |
ed9a39eb JM |
748 | |
749 | */ | |
c906108c SS |
750 | |
751 | static void | |
ed9a39eb | 752 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
753 | { |
754 | int regno, sp_offset, fp_offset; | |
16a0f3e7 | 755 | LONGEST return_value; |
c906108c SS |
756 | CORE_ADDR prologue_start, prologue_end, current_pc; |
757 | ||
758 | /* Check if this function is already in the cache of frame information. */ | |
759 | if (check_prologue_cache (fi)) | |
760 | return; | |
761 | ||
762 | /* Assume there is no frame until proven otherwise. */ | |
34e8f22d | 763 | fi->extra_info->framereg = ARM_SP_REGNUM; |
c3b4394c RE |
764 | fi->extra_info->framesize = 0; |
765 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
766 | |
767 | /* Check for Thumb prologue. */ | |
768 | if (arm_pc_is_thumb (fi->pc)) | |
769 | { | |
770 | thumb_scan_prologue (fi); | |
771 | save_prologue_cache (fi); | |
772 | return; | |
773 | } | |
774 | ||
775 | /* Find the function prologue. If we can't find the function in | |
776 | the symbol table, peek in the stack frame to find the PC. */ | |
777 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
778 | { | |
2a451106 KB |
779 | /* One way to find the end of the prologue (which works well |
780 | for unoptimized code) is to do the following: | |
781 | ||
782 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
783 | ||
784 | if (sal.line == 0) | |
785 | prologue_end = fi->pc; | |
786 | else if (sal.end < prologue_end) | |
787 | prologue_end = sal.end; | |
788 | ||
789 | This mechanism is very accurate so long as the optimizer | |
790 | doesn't move any instructions from the function body into the | |
791 | prologue. If this happens, sal.end will be the last | |
792 | instruction in the first hunk of prologue code just before | |
793 | the first instruction that the scheduler has moved from | |
794 | the body to the prologue. | |
795 | ||
796 | In order to make sure that we scan all of the prologue | |
797 | instructions, we use a slightly less accurate mechanism which | |
798 | may scan more than necessary. To help compensate for this | |
799 | lack of accuracy, the prologue scanning loop below contains | |
800 | several clauses which'll cause the loop to terminate early if | |
801 | an implausible prologue instruction is encountered. | |
802 | ||
803 | The expression | |
804 | ||
805 | prologue_start + 64 | |
806 | ||
807 | is a suitable endpoint since it accounts for the largest | |
808 | possible prologue plus up to five instructions inserted by | |
809 | the scheduler. */ | |
810 | ||
811 | if (prologue_end > prologue_start + 64) | |
812 | { | |
813 | prologue_end = prologue_start + 64; /* See above. */ | |
814 | } | |
c906108c SS |
815 | } |
816 | else | |
817 | { | |
818 | /* Get address of the stmfd in the prologue of the callee; the saved | |
96baa820 | 819 | PC is the address of the stmfd + 8. */ |
16a0f3e7 EZ |
820 | if (!safe_read_memory_integer (fi->frame, 4, &return_value)) |
821 | return; | |
822 | else | |
823 | { | |
824 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
825 | prologue_end = prologue_start + 64; /* See above. */ | |
826 | } | |
c906108c SS |
827 | } |
828 | ||
829 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 830 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 831 | |
96baa820 JM |
832 | Be careful, however, and if it doesn't look like a prologue, |
833 | don't try to scan it. If, for instance, a frameless function | |
834 | begins with stmfd sp!, then we will tell ourselves there is | |
835 | a frame, which will confuse stack traceback, as well ad"finish" | |
836 | and other operations that rely on a knowledge of the stack | |
837 | traceback. | |
838 | ||
839 | In the APCS, the prologue should start with "mov ip, sp" so | |
d4473757 KB |
840 | if we don't see this as the first insn, we will stop. [Note: |
841 | This doesn't seem to be true any longer, so it's now an optional | |
842 | part of the prologue. - Kevin Buettner, 2001-11-20] */ | |
c906108c SS |
843 | |
844 | sp_offset = fp_offset = 0; | |
c906108c | 845 | |
ed9a39eb JM |
846 | if (read_memory_unsigned_integer (prologue_start, 4) |
847 | == 0xe1a0c00d) /* mov ip, sp */ | |
d4473757 KB |
848 | current_pc = prologue_start + 4; |
849 | else | |
850 | current_pc = prologue_start; | |
851 | ||
852 | for (; current_pc < prologue_end; current_pc += 4) | |
96baa820 | 853 | { |
d4473757 KB |
854 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
855 | ||
856 | if ((insn & 0xffff0000) == 0xe92d0000) | |
857 | /* stmfd sp!, {..., fp, ip, lr, pc} | |
858 | or | |
859 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 860 | { |
d4473757 | 861 | int mask = insn & 0xffff; |
ed9a39eb | 862 | |
d4473757 | 863 | /* Calculate offsets of saved registers. */ |
34e8f22d | 864 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
865 | if (mask & (1 << regno)) |
866 | { | |
867 | sp_offset -= 4; | |
c3b4394c | 868 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
869 | } |
870 | } | |
871 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ | |
872 | { | |
873 | unsigned imm = insn & 0xff; /* immediate value */ | |
874 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
875 | imm = (imm >> rot) | (imm << (32 - rot)); | |
876 | fp_offset = -imm; | |
34e8f22d | 877 | fi->extra_info->framereg = ARM_FP_REGNUM; |
d4473757 KB |
878 | } |
879 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
880 | { | |
881 | unsigned imm = insn & 0xff; /* immediate value */ | |
882 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
883 | imm = (imm >> rot) | (imm << (32 - rot)); | |
884 | sp_offset -= imm; | |
885 | } | |
886 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
887 | { | |
888 | sp_offset -= 12; | |
34e8f22d | 889 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
c3b4394c | 890 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
891 | } |
892 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
893 | { | |
894 | int n_saved_fp_regs; | |
895 | unsigned int fp_start_reg, fp_bound_reg; | |
896 | ||
897 | if ((insn & 0x800) == 0x800) /* N0 is set */ | |
96baa820 | 898 | { |
d4473757 KB |
899 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
900 | n_saved_fp_regs = 3; | |
901 | else | |
902 | n_saved_fp_regs = 1; | |
96baa820 | 903 | } |
d4473757 | 904 | else |
96baa820 | 905 | { |
d4473757 KB |
906 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
907 | n_saved_fp_regs = 2; | |
908 | else | |
909 | n_saved_fp_regs = 4; | |
96baa820 | 910 | } |
d4473757 | 911 | |
34e8f22d | 912 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
913 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
914 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
915 | { |
916 | sp_offset -= 12; | |
c3b4394c | 917 | fi->saved_regs[fp_start_reg++] = sp_offset; |
96baa820 | 918 | } |
c906108c | 919 | } |
d4473757 KB |
920 | else if ((insn & 0xf0000000) != 0xe0000000) |
921 | break; /* Condition not true, exit early */ | |
922 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ | |
923 | break; /* Don't scan past a block load */ | |
924 | else | |
925 | /* The optimizer might shove anything into the prologue, | |
926 | so we just skip what we don't recognize. */ | |
927 | continue; | |
c906108c SS |
928 | } |
929 | ||
930 | /* The frame size is just the negative of the offset (from the original SP) | |
931 | of the last thing thing we pushed on the stack. The frame offset is | |
932 | [new FP] - [new SP]. */ | |
c3b4394c | 933 | fi->extra_info->framesize = -sp_offset; |
34e8f22d | 934 | if (fi->extra_info->framereg == ARM_FP_REGNUM) |
c3b4394c | 935 | fi->extra_info->frameoffset = fp_offset - sp_offset; |
d4473757 | 936 | else |
c3b4394c | 937 | fi->extra_info->frameoffset = 0; |
ed9a39eb | 938 | |
c906108c SS |
939 | save_prologue_cache (fi); |
940 | } | |
941 | ||
ed9a39eb JM |
942 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
943 | One thing we might want to do here is to check REGNUM against the | |
944 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
945 | the stack somewhere. This would provide a graceful failure mode | |
946 | when trying to get the value of caller-saves registers for an inner | |
947 | frame. */ | |
c906108c SS |
948 | |
949 | static CORE_ADDR | |
ed9a39eb | 950 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c SS |
951 | { |
952 | for (; fi; fi = fi->next) | |
c5aa993b | 953 | |
da3c6d4a | 954 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
955 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
956 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); | |
957 | else | |
958 | #endif | |
c3b4394c RE |
959 | if (fi->saved_regs[regnum] != 0) |
960 | return read_memory_integer (fi->saved_regs[regnum], | |
c5aa993b | 961 | REGISTER_RAW_SIZE (regnum)); |
c906108c SS |
962 | return read_register (regnum); |
963 | } | |
148754e5 RE |
964 | /* Function: frame_chain Given a GDB frame, determine the address of |
965 | the calling function's frame. This will be used to create a new | |
966 | GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC | |
967 | will be called for the new frame. For ARM, we save the frame size | |
968 | when we initialize the frame_info. */ | |
c5aa993b | 969 | |
148754e5 | 970 | static CORE_ADDR |
ed9a39eb | 971 | arm_frame_chain (struct frame_info *fi) |
c906108c | 972 | { |
da3c6d4a | 973 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
974 | CORE_ADDR fn_start, callers_pc, fp; |
975 | ||
976 | /* is this a dummy frame? */ | |
977 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
c5aa993b | 978 | return fi->frame; /* dummy frame same as caller's frame */ |
c906108c SS |
979 | |
980 | /* is caller-of-this a dummy frame? */ | |
c5aa993b | 981 | callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */ |
34e8f22d | 982 | fp = arm_find_callers_reg (fi, ARM_FP_REGNUM); |
c5aa993b JM |
983 | if (PC_IN_CALL_DUMMY (callers_pc, fp, fp)) |
984 | return fp; /* dummy frame's frame may bear no relation to ours */ | |
c906108c SS |
985 | |
986 | if (find_pc_partial_function (fi->pc, 0, &fn_start, 0)) | |
987 | if (fn_start == entry_point_address ()) | |
c5aa993b | 988 | return 0; /* in _start fn, don't chain further */ |
c906108c SS |
989 | #endif |
990 | CORE_ADDR caller_pc, fn_start; | |
c3b4394c | 991 | int framereg = fi->extra_info->framereg; |
c906108c SS |
992 | |
993 | if (fi->pc < LOWEST_PC) | |
994 | return 0; | |
995 | ||
996 | /* If the caller is the startup code, we're at the end of the chain. */ | |
997 | caller_pc = FRAME_SAVED_PC (fi); | |
998 | if (find_pc_partial_function (caller_pc, 0, &fn_start, 0)) | |
999 | if (fn_start == entry_point_address ()) | |
1000 | return 0; | |
1001 | ||
1002 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
1003 | the frame register of the caller is different from ours. | |
1004 | So we must scan the prologue of the caller to determine its | |
1005 | frame register number. */ | |
c3b4394c RE |
1006 | /* XXX Fixme, we should try to do this without creating a temporary |
1007 | caller_fi. */ | |
c906108c SS |
1008 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) |
1009 | { | |
c3b4394c RE |
1010 | struct frame_info caller_fi; |
1011 | struct cleanup *old_chain; | |
1012 | ||
1013 | /* Create a temporary frame suitable for scanning the caller's | |
1014 | prologue. (Ugh.) */ | |
c5aa993b | 1015 | memset (&caller_fi, 0, sizeof (caller_fi)); |
c3b4394c RE |
1016 | caller_fi.extra_info = (struct frame_extra_info *) |
1017 | xcalloc (1, sizeof (struct frame_extra_info)); | |
1018 | old_chain = make_cleanup (xfree, caller_fi.extra_info); | |
1019 | caller_fi.saved_regs = (CORE_ADDR *) | |
1020 | xcalloc (1, SIZEOF_FRAME_SAVED_REGS); | |
1021 | make_cleanup (xfree, caller_fi.saved_regs); | |
1022 | ||
1023 | /* Now, scan the prologue and obtain the frame register. */ | |
c906108c | 1024 | caller_fi.pc = caller_pc; |
c5aa993b | 1025 | arm_scan_prologue (&caller_fi); |
c3b4394c RE |
1026 | framereg = caller_fi.extra_info->framereg; |
1027 | ||
1028 | /* Deallocate the storage associated with the temporary frame | |
1029 | created above. */ | |
1030 | do_cleanups (old_chain); | |
c906108c SS |
1031 | } |
1032 | ||
1033 | /* If the caller used a frame register, return its value. | |
1034 | Otherwise, return the caller's stack pointer. */ | |
34e8f22d | 1035 | if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM) |
c906108c SS |
1036 | return arm_find_callers_reg (fi, framereg); |
1037 | else | |
c3b4394c | 1038 | return fi->frame + fi->extra_info->framesize; |
c906108c SS |
1039 | } |
1040 | ||
ed9a39eb JM |
1041 | /* This function actually figures out the frame address for a given pc |
1042 | and sp. This is tricky because we sometimes don't use an explicit | |
1043 | frame pointer, and the previous stack pointer isn't necessarily | |
1044 | recorded on the stack. The only reliable way to get this info is | |
1045 | to examine the prologue. FROMLEAF is a little confusing, it means | |
1046 | this is the next frame up the chain AFTER a frameless function. If | |
1047 | this is true, then the frame value for this frame is still in the | |
1048 | fp register. */ | |
c906108c | 1049 | |
148754e5 | 1050 | static void |
ed9a39eb | 1051 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1052 | { |
1053 | int reg; | |
f079148d | 1054 | CORE_ADDR sp; |
c906108c | 1055 | |
c3b4394c RE |
1056 | if (fi->saved_regs == NULL) |
1057 | frame_saved_regs_zalloc (fi); | |
1058 | ||
1059 | fi->extra_info = (struct frame_extra_info *) | |
1060 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1061 | ||
1062 | fi->extra_info->framesize = 0; | |
1063 | fi->extra_info->frameoffset = 0; | |
1064 | fi->extra_info->framereg = 0; | |
1065 | ||
c906108c SS |
1066 | if (fi->next) |
1067 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1068 | ||
c3b4394c | 1069 | memset (fi->saved_regs, '\000', sizeof fi->saved_regs); |
c906108c | 1070 | |
da3c6d4a | 1071 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
1072 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
1073 | { | |
da3c6d4a MS |
1074 | /* We need to setup fi->frame here because run_stack_dummy gets |
1075 | it wrong by assuming it's always FP. */ | |
34e8f22d RE |
1076 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, |
1077 | ARM_SP_REGNUM); | |
c3b4394c RE |
1078 | fi->extra_info->framesize = 0; |
1079 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
1080 | return; |
1081 | } | |
c5aa993b | 1082 | else |
c906108c | 1083 | #endif |
2a451106 | 1084 | |
da3c6d4a MS |
1085 | /* Compute stack pointer for this frame. We use this value for both |
1086 | the sigtramp and call dummy cases. */ | |
f079148d KB |
1087 | if (!fi->next) |
1088 | sp = read_sp(); | |
1089 | else | |
c3b4394c RE |
1090 | sp = (fi->next->frame - fi->next->extra_info->frameoffset |
1091 | + fi->next->extra_info->framesize); | |
f079148d | 1092 | |
2a451106 KB |
1093 | /* Determine whether or not we're in a sigtramp frame. |
1094 | Unfortunately, it isn't sufficient to test | |
1095 | fi->signal_handler_caller because this value is sometimes set | |
1096 | after invoking INIT_EXTRA_FRAME_INFO. So we test *both* | |
1097 | fi->signal_handler_caller and IN_SIGTRAMP to determine if we need | |
1098 | to use the sigcontext addresses for the saved registers. | |
1099 | ||
1100 | Note: If an ARM IN_SIGTRAMP method ever needs to compare against | |
1101 | the name of the function, the code below will have to be changed | |
1102 | to first fetch the name of the function and then pass this name | |
f079148d | 1103 | to IN_SIGTRAMP. */ |
2a451106 | 1104 | |
3bb04bdd | 1105 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
dd96c05b | 1106 | && (fi->signal_handler_caller || IN_SIGTRAMP (fi->pc, (char *)0))) |
2a451106 | 1107 | { |
2a451106 | 1108 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c | 1109 | fi->saved_regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg); |
2a451106 KB |
1110 | |
1111 | /* FIXME: What about thumb mode? */ | |
34e8f22d | 1112 | fi->extra_info->framereg = ARM_SP_REGNUM; |
c3b4394c RE |
1113 | fi->frame = |
1114 | read_memory_integer (fi->saved_regs[fi->extra_info->framereg], | |
1115 | REGISTER_RAW_SIZE (fi->extra_info->framereg)); | |
1116 | fi->extra_info->framesize = 0; | |
1117 | fi->extra_info->frameoffset = 0; | |
2a451106 KB |
1118 | |
1119 | } | |
f079148d KB |
1120 | else if (PC_IN_CALL_DUMMY (fi->pc, sp, fi->frame)) |
1121 | { | |
1122 | CORE_ADDR rp; | |
1123 | CORE_ADDR callers_sp; | |
1124 | ||
1125 | /* Set rp point at the high end of the saved registers. */ | |
1126 | rp = fi->frame - REGISTER_SIZE; | |
1127 | ||
1128 | /* Fill in addresses of saved registers. */ | |
34e8f22d RE |
1129 | fi->saved_regs[ARM_PS_REGNUM] = rp; |
1130 | rp -= REGISTER_RAW_SIZE (ARM_PS_REGNUM); | |
1131 | for (reg = ARM_PC_REGNUM; reg >= 0; reg--) | |
f079148d | 1132 | { |
c3b4394c | 1133 | fi->saved_regs[reg] = rp; |
f079148d KB |
1134 | rp -= REGISTER_RAW_SIZE (reg); |
1135 | } | |
1136 | ||
34e8f22d RE |
1137 | callers_sp = read_memory_integer (fi->saved_regs[ARM_SP_REGNUM], |
1138 | REGISTER_RAW_SIZE (ARM_SP_REGNUM)); | |
1139 | fi->extra_info->framereg = ARM_FP_REGNUM; | |
c3b4394c RE |
1140 | fi->extra_info->framesize = callers_sp - sp; |
1141 | fi->extra_info->frameoffset = fi->frame - sp; | |
f079148d | 1142 | } |
2a451106 | 1143 | else |
c906108c SS |
1144 | { |
1145 | arm_scan_prologue (fi); | |
1146 | ||
104c1213 JM |
1147 | if (!fi->next) |
1148 | /* this is the innermost frame? */ | |
c3b4394c | 1149 | fi->frame = read_register (fi->extra_info->framereg); |
34e8f22d | 1150 | else if (fi->extra_info->framereg == ARM_FP_REGNUM |
c3b4394c | 1151 | || fi->extra_info->framereg == THUMB_FP_REGNUM) |
ed9a39eb JM |
1152 | { |
1153 | /* not the innermost frame */ | |
1154 | /* If we have an FP, the callee saved it. */ | |
c3b4394c | 1155 | if (fi->next->saved_regs[fi->extra_info->framereg] != 0) |
ed9a39eb | 1156 | fi->frame = |
c3b4394c RE |
1157 | read_memory_integer (fi->next |
1158 | ->saved_regs[fi->extra_info->framereg], 4); | |
ed9a39eb JM |
1159 | else if (fromleaf) |
1160 | /* If we were called by a frameless fn. then our frame is | |
1161 | still in the frame pointer register on the board... */ | |
1162 | fi->frame = read_fp (); | |
1163 | } | |
c906108c | 1164 | |
ed9a39eb JM |
1165 | /* Calculate actual addresses of saved registers using offsets |
1166 | determined by arm_scan_prologue. */ | |
c906108c | 1167 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c RE |
1168 | if (fi->saved_regs[reg] != 0) |
1169 | fi->saved_regs[reg] += (fi->frame + fi->extra_info->framesize | |
1170 | - fi->extra_info->frameoffset); | |
c906108c SS |
1171 | } |
1172 | } | |
1173 | ||
1174 | ||
34e8f22d | 1175 | /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM |
ed9a39eb JM |
1176 | is saved in the stack anywhere, otherwise we get it from the |
1177 | registers. | |
c906108c SS |
1178 | |
1179 | The old definition of this function was a macro: | |
c5aa993b | 1180 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1181 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c | 1182 | |
148754e5 | 1183 | static CORE_ADDR |
ed9a39eb | 1184 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1185 | { |
da3c6d4a | 1186 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c | 1187 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
34e8f22d | 1188 | return generic_read_register_dummy (fi->pc, fi->frame, ARM_PC_REGNUM); |
c906108c SS |
1189 | else |
1190 | #endif | |
c3b4394c RE |
1191 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame - fi->extra_info->frameoffset, |
1192 | fi->frame)) | |
f079148d | 1193 | { |
34e8f22d RE |
1194 | return read_memory_integer (fi->saved_regs[ARM_PC_REGNUM], |
1195 | REGISTER_RAW_SIZE (ARM_PC_REGNUM)); | |
f079148d KB |
1196 | } |
1197 | else | |
c906108c | 1198 | { |
34e8f22d | 1199 | CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM); |
c906108c SS |
1200 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
1201 | } | |
1202 | } | |
1203 | ||
c906108c SS |
1204 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1205 | Examine the Program Status Register to decide which state we're in. */ | |
1206 | ||
148754e5 RE |
1207 | static CORE_ADDR |
1208 | arm_read_fp (void) | |
c906108c | 1209 | { |
34e8f22d | 1210 | if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ |
c906108c SS |
1211 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ |
1212 | else | |
34e8f22d | 1213 | return read_register (ARM_FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1214 | } |
1215 | ||
148754e5 RE |
1216 | /* Store into a struct frame_saved_regs the addresses of the saved |
1217 | registers of frame described by FRAME_INFO. This includes special | |
1218 | registers such as PC and FP saved in special ways in the stack | |
1219 | frame. SP is even more special: the address we return for it IS | |
1220 | the sp for the next frame. */ | |
c906108c | 1221 | |
148754e5 | 1222 | static void |
c3b4394c | 1223 | arm_frame_init_saved_regs (struct frame_info *fip) |
c906108c | 1224 | { |
c3b4394c RE |
1225 | |
1226 | if (fip->saved_regs) | |
1227 | return; | |
1228 | ||
1229 | arm_init_extra_frame_info (0, fip); | |
c906108c SS |
1230 | } |
1231 | ||
148754e5 RE |
1232 | /* Push an empty stack frame, to record the current PC, etc. */ |
1233 | ||
1234 | static void | |
ed9a39eb | 1235 | arm_push_dummy_frame (void) |
c906108c | 1236 | { |
34e8f22d | 1237 | CORE_ADDR old_sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1238 | CORE_ADDR sp = old_sp; |
1239 | CORE_ADDR fp, prologue_start; | |
1240 | int regnum; | |
1241 | ||
1242 | /* Push the two dummy prologue instructions in reverse order, | |
1243 | so that they'll be in the correct low-to-high order in memory. */ | |
1244 | /* sub fp, ip, #4 */ | |
1245 | sp = push_word (sp, 0xe24cb004); | |
1246 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1247 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1248 | ||
ed9a39eb JM |
1249 | /* Push a pointer to the dummy prologue + 12, because when stm |
1250 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1251 | instruction itself plus 12. */ |
1252 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1253 | |
f079148d | 1254 | /* Push the processor status. */ |
34e8f22d | 1255 | sp = push_word (sp, read_register (ARM_PS_REGNUM)); |
f079148d KB |
1256 | |
1257 | /* Push all 16 registers starting with r15. */ | |
34e8f22d | 1258 | for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--) |
c906108c | 1259 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1260 | |
f079148d | 1261 | /* Update fp (for both Thumb and ARM) and sp. */ |
34e8f22d | 1262 | write_register (ARM_FP_REGNUM, fp); |
c906108c | 1263 | write_register (THUMB_FP_REGNUM, fp); |
34e8f22d | 1264 | write_register (ARM_SP_REGNUM, sp); |
c906108c SS |
1265 | } |
1266 | ||
6eb69eab RE |
1267 | /* CALL_DUMMY_WORDS: |
1268 | This sequence of words is the instructions | |
1269 | ||
1270 | mov lr,pc | |
1271 | mov pc,r4 | |
1272 | illegal | |
1273 | ||
1274 | Note this is 12 bytes. */ | |
1275 | ||
34e8f22d | 1276 | static LONGEST arm_call_dummy_words[] = |
6eb69eab RE |
1277 | { |
1278 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe | |
1279 | }; | |
1280 | ||
3fb4b924 RE |
1281 | /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy |
1282 | breakpoint to the proper address in the call dummy, so that | |
1283 | `finish' after a stop in a call dummy works. | |
1284 | ||
d7b486e7 RE |
1285 | FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an |
1286 | optimal solution, but the call to arm_fix_call_dummy is immediately | |
1287 | followed by a call to run_stack_dummy, which is the only function | |
1288 | where call_dummy_breakpoint_offset is actually used. */ | |
3fb4b924 RE |
1289 | |
1290 | ||
1291 | static void | |
1292 | arm_set_call_dummy_breakpoint_offset (void) | |
1293 | { | |
1294 | if (caller_is_thumb) | |
1295 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4); | |
1296 | else | |
1297 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8); | |
1298 | } | |
1299 | ||
c906108c | 1300 | /* Fix up the call dummy, based on whether the processor is currently |
ed9a39eb JM |
1301 | in Thumb or ARM mode, and whether the target function is Thumb or |
1302 | ARM. There are three different situations requiring three | |
c906108c SS |
1303 | different dummies: |
1304 | ||
1305 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1306 | been copied into the dummy parameter to this function. |
c906108c | 1307 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1308 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1309 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1310 | works for calling both ARM and Thumb functions. |
c906108c | 1311 | |
ed9a39eb JM |
1312 | All three call dummies expect to receive the target function |
1313 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c | 1314 | |
34e8f22d | 1315 | static void |
ed9a39eb | 1316 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1317 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1318 | { |
1319 | static short thumb_dummy[4] = | |
1320 | { | |
c5aa993b JM |
1321 | 0xf000, 0xf801, /* bl label */ |
1322 | 0xdf18, /* swi 24 */ | |
1323 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1324 | }; |
1325 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1326 | ||
1327 | /* Set flag indicating whether the current PC is in a Thumb function. */ | |
c5aa993b | 1328 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
3fb4b924 | 1329 | arm_set_call_dummy_breakpoint_offset (); |
c906108c | 1330 | |
ed9a39eb JM |
1331 | /* If the target function is Thumb, set the low bit of the function |
1332 | address. And if the CPU is currently in ARM mode, patch the | |
1333 | second instruction of call dummy to use a BX instruction to | |
1334 | switch to Thumb mode. */ | |
c906108c SS |
1335 | target_is_thumb = arm_pc_is_thumb (fun); |
1336 | if (target_is_thumb) | |
1337 | { | |
1338 | fun |= 1; | |
1339 | if (!caller_is_thumb) | |
1340 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1341 | } | |
1342 | ||
1343 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1344 | instead of the ARM one that's already been copied. This will | |
1345 | work for both Thumb and ARM target functions. */ | |
1346 | if (caller_is_thumb) | |
1347 | { | |
1348 | int i; | |
1349 | char *p = dummy; | |
1350 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1351 | ||
1352 | for (i = 0; i < len; i++) | |
1353 | { | |
1354 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1355 | p += sizeof (thumb_dummy[0]); | |
1356 | } | |
1357 | } | |
1358 | ||
ed9a39eb JM |
1359 | /* Put the target address in r4; the call dummy will copy this to |
1360 | the PC. */ | |
c906108c SS |
1361 | write_register (4, fun); |
1362 | } | |
1363 | ||
ed9a39eb JM |
1364 | /* Note: ScottB |
1365 | ||
1366 | This function does not support passing parameters using the FPA | |
1367 | variant of the APCS. It passes any floating point arguments in the | |
1368 | general registers and/or on the stack. */ | |
c906108c | 1369 | |
39bbf761 | 1370 | static CORE_ADDR |
ea7c478f | 1371 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
ed9a39eb | 1372 | int struct_return, CORE_ADDR struct_addr) |
c906108c | 1373 | { |
ed9a39eb JM |
1374 | char *fp; |
1375 | int argnum, argreg, nstack_size; | |
1376 | ||
1377 | /* Walk through the list of args and determine how large a temporary | |
1378 | stack is required. Need to take care here as structs may be | |
1379 | passed on the stack, and we have to to push them. */ | |
1380 | nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */ | |
1381 | if (struct_return) /* The struct address goes in A1. */ | |
1382 | nstack_size += REGISTER_SIZE; | |
1383 | ||
1384 | /* Walk through the arguments and add their size to nstack_size. */ | |
1385 | for (argnum = 0; argnum < nargs; argnum++) | |
c5aa993b | 1386 | { |
c906108c | 1387 | int len; |
ed9a39eb JM |
1388 | struct type *arg_type; |
1389 | ||
1390 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1391 | len = TYPE_LENGTH (arg_type); | |
c906108c | 1392 | |
6b230f1b | 1393 | nstack_size += len; |
ed9a39eb | 1394 | } |
c906108c | 1395 | |
ed9a39eb JM |
1396 | /* Allocate room on the stack, and initialize our stack frame |
1397 | pointer. */ | |
1398 | fp = NULL; | |
1399 | if (nstack_size > 0) | |
1400 | { | |
1401 | sp -= nstack_size; | |
1402 | fp = (char *) sp; | |
1403 | } | |
1404 | ||
1405 | /* Initialize the integer argument register pointer. */ | |
34e8f22d | 1406 | argreg = ARM_A1_REGNUM; |
c906108c | 1407 | |
ed9a39eb JM |
1408 | /* The struct_return pointer occupies the first parameter passing |
1409 | register. */ | |
c906108c | 1410 | if (struct_return) |
c5aa993b | 1411 | write_register (argreg++, struct_addr); |
c906108c | 1412 | |
ed9a39eb JM |
1413 | /* Process arguments from left to right. Store as many as allowed |
1414 | in the parameter passing registers (A1-A4), and save the rest on | |
1415 | the temporary stack. */ | |
c5aa993b | 1416 | for (argnum = 0; argnum < nargs; argnum++) |
c906108c | 1417 | { |
ed9a39eb | 1418 | int len; |
c5aa993b | 1419 | char *val; |
c5aa993b | 1420 | CORE_ADDR regval; |
ed9a39eb JM |
1421 | enum type_code typecode; |
1422 | struct type *arg_type, *target_type; | |
1423 | ||
1424 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1425 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1426 | len = TYPE_LENGTH (arg_type); | |
1427 | typecode = TYPE_CODE (arg_type); | |
1428 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1429 | ||
da59e081 JM |
1430 | #if 1 |
1431 | /* I don't know why this code was disable. The only logical use | |
1432 | for a function pointer is to call that function, so setting | |
1433 | the mode bit is perfectly fine. FN */ | |
ed9a39eb | 1434 | /* If the argument is a pointer to a function, and it is a Thumb |
c906108c | 1435 | function, set the low bit of the pointer. */ |
ed9a39eb JM |
1436 | if (TYPE_CODE_PTR == typecode |
1437 | && NULL != target_type | |
1438 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1439 | { |
ed9a39eb | 1440 | CORE_ADDR regval = extract_address (val, len); |
c906108c SS |
1441 | if (arm_pc_is_thumb (regval)) |
1442 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1443 | } | |
c906108c | 1444 | #endif |
ed9a39eb JM |
1445 | /* Copy the argument to general registers or the stack in |
1446 | register-sized pieces. Large arguments are split between | |
1447 | registers and stack. */ | |
1448 | while (len > 0) | |
c906108c | 1449 | { |
ed9a39eb JM |
1450 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1451 | ||
1452 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
c906108c | 1453 | { |
ed9a39eb JM |
1454 | /* It's an argument being passed in a general register. */ |
1455 | regval = extract_address (val, partial_len); | |
1456 | write_register (argreg++, regval); | |
c906108c | 1457 | } |
ed9a39eb JM |
1458 | else |
1459 | { | |
1460 | /* Push the arguments onto the stack. */ | |
1461 | write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE); | |
1462 | fp += REGISTER_SIZE; | |
1463 | } | |
1464 | ||
1465 | len -= partial_len; | |
1466 | val += partial_len; | |
c906108c SS |
1467 | } |
1468 | } | |
c906108c SS |
1469 | |
1470 | /* Return adjusted stack pointer. */ | |
1471 | return sp; | |
1472 | } | |
1473 | ||
da3c6d4a MS |
1474 | /* Pop the current frame. So long as the frame info has been |
1475 | initialized properly (see arm_init_extra_frame_info), this code | |
1476 | works for dummy frames as well as regular frames. I.e, there's no | |
1477 | need to have a special case for dummy frames. */ | |
148754e5 | 1478 | static void |
ed9a39eb | 1479 | arm_pop_frame (void) |
c906108c | 1480 | { |
c906108c | 1481 | int regnum; |
8b93c638 | 1482 | struct frame_info *frame = get_current_frame (); |
c3b4394c RE |
1483 | CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset |
1484 | + frame->extra_info->framesize); | |
c906108c | 1485 | |
f079148d | 1486 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
c3b4394c | 1487 | if (frame->saved_regs[regnum] != 0) |
f079148d | 1488 | write_register (regnum, |
c3b4394c | 1489 | read_memory_integer (frame->saved_regs[regnum], |
f079148d | 1490 | REGISTER_RAW_SIZE (regnum))); |
8b93c638 | 1491 | |
34e8f22d RE |
1492 | write_register (ARM_PC_REGNUM, FRAME_SAVED_PC (frame)); |
1493 | write_register (ARM_SP_REGNUM, old_SP); | |
c906108c SS |
1494 | |
1495 | flush_cached_frames (); | |
1496 | } | |
1497 | ||
1498 | static void | |
ed9a39eb | 1499 | print_fpu_flags (int flags) |
c906108c | 1500 | { |
c5aa993b JM |
1501 | if (flags & (1 << 0)) |
1502 | fputs ("IVO ", stdout); | |
1503 | if (flags & (1 << 1)) | |
1504 | fputs ("DVZ ", stdout); | |
1505 | if (flags & (1 << 2)) | |
1506 | fputs ("OFL ", stdout); | |
1507 | if (flags & (1 << 3)) | |
1508 | fputs ("UFL ", stdout); | |
1509 | if (flags & (1 << 4)) | |
1510 | fputs ("INX ", stdout); | |
1511 | putchar ('\n'); | |
c906108c SS |
1512 | } |
1513 | ||
5e74b15c RE |
1514 | /* Print interesting information about the floating point processor |
1515 | (if present) or emulator. */ | |
34e8f22d | 1516 | static void |
5e74b15c | 1517 | arm_print_float_info (void) |
c906108c | 1518 | { |
34e8f22d | 1519 | register unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1520 | int type; |
1521 | ||
1522 | type = (status >> 24) & 127; | |
1523 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1524 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1525 | type); |
1526 | fputs ("mask: ", stdout); | |
1527 | print_fpu_flags (status >> 16); | |
1528 | fputs ("flags: ", stdout); | |
1529 | print_fpu_flags (status); | |
c906108c SS |
1530 | } |
1531 | ||
34e8f22d RE |
1532 | /* Return the GDB type object for the "standard" data type of data in |
1533 | register N. */ | |
1534 | ||
1535 | static struct type * | |
032758dc AC |
1536 | arm_register_type (int regnum) |
1537 | { | |
34e8f22d | 1538 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1539 | { |
d7449b42 | 1540 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1541 | return builtin_type_arm_ext_big; |
1542 | else | |
1543 | return builtin_type_arm_ext_littlebyte_bigword; | |
1544 | } | |
1545 | else | |
1546 | return builtin_type_int32; | |
1547 | } | |
1548 | ||
34e8f22d RE |
1549 | /* Index within `registers' of the first byte of the space for |
1550 | register N. */ | |
1551 | ||
1552 | static int | |
1553 | arm_register_byte (int regnum) | |
1554 | { | |
1555 | if (regnum < ARM_F0_REGNUM) | |
1556 | return regnum * INT_REGISTER_RAW_SIZE; | |
1557 | else if (regnum < ARM_PS_REGNUM) | |
1558 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1559 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE); | |
1560 | else | |
1561 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1562 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
1563 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); | |
1564 | } | |
1565 | ||
1566 | /* Number of bytes of storage in the actual machine representation for | |
1567 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
1568 | 12 bytes in length. */ | |
1569 | ||
1570 | static int | |
1571 | arm_register_raw_size (int regnum) | |
1572 | { | |
1573 | if (regnum < ARM_F0_REGNUM) | |
1574 | return INT_REGISTER_RAW_SIZE; | |
1575 | else if (regnum < ARM_FPS_REGNUM) | |
1576 | return FP_REGISTER_RAW_SIZE; | |
1577 | else | |
1578 | return STATUS_REGISTER_SIZE; | |
1579 | } | |
1580 | ||
1581 | /* Number of bytes of storage in a program's representation | |
1582 | for register N. */ | |
1583 | static int | |
1584 | arm_register_virtual_size (int regnum) | |
1585 | { | |
1586 | if (regnum < ARM_F0_REGNUM) | |
1587 | return INT_REGISTER_VIRTUAL_SIZE; | |
1588 | else if (regnum < ARM_FPS_REGNUM) | |
1589 | return FP_REGISTER_VIRTUAL_SIZE; | |
1590 | else | |
1591 | return STATUS_REGISTER_SIZE; | |
1592 | } | |
1593 | ||
1594 | ||
a37b3cc0 AC |
1595 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1596 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1597 | It is thought that this is is the floating-point register format on | |
1598 | little-endian systems. */ | |
c906108c | 1599 | |
ed9a39eb JM |
1600 | static void |
1601 | convert_from_extended (void *ptr, void *dbl) | |
c906108c | 1602 | { |
a37b3cc0 | 1603 | DOUBLEST d; |
d7449b42 | 1604 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1605 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1606 | else | |
1607 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1608 | ptr, &d); | |
1609 | floatformat_from_doublest (TARGET_DOUBLE_FORMAT, &d, dbl); | |
c906108c SS |
1610 | } |
1611 | ||
34e8f22d | 1612 | static void |
ed9a39eb | 1613 | convert_to_extended (void *dbl, void *ptr) |
c906108c | 1614 | { |
a37b3cc0 AC |
1615 | DOUBLEST d; |
1616 | floatformat_to_doublest (TARGET_DOUBLE_FORMAT, ptr, &d); | |
d7449b42 | 1617 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1618 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1619 | else | |
1620 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1621 | &d, dbl); | |
c906108c | 1622 | } |
ed9a39eb | 1623 | |
c906108c | 1624 | static int |
ed9a39eb | 1625 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1626 | { |
1627 | if (cond == INST_AL || cond == INST_NV) | |
1628 | return 1; | |
1629 | ||
1630 | switch (cond) | |
1631 | { | |
1632 | case INST_EQ: | |
1633 | return ((status_reg & FLAG_Z) != 0); | |
1634 | case INST_NE: | |
1635 | return ((status_reg & FLAG_Z) == 0); | |
1636 | case INST_CS: | |
1637 | return ((status_reg & FLAG_C) != 0); | |
1638 | case INST_CC: | |
1639 | return ((status_reg & FLAG_C) == 0); | |
1640 | case INST_MI: | |
1641 | return ((status_reg & FLAG_N) != 0); | |
1642 | case INST_PL: | |
1643 | return ((status_reg & FLAG_N) == 0); | |
1644 | case INST_VS: | |
1645 | return ((status_reg & FLAG_V) != 0); | |
1646 | case INST_VC: | |
1647 | return ((status_reg & FLAG_V) == 0); | |
1648 | case INST_HI: | |
1649 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1650 | case INST_LS: | |
1651 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1652 | case INST_GE: | |
1653 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1654 | case INST_LT: | |
1655 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1656 | case INST_GT: | |
1657 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1658 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1659 | case INST_LE: |
1660 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1661 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1662 | } |
1663 | return 1; | |
1664 | } | |
1665 | ||
9512d7fd | 1666 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1667 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1668 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1669 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1670 | #define sbits(obj,st,fn) \ | |
1671 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1672 | #define BranchDest(addr,instr) \ | |
1673 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1674 | #define ARM_PC_32 1 | |
1675 | ||
1676 | static unsigned long | |
ed9a39eb JM |
1677 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1678 | unsigned long status_reg) | |
c906108c SS |
1679 | { |
1680 | unsigned long res, shift; | |
1681 | int rm = bits (inst, 0, 3); | |
1682 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1683 | |
1684 | if (bit (inst, 4)) | |
c906108c SS |
1685 | { |
1686 | int rs = bits (inst, 8, 11); | |
1687 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1688 | } | |
1689 | else | |
1690 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1691 | |
1692 | res = (rm == 15 | |
c906108c | 1693 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1694 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1695 | : read_register (rm)); |
1696 | ||
1697 | switch (shifttype) | |
1698 | { | |
c5aa993b | 1699 | case 0: /* LSL */ |
c906108c SS |
1700 | res = shift >= 32 ? 0 : res << shift; |
1701 | break; | |
c5aa993b JM |
1702 | |
1703 | case 1: /* LSR */ | |
c906108c SS |
1704 | res = shift >= 32 ? 0 : res >> shift; |
1705 | break; | |
1706 | ||
c5aa993b JM |
1707 | case 2: /* ASR */ |
1708 | if (shift >= 32) | |
1709 | shift = 31; | |
c906108c SS |
1710 | res = ((res & 0x80000000L) |
1711 | ? ~((~res) >> shift) : res >> shift); | |
1712 | break; | |
1713 | ||
c5aa993b | 1714 | case 3: /* ROR/RRX */ |
c906108c SS |
1715 | shift &= 31; |
1716 | if (shift == 0) | |
1717 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1718 | else | |
c5aa993b | 1719 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1720 | break; |
1721 | } | |
1722 | ||
1723 | return res & 0xffffffff; | |
1724 | } | |
1725 | ||
c906108c SS |
1726 | /* Return number of 1-bits in VAL. */ |
1727 | ||
1728 | static int | |
ed9a39eb | 1729 | bitcount (unsigned long val) |
c906108c SS |
1730 | { |
1731 | int nbits; | |
1732 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1733 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1734 | return nbits; |
1735 | } | |
1736 | ||
34e8f22d | 1737 | CORE_ADDR |
ed9a39eb | 1738 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1739 | { |
c5aa993b | 1740 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1741 | unsigned short inst1 = read_memory_integer (pc, 2); |
c5aa993b | 1742 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1743 | unsigned long offset; |
1744 | ||
1745 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1746 | { | |
1747 | CORE_ADDR sp; | |
1748 | ||
1749 | /* Fetch the saved PC from the stack. It's stored above | |
1750 | all of the other registers. */ | |
1751 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
34e8f22d | 1752 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1753 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1754 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1755 | if (nextpc == pc) | |
1756 | error ("Infinite loop detected"); | |
1757 | } | |
1758 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1759 | { | |
34e8f22d | 1760 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1761 | unsigned long cond = bits (inst1, 8, 11); |
c906108c SS |
1762 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
1763 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); | |
1764 | } | |
1765 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1766 | { | |
1767 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1768 | } | |
1769 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1770 | { | |
1771 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1772 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1773 | nextpc = pc_val + offset; |
1774 | } | |
1775 | ||
1776 | return nextpc; | |
1777 | } | |
1778 | ||
34e8f22d | 1779 | CORE_ADDR |
ed9a39eb | 1780 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1781 | { |
1782 | unsigned long pc_val; | |
1783 | unsigned long this_instr; | |
1784 | unsigned long status; | |
1785 | CORE_ADDR nextpc; | |
1786 | ||
1787 | if (arm_pc_is_thumb (pc)) | |
1788 | return thumb_get_next_pc (pc); | |
1789 | ||
1790 | pc_val = (unsigned long) pc; | |
1791 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1792 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1793 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1794 | |
1795 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1796 | { | |
1797 | switch (bits (this_instr, 24, 27)) | |
1798 | { | |
c5aa993b JM |
1799 | case 0x0: |
1800 | case 0x1: /* data processing */ | |
1801 | case 0x2: | |
1802 | case 0x3: | |
c906108c SS |
1803 | { |
1804 | unsigned long operand1, operand2, result = 0; | |
1805 | unsigned long rn; | |
1806 | int c; | |
c5aa993b | 1807 | |
c906108c SS |
1808 | if (bits (this_instr, 12, 15) != 15) |
1809 | break; | |
1810 | ||
1811 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1812 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1813 | error ("Illegal update to pc in instruction"); |
1814 | ||
1815 | /* Multiply into PC */ | |
1816 | c = (status & FLAG_C) ? 1 : 0; | |
1817 | rn = bits (this_instr, 16, 19); | |
1818 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1819 | |
c906108c SS |
1820 | if (bit (this_instr, 25)) |
1821 | { | |
1822 | unsigned long immval = bits (this_instr, 0, 7); | |
1823 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1824 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1825 | & 0xffffffff; | |
c906108c | 1826 | } |
c5aa993b | 1827 | else /* operand 2 is a shifted register */ |
c906108c | 1828 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1829 | |
c906108c SS |
1830 | switch (bits (this_instr, 21, 24)) |
1831 | { | |
c5aa993b | 1832 | case 0x0: /*and */ |
c906108c SS |
1833 | result = operand1 & operand2; |
1834 | break; | |
1835 | ||
c5aa993b | 1836 | case 0x1: /*eor */ |
c906108c SS |
1837 | result = operand1 ^ operand2; |
1838 | break; | |
1839 | ||
c5aa993b | 1840 | case 0x2: /*sub */ |
c906108c SS |
1841 | result = operand1 - operand2; |
1842 | break; | |
1843 | ||
c5aa993b | 1844 | case 0x3: /*rsb */ |
c906108c SS |
1845 | result = operand2 - operand1; |
1846 | break; | |
1847 | ||
c5aa993b | 1848 | case 0x4: /*add */ |
c906108c SS |
1849 | result = operand1 + operand2; |
1850 | break; | |
1851 | ||
c5aa993b | 1852 | case 0x5: /*adc */ |
c906108c SS |
1853 | result = operand1 + operand2 + c; |
1854 | break; | |
1855 | ||
c5aa993b | 1856 | case 0x6: /*sbc */ |
c906108c SS |
1857 | result = operand1 - operand2 + c; |
1858 | break; | |
1859 | ||
c5aa993b | 1860 | case 0x7: /*rsc */ |
c906108c SS |
1861 | result = operand2 - operand1 + c; |
1862 | break; | |
1863 | ||
c5aa993b JM |
1864 | case 0x8: |
1865 | case 0x9: | |
1866 | case 0xa: | |
1867 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1868 | result = (unsigned long) nextpc; |
1869 | break; | |
1870 | ||
c5aa993b | 1871 | case 0xc: /*orr */ |
c906108c SS |
1872 | result = operand1 | operand2; |
1873 | break; | |
1874 | ||
c5aa993b | 1875 | case 0xd: /*mov */ |
c906108c SS |
1876 | /* Always step into a function. */ |
1877 | result = operand2; | |
c5aa993b | 1878 | break; |
c906108c | 1879 | |
c5aa993b | 1880 | case 0xe: /*bic */ |
c906108c SS |
1881 | result = operand1 & ~operand2; |
1882 | break; | |
1883 | ||
c5aa993b | 1884 | case 0xf: /*mvn */ |
c906108c SS |
1885 | result = ~operand2; |
1886 | break; | |
1887 | } | |
1888 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1889 | ||
1890 | if (nextpc == pc) | |
1891 | error ("Infinite loop detected"); | |
1892 | break; | |
1893 | } | |
c5aa993b JM |
1894 | |
1895 | case 0x4: | |
1896 | case 0x5: /* data transfer */ | |
1897 | case 0x6: | |
1898 | case 0x7: | |
c906108c SS |
1899 | if (bit (this_instr, 20)) |
1900 | { | |
1901 | /* load */ | |
1902 | if (bits (this_instr, 12, 15) == 15) | |
1903 | { | |
1904 | /* rd == pc */ | |
c5aa993b | 1905 | unsigned long rn; |
c906108c | 1906 | unsigned long base; |
c5aa993b | 1907 | |
c906108c SS |
1908 | if (bit (this_instr, 22)) |
1909 | error ("Illegal update to pc in instruction"); | |
1910 | ||
1911 | /* byte write to PC */ | |
1912 | rn = bits (this_instr, 16, 19); | |
1913 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1914 | if (bit (this_instr, 24)) | |
1915 | { | |
1916 | /* pre-indexed */ | |
1917 | int c = (status & FLAG_C) ? 1 : 0; | |
1918 | unsigned long offset = | |
c5aa993b | 1919 | (bit (this_instr, 25) |
ed9a39eb | 1920 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1921 | : bits (this_instr, 0, 11)); |
c906108c SS |
1922 | |
1923 | if (bit (this_instr, 23)) | |
1924 | base += offset; | |
1925 | else | |
1926 | base -= offset; | |
1927 | } | |
c5aa993b | 1928 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1929 | 4); |
c5aa993b | 1930 | |
c906108c SS |
1931 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1932 | ||
1933 | if (nextpc == pc) | |
1934 | error ("Infinite loop detected"); | |
1935 | } | |
1936 | } | |
1937 | break; | |
c5aa993b JM |
1938 | |
1939 | case 0x8: | |
1940 | case 0x9: /* block transfer */ | |
c906108c SS |
1941 | if (bit (this_instr, 20)) |
1942 | { | |
1943 | /* LDM */ | |
1944 | if (bit (this_instr, 15)) | |
1945 | { | |
1946 | /* loading pc */ | |
1947 | int offset = 0; | |
1948 | ||
1949 | if (bit (this_instr, 23)) | |
1950 | { | |
1951 | /* up */ | |
1952 | unsigned long reglist = bits (this_instr, 0, 14); | |
1953 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1954 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1955 | offset += 4; |
1956 | } | |
1957 | else if (bit (this_instr, 24)) | |
1958 | offset = -4; | |
c5aa993b | 1959 | |
c906108c | 1960 | { |
c5aa993b JM |
1961 | unsigned long rn_val = |
1962 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1963 | nextpc = |
1964 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1965 | + offset), |
c906108c SS |
1966 | 4); |
1967 | } | |
1968 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1969 | if (nextpc == pc) | |
1970 | error ("Infinite loop detected"); | |
1971 | } | |
1972 | } | |
1973 | break; | |
c5aa993b JM |
1974 | |
1975 | case 0xb: /* branch & link */ | |
1976 | case 0xa: /* branch */ | |
c906108c SS |
1977 | { |
1978 | nextpc = BranchDest (pc, this_instr); | |
1979 | ||
1980 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1981 | if (nextpc == pc) | |
1982 | error ("Infinite loop detected"); | |
1983 | break; | |
1984 | } | |
c5aa993b JM |
1985 | |
1986 | case 0xc: | |
1987 | case 0xd: | |
1988 | case 0xe: /* coproc ops */ | |
1989 | case 0xf: /* SWI */ | |
c906108c SS |
1990 | break; |
1991 | ||
1992 | default: | |
97e03143 | 1993 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
1994 | return (pc); |
1995 | } | |
1996 | } | |
1997 | ||
1998 | return nextpc; | |
1999 | } | |
2000 | ||
9512d7fd FN |
2001 | /* single_step() is called just before we want to resume the inferior, |
2002 | if we want to single-step it but there is no hardware or kernel | |
2003 | single-step support. We find the target of the coming instruction | |
2004 | and breakpoint it. | |
2005 | ||
2006 | single_step is also called just after the inferior stops. If we had | |
2007 | set up a simulated single-step, we undo our damage. */ | |
2008 | ||
34e8f22d RE |
2009 | static void |
2010 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd FN |
2011 | { |
2012 | static int next_pc; /* State between setting and unsetting. */ | |
2013 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ | |
2014 | ||
2015 | if (insert_bpt) | |
2016 | { | |
34e8f22d | 2017 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 2018 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
2019 | } |
2020 | else | |
80fcf3f0 | 2021 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 2022 | } |
9512d7fd | 2023 | |
c906108c SS |
2024 | #include "bfd-in2.h" |
2025 | #include "libcoff.h" | |
2026 | ||
2027 | static int | |
ed9a39eb | 2028 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2029 | { |
2030 | if (arm_pc_is_thumb (memaddr)) | |
2031 | { | |
c5aa993b JM |
2032 | static asymbol *asym; |
2033 | static combined_entry_type ce; | |
2034 | static struct coff_symbol_struct csym; | |
2035 | static struct _bfd fake_bfd; | |
2036 | static bfd_target fake_target; | |
c906108c SS |
2037 | |
2038 | if (csym.native == NULL) | |
2039 | { | |
da3c6d4a MS |
2040 | /* Create a fake symbol vector containing a Thumb symbol. |
2041 | This is solely so that the code in print_insn_little_arm() | |
2042 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2043 | the presence of a Thumb symbol and switch to decoding | |
2044 | Thumb instructions. */ | |
c5aa993b JM |
2045 | |
2046 | fake_target.flavour = bfd_target_coff_flavour; | |
2047 | fake_bfd.xvec = &fake_target; | |
c906108c | 2048 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2049 | csym.native = &ce; |
2050 | csym.symbol.the_bfd = &fake_bfd; | |
2051 | csym.symbol.name = "fake"; | |
2052 | asym = (asymbol *) & csym; | |
c906108c | 2053 | } |
c5aa993b | 2054 | |
c906108c | 2055 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2056 | info->symbols = &asym; |
c906108c SS |
2057 | } |
2058 | else | |
2059 | info->symbols = NULL; | |
c5aa993b | 2060 | |
d7449b42 | 2061 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
2062 | return print_insn_big_arm (memaddr, info); |
2063 | else | |
2064 | return print_insn_little_arm (memaddr, info); | |
2065 | } | |
2066 | ||
66e810cd RE |
2067 | /* The following define instruction sequences that will cause ARM |
2068 | cpu's to take an undefined instruction trap. These are used to | |
2069 | signal a breakpoint to GDB. | |
2070 | ||
2071 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2072 | modes. A different instruction is required for each mode. The ARM | |
2073 | cpu's can also be big or little endian. Thus four different | |
2074 | instructions are needed to support all cases. | |
2075 | ||
2076 | Note: ARMv4 defines several new instructions that will take the | |
2077 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2078 | not in fact add the new instructions. The new undefined | |
2079 | instructions in ARMv4 are all instructions that had no defined | |
2080 | behaviour in earlier chips. There is no guarantee that they will | |
2081 | raise an exception, but may be treated as NOP's. In practice, it | |
2082 | may only safe to rely on instructions matching: | |
2083 | ||
2084 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2085 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2086 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2087 | ||
2088 | Even this may only true if the condition predicate is true. The | |
2089 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2090 | ||
2091 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2092 | and NetBSD all use a software interrupt rather than an undefined | |
2093 | instruction to force a trap. This can be handled by by the | |
2094 | abi-specific code during establishment of the gdbarch vector. */ | |
2095 | ||
2096 | ||
d7b486e7 RE |
2097 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
2098 | override these definitions. */ | |
66e810cd RE |
2099 | #ifndef ARM_LE_BREAKPOINT |
2100 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
2101 | #endif | |
2102 | #ifndef ARM_BE_BREAKPOINT | |
2103 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
2104 | #endif | |
2105 | #ifndef THUMB_LE_BREAKPOINT | |
2106 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
2107 | #endif | |
2108 | #ifndef THUMB_BE_BREAKPOINT | |
2109 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
2110 | #endif | |
2111 | ||
2112 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2113 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2114 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2115 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2116 | ||
34e8f22d RE |
2117 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2118 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2119 | breakpoint should be used. It returns a pointer to a string of |
2120 | bytes that encode a breakpoint instruction, stores the length of | |
2121 | the string to *lenptr, and adjusts the program counter (if | |
2122 | necessary) to point to the actual memory location where the | |
c906108c SS |
2123 | breakpoint should be inserted. */ |
2124 | ||
34e8f22d RE |
2125 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
2126 | breakpoints and storing their handles instread of what was in | |
2127 | memory. It is nice that this is the same size as a handle - | |
2128 | otherwise remote-rdp will have to change. */ | |
2129 | ||
ab89facf | 2130 | static const unsigned char * |
ed9a39eb | 2131 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2132 | { |
66e810cd RE |
2133 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2134 | ||
c906108c SS |
2135 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
2136 | { | |
66e810cd RE |
2137 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2138 | *lenptr = tdep->thumb_breakpoint_size; | |
2139 | return tdep->thumb_breakpoint; | |
c906108c SS |
2140 | } |
2141 | else | |
2142 | { | |
66e810cd RE |
2143 | *lenptr = tdep->arm_breakpoint_size; |
2144 | return tdep->arm_breakpoint; | |
c906108c SS |
2145 | } |
2146 | } | |
ed9a39eb JM |
2147 | |
2148 | /* Extract from an array REGBUF containing the (raw) register state a | |
2149 | function return value of type TYPE, and copy that, in virtual | |
2150 | format, into VALBUF. */ | |
2151 | ||
34e8f22d | 2152 | static void |
ed9a39eb JM |
2153 | arm_extract_return_value (struct type *type, |
2154 | char regbuf[REGISTER_BYTES], | |
2155 | char *valbuf) | |
2156 | { | |
2157 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
08216dd7 RE |
2158 | { |
2159 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2160 | ||
2161 | switch (tdep->fp_model) | |
2162 | { | |
2163 | case ARM_FLOAT_FPA: | |
2164 | convert_from_extended (®buf[REGISTER_BYTE (ARM_F0_REGNUM)], | |
2165 | valbuf); | |
2166 | break; | |
2167 | ||
2168 | case ARM_FLOAT_SOFT: | |
2169 | case ARM_FLOAT_SOFT_VFP: | |
2170 | memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)], | |
2171 | TYPE_LENGTH (type)); | |
2172 | break; | |
2173 | ||
2174 | default: | |
2175 | internal_error | |
2176 | (__FILE__, __LINE__, | |
2177 | "arm_extract_return_value: Floating point model not supported"); | |
2178 | break; | |
2179 | } | |
2180 | } | |
ed9a39eb | 2181 | else |
34e8f22d RE |
2182 | memcpy (valbuf, ®buf[REGISTER_BYTE (ARM_A1_REGNUM)], |
2183 | TYPE_LENGTH (type)); | |
2184 | } | |
2185 | ||
67255d04 RE |
2186 | /* Extract from an array REGBUF containing the (raw) register state |
2187 | the address in which a function should return its structure value. */ | |
2188 | ||
2189 | static CORE_ADDR | |
2190 | arm_extract_struct_value_address (char *regbuf) | |
2191 | { | |
2192 | return extract_address (regbuf, REGISTER_RAW_SIZE(ARM_A1_REGNUM)); | |
2193 | } | |
2194 | ||
2195 | /* Will a function return an aggregate type in memory or in a | |
2196 | register? Return 0 if an aggregate type can be returned in a | |
2197 | register, 1 if it must be returned in memory. */ | |
2198 | ||
2199 | static int | |
2200 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2201 | { | |
2202 | int nRc; | |
2203 | register enum type_code code; | |
2204 | ||
2205 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
2206 | registers. For an aggregate type to be integer like, its size | |
2207 | must be less than or equal to REGISTER_SIZE and the offset of | |
2208 | each addressable subfield must be zero. Note that bit fields are | |
2209 | not addressable, and all addressable subfields of unions always | |
2210 | start at offset zero. | |
2211 | ||
2212 | This function is based on the behaviour of GCC 2.95.1. | |
2213 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2214 | ||
2215 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2216 | parameters correctly for a function returning the following | |
2217 | structure: struct { float f;}; This should be returned in memory, | |
2218 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2219 | know of any way to detect if a function like the above has been | |
2220 | compiled with the correct calling convention. */ | |
2221 | ||
2222 | /* All aggregate types that won't fit in a register must be returned | |
2223 | in memory. */ | |
2224 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
2225 | { | |
2226 | return 1; | |
2227 | } | |
2228 | ||
2229 | /* The only aggregate types that can be returned in a register are | |
2230 | structs and unions. Arrays must be returned in memory. */ | |
2231 | code = TYPE_CODE (type); | |
2232 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2233 | { | |
2234 | return 1; | |
2235 | } | |
2236 | ||
2237 | /* Assume all other aggregate types can be returned in a register. | |
2238 | Run a check for structures, unions and arrays. */ | |
2239 | nRc = 0; | |
2240 | ||
2241 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2242 | { | |
2243 | int i; | |
2244 | /* Need to check if this struct/union is "integer" like. For | |
2245 | this to be true, its size must be less than or equal to | |
2246 | REGISTER_SIZE and the offset of each addressable subfield | |
2247 | must be zero. Note that bit fields are not addressable, and | |
2248 | unions always start at offset zero. If any of the subfields | |
2249 | is a floating point type, the struct/union cannot be an | |
2250 | integer type. */ | |
2251 | ||
2252 | /* For each field in the object, check: | |
2253 | 1) Is it FP? --> yes, nRc = 1; | |
2254 | 2) Is it addressable (bitpos != 0) and | |
2255 | not packed (bitsize == 0)? | |
2256 | --> yes, nRc = 1 | |
2257 | */ | |
2258 | ||
2259 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2260 | { | |
2261 | enum type_code field_type_code; | |
2262 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
2263 | ||
2264 | /* Is it a floating point type field? */ | |
2265 | if (field_type_code == TYPE_CODE_FLT) | |
2266 | { | |
2267 | nRc = 1; | |
2268 | break; | |
2269 | } | |
2270 | ||
2271 | /* If bitpos != 0, then we have to care about it. */ | |
2272 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2273 | { | |
2274 | /* Bitfields are not addressable. If the field bitsize is | |
2275 | zero, then the field is not packed. Hence it cannot be | |
2276 | a bitfield or any other packed type. */ | |
2277 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2278 | { | |
2279 | nRc = 1; | |
2280 | break; | |
2281 | } | |
2282 | } | |
2283 | } | |
2284 | } | |
2285 | ||
2286 | return nRc; | |
2287 | } | |
2288 | ||
34e8f22d RE |
2289 | /* Write into appropriate registers a function return value of type |
2290 | TYPE, given in virtual format. */ | |
2291 | ||
2292 | static void | |
2293 | arm_store_return_value (struct type *type, char *valbuf) | |
2294 | { | |
2295 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2296 | { | |
08216dd7 | 2297 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
34e8f22d RE |
2298 | char buf[MAX_REGISTER_RAW_SIZE]; |
2299 | ||
08216dd7 RE |
2300 | switch (tdep->fp_model) |
2301 | { | |
2302 | case ARM_FLOAT_FPA: | |
2303 | ||
2304 | convert_to_extended (valbuf, buf); | |
2305 | write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM), buf, | |
2306 | MAX_REGISTER_RAW_SIZE); | |
2307 | break; | |
2308 | ||
2309 | case ARM_FLOAT_SOFT: | |
2310 | case ARM_FLOAT_SOFT_VFP: | |
2311 | write_register_bytes (ARM_A1_REGNUM, valbuf, TYPE_LENGTH (type)); | |
2312 | break; | |
2313 | ||
2314 | default: | |
2315 | internal_error | |
2316 | (__FILE__, __LINE__, | |
2317 | "arm_store_return_value: Floating point model not supported"); | |
2318 | break; | |
2319 | } | |
34e8f22d RE |
2320 | } |
2321 | else | |
08216dd7 | 2322 | write_register_bytes (ARM_A1_REGNUM, valbuf, TYPE_LENGTH (type)); |
34e8f22d RE |
2323 | } |
2324 | ||
2325 | /* Store the address of the place in which to copy the structure the | |
2326 | subroutine will return. This is called from call_function. */ | |
2327 | ||
2328 | static void | |
2329 | arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
2330 | { | |
2331 | write_register (ARM_A1_REGNUM, addr); | |
ed9a39eb JM |
2332 | } |
2333 | ||
9df628e0 RE |
2334 | static int |
2335 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2336 | { | |
2337 | CORE_ADDR jb_addr; | |
2338 | char buf[INT_REGISTER_RAW_SIZE]; | |
2339 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2340 | ||
2341 | jb_addr = read_register (ARM_A1_REGNUM); | |
2342 | ||
2343 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2344 | INT_REGISTER_RAW_SIZE)) | |
2345 | return 0; | |
2346 | ||
2347 | *pc = extract_address (buf, INT_REGISTER_RAW_SIZE); | |
2348 | return 1; | |
2349 | } | |
2350 | ||
ed9a39eb | 2351 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2352 | |
2353 | int | |
ed9a39eb | 2354 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2355 | { |
2356 | CORE_ADDR start_addr; | |
2357 | ||
ed9a39eb JM |
2358 | /* Find the starting address of the function containing the PC. If |
2359 | the caller didn't give us a name, look it up at the same time. */ | |
c906108c SS |
2360 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) |
2361 | return 0; | |
2362 | ||
2363 | return strncmp (name, "_call_via_r", 11) == 0; | |
2364 | } | |
2365 | ||
ed9a39eb JM |
2366 | /* If PC is in a Thumb call or return stub, return the address of the |
2367 | target PC, which is in a register. The thunk functions are called | |
2368 | _called_via_xx, where x is the register name. The possible names | |
2369 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2370 | |
2371 | CORE_ADDR | |
ed9a39eb | 2372 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2373 | { |
c5aa993b | 2374 | char *name; |
c906108c SS |
2375 | CORE_ADDR start_addr; |
2376 | ||
2377 | /* Find the starting address and name of the function containing the PC. */ | |
2378 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2379 | return 0; | |
2380 | ||
2381 | /* Call thunks always start with "_call_via_". */ | |
2382 | if (strncmp (name, "_call_via_", 10) == 0) | |
2383 | { | |
ed9a39eb JM |
2384 | /* Use the name suffix to determine which register contains the |
2385 | target PC. */ | |
c5aa993b JM |
2386 | static char *table[15] = |
2387 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2388 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2389 | }; | |
c906108c SS |
2390 | int regno; |
2391 | ||
2392 | for (regno = 0; regno <= 14; regno++) | |
2393 | if (strcmp (&name[10], table[regno]) == 0) | |
2394 | return read_register (regno); | |
2395 | } | |
ed9a39eb | 2396 | |
c5aa993b | 2397 | return 0; /* not a stub */ |
c906108c SS |
2398 | } |
2399 | ||
da3c6d4a MS |
2400 | /* If the user changes the register disassembly flavor used for info |
2401 | register and other commands, we have to also switch the flavor used | |
2402 | in opcodes for disassembly output. This function is run in the set | |
2403 | disassembly_flavor command, and does that. */ | |
bc90b915 FN |
2404 | |
2405 | static void | |
2406 | set_disassembly_flavor_sfunc (char *args, int from_tty, | |
2407 | struct cmd_list_element *c) | |
2408 | { | |
2409 | set_disassembly_flavor (); | |
2410 | } | |
2411 | \f | |
966fbf70 | 2412 | /* Return the ARM register name corresponding to register I. */ |
34e8f22d RE |
2413 | static char * |
2414 | arm_register_name (int i) | |
966fbf70 RE |
2415 | { |
2416 | return arm_register_names[i]; | |
2417 | } | |
2418 | ||
bc90b915 FN |
2419 | static void |
2420 | set_disassembly_flavor (void) | |
2421 | { | |
2422 | const char *setname, *setdesc, **regnames; | |
2423 | int numregs, j; | |
2424 | ||
2425 | /* Find the flavor that the user wants in the opcodes table. */ | |
2426 | int current = 0; | |
2427 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
2428 | while ((disassembly_flavor != setname) | |
2429 | && (current < num_flavor_options)) | |
2430 | get_arm_regnames (++current, &setname, &setdesc, ®names); | |
2431 | current_option = current; | |
2432 | ||
2433 | /* Fill our copy. */ | |
2434 | for (j = 0; j < numregs; j++) | |
2435 | arm_register_names[j] = (char *) regnames[j]; | |
2436 | ||
2437 | /* Adjust case. */ | |
34e8f22d | 2438 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2439 | { |
34e8f22d RE |
2440 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2441 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2442 | } |
2443 | else | |
2444 | { | |
34e8f22d RE |
2445 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2446 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2447 | } |
2448 | ||
2449 | /* Synchronize the disassembler. */ | |
2450 | set_arm_regname_option (current); | |
2451 | } | |
2452 | ||
2453 | /* arm_othernames implements the "othernames" command. This is kind | |
2454 | of hacky, and I prefer the set-show disassembly-flavor which is | |
2455 | also used for the x86 gdb. I will keep this around, however, in | |
2456 | case anyone is actually using it. */ | |
2457 | ||
2458 | static void | |
2459 | arm_othernames (char *names, int n) | |
2460 | { | |
2461 | /* Circle through the various flavors. */ | |
2462 | current_option = (current_option + 1) % num_flavor_options; | |
2463 | ||
2464 | disassembly_flavor = valid_flavors[current_option]; | |
2465 | set_disassembly_flavor (); | |
2466 | } | |
2467 | ||
a42dd537 KB |
2468 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
2469 | for ARM linux targets using the struct offsets defined in <link.h>. | |
2470 | Note, however, that link.h is not actually referred to in this file. | |
2471 | Instead, the relevant structs offsets were obtained from examining | |
2472 | link.h. (We can't refer to link.h from this file because the host | |
2473 | system won't necessarily have it, or if it does, the structs which | |
2474 | it defines will refer to the host system, not the target.) */ | |
2475 | ||
2476 | struct link_map_offsets * | |
2477 | arm_linux_svr4_fetch_link_map_offsets (void) | |
2478 | { | |
2479 | static struct link_map_offsets lmo; | |
2480 | static struct link_map_offsets *lmp = 0; | |
2481 | ||
2482 | if (lmp == 0) | |
2483 | { | |
2484 | lmp = &lmo; | |
2485 | ||
2486 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we | |
2487 | need. */ | |
2488 | ||
2489 | lmo.r_map_offset = 4; | |
2490 | lmo.r_map_size = 4; | |
2491 | ||
2492 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we | |
2493 | need. */ | |
2494 | ||
2495 | lmo.l_addr_offset = 0; | |
2496 | lmo.l_addr_size = 4; | |
2497 | ||
2498 | lmo.l_name_offset = 4; | |
2499 | lmo.l_name_size = 4; | |
2500 | ||
2501 | lmo.l_next_offset = 12; | |
2502 | lmo.l_next_size = 4; | |
2503 | ||
2504 | lmo.l_prev_offset = 16; | |
2505 | lmo.l_prev_size = 4; | |
2506 | } | |
2507 | ||
2508 | return lmp; | |
2509 | } | |
2510 | ||
082fc60d RE |
2511 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2512 | function. */ | |
2513 | ||
2514 | static int | |
2515 | coff_sym_is_thumb (int val) | |
2516 | { | |
2517 | return (val == C_THUMBEXT || | |
2518 | val == C_THUMBSTAT || | |
2519 | val == C_THUMBEXTFUNC || | |
2520 | val == C_THUMBSTATFUNC || | |
2521 | val == C_THUMBLABEL); | |
2522 | } | |
2523 | ||
2524 | /* arm_coff_make_msymbol_special() | |
2525 | arm_elf_make_msymbol_special() | |
2526 | ||
2527 | These functions test whether the COFF or ELF symbol corresponds to | |
2528 | an address in thumb code, and set a "special" bit in a minimal | |
2529 | symbol to indicate that it does. */ | |
2530 | ||
34e8f22d | 2531 | static void |
082fc60d RE |
2532 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2533 | { | |
2534 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2535 | STT_ARM_TFUNC). */ | |
2536 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2537 | == STT_LOPROC) | |
2538 | MSYMBOL_SET_SPECIAL (msym); | |
2539 | } | |
2540 | ||
34e8f22d | 2541 | static void |
082fc60d RE |
2542 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2543 | { | |
2544 | if (coff_sym_is_thumb (val)) | |
2545 | MSYMBOL_SET_SPECIAL (msym); | |
2546 | } | |
2547 | ||
97e03143 RE |
2548 | \f |
2549 | static void | |
2550 | process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj) | |
2551 | { | |
2552 | enum arm_abi *os_ident_ptr = obj; | |
2553 | const char *name; | |
2554 | unsigned int sectsize; | |
2555 | ||
2556 | name = bfd_get_section_name (abfd, sect); | |
2557 | sectsize = bfd_section_size (abfd, sect); | |
2558 | ||
2559 | if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0) | |
2560 | { | |
2561 | unsigned int name_length, data_length, note_type; | |
2562 | char *note; | |
2563 | ||
2564 | /* If the section is larger than this, it's probably not what we are | |
2565 | looking for. */ | |
2566 | if (sectsize > 128) | |
2567 | sectsize = 128; | |
2568 | ||
2569 | note = alloca (sectsize); | |
2570 | ||
2571 | bfd_get_section_contents (abfd, sect, note, | |
2572 | (file_ptr) 0, (bfd_size_type) sectsize); | |
2573 | ||
2574 | name_length = bfd_h_get_32 (abfd, note); | |
2575 | data_length = bfd_h_get_32 (abfd, note + 4); | |
2576 | note_type = bfd_h_get_32 (abfd, note + 8); | |
2577 | ||
2578 | if (name_length == 4 && data_length == 16 && note_type == 1 | |
2579 | && strcmp (note + 12, "GNU") == 0) | |
2580 | { | |
2581 | int os_number = bfd_h_get_32 (abfd, note + 16); | |
2582 | ||
d7afb4c9 | 2583 | /* The case numbers are from abi-tags in glibc. */ |
97e03143 RE |
2584 | switch (os_number) |
2585 | { | |
2586 | case 0 : | |
2587 | *os_ident_ptr = ARM_ABI_LINUX; | |
2588 | break; | |
2589 | ||
2590 | case 1 : | |
2591 | internal_error | |
2592 | (__FILE__, __LINE__, | |
2593 | "process_note_abi_sections: Hurd objects not supported"); | |
2594 | break; | |
2595 | ||
2596 | case 2 : | |
2597 | internal_error | |
2598 | (__FILE__, __LINE__, | |
2599 | "process_note_abi_sections: Solaris objects not supported"); | |
2600 | break; | |
2601 | ||
2602 | default : | |
2603 | internal_error | |
2604 | (__FILE__, __LINE__, | |
2605 | "process_note_abi_sections: unknown OS number %d", | |
2606 | os_number); | |
2607 | break; | |
2608 | } | |
2609 | } | |
2610 | } | |
2611 | /* NetBSD uses a similar trick. */ | |
2612 | else if (strcmp (name, ".note.netbsd.ident") == 0 && sectsize > 0) | |
2613 | { | |
2614 | unsigned int name_length, desc_length, note_type; | |
2615 | char *note; | |
2616 | ||
2617 | /* If the section is larger than this, it's probably not what we are | |
2618 | looking for. */ | |
2619 | if (sectsize > 128) | |
2620 | sectsize = 128; | |
2621 | ||
2622 | note = alloca (sectsize); | |
2623 | ||
2624 | bfd_get_section_contents (abfd, sect, note, | |
2625 | (file_ptr) 0, (bfd_size_type) sectsize); | |
2626 | ||
2627 | name_length = bfd_h_get_32 (abfd, note); | |
2628 | desc_length = bfd_h_get_32 (abfd, note + 4); | |
2629 | note_type = bfd_h_get_32 (abfd, note + 8); | |
2630 | ||
2631 | if (name_length == 7 && desc_length == 4 && note_type == 1 | |
2632 | && strcmp (note + 12, "NetBSD") == 0) | |
2633 | /* XXX Should we check the version here? | |
2634 | Probably not necessary yet. */ | |
2635 | *os_ident_ptr = ARM_ABI_NETBSD_ELF; | |
2636 | } | |
2637 | } | |
2638 | ||
2639 | /* Return one of the ELFOSABI_ constants for BFDs representing ELF | |
2640 | executables. If it's not an ELF executable or if the OS/ABI couldn't | |
d7afb4c9 | 2641 | be determined, simply return -1. */ |
97e03143 RE |
2642 | |
2643 | static int | |
2644 | get_elfosabi (bfd *abfd) | |
2645 | { | |
2646 | int elfosabi; | |
2647 | enum arm_abi arm_abi = ARM_ABI_UNKNOWN; | |
2648 | ||
2649 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; | |
2650 | ||
2651 | /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate | |
2652 | that we're on a SYSV system. However, GNU/Linux uses a note section | |
2653 | to record OS/ABI info, but leaves e_ident[EI_OSABI] zero. So we | |
2654 | have to check the note sections too. | |
2655 | ||
2656 | GNU/ARM tools set the EI_OSABI field to ELFOSABI_ARM, so handle that | |
d7afb4c9 | 2657 | as well. */ |
97e03143 RE |
2658 | if (elfosabi == 0 || elfosabi == ELFOSABI_ARM) |
2659 | { | |
2660 | bfd_map_over_sections (abfd, | |
2661 | process_note_abi_tag_sections, | |
2662 | &arm_abi); | |
2663 | } | |
2664 | ||
2665 | if (arm_abi != ARM_ABI_UNKNOWN) | |
2666 | return arm_abi; | |
2667 | ||
2668 | switch (elfosabi) | |
2669 | { | |
2670 | case ELFOSABI_NONE: | |
2671 | /* Existing ARM Tools don't set this field, so look at the EI_FLAGS | |
2672 | field for more information. */ | |
2673 | ||
2674 | switch (EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags)) | |
2675 | { | |
2676 | case EF_ARM_EABI_VER1: | |
2677 | return ARM_ABI_EABI_V1; | |
2678 | ||
2679 | case EF_ARM_EABI_VER2: | |
2680 | return ARM_ABI_EABI_V2; | |
2681 | ||
2682 | case EF_ARM_EABI_UNKNOWN: | |
2683 | /* Assume GNU tools. */ | |
2684 | return ARM_ABI_APCS; | |
2685 | ||
2686 | default: | |
2687 | internal_error (__FILE__, __LINE__, | |
2688 | "get_elfosabi: Unknown ARM EABI version 0x%lx", | |
2689 | EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags)); | |
2690 | ||
2691 | } | |
2692 | break; | |
2693 | ||
2694 | case ELFOSABI_NETBSD: | |
2695 | return ARM_ABI_NETBSD_ELF; | |
2696 | ||
2697 | case ELFOSABI_FREEBSD: | |
2698 | return ARM_ABI_FREEBSD; | |
2699 | ||
2700 | case ELFOSABI_LINUX: | |
2701 | return ARM_ABI_LINUX; | |
2702 | ||
2703 | case ELFOSABI_ARM: | |
2704 | /* Assume GNU tools with the old APCS abi. */ | |
2705 | return ARM_ABI_APCS; | |
2706 | ||
2707 | default: | |
2708 | } | |
2709 | ||
2710 | return ARM_ABI_UNKNOWN; | |
2711 | } | |
2712 | ||
2713 | struct arm_abi_handler | |
2714 | { | |
2715 | struct arm_abi_handler *next; | |
2716 | enum arm_abi abi; | |
2717 | void (*init_abi)(struct gdbarch_info, struct gdbarch *); | |
2718 | }; | |
2719 | ||
2720 | struct arm_abi_handler *arm_abi_handler_list = NULL; | |
2721 | ||
2722 | void | |
2723 | arm_gdbarch_register_os_abi (enum arm_abi abi, | |
2724 | void (*init_abi)(struct gdbarch_info, | |
2725 | struct gdbarch *)) | |
2726 | { | |
2727 | struct arm_abi_handler **handler_p; | |
2728 | ||
2729 | for (handler_p = &arm_abi_handler_list; *handler_p != NULL; | |
2730 | handler_p = &(*handler_p)->next) | |
2731 | { | |
2732 | if ((*handler_p)->abi == abi) | |
2733 | { | |
2734 | internal_error | |
2735 | (__FILE__, __LINE__, | |
2736 | "arm_gdbarch_register_os_abi: A handler for this ABI variant (%d)" | |
2737 | " has already been registered", (int)abi); | |
2738 | /* If user wants to continue, override previous definition. */ | |
2739 | (*handler_p)->init_abi = init_abi; | |
2740 | return; | |
2741 | } | |
2742 | } | |
2743 | ||
2744 | (*handler_p) | |
2745 | = (struct arm_abi_handler *) xmalloc (sizeof (struct arm_abi_handler)); | |
2746 | (*handler_p)->next = NULL; | |
2747 | (*handler_p)->abi = abi; | |
2748 | (*handler_p)->init_abi = init_abi; | |
2749 | } | |
2750 | ||
da3c6d4a MS |
2751 | /* Initialize the current architecture based on INFO. If possible, |
2752 | re-use an architecture from ARCHES, which is a list of | |
2753 | architectures already created during this debugging session. | |
97e03143 | 2754 | |
da3c6d4a MS |
2755 | Called e.g. at program startup, when reading a core file, and when |
2756 | reading a binary file. */ | |
97e03143 | 2757 | |
39bbf761 RE |
2758 | static struct gdbarch * |
2759 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2760 | { | |
97e03143 | 2761 | struct gdbarch_tdep *tdep; |
39bbf761 | 2762 | struct gdbarch *gdbarch; |
97e03143 RE |
2763 | enum arm_abi arm_abi = ARM_ABI_UNKNOWN; |
2764 | struct arm_abi_handler *abi_handler; | |
39bbf761 | 2765 | |
97e03143 | 2766 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2767 | |
97e03143 RE |
2768 | if (info.abfd != NULL) |
2769 | { | |
2770 | switch (bfd_get_flavour (info.abfd)) | |
2771 | { | |
2772 | case bfd_target_elf_flavour: | |
2773 | arm_abi = get_elfosabi (info.abfd); | |
2774 | break; | |
2775 | ||
2776 | case bfd_target_aout_flavour: | |
2777 | if (strcmp (bfd_get_target(info.abfd), "a.out-arm-netbsd") == 0) | |
2778 | arm_abi = ARM_ABI_NETBSD_AOUT; | |
2779 | else | |
2780 | /* Assume it's an old APCS-style ABI. */ | |
2781 | arm_abi = ARM_ABI_APCS; | |
2782 | break; | |
2783 | ||
2784 | case bfd_target_coff_flavour: | |
2785 | /* Assume it's an old APCS-style ABI. */ | |
2786 | /* XXX WinCE? */ | |
2787 | arm_abi = ARM_ABI_APCS; | |
2788 | break; | |
2789 | ||
2790 | default: | |
2791 | /* Not sure what to do here, leave the ABI as unknown. */ | |
2792 | break; | |
2793 | } | |
2794 | } | |
2795 | ||
d7afb4c9 | 2796 | /* Find a candidate among extant architectures. */ |
97e03143 RE |
2797 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2798 | arches != NULL; | |
2799 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2800 | { | |
2801 | /* Make sure the ABI selection matches. */ | |
2802 | tdep = gdbarch_tdep (arches->gdbarch); | |
2803 | if (tdep && tdep->arm_abi == arm_abi) | |
2804 | return arches->gdbarch; | |
2805 | } | |
2806 | ||
2807 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2808 | gdbarch = gdbarch_alloc (&info, tdep); | |
2809 | ||
2810 | tdep->arm_abi = arm_abi; | |
2811 | if (arm_abi < ARM_ABI_INVALID) | |
2812 | tdep->abi_name = arm_abi_names[arm_abi]; | |
2813 | else | |
2814 | { | |
2815 | internal_error (__FILE__, __LINE__, "Invalid setting of arm_abi %d", | |
2816 | (int) arm_abi); | |
2817 | tdep->abi_name = "<invalid>"; | |
2818 | } | |
39bbf761 | 2819 | |
08216dd7 RE |
2820 | /* This is the way it has always defaulted. */ |
2821 | tdep->fp_model = ARM_FLOAT_FPA; | |
2822 | ||
2823 | /* Breakpoints. */ | |
67255d04 RE |
2824 | switch (info.byte_order) |
2825 | { | |
2826 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2827 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2828 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2829 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2830 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2831 | ||
67255d04 RE |
2832 | break; |
2833 | ||
2834 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2835 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2836 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2837 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2838 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2839 | ||
67255d04 RE |
2840 | break; |
2841 | ||
2842 | default: | |
2843 | internal_error (__FILE__, __LINE__, | |
2844 | "arm_gdbarch_init: bad byte order for float format"); | |
2845 | } | |
2846 | ||
d7b486e7 RE |
2847 | /* On ARM targets char defaults to unsigned. */ |
2848 | set_gdbarch_char_signed (gdbarch, 0); | |
2849 | ||
9df628e0 | 2850 | /* This should be low enough for everything. */ |
97e03143 | 2851 | tdep->lowest_pc = 0x20; |
9df628e0 | 2852 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2853 | |
39bbf761 RE |
2854 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); |
2855 | ||
2856 | /* Call dummy code. */ | |
2857 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
2858 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
3fb4b924 RE |
2859 | /* We have to give this a value now, even though we will re-set it |
2860 | during each call to arm_fix_call_dummy. */ | |
2861 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 8); | |
39bbf761 RE |
2862 | set_gdbarch_call_dummy_p (gdbarch, 1); |
2863 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
2864 | ||
34e8f22d RE |
2865 | set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words); |
2866 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (arm_call_dummy_words)); | |
2867 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
d7b486e7 | 2868 | set_gdbarch_call_dummy_length (gdbarch, 0); |
34e8f22d RE |
2869 | |
2870 | set_gdbarch_fix_call_dummy (gdbarch, arm_fix_call_dummy); | |
2871 | ||
39bbf761 RE |
2872 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack); |
2873 | ||
2874 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
2875 | set_gdbarch_push_arguments (gdbarch, arm_push_arguments); | |
d7afb4c9 RE |
2876 | set_gdbarch_coerce_float_to_double (gdbarch, |
2877 | standard_coerce_float_to_double); | |
39bbf761 | 2878 | |
148754e5 | 2879 | /* Frame handling. */ |
39bbf761 | 2880 | set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid); |
148754e5 RE |
2881 | set_gdbarch_init_extra_frame_info (gdbarch, arm_init_extra_frame_info); |
2882 | set_gdbarch_read_fp (gdbarch, arm_read_fp); | |
2883 | set_gdbarch_frame_chain (gdbarch, arm_frame_chain); | |
2884 | set_gdbarch_frameless_function_invocation | |
2885 | (gdbarch, arm_frameless_function_invocation); | |
2886 | set_gdbarch_frame_saved_pc (gdbarch, arm_frame_saved_pc); | |
2887 | set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address); | |
2888 | set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address); | |
2889 | set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args); | |
2890 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2891 | set_gdbarch_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs); | |
2892 | set_gdbarch_push_dummy_frame (gdbarch, arm_push_dummy_frame); | |
2893 | set_gdbarch_pop_frame (gdbarch, arm_pop_frame); | |
2894 | ||
34e8f22d RE |
2895 | /* Address manipulation. */ |
2896 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2897 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2898 | ||
2899 | /* Offset from address of function to start of its code. */ | |
2900 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2901 | ||
2902 | /* Advance PC across function entry code. */ | |
2903 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2904 | ||
2905 | /* Get the PC when a frame might not be available. */ | |
2906 | set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); | |
2907 | ||
2908 | /* The stack grows downward. */ | |
2909 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2910 | ||
2911 | /* Breakpoint manipulation. */ | |
2912 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
2913 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2914 | ||
2915 | /* Information about registers, etc. */ | |
2916 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
2917 | set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ | |
2918 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); | |
2919 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
2920 | set_gdbarch_register_byte (gdbarch, arm_register_byte); | |
2921 | set_gdbarch_register_bytes (gdbarch, | |
2922 | (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
2923 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
2924 | + NUM_SREGS * STATUS_REGISTER_SIZE)); | |
2925 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); | |
2926 | set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size); | |
2927 | set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size); | |
2928 | set_gdbarch_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE); | |
2929 | set_gdbarch_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE); | |
2930 | set_gdbarch_register_virtual_type (gdbarch, arm_register_type); | |
2931 | ||
2932 | /* Integer registers are 4 bytes. */ | |
2933 | set_gdbarch_register_size (gdbarch, 4); | |
2934 | set_gdbarch_register_name (gdbarch, arm_register_name); | |
2935 | ||
2936 | /* Returning results. */ | |
2937 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); | |
2938 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
2939 | set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return); | |
67255d04 RE |
2940 | set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); |
2941 | set_gdbarch_extract_struct_value_address (gdbarch, | |
2942 | arm_extract_struct_value_address); | |
34e8f22d RE |
2943 | |
2944 | /* Single stepping. */ | |
2945 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2946 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2947 | ||
2948 | /* Minsymbol frobbing. */ | |
2949 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2950 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2951 | arm_coff_make_msymbol_special); | |
2952 | ||
97e03143 RE |
2953 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
2954 | if (arm_abi == ARM_ABI_UNKNOWN) | |
2955 | { | |
08216dd7 RE |
2956 | /* Don't complain about not knowing the ABI variant if we don't |
2957 | have an inferior. */ | |
2958 | if (info.abfd) | |
2959 | fprintf_filtered | |
2960 | (gdb_stderr, "GDB doesn't recognize the ABI of the inferior. " | |
2961 | "Attempting to continue with the default ARM settings"); | |
97e03143 RE |
2962 | } |
2963 | else | |
2964 | { | |
2965 | for (abi_handler = arm_abi_handler_list; abi_handler != NULL; | |
2966 | abi_handler = abi_handler->next) | |
2967 | if (abi_handler->abi == arm_abi) | |
2968 | break; | |
2969 | ||
2970 | if (abi_handler) | |
2971 | abi_handler->init_abi (info, gdbarch); | |
2972 | else | |
2973 | { | |
2974 | /* We assume that if GDB_MULTI_ARCH is less than | |
2975 | GDB_MULTI_ARCH_TM that an ABI variant can be supported by | |
2976 | overriding definitions in this file. */ | |
2977 | if (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) | |
2978 | fprintf_filtered | |
2979 | (gdb_stderr, | |
2980 | "A handler for the ABI variant \"%s\" is not built into this " | |
2981 | "configuration of GDB. " | |
2982 | "Attempting to continue with the default ARM settings", | |
2983 | arm_abi_names[arm_abi]); | |
2984 | } | |
2985 | } | |
2986 | ||
2987 | /* Now we have tuned the configuration, set a few final things, | |
2988 | based on what the OS ABI has told us. */ | |
2989 | ||
9df628e0 RE |
2990 | if (tdep->jb_pc >= 0) |
2991 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2992 | ||
08216dd7 RE |
2993 | /* Floating point sizes and format. */ |
2994 | switch (info.byte_order) | |
2995 | { | |
2996 | case BFD_ENDIAN_BIG: | |
2997 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2998 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2999 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
3000 | ||
3001 | break; | |
3002 | ||
3003 | case BFD_ENDIAN_LITTLE: | |
3004 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
3005 | if (tdep->fp_model == ARM_FLOAT_VFP | |
3006 | || tdep->fp_model == ARM_FLOAT_SOFT_VFP) | |
3007 | { | |
3008 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
3009 | set_gdbarch_long_double_format (gdbarch, | |
3010 | &floatformat_ieee_double_little); | |
3011 | } | |
3012 | else | |
3013 | { | |
3014 | set_gdbarch_double_format | |
3015 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
3016 | set_gdbarch_long_double_format | |
3017 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
3018 | } | |
3019 | break; | |
3020 | ||
3021 | default: | |
3022 | internal_error (__FILE__, __LINE__, | |
3023 | "arm_gdbarch_init: bad byte order for float format"); | |
3024 | } | |
3025 | ||
97e03143 | 3026 | /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still |
34e8f22d RE |
3027 | references the old architecture vector, not the one we are |
3028 | building here. */ | |
3029 | if (prologue_cache.saved_regs != NULL) | |
3030 | xfree (prologue_cache.saved_regs); | |
3031 | ||
3032 | prologue_cache.saved_regs = (CORE_ADDR *) | |
3033 | xcalloc (1, (sizeof (CORE_ADDR) | |
29673b29 AC |
3034 | * (gdbarch_num_regs (gdbarch) |
3035 | + gdbarch_num_pseudo_regs (gdbarch)))); | |
39bbf761 RE |
3036 | |
3037 | return gdbarch; | |
3038 | } | |
3039 | ||
97e03143 RE |
3040 | static void |
3041 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3042 | { | |
3043 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3044 | ||
3045 | if (tdep == NULL) | |
3046 | return; | |
3047 | ||
3048 | if (tdep->abi_name != NULL) | |
3049 | fprintf_unfiltered (file, "arm_dump_tdep: ABI = %s\n", tdep->abi_name); | |
3050 | else | |
3051 | internal_error (__FILE__, __LINE__, | |
3052 | "arm_dump_tdep: illegal setting of tdep->arm_abi (%d)", | |
3053 | (int) tdep->arm_abi); | |
3054 | ||
3055 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", | |
3056 | (unsigned long) tdep->lowest_pc); | |
3057 | } | |
3058 | ||
3059 | static void | |
3060 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
3061 | struct gdbarch *gdbarch) | |
3062 | { | |
3063 | /* Place-holder. */ | |
3064 | } | |
3065 | ||
3066 | static void | |
3067 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
3068 | struct gdbarch *gdbarch) | |
3069 | { | |
3070 | /* Place-holder. */ | |
3071 | } | |
3072 | ||
3073 | static void | |
3074 | arm_init_abi_apcs (struct gdbarch_info info, | |
3075 | struct gdbarch *gdbarch) | |
3076 | { | |
3077 | /* Place-holder. */ | |
3078 | } | |
3079 | ||
c906108c | 3080 | void |
ed9a39eb | 3081 | _initialize_arm_tdep (void) |
c906108c | 3082 | { |
bc90b915 FN |
3083 | struct ui_file *stb; |
3084 | long length; | |
96baa820 | 3085 | struct cmd_list_element *new_cmd; |
53904c9e AC |
3086 | const char *setname; |
3087 | const char *setdesc; | |
3088 | const char **regnames; | |
bc90b915 FN |
3089 | int numregs, i, j; |
3090 | static char *helptext; | |
085dd6e6 | 3091 | |
39bbf761 | 3092 | if (GDB_MULTI_ARCH) |
97e03143 RE |
3093 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
3094 | ||
3095 | /* Register some ABI variants for embedded systems. */ | |
3096 | arm_gdbarch_register_os_abi (ARM_ABI_EABI_V1, arm_init_abi_eabi_v1); | |
3097 | arm_gdbarch_register_os_abi (ARM_ABI_EABI_V2, arm_init_abi_eabi_v2); | |
3098 | arm_gdbarch_register_os_abi (ARM_ABI_APCS, arm_init_abi_apcs); | |
39bbf761 | 3099 | |
c906108c | 3100 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 3101 | |
bc90b915 FN |
3102 | /* Get the number of possible sets of register names defined in opcodes. */ |
3103 | num_flavor_options = get_arm_regname_num_options (); | |
3104 | ||
085dd6e6 | 3105 | /* Sync the opcode insn printer with our register viewer: */ |
bc90b915 | 3106 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3107 | |
bc90b915 FN |
3108 | /* Begin creating the help text. */ |
3109 | stb = mem_fileopen (); | |
3110 | fprintf_unfiltered (stb, "Set the disassembly flavor.\n\ | |
3111 | The valid values are:\n"); | |
ed9a39eb | 3112 | |
bc90b915 FN |
3113 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
3114 | valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *)); | |
3115 | for (i = 0; i < num_flavor_options; i++) | |
3116 | { | |
3117 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
53904c9e | 3118 | valid_flavors[i] = setname; |
bc90b915 FN |
3119 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
3120 | setdesc); | |
3121 | /* Copy the default names (if found) and synchronize disassembler. */ | |
3122 | if (!strcmp (setname, "std")) | |
3123 | { | |
53904c9e | 3124 | disassembly_flavor = setname; |
bc90b915 FN |
3125 | current_option = i; |
3126 | for (j = 0; j < numregs; j++) | |
3127 | arm_register_names[j] = (char *) regnames[j]; | |
3128 | set_arm_regname_option (i); | |
3129 | } | |
3130 | } | |
3131 | /* Mark the end of valid options. */ | |
3132 | valid_flavors[num_flavor_options] = NULL; | |
c906108c | 3133 | |
bc90b915 FN |
3134 | /* Finish the creation of the help text. */ |
3135 | fprintf_unfiltered (stb, "The default is \"std\"."); | |
3136 | helptext = ui_file_xstrdup (stb, &length); | |
3137 | ui_file_delete (stb); | |
ed9a39eb | 3138 | |
bc90b915 | 3139 | /* Add the disassembly-flavor command */ |
96baa820 | 3140 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
ed9a39eb | 3141 | valid_flavors, |
1ed2a135 | 3142 | &disassembly_flavor, |
bc90b915 | 3143 | helptext, |
ed9a39eb | 3144 | &setlist); |
9f60d481 | 3145 | set_cmd_sfunc (new_cmd, set_disassembly_flavor_sfunc); |
ed9a39eb JM |
3146 | add_show_from_set (new_cmd, &showlist); |
3147 | ||
c906108c SS |
3148 | /* ??? Maybe this should be a boolean. */ |
3149 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 3150 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 3151 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 3152 | &showlist); |
c906108c | 3153 | |
bc90b915 FN |
3154 | /* Add the deprecated "othernames" command */ |
3155 | ||
3156 | add_com ("othernames", class_obscure, arm_othernames, | |
3157 | "Switch to the next set of register names."); | |
c3b4394c RE |
3158 | |
3159 | /* Fill in the prologue_cache fields. */ | |
34e8f22d | 3160 | prologue_cache.saved_regs = NULL; |
c3b4394c RE |
3161 | prologue_cache.extra_info = (struct frame_extra_info *) |
3162 | xcalloc (1, sizeof (struct frame_extra_info)); | |
c906108c | 3163 | } |