[deliverable/binutils-gdb.git] / gdb / arm-tdep.h

/* Common target dependent code for GDB on ARM systems.
   Copyright (C) 2002-2017 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef ARM_TDEP_H
#define ARM_TDEP_H

/* Forward declarations.  */
struct gdbarch;
struct regset;
struct address_space;
struct get_next_pcs;
struct arm_get_next_pcs;
struct gdb_get_next_pcs;

#include "arch/arm.h"

#include <vector>

/* Say how long FP registers are.  Used for documentation purposes and
   code readability in this header.  IEEE extended doubles are 80
   bits.  DWORD aligned they use 96 bits.  */
#define FP_REGISTER_SIZE	12

/* Say how long VFP double precision registers are.  Used for documentation
   purposes and code readability.  These are fixed at 64 bits.  */
#define VFP_REGISTER_SIZE	8

/* Number of machine registers.  The only define actually required 
   is gdbarch_num_regs.  The other definitions are used for documentation
   purposes and code readability.  */
/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
   (and called PS for processor status) so the status bits can be cleared
   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
   in PS.  */
#define NUM_FREGS	8	/* Number of floating point registers.  */
#define NUM_SREGS	2	/* Number of status registers.  */
#define NUM_GREGS	16	/* Number of general purpose registers.  */


/* Type of floating-point code in use by inferior.  There are really 3 models
   that are traditionally supported (plus the endianness issue), but gcc can
   only generate 2 of those.  The third is APCS_FLOAT, where arguments to
   functions are passed in floating-point registers.  

   In addition to the traditional models, VFP adds two more. 

   If you update this enum, don't forget to update fp_model_strings in 
   arm-tdep.c.  */

enum arm_float_model
{
  ARM_FLOAT_AUTO,	/* Automatic detection.  Do not set in tdep.  */
  ARM_FLOAT_SOFT_FPA,	/* Traditional soft-float (mixed-endian on LE ARM).  */
  ARM_FLOAT_FPA,	/* FPA co-processor.  GCC calling convention.  */
  ARM_FLOAT_SOFT_VFP,	/* Soft-float with pure-endian doubles.  */
  ARM_FLOAT_VFP,	/* Full VFP calling convention.  */
  ARM_FLOAT_LAST	/* Keep at end.  */
};

/* ABI used by the inferior.  */
enum arm_abi_kind
{
  ARM_ABI_AUTO,
  ARM_ABI_APCS,
  ARM_ABI_AAPCS,
  ARM_ABI_LAST
};

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Target-dependent structure in gdbarch.  */
struct gdbarch_tdep
{
  /* The ABI for this architecture.  It should never be set to
     ARM_ABI_AUTO.  */
  enum arm_abi_kind arm_abi;

  enum arm_float_model fp_model; /* Floating point calling conventions.  */

  int have_fpa_registers;	/* Does the target report the FPA registers?  */
  int have_wmmx_registers;	/* Does the target report the WMMX registers?  */
  /* The number of VFP registers reported by the target.  It is zero
     if VFP registers are not supported.  */
  int vfp_register_count;
  int have_vfp_pseudos;		/* Are we synthesizing the single precision
				   VFP registers?  */
  int have_neon_pseudos;	/* Are we synthesizing the quad precision
				   NEON registers?  Requires
				   have_vfp_pseudos.  */
  int have_neon;		/* Do we have a NEON unit?  */

  int is_m;			/* Does the target follow the "M" profile.  */
  CORE_ADDR lowest_pc;		/* Lowest address at which instructions 
				   will appear.  */

  const gdb_byte *arm_breakpoint;	/* Breakpoint pattern for an ARM insn.  */
  int arm_breakpoint_size;	/* And its size.  */
  const gdb_byte *thumb_breakpoint;	/* Breakpoint pattern for a Thumb insn.  */
  int thumb_breakpoint_size;	/* And its size.  */

  /* If the Thumb breakpoint is an undefined instruction (which is
     affected by IT blocks) rather than a BKPT instruction (which is
     not), then we need a 32-bit Thumb breakpoint to preserve the
     instruction count in IT blocks.  */
  const gdb_byte *thumb2_breakpoint;
  int thumb2_breakpoint_size;

  int jb_pc;			/* Offset to PC value in jump buffer.
				   If this is negative, longjmp support
				   will be disabled.  */
  size_t jb_elt_size;		/* And the size of each entry in the buf.  */

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* ISA-specific data types.  */
  struct type *arm_ext_type;
  struct type *neon_double_type;
  struct type *neon_quad_type;

   /* syscall record.  */
  int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
};

/* Structures used for displaced stepping.  */

/* The maximum number of temporaries available for displaced instructions.  */
#define DISPLACED_TEMPS			16
/* The maximum number of modified instructions generated for one single-stepped
   instruction, including the breakpoint (usually at the end of the instruction
   sequence) and any scratch words, etc.  */
#define DISPLACED_MODIFIED_INSNS	8

struct displaced_step_closure
{
  ULONGEST tmp[DISPLACED_TEMPS];
  int rd;
  int wrote_to_pc;
  union
  {
    struct
    {
      int xfersize;
      int rn;			   /* Writeback register.  */
      unsigned int immed : 1;      /* Offset is immediate.  */
      unsigned int writeback : 1;  /* Perform base-register writeback.  */
      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
    } ldst;

    struct
    {
      unsigned long dest;
      unsigned int link : 1;
      unsigned int exchange : 1;
      unsigned int cond : 4;
    } branch;

    struct
    {
      unsigned int regmask;
      int rn;
      CORE_ADDR xfer_addr;
      unsigned int load : 1;
      unsigned int user : 1;
      unsigned int increment : 1;
      unsigned int before : 1;
      unsigned int writeback : 1;
      unsigned int cond : 4;
    } block;

    struct
    {
      unsigned int immed : 1;
    } preload;

    struct
    {
      /* If non-NULL, override generic SVC handling (e.g. for a particular
         OS).  */
      int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
			  struct displaced_step_closure *dsc);
    } svc;
  } u;

  /* The size of original instruction, 2 or 4.  */
  unsigned int insn_size;
  /* True if the original insn (and thus all replacement insns) are Thumb
     instead of ARM.   */
  unsigned int is_thumb;

  /* The slots in the array is used in this way below,
     - ARM instruction occupies one slot,
     - Thumb 16 bit instruction occupies one slot,
     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
  unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
  int numinsns;
  CORE_ADDR insn_addr;
  CORE_ADDR scratch_base;
  void (*cleanup) (struct gdbarch *, struct regcache *,
		   struct displaced_step_closure *);
};

/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
   write may write to the PC, specifies the way the CPSR T bit, etc. is
   modified by the instruction.  */

enum pc_write_style
{
  BRANCH_WRITE_PC,
  BX_WRITE_PC,
  LOAD_WRITE_PC,
  ALU_WRITE_PC,
  CANNOT_WRITE_PC
};

extern void
  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct regcache *regs,
			      struct displaced_step_closure *dsc);
extern void
  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct displaced_step_closure *dsc);
extern ULONGEST
  displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
		      int regno);
extern void
  displaced_write_reg (struct regcache *regs,
		       struct displaced_step_closure *dsc, int regno,
		       ULONGEST val, enum pc_write_style write_pc);

CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);

ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
							int len,
							int byte_order);

CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
					     CORE_ADDR val);

int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);

std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
int arm_is_thumb (struct regcache *regcache);
int arm_frame_is_thumb (struct frame_info *frame);

extern void arm_displaced_step_fixup (struct gdbarch *,
				      struct displaced_step_closure *,
				      CORE_ADDR, CORE_ADDR, struct regcache *);

/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
extern int arm_psr_thumb_bit (struct gdbarch *);

/* Is the instruction at the given memory address a Thumb or ARM
   instruction?  */
extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);

extern int arm_process_record (struct gdbarch *gdbarch, 
                               struct regcache *regcache, CORE_ADDR addr);
/* Functions exported from arm-bsd-tdep.h.  */

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */

extern void
  armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
				       iterate_over_regset_sections_cb *cb,
				       void *cb_data,
				       const struct regcache *regcache);

/* Target descriptions.  */
extern struct target_desc *tdesc_arm_with_m;
extern struct target_desc *tdesc_arm_with_iwmmxt;
extern struct target_desc *tdesc_arm_with_vfpv2;
extern struct target_desc *tdesc_arm_with_vfpv3;
extern struct target_desc *tdesc_arm_with_neon;

#endif /* arm-tdep.h */
Commit	Line	Data
34e8f22d	1	/* Common target dependent code for GDB on ARM systems.
61baf725	2	Copyright (C) 2002-2017 Free Software Foundation, Inc.
34e8f22d RE	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
a9762ec7	8	the Free Software Foundation; either version 3 of the License, or
34e8f22d RE	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
a9762ec7	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
34e8f22d	18
47ccd048 MK	19	#ifndef ARM_TDEP_H
	20	#define ARM_TDEP_H
	21
cb587d83	22	/* Forward declarations. */
47ccd048	23	struct gdbarch;
cb587d83	24	struct regset;
3352110b	25	struct address_space;
d9311bfa AT	26	struct get_next_pcs;
	27	struct arm_get_next_pcs;
	28	struct gdb_get_next_pcs;
cb587d83	29
ec741292	30	#include "arch/arm.h"
34e8f22d	31
a0ff9e1a SM	32	#include <vector>
a0ff9e1a SM	33
34e8f22d RE	34	/* Say how long FP registers are. Used for documentation purposes and
	35	code readability in this header. IEEE extended doubles are 80
	36	bits. DWORD aligned they use 96 bits. */
7a5ea0d4	37	#define FP_REGISTER_SIZE 12
34e8f22d	38
3184d3f9 JL	39	/* Say how long VFP double precision registers are. Used for documentation
	40	purposes and code readability. These are fixed at 64 bits. */
	41	#define VFP_REGISTER_SIZE 8
	42
34e8f22d	43	/* Number of machine registers. The only define actually required
f57d151a	44	is gdbarch_num_regs. The other definitions are used for documentation
34e8f22d RE	45	purposes and code readability. */
	46	/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
	47	(and called PS for processor status) so the status bits can be cleared
	48	from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
	49	in PS. */
	50	#define NUM_FREGS 8 /* Number of floating point registers. */
	51	#define NUM_SREGS 2 /* Number of status registers. */
	52	#define NUM_GREGS 16 /* Number of general purpose registers. */
	53
	54
9779414d	55
08216dd7 RE	56	/* Type of floating-point code in use by inferior. There are really 3 models
	57	that are traditionally supported (plus the endianness issue), but gcc can
	58	only generate 2 of those. The third is APCS_FLOAT, where arguments to
	59	functions are passed in floating-point registers.
	60
fd50bc42 RE	61	In addition to the traditional models, VFP adds two more.
	62
	63	If you update this enum, don't forget to update fp_model_strings in
	64	arm-tdep.c. */
08216dd7 RE	65
	66	enum arm_float_model
	67	{
fd50bc42 RE	68	ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
	69	ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
	70	ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
	71	ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
	72	ARM_FLOAT_VFP, /* Full VFP calling convention. */
	73	ARM_FLOAT_LAST /* Keep at end. */
08216dd7 RE	74	};
08216dd7 RE	75
28e97307 DJ	76	/* ABI used by the inferior. */
	77	enum arm_abi_kind
	78	{
	79	ARM_ABI_AUTO,
	80	ARM_ABI_APCS,
	81	ARM_ABI_AAPCS,
	82	ARM_ABI_LAST
	83	};
fd50bc42	84
7c00367c MK	85	/* Convention for returning structures. */
	86
	87	enum struct_return
	88	{
	89	pcc_struct_return, /* Return "short" structures in memory. */
	90	reg_struct_return /* Return "short" structures in registers. */
	91	};
	92
97e03143 RE	93	/* Target-dependent structure in gdbarch. */
	94	struct gdbarch_tdep
	95	{
28e97307 DJ	96	/* The ABI for this architecture. It should never be set to
	97	ARM_ABI_AUTO. */
	98	enum arm_abi_kind arm_abi;
	99
08216dd7 RE	100	enum arm_float_model fp_model; /* Floating point calling conventions. */
08216dd7 RE	101
ff6f572f	102	int have_fpa_registers; /* Does the target report the FPA registers? */
a56cc1ce	103	int have_wmmx_registers; /* Does the target report the WMMX registers? */
330c6ca9 YQ	104	/* The number of VFP registers reported by the target. It is zero
	105	if VFP registers are not supported. */
	106	int vfp_register_count;
58d6951d DJ	107	int have_vfp_pseudos; /* Are we synthesizing the single precision
	108	VFP registers? */
	109	int have_neon_pseudos; /* Are we synthesizing the quad precision
	110	NEON registers? Requires
	111	have_vfp_pseudos. */
	112	int have_neon; /* Do we have a NEON unit? */
ff6f572f	113
9779414d	114	int is_m; /* Does the target follow the "M" profile. */
97e03143 RE	115	CORE_ADDR lowest_pc; /* Lowest address at which instructions
97e03143 RE	116	will appear. */
9df628e0	117
948f8e3d	118	const gdb_byte arm_breakpoint; / Breakpoint pattern for an ARM insn. */
9df628e0	119	int arm_breakpoint_size; /* And its size. */
948f8e3d	120	const gdb_byte thumb_breakpoint; / Breakpoint pattern for a Thumb insn. */
9df628e0 RE	121	int thumb_breakpoint_size; /* And its size. */
9df628e0 RE	122
177321bd DJ	123	/* If the Thumb breakpoint is an undefined instruction (which is
	124	affected by IT blocks) rather than a BKPT instruction (which is
	125	not), then we need a 32-bit Thumb breakpoint to preserve the
	126	instruction count in IT blocks. */
948f8e3d	127	const gdb_byte *thumb2_breakpoint;
177321bd DJ	128	int thumb2_breakpoint_size;
177321bd DJ	129
0963b4bd	130	int jb_pc; /* Offset to PC value in jump buffer.
9df628e0 RE	131	If this is negative, longjmp support
	132	will be disabled. */
	133	size_t jb_elt_size; /* And the size of each entry in the buf. */
cb587d83	134
7c00367c MK	135	/* Convention for returning structures. */
	136	enum struct_return struct_return;
	137
27067745 UW	138	/* ISA-specific data types. */
27067745 UW	139	struct type *arm_ext_type;
58d6951d DJ	140	struct type *neon_double_type;
58d6951d DJ	141	struct type *neon_quad_type;
25b41d01	142
97dfe206 OJ	143	/* syscall record. */
97dfe206 OJ	144	int (arm_syscall_record) (struct regcache regcache, unsigned long svc_number);
97e03143 RE	145	};
97e03143 RE	146
cca44b1b JB	147	/* Structures used for displaced stepping. */
	148
	149	/* The maximum number of temporaries available for displaced instructions. */
	150	#define DISPLACED_TEMPS 16
	151	/* The maximum number of modified instructions generated for one single-stepped
	152	instruction, including the breakpoint (usually at the end of the instruction
	153	sequence) and any scratch words, etc. */
	154	#define DISPLACED_MODIFIED_INSNS 8
	155
	156	struct displaced_step_closure
	157	{
	158	ULONGEST tmp[DISPLACED_TEMPS];
	159	int rd;
	160	int wrote_to_pc;
	161	union
	162	{
	163	struct
	164	{
	165	int xfersize;
	166	int rn; /* Writeback register. */
	167	unsigned int immed : 1; /* Offset is immediate. */
	168	unsigned int writeback : 1; /* Perform base-register writeback. */
	169	unsigned int restore_r4 : 1; /* Used r4 as scratch. */
	170	} ldst;
	171
	172	struct
	173	{
	174	unsigned long dest;
	175	unsigned int link : 1;
	176	unsigned int exchange : 1;
	177	unsigned int cond : 4;
	178	} branch;
	179
	180	struct
	181	{
	182	unsigned int regmask;
	183	int rn;
	184	CORE_ADDR xfer_addr;
	185	unsigned int load : 1;
	186	unsigned int user : 1;
	187	unsigned int increment : 1;
	188	unsigned int before : 1;
	189	unsigned int writeback : 1;
	190	unsigned int cond : 4;
	191	} block;
	192
	193	struct
	194	{
	195	unsigned int immed : 1;
	196	} preload;
	197
	198	struct
	199	{
	200	/* If non-NULL, override generic SVC handling (e.g. for a particular
	201	OS). */
bd18283a	202	int (copy_svc_os) (struct gdbarch gdbarch, struct regcache *regs,
cca44b1b JB	203	struct displaced_step_closure *dsc);
	204	} svc;
	205	} u;
4db71c0b YQ	206
	207	/* The size of original instruction, 2 or 4. */
	208	unsigned int insn_size;
	209	/* True if the original insn (and thus all replacement insns) are Thumb
	210	instead of ARM. */
	211	unsigned int is_thumb;
	212
	213	/* The slots in the array is used in this way below,
	214	- ARM instruction occupies one slot,
	215	- Thumb 16 bit instruction occupies one slot,
	216	- Thumb 32-bit instruction occupies two slots, one part for each. */
cca44b1b JB	217	unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
	218	int numinsns;
	219	CORE_ADDR insn_addr;
	220	CORE_ADDR scratch_base;
	221	void (cleanup) (struct gdbarch , struct regcache *,
	222	struct displaced_step_closure *);
	223	};
	224
	225	/* Values for the WRITE_PC argument to displaced_write_reg. If the register
	226	write may write to the PC, specifies the way the CPSR T bit, etc. is
	227	modified by the instruction. */
	228
	229	enum pc_write_style
	230	{
	231	BRANCH_WRITE_PC,
	232	BX_WRITE_PC,
	233	LOAD_WRITE_PC,
	234	ALU_WRITE_PC,
	235	CANNOT_WRITE_PC
	236	};
	237
	238	extern void
b434a28f YQ	239	arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
b434a28f YQ	240	CORE_ADDR to, struct regcache *regs,
cca44b1b JB	241	struct displaced_step_closure *dsc);
	242	extern void
	243	arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
	244	CORE_ADDR to, struct displaced_step_closure *dsc);
	245	extern ULONGEST
36073a92 YQ	246	displaced_read_reg (struct regcache regs, struct displaced_step_closure dsc,
36073a92 YQ	247	int regno);
cca44b1b JB	248	extern void
	249	displaced_write_reg (struct regcache *regs,
	250	struct displaced_step_closure *dsc, int regno,
	251	ULONGEST val, enum pc_write_style write_pc);
7c00367c	252
6dc13412	253	CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
d9311bfa AT	254
	255	ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
	256	int len,
	257	int byte_order);
	258
	259	CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
	260	CORE_ADDR val);
	261
d9311bfa AT	262	int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);
d9311bfa AT	263
a0ff9e1a	264	std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
d0e59a68	265	int arm_is_thumb (struct regcache *regcache);
25b41d01	266	int arm_frame_is_thumb (struct frame_info *frame);
190dce09	267
cca44b1b JB	268	extern void arm_displaced_step_fixup (struct gdbarch *,
	269	struct displaced_step_closure *,
	270	CORE_ADDR, CORE_ADDR, struct regcache *);
	271
478fd957 UW	272	/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
	273	extern int arm_psr_thumb_bit (struct gdbarch *);
	274
e3039479 UW	275	/* Is the instruction at the given memory address a Thumb or ARM
	276	instruction? */
	277	extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
	278
72508ac0 PO	279	extern int arm_process_record (struct gdbarch *gdbarch,
72508ac0 PO	280	struct regcache *regcache, CORE_ADDR addr);
03b62bbb	281	/* Functions exported from arm-bsd-tdep.h. */
47ccd048 MK	282
	283	/* Return the appropriate register set for the core section identified
	284	by SECT_NAME and SECT_SIZE. */
	285
ed09174e AA	286	extern void
	287	armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
	288	iterate_over_regset_sections_cb *cb,
	289	void *cb_data,
	290	const struct regcache *regcache);
47ccd048	291
ef7e8358 UW	292	/* Target descriptions. */
	293	extern struct target_desc *tdesc_arm_with_m;
	294	extern struct target_desc *tdesc_arm_with_iwmmxt;
	295	extern struct target_desc *tdesc_arm_with_vfpv2;
	296	extern struct target_desc *tdesc_arm_with_vfpv3;
	297	extern struct target_desc *tdesc_arm_with_neon;
	298
47ccd048	299	#endif /* arm-tdep.h */