[deliverable/binutils-gdb.git] / gdb / arm-tdep.h

/* Common target dependent code for GDB on ARM systems.
   Copyright (C) 2002-2017 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef ARM_TDEP_H
#define ARM_TDEP_H

/* Forward declarations.  */
struct gdbarch;
struct regset;
struct address_space;
struct get_next_pcs;
struct arm_get_next_pcs;
struct gdb_get_next_pcs;

#include "arch/arm.h"
#include "infrun.h"

#include <vector>

/* Say how long FP registers are.  Used for documentation purposes and
   code readability in this header.  IEEE extended doubles are 80
   bits.  DWORD aligned they use 96 bits.  */
#define FP_REGISTER_SIZE	12

/* Say how long VFP double precision registers are.  Used for documentation
   purposes and code readability.  These are fixed at 64 bits.  */
#define VFP_REGISTER_SIZE	8

/* Number of machine registers.  The only define actually required 
   is gdbarch_num_regs.  The other definitions are used for documentation
   purposes and code readability.  */
/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
   (and called PS for processor status) so the status bits can be cleared
   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
   in PS.  */
#define NUM_FREGS	8	/* Number of floating point registers.  */
#define NUM_SREGS	2	/* Number of status registers.  */
#define NUM_GREGS	16	/* Number of general purpose registers.  */


/* Type of floating-point code in use by inferior.  There are really 3 models
   that are traditionally supported (plus the endianness issue), but gcc can
   only generate 2 of those.  The third is APCS_FLOAT, where arguments to
   functions are passed in floating-point registers.  

   In addition to the traditional models, VFP adds two more. 

   If you update this enum, don't forget to update fp_model_strings in 
   arm-tdep.c.  */

enum arm_float_model
{
  ARM_FLOAT_AUTO,	/* Automatic detection.  Do not set in tdep.  */
  ARM_FLOAT_SOFT_FPA,	/* Traditional soft-float (mixed-endian on LE ARM).  */
  ARM_FLOAT_FPA,	/* FPA co-processor.  GCC calling convention.  */
  ARM_FLOAT_SOFT_VFP,	/* Soft-float with pure-endian doubles.  */
  ARM_FLOAT_VFP,	/* Full VFP calling convention.  */
  ARM_FLOAT_LAST	/* Keep at end.  */
};

/* ABI used by the inferior.  */
enum arm_abi_kind
{
  ARM_ABI_AUTO,
  ARM_ABI_APCS,
  ARM_ABI_AAPCS,
  ARM_ABI_LAST
};

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Target-dependent structure in gdbarch.  */
struct gdbarch_tdep
{
  /* The ABI for this architecture.  It should never be set to
     ARM_ABI_AUTO.  */
  enum arm_abi_kind arm_abi;

  enum arm_float_model fp_model; /* Floating point calling conventions.  */

  int have_fpa_registers;	/* Does the target report the FPA registers?  */
  int have_wmmx_registers;	/* Does the target report the WMMX registers?  */
  /* The number of VFP registers reported by the target.  It is zero
     if VFP registers are not supported.  */
  int vfp_register_count;
  int have_vfp_pseudos;		/* Are we synthesizing the single precision
				   VFP registers?  */
  int have_neon_pseudos;	/* Are we synthesizing the quad precision
				   NEON registers?  Requires
				   have_vfp_pseudos.  */
  int have_neon;		/* Do we have a NEON unit?  */

  int is_m;			/* Does the target follow the "M" profile.  */
  CORE_ADDR lowest_pc;		/* Lowest address at which instructions 
				   will appear.  */

  const gdb_byte *arm_breakpoint;	/* Breakpoint pattern for an ARM insn.  */
  int arm_breakpoint_size;	/* And its size.  */
  const gdb_byte *thumb_breakpoint;	/* Breakpoint pattern for a Thumb insn.  */
  int thumb_breakpoint_size;	/* And its size.  */

  /* If the Thumb breakpoint is an undefined instruction (which is
     affected by IT blocks) rather than a BKPT instruction (which is
     not), then we need a 32-bit Thumb breakpoint to preserve the
     instruction count in IT blocks.  */
  const gdb_byte *thumb2_breakpoint;
  int thumb2_breakpoint_size;

  int jb_pc;			/* Offset to PC value in jump buffer.
				   If this is negative, longjmp support
				   will be disabled.  */
  size_t jb_elt_size;		/* And the size of each entry in the buf.  */

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* ISA-specific data types.  */
  struct type *arm_ext_type;
  struct type *neon_double_type;
  struct type *neon_quad_type;

   /* syscall record.  */
  int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
};

/* Structures used for displaced stepping.  */

/* The maximum number of temporaries available for displaced instructions.  */
#define DISPLACED_TEMPS			16
/* The maximum number of modified instructions generated for one single-stepped
   instruction, including the breakpoint (usually at the end of the instruction
   sequence) and any scratch words, etc.  */
#define DISPLACED_MODIFIED_INSNS	8

struct arm_displaced_step_closure : public displaced_step_closure
{
  ULONGEST tmp[DISPLACED_TEMPS];
  int rd;
  int wrote_to_pc;
  union
  {
    struct
    {
      int xfersize;
      int rn;			   /* Writeback register.  */
      unsigned int immed : 1;      /* Offset is immediate.  */
      unsigned int writeback : 1;  /* Perform base-register writeback.  */
      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
    } ldst;

    struct
    {
      unsigned long dest;
      unsigned int link : 1;
      unsigned int exchange : 1;
      unsigned int cond : 4;
    } branch;

    struct
    {
      unsigned int regmask;
      int rn;
      CORE_ADDR xfer_addr;
      unsigned int load : 1;
      unsigned int user : 1;
      unsigned int increment : 1;
      unsigned int before : 1;
      unsigned int writeback : 1;
      unsigned int cond : 4;
    } block;

    struct
    {
      unsigned int immed : 1;
    } preload;

    struct
    {
      /* If non-NULL, override generic SVC handling (e.g. for a particular
         OS).  */
      int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
			  arm_displaced_step_closure *dsc);
    } svc;
  } u;

  /* The size of original instruction, 2 or 4.  */
  unsigned int insn_size;
  /* True if the original insn (and thus all replacement insns) are Thumb
     instead of ARM.   */
  unsigned int is_thumb;

  /* The slots in the array is used in this way below,
     - ARM instruction occupies one slot,
     - Thumb 16 bit instruction occupies one slot,
     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
  unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
  int numinsns;
  CORE_ADDR insn_addr;
  CORE_ADDR scratch_base;
  void (*cleanup) (struct gdbarch *, struct regcache *,
		   arm_displaced_step_closure *);
};

/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
   write may write to the PC, specifies the way the CPSR T bit, etc. is
   modified by the instruction.  */

enum pc_write_style
{
  BRANCH_WRITE_PC,
  BX_WRITE_PC,
  LOAD_WRITE_PC,
  ALU_WRITE_PC,
  CANNOT_WRITE_PC
};

extern void
  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct regcache *regs,
			      arm_displaced_step_closure *dsc);
extern void
  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, arm_displaced_step_closure *dsc);
extern ULONGEST
  displaced_read_reg (struct regcache *regs, arm_displaced_step_closure *dsc,
		      int regno);
extern void
  displaced_write_reg (struct regcache *regs,
		       arm_displaced_step_closure *dsc, int regno,
		       ULONGEST val, enum pc_write_style write_pc);

CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);

ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
							int len,
							int byte_order);

CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
					     CORE_ADDR val);

int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);

std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
int arm_is_thumb (struct regcache *regcache);
int arm_frame_is_thumb (struct frame_info *frame);

extern void arm_displaced_step_fixup (struct gdbarch *,
				      struct displaced_step_closure *,
				      CORE_ADDR, CORE_ADDR, struct regcache *);

/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
extern int arm_psr_thumb_bit (struct gdbarch *);

/* Is the instruction at the given memory address a Thumb or ARM
   instruction?  */
extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);

extern int arm_process_record (struct gdbarch *gdbarch, 
                               struct regcache *regcache, CORE_ADDR addr);
/* Functions exported from arm-bsd-tdep.h.  */

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */

extern void
  armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
				       iterate_over_regset_sections_cb *cb,
				       void *cb_data,
				       const struct regcache *regcache);

/* Target descriptions.  */
extern struct target_desc *tdesc_arm_with_m;
extern struct target_desc *tdesc_arm_with_iwmmxt;
extern struct target_desc *tdesc_arm_with_vfpv2;
extern struct target_desc *tdesc_arm_with_vfpv3;
extern struct target_desc *tdesc_arm_with_neon;

#endif /* arm-tdep.h */
Commit	Line	Data
34e8f22d	1	/* Common target dependent code for GDB on ARM systems.
61baf725	2	Copyright (C) 2002-2017 Free Software Foundation, Inc.
34e8f22d RE	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
a9762ec7	8	the Free Software Foundation; either version 3 of the License, or
34e8f22d RE	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
a9762ec7	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
34e8f22d	18
47ccd048 MK	19	#ifndef ARM_TDEP_H
	20	#define ARM_TDEP_H
	21
cb587d83	22	/* Forward declarations. */
47ccd048	23	struct gdbarch;
cb587d83	24	struct regset;
3352110b	25	struct address_space;
d9311bfa AT	26	struct get_next_pcs;
	27	struct arm_get_next_pcs;
	28	struct gdb_get_next_pcs;
cb587d83	29
ec741292	30	#include "arch/arm.h"
cfba9872	31	#include "infrun.h"
34e8f22d	32
a0ff9e1a SM	33	#include <vector>
a0ff9e1a SM	34
34e8f22d RE	35	/* Say how long FP registers are. Used for documentation purposes and
	36	code readability in this header. IEEE extended doubles are 80
	37	bits. DWORD aligned they use 96 bits. */
7a5ea0d4	38	#define FP_REGISTER_SIZE 12
34e8f22d	39
3184d3f9 JL	40	/* Say how long VFP double precision registers are. Used for documentation
	41	purposes and code readability. These are fixed at 64 bits. */
	42	#define VFP_REGISTER_SIZE 8
	43
34e8f22d	44	/* Number of machine registers. The only define actually required
f57d151a	45	is gdbarch_num_regs. The other definitions are used for documentation
34e8f22d RE	46	purposes and code readability. */
	47	/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
	48	(and called PS for processor status) so the status bits can be cleared
	49	from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
	50	in PS. */
	51	#define NUM_FREGS 8 /* Number of floating point registers. */
	52	#define NUM_SREGS 2 /* Number of status registers. */
	53	#define NUM_GREGS 16 /* Number of general purpose registers. */
	54
	55
9779414d	56
08216dd7 RE	57	/* Type of floating-point code in use by inferior. There are really 3 models
	58	that are traditionally supported (plus the endianness issue), but gcc can
	59	only generate 2 of those. The third is APCS_FLOAT, where arguments to
	60	functions are passed in floating-point registers.
	61
fd50bc42 RE	62	In addition to the traditional models, VFP adds two more.
	63
	64	If you update this enum, don't forget to update fp_model_strings in
	65	arm-tdep.c. */
08216dd7 RE	66
	67	enum arm_float_model
	68	{
fd50bc42 RE	69	ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
	70	ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
	71	ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
	72	ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
	73	ARM_FLOAT_VFP, /* Full VFP calling convention. */
	74	ARM_FLOAT_LAST /* Keep at end. */
08216dd7 RE	75	};
08216dd7 RE	76
28e97307 DJ	77	/* ABI used by the inferior. */
	78	enum arm_abi_kind
	79	{
	80	ARM_ABI_AUTO,
	81	ARM_ABI_APCS,
	82	ARM_ABI_AAPCS,
	83	ARM_ABI_LAST
	84	};
fd50bc42	85
7c00367c MK	86	/* Convention for returning structures. */
	87
	88	enum struct_return
	89	{
	90	pcc_struct_return, /* Return "short" structures in memory. */
	91	reg_struct_return /* Return "short" structures in registers. */
	92	};
	93
97e03143 RE	94	/* Target-dependent structure in gdbarch. */
	95	struct gdbarch_tdep
	96	{
28e97307 DJ	97	/* The ABI for this architecture. It should never be set to
	98	ARM_ABI_AUTO. */
	99	enum arm_abi_kind arm_abi;
	100
08216dd7 RE	101	enum arm_float_model fp_model; /* Floating point calling conventions. */
08216dd7 RE	102
ff6f572f	103	int have_fpa_registers; /* Does the target report the FPA registers? */
a56cc1ce	104	int have_wmmx_registers; /* Does the target report the WMMX registers? */
330c6ca9 YQ	105	/* The number of VFP registers reported by the target. It is zero
	106	if VFP registers are not supported. */
	107	int vfp_register_count;
58d6951d DJ	108	int have_vfp_pseudos; /* Are we synthesizing the single precision
	109	VFP registers? */
	110	int have_neon_pseudos; /* Are we synthesizing the quad precision
	111	NEON registers? Requires
	112	have_vfp_pseudos. */
	113	int have_neon; /* Do we have a NEON unit? */
ff6f572f	114
9779414d	115	int is_m; /* Does the target follow the "M" profile. */
97e03143 RE	116	CORE_ADDR lowest_pc; /* Lowest address at which instructions
97e03143 RE	117	will appear. */
9df628e0	118
948f8e3d	119	const gdb_byte arm_breakpoint; / Breakpoint pattern for an ARM insn. */
9df628e0	120	int arm_breakpoint_size; /* And its size. */
948f8e3d	121	const gdb_byte thumb_breakpoint; / Breakpoint pattern for a Thumb insn. */
9df628e0 RE	122	int thumb_breakpoint_size; /* And its size. */
9df628e0 RE	123
177321bd DJ	124	/* If the Thumb breakpoint is an undefined instruction (which is
	125	affected by IT blocks) rather than a BKPT instruction (which is
	126	not), then we need a 32-bit Thumb breakpoint to preserve the
	127	instruction count in IT blocks. */
948f8e3d	128	const gdb_byte *thumb2_breakpoint;
177321bd DJ	129	int thumb2_breakpoint_size;
177321bd DJ	130
0963b4bd	131	int jb_pc; /* Offset to PC value in jump buffer.
9df628e0 RE	132	If this is negative, longjmp support
	133	will be disabled. */
	134	size_t jb_elt_size; /* And the size of each entry in the buf. */
cb587d83	135
7c00367c MK	136	/* Convention for returning structures. */
	137	enum struct_return struct_return;
	138
27067745 UW	139	/* ISA-specific data types. */
27067745 UW	140	struct type *arm_ext_type;
58d6951d DJ	141	struct type *neon_double_type;
58d6951d DJ	142	struct type *neon_quad_type;
25b41d01	143
97dfe206 OJ	144	/* syscall record. */
97dfe206 OJ	145	int (arm_syscall_record) (struct regcache regcache, unsigned long svc_number);
97e03143 RE	146	};
97e03143 RE	147
cca44b1b JB	148	/* Structures used for displaced stepping. */
	149
	150	/* The maximum number of temporaries available for displaced instructions. */
	151	#define DISPLACED_TEMPS 16
	152	/* The maximum number of modified instructions generated for one single-stepped
	153	instruction, including the breakpoint (usually at the end of the instruction
	154	sequence) and any scratch words, etc. */
	155	#define DISPLACED_MODIFIED_INSNS 8
	156
cfba9872	157	struct arm_displaced_step_closure : public displaced_step_closure
cca44b1b JB	158	{
	159	ULONGEST tmp[DISPLACED_TEMPS];
	160	int rd;
	161	int wrote_to_pc;
	162	union
	163	{
	164	struct
	165	{
	166	int xfersize;
	167	int rn; /* Writeback register. */
	168	unsigned int immed : 1; /* Offset is immediate. */
	169	unsigned int writeback : 1; /* Perform base-register writeback. */
	170	unsigned int restore_r4 : 1; /* Used r4 as scratch. */
	171	} ldst;
	172
	173	struct
	174	{
	175	unsigned long dest;
	176	unsigned int link : 1;
	177	unsigned int exchange : 1;
	178	unsigned int cond : 4;
	179	} branch;
	180
	181	struct
	182	{
	183	unsigned int regmask;
	184	int rn;
	185	CORE_ADDR xfer_addr;
	186	unsigned int load : 1;
	187	unsigned int user : 1;
	188	unsigned int increment : 1;
	189	unsigned int before : 1;
	190	unsigned int writeback : 1;
	191	unsigned int cond : 4;
	192	} block;
	193
	194	struct
	195	{
	196	unsigned int immed : 1;
	197	} preload;
	198
	199	struct
	200	{
	201	/* If non-NULL, override generic SVC handling (e.g. for a particular
	202	OS). */
bd18283a	203	int (copy_svc_os) (struct gdbarch gdbarch, struct regcache *regs,
cfba9872	204	arm_displaced_step_closure *dsc);
cca44b1b JB	205	} svc;
cca44b1b JB	206	} u;
4db71c0b YQ	207
	208	/* The size of original instruction, 2 or 4. */
	209	unsigned int insn_size;
	210	/* True if the original insn (and thus all replacement insns) are Thumb
	211	instead of ARM. */
	212	unsigned int is_thumb;
	213
	214	/* The slots in the array is used in this way below,
	215	- ARM instruction occupies one slot,
	216	- Thumb 16 bit instruction occupies one slot,
	217	- Thumb 32-bit instruction occupies two slots, one part for each. */
cca44b1b JB	218	unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
	219	int numinsns;
	220	CORE_ADDR insn_addr;
	221	CORE_ADDR scratch_base;
	222	void (cleanup) (struct gdbarch , struct regcache *,
cfba9872	223	arm_displaced_step_closure *);
cca44b1b JB	224	};
	225
	226	/* Values for the WRITE_PC argument to displaced_write_reg. If the register
	227	write may write to the PC, specifies the way the CPSR T bit, etc. is
	228	modified by the instruction. */
	229
	230	enum pc_write_style
	231	{
	232	BRANCH_WRITE_PC,
	233	BX_WRITE_PC,
	234	LOAD_WRITE_PC,
	235	ALU_WRITE_PC,
	236	CANNOT_WRITE_PC
	237	};
	238
	239	extern void
b434a28f YQ	240	arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
b434a28f YQ	241	CORE_ADDR to, struct regcache *regs,
cfba9872	242	arm_displaced_step_closure *dsc);
cca44b1b JB	243	extern void
cca44b1b JB	244	arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
cfba9872	245	CORE_ADDR to, arm_displaced_step_closure *dsc);
cca44b1b	246	extern ULONGEST
cfba9872	247	displaced_read_reg (struct regcache regs, arm_displaced_step_closure dsc,
36073a92	248	int regno);
cca44b1b JB	249	extern void
cca44b1b JB	250	displaced_write_reg (struct regcache *regs,
cfba9872	251	arm_displaced_step_closure *dsc, int regno,
cca44b1b	252	ULONGEST val, enum pc_write_style write_pc);
7c00367c	253
6dc13412	254	CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
d9311bfa AT	255
	256	ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
	257	int len,
	258	int byte_order);
	259
	260	CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
	261	CORE_ADDR val);
	262
d9311bfa AT	263	int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);
d9311bfa AT	264
a0ff9e1a	265	std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
d0e59a68	266	int arm_is_thumb (struct regcache *regcache);
25b41d01	267	int arm_frame_is_thumb (struct frame_info *frame);
190dce09	268
cca44b1b JB	269	extern void arm_displaced_step_fixup (struct gdbarch *,
	270	struct displaced_step_closure *,
	271	CORE_ADDR, CORE_ADDR, struct regcache *);
	272
478fd957 UW	273	/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
	274	extern int arm_psr_thumb_bit (struct gdbarch *);
	275
e3039479 UW	276	/* Is the instruction at the given memory address a Thumb or ARM
	277	instruction? */
	278	extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
	279
72508ac0 PO	280	extern int arm_process_record (struct gdbarch *gdbarch,
72508ac0 PO	281	struct regcache *regcache, CORE_ADDR addr);
03b62bbb	282	/* Functions exported from arm-bsd-tdep.h. */
47ccd048 MK	283
	284	/* Return the appropriate register set for the core section identified
	285	by SECT_NAME and SECT_SIZE. */
	286
ed09174e AA	287	extern void
	288	armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
	289	iterate_over_regset_sections_cb *cb,
	290	void *cb_data,
	291	const struct regcache *regcache);
47ccd048	292
ef7e8358 UW	293	/* Target descriptions. */
	294	extern struct target_desc *tdesc_arm_with_m;
	295	extern struct target_desc *tdesc_arm_with_iwmmxt;
	296	extern struct target_desc *tdesc_arm_with_vfpv2;
	297	extern struct target_desc *tdesc_arm_with_vfpv3;
	298	extern struct target_desc *tdesc_arm_with_neon;
	299
47ccd048	300	#endif /* arm-tdep.h */