[deliverable/binutils-gdb.git] / gdb / arm-tdep.h

/* Common target dependent code for GDB on ARM systems.
   Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010, 2011
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef ARM_TDEP_H
#define ARM_TDEP_H

/* Forward declarations.  */
struct gdbarch;
struct regset;

/* Register numbers of various important registers.  */

enum gdb_regnum {
  ARM_A1_REGNUM = 0,		/* first integer-like argument */
  ARM_A4_REGNUM = 3,		/* last integer-like argument */
  ARM_AP_REGNUM = 11,
  ARM_IP_REGNUM = 12,
  ARM_SP_REGNUM = 13,		/* Contains address of top of stack */
  ARM_LR_REGNUM = 14,		/* address to return to from a function call */
  ARM_PC_REGNUM = 15,		/* Contains program counter */
  ARM_F0_REGNUM = 16,		/* first floating point register */
  ARM_F3_REGNUM = 19,		/* last floating point argument register */
  ARM_F7_REGNUM = 23, 		/* last floating point register */
  ARM_FPS_REGNUM = 24,		/* floating point status register */
  ARM_PS_REGNUM = 25,		/* Contains processor status */
  ARM_WR0_REGNUM,		/* WMMX data registers.  */
  ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
  ARM_WC0_REGNUM,		/* WMMX control registers.  */
  ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
  ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
  ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
  ARM_WCGR0_REGNUM,		/* WMMX general purpose registers.  */
  ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
  ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
  ARM_D0_REGNUM,		/* VFP double-precision registers.  */
  ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
  ARM_FPSCR_REGNUM,

  ARM_NUM_REGS,

  /* Other useful registers.  */
  ARM_FP_REGNUM = 11,		/* Frame register in ARM code, if used.  */
  THUMB_FP_REGNUM = 7,		/* Frame register in Thumb code, if used.  */
  ARM_NUM_ARG_REGS = 4, 
  ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  ARM_NUM_FP_ARG_REGS = 4,
  ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
};

/* Size of integer registers.  */
#define INT_REGISTER_SIZE		4

/* Say how long FP registers are.  Used for documentation purposes and
   code readability in this header.  IEEE extended doubles are 80
   bits.  DWORD aligned they use 96 bits.  */
#define FP_REGISTER_SIZE	12

/* Number of machine registers.  The only define actually required 
   is gdbarch_num_regs.  The other definitions are used for documentation
   purposes and code readability.  */
/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
   (and called PS for processor status) so the status bits can be cleared
   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
   in PS.  */
#define NUM_FREGS	8	/* Number of floating point registers.  */
#define NUM_SREGS	2	/* Number of status registers.  */
#define NUM_GREGS	16	/* Number of general purpose registers.  */


/* Instruction condition field values.  */
#define INST_EQ		0x0
#define INST_NE		0x1
#define INST_CS		0x2
#define INST_CC		0x3
#define INST_MI		0x4
#define INST_PL		0x5
#define INST_VS		0x6
#define INST_VC		0x7
#define INST_HI		0x8
#define INST_LS		0x9
#define INST_GE		0xa
#define INST_LT		0xb
#define INST_GT		0xc
#define INST_LE		0xd
#define INST_AL		0xe
#define INST_NV		0xf

#define FLAG_N		0x80000000
#define FLAG_Z		0x40000000
#define FLAG_C		0x20000000
#define FLAG_V		0x10000000

#define CPSR_T		0x20

#define XPSR_T		0x01000000

/* Type of floating-point code in use by inferior.  There are really 3 models
   that are traditionally supported (plus the endianness issue), but gcc can
   only generate 2 of those.  The third is APCS_FLOAT, where arguments to
   functions are passed in floating-point registers.  

   In addition to the traditional models, VFP adds two more. 

   If you update this enum, don't forget to update fp_model_strings in 
   arm-tdep.c.  */

enum arm_float_model
{
  ARM_FLOAT_AUTO,	/* Automatic detection.  Do not set in tdep.  */
  ARM_FLOAT_SOFT_FPA,	/* Traditional soft-float (mixed-endian on LE ARM).  */
  ARM_FLOAT_FPA,	/* FPA co-processor.  GCC calling convention.  */
  ARM_FLOAT_SOFT_VFP,	/* Soft-float with pure-endian doubles.  */
  ARM_FLOAT_VFP,	/* Full VFP calling convention.  */
  ARM_FLOAT_LAST	/* Keep at end.  */
};

/* ABI used by the inferior.  */
enum arm_abi_kind
{
  ARM_ABI_AUTO,
  ARM_ABI_APCS,
  ARM_ABI_AAPCS,
  ARM_ABI_LAST
};

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Target-dependent structure in gdbarch.  */
struct gdbarch_tdep
{
  /* The ABI for this architecture.  It should never be set to
     ARM_ABI_AUTO.  */
  enum arm_abi_kind arm_abi;

  enum arm_float_model fp_model; /* Floating point calling conventions.  */

  int have_fpa_registers;	/* Does the target report the FPA registers?  */
  int have_vfp_registers;	/* Does the target report the VFP registers?  */
  int have_vfp_pseudos;		/* Are we synthesizing the single precision
				   VFP registers?  */
  int have_neon_pseudos;	/* Are we synthesizing the quad precision
				   NEON registers?  Requires
				   have_vfp_pseudos.  */
  int have_neon;		/* Do we have a NEON unit?  */

  int is_m;			/* Does the target follow the "M" profile.  */
  CORE_ADDR lowest_pc;		/* Lowest address at which instructions 
				   will appear.  */

  const char *arm_breakpoint;	/* Breakpoint pattern for an ARM insn.  */
  int arm_breakpoint_size;	/* And its size.  */
  const char *thumb_breakpoint;	/* Breakpoint pattern for a Thumb insn.  */
  int thumb_breakpoint_size;	/* And its size.  */

  /* If the Thumb breakpoint is an undefined instruction (which is
     affected by IT blocks) rather than a BKPT instruction (which is
     not), then we need a 32-bit Thumb breakpoint to preserve the
     instruction count in IT blocks.  */
  const char *thumb2_breakpoint;
  int thumb2_breakpoint_size;

  int jb_pc;			/* Offset to PC value in jump buffer.
				   If this is negative, longjmp support
				   will be disabled.  */
  size_t jb_elt_size;		/* And the size of each entry in the buf.  */

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* Cached core file helpers.  */
  struct regset *gregset, *fpregset;

  /* ISA-specific data types.  */
  struct type *arm_ext_type;
  struct type *neon_double_type;
  struct type *neon_quad_type;

  /* Return the expected next PC if FRAME is stopped at a syscall
     instruction.  */
  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
};

/* Structures used for displaced stepping.  */

/* The maximum number of temporaries available for displaced instructions.  */
#define DISPLACED_TEMPS			16
/* The maximum number of modified instructions generated for one single-stepped
   instruction, including the breakpoint (usually at the end of the instruction
   sequence) and any scratch words, etc.  */
#define DISPLACED_MODIFIED_INSNS	8

struct displaced_step_closure
{
  ULONGEST tmp[DISPLACED_TEMPS];
  int rd;
  int wrote_to_pc;
  union
  {
    struct
    {
      int xfersize;
      int rn;			   /* Writeback register.  */
      unsigned int immed : 1;      /* Offset is immediate.  */
      unsigned int writeback : 1;  /* Perform base-register writeback.  */
      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
    } ldst;

    struct
    {
      unsigned long dest;
      unsigned int link : 1;
      unsigned int exchange : 1;
      unsigned int cond : 4;
    } branch;

    struct
    {
      unsigned int regmask;
      int rn;
      CORE_ADDR xfer_addr;
      unsigned int load : 1;
      unsigned int user : 1;
      unsigned int increment : 1;
      unsigned int before : 1;
      unsigned int writeback : 1;
      unsigned int cond : 4;
    } block;

    struct
    {
      unsigned int immed : 1;
    } preload;

    struct
    {
      /* If non-NULL, override generic SVC handling (e.g. for a particular
         OS).  */
      int (*copy_svc_os) (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
			  struct regcache *regs,
			  struct displaced_step_closure *dsc);
    } svc;
  } u;

  /* The size of original instruction, 2 or 4.  */
  unsigned int insn_size;
  /* True if the original insn (and thus all replacement insns) are Thumb
     instead of ARM.   */
  unsigned int is_thumb;

  /* The slots in the array is used in this way below,
     - ARM instruction occupies one slot,
     - Thumb 16 bit instruction occupies one slot,
     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
  unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
  int numinsns;
  CORE_ADDR insn_addr;
  CORE_ADDR scratch_base;
  void (*cleanup) (struct gdbarch *, struct regcache *,
		   struct displaced_step_closure *);
};

/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
   write may write to the PC, specifies the way the CPSR T bit, etc. is
   modified by the instruction.  */

enum pc_write_style
{
  BRANCH_WRITE_PC,
  BX_WRITE_PC,
  LOAD_WRITE_PC,
  ALU_WRITE_PC,
  CANNOT_WRITE_PC
};

extern void
  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct regcache *regs,
			      struct displaced_step_closure *dsc);
extern void
  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct displaced_step_closure *dsc);
extern ULONGEST
  displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
		      int regno);
extern void
  displaced_write_reg (struct regcache *regs,
		       struct displaced_step_closure *dsc, int regno,
		       ULONGEST val, enum pc_write_style write_pc);

CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
void arm_insert_single_step_breakpoint (struct gdbarch *,
					struct address_space *, CORE_ADDR);
int arm_software_single_step (struct frame_info *);
int arm_frame_is_thumb (struct frame_info *frame);

extern struct displaced_step_closure *
  arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
				struct regcache *);
extern void arm_displaced_step_fixup (struct gdbarch *,
				      struct displaced_step_closure *,
				      CORE_ADDR, CORE_ADDR, struct regcache *);

/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
extern int arm_psr_thumb_bit (struct gdbarch *);

/* Is the instruction at the given memory address a Thumb or ARM
   instruction?  */
extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);

/* Functions exported from armbsd-tdep.h.  */

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */

extern const struct regset *
  armbsd_regset_from_core_section (struct gdbarch *gdbarch,
				   const char *sect_name, size_t sect_size);

#endif /* arm-tdep.h */
Commit	Line	Data
34e8f22d	1	/* Common target dependent code for GDB on ARM systems.
7b6bb8da	2	Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010, 2011
4c38e0a4	3	Free Software Foundation, Inc.
34e8f22d RE	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
a9762ec7	9	the Free Software Foundation; either version 3 of the License, or
34e8f22d RE	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
a9762ec7	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
34e8f22d	19
47ccd048 MK	20	#ifndef ARM_TDEP_H
	21	#define ARM_TDEP_H
	22
cb587d83	23	/* Forward declarations. */
47ccd048	24	struct gdbarch;
cb587d83 DJ	25	struct regset;
cb587d83 DJ	26
7157eed4	27	/* Register numbers of various important registers. */
34e8f22d	28
47a73475 MS	29	enum gdb_regnum {
	30	ARM_A1_REGNUM = 0, /* first integer-like argument */
	31	ARM_A4_REGNUM = 3, /* last integer-like argument */
	32	ARM_AP_REGNUM = 11,
4be43953	33	ARM_IP_REGNUM = 12,
47a73475 MS	34	ARM_SP_REGNUM = 13, /* Contains address of top of stack */
	35	ARM_LR_REGNUM = 14, /* address to return to from a function call */
	36	ARM_PC_REGNUM = 15, /* Contains program counter */
	37	ARM_F0_REGNUM = 16, /* first floating point register */
	38	ARM_F3_REGNUM = 19, /* last floating point argument register */
	39	ARM_F7_REGNUM = 23, /* last floating point register */
	40	ARM_FPS_REGNUM = 24, /* floating point status register */
	41	ARM_PS_REGNUM = 25, /* Contains processor status */
ff6f572f DJ	42	ARM_WR0_REGNUM, /* WMMX data registers. */
	43	ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
	44	ARM_WC0_REGNUM, /* WMMX control registers. */
	45	ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
	46	ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
	47	ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
	48	ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
	49	ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
	50	ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
58d6951d DJ	51	ARM_D0_REGNUM, /* VFP double-precision registers. */
58d6951d DJ	52	ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
3b273a55	53	ARM_FPSCR_REGNUM,
ff6f572f DJ	54
	55	ARM_NUM_REGS,
	56
	57	/* Other useful registers. */
47a73475 MS	58	ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
	59	THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
	60	ARM_NUM_ARG_REGS = 4,
	61	ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
	62	ARM_NUM_FP_ARG_REGS = 4,
	63	ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
	64	};
34e8f22d	65
34e8f22d	66	/* Size of integer registers. */
7a5ea0d4	67	#define INT_REGISTER_SIZE 4
34e8f22d RE	68
	69	/* Say how long FP registers are. Used for documentation purposes and
	70	code readability in this header. IEEE extended doubles are 80
	71	bits. DWORD aligned they use 96 bits. */
7a5ea0d4	72	#define FP_REGISTER_SIZE 12
34e8f22d	73
34e8f22d	74	/* Number of machine registers. The only define actually required
f57d151a	75	is gdbarch_num_regs. The other definitions are used for documentation
34e8f22d RE	76	purposes and code readability. */
	77	/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
	78	(and called PS for processor status) so the status bits can be cleared
	79	from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
	80	in PS. */
	81	#define NUM_FREGS 8 /* Number of floating point registers. */
	82	#define NUM_SREGS 2 /* Number of status registers. */
	83	#define NUM_GREGS 16 /* Number of general purpose registers. */
	84
	85
	86	/* Instruction condition field values. */
	87	#define INST_EQ 0x0
	88	#define INST_NE 0x1
	89	#define INST_CS 0x2
	90	#define INST_CC 0x3
	91	#define INST_MI 0x4
	92	#define INST_PL 0x5
	93	#define INST_VS 0x6
	94	#define INST_VC 0x7
	95	#define INST_HI 0x8
	96	#define INST_LS 0x9
	97	#define INST_GE 0xa
	98	#define INST_LT 0xb
	99	#define INST_GT 0xc
	100	#define INST_LE 0xd
	101	#define INST_AL 0xe
	102	#define INST_NV 0xf
	103
	104	#define FLAG_N 0x80000000
	105	#define FLAG_Z 0x40000000
	106	#define FLAG_C 0x20000000
	107	#define FLAG_V 0x10000000
	108
b39cc962 DJ	109	#define CPSR_T 0x20
b39cc962 DJ	110
9779414d DJ	111	#define XPSR_T 0x01000000
9779414d DJ	112
08216dd7 RE	113	/* Type of floating-point code in use by inferior. There are really 3 models
	114	that are traditionally supported (plus the endianness issue), but gcc can
	115	only generate 2 of those. The third is APCS_FLOAT, where arguments to
	116	functions are passed in floating-point registers.
	117
fd50bc42 RE	118	In addition to the traditional models, VFP adds two more.
	119
	120	If you update this enum, don't forget to update fp_model_strings in
	121	arm-tdep.c. */
08216dd7 RE	122
	123	enum arm_float_model
	124	{
fd50bc42 RE	125	ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
	126	ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
	127	ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
	128	ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
	129	ARM_FLOAT_VFP, /* Full VFP calling convention. */
	130	ARM_FLOAT_LAST /* Keep at end. */
08216dd7 RE	131	};
08216dd7 RE	132
28e97307 DJ	133	/* ABI used by the inferior. */
	134	enum arm_abi_kind
	135	{
	136	ARM_ABI_AUTO,
	137	ARM_ABI_APCS,
	138	ARM_ABI_AAPCS,
	139	ARM_ABI_LAST
	140	};
fd50bc42	141
7c00367c MK	142	/* Convention for returning structures. */
	143
	144	enum struct_return
	145	{
	146	pcc_struct_return, /* Return "short" structures in memory. */
	147	reg_struct_return /* Return "short" structures in registers. */
	148	};
	149
97e03143 RE	150	/* Target-dependent structure in gdbarch. */
	151	struct gdbarch_tdep
	152	{
28e97307 DJ	153	/* The ABI for this architecture. It should never be set to
	154	ARM_ABI_AUTO. */
	155	enum arm_abi_kind arm_abi;
	156
08216dd7 RE	157	enum arm_float_model fp_model; /* Floating point calling conventions. */
08216dd7 RE	158
ff6f572f	159	int have_fpa_registers; /* Does the target report the FPA registers? */
58d6951d DJ	160	int have_vfp_registers; /* Does the target report the VFP registers? */
	161	int have_vfp_pseudos; /* Are we synthesizing the single precision
	162	VFP registers? */
	163	int have_neon_pseudos; /* Are we synthesizing the quad precision
	164	NEON registers? Requires
	165	have_vfp_pseudos. */
	166	int have_neon; /* Do we have a NEON unit? */
ff6f572f	167
9779414d	168	int is_m; /* Does the target follow the "M" profile. */
97e03143 RE	169	CORE_ADDR lowest_pc; /* Lowest address at which instructions
97e03143 RE	170	will appear. */
9df628e0 RE	171
	172	const char arm_breakpoint; / Breakpoint pattern for an ARM insn. */
	173	int arm_breakpoint_size; /* And its size. */
177321bd	174	const char thumb_breakpoint; / Breakpoint pattern for a Thumb insn. */
9df628e0 RE	175	int thumb_breakpoint_size; /* And its size. */
9df628e0 RE	176
177321bd DJ	177	/* If the Thumb breakpoint is an undefined instruction (which is
	178	affected by IT blocks) rather than a BKPT instruction (which is
	179	not), then we need a 32-bit Thumb breakpoint to preserve the
	180	instruction count in IT blocks. */
	181	const char *thumb2_breakpoint;
	182	int thumb2_breakpoint_size;
	183
0963b4bd	184	int jb_pc; /* Offset to PC value in jump buffer.
9df628e0 RE	185	If this is negative, longjmp support
	186	will be disabled. */
	187	size_t jb_elt_size; /* And the size of each entry in the buf. */
cb587d83	188
7c00367c MK	189	/* Convention for returning structures. */
	190	enum struct_return struct_return;
	191
cb587d83 DJ	192	/* Cached core file helpers. */
cb587d83 DJ	193	struct regset gregset, fpregset;
27067745 UW	194
	195	/* ISA-specific data types. */
	196	struct type *arm_ext_type;
58d6951d DJ	197	struct type *neon_double_type;
58d6951d DJ	198	struct type *neon_quad_type;
25b41d01 YQ	199
	200	/* Return the expected next PC if FRAME is stopped at a syscall
	201	instruction. */
	202	CORE_ADDR (syscall_next_pc) (struct frame_info frame);
97e03143 RE	203	};
97e03143 RE	204
cca44b1b JB	205	/* Structures used for displaced stepping. */
	206
	207	/* The maximum number of temporaries available for displaced instructions. */
	208	#define DISPLACED_TEMPS 16
	209	/* The maximum number of modified instructions generated for one single-stepped
	210	instruction, including the breakpoint (usually at the end of the instruction
	211	sequence) and any scratch words, etc. */
	212	#define DISPLACED_MODIFIED_INSNS 8
	213
	214	struct displaced_step_closure
	215	{
	216	ULONGEST tmp[DISPLACED_TEMPS];
	217	int rd;
	218	int wrote_to_pc;
	219	union
	220	{
	221	struct
	222	{
	223	int xfersize;
	224	int rn; /* Writeback register. */
	225	unsigned int immed : 1; /* Offset is immediate. */
	226	unsigned int writeback : 1; /* Perform base-register writeback. */
	227	unsigned int restore_r4 : 1; /* Used r4 as scratch. */
	228	} ldst;
	229
	230	struct
	231	{
	232	unsigned long dest;
	233	unsigned int link : 1;
	234	unsigned int exchange : 1;
	235	unsigned int cond : 4;
	236	} branch;
	237
	238	struct
	239	{
	240	unsigned int regmask;
	241	int rn;
	242	CORE_ADDR xfer_addr;
	243	unsigned int load : 1;
	244	unsigned int user : 1;
	245	unsigned int increment : 1;
	246	unsigned int before : 1;
	247	unsigned int writeback : 1;
	248	unsigned int cond : 4;
	249	} block;
	250
	251	struct
	252	{
	253	unsigned int immed : 1;
	254	} preload;
	255
	256	struct
	257	{
	258	/* If non-NULL, override generic SVC handling (e.g. for a particular
	259	OS). */
	260	int (copy_svc_os) (struct gdbarch gdbarch, uint32_t insn, CORE_ADDR to,
	261	struct regcache *regs,
	262	struct displaced_step_closure *dsc);
	263	} svc;
	264	} u;
4db71c0b YQ	265
	266	/* The size of original instruction, 2 or 4. */
	267	unsigned int insn_size;
	268	/* True if the original insn (and thus all replacement insns) are Thumb
	269	instead of ARM. */
	270	unsigned int is_thumb;
	271
	272	/* The slots in the array is used in this way below,
	273	- ARM instruction occupies one slot,
	274	- Thumb 16 bit instruction occupies one slot,
	275	- Thumb 32-bit instruction occupies two slots, one part for each. */
cca44b1b JB	276	unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
	277	int numinsns;
	278	CORE_ADDR insn_addr;
	279	CORE_ADDR scratch_base;
	280	void (cleanup) (struct gdbarch , struct regcache *,
	281	struct displaced_step_closure *);
	282	};
	283
	284	/* Values for the WRITE_PC argument to displaced_write_reg. If the register
	285	write may write to the PC, specifies the way the CPSR T bit, etc. is
	286	modified by the instruction. */
	287
	288	enum pc_write_style
	289	{
	290	BRANCH_WRITE_PC,
	291	BX_WRITE_PC,
	292	LOAD_WRITE_PC,
	293	ALU_WRITE_PC,
	294	CANNOT_WRITE_PC
	295	};
	296
	297	extern void
b434a28f YQ	298	arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
b434a28f YQ	299	CORE_ADDR to, struct regcache *regs,
cca44b1b JB	300	struct displaced_step_closure *dsc);
	301	extern void
	302	arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
	303	CORE_ADDR to, struct displaced_step_closure *dsc);
	304	extern ULONGEST
36073a92 YQ	305	displaced_read_reg (struct regcache regs, struct displaced_step_closure dsc,
36073a92 YQ	306	int regno);
cca44b1b JB	307	extern void
	308	displaced_write_reg (struct regcache *regs,
	309	struct displaced_step_closure *dsc, int regno,
	310	ULONGEST val, enum pc_write_style write_pc);
7c00367c	311
6dc13412	312	CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
daddc3c1	313	CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
18819fa6 UW	314	void arm_insert_single_step_breakpoint (struct gdbarch *,
18819fa6 UW	315	struct address_space *, CORE_ADDR);
0b1b3e42	316	int arm_software_single_step (struct frame_info *);
25b41d01	317	int arm_frame_is_thumb (struct frame_info *frame);
190dce09	318
cca44b1b JB	319	extern struct displaced_step_closure *
	320	arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
	321	struct regcache *);
	322	extern void arm_displaced_step_fixup (struct gdbarch *,
	323	struct displaced_step_closure *,
	324	CORE_ADDR, CORE_ADDR, struct regcache *);
	325
478fd957 UW	326	/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
	327	extern int arm_psr_thumb_bit (struct gdbarch *);
	328
e3039479 UW	329	/* Is the instruction at the given memory address a Thumb or ARM
	330	instruction? */
	331	extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
	332
47ccd048 MK	333	/* Functions exported from armbsd-tdep.h. */
	334
	335	/* Return the appropriate register set for the core section identified
	336	by SECT_NAME and SECT_SIZE. */
	337
	338	extern const struct regset *
	339	armbsd_regset_from_core_section (struct gdbarch *gdbarch,
	340	const char *sect_name, size_t sect_size);
	341
	342	#endif /* arm-tdep.h */