[deliverable/binutils-gdb.git] / gdb / armnbsd-nat.c

/* Native-dependent code for BSD Unix running on ARM's, for GDB.

   Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 1999, 2002, 2004, 2007
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street, Fifth Floor,
   Boston, MA 02110-1301, USA.  */

#include "defs.h"
#include "gdbcore.h"
#include "inferior.h"
#include "regcache.h"
#include "target.h"

#include "gdb_string.h"
#include <sys/types.h>
#include <sys/ptrace.h>
#include <machine/reg.h>
#include <machine/frame.h>

#include "arm-tdep.h"
#include "inf-ptrace.h"

extern int arm_apcs_32;

static void
supply_gregset (struct reg *gregset)
{
  int regno;
  CORE_ADDR r_pc;

  /* Integer registers.  */
  for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++)
    regcache_raw_supply (current_regcache, regno, (char *) &gregset->r[regno]);

  regcache_raw_supply (current_regcache, ARM_SP_REGNUM,
		       (char *) &gregset->r_sp);
  regcache_raw_supply (current_regcache, ARM_LR_REGNUM,
		       (char *) &gregset->r_lr);
  /* This is ok: we're running native...  */
  r_pc = ADDR_BITS_REMOVE (gregset->r_pc);
  regcache_raw_supply (current_regcache, ARM_PC_REGNUM, (char *) &r_pc);

  if (arm_apcs_32)
    regcache_raw_supply (current_regcache, ARM_PS_REGNUM,
			 (char *) &gregset->r_cpsr);
  else
    regcache_raw_supply (current_regcache, ARM_PS_REGNUM,
			 (char *) &gregset->r_pc);
}

static void
supply_fparegset (struct fpreg *fparegset)
{
  int regno;

  for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++)
    regcache_raw_supply (current_regcache, regno,
			 (char *) &fparegset->fpr[regno - ARM_F0_REGNUM]);

  regcache_raw_supply (current_regcache, ARM_FPS_REGNUM,
		       (char *) &fparegset->fpr_fpsr);
}

static void
fetch_register (int regno)
{
  struct reg inferior_registers;
  int ret;

  ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid),
		(PTRACE_TYPE_ARG3) &inferior_registers, 0);

  if (ret < 0)
    {
      warning (_("unable to fetch general register"));
      return;
    }

  switch (regno)
    {
    case ARM_SP_REGNUM:
      regcache_raw_supply (current_regcache, ARM_SP_REGNUM,
			   (char *) &inferior_registers.r_sp);
      break;

    case ARM_LR_REGNUM:
      regcache_raw_supply (current_regcache, ARM_LR_REGNUM,
			   (char *) &inferior_registers.r_lr);
      break;

    case ARM_PC_REGNUM:
      /* This is ok: we're running native... */
      inferior_registers.r_pc = ADDR_BITS_REMOVE (inferior_registers.r_pc);
      regcache_raw_supply (current_regcache, ARM_PC_REGNUM,
			   (char *) &inferior_registers.r_pc);
      break;

    case ARM_PS_REGNUM:
      if (arm_apcs_32)
	regcache_raw_supply (current_regcache, ARM_PS_REGNUM,
			     (char *) &inferior_registers.r_cpsr);
      else
	regcache_raw_supply (current_regcache, ARM_PS_REGNUM,
			     (char *) &inferior_registers.r_pc);
      break;

    default:
      regcache_raw_supply (current_regcache, regno,
			   (char *) &inferior_registers.r[regno]);
      break;
    }
}

static void
fetch_regs (void)
{
  struct reg inferior_registers;
  int ret;
  int regno;

  ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid),
		(PTRACE_TYPE_ARG3) &inferior_registers, 0);

  if (ret < 0)
    {
      warning (_("unable to fetch general registers"));
      return;
    }

  supply_gregset (&inferior_registers);
}

static void
fetch_fp_register (int regno)
{
  struct fpreg inferior_fp_registers;
  int ret;

  ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid),
		(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);

  if (ret < 0)
    {
      warning (_("unable to fetch floating-point register"));
      return;
    }

  switch (regno)
    {
    case ARM_FPS_REGNUM:
      regcache_raw_supply (current_regcache, ARM_FPS_REGNUM,
			   (char *) &inferior_fp_registers.fpr_fpsr);
      break;

    default:
      regcache_raw_supply (current_regcache, regno,
			   (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]);
      break;
    }
}

static void
fetch_fp_regs (void)
{
  struct fpreg inferior_fp_registers;
  int ret;
  int regno;

  ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid),
		(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);

  if (ret < 0)
    {
      warning (_("unable to fetch general registers"));
      return;
    }

  supply_fparegset (&inferior_fp_registers);
}

static void
armnbsd_fetch_registers (int regno)
{
  if (regno >= 0)
    {
      if (regno < ARM_F0_REGNUM || regno > ARM_FPS_REGNUM)
	fetch_register (regno);
      else
	fetch_fp_register (regno);
    }
  else
    {
      fetch_regs ();
      fetch_fp_regs ();
    }
}


static void
store_register (int regno)
{
  struct reg inferior_registers;
  int ret;

  ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid),
		(PTRACE_TYPE_ARG3) &inferior_registers, 0);

  if (ret < 0)
    {
      warning (_("unable to fetch general registers"));
      return;
    }

  switch (regno)
    {
    case ARM_SP_REGNUM:
      regcache_raw_collect (current_regcache, ARM_SP_REGNUM,
			    (char *) &inferior_registers.r_sp);
      break;

    case ARM_LR_REGNUM:
      regcache_raw_collect (current_regcache, ARM_LR_REGNUM,
			    (char *) &inferior_registers.r_lr);
      break;

    case ARM_PC_REGNUM:
      if (arm_apcs_32)
	regcache_raw_collect (current_regcache, ARM_PC_REGNUM,
			      (char *) &inferior_registers.r_pc);
      else
	{
	  unsigned pc_val;

	  regcache_raw_collect (current_regcache, ARM_PC_REGNUM,
				(char *) &pc_val);
	  
	  pc_val = ADDR_BITS_REMOVE (pc_val);
	  inferior_registers.r_pc
	    ^= ADDR_BITS_REMOVE (inferior_registers.r_pc);
	  inferior_registers.r_pc |= pc_val;
	}
      break;

    case ARM_PS_REGNUM:
      if (arm_apcs_32)
	regcache_raw_collect (current_regcache, ARM_PS_REGNUM,
			      (char *) &inferior_registers.r_cpsr);
      else
	{
	  unsigned psr_val;

	  regcache_raw_collect (current_regcache, ARM_PS_REGNUM,
				(char *) &psr_val);

	  psr_val ^= ADDR_BITS_REMOVE (psr_val);
	  inferior_registers.r_pc = ADDR_BITS_REMOVE (inferior_registers.r_pc);
	  inferior_registers.r_pc |= psr_val;
	}
      break;

    default:
      regcache_raw_collect (current_regcache, regno,
			    (char *) &inferior_registers.r[regno]);
      break;
    }

  ret = ptrace (PT_SETREGS, PIDGET (inferior_ptid),
		(PTRACE_TYPE_ARG3) &inferior_registers, 0);

  if (ret < 0)
    warning (_("unable to write register %d to inferior"), regno);
}

static void
store_regs (void)
{
  struct reg inferior_registers;
  int ret;
  int regno;


  for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++)
    regcache_raw_collect (current_regcache, regno,
			  (char *) &inferior_registers.r[regno]);

  regcache_raw_collect (current_regcache, ARM_SP_REGNUM,
			(char *) &inferior_registers.r_sp);
  regcache_raw_collect (current_regcache, ARM_LR_REGNUM,
			(char *) &inferior_registers.r_lr);

  if (arm_apcs_32)
    {
      regcache_raw_collect (current_regcache, ARM_PC_REGNUM,
			    (char *) &inferior_registers.r_pc);
      regcache_raw_collect (current_regcache, ARM_PS_REGNUM,
			    (char *) &inferior_registers.r_cpsr);
    }
  else
    {
      unsigned pc_val;
      unsigned psr_val;

      regcache_raw_collect (current_regcache, ARM_PC_REGNUM,
			    (char *) &pc_val);
      regcache_raw_collect (current_regcache, ARM_PS_REGNUM,
			    (char *) &psr_val);
	  
      pc_val = ADDR_BITS_REMOVE (pc_val);
      psr_val ^= ADDR_BITS_REMOVE (psr_val);

      inferior_registers.r_pc = pc_val | psr_val;
    }

  ret = ptrace (PT_SETREGS, PIDGET (inferior_ptid),
		(PTRACE_TYPE_ARG3) &inferior_registers, 0);

  if (ret < 0)
    warning (_("unable to store general registers"));
}

static void
store_fp_register (int regno)
{
  struct fpreg inferior_fp_registers;
  int ret;

  ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid),
		(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);

  if (ret < 0)
    {
      warning (_("unable to fetch floating-point registers"));
      return;
    }

  switch (regno)
    {
    case ARM_FPS_REGNUM:
      regcache_raw_collect (current_regcache, ARM_FPS_REGNUM,
			    (char *) &inferior_fp_registers.fpr_fpsr);
      break;

    default:
      regcache_raw_collect (current_regcache, regno,
			    (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]);
      break;
    }

  ret = ptrace (PT_SETFPREGS, PIDGET (inferior_ptid),
		(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);

  if (ret < 0)
    warning (_("unable to write register %d to inferior"), regno);
}

static void
store_fp_regs (void)
{
  struct fpreg inferior_fp_registers;
  int ret;
  int regno;


  for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++)
    regcache_raw_collect (current_regcache, regno,
			  (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]);

  regcache_raw_collect (current_regcache, ARM_FPS_REGNUM,
			(char *) &inferior_fp_registers.fpr_fpsr);

  ret = ptrace (PT_SETFPREGS, PIDGET (inferior_ptid),
		(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);

  if (ret < 0)
    warning (_("unable to store floating-point registers"));
}

static void
armnbsd_store_registers (int regno)
{
  if (regno >= 0)
    {
      if (regno < ARM_F0_REGNUM || regno > ARM_FPS_REGNUM)
	store_register (regno);
      else
	store_fp_register (regno);
    }
  else
    {
      store_regs ();
      store_fp_regs ();
    }
}

struct md_core
{
  struct reg intreg;
  struct fpreg freg;
};

static void
fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
		      int which, CORE_ADDR ignore)
{
  struct md_core *core_reg = (struct md_core *) core_reg_sect;
  int regno;
  CORE_ADDR r_pc;

  supply_gregset (&core_reg->intreg);
  supply_fparegset (&core_reg->freg);
}

static void
fetch_elfcore_registers (char *core_reg_sect, unsigned core_reg_size,
			 int which, CORE_ADDR ignore)
{
  struct reg gregset;
  struct fpreg fparegset;

  switch (which)
    {
    case 0:	/* Integer registers.  */
      if (core_reg_size != sizeof (struct reg))
	warning (_("wrong size of register set in core file"));
      else
	{
	  /* The memcpy may be unnecessary, but we can't really be sure
	     of the alignment of the data in the core file.  */
	  memcpy (&gregset, core_reg_sect, sizeof (gregset));
	  supply_gregset (&gregset);
	}
      break;

    case 2:
      if (core_reg_size != sizeof (struct fpreg))
	warning (_("wrong size of FPA register set in core file"));
      else
	{
	  /* The memcpy may be unnecessary, but we can't really be sure
	     of the alignment of the data in the core file.  */
	  memcpy (&fparegset, core_reg_sect, sizeof (fparegset));
	  supply_fparegset (&fparegset);
	}
      break;

    default:
      /* Don't know what kind of register request this is; just ignore it.  */
      break;
    }
}

static struct core_fns arm_netbsd_core_fns =
{
  bfd_target_unknown_flavour,		/* core_flovour.  */
  default_check_format,			/* check_format.  */
  default_core_sniffer,			/* core_sniffer.  */
  fetch_core_registers,			/* core_read_registers.  */
  NULL
};

static struct core_fns arm_netbsd_elfcore_fns =
{
  bfd_target_elf_flavour,		/* core_flovour.  */
  default_check_format,			/* check_format.  */
  default_core_sniffer,			/* core_sniffer.  */
  fetch_elfcore_registers,		/* core_read_registers.  */
  NULL
};

void
_initialize_arm_netbsd_nat (void)
{
  struct target_ops *t;

  t = inf_ptrace_target ();
  t->to_fetch_registers = armnbsd_fetch_registers;
  t->to_store_registers = armnbsd_store_registers;
  add_target (t);

  deprecated_add_core_fns (&arm_netbsd_core_fns);
  deprecated_add_core_fns (&arm_netbsd_elfcore_fns);
}
Commit	Line	Data
e7a42bc8	1	/* Native-dependent code for BSD Unix running on ARM's, for GDB.
9f8e0089	2
6aba47ca	3	Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 1999, 2002, 2004, 2007
34e8f22d	4	Free Software Foundation, Inc.
e7a42bc8 FN	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
197e01b6 EZ	20	Foundation, Inc., 51 Franklin Street, Fifth Floor,
197e01b6 EZ	21	Boston, MA 02110-1301, USA. */
e7a42bc8 FN	22
e7a42bc8 FN	23	#include "defs.h"
2b73aeb1 MK	24	#include "gdbcore.h"
	25	#include "inferior.h"
	26	#include "regcache.h"
	27	#include "target.h"
e7a42bc8	28
2b73aeb1	29	#include "gdb_string.h"
e7a42bc8 FN	30	#include <sys/types.h>
	31	#include <sys/ptrace.h>
	32	#include <machine/reg.h>
	33	#include <machine/frame.h>
2b73aeb1 MK	34
	35	#include "arm-tdep.h"
	36	#include "inf-ptrace.h"
e7a42bc8	37
47221191 RE	38	extern int arm_apcs_32;
47221191 RE	39
b34db576 RE	40	static void
	41	supply_gregset (struct reg *gregset)
	42	{
	43	int regno;
	44	CORE_ADDR r_pc;
	45
	46	/* Integer registers. */
	47	for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++)
23a6d369	48	regcache_raw_supply (current_regcache, regno, (char *) &gregset->r[regno]);
b34db576	49
23a6d369 AC	50	regcache_raw_supply (current_regcache, ARM_SP_REGNUM,
	51	(char *) &gregset->r_sp);
	52	regcache_raw_supply (current_regcache, ARM_LR_REGNUM,
	53	(char *) &gregset->r_lr);
b34db576 RE	54	/* This is ok: we're running native... */
b34db576 RE	55	r_pc = ADDR_BITS_REMOVE (gregset->r_pc);
23a6d369	56	regcache_raw_supply (current_regcache, ARM_PC_REGNUM, (char *) &r_pc);
b34db576 RE	57
b34db576 RE	58	if (arm_apcs_32)
23a6d369 AC	59	regcache_raw_supply (current_regcache, ARM_PS_REGNUM,
23a6d369 AC	60	(char *) &gregset->r_cpsr);
b34db576	61	else
23a6d369 AC	62	regcache_raw_supply (current_regcache, ARM_PS_REGNUM,
23a6d369 AC	63	(char *) &gregset->r_pc);
b34db576 RE	64	}
	65
	66	static void
	67	supply_fparegset (struct fpreg *fparegset)
	68	{
	69	int regno;
	70
	71	for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++)
23a6d369 AC	72	regcache_raw_supply (current_regcache, regno,
23a6d369 AC	73	(char *) &fparegset->fpr[regno - ARM_F0_REGNUM]);
b34db576	74
23a6d369 AC	75	regcache_raw_supply (current_regcache, ARM_FPS_REGNUM,
23a6d369 AC	76	(char *) &fparegset->fpr_fpsr);
b34db576 RE	77	}
b34db576 RE	78
47221191 RE	79	static void
	80	fetch_register (int regno)
	81	{
	82	struct reg inferior_registers;
	83	int ret;
	84
	85	ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid),
9f8e0089	86	(PTRACE_TYPE_ARG3) &inferior_registers, 0);
47221191 RE	87
	88	if (ret < 0)
	89	{
edefbb7c	90	warning (_("unable to fetch general register"));
47221191 RE	91	return;
	92	}
	93
	94	switch (regno)
	95	{
	96	case ARM_SP_REGNUM:
23a6d369 AC	97	regcache_raw_supply (current_regcache, ARM_SP_REGNUM,
23a6d369 AC	98	(char *) &inferior_registers.r_sp);
47221191 RE	99	break;
	100
	101	case ARM_LR_REGNUM:
23a6d369 AC	102	regcache_raw_supply (current_regcache, ARM_LR_REGNUM,
23a6d369 AC	103	(char *) &inferior_registers.r_lr);
47221191 RE	104	break;
	105
	106	case ARM_PC_REGNUM:
	107	/* This is ok: we're running native... */
	108	inferior_registers.r_pc = ADDR_BITS_REMOVE (inferior_registers.r_pc);
23a6d369 AC	109	regcache_raw_supply (current_regcache, ARM_PC_REGNUM,
23a6d369 AC	110	(char *) &inferior_registers.r_pc);
47221191 RE	111	break;
	112
	113	case ARM_PS_REGNUM:
	114	if (arm_apcs_32)
23a6d369 AC	115	regcache_raw_supply (current_regcache, ARM_PS_REGNUM,
23a6d369 AC	116	(char *) &inferior_registers.r_cpsr);
47221191	117	else
23a6d369 AC	118	regcache_raw_supply (current_regcache, ARM_PS_REGNUM,
23a6d369 AC	119	(char *) &inferior_registers.r_pc);
47221191 RE	120	break;
	121
	122	default:
23a6d369 AC	123	regcache_raw_supply (current_regcache, regno,
23a6d369 AC	124	(char *) &inferior_registers.r[regno]);
47221191 RE	125	break;
	126	}
	127	}
	128
	129	static void
3e56fc4b	130	fetch_regs (void)
e7a42bc8 FN	131	{
e7a42bc8 FN	132	struct reg inferior_registers;
47221191 RE	133	int ret;
	134	int regno;
	135
	136	ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid),
9f8e0089	137	(PTRACE_TYPE_ARG3) &inferior_registers, 0);
47221191 RE	138
	139	if (ret < 0)
	140	{
edefbb7c	141	warning (_("unable to fetch general registers"));
47221191 RE	142	return;
	143	}
	144
b34db576	145	supply_gregset (&inferior_registers);
47221191 RE	146	}
	147
	148	static void
	149	fetch_fp_register (int regno)
	150	{
	151	struct fpreg inferior_fp_registers;
	152	int ret;
	153
	154	ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid),
9f8e0089	155	(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);
47221191 RE	156
	157	if (ret < 0)
	158	{
edefbb7c	159	warning (_("unable to fetch floating-point register"));
47221191 RE	160	return;
	161	}
	162
	163	switch (regno)
	164	{
	165	case ARM_FPS_REGNUM:
23a6d369 AC	166	regcache_raw_supply (current_regcache, ARM_FPS_REGNUM,
23a6d369 AC	167	(char *) &inferior_fp_registers.fpr_fpsr);
47221191 RE	168	break;
	169
	170	default:
23a6d369 AC	171	regcache_raw_supply (current_regcache, regno,
23a6d369 AC	172	(char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]);
47221191 RE	173	break;
	174	}
	175	}
	176
	177	static void
3e56fc4b	178	fetch_fp_regs (void)
47221191 RE	179	{
	180	struct fpreg inferior_fp_registers;
	181	int ret;
	182	int regno;
	183
	184	ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid),
9f8e0089	185	(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);
47221191 RE	186
	187	if (ret < 0)
	188	{
edefbb7c	189	warning (_("unable to fetch general registers"));
47221191 RE	190	return;
	191	}
	192
b34db576	193	supply_fparegset (&inferior_fp_registers);
e7a42bc8 FN	194	}
e7a42bc8 FN	195
2b73aeb1 MK	196	static void
2b73aeb1 MK	197	armnbsd_fetch_registers (int regno)
47221191 RE	198	{
	199	if (regno >= 0)
	200	{
	201	if (regno < ARM_F0_REGNUM \|\| regno > ARM_FPS_REGNUM)
	202	fetch_register (regno);
	203	else
	204	fetch_fp_register (regno);
	205	}
	206	else
	207	{
	208	fetch_regs ();
	209	fetch_fp_regs ();
	210	}
	211	}
	212
	213
	214	static void
	215	store_register (int regno)
e7a42bc8 FN	216	{
e7a42bc8 FN	217	struct reg inferior_registers;
47221191 RE	218	int ret;
	219
	220	ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid),
9f8e0089	221	(PTRACE_TYPE_ARG3) &inferior_registers, 0);
47221191 RE	222
	223	if (ret < 0)
	224	{
edefbb7c	225	warning (_("unable to fetch general registers"));
47221191 RE	226	return;
	227	}
	228
	229	switch (regno)
	230	{
	231	case ARM_SP_REGNUM:
822c9732 AC	232	regcache_raw_collect (current_regcache, ARM_SP_REGNUM,
822c9732 AC	233	(char *) &inferior_registers.r_sp);
47221191 RE	234	break;
	235
	236	case ARM_LR_REGNUM:
822c9732 AC	237	regcache_raw_collect (current_regcache, ARM_LR_REGNUM,
822c9732 AC	238	(char *) &inferior_registers.r_lr);
47221191	239	break;
e7a42bc8	240
47221191 RE	241	case ARM_PC_REGNUM:
47221191 RE	242	if (arm_apcs_32)
822c9732 AC	243	regcache_raw_collect (current_regcache, ARM_PC_REGNUM,
822c9732 AC	244	(char *) &inferior_registers.r_pc);
47221191 RE	245	else
	246	{
	247	unsigned pc_val;
e7a42bc8	248
822c9732 AC	249	regcache_raw_collect (current_regcache, ARM_PC_REGNUM,
822c9732 AC	250	(char *) &pc_val);
47221191 RE	251
	252	pc_val = ADDR_BITS_REMOVE (pc_val);
	253	inferior_registers.r_pc
	254	^= ADDR_BITS_REMOVE (inferior_registers.r_pc);
	255	inferior_registers.r_pc \|= pc_val;
	256	}
	257	break;
	258
	259	case ARM_PS_REGNUM:
	260	if (arm_apcs_32)
822c9732 AC	261	regcache_raw_collect (current_regcache, ARM_PS_REGNUM,
822c9732 AC	262	(char *) &inferior_registers.r_cpsr);
47221191 RE	263	else
	264	{
	265	unsigned psr_val;
	266
822c9732 AC	267	regcache_raw_collect (current_regcache, ARM_PS_REGNUM,
822c9732 AC	268	(char *) &psr_val);
47221191 RE	269
	270	psr_val ^= ADDR_BITS_REMOVE (psr_val);
	271	inferior_registers.r_pc = ADDR_BITS_REMOVE (inferior_registers.r_pc);
	272	inferior_registers.r_pc \|= psr_val;
	273	}
	274	break;
	275
	276	default:
822c9732 AC	277	regcache_raw_collect (current_regcache, regno,
822c9732 AC	278	(char *) &inferior_registers.r[regno]);
47221191 RE	279	break;
	280	}
	281
	282	ret = ptrace (PT_SETREGS, PIDGET (inferior_ptid),
9f8e0089	283	(PTRACE_TYPE_ARG3) &inferior_registers, 0);
47221191 RE	284
47221191 RE	285	if (ret < 0)
edefbb7c	286	warning (_("unable to write register %d to inferior"), regno);
47221191 RE	287	}
	288
	289	static void
3e56fc4b	290	store_regs (void)
47221191 RE	291	{
	292	struct reg inferior_registers;
	293	int ret;
	294	int regno;
	295
	296
	297	for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++)
822c9732 AC	298	regcache_raw_collect (current_regcache, regno,
822c9732 AC	299	(char *) &inferior_registers.r[regno]);
47221191	300
822c9732 AC	301	regcache_raw_collect (current_regcache, ARM_SP_REGNUM,
	302	(char *) &inferior_registers.r_sp);
	303	regcache_raw_collect (current_regcache, ARM_LR_REGNUM,
	304	(char *) &inferior_registers.r_lr);
47221191 RE	305
	306	if (arm_apcs_32)
	307	{
822c9732 AC	308	regcache_raw_collect (current_regcache, ARM_PC_REGNUM,
	309	(char *) &inferior_registers.r_pc);
	310	regcache_raw_collect (current_regcache, ARM_PS_REGNUM,
	311	(char *) &inferior_registers.r_cpsr);
47221191 RE	312	}
	313	else
	314	{
	315	unsigned pc_val;
	316	unsigned psr_val;
	317
822c9732 AC	318	regcache_raw_collect (current_regcache, ARM_PC_REGNUM,
	319	(char *) &pc_val);
	320	regcache_raw_collect (current_regcache, ARM_PS_REGNUM,
	321	(char *) &psr_val);
47221191 RE	322
	323	pc_val = ADDR_BITS_REMOVE (pc_val);
	324	psr_val ^= ADDR_BITS_REMOVE (psr_val);
	325
	326	inferior_registers.r_pc = pc_val \| psr_val;
	327	}
	328
	329	ret = ptrace (PT_SETREGS, PIDGET (inferior_ptid),
9f8e0089	330	(PTRACE_TYPE_ARG3) &inferior_registers, 0);
47221191 RE	331
47221191 RE	332	if (ret < 0)
edefbb7c	333	warning (_("unable to store general registers"));
47221191 RE	334	}
	335
	336	static void
	337	store_fp_register (int regno)
	338	{
	339	struct fpreg inferior_fp_registers;
	340	int ret;
	341
	342	ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid),
9f8e0089	343	(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);
47221191 RE	344
	345	if (ret < 0)
	346	{
edefbb7c	347	warning (_("unable to fetch floating-point registers"));
47221191 RE	348	return;
	349	}
	350
	351	switch (regno)
	352	{
	353	case ARM_FPS_REGNUM:
822c9732 AC	354	regcache_raw_collect (current_regcache, ARM_FPS_REGNUM,
822c9732 AC	355	(char *) &inferior_fp_registers.fpr_fpsr);
47221191 RE	356	break;
	357
	358	default:
822c9732 AC	359	regcache_raw_collect (current_regcache, regno,
822c9732 AC	360	(char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]);
47221191 RE	361	break;
	362	}
	363
	364	ret = ptrace (PT_SETFPREGS, PIDGET (inferior_ptid),
9f8e0089	365	(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);
47221191 RE	366
47221191 RE	367	if (ret < 0)
edefbb7c	368	warning (_("unable to write register %d to inferior"), regno);
47221191 RE	369	}
	370
	371	static void
3e56fc4b	372	store_fp_regs (void)
47221191 RE	373	{
	374	struct fpreg inferior_fp_registers;
	375	int ret;
	376	int regno;
	377
	378
	379	for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++)
822c9732 AC	380	regcache_raw_collect (current_regcache, regno,
822c9732 AC	381	(char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]);
47221191	382
822c9732 AC	383	regcache_raw_collect (current_regcache, ARM_FPS_REGNUM,
822c9732 AC	384	(char *) &inferior_fp_registers.fpr_fpsr);
47221191 RE	385
47221191 RE	386	ret = ptrace (PT_SETFPREGS, PIDGET (inferior_ptid),
9f8e0089	387	(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);
47221191 RE	388
47221191 RE	389	if (ret < 0)
edefbb7c	390	warning (_("unable to store floating-point registers"));
47221191 RE	391	}
47221191 RE	392
2b73aeb1 MK	393	static void
2b73aeb1 MK	394	armnbsd_store_registers (int regno)
47221191 RE	395	{
	396	if (regno >= 0)
	397	{
	398	if (regno < ARM_F0_REGNUM \|\| regno > ARM_FPS_REGNUM)
	399	store_register (regno);
	400	else
	401	store_fp_register (regno);
	402	}
	403	else
	404	{
	405	store_regs ();
	406	store_fp_regs ();
	407	}
e7a42bc8 FN	408	}
	409
	410	struct md_core
	411	{
	412	struct reg intreg;
	413	struct fpreg freg;
	414	};
	415
3e56fc4b	416	static void
47221191 RE	417	fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
47221191 RE	418	int which, CORE_ADDR ignore)
e7a42bc8 FN	419	{
e7a42bc8 FN	420	struct md_core core_reg = (struct md_core ) core_reg_sect;
3e56fc4b RE	421	int regno;
3e56fc4b RE	422	CORE_ADDR r_pc;
3e56fc4b	423
b34db576 RE	424	supply_gregset (&core_reg->intreg);
	425	supply_fparegset (&core_reg->freg);
	426	}
3e56fc4b	427
b34db576 RE	428	static void
	429	fetch_elfcore_registers (char *core_reg_sect, unsigned core_reg_size,
	430	int which, CORE_ADDR ignore)
	431	{
	432	struct reg gregset;
	433	struct fpreg fparegset;
e7a42bc8	434
b34db576 RE	435	switch (which)
	436	{
	437	case 0: /* Integer registers. */
	438	if (core_reg_size != sizeof (struct reg))
edefbb7c	439	warning (_("wrong size of register set in core file"));
b34db576 RE	440	else
	441	{
	442	/* The memcpy may be unnecessary, but we can't really be sure
	443	of the alignment of the data in the core file. */
	444	memcpy (&gregset, core_reg_sect, sizeof (gregset));
	445	supply_gregset (&gregset);
	446	}
	447	break;
	448
	449	case 2:
	450	if (core_reg_size != sizeof (struct fpreg))
edefbb7c	451	warning (_("wrong size of FPA register set in core file"));
b34db576 RE	452	else
	453	{
	454	/* The memcpy may be unnecessary, but we can't really be sure
	455	of the alignment of the data in the core file. */
	456	memcpy (&fparegset, core_reg_sect, sizeof (fparegset));
	457	supply_fparegset (&fparegset);
	458	}
	459	break;
3e56fc4b	460
b34db576 RE	461	default:
	462	/* Don't know what kind of register request this is; just ignore it. */
	463	break;
	464	}
e7a42bc8 FN	465	}
e7a42bc8 FN	466
3e56fc4b RE	467	static struct core_fns arm_netbsd_core_fns =
	468	{
	469	bfd_target_unknown_flavour, /* core_flovour. */
	470	default_check_format, /* check_format. */
	471	default_core_sniffer, /* core_sniffer. */
	472	fetch_core_registers, /* core_read_registers. */
	473	NULL
	474	};
	475
b34db576 RE	476	static struct core_fns arm_netbsd_elfcore_fns =
	477	{
	478	bfd_target_elf_flavour, /* core_flovour. */
	479	default_check_format, /* check_format. */
	480	default_core_sniffer, /* core_sniffer. */
	481	fetch_elfcore_registers, /* core_read_registers. */
	482	NULL
	483	};
	484
3e56fc4b RE	485	void
	486	_initialize_arm_netbsd_nat (void)
	487	{
2b73aeb1 MK	488	struct target_ops *t;
	489
	490	t = inf_ptrace_target ();
	491	t->to_fetch_registers = armnbsd_fetch_registers;
	492	t->to_store_registers = armnbsd_store_registers;
	493	add_target (t);
	494
00e32a35 AC	495	deprecated_add_core_fns (&arm_netbsd_core_fns);
00e32a35 AC	496	deprecated_add_core_fns (&arm_netbsd_elfcore_fns);
3e56fc4b	497	}