Commit | Line | Data |
---|---|---|
e7a42bc8 | 1 | /* Native-dependent code for BSD Unix running on ARM's, for GDB. |
9f8e0089 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 1999, 2002, 2004, 2007 |
34e8f22d | 4 | Free Software Foundation, Inc. |
e7a42bc8 FN |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
e7a42bc8 FN |
22 | |
23 | #include "defs.h" | |
2b73aeb1 MK |
24 | #include "gdbcore.h" |
25 | #include "inferior.h" | |
26 | #include "regcache.h" | |
27 | #include "target.h" | |
e7a42bc8 | 28 | |
2b73aeb1 | 29 | #include "gdb_string.h" |
e7a42bc8 FN |
30 | #include <sys/types.h> |
31 | #include <sys/ptrace.h> | |
32 | #include <machine/reg.h> | |
33 | #include <machine/frame.h> | |
2b73aeb1 MK |
34 | |
35 | #include "arm-tdep.h" | |
36 | #include "inf-ptrace.h" | |
e7a42bc8 | 37 | |
47221191 RE |
38 | extern int arm_apcs_32; |
39 | ||
b34db576 | 40 | static void |
d683e2b7 | 41 | arm_supply_gregset (struct regcache *regcache, struct reg *gregset) |
b34db576 RE |
42 | { |
43 | int regno; | |
44 | CORE_ADDR r_pc; | |
45 | ||
46 | /* Integer registers. */ | |
47 | for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++) | |
d683e2b7 | 48 | regcache_raw_supply (regcache, regno, (char *) &gregset->r[regno]); |
b34db576 | 49 | |
d683e2b7 | 50 | regcache_raw_supply (regcache, ARM_SP_REGNUM, |
23a6d369 | 51 | (char *) &gregset->r_sp); |
d683e2b7 | 52 | regcache_raw_supply (regcache, ARM_LR_REGNUM, |
23a6d369 | 53 | (char *) &gregset->r_lr); |
b34db576 RE |
54 | /* This is ok: we're running native... */ |
55 | r_pc = ADDR_BITS_REMOVE (gregset->r_pc); | |
d683e2b7 | 56 | regcache_raw_supply (regcache, ARM_PC_REGNUM, (char *) &r_pc); |
b34db576 RE |
57 | |
58 | if (arm_apcs_32) | |
d683e2b7 | 59 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
23a6d369 | 60 | (char *) &gregset->r_cpsr); |
b34db576 | 61 | else |
d683e2b7 | 62 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
23a6d369 | 63 | (char *) &gregset->r_pc); |
b34db576 RE |
64 | } |
65 | ||
66 | static void | |
d683e2b7 | 67 | arm_supply_fparegset (struct regcache *regcache, struct fpreg *fparegset) |
b34db576 RE |
68 | { |
69 | int regno; | |
70 | ||
71 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) | |
d683e2b7 | 72 | regcache_raw_supply (regcache, regno, |
23a6d369 | 73 | (char *) &fparegset->fpr[regno - ARM_F0_REGNUM]); |
b34db576 | 74 | |
d683e2b7 | 75 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
23a6d369 | 76 | (char *) &fparegset->fpr_fpsr); |
b34db576 RE |
77 | } |
78 | ||
47221191 | 79 | static void |
56be3814 | 80 | fetch_register (struct regcache *regcache, int regno) |
47221191 RE |
81 | { |
82 | struct reg inferior_registers; | |
83 | int ret; | |
84 | ||
85 | ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid), | |
9f8e0089 | 86 | (PTRACE_TYPE_ARG3) &inferior_registers, 0); |
47221191 RE |
87 | |
88 | if (ret < 0) | |
89 | { | |
edefbb7c | 90 | warning (_("unable to fetch general register")); |
47221191 RE |
91 | return; |
92 | } | |
93 | ||
94 | switch (regno) | |
95 | { | |
96 | case ARM_SP_REGNUM: | |
56be3814 | 97 | regcache_raw_supply (regcache, ARM_SP_REGNUM, |
23a6d369 | 98 | (char *) &inferior_registers.r_sp); |
47221191 RE |
99 | break; |
100 | ||
101 | case ARM_LR_REGNUM: | |
56be3814 | 102 | regcache_raw_supply (regcache, ARM_LR_REGNUM, |
23a6d369 | 103 | (char *) &inferior_registers.r_lr); |
47221191 RE |
104 | break; |
105 | ||
106 | case ARM_PC_REGNUM: | |
107 | /* This is ok: we're running native... */ | |
108 | inferior_registers.r_pc = ADDR_BITS_REMOVE (inferior_registers.r_pc); | |
56be3814 | 109 | regcache_raw_supply (regcache, ARM_PC_REGNUM, |
23a6d369 | 110 | (char *) &inferior_registers.r_pc); |
47221191 RE |
111 | break; |
112 | ||
113 | case ARM_PS_REGNUM: | |
114 | if (arm_apcs_32) | |
56be3814 | 115 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
23a6d369 | 116 | (char *) &inferior_registers.r_cpsr); |
47221191 | 117 | else |
56be3814 | 118 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
23a6d369 | 119 | (char *) &inferior_registers.r_pc); |
47221191 RE |
120 | break; |
121 | ||
122 | default: | |
56be3814 | 123 | regcache_raw_supply (regcache, regno, |
23a6d369 | 124 | (char *) &inferior_registers.r[regno]); |
47221191 RE |
125 | break; |
126 | } | |
127 | } | |
128 | ||
129 | static void | |
56be3814 | 130 | fetch_regs (struct regcache *regcache) |
e7a42bc8 FN |
131 | { |
132 | struct reg inferior_registers; | |
47221191 RE |
133 | int ret; |
134 | int regno; | |
135 | ||
136 | ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid), | |
9f8e0089 | 137 | (PTRACE_TYPE_ARG3) &inferior_registers, 0); |
47221191 RE |
138 | |
139 | if (ret < 0) | |
140 | { | |
edefbb7c | 141 | warning (_("unable to fetch general registers")); |
47221191 RE |
142 | return; |
143 | } | |
144 | ||
56be3814 | 145 | arm_supply_gregset (regcache, &inferior_registers); |
47221191 RE |
146 | } |
147 | ||
148 | static void | |
56be3814 | 149 | fetch_fp_register (struct regcache *regcache, int regno) |
47221191 RE |
150 | { |
151 | struct fpreg inferior_fp_registers; | |
152 | int ret; | |
153 | ||
154 | ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), | |
9f8e0089 | 155 | (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); |
47221191 RE |
156 | |
157 | if (ret < 0) | |
158 | { | |
edefbb7c | 159 | warning (_("unable to fetch floating-point register")); |
47221191 RE |
160 | return; |
161 | } | |
162 | ||
163 | switch (regno) | |
164 | { | |
165 | case ARM_FPS_REGNUM: | |
56be3814 | 166 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
23a6d369 | 167 | (char *) &inferior_fp_registers.fpr_fpsr); |
47221191 RE |
168 | break; |
169 | ||
170 | default: | |
56be3814 | 171 | regcache_raw_supply (regcache, regno, |
23a6d369 | 172 | (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]); |
47221191 RE |
173 | break; |
174 | } | |
175 | } | |
176 | ||
177 | static void | |
56be3814 | 178 | fetch_fp_regs (struct regcache *regcache) |
47221191 RE |
179 | { |
180 | struct fpreg inferior_fp_registers; | |
181 | int ret; | |
182 | int regno; | |
183 | ||
184 | ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), | |
9f8e0089 | 185 | (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); |
47221191 RE |
186 | |
187 | if (ret < 0) | |
188 | { | |
edefbb7c | 189 | warning (_("unable to fetch general registers")); |
47221191 RE |
190 | return; |
191 | } | |
192 | ||
56be3814 | 193 | arm_supply_fparegset (regcache, &inferior_fp_registers); |
e7a42bc8 FN |
194 | } |
195 | ||
2b73aeb1 | 196 | static void |
56be3814 | 197 | armnbsd_fetch_registers (struct regcache *regcache, int regno) |
47221191 RE |
198 | { |
199 | if (regno >= 0) | |
200 | { | |
201 | if (regno < ARM_F0_REGNUM || regno > ARM_FPS_REGNUM) | |
56be3814 | 202 | fetch_register (regcache, regno); |
47221191 | 203 | else |
56be3814 | 204 | fetch_fp_register (regcache, regno); |
47221191 RE |
205 | } |
206 | else | |
207 | { | |
56be3814 UW |
208 | fetch_regs (regcache); |
209 | fetch_fp_regs (regcache); | |
47221191 RE |
210 | } |
211 | } | |
212 | ||
213 | ||
214 | static void | |
56be3814 | 215 | store_register (const struct regcache *regcache, int regno) |
e7a42bc8 FN |
216 | { |
217 | struct reg inferior_registers; | |
47221191 RE |
218 | int ret; |
219 | ||
220 | ret = ptrace (PT_GETREGS, PIDGET (inferior_ptid), | |
9f8e0089 | 221 | (PTRACE_TYPE_ARG3) &inferior_registers, 0); |
47221191 RE |
222 | |
223 | if (ret < 0) | |
224 | { | |
edefbb7c | 225 | warning (_("unable to fetch general registers")); |
47221191 RE |
226 | return; |
227 | } | |
228 | ||
229 | switch (regno) | |
230 | { | |
231 | case ARM_SP_REGNUM: | |
56be3814 | 232 | regcache_raw_collect (regcache, ARM_SP_REGNUM, |
822c9732 | 233 | (char *) &inferior_registers.r_sp); |
47221191 RE |
234 | break; |
235 | ||
236 | case ARM_LR_REGNUM: | |
56be3814 | 237 | regcache_raw_collect (regcache, ARM_LR_REGNUM, |
822c9732 | 238 | (char *) &inferior_registers.r_lr); |
47221191 | 239 | break; |
e7a42bc8 | 240 | |
47221191 RE |
241 | case ARM_PC_REGNUM: |
242 | if (arm_apcs_32) | |
56be3814 | 243 | regcache_raw_collect (regcache, ARM_PC_REGNUM, |
822c9732 | 244 | (char *) &inferior_registers.r_pc); |
47221191 RE |
245 | else |
246 | { | |
247 | unsigned pc_val; | |
e7a42bc8 | 248 | |
56be3814 | 249 | regcache_raw_collect (regcache, ARM_PC_REGNUM, |
822c9732 | 250 | (char *) &pc_val); |
47221191 RE |
251 | |
252 | pc_val = ADDR_BITS_REMOVE (pc_val); | |
253 | inferior_registers.r_pc | |
254 | ^= ADDR_BITS_REMOVE (inferior_registers.r_pc); | |
255 | inferior_registers.r_pc |= pc_val; | |
256 | } | |
257 | break; | |
258 | ||
259 | case ARM_PS_REGNUM: | |
260 | if (arm_apcs_32) | |
56be3814 | 261 | regcache_raw_collect (regcache, ARM_PS_REGNUM, |
822c9732 | 262 | (char *) &inferior_registers.r_cpsr); |
47221191 RE |
263 | else |
264 | { | |
265 | unsigned psr_val; | |
266 | ||
56be3814 | 267 | regcache_raw_collect (regcache, ARM_PS_REGNUM, |
822c9732 | 268 | (char *) &psr_val); |
47221191 RE |
269 | |
270 | psr_val ^= ADDR_BITS_REMOVE (psr_val); | |
271 | inferior_registers.r_pc = ADDR_BITS_REMOVE (inferior_registers.r_pc); | |
272 | inferior_registers.r_pc |= psr_val; | |
273 | } | |
274 | break; | |
275 | ||
276 | default: | |
56be3814 | 277 | regcache_raw_collect (regcache, regno, |
822c9732 | 278 | (char *) &inferior_registers.r[regno]); |
47221191 RE |
279 | break; |
280 | } | |
281 | ||
282 | ret = ptrace (PT_SETREGS, PIDGET (inferior_ptid), | |
9f8e0089 | 283 | (PTRACE_TYPE_ARG3) &inferior_registers, 0); |
47221191 RE |
284 | |
285 | if (ret < 0) | |
edefbb7c | 286 | warning (_("unable to write register %d to inferior"), regno); |
47221191 RE |
287 | } |
288 | ||
289 | static void | |
56be3814 | 290 | store_regs (const struct regcache *regcache) |
47221191 RE |
291 | { |
292 | struct reg inferior_registers; | |
293 | int ret; | |
294 | int regno; | |
295 | ||
296 | ||
297 | for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++) | |
56be3814 | 298 | regcache_raw_collect (regcache, regno, |
822c9732 | 299 | (char *) &inferior_registers.r[regno]); |
47221191 | 300 | |
56be3814 | 301 | regcache_raw_collect (regcache, ARM_SP_REGNUM, |
822c9732 | 302 | (char *) &inferior_registers.r_sp); |
56be3814 | 303 | regcache_raw_collect (regcache, ARM_LR_REGNUM, |
822c9732 | 304 | (char *) &inferior_registers.r_lr); |
47221191 RE |
305 | |
306 | if (arm_apcs_32) | |
307 | { | |
56be3814 | 308 | regcache_raw_collect (regcache, ARM_PC_REGNUM, |
822c9732 | 309 | (char *) &inferior_registers.r_pc); |
56be3814 | 310 | regcache_raw_collect (regcache, ARM_PS_REGNUM, |
822c9732 | 311 | (char *) &inferior_registers.r_cpsr); |
47221191 RE |
312 | } |
313 | else | |
314 | { | |
315 | unsigned pc_val; | |
316 | unsigned psr_val; | |
317 | ||
56be3814 | 318 | regcache_raw_collect (regcache, ARM_PC_REGNUM, |
822c9732 | 319 | (char *) &pc_val); |
56be3814 | 320 | regcache_raw_collect (regcache, ARM_PS_REGNUM, |
822c9732 | 321 | (char *) &psr_val); |
47221191 RE |
322 | |
323 | pc_val = ADDR_BITS_REMOVE (pc_val); | |
324 | psr_val ^= ADDR_BITS_REMOVE (psr_val); | |
325 | ||
326 | inferior_registers.r_pc = pc_val | psr_val; | |
327 | } | |
328 | ||
329 | ret = ptrace (PT_SETREGS, PIDGET (inferior_ptid), | |
9f8e0089 | 330 | (PTRACE_TYPE_ARG3) &inferior_registers, 0); |
47221191 RE |
331 | |
332 | if (ret < 0) | |
edefbb7c | 333 | warning (_("unable to store general registers")); |
47221191 RE |
334 | } |
335 | ||
336 | static void | |
56be3814 | 337 | store_fp_register (const struct regcache *regcache, int regno) |
47221191 RE |
338 | { |
339 | struct fpreg inferior_fp_registers; | |
340 | int ret; | |
341 | ||
342 | ret = ptrace (PT_GETFPREGS, PIDGET (inferior_ptid), | |
9f8e0089 | 343 | (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); |
47221191 RE |
344 | |
345 | if (ret < 0) | |
346 | { | |
edefbb7c | 347 | warning (_("unable to fetch floating-point registers")); |
47221191 RE |
348 | return; |
349 | } | |
350 | ||
351 | switch (regno) | |
352 | { | |
353 | case ARM_FPS_REGNUM: | |
56be3814 | 354 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, |
822c9732 | 355 | (char *) &inferior_fp_registers.fpr_fpsr); |
47221191 RE |
356 | break; |
357 | ||
358 | default: | |
56be3814 | 359 | regcache_raw_collect (regcache, regno, |
822c9732 | 360 | (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]); |
47221191 RE |
361 | break; |
362 | } | |
363 | ||
364 | ret = ptrace (PT_SETFPREGS, PIDGET (inferior_ptid), | |
9f8e0089 | 365 | (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); |
47221191 RE |
366 | |
367 | if (ret < 0) | |
edefbb7c | 368 | warning (_("unable to write register %d to inferior"), regno); |
47221191 RE |
369 | } |
370 | ||
371 | static void | |
56be3814 | 372 | store_fp_regs (const struct regcache *regcache) |
47221191 RE |
373 | { |
374 | struct fpreg inferior_fp_registers; | |
375 | int ret; | |
376 | int regno; | |
377 | ||
378 | ||
379 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) | |
56be3814 | 380 | regcache_raw_collect (regcache, regno, |
822c9732 | 381 | (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]); |
47221191 | 382 | |
56be3814 | 383 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, |
822c9732 | 384 | (char *) &inferior_fp_registers.fpr_fpsr); |
47221191 RE |
385 | |
386 | ret = ptrace (PT_SETFPREGS, PIDGET (inferior_ptid), | |
9f8e0089 | 387 | (PTRACE_TYPE_ARG3) &inferior_fp_registers, 0); |
47221191 RE |
388 | |
389 | if (ret < 0) | |
edefbb7c | 390 | warning (_("unable to store floating-point registers")); |
47221191 RE |
391 | } |
392 | ||
2b73aeb1 | 393 | static void |
56be3814 | 394 | armnbsd_store_registers (struct regcache *regcache, int regno) |
47221191 RE |
395 | { |
396 | if (regno >= 0) | |
397 | { | |
398 | if (regno < ARM_F0_REGNUM || regno > ARM_FPS_REGNUM) | |
56be3814 | 399 | store_register (regcache, regno); |
47221191 | 400 | else |
56be3814 | 401 | store_fp_register (regcache, regno); |
47221191 RE |
402 | } |
403 | else | |
404 | { | |
56be3814 UW |
405 | store_regs (regcache); |
406 | store_fp_regs (regcache); | |
47221191 | 407 | } |
e7a42bc8 FN |
408 | } |
409 | ||
410 | struct md_core | |
411 | { | |
412 | struct reg intreg; | |
413 | struct fpreg freg; | |
414 | }; | |
415 | ||
3e56fc4b | 416 | static void |
9eefc95f UW |
417 | fetch_core_registers (struct regcache *regcache, |
418 | char *core_reg_sect, unsigned core_reg_size, | |
47221191 | 419 | int which, CORE_ADDR ignore) |
e7a42bc8 FN |
420 | { |
421 | struct md_core *core_reg = (struct md_core *) core_reg_sect; | |
3e56fc4b RE |
422 | int regno; |
423 | CORE_ADDR r_pc; | |
3e56fc4b | 424 | |
9eefc95f UW |
425 | arm_supply_gregset (regcache, &core_reg->intreg); |
426 | arm_supply_fparegset (regcache, &core_reg->freg); | |
b34db576 | 427 | } |
3e56fc4b | 428 | |
b34db576 | 429 | static void |
9eefc95f UW |
430 | fetch_elfcore_registers (struct regcache *regcache, |
431 | char *core_reg_sect, unsigned core_reg_size, | |
b34db576 RE |
432 | int which, CORE_ADDR ignore) |
433 | { | |
434 | struct reg gregset; | |
435 | struct fpreg fparegset; | |
e7a42bc8 | 436 | |
b34db576 RE |
437 | switch (which) |
438 | { | |
439 | case 0: /* Integer registers. */ | |
440 | if (core_reg_size != sizeof (struct reg)) | |
edefbb7c | 441 | warning (_("wrong size of register set in core file")); |
b34db576 RE |
442 | else |
443 | { | |
444 | /* The memcpy may be unnecessary, but we can't really be sure | |
445 | of the alignment of the data in the core file. */ | |
446 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
9eefc95f | 447 | arm_supply_gregset (regcache, &gregset); |
b34db576 RE |
448 | } |
449 | break; | |
450 | ||
451 | case 2: | |
452 | if (core_reg_size != sizeof (struct fpreg)) | |
edefbb7c | 453 | warning (_("wrong size of FPA register set in core file")); |
b34db576 RE |
454 | else |
455 | { | |
456 | /* The memcpy may be unnecessary, but we can't really be sure | |
457 | of the alignment of the data in the core file. */ | |
458 | memcpy (&fparegset, core_reg_sect, sizeof (fparegset)); | |
9eefc95f | 459 | arm_supply_fparegset (regcache, &fparegset); |
b34db576 RE |
460 | } |
461 | break; | |
3e56fc4b | 462 | |
b34db576 RE |
463 | default: |
464 | /* Don't know what kind of register request this is; just ignore it. */ | |
465 | break; | |
466 | } | |
e7a42bc8 FN |
467 | } |
468 | ||
3e56fc4b RE |
469 | static struct core_fns arm_netbsd_core_fns = |
470 | { | |
471 | bfd_target_unknown_flavour, /* core_flovour. */ | |
472 | default_check_format, /* check_format. */ | |
473 | default_core_sniffer, /* core_sniffer. */ | |
474 | fetch_core_registers, /* core_read_registers. */ | |
475 | NULL | |
476 | }; | |
477 | ||
b34db576 RE |
478 | static struct core_fns arm_netbsd_elfcore_fns = |
479 | { | |
480 | bfd_target_elf_flavour, /* core_flovour. */ | |
481 | default_check_format, /* check_format. */ | |
482 | default_core_sniffer, /* core_sniffer. */ | |
483 | fetch_elfcore_registers, /* core_read_registers. */ | |
484 | NULL | |
485 | }; | |
486 | ||
3e56fc4b RE |
487 | void |
488 | _initialize_arm_netbsd_nat (void) | |
489 | { | |
2b73aeb1 MK |
490 | struct target_ops *t; |
491 | ||
492 | t = inf_ptrace_target (); | |
493 | t->to_fetch_registers = armnbsd_fetch_registers; | |
494 | t->to_store_registers = armnbsd_store_registers; | |
495 | add_target (t); | |
496 | ||
00e32a35 AC |
497 | deprecated_add_core_fns (&arm_netbsd_core_fns); |
498 | deprecated_add_core_fns (&arm_netbsd_elfcore_fns); | |
3e56fc4b | 499 | } |