Commit | Line | Data |
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8818c391 | 1 | /* Target-dependent code for Atmel AVR, for GDB. |
0fd88904 | 2 | |
ecd75fc8 | 3 | Copyright (C) 1996-2014 Free Software Foundation, Inc. |
8818c391 TR |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
8818c391 TR |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
8818c391 | 19 | |
de18ac1f | 20 | /* Contributed by Theodore A. Roth, troth@openavr.org */ |
8818c391 TR |
21 | |
22 | /* Portions of this file were taken from the original gdb-4.18 patch developed | |
23 | by Denis Chertykov, denisc@overta.ru */ | |
24 | ||
25 | #include "defs.h" | |
4add8633 TR |
26 | #include "frame.h" |
27 | #include "frame-unwind.h" | |
28 | #include "frame-base.h" | |
29 | #include "trad-frame.h" | |
8818c391 TR |
30 | #include "gdbcmd.h" |
31 | #include "gdbcore.h" | |
e6bb342a | 32 | #include "gdbtypes.h" |
8818c391 TR |
33 | #include "inferior.h" |
34 | #include "symfile.h" | |
35 | #include "arch-utils.h" | |
36 | #include "regcache.h" | |
0e9f083f | 37 | #include <string.h> |
a89aa300 | 38 | #include "dis-asm.h" |
77e371c0 | 39 | #include "objfiles.h" |
8818c391 TR |
40 | |
41 | /* AVR Background: | |
42 | ||
43 | (AVR micros are pure Harvard Architecture processors.) | |
44 | ||
45 | The AVR family of microcontrollers have three distinctly different memory | |
0963b4bd MS |
46 | spaces: flash, sram and eeprom. The flash is 16 bits wide and is used for |
47 | the most part to store program instructions. The sram is 8 bits wide and is | |
48 | used for the stack and the heap. Some devices lack sram and some can have | |
8818c391 TR |
49 | an additional external sram added on as a peripheral. |
50 | ||
51 | The eeprom is 8 bits wide and is used to store data when the device is | |
0963b4bd MS |
52 | powered down. Eeprom is not directly accessible, it can only be accessed |
53 | via io-registers using a special algorithm. Accessing eeprom via gdb's | |
8818c391 TR |
54 | remote serial protocol ('m' or 'M' packets) looks difficult to do and is |
55 | not included at this time. | |
56 | ||
57 | [The eeprom could be read manually via ``x/b <eaddr + AVR_EMEM_START>'' or | |
58 | written using ``set {unsigned char}<eaddr + AVR_EMEM_START>''. For this to | |
59 | work, the remote target must be able to handle eeprom accesses and perform | |
60 | the address translation.] | |
61 | ||
0963b4bd | 62 | All three memory spaces have physical addresses beginning at 0x0. In |
8818c391 TR |
63 | addition, the flash is addressed by gcc/binutils/gdb with respect to 8 bit |
64 | bytes instead of the 16 bit wide words used by the real device for the | |
65 | Program Counter. | |
66 | ||
67 | In order for remote targets to work correctly, extra bits must be added to | |
68 | addresses before they are send to the target or received from the target | |
0963b4bd MS |
69 | via the remote serial protocol. The extra bits are the MSBs and are used to |
70 | decode which memory space the address is referring to. */ | |
8818c391 | 71 | |
8818c391 TR |
72 | /* Constants: prefixed with AVR_ to avoid name space clashes */ |
73 | ||
487d9753 PL |
74 | /* Address space flags */ |
75 | ||
76 | /* We are assigning the TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1 to the flash address | |
77 | space. */ | |
78 | ||
79 | #define AVR_TYPE_ADDRESS_CLASS_FLASH TYPE_ADDRESS_CLASS_1 | |
80 | #define AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH \ | |
81 | TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1 | |
82 | ||
83 | ||
8818c391 | 84 | enum |
2e5ff58c TR |
85 | { |
86 | AVR_REG_W = 24, | |
87 | AVR_REG_X = 26, | |
88 | AVR_REG_Y = 28, | |
89 | AVR_FP_REGNUM = 28, | |
90 | AVR_REG_Z = 30, | |
91 | ||
92 | AVR_SREG_REGNUM = 32, | |
93 | AVR_SP_REGNUM = 33, | |
94 | AVR_PC_REGNUM = 34, | |
95 | ||
96 | AVR_NUM_REGS = 32 + 1 /*SREG*/ + 1 /*SP*/ + 1 /*PC*/, | |
97 | AVR_NUM_REG_BYTES = 32 + 1 /*SREG*/ + 2 /*SP*/ + 4 /*PC*/, | |
98 | ||
7d2552b4 TG |
99 | /* Pseudo registers. */ |
100 | AVR_PSEUDO_PC_REGNUM = 35, | |
101 | AVR_NUM_PSEUDO_REGS = 1, | |
102 | ||
2e5ff58c TR |
103 | AVR_PC_REG_INDEX = 35, /* index into array of registers */ |
104 | ||
4add8633 | 105 | AVR_MAX_PROLOGUE_SIZE = 64, /* bytes */ |
2e5ff58c | 106 | |
0963b4bd | 107 | /* Count of pushed registers. From r2 to r17 (inclusively), r28, r29 */ |
2e5ff58c TR |
108 | AVR_MAX_PUSHES = 18, |
109 | ||
0963b4bd | 110 | /* Number of the last pushed register. r17 for current avr-gcc */ |
2e5ff58c TR |
111 | AVR_LAST_PUSHED_REGNUM = 17, |
112 | ||
4add8633 TR |
113 | AVR_ARG1_REGNUM = 24, /* Single byte argument */ |
114 | AVR_ARGN_REGNUM = 25, /* Multi byte argments */ | |
115 | ||
116 | AVR_RET1_REGNUM = 24, /* Single byte return value */ | |
117 | AVR_RETN_REGNUM = 25, /* Multi byte return value */ | |
118 | ||
2e5ff58c | 119 | /* FIXME: TRoth/2002-01-??: Can we shift all these memory masks left 8 |
0963b4bd | 120 | bits? Do these have to match the bfd vma values? It sure would make |
2e5ff58c TR |
121 | things easier in the future if they didn't need to match. |
122 | ||
123 | Note: I chose these values so as to be consistent with bfd vma | |
124 | addresses. | |
125 | ||
126 | TRoth/2002-04-08: There is already a conflict with very large programs | |
0963b4bd | 127 | in the mega128. The mega128 has 128K instruction bytes (64K words), |
2e5ff58c TR |
128 | thus the Most Significant Bit is 0x10000 which gets masked off my |
129 | AVR_MEM_MASK. | |
130 | ||
131 | The problem manifests itself when trying to set a breakpoint in a | |
132 | function which resides in the upper half of the instruction space and | |
133 | thus requires a 17-bit address. | |
134 | ||
135 | For now, I've just removed the EEPROM mask and changed AVR_MEM_MASK | |
0963b4bd | 136 | from 0x00ff0000 to 0x00f00000. Eeprom is not accessible from gdb yet, |
2e5ff58c TR |
137 | but could be for some remote targets by just adding the correct offset |
138 | to the address and letting the remote target handle the low-level | |
0963b4bd | 139 | details of actually accessing the eeprom. */ |
2e5ff58c TR |
140 | |
141 | AVR_IMEM_START = 0x00000000, /* INSN memory */ | |
142 | AVR_SMEM_START = 0x00800000, /* SRAM memory */ | |
8818c391 | 143 | #if 1 |
2e5ff58c TR |
144 | /* No eeprom mask defined */ |
145 | AVR_MEM_MASK = 0x00f00000, /* mask to determine memory space */ | |
8818c391 | 146 | #else |
2e5ff58c TR |
147 | AVR_EMEM_START = 0x00810000, /* EEPROM memory */ |
148 | AVR_MEM_MASK = 0x00ff0000, /* mask to determine memory space */ | |
8818c391 | 149 | #endif |
2e5ff58c | 150 | }; |
8818c391 | 151 | |
4add8633 TR |
152 | /* Prologue types: |
153 | ||
154 | NORMAL and CALL are the typical types (the -mcall-prologues gcc option | |
155 | causes the generation of the CALL type prologues). */ | |
156 | ||
157 | enum { | |
158 | AVR_PROLOGUE_NONE, /* No prologue */ | |
159 | AVR_PROLOGUE_NORMAL, | |
160 | AVR_PROLOGUE_CALL, /* -mcall-prologues */ | |
161 | AVR_PROLOGUE_MAIN, | |
162 | AVR_PROLOGUE_INTR, /* interrupt handler */ | |
163 | AVR_PROLOGUE_SIG, /* signal handler */ | |
164 | }; | |
165 | ||
8818c391 TR |
166 | /* Any function with a frame looks like this |
167 | ....... <-SP POINTS HERE | |
168 | LOCALS1 <-FP POINTS HERE | |
169 | LOCALS0 | |
170 | SAVED FP | |
171 | SAVED R3 | |
172 | SAVED R2 | |
173 | RET PC | |
174 | FIRST ARG | |
175 | SECOND ARG */ | |
176 | ||
4add8633 | 177 | struct avr_unwind_cache |
2e5ff58c | 178 | { |
4add8633 TR |
179 | /* The previous frame's inner most stack address. Used as this |
180 | frame ID's stack_addr. */ | |
181 | CORE_ADDR prev_sp; | |
182 | /* The frame's base, optionally used by the high-level debug info. */ | |
183 | CORE_ADDR base; | |
184 | int size; | |
185 | int prologue_type; | |
186 | /* Table indicating the location of each and every register. */ | |
187 | struct trad_frame_saved_reg *saved_regs; | |
2e5ff58c | 188 | }; |
8818c391 TR |
189 | |
190 | struct gdbarch_tdep | |
2e5ff58c | 191 | { |
4e99ad69 | 192 | /* Number of bytes stored to the stack by call instructions. |
9c97a070 | 193 | 2 bytes for avr1-5 and avrxmega1-5, 3 bytes for avr6 and avrxmega6-7. */ |
4e99ad69 | 194 | int call_length; |
7d2552b4 TG |
195 | |
196 | /* Type for void. */ | |
197 | struct type *void_type; | |
198 | /* Type for a function returning void. */ | |
199 | struct type *func_void_type; | |
200 | /* Type for a pointer to a function. Used for the type of PC. */ | |
201 | struct type *pc_type; | |
2e5ff58c | 202 | }; |
8818c391 | 203 | |
0963b4bd | 204 | /* Lookup the name of a register given it's number. */ |
8818c391 | 205 | |
fa88f677 | 206 | static const char * |
d93859e2 | 207 | avr_register_name (struct gdbarch *gdbarch, int regnum) |
8818c391 | 208 | { |
4e99ad69 | 209 | static const char * const register_names[] = { |
2e5ff58c TR |
210 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
211 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
8818c391 TR |
212 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
213 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
7d2552b4 TG |
214 | "SREG", "SP", "PC2", |
215 | "pc" | |
8818c391 TR |
216 | }; |
217 | if (regnum < 0) | |
218 | return NULL; | |
219 | if (regnum >= (sizeof (register_names) / sizeof (*register_names))) | |
220 | return NULL; | |
221 | return register_names[regnum]; | |
222 | } | |
223 | ||
8818c391 TR |
224 | /* Return the GDB type object for the "standard" data type |
225 | of data in register N. */ | |
226 | ||
227 | static struct type * | |
866b76ea | 228 | avr_register_type (struct gdbarch *gdbarch, int reg_nr) |
8818c391 | 229 | { |
866b76ea | 230 | if (reg_nr == AVR_PC_REGNUM) |
df4df182 | 231 | return builtin_type (gdbarch)->builtin_uint32; |
7d2552b4 TG |
232 | if (reg_nr == AVR_PSEUDO_PC_REGNUM) |
233 | return gdbarch_tdep (gdbarch)->pc_type; | |
866b76ea | 234 | if (reg_nr == AVR_SP_REGNUM) |
0dfff4cb | 235 | return builtin_type (gdbarch)->builtin_data_ptr; |
7d2552b4 | 236 | return builtin_type (gdbarch)->builtin_uint8; |
8818c391 TR |
237 | } |
238 | ||
0963b4bd | 239 | /* Instruction address checks and convertions. */ |
8818c391 TR |
240 | |
241 | static CORE_ADDR | |
242 | avr_make_iaddr (CORE_ADDR x) | |
243 | { | |
244 | return ((x) | AVR_IMEM_START); | |
245 | } | |
246 | ||
0963b4bd | 247 | /* FIXME: TRoth: Really need to use a larger mask for instructions. Some |
8818c391 TR |
248 | devices are already up to 128KBytes of flash space. |
249 | ||
0963b4bd | 250 | TRoth/2002-04-8: See comment above where AVR_IMEM_START is defined. */ |
8818c391 TR |
251 | |
252 | static CORE_ADDR | |
253 | avr_convert_iaddr_to_raw (CORE_ADDR x) | |
254 | { | |
255 | return ((x) & 0xffffffff); | |
256 | } | |
257 | ||
0963b4bd | 258 | /* SRAM address checks and convertions. */ |
8818c391 TR |
259 | |
260 | static CORE_ADDR | |
261 | avr_make_saddr (CORE_ADDR x) | |
262 | { | |
ee143e81 TG |
263 | /* Return 0 for NULL. */ |
264 | if (x == 0) | |
265 | return 0; | |
266 | ||
8818c391 TR |
267 | return ((x) | AVR_SMEM_START); |
268 | } | |
269 | ||
8818c391 TR |
270 | static CORE_ADDR |
271 | avr_convert_saddr_to_raw (CORE_ADDR x) | |
272 | { | |
273 | return ((x) & 0xffffffff); | |
274 | } | |
275 | ||
0963b4bd MS |
276 | /* EEPROM address checks and convertions. I don't know if these will ever |
277 | actually be used, but I've added them just the same. TRoth */ | |
8818c391 TR |
278 | |
279 | /* TRoth/2002-04-08: Commented out for now to allow fix for problem with large | |
0963b4bd | 280 | programs in the mega128. */ |
8818c391 TR |
281 | |
282 | /* static CORE_ADDR */ | |
283 | /* avr_make_eaddr (CORE_ADDR x) */ | |
284 | /* { */ | |
285 | /* return ((x) | AVR_EMEM_START); */ | |
286 | /* } */ | |
287 | ||
288 | /* static int */ | |
289 | /* avr_eaddr_p (CORE_ADDR x) */ | |
290 | /* { */ | |
291 | /* return (((x) & AVR_MEM_MASK) == AVR_EMEM_START); */ | |
292 | /* } */ | |
293 | ||
294 | /* static CORE_ADDR */ | |
295 | /* avr_convert_eaddr_to_raw (CORE_ADDR x) */ | |
296 | /* { */ | |
297 | /* return ((x) & 0xffffffff); */ | |
298 | /* } */ | |
299 | ||
0963b4bd | 300 | /* Convert from address to pointer and vice-versa. */ |
8818c391 TR |
301 | |
302 | static void | |
9898f801 UW |
303 | avr_address_to_pointer (struct gdbarch *gdbarch, |
304 | struct type *type, gdb_byte *buf, CORE_ADDR addr) | |
8818c391 | 305 | { |
e17a4113 UW |
306 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
307 | ||
487d9753 PL |
308 | /* Is it a data address in flash? */ |
309 | if (AVR_TYPE_ADDRESS_CLASS_FLASH (type)) | |
310 | { | |
311 | /* A data address in flash is always byte addressed. */ | |
312 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, | |
313 | avr_convert_iaddr_to_raw (addr)); | |
314 | } | |
8818c391 | 315 | /* Is it a code address? */ |
487d9753 PL |
316 | else if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC |
317 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
8818c391 | 318 | { |
487d9753 PL |
319 | /* A code address, either a function pointer or the program counter, is |
320 | word (16 bits) addressed. */ | |
e17a4113 | 321 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, |
4ea2465e | 322 | avr_convert_iaddr_to_raw (addr >> 1)); |
8818c391 TR |
323 | } |
324 | else | |
325 | { | |
326 | /* Strip off any upper segment bits. */ | |
e17a4113 | 327 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, |
2e5ff58c | 328 | avr_convert_saddr_to_raw (addr)); |
8818c391 TR |
329 | } |
330 | } | |
331 | ||
332 | static CORE_ADDR | |
9898f801 UW |
333 | avr_pointer_to_address (struct gdbarch *gdbarch, |
334 | struct type *type, const gdb_byte *buf) | |
8818c391 | 335 | { |
e17a4113 UW |
336 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
337 | CORE_ADDR addr | |
338 | = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); | |
8818c391 | 339 | |
487d9753 PL |
340 | /* Is it a data address in flash? */ |
341 | if (AVR_TYPE_ADDRESS_CLASS_FLASH (type)) | |
342 | return avr_make_iaddr (addr); | |
8818c391 | 343 | /* Is it a code address? */ |
487d9753 PL |
344 | else if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC |
345 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD | |
346 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
4ea2465e | 347 | return avr_make_iaddr (addr << 1); |
8818c391 TR |
348 | else |
349 | return avr_make_saddr (addr); | |
350 | } | |
351 | ||
8a1d23b2 TG |
352 | static CORE_ADDR |
353 | avr_integer_to_address (struct gdbarch *gdbarch, | |
354 | struct type *type, const gdb_byte *buf) | |
355 | { | |
356 | ULONGEST addr = unpack_long (type, buf); | |
357 | ||
358 | return avr_make_saddr (addr); | |
359 | } | |
360 | ||
8818c391 | 361 | static CORE_ADDR |
61a1198a | 362 | avr_read_pc (struct regcache *regcache) |
8818c391 | 363 | { |
8619218d | 364 | ULONGEST pc; |
61a1198a UW |
365 | regcache_cooked_read_unsigned (regcache, AVR_PC_REGNUM, &pc); |
366 | return avr_make_iaddr (pc); | |
8818c391 TR |
367 | } |
368 | ||
369 | static void | |
61a1198a | 370 | avr_write_pc (struct regcache *regcache, CORE_ADDR val) |
8818c391 | 371 | { |
61a1198a | 372 | regcache_cooked_write_unsigned (regcache, AVR_PC_REGNUM, |
7d2552b4 TG |
373 | avr_convert_iaddr_to_raw (val)); |
374 | } | |
375 | ||
05d1431c | 376 | static enum register_status |
7d2552b4 TG |
377 | avr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
378 | int regnum, gdb_byte *buf) | |
379 | { | |
380 | ULONGEST val; | |
05d1431c | 381 | enum register_status status; |
7d2552b4 TG |
382 | |
383 | switch (regnum) | |
384 | { | |
385 | case AVR_PSEUDO_PC_REGNUM: | |
05d1431c PA |
386 | status = regcache_raw_read_unsigned (regcache, AVR_PC_REGNUM, &val); |
387 | if (status != REG_VALID) | |
388 | return status; | |
7d2552b4 TG |
389 | val >>= 1; |
390 | store_unsigned_integer (buf, 4, gdbarch_byte_order (gdbarch), val); | |
05d1431c | 391 | return status; |
7d2552b4 TG |
392 | default: |
393 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
394 | } | |
395 | } | |
396 | ||
397 | static void | |
398 | avr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
399 | int regnum, const gdb_byte *buf) | |
400 | { | |
401 | ULONGEST val; | |
402 | ||
403 | switch (regnum) | |
404 | { | |
405 | case AVR_PSEUDO_PC_REGNUM: | |
406 | val = extract_unsigned_integer (buf, 4, gdbarch_byte_order (gdbarch)); | |
407 | val <<= 1; | |
408 | regcache_raw_write_unsigned (regcache, AVR_PC_REGNUM, val); | |
409 | break; | |
410 | default: | |
411 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
412 | } | |
8818c391 TR |
413 | } |
414 | ||
4add8633 | 415 | /* Function: avr_scan_prologue |
8818c391 | 416 | |
4add8633 | 417 | This function decodes an AVR function prologue to determine: |
8818c391 TR |
418 | 1) the size of the stack frame |
419 | 2) which registers are saved on it | |
420 | 3) the offsets of saved regs | |
4add8633 | 421 | This information is stored in the avr_unwind_cache structure. |
8818c391 | 422 | |
e3d8b004 TR |
423 | Some devices lack the sbiw instruction, so on those replace this: |
424 | sbiw r28, XX | |
425 | with this: | |
426 | subi r28,lo8(XX) | |
427 | sbci r29,hi8(XX) | |
428 | ||
429 | A typical AVR function prologue with a frame pointer might look like this: | |
430 | push rXX ; saved regs | |
431 | ... | |
432 | push r28 | |
433 | push r29 | |
434 | in r28,__SP_L__ | |
435 | in r29,__SP_H__ | |
436 | sbiw r28,<LOCALS_SIZE> | |
437 | in __tmp_reg__,__SREG__ | |
8818c391 | 438 | cli |
e3d8b004 | 439 | out __SP_H__,r29 |
72fab697 TR |
440 | out __SREG__,__tmp_reg__ |
441 | out __SP_L__,r28 | |
e3d8b004 TR |
442 | |
443 | A typical AVR function prologue without a frame pointer might look like | |
444 | this: | |
445 | push rXX ; saved regs | |
446 | ... | |
447 | ||
448 | A main function prologue looks like this: | |
449 | ldi r28,lo8(<RAM_ADDR> - <LOCALS_SIZE>) | |
450 | ldi r29,hi8(<RAM_ADDR> - <LOCALS_SIZE>) | |
451 | out __SP_H__,r29 | |
452 | out __SP_L__,r28 | |
453 | ||
454 | A signal handler prologue looks like this: | |
455 | push __zero_reg__ | |
456 | push __tmp_reg__ | |
457 | in __tmp_reg__, __SREG__ | |
458 | push __tmp_reg__ | |
459 | clr __zero_reg__ | |
460 | push rXX ; save registers r18:r27, r30:r31 | |
461 | ... | |
462 | push r28 ; save frame pointer | |
463 | push r29 | |
464 | in r28, __SP_L__ | |
465 | in r29, __SP_H__ | |
466 | sbiw r28, <LOCALS_SIZE> | |
467 | out __SP_H__, r29 | |
468 | out __SP_L__, r28 | |
469 | ||
470 | A interrupt handler prologue looks like this: | |
471 | sei | |
472 | push __zero_reg__ | |
473 | push __tmp_reg__ | |
474 | in __tmp_reg__, __SREG__ | |
475 | push __tmp_reg__ | |
476 | clr __zero_reg__ | |
477 | push rXX ; save registers r18:r27, r30:r31 | |
478 | ... | |
479 | push r28 ; save frame pointer | |
480 | push r29 | |
481 | in r28, __SP_L__ | |
482 | in r29, __SP_H__ | |
483 | sbiw r28, <LOCALS_SIZE> | |
484 | cli | |
485 | out __SP_H__, r29 | |
486 | sei | |
487 | out __SP_L__, r28 | |
488 | ||
489 | A `-mcall-prologues' prologue looks like this (Note that the megas use a | |
490 | jmp instead of a rjmp, thus the prologue is one word larger since jmp is a | |
491 | 32 bit insn and rjmp is a 16 bit insn): | |
492 | ldi r26,lo8(<LOCALS_SIZE>) | |
493 | ldi r27,hi8(<LOCALS_SIZE>) | |
494 | ldi r30,pm_lo8(.L_foo_body) | |
495 | ldi r31,pm_hi8(.L_foo_body) | |
496 | rjmp __prologue_saves__+RRR | |
497 | .L_foo_body: */ | |
8818c391 | 498 | |
4add8633 TR |
499 | /* Not really part of a prologue, but still need to scan for it, is when a |
500 | function prologue moves values passed via registers as arguments to new | |
0963b4bd MS |
501 | registers. In this case, all local variables live in registers, so there |
502 | may be some register saves. This is what it looks like: | |
4add8633 TR |
503 | movw rMM, rNN |
504 | ... | |
505 | ||
0963b4bd MS |
506 | There could be multiple movw's. If the target doesn't have a movw insn, it |
507 | will use two mov insns. This could be done after any of the above prologue | |
4add8633 TR |
508 | types. */ |
509 | ||
510 | static CORE_ADDR | |
e17a4113 | 511 | avr_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc_beg, CORE_ADDR pc_end, |
4e99ad69 | 512 | struct avr_unwind_cache *info) |
8818c391 | 513 | { |
e17a4113 | 514 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2e5ff58c TR |
515 | int i; |
516 | unsigned short insn; | |
2e5ff58c | 517 | int scan_stage = 0; |
3b7344d5 | 518 | struct bound_minimal_symbol msymbol; |
8818c391 TR |
519 | unsigned char prologue[AVR_MAX_PROLOGUE_SIZE]; |
520 | int vpc = 0; | |
4e99ad69 TG |
521 | int len; |
522 | ||
523 | len = pc_end - pc_beg; | |
524 | if (len > AVR_MAX_PROLOGUE_SIZE) | |
525 | len = AVR_MAX_PROLOGUE_SIZE; | |
8818c391 | 526 | |
4add8633 | 527 | /* FIXME: TRoth/2003-06-11: This could be made more efficient by only |
0963b4bd MS |
528 | reading in the bytes of the prologue. The problem is that the figuring |
529 | out where the end of the prologue is is a bit difficult. The old code | |
4add8633 | 530 | tried to do that, but failed quite often. */ |
4e99ad69 | 531 | read_memory (pc_beg, prologue, len); |
8818c391 TR |
532 | |
533 | /* Scanning main()'s prologue | |
534 | ldi r28,lo8(<RAM_ADDR> - <LOCALS_SIZE>) | |
535 | ldi r29,hi8(<RAM_ADDR> - <LOCALS_SIZE>) | |
536 | out __SP_H__,r29 | |
537 | out __SP_L__,r28 */ | |
538 | ||
4e99ad69 | 539 | if (len >= 4) |
8818c391 TR |
540 | { |
541 | CORE_ADDR locals; | |
4e99ad69 | 542 | static const unsigned char img[] = { |
2e5ff58c TR |
543 | 0xde, 0xbf, /* out __SP_H__,r29 */ |
544 | 0xcd, 0xbf /* out __SP_L__,r28 */ | |
8818c391 TR |
545 | }; |
546 | ||
e17a4113 | 547 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
8818c391 | 548 | /* ldi r28,lo8(<RAM_ADDR> - <LOCALS_SIZE>) */ |
2e5ff58c TR |
549 | if ((insn & 0xf0f0) == 0xe0c0) |
550 | { | |
551 | locals = (insn & 0xf) | ((insn & 0x0f00) >> 4); | |
e17a4113 | 552 | insn = extract_unsigned_integer (&prologue[vpc + 2], 2, byte_order); |
2e5ff58c TR |
553 | /* ldi r29,hi8(<RAM_ADDR> - <LOCALS_SIZE>) */ |
554 | if ((insn & 0xf0f0) == 0xe0d0) | |
555 | { | |
556 | locals |= ((insn & 0xf) | ((insn & 0x0f00) >> 4)) << 8; | |
4e99ad69 TG |
557 | if (vpc + 4 + sizeof (img) < len |
558 | && memcmp (prologue + vpc + 4, img, sizeof (img)) == 0) | |
2e5ff58c | 559 | { |
4add8633 TR |
560 | info->prologue_type = AVR_PROLOGUE_MAIN; |
561 | info->base = locals; | |
4e99ad69 | 562 | return pc_beg + 4; |
2e5ff58c TR |
563 | } |
564 | } | |
565 | } | |
8818c391 | 566 | } |
2e5ff58c | 567 | |
4add8633 TR |
568 | /* Scanning `-mcall-prologues' prologue |
569 | Classic prologue is 10 bytes, mega prologue is a 12 bytes long */ | |
8818c391 | 570 | |
e3d8b004 | 571 | while (1) /* Using a while to avoid many goto's */ |
8818c391 TR |
572 | { |
573 | int loc_size; | |
574 | int body_addr; | |
575 | unsigned num_pushes; | |
4add8633 | 576 | int pc_offset = 0; |
2e5ff58c | 577 | |
4e99ad69 TG |
578 | /* At least the fifth instruction must have been executed to |
579 | modify frame shape. */ | |
580 | if (len < 10) | |
581 | break; | |
582 | ||
e17a4113 | 583 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
8818c391 | 584 | /* ldi r26,<LOCALS_SIZE> */ |
2e5ff58c TR |
585 | if ((insn & 0xf0f0) != 0xe0a0) |
586 | break; | |
8818c391 | 587 | loc_size = (insn & 0xf) | ((insn & 0x0f00) >> 4); |
4add8633 | 588 | pc_offset += 2; |
2e5ff58c | 589 | |
e17a4113 | 590 | insn = extract_unsigned_integer (&prologue[vpc + 2], 2, byte_order); |
8818c391 TR |
591 | /* ldi r27,<LOCALS_SIZE> / 256 */ |
592 | if ((insn & 0xf0f0) != 0xe0b0) | |
2e5ff58c | 593 | break; |
8818c391 | 594 | loc_size |= ((insn & 0xf) | ((insn & 0x0f00) >> 4)) << 8; |
4add8633 | 595 | pc_offset += 2; |
2e5ff58c | 596 | |
e17a4113 | 597 | insn = extract_unsigned_integer (&prologue[vpc + 4], 2, byte_order); |
8818c391 TR |
598 | /* ldi r30,pm_lo8(.L_foo_body) */ |
599 | if ((insn & 0xf0f0) != 0xe0e0) | |
2e5ff58c | 600 | break; |
8818c391 | 601 | body_addr = (insn & 0xf) | ((insn & 0x0f00) >> 4); |
4add8633 | 602 | pc_offset += 2; |
8818c391 | 603 | |
e17a4113 | 604 | insn = extract_unsigned_integer (&prologue[vpc + 6], 2, byte_order); |
8818c391 TR |
605 | /* ldi r31,pm_hi8(.L_foo_body) */ |
606 | if ((insn & 0xf0f0) != 0xe0f0) | |
2e5ff58c | 607 | break; |
8818c391 | 608 | body_addr |= ((insn & 0xf) | ((insn & 0x0f00) >> 4)) << 8; |
4add8633 | 609 | pc_offset += 2; |
8818c391 | 610 | |
8818c391 | 611 | msymbol = lookup_minimal_symbol ("__prologue_saves__", NULL, NULL); |
3b7344d5 | 612 | if (!msymbol.minsym) |
2e5ff58c | 613 | break; |
8818c391 | 614 | |
e17a4113 | 615 | insn = extract_unsigned_integer (&prologue[vpc + 8], 2, byte_order); |
8818c391 | 616 | /* rjmp __prologue_saves__+RRR */ |
e3d8b004 TR |
617 | if ((insn & 0xf000) == 0xc000) |
618 | { | |
619 | /* Extract PC relative offset from RJMP */ | |
620 | i = (insn & 0xfff) | (insn & 0x800 ? (-1 ^ 0xfff) : 0); | |
621 | /* Convert offset to byte addressable mode */ | |
622 | i *= 2; | |
623 | /* Destination address */ | |
4e99ad69 | 624 | i += pc_beg + 10; |
e3d8b004 | 625 | |
4e99ad69 | 626 | if (body_addr != (pc_beg + 10)/2) |
e3d8b004 | 627 | break; |
4add8633 TR |
628 | |
629 | pc_offset += 2; | |
e3d8b004 | 630 | } |
e3d8b004 TR |
631 | else if ((insn & 0xfe0e) == 0x940c) |
632 | { | |
633 | /* Extract absolute PC address from JMP */ | |
634 | i = (((insn & 0x1) | ((insn & 0x1f0) >> 3) << 16) | |
e17a4113 UW |
635 | | (extract_unsigned_integer (&prologue[vpc + 10], 2, byte_order) |
636 | & 0xffff)); | |
e3d8b004 TR |
637 | /* Convert address to byte addressable mode */ |
638 | i *= 2; | |
639 | ||
4e99ad69 | 640 | if (body_addr != (pc_beg + 12)/2) |
e3d8b004 | 641 | break; |
4add8633 TR |
642 | |
643 | pc_offset += 4; | |
e3d8b004 TR |
644 | } |
645 | else | |
646 | break; | |
2e5ff58c | 647 | |
4add8633 | 648 | /* Resolve offset (in words) from __prologue_saves__ symbol. |
8818c391 | 649 | Which is a pushes count in `-mcall-prologues' mode */ |
77e371c0 | 650 | num_pushes = AVR_MAX_PUSHES - (i - BMSYMBOL_VALUE_ADDRESS (msymbol)) / 2; |
8818c391 TR |
651 | |
652 | if (num_pushes > AVR_MAX_PUSHES) | |
4add8633 | 653 | { |
edefbb7c | 654 | fprintf_unfiltered (gdb_stderr, _("Num pushes too large: %d\n"), |
4add8633 TR |
655 | num_pushes); |
656 | num_pushes = 0; | |
657 | } | |
2e5ff58c | 658 | |
8818c391 | 659 | if (num_pushes) |
2e5ff58c TR |
660 | { |
661 | int from; | |
4add8633 TR |
662 | |
663 | info->saved_regs[AVR_FP_REGNUM + 1].addr = num_pushes; | |
2e5ff58c | 664 | if (num_pushes >= 2) |
4add8633 TR |
665 | info->saved_regs[AVR_FP_REGNUM].addr = num_pushes - 1; |
666 | ||
2e5ff58c TR |
667 | i = 0; |
668 | for (from = AVR_LAST_PUSHED_REGNUM + 1 - (num_pushes - 2); | |
669 | from <= AVR_LAST_PUSHED_REGNUM; ++from) | |
4add8633 | 670 | info->saved_regs [from].addr = ++i; |
2e5ff58c | 671 | } |
4add8633 TR |
672 | info->size = loc_size + num_pushes; |
673 | info->prologue_type = AVR_PROLOGUE_CALL; | |
674 | ||
4e99ad69 | 675 | return pc_beg + pc_offset; |
8818c391 TR |
676 | } |
677 | ||
4add8633 TR |
678 | /* Scan for the beginning of the prologue for an interrupt or signal |
679 | function. Note that we have to set the prologue type here since the | |
680 | third stage of the prologue may not be present (e.g. no saved registered | |
681 | or changing of the SP register). */ | |
8818c391 | 682 | |
4add8633 | 683 | if (1) |
8818c391 | 684 | { |
4e99ad69 | 685 | static const unsigned char img[] = { |
2e5ff58c TR |
686 | 0x78, 0x94, /* sei */ |
687 | 0x1f, 0x92, /* push r1 */ | |
688 | 0x0f, 0x92, /* push r0 */ | |
689 | 0x0f, 0xb6, /* in r0,0x3f SREG */ | |
690 | 0x0f, 0x92, /* push r0 */ | |
691 | 0x11, 0x24 /* clr r1 */ | |
8818c391 | 692 | }; |
4e99ad69 TG |
693 | if (len >= sizeof (img) |
694 | && memcmp (prologue, img, sizeof (img)) == 0) | |
2e5ff58c | 695 | { |
4add8633 | 696 | info->prologue_type = AVR_PROLOGUE_INTR; |
2e5ff58c | 697 | vpc += sizeof (img); |
4add8633 TR |
698 | info->saved_regs[AVR_SREG_REGNUM].addr = 3; |
699 | info->saved_regs[0].addr = 2; | |
700 | info->saved_regs[1].addr = 1; | |
701 | info->size += 3; | |
2e5ff58c | 702 | } |
4e99ad69 TG |
703 | else if (len >= sizeof (img) - 2 |
704 | && memcmp (img + 2, prologue, sizeof (img) - 2) == 0) | |
2e5ff58c | 705 | { |
4add8633 TR |
706 | info->prologue_type = AVR_PROLOGUE_SIG; |
707 | vpc += sizeof (img) - 2; | |
708 | info->saved_regs[AVR_SREG_REGNUM].addr = 3; | |
709 | info->saved_regs[0].addr = 2; | |
710 | info->saved_regs[1].addr = 1; | |
243e2c5d | 711 | info->size += 2; |
2e5ff58c | 712 | } |
8818c391 TR |
713 | } |
714 | ||
715 | /* First stage of the prologue scanning. | |
4add8633 | 716 | Scan pushes (saved registers) */ |
8818c391 | 717 | |
4e99ad69 | 718 | for (; vpc < len; vpc += 2) |
8818c391 | 719 | { |
e17a4113 | 720 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
2e5ff58c TR |
721 | if ((insn & 0xfe0f) == 0x920f) /* push rXX */ |
722 | { | |
0963b4bd | 723 | /* Bits 4-9 contain a mask for registers R0-R32. */ |
4add8633 TR |
724 | int regno = (insn & 0x1f0) >> 4; |
725 | info->size++; | |
726 | info->saved_regs[regno].addr = info->size; | |
2e5ff58c TR |
727 | scan_stage = 1; |
728 | } | |
8818c391 | 729 | else |
2e5ff58c | 730 | break; |
8818c391 TR |
731 | } |
732 | ||
243e2c5d | 733 | gdb_assert (vpc < AVR_MAX_PROLOGUE_SIZE); |
4add8633 | 734 | |
1bd0bb72 TG |
735 | /* Handle static small stack allocation using rcall or push. */ |
736 | ||
737 | while (scan_stage == 1 && vpc < len) | |
738 | { | |
739 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); | |
740 | if (insn == 0xd000) /* rcall .+0 */ | |
741 | { | |
742 | info->size += gdbarch_tdep (gdbarch)->call_length; | |
743 | vpc += 2; | |
744 | } | |
7588d2ec | 745 | else if (insn == 0x920f || insn == 0x921f) /* push r0 or push r1 */ |
1bd0bb72 TG |
746 | { |
747 | info->size += 1; | |
748 | vpc += 2; | |
749 | } | |
750 | else | |
751 | break; | |
752 | } | |
753 | ||
8818c391 TR |
754 | /* Second stage of the prologue scanning. |
755 | Scan: | |
756 | in r28,__SP_L__ | |
757 | in r29,__SP_H__ */ | |
758 | ||
4e99ad69 | 759 | if (scan_stage == 1 && vpc < len) |
8818c391 | 760 | { |
4e99ad69 | 761 | static const unsigned char img[] = { |
2e5ff58c TR |
762 | 0xcd, 0xb7, /* in r28,__SP_L__ */ |
763 | 0xde, 0xb7 /* in r29,__SP_H__ */ | |
8818c391 | 764 | }; |
2e5ff58c | 765 | |
4e99ad69 TG |
766 | if (vpc + sizeof (img) < len |
767 | && memcmp (prologue + vpc, img, sizeof (img)) == 0) | |
2e5ff58c TR |
768 | { |
769 | vpc += 4; | |
2e5ff58c TR |
770 | scan_stage = 2; |
771 | } | |
8818c391 TR |
772 | } |
773 | ||
0963b4bd | 774 | /* Third stage of the prologue scanning. (Really two stages). |
8818c391 TR |
775 | Scan for: |
776 | sbiw r28,XX or subi r28,lo8(XX) | |
72fab697 | 777 | sbci r29,hi8(XX) |
8818c391 TR |
778 | in __tmp_reg__,__SREG__ |
779 | cli | |
e3d8b004 | 780 | out __SP_H__,r29 |
8818c391 | 781 | out __SREG__,__tmp_reg__ |
e3d8b004 | 782 | out __SP_L__,r28 */ |
8818c391 | 783 | |
4e99ad69 | 784 | if (scan_stage == 2 && vpc < len) |
8818c391 TR |
785 | { |
786 | int locals_size = 0; | |
4e99ad69 | 787 | static const unsigned char img[] = { |
2e5ff58c TR |
788 | 0x0f, 0xb6, /* in r0,0x3f */ |
789 | 0xf8, 0x94, /* cli */ | |
e3d8b004 | 790 | 0xde, 0xbf, /* out 0x3e,r29 ; SPH */ |
2e5ff58c | 791 | 0x0f, 0xbe, /* out 0x3f,r0 ; SREG */ |
e3d8b004 | 792 | 0xcd, 0xbf /* out 0x3d,r28 ; SPL */ |
8818c391 | 793 | }; |
4e99ad69 | 794 | static const unsigned char img_sig[] = { |
e3d8b004 TR |
795 | 0xde, 0xbf, /* out 0x3e,r29 ; SPH */ |
796 | 0xcd, 0xbf /* out 0x3d,r28 ; SPL */ | |
8818c391 | 797 | }; |
4e99ad69 | 798 | static const unsigned char img_int[] = { |
2e5ff58c | 799 | 0xf8, 0x94, /* cli */ |
e3d8b004 | 800 | 0xde, 0xbf, /* out 0x3e,r29 ; SPH */ |
2e5ff58c | 801 | 0x78, 0x94, /* sei */ |
e3d8b004 | 802 | 0xcd, 0xbf /* out 0x3d,r28 ; SPL */ |
8818c391 | 803 | }; |
2e5ff58c | 804 | |
e17a4113 | 805 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
2e5ff58c | 806 | if ((insn & 0xff30) == 0x9720) /* sbiw r28,XXX */ |
1bd0bb72 TG |
807 | { |
808 | locals_size = (insn & 0xf) | ((insn & 0xc0) >> 2); | |
809 | vpc += 2; | |
810 | } | |
2e5ff58c TR |
811 | else if ((insn & 0xf0f0) == 0x50c0) /* subi r28,lo8(XX) */ |
812 | { | |
813 | locals_size = (insn & 0xf) | ((insn & 0xf00) >> 4); | |
1bd0bb72 | 814 | vpc += 2; |
e17a4113 | 815 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
2e5ff58c | 816 | vpc += 2; |
1bd0bb72 | 817 | locals_size += ((insn & 0xf) | ((insn & 0xf00) >> 4)) << 8; |
2e5ff58c | 818 | } |
8818c391 | 819 | else |
1bd0bb72 | 820 | return pc_beg + vpc; |
4add8633 | 821 | |
0963b4bd | 822 | /* Scan the last part of the prologue. May not be present for interrupt |
4add8633 TR |
823 | or signal handler functions, which is why we set the prologue type |
824 | when we saw the beginning of the prologue previously. */ | |
825 | ||
4e99ad69 TG |
826 | if (vpc + sizeof (img_sig) < len |
827 | && memcmp (prologue + vpc, img_sig, sizeof (img_sig)) == 0) | |
4add8633 TR |
828 | { |
829 | vpc += sizeof (img_sig); | |
830 | } | |
4e99ad69 TG |
831 | else if (vpc + sizeof (img_int) < len |
832 | && memcmp (prologue + vpc, img_int, sizeof (img_int)) == 0) | |
4add8633 TR |
833 | { |
834 | vpc += sizeof (img_int); | |
835 | } | |
4e99ad69 TG |
836 | if (vpc + sizeof (img) < len |
837 | && memcmp (prologue + vpc, img, sizeof (img)) == 0) | |
4add8633 TR |
838 | { |
839 | info->prologue_type = AVR_PROLOGUE_NORMAL; | |
840 | vpc += sizeof (img); | |
841 | } | |
842 | ||
843 | info->size += locals_size; | |
844 | ||
4e99ad69 | 845 | /* Fall through. */ |
8818c391 | 846 | } |
4add8633 TR |
847 | |
848 | /* If we got this far, we could not scan the prologue, so just return the pc | |
849 | of the frame plus an adjustment for argument move insns. */ | |
850 | ||
4e99ad69 TG |
851 | for (; vpc < len; vpc += 2) |
852 | { | |
e17a4113 | 853 | insn = extract_unsigned_integer (&prologue[vpc], 2, byte_order); |
4e99ad69 TG |
854 | if ((insn & 0xff00) == 0x0100) /* movw rXX, rYY */ |
855 | continue; | |
856 | else if ((insn & 0xfc00) == 0x2c00) /* mov rXX, rYY */ | |
857 | continue; | |
858 | else | |
859 | break; | |
860 | } | |
861 | ||
862 | return pc_beg + vpc; | |
8818c391 TR |
863 | } |
864 | ||
4add8633 | 865 | static CORE_ADDR |
6093d2eb | 866 | avr_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
4add8633 TR |
867 | { |
868 | CORE_ADDR func_addr, func_end; | |
8c201e54 | 869 | CORE_ADDR post_prologue_pc; |
8818c391 | 870 | |
4add8633 | 871 | /* See what the symbol table says */ |
8818c391 | 872 | |
8c201e54 TG |
873 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
874 | return pc; | |
2e5ff58c | 875 | |
8c201e54 TG |
876 | post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); |
877 | if (post_prologue_pc != 0) | |
878 | return max (pc, post_prologue_pc); | |
8818c391 | 879 | |
8c201e54 TG |
880 | { |
881 | CORE_ADDR prologue_end = pc; | |
882 | struct avr_unwind_cache info = {0}; | |
883 | struct trad_frame_saved_reg saved_regs[AVR_NUM_REGS]; | |
8818c391 | 884 | |
8c201e54 TG |
885 | info.saved_regs = saved_regs; |
886 | ||
887 | /* Need to run the prologue scanner to figure out if the function has a | |
888 | prologue and possibly skip over moving arguments passed via registers | |
889 | to other registers. */ | |
890 | ||
891 | prologue_end = avr_scan_prologue (gdbarch, func_addr, func_end, &info); | |
892 | ||
893 | if (info.prologue_type != AVR_PROLOGUE_NONE) | |
894 | return prologue_end; | |
895 | } | |
2e5ff58c | 896 | |
4e99ad69 TG |
897 | /* Either we didn't find the start of this function (nothing we can do), |
898 | or there's no line info, or the line after the prologue is after | |
0963b4bd | 899 | the end of the function (there probably isn't a prologue). */ |
2e5ff58c | 900 | |
8c201e54 | 901 | return pc; |
4add8633 | 902 | } |
8818c391 | 903 | |
0963b4bd MS |
904 | /* Not all avr devices support the BREAK insn. Those that don't should treat |
905 | it as a NOP. Thus, it should be ok. Since the avr is currently a remote | |
906 | only target, this shouldn't be a problem (I hope). TRoth/2003-05-14 */ | |
8818c391 | 907 | |
4add8633 | 908 | static const unsigned char * |
0963b4bd MS |
909 | avr_breakpoint_from_pc (struct gdbarch *gdbarch, |
910 | CORE_ADDR *pcptr, int *lenptr) | |
4add8633 | 911 | { |
4e99ad69 | 912 | static const unsigned char avr_break_insn [] = { 0x98, 0x95 }; |
4add8633 TR |
913 | *lenptr = sizeof (avr_break_insn); |
914 | return avr_break_insn; | |
8818c391 TR |
915 | } |
916 | ||
4c8b6ae0 UW |
917 | /* Determine, for architecture GDBARCH, how a return value of TYPE |
918 | should be returned. If it is supposed to be returned in registers, | |
919 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
920 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
921 | from WRITEBUF into REGCACHE. */ | |
922 | ||
63807e1d | 923 | static enum return_value_convention |
6a3a010b | 924 | avr_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
925 | struct type *valtype, struct regcache *regcache, |
926 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
4c8b6ae0 | 927 | { |
1bd0bb72 TG |
928 | int i; |
929 | /* Single byte are returned in r24. | |
930 | Otherwise, the MSB of the return value is always in r25, calculate which | |
931 | register holds the LSB. */ | |
932 | int lsb_reg; | |
933 | ||
934 | if ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
935 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
936 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
937 | && TYPE_LENGTH (valtype) > 8) | |
938 | return RETURN_VALUE_STRUCT_CONVENTION; | |
939 | ||
940 | if (TYPE_LENGTH (valtype) <= 2) | |
941 | lsb_reg = 24; | |
942 | else if (TYPE_LENGTH (valtype) <= 4) | |
943 | lsb_reg = 22; | |
944 | else if (TYPE_LENGTH (valtype) <= 8) | |
945 | lsb_reg = 18; | |
946 | else | |
f3574227 | 947 | gdb_assert_not_reached ("unexpected type length"); |
4c8b6ae0 UW |
948 | |
949 | if (writebuf != NULL) | |
950 | { | |
1bd0bb72 TG |
951 | for (i = 0; i < TYPE_LENGTH (valtype); i++) |
952 | regcache_cooked_write (regcache, lsb_reg + i, writebuf + i); | |
4c8b6ae0 UW |
953 | } |
954 | ||
955 | if (readbuf != NULL) | |
956 | { | |
1bd0bb72 TG |
957 | for (i = 0; i < TYPE_LENGTH (valtype); i++) |
958 | regcache_cooked_read (regcache, lsb_reg + i, readbuf + i); | |
4c8b6ae0 UW |
959 | } |
960 | ||
1bd0bb72 | 961 | return RETURN_VALUE_REGISTER_CONVENTION; |
4c8b6ae0 UW |
962 | } |
963 | ||
964 | ||
4add8633 TR |
965 | /* Put here the code to store, into fi->saved_regs, the addresses of |
966 | the saved registers of frame described by FRAME_INFO. This | |
967 | includes special registers such as pc and fp saved in special ways | |
968 | in the stack frame. sp is even more special: the address we return | |
0963b4bd | 969 | for it IS the sp for the next frame. */ |
8818c391 | 970 | |
63807e1d | 971 | static struct avr_unwind_cache * |
94afd7a6 | 972 | avr_frame_unwind_cache (struct frame_info *this_frame, |
4add8633 | 973 | void **this_prologue_cache) |
8818c391 | 974 | { |
4e99ad69 | 975 | CORE_ADDR start_pc, current_pc; |
4add8633 TR |
976 | ULONGEST prev_sp; |
977 | ULONGEST this_base; | |
978 | struct avr_unwind_cache *info; | |
4e99ad69 TG |
979 | struct gdbarch *gdbarch; |
980 | struct gdbarch_tdep *tdep; | |
4add8633 TR |
981 | int i; |
982 | ||
4e99ad69 TG |
983 | if (*this_prologue_cache) |
984 | return *this_prologue_cache; | |
4add8633 TR |
985 | |
986 | info = FRAME_OBSTACK_ZALLOC (struct avr_unwind_cache); | |
4e99ad69 | 987 | *this_prologue_cache = info; |
94afd7a6 | 988 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
4add8633 TR |
989 | |
990 | info->size = 0; | |
991 | info->prologue_type = AVR_PROLOGUE_NONE; | |
992 | ||
4e99ad69 TG |
993 | start_pc = get_frame_func (this_frame); |
994 | current_pc = get_frame_pc (this_frame); | |
995 | if ((start_pc > 0) && (start_pc <= current_pc)) | |
e17a4113 UW |
996 | avr_scan_prologue (get_frame_arch (this_frame), |
997 | start_pc, current_pc, info); | |
4add8633 | 998 | |
3b85b0f1 TR |
999 | if ((info->prologue_type != AVR_PROLOGUE_NONE) |
1000 | && (info->prologue_type != AVR_PROLOGUE_MAIN)) | |
4add8633 TR |
1001 | { |
1002 | ULONGEST high_base; /* High byte of FP */ | |
1003 | ||
1004 | /* The SP was moved to the FP. This indicates that a new frame | |
1005 | was created. Get THIS frame's FP value by unwinding it from | |
1006 | the next frame. */ | |
94afd7a6 | 1007 | this_base = get_frame_register_unsigned (this_frame, AVR_FP_REGNUM); |
4e99ad69 | 1008 | high_base = get_frame_register_unsigned (this_frame, AVR_FP_REGNUM + 1); |
4add8633 TR |
1009 | this_base += (high_base << 8); |
1010 | ||
1011 | /* The FP points at the last saved register. Adjust the FP back | |
1012 | to before the first saved register giving the SP. */ | |
1013 | prev_sp = this_base + info->size; | |
1014 | } | |
8818c391 | 1015 | else |
4add8633 TR |
1016 | { |
1017 | /* Assume that the FP is this frame's SP but with that pushed | |
1018 | stack space added back. */ | |
94afd7a6 | 1019 | this_base = get_frame_register_unsigned (this_frame, AVR_SP_REGNUM); |
4add8633 TR |
1020 | prev_sp = this_base + info->size; |
1021 | } | |
1022 | ||
1023 | /* Add 1 here to adjust for the post-decrement nature of the push | |
1024 | instruction.*/ | |
4e99ad69 | 1025 | info->prev_sp = avr_make_saddr (prev_sp + 1); |
4add8633 TR |
1026 | info->base = avr_make_saddr (this_base); |
1027 | ||
4e99ad69 TG |
1028 | gdbarch = get_frame_arch (this_frame); |
1029 | ||
4add8633 | 1030 | /* Adjust all the saved registers so that they contain addresses and not |
3b85b0f1 | 1031 | offsets. */ |
4e99ad69 TG |
1032 | for (i = 0; i < gdbarch_num_regs (gdbarch) - 1; i++) |
1033 | if (info->saved_regs[i].addr > 0) | |
1034 | info->saved_regs[i].addr = info->prev_sp - info->saved_regs[i].addr; | |
4add8633 TR |
1035 | |
1036 | /* Except for the main and startup code, the return PC is always saved on | |
0963b4bd | 1037 | the stack and is at the base of the frame. */ |
4add8633 TR |
1038 | |
1039 | if (info->prologue_type != AVR_PROLOGUE_MAIN) | |
4e99ad69 | 1040 | info->saved_regs[AVR_PC_REGNUM].addr = info->prev_sp; |
4add8633 | 1041 | |
3b85b0f1 TR |
1042 | /* The previous frame's SP needed to be computed. Save the computed |
1043 | value. */ | |
4e99ad69 TG |
1044 | tdep = gdbarch_tdep (gdbarch); |
1045 | trad_frame_set_value (info->saved_regs, AVR_SP_REGNUM, | |
1046 | info->prev_sp - 1 + tdep->call_length); | |
3b85b0f1 | 1047 | |
4add8633 | 1048 | return info; |
8818c391 TR |
1049 | } |
1050 | ||
1051 | static CORE_ADDR | |
4add8633 | 1052 | avr_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
8818c391 | 1053 | { |
4add8633 TR |
1054 | ULONGEST pc; |
1055 | ||
11411de3 | 1056 | pc = frame_unwind_register_unsigned (next_frame, AVR_PC_REGNUM); |
4add8633 TR |
1057 | |
1058 | return avr_make_iaddr (pc); | |
8818c391 TR |
1059 | } |
1060 | ||
30244cd8 UW |
1061 | static CORE_ADDR |
1062 | avr_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1063 | { | |
1064 | ULONGEST sp; | |
1065 | ||
11411de3 | 1066 | sp = frame_unwind_register_unsigned (next_frame, AVR_SP_REGNUM); |
30244cd8 UW |
1067 | |
1068 | return avr_make_saddr (sp); | |
1069 | } | |
1070 | ||
4add8633 TR |
1071 | /* Given a GDB frame, determine the address of the calling function's |
1072 | frame. This will be used to create a new GDB frame struct. */ | |
8818c391 | 1073 | |
4add8633 | 1074 | static void |
94afd7a6 | 1075 | avr_frame_this_id (struct frame_info *this_frame, |
4add8633 TR |
1076 | void **this_prologue_cache, |
1077 | struct frame_id *this_id) | |
8818c391 | 1078 | { |
4add8633 | 1079 | struct avr_unwind_cache *info |
94afd7a6 | 1080 | = avr_frame_unwind_cache (this_frame, this_prologue_cache); |
4add8633 TR |
1081 | CORE_ADDR base; |
1082 | CORE_ADDR func; | |
1083 | struct frame_id id; | |
1084 | ||
1085 | /* The FUNC is easy. */ | |
94afd7a6 | 1086 | func = get_frame_func (this_frame); |
4add8633 | 1087 | |
4add8633 TR |
1088 | /* Hopefully the prologue analysis either correctly determined the |
1089 | frame's base (which is the SP from the previous frame), or set | |
1090 | that base to "NULL". */ | |
1091 | base = info->prev_sp; | |
1092 | if (base == 0) | |
1093 | return; | |
1094 | ||
1095 | id = frame_id_build (base, func); | |
4add8633 | 1096 | (*this_id) = id; |
8818c391 TR |
1097 | } |
1098 | ||
94afd7a6 UW |
1099 | static struct value * |
1100 | avr_frame_prev_register (struct frame_info *this_frame, | |
4e99ad69 | 1101 | void **this_prologue_cache, int regnum) |
8818c391 | 1102 | { |
e17a4113 UW |
1103 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1104 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
4add8633 | 1105 | struct avr_unwind_cache *info |
94afd7a6 | 1106 | = avr_frame_unwind_cache (this_frame, this_prologue_cache); |
8818c391 | 1107 | |
7d2552b4 | 1108 | if (regnum == AVR_PC_REGNUM || regnum == AVR_PSEUDO_PC_REGNUM) |
3b85b0f1 | 1109 | { |
7d2552b4 | 1110 | if (trad_frame_addr_p (info->saved_regs, AVR_PC_REGNUM)) |
3b85b0f1 | 1111 | { |
94afd7a6 UW |
1112 | /* Reading the return PC from the PC register is slightly |
1113 | abnormal. register_size(AVR_PC_REGNUM) says it is 4 bytes, | |
1114 | but in reality, only two bytes (3 in upcoming mega256) are | |
1115 | stored on the stack. | |
1116 | ||
1117 | Also, note that the value on the stack is an addr to a word | |
1118 | not a byte, so we will need to multiply it by two at some | |
1119 | point. | |
1120 | ||
1121 | And to confuse matters even more, the return address stored | |
1122 | on the stack is in big endian byte order, even though most | |
0963b4bd | 1123 | everything else about the avr is little endian. Ick! */ |
94afd7a6 | 1124 | ULONGEST pc; |
4e99ad69 | 1125 | int i; |
e362b510 | 1126 | gdb_byte buf[3]; |
4e99ad69 TG |
1127 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1128 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
94afd7a6 | 1129 | |
7d2552b4 TG |
1130 | read_memory (info->saved_regs[AVR_PC_REGNUM].addr, |
1131 | buf, tdep->call_length); | |
94afd7a6 | 1132 | |
4e99ad69 TG |
1133 | /* Extract the PC read from memory as a big-endian. */ |
1134 | pc = 0; | |
1135 | for (i = 0; i < tdep->call_length; i++) | |
1136 | pc = (pc << 8) | buf[i]; | |
94afd7a6 | 1137 | |
7d2552b4 TG |
1138 | if (regnum == AVR_PC_REGNUM) |
1139 | pc <<= 1; | |
1140 | ||
1141 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
3b85b0f1 | 1142 | } |
94afd7a6 UW |
1143 | |
1144 | return frame_unwind_got_optimized (this_frame, regnum); | |
3b85b0f1 | 1145 | } |
94afd7a6 UW |
1146 | |
1147 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
4add8633 | 1148 | } |
8818c391 | 1149 | |
4add8633 TR |
1150 | static const struct frame_unwind avr_frame_unwind = { |
1151 | NORMAL_FRAME, | |
8fbca658 | 1152 | default_frame_unwind_stop_reason, |
4add8633 | 1153 | avr_frame_this_id, |
94afd7a6 UW |
1154 | avr_frame_prev_register, |
1155 | NULL, | |
1156 | default_frame_sniffer | |
4add8633 TR |
1157 | }; |
1158 | ||
8818c391 | 1159 | static CORE_ADDR |
94afd7a6 | 1160 | avr_frame_base_address (struct frame_info *this_frame, void **this_cache) |
8818c391 | 1161 | { |
4add8633 | 1162 | struct avr_unwind_cache *info |
94afd7a6 | 1163 | = avr_frame_unwind_cache (this_frame, this_cache); |
8818c391 | 1164 | |
4add8633 TR |
1165 | return info->base; |
1166 | } | |
8818c391 | 1167 | |
4add8633 TR |
1168 | static const struct frame_base avr_frame_base = { |
1169 | &avr_frame_unwind, | |
1170 | avr_frame_base_address, | |
1171 | avr_frame_base_address, | |
1172 | avr_frame_base_address | |
1173 | }; | |
ced15480 | 1174 | |
94afd7a6 UW |
1175 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
1176 | frame. The frame ID's base needs to match the TOS value saved by | |
1177 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
8818c391 | 1178 | |
4add8633 | 1179 | static struct frame_id |
94afd7a6 | 1180 | avr_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
4add8633 TR |
1181 | { |
1182 | ULONGEST base; | |
8818c391 | 1183 | |
94afd7a6 UW |
1184 | base = get_frame_register_unsigned (this_frame, AVR_SP_REGNUM); |
1185 | return frame_id_build (avr_make_saddr (base), get_frame_pc (this_frame)); | |
8818c391 TR |
1186 | } |
1187 | ||
4add8633 | 1188 | /* When arguments must be pushed onto the stack, they go on in reverse |
0963b4bd | 1189 | order. The below implements a FILO (stack) to do this. */ |
8818c391 | 1190 | |
4add8633 TR |
1191 | struct stack_item |
1192 | { | |
1193 | int len; | |
1194 | struct stack_item *prev; | |
1195 | void *data; | |
1196 | }; | |
8818c391 | 1197 | |
4add8633 | 1198 | static struct stack_item * |
0fd88904 | 1199 | push_stack_item (struct stack_item *prev, const bfd_byte *contents, int len) |
8818c391 | 1200 | { |
4add8633 TR |
1201 | struct stack_item *si; |
1202 | si = xmalloc (sizeof (struct stack_item)); | |
1203 | si->data = xmalloc (len); | |
1204 | si->len = len; | |
1205 | si->prev = prev; | |
1206 | memcpy (si->data, contents, len); | |
1207 | return si; | |
8818c391 TR |
1208 | } |
1209 | ||
4add8633 TR |
1210 | static struct stack_item *pop_stack_item (struct stack_item *si); |
1211 | static struct stack_item * | |
1212 | pop_stack_item (struct stack_item *si) | |
8818c391 | 1213 | { |
4add8633 TR |
1214 | struct stack_item *dead = si; |
1215 | si = si->prev; | |
1216 | xfree (dead->data); | |
1217 | xfree (dead); | |
1218 | return si; | |
8818c391 TR |
1219 | } |
1220 | ||
8818c391 TR |
1221 | /* Setup the function arguments for calling a function in the inferior. |
1222 | ||
1223 | On the AVR architecture, there are 18 registers (R25 to R8) which are | |
1224 | dedicated for passing function arguments. Up to the first 18 arguments | |
1225 | (depending on size) may go into these registers. The rest go on the stack. | |
1226 | ||
4add8633 | 1227 | All arguments are aligned to start in even-numbered registers (odd-sized |
0963b4bd | 1228 | arguments, including char, have one free register above them). For example, |
4add8633 TR |
1229 | an int in arg1 and a char in arg2 would be passed as such: |
1230 | ||
1231 | arg1 -> r25:r24 | |
1232 | arg2 -> r22 | |
1233 | ||
1234 | Arguments that are larger than 2 bytes will be split between two or more | |
1235 | registers as available, but will NOT be split between a register and the | |
0963b4bd | 1236 | stack. Arguments that go onto the stack are pushed last arg first (this is |
4add8633 TR |
1237 | similar to the d10v). */ |
1238 | ||
1239 | /* NOTE: TRoth/2003-06-17: The rest of this comment is old looks to be | |
1240 | inaccurate. | |
8818c391 TR |
1241 | |
1242 | An exceptional case exists for struct arguments (and possibly other | |
1243 | aggregates such as arrays) -- if the size is larger than WORDSIZE bytes but | |
1244 | not a multiple of WORDSIZE bytes. In this case the argument is never split | |
1245 | between the registers and the stack, but instead is copied in its entirety | |
1246 | onto the stack, AND also copied into as many registers as there is room | |
1247 | for. In other words, space in registers permitting, two copies of the same | |
1248 | argument are passed in. As far as I can tell, only the one on the stack is | |
1249 | used, although that may be a function of the level of compiler | |
1250 | optimization. I suspect this is a compiler bug. Arguments of these odd | |
1251 | sizes are left-justified within the word (as opposed to arguments smaller | |
1252 | than WORDSIZE bytes, which are right-justified). | |
1253 | ||
1254 | If the function is to return an aggregate type such as a struct, the caller | |
1255 | must allocate space into which the callee will copy the return value. In | |
1256 | this case, a pointer to the return value location is passed into the callee | |
1257 | in register R0, which displaces one of the other arguments passed in via | |
0963b4bd | 1258 | registers R0 to R2. */ |
8818c391 TR |
1259 | |
1260 | static CORE_ADDR | |
7d9b040b | 1261 | avr_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
4add8633 TR |
1262 | struct regcache *regcache, CORE_ADDR bp_addr, |
1263 | int nargs, struct value **args, CORE_ADDR sp, | |
1264 | int struct_return, CORE_ADDR struct_addr) | |
8818c391 | 1265 | { |
e17a4113 | 1266 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4add8633 | 1267 | int i; |
e362b510 | 1268 | gdb_byte buf[3]; |
6d1915d4 | 1269 | int call_length = gdbarch_tdep (gdbarch)->call_length; |
4add8633 TR |
1270 | CORE_ADDR return_pc = avr_convert_iaddr_to_raw (bp_addr); |
1271 | int regnum = AVR_ARGN_REGNUM; | |
1272 | struct stack_item *si = NULL; | |
8818c391 | 1273 | |
4add8633 | 1274 | if (struct_return) |
8818c391 | 1275 | { |
fd6d6815 TG |
1276 | regcache_cooked_write_unsigned |
1277 | (regcache, regnum--, (struct_addr >> 8) & 0xff); | |
1278 | regcache_cooked_write_unsigned | |
1279 | (regcache, regnum--, struct_addr & 0xff); | |
1280 | /* SP being post decremented, we need to reserve one byte so that the | |
1281 | return address won't overwrite the result (or vice-versa). */ | |
1282 | if (sp == struct_addr) | |
1283 | sp--; | |
8818c391 TR |
1284 | } |
1285 | ||
4add8633 | 1286 | for (i = 0; i < nargs; i++) |
8818c391 | 1287 | { |
4add8633 TR |
1288 | int last_regnum; |
1289 | int j; | |
1290 | struct value *arg = args[i]; | |
4991999e | 1291 | struct type *type = check_typedef (value_type (arg)); |
0fd88904 | 1292 | const bfd_byte *contents = value_contents (arg); |
4add8633 TR |
1293 | int len = TYPE_LENGTH (type); |
1294 | ||
0963b4bd | 1295 | /* Calculate the potential last register needed. */ |
4add8633 TR |
1296 | last_regnum = regnum - (len + (len & 1)); |
1297 | ||
0963b4bd MS |
1298 | /* If there are registers available, use them. Once we start putting |
1299 | stuff on the stack, all subsequent args go on stack. */ | |
4add8633 TR |
1300 | if ((si == NULL) && (last_regnum >= 8)) |
1301 | { | |
1302 | ULONGEST val; | |
1303 | ||
0963b4bd | 1304 | /* Skip a register for odd length args. */ |
4add8633 TR |
1305 | if (len & 1) |
1306 | regnum--; | |
1307 | ||
e17a4113 | 1308 | val = extract_unsigned_integer (contents, len, byte_order); |
6d1915d4 TG |
1309 | for (j = 0; j < len; j++) |
1310 | regcache_cooked_write_unsigned | |
1311 | (regcache, regnum--, val >> (8 * (len - j - 1))); | |
4add8633 | 1312 | } |
0963b4bd | 1313 | /* No registers available, push the args onto the stack. */ |
4add8633 TR |
1314 | else |
1315 | { | |
0963b4bd | 1316 | /* From here on, we don't care about regnum. */ |
4add8633 TR |
1317 | si = push_stack_item (si, contents, len); |
1318 | } | |
8818c391 | 1319 | } |
909cd28e | 1320 | |
0963b4bd | 1321 | /* Push args onto the stack. */ |
4add8633 TR |
1322 | while (si) |
1323 | { | |
1324 | sp -= si->len; | |
0963b4bd | 1325 | /* Add 1 to sp here to account for post decr nature of pushes. */ |
4e99ad69 | 1326 | write_memory (sp + 1, si->data, si->len); |
4add8633 TR |
1327 | si = pop_stack_item (si); |
1328 | } | |
3605c34a | 1329 | |
4add8633 TR |
1330 | /* Set the return address. For the avr, the return address is the BP_ADDR. |
1331 | Need to push the return address onto the stack noting that it needs to be | |
1332 | in big-endian order on the stack. */ | |
6d1915d4 TG |
1333 | for (i = 1; i <= call_length; i++) |
1334 | { | |
1335 | buf[call_length - i] = return_pc & 0xff; | |
1336 | return_pc >>= 8; | |
1337 | } | |
3605c34a | 1338 | |
6d1915d4 | 1339 | sp -= call_length; |
0963b4bd | 1340 | /* Use 'sp + 1' since pushes are post decr ops. */ |
6d1915d4 | 1341 | write_memory (sp + 1, buf, call_length); |
3605c34a | 1342 | |
0963b4bd | 1343 | /* Finally, update the SP register. */ |
4add8633 TR |
1344 | regcache_cooked_write_unsigned (regcache, AVR_SP_REGNUM, |
1345 | avr_convert_saddr_to_raw (sp)); | |
3605c34a | 1346 | |
6d1915d4 TG |
1347 | /* Return SP value for the dummy frame, where the return address hasn't been |
1348 | pushed. */ | |
1349 | return sp + call_length; | |
3605c34a TR |
1350 | } |
1351 | ||
53f6a2c9 TG |
1352 | /* Unfortunately dwarf2 register for SP is 32. */ |
1353 | ||
1354 | static int | |
1355 | avr_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
1356 | { | |
1357 | if (reg >= 0 && reg < 32) | |
1358 | return reg; | |
1359 | if (reg == 32) | |
1360 | return AVR_SP_REGNUM; | |
1361 | ||
1362 | warning (_("Unmapped DWARF Register #%d encountered."), reg); | |
1363 | ||
1364 | return -1; | |
1365 | } | |
1366 | ||
487d9753 PL |
1367 | /* Implementation of `address_class_type_flags' gdbarch method. |
1368 | ||
1369 | This method maps DW_AT_address_class attributes to a | |
1370 | type_instance_flag_value. */ | |
1371 | ||
1372 | static int | |
1373 | avr_address_class_type_flags (int byte_size, int dwarf2_addr_class) | |
1374 | { | |
1375 | /* The value 1 of the DW_AT_address_class attribute corresponds to the | |
1376 | __flash qualifier. Note that this attribute is only valid with | |
1377 | pointer types and therefore the flag is set to the pointer type and | |
1378 | not its target type. */ | |
1379 | if (dwarf2_addr_class == 1 && byte_size == 2) | |
1380 | return AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH; | |
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | /* Implementation of `address_class_type_flags_to_name' gdbarch method. | |
1385 | ||
1386 | Convert a type_instance_flag_value to an address space qualifier. */ | |
1387 | ||
1388 | static const char* | |
1389 | avr_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags) | |
1390 | { | |
1391 | if (type_flags & AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH) | |
1392 | return "flash"; | |
1393 | else | |
1394 | return NULL; | |
1395 | } | |
1396 | ||
1397 | /* Implementation of `address_class_name_to_type_flags' gdbarch method. | |
1398 | ||
1399 | Convert an address space qualifier to a type_instance_flag_value. */ | |
1400 | ||
1401 | static int | |
1402 | avr_address_class_name_to_type_flags (struct gdbarch *gdbarch, | |
1403 | const char* name, | |
1404 | int *type_flags_ptr) | |
1405 | { | |
1406 | if (strcmp (name, "flash") == 0) | |
1407 | { | |
1408 | *type_flags_ptr = AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH; | |
1409 | return 1; | |
1410 | } | |
1411 | else | |
1412 | return 0; | |
1413 | } | |
1414 | ||
0963b4bd | 1415 | /* Initialize the gdbarch structure for the AVR's. */ |
8818c391 TR |
1416 | |
1417 | static struct gdbarch * | |
2e5ff58c TR |
1418 | avr_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
1419 | { | |
2e5ff58c TR |
1420 | struct gdbarch *gdbarch; |
1421 | struct gdbarch_tdep *tdep; | |
4e99ad69 TG |
1422 | struct gdbarch_list *best_arch; |
1423 | int call_length; | |
8818c391 | 1424 | |
4e99ad69 | 1425 | /* Avr-6 call instructions save 3 bytes. */ |
8818c391 TR |
1426 | switch (info.bfd_arch_info->mach) |
1427 | { | |
1428 | case bfd_mach_avr1: | |
9c97a070 | 1429 | case bfd_mach_avrxmega1: |
8818c391 | 1430 | case bfd_mach_avr2: |
9c97a070 | 1431 | case bfd_mach_avrxmega2: |
8818c391 | 1432 | case bfd_mach_avr3: |
9c97a070 | 1433 | case bfd_mach_avrxmega3: |
8818c391 | 1434 | case bfd_mach_avr4: |
9c97a070 | 1435 | case bfd_mach_avrxmega4: |
8818c391 | 1436 | case bfd_mach_avr5: |
9c97a070 | 1437 | case bfd_mach_avrxmega5: |
4e99ad69 TG |
1438 | default: |
1439 | call_length = 2; | |
1440 | break; | |
1441 | case bfd_mach_avr6: | |
9c97a070 PL |
1442 | case bfd_mach_avrxmega6: |
1443 | case bfd_mach_avrxmega7: | |
4e99ad69 | 1444 | call_length = 3; |
8818c391 TR |
1445 | break; |
1446 | } | |
1447 | ||
4e99ad69 TG |
1448 | /* If there is already a candidate, use it. */ |
1449 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
1450 | best_arch != NULL; | |
1451 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
1452 | { | |
1453 | if (gdbarch_tdep (best_arch->gdbarch)->call_length == call_length) | |
1454 | return best_arch->gdbarch; | |
1455 | } | |
1456 | ||
0963b4bd | 1457 | /* None found, create a new architecture from the information provided. */ |
70ba0933 | 1458 | tdep = XNEW (struct gdbarch_tdep); |
4e99ad69 TG |
1459 | gdbarch = gdbarch_alloc (&info, tdep); |
1460 | ||
1461 | tdep->call_length = call_length; | |
1462 | ||
7d2552b4 TG |
1463 | /* Create a type for PC. We can't use builtin types here, as they may not |
1464 | be defined. */ | |
1465 | tdep->void_type = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void"); | |
1466 | tdep->func_void_type = make_function_type (tdep->void_type, NULL); | |
1467 | tdep->pc_type = arch_type (gdbarch, TYPE_CODE_PTR, 4, NULL); | |
1468 | TYPE_TARGET_TYPE (tdep->pc_type) = tdep->func_void_type; | |
1469 | TYPE_UNSIGNED (tdep->pc_type) = 1; | |
1470 | ||
8818c391 TR |
1471 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1472 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1473 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1474 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
1475 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1476 | set_gdbarch_addr_bit (gdbarch, 32); | |
8818c391 TR |
1477 | |
1478 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1479 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1480 | set_gdbarch_long_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1481 | ||
8da61cc4 DJ |
1482 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
1483 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); | |
1484 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_single); | |
8818c391 TR |
1485 | |
1486 | set_gdbarch_read_pc (gdbarch, avr_read_pc); | |
1487 | set_gdbarch_write_pc (gdbarch, avr_write_pc); | |
8818c391 TR |
1488 | |
1489 | set_gdbarch_num_regs (gdbarch, AVR_NUM_REGS); | |
1490 | ||
1491 | set_gdbarch_sp_regnum (gdbarch, AVR_SP_REGNUM); | |
8818c391 TR |
1492 | set_gdbarch_pc_regnum (gdbarch, AVR_PC_REGNUM); |
1493 | ||
1494 | set_gdbarch_register_name (gdbarch, avr_register_name); | |
866b76ea | 1495 | set_gdbarch_register_type (gdbarch, avr_register_type); |
8818c391 | 1496 | |
7d2552b4 TG |
1497 | set_gdbarch_num_pseudo_regs (gdbarch, AVR_NUM_PSEUDO_REGS); |
1498 | set_gdbarch_pseudo_register_read (gdbarch, avr_pseudo_register_read); | |
1499 | set_gdbarch_pseudo_register_write (gdbarch, avr_pseudo_register_write); | |
1500 | ||
4c8b6ae0 | 1501 | set_gdbarch_return_value (gdbarch, avr_return_value); |
8818c391 TR |
1502 | set_gdbarch_print_insn (gdbarch, print_insn_avr); |
1503 | ||
4add8633 | 1504 | set_gdbarch_push_dummy_call (gdbarch, avr_push_dummy_call); |
8818c391 | 1505 | |
53f6a2c9 TG |
1506 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, avr_dwarf_reg_to_regnum); |
1507 | ||
8818c391 TR |
1508 | set_gdbarch_address_to_pointer (gdbarch, avr_address_to_pointer); |
1509 | set_gdbarch_pointer_to_address (gdbarch, avr_pointer_to_address); | |
8a1d23b2 | 1510 | set_gdbarch_integer_to_address (gdbarch, avr_integer_to_address); |
8818c391 | 1511 | |
8818c391 | 1512 | set_gdbarch_skip_prologue (gdbarch, avr_skip_prologue); |
8818c391 TR |
1513 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
1514 | ||
909cd28e | 1515 | set_gdbarch_breakpoint_from_pc (gdbarch, avr_breakpoint_from_pc); |
8818c391 | 1516 | |
94afd7a6 | 1517 | frame_unwind_append_unwinder (gdbarch, &avr_frame_unwind); |
4add8633 TR |
1518 | frame_base_set_default (gdbarch, &avr_frame_base); |
1519 | ||
94afd7a6 | 1520 | set_gdbarch_dummy_id (gdbarch, avr_dummy_id); |
4add8633 TR |
1521 | |
1522 | set_gdbarch_unwind_pc (gdbarch, avr_unwind_pc); | |
30244cd8 | 1523 | set_gdbarch_unwind_sp (gdbarch, avr_unwind_sp); |
8818c391 | 1524 | |
487d9753 PL |
1525 | set_gdbarch_address_class_type_flags (gdbarch, avr_address_class_type_flags); |
1526 | set_gdbarch_address_class_name_to_type_flags | |
1527 | (gdbarch, avr_address_class_name_to_type_flags); | |
1528 | set_gdbarch_address_class_type_flags_to_name | |
1529 | (gdbarch, avr_address_class_type_flags_to_name); | |
1530 | ||
8818c391 TR |
1531 | return gdbarch; |
1532 | } | |
1533 | ||
1534 | /* Send a query request to the avr remote target asking for values of the io | |
0963b4bd | 1535 | registers. If args parameter is not NULL, then the user has requested info |
8818c391 | 1536 | on a specific io register [This still needs implemented and is ignored for |
0963b4bd | 1537 | now]. The query string should be one of these forms: |
8818c391 TR |
1538 | |
1539 | "Ravr.io_reg" -> reply is "NN" number of io registers | |
1540 | ||
1541 | "Ravr.io_reg:addr,len" where addr is first register and len is number of | |
0963b4bd | 1542 | registers to be read. The reply should be "<NAME>,VV;" for each io register |
8818c391 TR |
1543 | where, <NAME> is a string, and VV is the hex value of the register. |
1544 | ||
0963b4bd | 1545 | All io registers are 8-bit. */ |
8818c391 TR |
1546 | |
1547 | static void | |
1548 | avr_io_reg_read_command (char *args, int from_tty) | |
1549 | { | |
1e3ff5ad | 1550 | LONGEST bufsiz = 0; |
13547ab6 | 1551 | gdb_byte *buf; |
001f13d8 | 1552 | const char *bufstr; |
2e5ff58c | 1553 | char query[400]; |
001f13d8 | 1554 | const char *p; |
2e5ff58c TR |
1555 | unsigned int nreg = 0; |
1556 | unsigned int val; | |
1557 | int i, j, k, step; | |
8818c391 | 1558 | |
0963b4bd | 1559 | /* Find out how many io registers the target has. */ |
13547ab6 DJ |
1560 | bufsiz = target_read_alloc (¤t_target, TARGET_OBJECT_AVR, |
1561 | "avr.io_reg", &buf); | |
001f13d8 | 1562 | bufstr = (const char *) buf; |
8818c391 | 1563 | |
13547ab6 | 1564 | if (bufsiz <= 0) |
8818c391 | 1565 | { |
2e5ff58c | 1566 | fprintf_unfiltered (gdb_stderr, |
13547ab6 DJ |
1567 | _("ERR: info io_registers NOT supported " |
1568 | "by current target\n")); | |
8818c391 TR |
1569 | return; |
1570 | } | |
1571 | ||
001f13d8 | 1572 | if (sscanf (bufstr, "%x", &nreg) != 1) |
8818c391 | 1573 | { |
2e5ff58c | 1574 | fprintf_unfiltered (gdb_stderr, |
edefbb7c | 1575 | _("Error fetching number of io registers\n")); |
13547ab6 | 1576 | xfree (buf); |
8818c391 TR |
1577 | return; |
1578 | } | |
1579 | ||
13547ab6 DJ |
1580 | xfree (buf); |
1581 | ||
2e5ff58c | 1582 | reinitialize_more_filter (); |
8818c391 | 1583 | |
edefbb7c | 1584 | printf_unfiltered (_("Target has %u io registers:\n\n"), nreg); |
8818c391 TR |
1585 | |
1586 | /* only fetch up to 8 registers at a time to keep the buffer small */ | |
1587 | step = 8; | |
1588 | ||
2e5ff58c | 1589 | for (i = 0; i < nreg; i += step) |
8818c391 | 1590 | { |
91ccbfc1 TR |
1591 | /* how many registers this round? */ |
1592 | j = step; | |
1593 | if ((i+j) >= nreg) | |
1594 | j = nreg - i; /* last block is less than 8 registers */ | |
8818c391 | 1595 | |
2e5ff58c | 1596 | snprintf (query, sizeof (query) - 1, "avr.io_reg:%x,%x", i, j); |
13547ab6 DJ |
1597 | bufsiz = target_read_alloc (¤t_target, TARGET_OBJECT_AVR, |
1598 | query, &buf); | |
8818c391 | 1599 | |
001f13d8 | 1600 | p = (const char *) buf; |
2e5ff58c TR |
1601 | for (k = i; k < (i + j); k++) |
1602 | { | |
1603 | if (sscanf (p, "%[^,],%x;", query, &val) == 2) | |
1604 | { | |
1605 | printf_filtered ("[%02x] %-15s : %02x\n", k, query, val); | |
1606 | while ((*p != ';') && (*p != '\0')) | |
1607 | p++; | |
1608 | p++; /* skip over ';' */ | |
1609 | if (*p == '\0') | |
1610 | break; | |
1611 | } | |
1612 | } | |
13547ab6 DJ |
1613 | |
1614 | xfree (buf); | |
8818c391 TR |
1615 | } |
1616 | } | |
1617 | ||
a78f21af AC |
1618 | extern initialize_file_ftype _initialize_avr_tdep; /* -Wmissing-prototypes */ |
1619 | ||
8818c391 TR |
1620 | void |
1621 | _initialize_avr_tdep (void) | |
1622 | { | |
1623 | register_gdbarch_init (bfd_arch_avr, avr_gdbarch_init); | |
1624 | ||
1625 | /* Add a new command to allow the user to query the avr remote target for | |
1626 | the values of the io space registers in a saner way than just using | |
0963b4bd | 1627 | `x/NNNb ADDR`. */ |
8818c391 TR |
1628 | |
1629 | /* FIXME: TRoth/2002-02-18: This should probably be changed to 'info avr | |
0963b4bd | 1630 | io_registers' to signify it is not available on other platforms. */ |
8818c391 TR |
1631 | |
1632 | add_cmd ("io_registers", class_info, avr_io_reg_read_command, | |
1a966eab AC |
1633 | _("query remote avr target for io space register values"), |
1634 | &infolist); | |
8818c391 | 1635 | } |