Commit | Line | Data |
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ed9a39eb | 1 | /* Definitions to target GDB to ARM targets. |
b6ba6518 | 2 | Copyright 1986, 1987, 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, |
c3b4394c | 3 | 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
ed9a39eb JM |
22 | #ifndef TM_ARM_H |
23 | #define TM_ARM_H | |
24 | ||
39bbf761 RE |
25 | #ifndef GDB_MULTI_ARCH |
26 | #define GDB_MULTI_ARCH 1 | |
27 | #endif | |
28 | ||
f88e2c52 | 29 | #include "regcache.h" |
9da8e4f8 | 30 | #include "floatformat.h" |
f88e2c52 | 31 | |
ed9a39eb | 32 | /* IEEE format floating point. */ |
39bbf761 | 33 | #define TARGET_DOUBLE_FORMAT (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG \ |
ed9a39eb JM |
34 | ? &floatformat_ieee_double_big \ |
35 | : &floatformat_ieee_double_littlebyte_bigword) | |
c906108c | 36 | |
ed9a39eb JM |
37 | /* The following define instruction sequences that will cause ARM |
38 | cpu's to take an undefined instruction trap. These are used to | |
39 | signal a breakpoint to GDB. | |
40 | ||
41 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
42 | modes. A different instruction is required for each mode. The ARM | |
43 | cpu's can also be big or little endian. Thus four different | |
44 | instructions are needed to support all cases. | |
45 | ||
46 | Note: ARMv4 defines several new instructions that will take the | |
47 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
48 | not in fact add the new instructions. The new undefined | |
49 | instructions in ARMv4 are all instructions that had no defined | |
50 | behaviour in earlier chips. There is no guarantee that they will | |
51 | raise an exception, but may be treated as NOP's. In practice, it | |
52 | may only safe to rely on instructions matching: | |
53 | ||
54 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
55 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
56 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
57 | ||
58 | Even this may only true if the condition predicate is true. The | |
59 | following use a condition predicate of ALWAYS so it is always TRUE. | |
60 | ||
9512d7fd FN |
61 | There are other ways of forcing a breakpoint. ARM Linux, RISC iX, |
62 | and NetBSD will all use a software interrupt rather than an | |
63 | undefined instruction to force a trap. This can be handled by | |
ed9a39eb JM |
64 | redefining some or all of the following in a target dependent |
65 | fashion. */ | |
66 | ||
67 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
68 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
69 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
70 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
c906108c | 71 | |
c906108c SS |
72 | /* The system C compiler uses a similar structure return convention to gcc */ |
73 | extern use_struct_convention_fn arm_use_struct_convention; | |
ed9a39eb JM |
74 | #define USE_STRUCT_CONVENTION(gcc_p, type) \ |
75 | arm_use_struct_convention (gcc_p, type) | |
c906108c | 76 | |
c906108c SS |
77 | /* Extract from an array REGBUF containing the (raw) register state |
78 | the address in which a function should return its structure value, | |
79 | as a CORE_ADDR (or an expression that can be used as one). */ | |
80 | ||
7a292a7a | 81 | #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \ |
ed9a39eb | 82 | (extract_address ((PTR)(REGBUF), REGISTER_RAW_SIZE(0))) |
c906108c SS |
83 | |
84 | /* Specify that for the native compiler variables for a particular | |
85 | lexical context are listed after the beginning LBRAC instead of | |
86 | before in the executables list of symbols. */ | |
87 | #define VARIABLES_INSIDE_BLOCK(desc, gcc_p) (!(gcc_p)) | |
c906108c | 88 | \f |
34e8f22d | 89 | /* XXX This is NOT multi-arch compatible. */ |
c906108c | 90 | #define CALL_DUMMY_BREAKPOINT_OFFSET arm_call_dummy_breakpoint_offset() |
ed9a39eb | 91 | extern int arm_call_dummy_breakpoint_offset (void); |
c906108c | 92 | |
dfcd3bfb JM |
93 | /* The first 0x20 bytes are the trap vectors. */ |
94 | #define LOWEST_PC 0x20 | |
95 | ||
ed9a39eb | 96 | #endif /* TM_ARM_H */ |