Commit | Line | Data |
---|---|---|
ed9a39eb | 1 | /* Definitions to target GDB to ARM targets. |
b6ba6518 | 2 | Copyright 1986, 1987, 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, |
c3b4394c | 3 | 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
ed9a39eb JM |
22 | #ifndef TM_ARM_H |
23 | #define TM_ARM_H | |
24 | ||
f88e2c52 | 25 | #include "regcache.h" |
9da8e4f8 | 26 | #include "floatformat.h" |
f88e2c52 | 27 | |
ed9a39eb | 28 | /* Forward declarations for prototypes. */ |
c906108c SS |
29 | struct type; |
30 | struct value; | |
c906108c | 31 | |
ed9a39eb | 32 | /* IEEE format floating point. */ |
d7449b42 | 33 | #define TARGET_DOUBLE_FORMAT (target_byte_order == BFD_ENDIAN_BIG \ |
ed9a39eb JM |
34 | ? &floatformat_ieee_double_big \ |
35 | : &floatformat_ieee_double_littlebyte_bigword) | |
c906108c | 36 | |
ed9a39eb JM |
37 | /* When reading symbols, we need to zap the low bit of the address, |
38 | which may be set to 1 for Thumb functions. */ | |
c906108c SS |
39 | |
40 | #define SMASH_TEXT_ADDRESS(addr) ((addr) &= ~0x1) | |
41 | ||
42 | /* Remove useless bits from addresses in a running program. */ | |
43 | ||
ed9a39eb | 44 | CORE_ADDR arm_addr_bits_remove (CORE_ADDR); |
c906108c | 45 | |
ed9a39eb | 46 | #define ADDR_BITS_REMOVE(val) (arm_addr_bits_remove (val)) |
c906108c | 47 | |
ed9a39eb JM |
48 | /* Offset from address of function to start of its code. Zero on most |
49 | machines. */ | |
c906108c | 50 | |
ed9a39eb | 51 | #define FUNCTION_START_OFFSET 0 |
c906108c | 52 | |
ed9a39eb JM |
53 | /* Advance PC across any function entry prologue instructions to reach |
54 | some "real" code. */ | |
c906108c | 55 | |
ed9a39eb | 56 | extern CORE_ADDR arm_skip_prologue (CORE_ADDR pc); |
c906108c | 57 | |
ed9a39eb | 58 | #define SKIP_PROLOGUE(pc) (arm_skip_prologue (pc)) |
c906108c | 59 | |
ed9a39eb JM |
60 | /* Immediately after a function call, return the saved pc. Can't |
61 | always go through the frames for this because on some machines the | |
62 | new frame is not set up until the new function executes some | |
63 | instructions. */ | |
c906108c | 64 | |
ed9a39eb | 65 | #define SAVED_PC_AFTER_CALL(frame) arm_saved_pc_after_call (frame) |
c906108c | 66 | struct frame_info; |
ed9a39eb JM |
67 | extern CORE_ADDR arm_saved_pc_after_call (struct frame_info *); |
68 | ||
69 | /* The following define instruction sequences that will cause ARM | |
70 | cpu's to take an undefined instruction trap. These are used to | |
71 | signal a breakpoint to GDB. | |
72 | ||
73 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
74 | modes. A different instruction is required for each mode. The ARM | |
75 | cpu's can also be big or little endian. Thus four different | |
76 | instructions are needed to support all cases. | |
77 | ||
78 | Note: ARMv4 defines several new instructions that will take the | |
79 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
80 | not in fact add the new instructions. The new undefined | |
81 | instructions in ARMv4 are all instructions that had no defined | |
82 | behaviour in earlier chips. There is no guarantee that they will | |
83 | raise an exception, but may be treated as NOP's. In practice, it | |
84 | may only safe to rely on instructions matching: | |
85 | ||
86 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
87 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
88 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
89 | ||
90 | Even this may only true if the condition predicate is true. The | |
91 | following use a condition predicate of ALWAYS so it is always TRUE. | |
92 | ||
9512d7fd FN |
93 | There are other ways of forcing a breakpoint. ARM Linux, RISC iX, |
94 | and NetBSD will all use a software interrupt rather than an | |
95 | undefined instruction to force a trap. This can be handled by | |
ed9a39eb JM |
96 | redefining some or all of the following in a target dependent |
97 | fashion. */ | |
98 | ||
99 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
100 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
101 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
102 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
c906108c SS |
103 | |
104 | /* Stack grows downward. */ | |
105 | ||
106 | #define INNER_THAN(lhs,rhs) ((lhs) < (rhs)) | |
107 | ||
ed9a39eb JM |
108 | /* !!!! if we're using RDP, then we're inserting breakpoints and |
109 | storing their handles instread of what was in memory. It is nice | |
110 | that this is the same size as a handle - otherwise remote-rdp will | |
c906108c SS |
111 | have to change. */ |
112 | ||
ed9a39eb JM |
113 | /* BREAKPOINT_FROM_PC uses the program counter value to determine |
114 | whether a 16- or 32-bit breakpoint should be used. It returns a | |
115 | pointer to a string of bytes that encode a breakpoint instruction, | |
116 | stores the length of the string to *lenptr, and adjusts the pc (if | |
117 | necessary) to point to the actual memory location where the | |
118 | breakpoint should be inserted. */ | |
c906108c SS |
119 | |
120 | extern breakpoint_from_pc_fn arm_breakpoint_from_pc; | |
121 | #define BREAKPOINT_FROM_PC(pcptr, lenptr) arm_breakpoint_from_pc (pcptr, lenptr) | |
122 | ||
ed9a39eb JM |
123 | /* Amount PC must be decremented by after a breakpoint. This is often |
124 | the number of bytes in BREAKPOINT but not always. */ | |
c906108c SS |
125 | |
126 | #define DECR_PC_AFTER_BREAK 0 | |
127 | ||
ed9a39eb JM |
128 | /* Code to execute to print interesting information about the floating |
129 | point processor (if any) or emulator. No need to define if there | |
130 | is nothing to do. */ | |
104c1213 JM |
131 | extern void arm_float_info (void); |
132 | ||
ed9a39eb | 133 | #define FLOAT_INFO { arm_float_info (); } |
c906108c SS |
134 | |
135 | /* Say how long (ordinary) registers are. This is a piece of bogosity | |
136 | used in push_word and a few other places; REGISTER_RAW_SIZE is the | |
137 | real way to know how big a register is. */ | |
138 | ||
ed9a39eb JM |
139 | #define REGISTER_SIZE 4 |
140 | ||
141 | /* Say how long FP registers are. Used for documentation purposes and | |
142 | code readability in this header. IEEE extended doubles are 80 | |
143 | bits. DWORD aligned they use 96 bits. */ | |
144 | #define FP_REGISTER_RAW_SIZE 12 | |
145 | ||
146 | /* GCC doesn't support long doubles (extended IEEE values). The FP | |
147 | register virtual size is therefore 64 bits. Used for documentation | |
148 | purposes and code readability in this header. */ | |
149 | #define FP_REGISTER_VIRTUAL_SIZE 8 | |
150 | ||
151 | /* Status registers are the same size as general purpose registers. | |
152 | Used for documentation purposes and code readability in this | |
153 | header. */ | |
154 | #define STATUS_REGISTER_SIZE REGISTER_SIZE | |
155 | ||
156 | /* Number of machine registers. The only define actually required | |
157 | is NUM_REGS. The other definitions are used for documentation | |
158 | purposes and code readability. */ | |
159 | /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS) | |
160 | (and called PS for processor status) so the status bits can be cleared | |
161 | from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed | |
162 | in PS. */ | |
163 | #define NUM_FREGS 8 /* Number of floating point registers. */ | |
164 | #define NUM_SREGS 2 /* Number of status registers. */ | |
165 | #define NUM_GREGS 16 /* Number of general purpose registers. */ | |
166 | #define NUM_REGS (NUM_GREGS + NUM_FREGS + NUM_SREGS) | |
c906108c | 167 | |
afe64c1a AC |
168 | /* An array of names of registers. */ |
169 | extern char **arm_register_names; | |
170 | ||
966fbf70 RE |
171 | #define REGISTER_NAME(i) arm_register_name(i) |
172 | char *arm_register_name (int); | |
c906108c | 173 | |
ed9a39eb JM |
174 | /* Register numbers of various important registers. Note that some of |
175 | these values are "real" register numbers, and correspond to the | |
176 | general registers of the machine, and some are "phony" register | |
177 | numbers which are too large to be actual register numbers as far as | |
178 | the user is concerned but do serve to get the desired values when | |
179 | passed to read_register. */ | |
c906108c SS |
180 | |
181 | #define A1_REGNUM 0 /* first integer-like argument */ | |
182 | #define A4_REGNUM 3 /* last integer-like argument */ | |
183 | #define AP_REGNUM 11 | |
184 | #define FP_REGNUM 11 /* Contains address of executing stack frame */ | |
185 | #define SP_REGNUM 13 /* Contains address of top of stack */ | |
186 | #define LR_REGNUM 14 /* address to return to from a function call */ | |
187 | #define PC_REGNUM 15 /* Contains program counter */ | |
188 | #define F0_REGNUM 16 /* first floating point register */ | |
189 | #define F3_REGNUM 19 /* last floating point argument register */ | |
190 | #define F7_REGNUM 23 /* last floating point register */ | |
191 | #define FPS_REGNUM 24 /* floating point status register */ | |
192 | #define PS_REGNUM 25 /* Contains processor status */ | |
193 | ||
194 | #define THUMB_FP_REGNUM 7 /* R7 is frame register on Thumb */ | |
195 | ||
196 | #define ARM_NUM_ARG_REGS 4 | |
197 | #define ARM_LAST_ARG_REGNUM A4_REGNUM | |
198 | #define ARM_NUM_FP_ARG_REGS 4 | |
199 | #define ARM_LAST_FP_ARG_REGNUM F3_REGNUM | |
200 | ||
201 | /* Instruction condition field values. */ | |
202 | #define INST_EQ 0x0 | |
203 | #define INST_NE 0x1 | |
204 | #define INST_CS 0x2 | |
205 | #define INST_CC 0x3 | |
206 | #define INST_MI 0x4 | |
207 | #define INST_PL 0x5 | |
208 | #define INST_VS 0x6 | |
209 | #define INST_VC 0x7 | |
210 | #define INST_HI 0x8 | |
211 | #define INST_LS 0x9 | |
212 | #define INST_GE 0xa | |
213 | #define INST_LT 0xb | |
214 | #define INST_GT 0xc | |
215 | #define INST_LE 0xd | |
216 | #define INST_AL 0xe | |
217 | #define INST_NV 0xf | |
218 | ||
219 | #define FLAG_N 0x80000000 | |
220 | #define FLAG_Z 0x40000000 | |
221 | #define FLAG_C 0x20000000 | |
222 | #define FLAG_V 0x10000000 | |
223 | ||
224 | ||
225 | ||
226 | /* Total amount of space needed to store our copies of the machine's | |
227 | register state, the array `registers'. */ | |
ed9a39eb JM |
228 | |
229 | #define REGISTER_BYTES ((NUM_GREGS * REGISTER_SIZE) + \ | |
230 | (NUM_FREGS * FP_REGISTER_RAW_SIZE) + \ | |
231 | (NUM_SREGS * STATUS_REGISTER_SIZE)) | |
c906108c SS |
232 | |
233 | /* Index within `registers' of the first byte of the space for | |
234 | register N. */ | |
235 | ||
ed9a39eb JM |
236 | #define REGISTER_BYTE(N) \ |
237 | ((N) < F0_REGNUM \ | |
238 | ? (N) * REGISTER_SIZE \ | |
239 | : ((N) < PS_REGNUM \ | |
240 | ? (NUM_GREGS * REGISTER_SIZE + \ | |
241 | ((N) - F0_REGNUM) * FP_REGISTER_RAW_SIZE) \ | |
242 | : (NUM_GREGS * REGISTER_SIZE + \ | |
243 | NUM_FREGS * FP_REGISTER_RAW_SIZE + \ | |
244 | ((N) - FPS_REGNUM) * STATUS_REGISTER_SIZE))) | |
245 | ||
246 | /* Number of bytes of storage in the actual machine representation for | |
247 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
248 | 12 bytes in length. */ | |
249 | #define REGISTER_RAW_SIZE(N) \ | |
250 | ((N) < F0_REGNUM ? REGISTER_SIZE : \ | |
251 | (N) < FPS_REGNUM ? FP_REGISTER_RAW_SIZE : STATUS_REGISTER_SIZE) | |
252 | ||
253 | /* Number of bytes of storage in a program's representation | |
254 | for register N. */ | |
255 | #define REGISTER_VIRTUAL_SIZE(N) \ | |
256 | ((N) < F0_REGNUM ? REGISTER_SIZE : \ | |
257 | (N) < FPS_REGNUM ? FP_REGISTER_VIRTUAL_SIZE : STATUS_REGISTER_SIZE) | |
c906108c SS |
258 | |
259 | /* Largest value REGISTER_RAW_SIZE can have. */ | |
260 | ||
ed9a39eb | 261 | #define MAX_REGISTER_RAW_SIZE FP_REGISTER_RAW_SIZE |
c906108c SS |
262 | |
263 | /* Largest value REGISTER_VIRTUAL_SIZE can have. */ | |
ed9a39eb | 264 | #define MAX_REGISTER_VIRTUAL_SIZE FP_REGISTER_VIRTUAL_SIZE |
c906108c | 265 | |
ed9a39eb JM |
266 | /* Return the GDB type object for the "standard" data type of data in |
267 | register N. */ | |
c906108c | 268 | |
032758dc AC |
269 | extern struct type *arm_register_type (int regnum); |
270 | #define REGISTER_VIRTUAL_TYPE(N) arm_register_type (N) | |
ed9a39eb | 271 | |
c906108c SS |
272 | /* The system C compiler uses a similar structure return convention to gcc */ |
273 | extern use_struct_convention_fn arm_use_struct_convention; | |
ed9a39eb JM |
274 | #define USE_STRUCT_CONVENTION(gcc_p, type) \ |
275 | arm_use_struct_convention (gcc_p, type) | |
c906108c SS |
276 | |
277 | /* Store the address of the place in which to copy the structure the | |
278 | subroutine will return. This is called from call_function. */ | |
279 | ||
280 | #define STORE_STRUCT_RETURN(ADDR, SP) \ | |
ed9a39eb | 281 | write_register (A1_REGNUM, (ADDR)) |
c906108c | 282 | |
ed9a39eb JM |
283 | /* Extract from an array REGBUF containing the (raw) register state a |
284 | function return value of type TYPE, and copy that, in virtual | |
285 | format, into VALBUF. */ | |
c906108c | 286 | |
ed9a39eb | 287 | extern void arm_extract_return_value (struct type *, char[], char *); |
c906108c | 288 | #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \ |
ed9a39eb | 289 | arm_extract_return_value ((TYPE), (REGBUF), (VALBUF)) |
c906108c | 290 | |
ed9a39eb JM |
291 | /* Write into appropriate registers a function return value of type |
292 | TYPE, given in virtual format. */ | |
c906108c | 293 | |
ed9a39eb | 294 | extern void convert_to_extended (void *dbl, void *ptr); |
c906108c SS |
295 | #define STORE_RETURN_VALUE(TYPE,VALBUF) \ |
296 | if (TYPE_CODE (TYPE) == TYPE_CODE_FLT) { \ | |
297 | char _buf[MAX_REGISTER_RAW_SIZE]; \ | |
298 | convert_to_extended (VALBUF, _buf); \ | |
299 | write_register_bytes (REGISTER_BYTE (F0_REGNUM), _buf, MAX_REGISTER_RAW_SIZE); \ | |
300 | } else \ | |
301 | write_register_bytes (0, VALBUF, TYPE_LENGTH (TYPE)) | |
302 | ||
303 | /* Extract from an array REGBUF containing the (raw) register state | |
304 | the address in which a function should return its structure value, | |
305 | as a CORE_ADDR (or an expression that can be used as one). */ | |
306 | ||
7a292a7a | 307 | #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \ |
ed9a39eb | 308 | (extract_address ((PTR)(REGBUF), REGISTER_RAW_SIZE(0))) |
c906108c SS |
309 | |
310 | /* Specify that for the native compiler variables for a particular | |
311 | lexical context are listed after the beginning LBRAC instead of | |
312 | before in the executables list of symbols. */ | |
313 | #define VARIABLES_INSIDE_BLOCK(desc, gcc_p) (!(gcc_p)) | |
c906108c | 314 | \f |
c5aa993b | 315 | |
ed9a39eb | 316 | extern void arm_init_extra_frame_info (int fromleaf, struct frame_info * fi); |
96baa820 | 317 | #define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \ |
ed9a39eb | 318 | arm_init_extra_frame_info ((fromleaf), (fi)) |
c906108c SS |
319 | |
320 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. */ | |
ed9a39eb | 321 | CORE_ADDR arm_target_read_fp (void); |
c906108c SS |
322 | #define TARGET_READ_FP() arm_target_read_fp () |
323 | ||
ed9a39eb JM |
324 | /* Describe the pointer in each stack frame to the previous stack |
325 | frame (its caller). */ | |
c906108c | 326 | |
ed9a39eb JM |
327 | /* FRAME_CHAIN takes a frame's nominal address and produces the |
328 | frame's chain-pointer. | |
c906108c SS |
329 | |
330 | However, if FRAME_CHAIN_VALID returns zero, | |
331 | it means the given frame is the outermost one and has no caller. */ | |
332 | ||
ed9a39eb JM |
333 | #define FRAME_CHAIN(thisframe) arm_frame_chain (thisframe) |
334 | extern CORE_ADDR arm_frame_chain (struct frame_info *); | |
c906108c | 335 | |
ed9a39eb JM |
336 | extern int arm_frame_chain_valid (CORE_ADDR, struct frame_info *); |
337 | #define FRAME_CHAIN_VALID(chain, thisframe) \ | |
338 | arm_frame_chain_valid (chain, thisframe) | |
c906108c SS |
339 | |
340 | /* Define other aspects of the stack frame. */ | |
341 | ||
96baa820 JM |
342 | /* A macro that tells us whether the function invocation represented |
343 | by FI does not have a frame on the stack associated with it. If it | |
344 | does not, FRAMELESS is set to 1, else 0. | |
345 | ||
ed9a39eb JM |
346 | Sometimes we have functions that do a little setup (like saving the |
347 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
96baa820 | 348 | The symbol table will report this as a prologue. However, it is |
ed9a39eb | 349 | important not to try to parse these partial frames as frames, or we |
96baa820 JM |
350 | will get really confused. |
351 | ||
ed9a39eb JM |
352 | So I will demand 3 instructions between the start & end of the |
353 | prologue before I call it a real prologue, i.e. at least | |
96baa820 JM |
354 | mov ip, sp, |
355 | stmdb sp!, {} | |
356 | sub sp, ip, #4. */ | |
357 | ||
104c1213 | 358 | extern int arm_frameless_function_invocation (struct frame_info *fi); |
96baa820 JM |
359 | #define FRAMELESS_FUNCTION_INVOCATION(FI) \ |
360 | (arm_frameless_function_invocation (FI)) | |
ed9a39eb | 361 | |
c906108c SS |
362 | /* Saved Pc. */ |
363 | ||
364 | #define FRAME_SAVED_PC(FRAME) arm_frame_saved_pc (FRAME) | |
ed9a39eb | 365 | extern CORE_ADDR arm_frame_saved_pc (struct frame_info *); |
c906108c SS |
366 | |
367 | #define FRAME_ARGS_ADDRESS(fi) (fi->frame) | |
368 | ||
369 | #define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame) | |
370 | ||
371 | /* Return number of args passed to a frame. | |
372 | Can return -1, meaning no way to tell. */ | |
373 | ||
392a587b | 374 | #define FRAME_NUM_ARGS(fi) (-1) |
c906108c | 375 | |
ed9a39eb | 376 | /* Return number of bytes at start of arglist that are not really args. */ |
c906108c SS |
377 | |
378 | #define FRAME_ARGS_SKIP 0 | |
379 | ||
ed9a39eb JM |
380 | /* Put here the code to store, into a struct frame_saved_regs, the |
381 | addresses of the saved registers of frame described by FRAME_INFO. | |
c906108c | 382 | This includes special registers such as pc and fp saved in special |
ed9a39eb JM |
383 | ways in the stack frame. sp is even more special: the address we |
384 | return for it IS the sp for the next frame. */ | |
c906108c | 385 | |
c3b4394c RE |
386 | void arm_frame_init_saved_regs (struct frame_info *); |
387 | #define FRAME_INIT_SAVED_REGS(frame_info) \ | |
388 | arm_frame_init_saved_regs (frame_info); | |
c5aa993b | 389 | |
c906108c SS |
390 | /* Things needed for making the inferior call functions. */ |
391 | ||
392 | #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \ | |
ed9a39eb JM |
393 | sp = arm_push_arguments ((nargs), (args), (sp), (struct_return), (struct_addr)) |
394 | extern CORE_ADDR arm_push_arguments (int, struct value **, CORE_ADDR, int, | |
395 | CORE_ADDR); | |
c906108c SS |
396 | |
397 | /* Push an empty stack frame, to record the current PC, etc. */ | |
398 | ||
ed9a39eb | 399 | void arm_push_dummy_frame (void); |
c906108c SS |
400 | |
401 | #define PUSH_DUMMY_FRAME arm_push_dummy_frame () | |
402 | ||
403 | /* Discard from the stack the innermost frame, restoring all registers. */ | |
404 | ||
ed9a39eb | 405 | void arm_pop_frame (void); |
c906108c SS |
406 | |
407 | #define POP_FRAME arm_pop_frame () | |
408 | ||
409 | /* This sequence of words is the instructions | |
410 | ||
c5aa993b JM |
411 | mov lr,pc |
412 | mov pc,r4 | |
413 | illegal | |
c906108c SS |
414 | |
415 | Note this is 12 bytes. */ | |
416 | ||
ed9a39eb JM |
417 | #define CALL_DUMMY {0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe} |
418 | #define CALL_DUMMY_START_OFFSET 0 /* Start execution at beginning of dummy */ | |
c906108c SS |
419 | |
420 | #define CALL_DUMMY_BREAKPOINT_OFFSET arm_call_dummy_breakpoint_offset() | |
ed9a39eb | 421 | extern int arm_call_dummy_breakpoint_offset (void); |
c906108c | 422 | |
ed9a39eb JM |
423 | /* Insert the specified number of args and function address into a |
424 | call sequence of the above form stored at DUMMYNAME. */ | |
c906108c SS |
425 | |
426 | #define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \ | |
ed9a39eb | 427 | arm_fix_call_dummy ((dummyname), (pc), (fun), (nargs), (args), (type), (gcc_p)) |
c906108c | 428 | |
ed9a39eb JM |
429 | void arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, |
430 | int nargs, struct value ** args, | |
431 | struct type * type, int gcc_p); | |
c906108c | 432 | |
9512d7fd FN |
433 | /* Most ARMs don't have single stepping capability, so provide a |
434 | single-stepping mechanism by default */ | |
80fcf3f0 FN |
435 | #undef SOFTWARE_SINGLE_STEP_P |
436 | #define SOFTWARE_SINGLE_STEP_P() 1 | |
437 | ||
9512d7fd | 438 | #define SOFTWARE_SINGLE_STEP(sig,bpt) arm_software_single_step((sig), (bpt)) |
c3d45d70 | 439 | void arm_software_single_step (int, int); |
9512d7fd | 440 | |
ed9a39eb | 441 | CORE_ADDR arm_get_next_pc (CORE_ADDR pc); |
c906108c | 442 | |
ed9a39eb JM |
443 | /* Macros for setting and testing a bit in a minimal symbol that marks |
444 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
445 | is used for this purpose. This field is already being used to store | |
446 | the symbol size, so the assumption is that the symbol size cannot | |
447 | exceed 2^31. | |
c5aa993b | 448 | |
c906108c | 449 | COFF_MAKE_MSYMBOL_SPECIAL |
ed9a39eb JM |
450 | ELF_MAKE_MSYMBOL_SPECIAL |
451 | ||
452 | These macros test whether the COFF or ELF symbol corresponds to a | |
453 | thumb function, and set a "special" bit in a minimal symbol to | |
454 | indicate that it does. | |
455 | ||
456 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
457 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
458 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
459 | i.e. the "info" field with the "special" bit | |
460 | masked out | |
461 | */ | |
c5aa993b JM |
462 | |
463 | extern int coff_sym_is_thumb (int val); | |
ed9a39eb | 464 | |
c906108c | 465 | #define MSYMBOL_SET_SPECIAL(msym) \ |
ed9a39eb | 466 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000) |
c906108c SS |
467 | #define MSYMBOL_IS_SPECIAL(msym) \ |
468 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
469 | #define MSYMBOL_SIZE(msym) \ | |
470 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
471 | ||
ed9a39eb | 472 | /* Thumb symbols are of type STT_LOPROC, (synonymous with STT_ARM_TFUNC) */ |
c906108c | 473 | #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \ |
ed9a39eb JM |
474 | { if(ELF_ST_TYPE(((elf_symbol_type *)(sym))->internal_elf_sym.st_info) == STT_LOPROC) \ |
475 | MSYMBOL_SET_SPECIAL(msym); } | |
c5aa993b | 476 | |
c906108c SS |
477 | #define COFF_MAKE_MSYMBOL_SPECIAL(val,msym) \ |
478 | { if(coff_sym_is_thumb(val)) MSYMBOL_SET_SPECIAL(msym); } | |
479 | ||
dfcd3bfb JM |
480 | /* The first 0x20 bytes are the trap vectors. */ |
481 | #define LOWEST_PC 0x20 | |
482 | ||
e1d6e81f SB |
483 | /* Function to determine whether MEMADDR is in a Thumb function. */ |
484 | extern int arm_pc_is_thumb (bfd_vma memaddr); | |
485 | ||
486 | /* Function to determine whether MEMADDR is in a call dummy called from | |
487 | a Thumb function. */ | |
488 | extern int arm_pc_is_thumb_dummy (bfd_vma memaddr); | |
489 | ||
ed9a39eb | 490 | #endif /* TM_ARM_H */ |