[deliverable/binutils-gdb.git] / gdb / config / mips / tm-mips.h

/* Definitions to make GDB run on a mips box under 4.3bsd.
   Copyright 1986, 1987, 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
   Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   and by Alessandro Forin (af@cs.cmu.edu) at CMU..

This file is part of GDB.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */

#include <bfd.h>
#include "coff/sym.h"		/* Needed for PDR below.  */
#include "coff/symconst.h"

#if !defined (TARGET_BYTE_ORDER)
#define TARGET_BYTE_ORDER LITTLE_ENDIAN
#endif

/* Floating point is IEEE compliant */
#define IEEE_FLOAT

/* Some MIPS boards are provided both with and without a floating
   point coprocessor; we provide a user settable variable to tell gdb
   whether there is one or not.  */
extern int mips_fpu;

/* Offset from address of function to start of its code.
   Zero on most machines.  */

#define FUNCTION_START_OFFSET 0

/* Advance PC across any function entry prologue instructions
   to reach some "real" code.  */

#define SKIP_PROLOGUE(pc)	pc = mips_skip_prologue (pc, 0)
extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));

/* Return non-zero if PC points to an instruction which will cause a step
   to execute both the instruction at PC and an instruction at PC+4.  */
#define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))

/* Immediately after a function call, return the saved pc.
   Can't always go through the frames for this because on some machines
   the new frame is not set up until the new function executes
   some instructions.  */

#define SAVED_PC_AFTER_CALL(frame)	read_register(RA_REGNUM)

/* Are we currently handling a signal */

extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
#define IN_SIGTRAMP(pc, name)	in_sigtramp(pc, name)

/* Stack grows downward.  */

#define INNER_THAN <

#define BIG_ENDIAN 4321
#if TARGET_BYTE_ORDER == BIG_ENDIAN
#define BREAKPOINT {0, 0x5, 0, 0xd}
#else
#define BREAKPOINT {0xd, 0, 0x5, 0}
#endif

/* Amount PC must be decremented by after a breakpoint.
   This is often the number of bytes in BREAKPOINT
   but not always.  */

#define DECR_PC_AFTER_BREAK 0

/* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */

#define ABOUT_TO_RETURN(pc) (read_memory_integer (pc, 4) == 0x3e00008)

/* This is taken care of in print_floating [IEEE_FLOAT].  */

#define INVALID_FLOAT(p,l) 0

/* Say how long (ordinary) registers are.  This is a piece of bogosity
   used in push_word and a few other places; REGISTER_RAW_SIZE is the
   real way to know how big a register is.  */

#define REGISTER_SIZE 4

/* The size of a register.  This is predefined in tm-mips64.h.  We
   can't use REGISTER_SIZE because that is used for various other
   things.  */

#ifndef MIPS_REGSIZE
#define MIPS_REGSIZE 4
#endif

/* Number of machine registers */

#define NUM_REGS 80

/* Initializer for an array of names of registers.
   There should be NUM_REGS strings in this initializer.  */

#define REGISTER_NAMES 	\
    {	"zero",	"at",	"v0",	"v1",	"a0",	"a1",	"a2",	"a3", \
	"t0",	"t1",	"t2",	"t3",	"t4",	"t5",	"t6",	"t7", \
	"s0",	"s1",	"s2",	"s3",	"s4",	"s5",	"s6",	"s7", \
	"t8",	"t9",	"k0",	"k1",	"gp",	"sp",	"s8",	"ra", \
	"sr",	"lo",	"hi",	"bad",	"cause","pc",    \
	"f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
	"f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
	"f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
	"f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
	"fsr",  "fir",  "fp",   "inx",  "rand", "tlblo","ctxt", "tlbhi",\
	"epc",  "prid"\
    }

/* Register numbers of various important registers.
   Note that some of these values are "real" register numbers,
   and correspond to the general registers of the machine,
   and some are "phony" register numbers which are too large
   to be actual register numbers as far as the user is concerned
   but do serve to get the desired values when passed to read_register.  */

#define ZERO_REGNUM 0		/* read-only register, always 0 */
#define V0_REGNUM 2		/* Function integer return value */
#define A0_REGNUM 4		/* Loc of first arg during a subr call */
#define SP_REGNUM 29		/* Contains address of top of stack */
#define RA_REGNUM 31		/* Contains return address value */
#define PS_REGNUM 32		/* Contains processor status */
#define HI_REGNUM 34            /* Multiple/divide temp */
#define LO_REGNUM 33            /* ... */
#define BADVADDR_REGNUM 35	/* bad vaddr for addressing exception */
#define CAUSE_REGNUM 36		/* describes last exception */
#define PC_REGNUM 37		/* Contains program counter */
#define FP0_REGNUM 38           /* Floating point register 0 (single float) */
#define FCRCS_REGNUM 70         /* FP control/status */
#define FCRIR_REGNUM 71         /* FP implementation/revision */
#define FP_REGNUM 72		/* Pseudo register that contains true address of executing stack frame */
#define	FIRST_EMBED_REGNUM 73	/* First supervisor register for embedded use */
#define	LAST_EMBED_REGNUM 79	/* Last one */

/* Define DO_REGISTERS_INFO() to do machine-specific formatting
   of register dumps. */

#define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)

/* Total amount of space needed to store our copies of the machine's
   register state, the array `registers'.  */
#define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)

/* Index within `registers' of the first byte of the space for
   register N.  */

#define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)

/* Number of bytes of storage in the actual machine representation
   for register N.  On mips, all regs are the same size.  */

#define REGISTER_RAW_SIZE(N) MIPS_REGSIZE

/* Number of bytes of storage in the program's representation
   for register N.  On mips, all regs are the same size.  */

#define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE

/* Largest value REGISTER_RAW_SIZE can have.  */

#define MAX_REGISTER_RAW_SIZE 8

/* Largest value REGISTER_VIRTUAL_SIZE can have.  */

#define MAX_REGISTER_VIRTUAL_SIZE 8

/* Return the GDB type object for the "standard" data type
   of data in register N.  */

#ifndef REGISTER_VIRTUAL_TYPE
#define REGISTER_VIRTUAL_TYPE(N) \
	(((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32)  \
	 ? builtin_type_float : builtin_type_int)
#endif

#if HOST_BYTE_ORDER == BIG_ENDIAN
/* All mips targets store doubles in a register pair with the least
   significant register in the lower numbered register.
   If the host is big endian, double register values need conversion between
   memory and register formats.  */

#define REGISTER_CONVERT_TO_TYPE(n, type, buffer)			\
  do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && 		\
	  TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
        char __temp[4];							\
	memcpy (__temp, ((char *)(buffer))+4, 4);			\
	memcpy (((char *)(buffer))+4, (buffer), 4); 			\
	memcpy (((char *)(buffer)), __temp, 4); }} while (0)

#define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)			\
  do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 &&			\
	  TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
        char __temp[4];							\
	memcpy (__temp, ((char *)(buffer))+4, 4);			\
	memcpy (((char *)(buffer))+4, (buffer), 4); 			\
	memcpy (((char *)(buffer)), __temp, 4); }} while (0)
#endif

/* Store the address of the place in which to copy the structure the
   subroutine will return.  Handled by mips_push_arguments.  */

#define STORE_STRUCT_RETURN(addr, sp)	/**/

/* Extract from an array REGBUF containing the (raw) register state
   a function return value of type TYPE, and copy that, in virtual format,
   into VALBUF.  XXX floats */

#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
  mips_extract_return_value(TYPE, REGBUF, VALBUF)

/* Write into appropriate registers a function return value
   of type TYPE, given in virtual format.  */

#define STORE_RETURN_VALUE(TYPE,VALBUF) \
  mips_store_return_value(TYPE, VALBUF)

/* Extract from an array REGBUF containing the (raw) register state
   the address in which a function should return its structure value,
   as a CORE_ADDR (or an expression that can be used as one).  */
/* The address is passed in a0 upon entry to the function, but when
   the function exits, the compiler has copied the value to v0.  This
   convention is specified by the System V ABI, so I think we can rely
   on it.  */

#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
  (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
		    REGISTER_RAW_SIZE (V0_REGNUM)))

/* Structures are returned by ref in extra arg0 */
#define USE_STRUCT_CONVENTION(gcc_p, type)	1

\f
/* Describe the pointer in each stack frame to the previous stack frame
   (its caller).  */

/* FRAME_CHAIN takes a frame's nominal address
   and produces the frame's chain-pointer. */

#define FRAME_CHAIN(thisframe) (FRAME_ADDR)mips_frame_chain(thisframe)

/* Define other aspects of the stack frame.  */


/* A macro that tells us whether the function invocation represented
   by FI does not have a frame on the stack associated with it.  If it
   does not, FRAMELESS is set to 1, else 0.  */
/* We handle this differently for mips, and maybe we should not */

#define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS)  {(FRAMELESS) = 0;}

/* Saved Pc.  */

#define FRAME_SAVED_PC(FRAME)	(mips_frame_saved_pc(FRAME))

#define FRAME_ARGS_ADDRESS(fi)	(fi)->frame

#define FRAME_LOCALS_ADDRESS(fi) (fi)->frame

/* Return number of args passed to a frame.
   Can return -1, meaning no way to tell.  */

#define FRAME_NUM_ARGS(num, fi)	(num = mips_frame_num_args(fi))

/* Return number of bytes at start of arglist that are not really args.  */

#define FRAME_ARGS_SKIP 0

/* Put here the code to store, into a struct frame_saved_regs,
   the addresses of the saved registers of frame described by FRAME_INFO.
   This includes special registers such as pc and fp saved in special
   ways in the stack frame.  sp is even more special:
   the address we return for it IS the sp for the next frame.  */

#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
  do { \
    if ((frame_info)->saved_regs == NULL) \
      mips_find_saved_regs (frame_info); \
    (frame_saved_regs) = *(frame_info)->saved_regs; \
    (frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \
  } while (0)

\f
/* Things needed for making the inferior call functions.  */

/* Stack has strict alignment. However, use PUSH_ARGUMENTS
   to take care of it. */
/*#define STACK_ALIGN(addr)	(((addr)+3)&~3)*/

#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
    sp = mips_push_arguments(nargs, args, sp, struct_return, struct_addr)

/* Push an empty stack frame, to record the current PC, etc.  */

#define PUSH_DUMMY_FRAME 	mips_push_dummy_frame()

/* Discard from the stack the innermost frame, restoring all registers.  */

#define POP_FRAME		mips_pop_frame()

#define MK_OP(op,rs,rt,offset) (((op)<<26)|((rs)<<21)|((rt)<<16)|(offset))
#ifndef OP_LDFPR
#define OP_LDFPR 061	/* lwc1 */
#endif
#ifndef OP_LDGPR
#define OP_LDGPR 043	/* lw */
#endif
#define CALL_DUMMY_SIZE (16*4)
#define Dest_Reg 2
#define CALL_DUMMY {\
 MK_OP(0,RA_REGNUM,0,8),	/* jr $ra # Fake ABOUT_TO_RETURN ...*/\
 0,				/* nop 	  #  ... to stop raw backtrace*/\
 0x27bd0000,			/* addu	sp,?0 # Pseudo prologue */\
/* Start here; reload FP regs, then GP regs: */\
 MK_OP(OP_LDFPR,SP_REGNUM,12,0             ), /* l[wd]c1 $f12,0(sp) */\
 MK_OP(OP_LDFPR,SP_REGNUM,13,  MIPS_REGSIZE), /* l[wd]c1 $f13,{4,8}(sp) */\
 MK_OP(OP_LDFPR,SP_REGNUM,14,2*MIPS_REGSIZE), /* l[wd]c1 $f14,{8,16}(sp) */\
 MK_OP(OP_LDFPR,SP_REGNUM,15,3*MIPS_REGSIZE), /* l[wd]c1 $f15,{12,24}(sp) */\
 MK_OP(OP_LDGPR,SP_REGNUM, 4,0             ), /* l[wd] $r4,0(sp) */\
 MK_OP(OP_LDGPR,SP_REGNUM, 5,  MIPS_REGSIZE), /* l[wd] $r5,{4,8}(sp) */\
 MK_OP(OP_LDGPR,SP_REGNUM, 6,2*MIPS_REGSIZE), /* l[wd] $r6,{8,16}(sp) */\
 MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
 (017<<26)| (Dest_Reg << 16),	/* lui $r31,<target upper 16 bits>*/\
 MK_OP(13,Dest_Reg,Dest_Reg,0),	/* ori $r31,$r31,<lower 16 bits>*/ \
 (Dest_Reg<<21) | (31<<11) | 9,	/* jalr $r31 */\
 MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
 0x5000d,			/* bpt */\
}

#define CALL_DUMMY_START_OFFSET 12

#define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + (12 * 4))

/* Insert the specified number of args and function address
   into a call sequence of the above form stored at DUMMYNAME.  */

#if TARGET_BYTE_ORDER == BIG_ENDIAN && ! defined (GDB_TARGET_IS_MIPS64)
/* For big endian mips machines we need to switch the order of the
   words with a floating-point value (it was already coerced to a double
   by mips_push_arguments).  */
#define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
  do {									\
    ((int*)(dummyname))[11] |= ((unsigned long)(fun)) >> 16;		\
    ((int*)(dummyname))[12] |= (unsigned short)(fun);			\
    if (! mips_fpu) {							\
      ((int *) (dummyname))[3] = 0; ((int *) (dummyname))[4] = 0;	\
      ((int *) (dummyname))[5] = 0; ((int *) (dummyname))[6] = 0;	\
    } else {								\
      if (nargs > 0 &&							\
	  TYPE_CODE(VALUE_TYPE(args[0])) == TYPE_CODE_FLT) {		\
	if (TYPE_LENGTH(VALUE_TYPE(args[0])) > 8)			\
	  error ("Can't pass floating point value of more than 8 bytes to a function"); \
	((int *) (dummyname))[3] = MK_OP(OP_LDFPR,SP_REGNUM,12,4);	\
	((int *) (dummyname))[4] = MK_OP(OP_LDFPR,SP_REGNUM,13,0);	\
      }									\
      if (nargs > 1 &&							\
	  TYPE_CODE(VALUE_TYPE(args[1])) == TYPE_CODE_FLT) {		\
	if (TYPE_LENGTH(VALUE_TYPE(args[1])) > 8)			\
	  error ("Can't pass floating point value of more than 8 bytes to a function"); \
	((int *) (dummyname))[5] = MK_OP(OP_LDFPR,SP_REGNUM,14,12);	\
	((int *) (dummyname))[6] = MK_OP(OP_LDFPR,SP_REGNUM,15,8);	\
      }									\
    }									\
  } while (0)
#else
#define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs,	args, rettype, gcc_p)\
  do \
    { \
      ((int*)(dummyname))[11] |= ((unsigned long)(fun)) >> 16; \
      ((int*)(dummyname))[12] |= (unsigned short)(fun); \
      if (! mips_fpu) \
	{ \
	  ((int *) (dummyname))[3] = 0; \
	  ((int *) (dummyname))[4] = 0; \
	  ((int *) (dummyname))[5] = 0; \
	  ((int *) (dummyname))[6] = 0; \
	} \
    } \
  while (0)
#endif

/* There's a mess in stack frame creation.  See comments in blockframe.c
   near reference to INIT_FRAME_PC_FIRST.  */

#define	INIT_FRAME_PC(fromleaf, prev) /* nada */

#define INIT_FRAME_PC_FIRST(fromleaf, prev) \
  (prev)->pc = ((fromleaf) ? SAVED_PC_AFTER_CALL ((prev)->next) : \
	      (prev)->next ? FRAME_SAVED_PC ((prev)->next) : read_pc ());

/* Special symbol found in blocks associated with routines.  We can hang
   mips_extra_func_info_t's off of this.  */

#define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"

/* Specific information about a procedure.
   This overlays the MIPS's PDR records, 
   mipsread.c (ab)uses this to save memory */

typedef struct mips_extra_func_info {
	long	numargs;	/* number of args to procedure (was iopt) */
	PDR	pdr;		/* Procedure descriptor record */
} *mips_extra_func_info_t;

#define EXTRA_FRAME_INFO \
  mips_extra_func_info_t proc_desc; \
  int num_args;\
  struct frame_saved_regs *saved_regs;

#define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)

#define	PRINT_EXTRA_FRAME_INFO(fi) \
  { \
    if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
      printf_filtered (" frame pointer is at %s+%d\n", \
                       reg_names[fi->proc_desc->pdr.framereg], \
                                 fi->proc_desc->pdr.frameoffset); \
  }

/* It takes two values to specify a frame on the MIPS.  Sigh.

   In fact, at the moment, the *PC* is the primary value that sets up
   a frame.  The PC is looked up to see what function it's in; symbol
   information from that function tells us which register is the frame
   pointer base, and what offset from there is the "virtual frame pointer".
   (This is usually an offset from SP.)  FIXME -- this should be cleaned
   up so that the primary value is the SP, and the PC is used to disambiguate
   multiple functions with the same SP that are at different stack levels. */

#define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
/* FIXME:  Depends on equivalence between FRAME and "struct frame_info *",
   and equivalence between CORE_ADDR and FRAME_ADDR. */
extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));

/* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */

#define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)

/* Convert a ecoff register number to a gdb REGNUM */

#define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
Commit	Line	Data
5076de82 FF	1	/* Definitions to make GDB run on a mips box under 4.3bsd.
	2	Copyright 1986, 1987, 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
	3	Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
	4	and by Alessandro Forin (af@cs.cmu.edu) at CMU..
	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
	21
05e9e188	22	#include <bfd.h>
5076de82 FF	23	#include "coff/sym.h" /* Needed for PDR below. */
	24	#include "coff/symconst.h"
	25
	26	#if !defined (TARGET_BYTE_ORDER)
	27	#define TARGET_BYTE_ORDER LITTLE_ENDIAN
	28	#endif
	29
	30	/* Floating point is IEEE compliant */
	31	#define IEEE_FLOAT
	32
	33	/* Some MIPS boards are provided both with and without a floating
	34	point coprocessor; we provide a user settable variable to tell gdb
	35	whether there is one or not. */
	36	extern int mips_fpu;
	37
	38	/* Offset from address of function to start of its code.
	39	Zero on most machines. */
	40
	41	#define FUNCTION_START_OFFSET 0
	42
	43	/* Advance PC across any function entry prologue instructions
	44	to reach some "real" code. */
	45
ee5fb959 JK	46	#define SKIP_PROLOGUE(pc) pc = mips_skip_prologue (pc, 0)
ee5fb959 JK	47	extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
5076de82	48
b5aff268 JK	49	/* Return non-zero if PC points to an instruction which will cause a step
	50	to execute both the instruction at PC and an instruction at PC+4. */
	51	#define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
	52
5076de82 FF	53	/* Immediately after a function call, return the saved pc.
	54	Can't always go through the frames for this because on some machines
	55	the new frame is not set up until the new function executes
	56	some instructions. */
	57
	58	#define SAVED_PC_AFTER_CALL(frame) read_register(RA_REGNUM)
	59
	60	/* Are we currently handling a signal */
	61
e03c0cc6	62	extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
5076de82 FF	63	#define IN_SIGTRAMP(pc, name) in_sigtramp(pc, name)
5076de82 FF	64
5076de82 FF	65	/* Stack grows downward. */
	66
	67	#define INNER_THAN <
	68
	69	#define BIG_ENDIAN 4321
	70	#if TARGET_BYTE_ORDER == BIG_ENDIAN
	71	#define BREAKPOINT {0, 0x5, 0, 0xd}
	72	#else
	73	#define BREAKPOINT {0xd, 0, 0x5, 0}
	74	#endif
	75
	76	/* Amount PC must be decremented by after a breakpoint.
	77	This is often the number of bytes in BREAKPOINT
	78	but not always. */
	79
	80	#define DECR_PC_AFTER_BREAK 0
	81
	82	/* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */
	83
	84	#define ABOUT_TO_RETURN(pc) (read_memory_integer (pc, 4) == 0x3e00008)
	85
7c86bda2	86	/* This is taken care of in print_floating [IEEE_FLOAT]. */
5076de82	87
7c86bda2	88	#define INVALID_FLOAT(p,l) 0
5076de82	89
f4f0d174 JK	90	/* Say how long (ordinary) registers are. This is a piece of bogosity
	91	used in push_word and a few other places; REGISTER_RAW_SIZE is the
	92	real way to know how big a register is. */
5076de82	93
f4f0d174	94	#define REGISTER_SIZE 4
5076de82	95
4fbce2fd KH	96	/* The size of a register. This is predefined in tm-mips64.h. We
	97	can't use REGISTER_SIZE because that is used for various other
	98	things. */
	99
	100	#ifndef MIPS_REGSIZE
	101	#define MIPS_REGSIZE 4
	102	#endif
	103
5076de82 FF	104	/* Number of machine registers */
	105
	106	#define NUM_REGS 80
	107
	108	/* Initializer for an array of names of registers.
	109	There should be NUM_REGS strings in this initializer. */
	110
	111	#define REGISTER_NAMES \
	112	{ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
	113	"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
	114	"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
	115	"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
	116	"sr", "lo", "hi", "bad", "cause","pc", \
	117	"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
	118	"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
	119	"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
	120	"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
	121	"fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\
	122	"epc", "prid"\
	123	}
	124
	125	/* Register numbers of various important registers.
	126	Note that some of these values are "real" register numbers,
	127	and correspond to the general registers of the machine,
	128	and some are "phony" register numbers which are too large
	129	to be actual register numbers as far as the user is concerned
	130	but do serve to get the desired values when passed to read_register. */
	131
	132	#define ZERO_REGNUM 0 /* read-only register, always 0 */
138dd57c	133	#define V0_REGNUM 2 /* Function integer return value */
5076de82 FF	134	#define A0_REGNUM 4 /* Loc of first arg during a subr call */
	135	#define SP_REGNUM 29 /* Contains address of top of stack */
	136	#define RA_REGNUM 31 /* Contains return address value */
	137	#define PS_REGNUM 32 /* Contains processor status */
	138	#define HI_REGNUM 34 /* Multiple/divide temp */
	139	#define LO_REGNUM 33 /* ... */
	140	#define BADVADDR_REGNUM 35 /* bad vaddr for addressing exception */
	141	#define CAUSE_REGNUM 36 /* describes last exception */
	142	#define PC_REGNUM 37 /* Contains program counter */
	143	#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
	144	#define FCRCS_REGNUM 70 /* FP control/status */
	145	#define FCRIR_REGNUM 71 /* FP implementation/revision */
	146	#define FP_REGNUM 72 /* Pseudo register that contains true address of executing stack frame */
	147	#define FIRST_EMBED_REGNUM 73 /* First supervisor register for embedded use */
	148	#define LAST_EMBED_REGNUM 79 /* Last one */
	149
	150	/* Define DO_REGISTERS_INFO() to do machine-specific formatting
	151	of register dumps. */
	152
	153	#define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
	154
	155	/* Total amount of space needed to store our copies of the machine's
	156	register state, the array `registers'. */
4fbce2fd	157	#define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
5076de82 FF	158
	159	/* Index within `registers' of the first byte of the space for
	160	register N. */
	161
4fbce2fd	162	#define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
5076de82 FF	163
5076de82 FF	164	/* Number of bytes of storage in the actual machine representation
4fbce2fd	165	for register N. On mips, all regs are the same size. */
5076de82	166
4fbce2fd	167	#define REGISTER_RAW_SIZE(N) MIPS_REGSIZE
5076de82 FF	168
5076de82 FF	169	/* Number of bytes of storage in the program's representation
4fbce2fd	170	for register N. On mips, all regs are the same size. */
5076de82	171
4fbce2fd	172	#define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE
5076de82 FF	173
	174	/* Largest value REGISTER_RAW_SIZE can have. */
	175
ac8cf67d	176	#define MAX_REGISTER_RAW_SIZE 8
5076de82 FF	177
	178	/* Largest value REGISTER_VIRTUAL_SIZE can have. */
	179
ac8cf67d	180	#define MAX_REGISTER_VIRTUAL_SIZE 8
5076de82	181
5076de82 FF	182	/* Return the GDB type object for the "standard" data type
	183	of data in register N. */
	184
031b390a	185	#ifndef REGISTER_VIRTUAL_TYPE
5076de82 FF	186	#define REGISTER_VIRTUAL_TYPE(N) \
5076de82 FF	187	(((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) \
031b390a KH	188	? builtin_type_float : builtin_type_int)
031b390a KH	189	#endif
5076de82	190
ac8cf67d PS	191	#if HOST_BYTE_ORDER == BIG_ENDIAN
	192	/* All mips targets store doubles in a register pair with the least
	193	significant register in the lower numbered register.
	194	If the host is big endian, double register values need conversion between
	195	memory and register formats. */
	196
	197	#define REGISTER_CONVERT_TO_TYPE(n, type, buffer) \
	198	do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \
	199	TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
	200	char __temp[4]; \
	201	memcpy (__temp, ((char *)(buffer))+4, 4); \
	202	memcpy (((char *)(buffer))+4, (buffer), 4); \
	203	memcpy (((char *)(buffer)), __temp, 4); }} while (0)
	204
	205	#define REGISTER_CONVERT_FROM_TYPE(n, type, buffer) \
	206	do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \
	207	TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
	208	char __temp[4]; \
	209	memcpy (__temp, ((char *)(buffer))+4, 4); \
	210	memcpy (((char *)(buffer))+4, (buffer), 4); \
	211	memcpy (((char *)(buffer)), __temp, 4); }} while (0)
	212	#endif
	213
5076de82	214	/* Store the address of the place in which to copy the structure the
0c28fe8d	215	subroutine will return. Handled by mips_push_arguments. */
5076de82	216
0c28fe8d	217	#define STORE_STRUCT_RETURN(addr, sp) /**/
5076de82 FF	218
	219	/* Extract from an array REGBUF containing the (raw) register state
	220	a function return value of type TYPE, and copy that, in virtual format,
	221	into VALBUF. XXX floats */
	222
	223	#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
ac8cf67d	224	mips_extract_return_value(TYPE, REGBUF, VALBUF)
5076de82 FF	225
	226	/* Write into appropriate registers a function return value
	227	of type TYPE, given in virtual format. */
	228
	229	#define STORE_RETURN_VALUE(TYPE,VALBUF) \
ac8cf67d	230	mips_store_return_value(TYPE, VALBUF)
5076de82 FF	231
	232	/* Extract from an array REGBUF containing the (raw) register state
	233	the address in which a function should return its structure value,
	234	as a CORE_ADDR (or an expression that can be used as one). */
138dd57c JK	235	/* The address is passed in a0 upon entry to the function, but when
138dd57c JK	236	the function exits, the compiler has copied the value to v0. This
e8239c2f JK	237	convention is specified by the System V ABI, so I think we can rely
e8239c2f JK	238	on it. */
5076de82	239
138dd57c JK	240	#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
	241	(extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
	242	REGISTER_RAW_SIZE (V0_REGNUM)))
5076de82 FF	243
	244	/* Structures are returned by ref in extra arg0 */
	245	#define USE_STRUCT_CONVENTION(gcc_p, type) 1
	246
	247	\f
	248	/* Describe the pointer in each stack frame to the previous stack frame
	249	(its caller). */
	250
	251	/* FRAME_CHAIN takes a frame's nominal address
	252	and produces the frame's chain-pointer. */
	253
	254	#define FRAME_CHAIN(thisframe) (FRAME_ADDR)mips_frame_chain(thisframe)
	255
	256	/* Define other aspects of the stack frame. */
	257
	258
	259	/* A macro that tells us whether the function invocation represented
	260	by FI does not have a frame on the stack associated with it. If it
	261	does not, FRAMELESS is set to 1, else 0. */
	262	/* We handle this differently for mips, and maybe we should not */
	263
	264	#define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS) {(FRAMELESS) = 0;}
	265
	266	/* Saved Pc. */
	267
	268	#define FRAME_SAVED_PC(FRAME) (mips_frame_saved_pc(FRAME))
	269
	270	#define FRAME_ARGS_ADDRESS(fi) (fi)->frame
	271
	272	#define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
	273
	274	/* Return number of args passed to a frame.
	275	Can return -1, meaning no way to tell. */
	276
	277	#define FRAME_NUM_ARGS(num, fi) (num = mips_frame_num_args(fi))
	278
	279	/* Return number of bytes at start of arglist that are not really args. */
	280
	281	#define FRAME_ARGS_SKIP 0
	282
	283	/* Put here the code to store, into a struct frame_saved_regs,
	284	the addresses of the saved registers of frame described by FRAME_INFO.
	285	This includes special registers such as pc and fp saved in special
	286	ways in the stack frame. sp is even more special:
	287	the address we return for it IS the sp for the next frame. */
	288
14d79562 JK	289	#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
	290	do { \
	291	if ((frame_info)->saved_regs == NULL) \
	292	mips_find_saved_regs (frame_info); \
	293	(frame_saved_regs) = *(frame_info)->saved_regs; \
	294	(frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \
	295	} while (0)
5076de82 FF	296
	297	\f
	298	/* Things needed for making the inferior call functions. */
	299
	300	/* Stack has strict alignment. However, use PUSH_ARGUMENTS
	301	to take care of it. */
	302	/#define STACK_ALIGN(addr) (((addr)+3)&~3)/
	303
	304	#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
	305	sp = mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
	306
	307	/* Push an empty stack frame, to record the current PC, etc. */
	308
	309	#define PUSH_DUMMY_FRAME mips_push_dummy_frame()
	310
	311	/* Discard from the stack the innermost frame, restoring all registers. */
	312
	313	#define POP_FRAME mips_pop_frame()
	314
	315	#define MK_OP(op,rs,rt,offset) (((op)<<26)\|((rs)<<21)\|((rt)<<16)\|(offset))
4fbce2fd KH	316	#ifndef OP_LDFPR
	317	#define OP_LDFPR 061 /* lwc1 */
	318	#endif
	319	#ifndef OP_LDGPR
	320	#define OP_LDGPR 043 /* lw */
	321	#endif
5076de82 FF	322	#define CALL_DUMMY_SIZE (16*4)
	323	#define Dest_Reg 2
	324	#define CALL_DUMMY {\
	325	MK_OP(0,RA_REGNUM,0,8), /* jr $ra # Fake ABOUT_TO_RETURN ...*/\
	326	0, /* nop # ... to stop raw backtrace*/\
	327	0x27bd0000, /* addu sp,?0 # Pseudo prologue */\
4fbce2fd KH	328	/* Start here; reload FP regs, then GP regs: */\
	329	MK_OP(OP_LDFPR,SP_REGNUM,12,0 ), /* l[wd]c1 $f12,0(sp) */\
	330	MK_OP(OP_LDFPR,SP_REGNUM,13, MIPS_REGSIZE), /* l[wd]c1 $f13,{4,8}(sp) */\
	331	MK_OP(OP_LDFPR,SP_REGNUM,14,2MIPS_REGSIZE), / l[wd]c1 $f14,{8,16}(sp) */\
	332	MK_OP(OP_LDFPR,SP_REGNUM,15,3MIPS_REGSIZE), / l[wd]c1 $f15,{12,24}(sp) */\
	333	MK_OP(OP_LDGPR,SP_REGNUM, 4,0 ), /* l[wd] $r4,0(sp) */\
	334	MK_OP(OP_LDGPR,SP_REGNUM, 5, MIPS_REGSIZE), /* l[wd] $r5,{4,8}(sp) */\
	335	MK_OP(OP_LDGPR,SP_REGNUM, 6,2MIPS_REGSIZE), / l[wd] $r6,{8,16}(sp) */\
	336	MK_OP(OP_LDGPR,SP_REGNUM, 7,3MIPS_REGSIZE), / l[wd] $r7,{12,24}(sp) */\
5076de82 FF	337	(017<<26)\| (Dest_Reg << 16), /* lui $r31,<target upper 16 bits>*/\
	338	MK_OP(13,Dest_Reg,Dest_Reg,0), /* ori $r31,$r31,<lower 16 bits>*/ \
	339	(Dest_Reg<<21) \| (31<<11) \| 9, /* jalr $r31 */\
4fbce2fd	340	MK_OP(OP_LDGPR,SP_REGNUM, 7,3MIPS_REGSIZE), / l[wd] $r7,{12,24}(sp) */\
5076de82 FF	341	0x5000d, /* bpt */\
	342	}
	343
	344	#define CALL_DUMMY_START_OFFSET 12
	345
f0d2557c PS	346	#define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + (12 * 4))
f0d2557c PS	347
5076de82 FF	348	/* Insert the specified number of args and function address
	349	into a call sequence of the above form stored at DUMMYNAME. */
	350
4fbce2fd	351	#if TARGET_BYTE_ORDER == BIG_ENDIAN && ! defined (GDB_TARGET_IS_MIPS64)
08447510 PS	352	/* For big endian mips machines we need to switch the order of the
	353	words with a floating-point value (it was already coerced to a double
	354	by mips_push_arguments). */
ac8cf67d PS	355	#define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
	356	do { \
	357	((int*)(dummyname))[11] \|= ((unsigned long)(fun)) >> 16; \
	358	((int*)(dummyname))[12] \|= (unsigned short)(fun); \
	359	if (! mips_fpu) { \
	360	((int ) (dummyname))[3] = 0; ((int ) (dummyname))[4] = 0; \
	361	((int ) (dummyname))[5] = 0; ((int ) (dummyname))[6] = 0; \
	362	} else { \
	363	if (nargs > 0 && \
08447510 PS	364	TYPE_CODE(VALUE_TYPE(args[0])) == TYPE_CODE_FLT) { \
	365	if (TYPE_LENGTH(VALUE_TYPE(args[0])) > 8) \
	366	error ("Can't pass floating point value of more than 8 bytes to a function"); \
4fbce2fd KH	367	((int *) (dummyname))[3] = MK_OP(OP_LDFPR,SP_REGNUM,12,4); \
4fbce2fd KH	368	((int *) (dummyname))[4] = MK_OP(OP_LDFPR,SP_REGNUM,13,0); \
ac8cf67d PS	369	} \
ac8cf67d PS	370	if (nargs > 1 && \
08447510 PS	371	TYPE_CODE(VALUE_TYPE(args[1])) == TYPE_CODE_FLT) { \
	372	if (TYPE_LENGTH(VALUE_TYPE(args[1])) > 8) \
	373	error ("Can't pass floating point value of more than 8 bytes to a function"); \
4fbce2fd KH	374	((int *) (dummyname))[5] = MK_OP(OP_LDFPR,SP_REGNUM,14,12); \
4fbce2fd KH	375	((int *) (dummyname))[6] = MK_OP(OP_LDFPR,SP_REGNUM,15,8); \
ac8cf67d PS	376	} \
	377	} \
	378	} while (0)
	379	#else
5076de82 FF	380	#define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p)\
	381	do \
	382	{ \
	383	((int*)(dummyname))[11] \|= ((unsigned long)(fun)) >> 16; \
	384	((int*)(dummyname))[12] \|= (unsigned short)(fun); \
	385	if (! mips_fpu) \
	386	{ \
	387	((int *) (dummyname))[3] = 0; \
	388	((int *) (dummyname))[4] = 0; \
	389	((int *) (dummyname))[5] = 0; \
	390	((int *) (dummyname))[6] = 0; \
	391	} \
	392	} \
	393	while (0)
ac8cf67d	394	#endif
5076de82 FF	395
	396	/* There's a mess in stack frame creation. See comments in blockframe.c
	397	near reference to INIT_FRAME_PC_FIRST. */
	398
	399	#define INIT_FRAME_PC(fromleaf, prev) /* nada */
	400
	401	#define INIT_FRAME_PC_FIRST(fromleaf, prev) \
	402	(prev)->pc = ((fromleaf) ? SAVED_PC_AFTER_CALL ((prev)->next) : \
	403	(prev)->next ? FRAME_SAVED_PC ((prev)->next) : read_pc ());
	404
	405	/* Special symbol found in blocks associated with routines. We can hang
	406	mips_extra_func_info_t's off of this. */
	407
	408	#define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
	409
	410	/* Specific information about a procedure.
	411	This overlays the MIPS's PDR records,
	412	mipsread.c (ab)uses this to save memory */
	413
	414	typedef struct mips_extra_func_info {
	415	long numargs; /* number of args to procedure (was iopt) */
	416	PDR pdr; /* Procedure descriptor record */
	417	} *mips_extra_func_info_t;
	418
	419	#define EXTRA_FRAME_INFO \
	420	mips_extra_func_info_t proc_desc; \
	421	int num_args;\
	422	struct frame_saved_regs *saved_regs;
	423
	424	#define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)
	425
	426	#define PRINT_EXTRA_FRAME_INFO(fi) \
	427	{ \
	428	if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
	429	printf_filtered (" frame pointer is at %s+%d\n", \
	430	reg_names[fi->proc_desc->pdr.framereg], \
	431	fi->proc_desc->pdr.frameoffset); \
	432	}
	433
	434	/* It takes two values to specify a frame on the MIPS. Sigh.
	435
	436	In fact, at the moment, the PC is the primary value that sets up
	437	a frame. The PC is looked up to see what function it's in; symbol
	438	information from that function tells us which register is the frame
	439	pointer base, and what offset from there is the "virtual frame pointer".
	440	(This is usually an offset from SP.) FIXME -- this should be cleaned
	441	up so that the primary value is the SP, and the PC is used to disambiguate
	442	multiple functions with the same SP that are at different stack levels. */
	443
	444	#define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
	445	/* FIXME: Depends on equivalence between FRAME and "struct frame_info *",
	446	and equivalence between CORE_ADDR and FRAME_ADDR. */
	447	extern struct frame_info setup_arbitrary_frame PARAMS ((int, CORE_ADDR ));
	448
01422144 PS	449	/* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
	450
	451	#define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
8b15c480 PS	452
	453	/* Convert a ecoff register number to a gdb REGNUM */
	454
	455	#define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)