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c906108c SS |
1 | /* Parameters for execution on a Matsushita mn10200 processor. |
2 | Copyright 1997 Free Software Foundation, Inc. | |
3 | ||
4 | Contributed by Geoffrey Noer <noer@cygnus.com> | |
5 | ||
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | /* The mn10200 is little endian. */ | |
24 | #define TARGET_BYTE_ORDER LITTLE_ENDIAN | |
25 | ||
26 | /* ints are only 16bits on the mn10200. */ | |
27 | #undef TARGET_INT_BIT | |
28 | #define TARGET_INT_BIT 16 | |
29 | ||
30 | /* The mn10200 doesn't support long long types. */ | |
31 | #undef TARGET_LONG_LONG_BIT | |
32 | #define TARGET_LONG_LONG_BIT 32 | |
33 | ||
34 | /* The mn10200 doesn't support double or long double either. */ | |
35 | #undef TARGET_DOUBLE_BIT | |
36 | #undef TARGET_LONG_DOUBLE_BIT | |
37 | #define TARGET_DOUBLE_BIT 32 | |
38 | #define TARGET_LONG_DOUBLE_BIT 32 | |
39 | ||
40 | /* Not strictly correct, but the machine independent code is not | |
41 | ready to handle any of the basic sizes not being a power of two. */ | |
42 | #undef TARGET_PTR_BIT | |
43 | #define TARGET_PTR_BIT 32 | |
44 | ||
45 | /* The mn10200 really has 24 bit registers but the simulator reads/writes | |
46 | them as 32bit values, so we claim they're 32bits each. This may have | |
47 | to be tweaked if the Matsushita emulator/board really deals with them | |
48 | as 24bits each. */ | |
49 | #define REGISTER_SIZE 4 | |
50 | ||
51 | #define MAX_REGISTER_RAW_SIZE REGISTER_SIZE | |
52 | #define NUM_REGS 11 | |
53 | ||
54 | #define REGISTER_BYTES (NUM_REGS * REGISTER_SIZE) | |
55 | ||
56 | #define REGISTER_NAMES \ | |
57 | { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "sp", \ | |
58 | "pc", "mdr", "psw"} | |
59 | ||
60 | #define FP_REGNUM 6 | |
61 | #define SP_REGNUM 7 | |
62 | #define PC_REGNUM 8 | |
63 | #define MDR_REGNUM 9 | |
64 | #define PSW_REGNUM 10 | |
65 | ||
66 | /* Treat the registers as 32bit values. */ | |
67 | #define REGISTER_VIRTUAL_TYPE(REG) builtin_type_long | |
68 | ||
69 | #define REGISTER_BYTE(REG) ((REG) * REGISTER_SIZE) | |
70 | #define REGISTER_VIRTUAL_SIZE(REG) REGISTER_SIZE | |
71 | #define REGISTER_RAW_SIZE(REG) REGISTER_SIZE | |
72 | ||
73 | #define MAX_REGISTER_VIRTUAL_SIZE REGISTER_SIZE | |
74 | ||
75 | /* The breakpoint instruction must be the same size as te smallest | |
76 | instruction in the instruction set. | |
77 | ||
78 | The Matsushita mn10x00 processors have single byte instructions | |
79 | so we need a single byte breakpoint. Matsushita hasn't defined | |
80 | one, so we defined it ourselves. | |
81 | ||
82 | 0xff is the only available single byte insn left on the mn10200. */ | |
83 | #define BREAKPOINT {0xff} | |
84 | ||
85 | #define FUNCTION_START_OFFSET 0 | |
86 | ||
87 | #define DECR_PC_AFTER_BREAK 0 | |
88 | ||
89 | /* Stacks grow the normal way. */ | |
90 | #define INNER_THAN(lhs,rhs) ((lhs) < (rhs)) | |
91 | ||
92 | #define SAVED_PC_AFTER_CALL(frame) \ | |
93 | (read_memory_integer (read_register (SP_REGNUM), REGISTER_SIZE) & 0xffffff) | |
94 | ||
c906108c SS |
95 | struct frame_info; |
96 | struct frame_saved_regs; | |
97 | struct type; | |
98 | struct value; | |
c906108c SS |
99 | |
100 | #define EXTRA_FRAME_INFO struct frame_saved_regs fsr; int status; int stack_size; | |
101 | ||
102 | extern void mn10200_init_extra_frame_info PARAMS ((struct frame_info *)); | |
103 | #define INIT_EXTRA_FRAME_INFO(fromleaf, fi) mn10200_init_extra_frame_info (fi) | |
104 | #define INIT_FRAME_PC(x,y) | |
105 | ||
106 | extern void mn10200_frame_find_saved_regs PARAMS ((struct frame_info *, | |
c5aa993b | 107 | struct frame_saved_regs *)); |
c906108c SS |
108 | #define FRAME_FIND_SAVED_REGS(fi, regaddr) regaddr = fi->fsr |
109 | ||
110 | extern CORE_ADDR mn10200_frame_chain PARAMS ((struct frame_info *)); | |
111 | #define FRAME_CHAIN(fi) mn10200_frame_chain (fi) | |
112 | #define FRAME_CHAIN_VALID(FP, FI) generic_frame_chain_valid (FP, FI) | |
113 | ||
114 | extern CORE_ADDR mn10200_find_callers_reg PARAMS ((struct frame_info *, int)); | |
c5aa993b | 115 | extern CORE_ADDR mn10200_frame_saved_pc PARAMS ((struct frame_info *)); |
c906108c SS |
116 | #define FRAME_SAVED_PC(FI) (mn10200_frame_saved_pc (FI)) |
117 | ||
118 | /* Extract from an array REGBUF containing the (raw) register state | |
119 | a function return value of type TYPE, and copy that, in virtual format, | |
120 | into VALBUF. */ | |
121 | ||
122 | #define EXTRACT_RETURN_VALUE(TYPE, REGBUF, VALBUF) \ | |
123 | { \ | |
124 | if (TYPE_LENGTH (TYPE) > 8) \ | |
125 | abort (); \ | |
126 | else if (TYPE_LENGTH (TYPE) > 2 && TYPE_CODE (TYPE) != TYPE_CODE_PTR) \ | |
127 | { \ | |
128 | memcpy (VALBUF, REGBUF + REGISTER_BYTE (0), 2); \ | |
129 | memcpy (VALBUF + 2, REGBUF + REGISTER_BYTE (1), 2); \ | |
130 | } \ | |
131 | else if (TYPE_CODE (TYPE) == TYPE_CODE_PTR)\ | |
132 | { \ | |
133 | memcpy (VALBUF, REGBUF + REGISTER_BYTE (4), TYPE_LENGTH (TYPE)); \ | |
134 | } \ | |
135 | else \ | |
136 | { \ | |
137 | memcpy (VALBUF, REGBUF + REGISTER_BYTE (0), TYPE_LENGTH (TYPE)); \ | |
138 | } \ | |
139 | } | |
140 | ||
141 | #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \ | |
142 | extract_address (REGBUF + REGISTER_BYTE (4), \ | |
143 | REGISTER_RAW_SIZE (4)) | |
144 | ||
145 | #define STORE_RETURN_VALUE(TYPE, VALBUF) \ | |
146 | { \ | |
147 | if (TYPE_LENGTH (TYPE) > 8) \ | |
148 | abort (); \ | |
149 | else if (TYPE_LENGTH (TYPE) > 2 && TYPE_CODE (TYPE) != TYPE_CODE_PTR) \ | |
150 | { \ | |
151 | write_register_bytes (REGISTER_BYTE (0), VALBUF, 2); \ | |
152 | write_register_bytes (REGISTER_BYTE (1), VALBUF + 2, 2); \ | |
153 | } \ | |
154 | else if (TYPE_CODE (TYPE) == TYPE_CODE_PTR)\ | |
155 | { \ | |
156 | write_register_bytes (REGISTER_BYTE (4), VALBUF, TYPE_LENGTH (TYPE)); \ | |
157 | } \ | |
158 | else \ | |
159 | { \ | |
160 | write_register_bytes (REGISTER_BYTE (0), VALBUF, TYPE_LENGTH (TYPE)); \ | |
161 | } \ | |
162 | } | |
163 | ||
d4f3574e SS |
164 | |
165 | extern CORE_ADDR mn10200_store_struct_return (CORE_ADDR addr, CORE_ADDR sp); | |
c906108c SS |
166 | #define STORE_STRUCT_RETURN(STRUCT_ADDR, SP) \ |
167 | (SP) = mn10200_store_struct_return (STRUCT_ADDR, SP) | |
168 | ||
169 | extern CORE_ADDR mn10200_skip_prologue PARAMS ((CORE_ADDR)); | |
b83266a0 | 170 | #define SKIP_PROLOGUE(pc) (mn10200_skip_prologue (pc)) |
c906108c SS |
171 | |
172 | #define FRAME_ARGS_SKIP 0 | |
173 | ||
174 | #define FRAME_ARGS_ADDRESS(fi) ((fi)->frame) | |
175 | #define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame) | |
392a587b | 176 | #define FRAME_NUM_ARGS(fi) (-1) |
c906108c SS |
177 | |
178 | extern void mn10200_pop_frame PARAMS ((struct frame_info *)); | |
179 | #define POP_FRAME mn10200_pop_frame (get_current_frame ()) | |
180 | ||
7a292a7a | 181 | #define USE_GENERIC_DUMMY_FRAMES 1 |
c906108c SS |
182 | #define CALL_DUMMY {0} |
183 | #define CALL_DUMMY_START_OFFSET (0) | |
184 | #define CALL_DUMMY_BREAKPOINT_OFFSET (0) | |
185 | #define CALL_DUMMY_LOCATION AT_ENTRY_POINT | |
186 | #define FIX_CALL_DUMMY(DUMMY, START, FUNADDR, NARGS, ARGS, TYPE, GCCP) | |
187 | #define CALL_DUMMY_ADDRESS() entry_point_address () | |
188 | ||
189 | extern CORE_ADDR mn10200_push_return_address PARAMS ((CORE_ADDR, CORE_ADDR)); | |
190 | #define PUSH_RETURN_ADDRESS(PC, SP) mn10200_push_return_address (PC, SP) | |
191 | ||
192 | #define PUSH_DUMMY_FRAME generic_push_dummy_frame () | |
193 | ||
194 | extern CORE_ADDR | |
c5aa993b JM |
195 | mn10200_push_arguments PARAMS ((int, struct value **, CORE_ADDR, |
196 | unsigned char, CORE_ADDR)); | |
c906108c | 197 | #define PUSH_ARGUMENTS(NARGS, ARGS, SP, STRUCT_RETURN, STRUCT_ADDR) \ |
392a587b | 198 | (mn10200_push_arguments (NARGS, ARGS, SP, STRUCT_RETURN, STRUCT_ADDR)) |
c906108c | 199 | |
7a292a7a | 200 | #define PC_IN_CALL_DUMMY(PC, SP, FP) generic_pc_in_call_dummy (PC, SP, FP) |
c906108c SS |
201 | |
202 | #define REG_STRUCT_HAS_ADDR(gcc_p,TYPE) \ | |
203 | (TYPE_LENGTH (TYPE) > 8) | |
204 | ||
205 | extern use_struct_convention_fn mn10200_use_struct_convention; | |
206 | #define USE_STRUCT_CONVENTION(GCC_P, TYPE) mn10200_use_struct_convention (GCC_P, TYPE) | |
207 | ||
208 | /* Override the default get_saved_register function with | |
209 | one that takes account of generic CALL_DUMMY frames. */ | |
7a292a7a SS |
210 | #define GET_SAVED_REGISTER(raw_buffer, optimized, addrp, frame, regnum, lval) \ |
211 | generic_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval) | |
c906108c SS |
212 | |
213 | /* Define this for Wingdb */ | |
214 | #define TARGET_MN10200 |