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c906108c SS |
1 | /* HPPA PA-RISC machine native support for BSD, for GDB. |
2 | Copyright 1991, 1992 Free Software Foundation, Inc. | |
3 | ||
c5aa993b | 4 | This file is part of GDB. |
c906108c | 5 | |
c5aa993b JM |
6 | This program is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
c906108c | 10 | |
c5aa993b JM |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
c906108c | 15 | |
c5aa993b JM |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
20 | |
21 | #include "somsolib.h" | |
22 | ||
23 | #define U_REGS_OFFSET 0 | |
24 | ||
25 | #define KERNEL_U_ADDR 0 | |
26 | ||
27 | /* What a coincidence! */ | |
28 | #define REGISTER_U_ADDR(addr, blockend, regno) \ | |
29 | { addr = (int)(blockend) + REGISTER_BYTE (regno);} | |
30 | ||
31 | /* 3rd argument to ptrace is supposed to be a caddr_t. */ | |
32 | ||
33 | #define PTRACE_ARG3_TYPE caddr_t | |
34 | ||
35 | /* HPUX 8.0, in its infinite wisdom, has chosen to prototype ptrace | |
36 | with five arguments, so programs written for normal ptrace lose. */ | |
37 | #define FIVE_ARG_PTRACE | |
38 | ||
39 | ||
40 | /* This macro defines the register numbers (from REGISTER_NAMES) that | |
41 | are effectively unavailable to the user through ptrace(). It allows | |
42 | us to include the whole register set in REGISTER_NAMES (inorder to | |
43 | better support remote debugging). If it is used in | |
44 | fetch/store_inferior_registers() gdb will not complain about I/O errors | |
45 | on fetching these registers. If all registers in REGISTER_NAMES | |
46 | are available, then return false (0). */ | |
47 | ||
48 | #define CANNOT_STORE_REGISTER(regno) \ | |
49 | ((regno) == 0) || \ | |
50 | ((regno) == PCSQ_HEAD_REGNUM) || \ | |
51 | ((regno) >= PCSQ_TAIL_REGNUM && (regno) < IPSW_REGNUM) || \ | |
52 | ((regno) > IPSW_REGNUM && (regno) < FP4_REGNUM) | |
53 | ||
54 | /* fetch_inferior_registers is in hppab-nat.c. */ | |
55 | #define FETCH_INFERIOR_REGISTERS | |
56 | ||
57 | /* attach/detach works to some extent under BSD and HPUX. So long | |
58 | as the process you're attaching to isn't blocked waiting on io, | |
59 | blocked waiting on a signal, or in a system call things work | |
60 | fine. (The problems in those cases are related to the fact that | |
61 | the kernel can't provide complete register information for the | |
62 | target process... Which really pisses off GDB.) */ | |
63 | ||
64 | #define ATTACH_DETACH | |
65 | ||
66 | /* The PA-BSD kernel has support for using the data memory break bit | |
67 | to implement fast watchpoints. | |
68 | ||
69 | Watchpoints on the PA act much like traditional page protection | |
70 | schemes, but with some notable differences. | |
71 | ||
72 | First, a special bit in the page table entry is used to cause | |
73 | a trap when a specific page is written to. This avoids having | |
74 | to overload watchpoints on the page protection bits. This makes | |
75 | it possible for the kernel to easily decide if a trap was caused | |
76 | by a watchpoint or by the user writing to protected memory and can | |
77 | signal the user program differently in each case. | |
c5aa993b | 78 | |
c906108c SS |
79 | Second, the PA has a bit in the processor status word which causes |
80 | data memory breakpoints (aka watchpoints) to be disabled for a single | |
81 | instruction. This bit can be used to avoid the overhead of unprotecting | |
82 | and reprotecting pages when it becomes necessary to step over a watchpoint. | |
83 | ||
84 | ||
85 | When the kernel receives a trap indicating a write to a page which | |
86 | is being watched, the kernel performs a couple of simple actions. First | |
87 | is sets the magic "disable memory breakpoint" bit in the processor | |
88 | status word, it then sends a SIGTRAP to the process which caused the | |
89 | trap. | |
90 | ||
91 | GDB will take control and catch the signal for the inferior. GDB then | |
92 | examines the PSW-X bit to determine if the SIGTRAP was caused by a | |
93 | watchpoint firing. If so GDB single steps the inferior over the | |
94 | instruction which caused the watchpoint to trigger (note because the | |
95 | kernel disabled the data memory break bit for one instruction no trap | |
96 | will be taken!). GDB will then determines the appropriate action to | |
97 | take. (this may include restarting the inferior if the watchpoint | |
98 | fired because of a write to an address on the same page as a watchpoint, | |
99 | but no write to the watched address occured). */ | |
100 | ||
c5aa993b | 101 | #define TARGET_HAS_HARDWARE_WATCHPOINTS /* Enable the code in procfs.c */ |
c906108c SS |
102 | |
103 | /* The PA can watch any number of locations, there's no need for it to reject | |
104 | anything (generic routines already check that all intermediates are | |
105 | in memory). */ | |
106 | #define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \ | |
107 | ((type) == bp_hardware_watchpoint) | |
108 | ||
109 | /* When a hardware watchpoint fires off the PC will be left at the | |
110 | instruction which caused the watchpoint. It will be necessary for | |
111 | GDB to step over the watchpoint. | |
112 | ||
113 | On a PA running BSD, it is trivial to identify when it will be | |
114 | necessary to step over a hardware watchpoint as we can examine | |
115 | the PSW-X bit. If the bit is on, then we trapped because of a | |
116 | watchpoint, else we trapped for some other reason. */ | |
117 | #define STOPPED_BY_WATCHPOINT(W) \ | |
118 | ((W).kind == TARGET_WAITKIND_STOPPED \ | |
119 | && (W).value.sig == TARGET_SIGNAL_TRAP \ | |
120 | && ((int) read_register (IPSW_REGNUM) & 0x00100000)) | |
121 | ||
122 | /* The PA can single step over a watchpoint if the kernel has set the | |
123 | "X" bit in the processor status word (disable data memory breakpoint | |
124 | for one instruction). | |
125 | ||
126 | The kernel will always set this bit before notifying the inferior | |
127 | that it hit a watchpoint. Thus, the inferior can single step over | |
128 | the instruction which caused the watchpoint to fire. This avoids | |
129 | the traditional need to disable the watchpoint, step the inferior, | |
130 | then enable the watchpoint again. */ | |
131 | #define HAVE_STEPPABLE_WATCHPOINT | |
132 | ||
133 | /* Use these macros for watchpoint insertion/deletion. */ | |
134 | /* type can be 0: write watch, 1: read watch, 2: access watch (read/write) */ | |
135 | #define target_insert_watchpoint(addr, len, type) hppa_set_watchpoint (addr, len, 1) | |
136 | #define target_remove_watchpoint(addr, len, type) hppa_set_watchpoint (addr, len, 0) |