Commit | Line | Data |
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d6ea322f | 1 | /* Target machine definitions for GDB for an embedded SPARC. |
d0e51077 | 2 | Copyright 1996 Free Software Foundation, Inc. |
d6ea322f DP |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
19 | ||
20 | #include "sparc/tm-sparc.h" | |
21 | ||
22 | #define TARGET_SPARCLET 1 | |
23 | ||
edbceb89 DE |
24 | /* Select the sparclet disassembler. Slightly different instruction set from |
25 | the V8 sparc. */ | |
26 | ||
27 | #undef TM_PRINT_INSN_MACH | |
28 | #define TM_PRINT_INSN_MACH bfd_mach_sparc_sparclet | |
29 | ||
d6ea322f DP |
30 | /* overrides of tm-sparc.h */ |
31 | ||
d0e51077 DE |
32 | #undef TARGET_BYTE_ORDER |
33 | #define TARGET_BYTE_ORDER_SELECTABLE | |
34 | ||
35 | /* Sequence of bytes for breakpoint instruction (ta 1). */ | |
36 | #undef BREAKPOINT | |
37 | #define BIG_BREAKPOINT {0x91, 0xd0, 0x20, 0x01} | |
38 | #define LITTLE_BREAKPOINT {0x01, 0x20, 0xd0, 0x91} | |
39 | ||
a7f6f9ed MS |
40 | #undef NUM_REGS /* formerly "72" */ |
41 | /* WIN FP CPU CCP ASR AWR APSR */ | |
42 | #define NUM_REGS (32 + 32 + 8 + 8 + 8/*+ 32 + 1*/) | |
43 | ||
44 | #undef REGISTER_BYTES /* formerly "(32*4 + 32*4 + 8*4)" */ | |
45 | #define REGISTER_BYTES (32*4 + 32*4 + 8*4 + 8*4 + 8*4/* + 32*4 + 1*4*/) | |
46 | ||
d6ea322f DP |
47 | /* Initializer for an array of names of registers. |
48 | There should be NUM_REGS strings in this initializer. */ | |
49 | /* Sparclet has no fp! */ | |
50 | /* Compiler maps types for floats by number, so can't | |
51 | change the numbers here. */ | |
52 | ||
53 | #undef REGISTER_NAMES | |
d6ea322f | 54 | #define REGISTER_NAMES \ |
a7f6f9ed | 55 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \ |
d6ea322f DP |
56 | "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", \ |
57 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", \ | |
58 | "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", \ | |
a7f6f9ed MS |
59 | \ |
60 | "", "", "", "", "", "", "", "", /* no FPU regs */ \ | |
61 | "", "", "", "", "", "", "", "", \ | |
62 | "", "", "", "", "", "", "", "", \ | |
63 | "", "", "", "", "", "", "", "", \ | |
64 | /* no CPSR, FPSR */ \ | |
65 | "y", "psr", "wim", "tbr", "pc", "npc", "", "", \ | |
66 | \ | |
67 | "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "", \ | |
68 | \ | |
5a1ed5f7 MS |
69 | /* ASR15 ASR19 (don't display them) */ \ |
70 | "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22", \ | |
a7f6f9ed MS |
71 | /* \ |
72 | "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7", \ | |
73 | "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15", \ | |
74 | "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23", \ | |
75 | "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31", \ | |
76 | "apsr", \ | |
77 | */ \ | |
78 | } | |
d6ea322f DP |
79 | |
80 | /* Remove FP dependant code which was defined in tm-sparc.h */ | |
81 | #undef FP0_REGNUM /* Floating point register 0 */ | |
82 | #undef FPS_REGNUM /* Floating point status register */ | |
83 | #undef CPS_REGNUM /* Coprocessor status register */ | |
84 | ||
a7f6f9ed MS |
85 | /* sparclet register numbers */ |
86 | #define CCSR_REGNUM 72 | |
87 | ||
d6ea322f | 88 | #undef EXTRACT_RETURN_VALUE |
a7f6f9ed | 89 | #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \ |
d6ea322f | 90 | { \ |
a7f6f9ed MS |
91 | memcpy ((VALBUF), \ |
92 | (char *)(REGBUF) + REGISTER_RAW_SIZE (O0_REGNUM) * 8 + \ | |
93 | (TYPE_LENGTH(TYPE) >= REGISTER_RAW_SIZE (O0_REGNUM) \ | |
94 | ? 0 : REGISTER_RAW_SIZE (O0_REGNUM) - TYPE_LENGTH(TYPE)), \ | |
95 | TYPE_LENGTH(TYPE)); \ | |
d6ea322f DP |
96 | } |
97 | #undef STORE_RETURN_VALUE | |
98 | #define STORE_RETURN_VALUE(TYPE,VALBUF) \ | |
a7f6f9ed MS |
99 | { \ |
100 | /* Other values are returned in register %o0. */ \ | |
101 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), (VALBUF), \ | |
102 | TYPE_LENGTH (TYPE)); \ | |
d6ea322f | 103 | } |
a7f6f9ed | 104 | |
d6ea322f DP |
105 | #undef PRINT_REGISTER_HOOK |
106 | #define PRINT_REGISTER_HOOK(regno) | |
107 | ||
d6ea322f DP |
108 | /* Offsets into jmp_buf. Not defined by Sun, but at least documented in a |
109 | comment in <machine/setjmp.h>! */ | |
110 | ||
111 | #define JB_ELEMENT_SIZE 4 /* Size of each element in jmp_buf */ | |
112 | ||
113 | #define JB_ONSSTACK 0 | |
114 | #define JB_SIGMASK 1 | |
115 | #define JB_SP 2 | |
116 | #define JB_PC 3 | |
117 | #define JB_NPC 4 | |
118 | #define JB_PSR 5 | |
119 | #define JB_G1 6 | |
120 | #define JB_O0 7 | |
121 | #define JB_WBCNT 8 | |
122 | ||
123 | /* Figure out where the longjmp will land. We expect that we have just entered | |
124 | longjmp and haven't yet setup the stack frame, so the args are still in the | |
125 | output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we | |
126 | extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. | |
127 | This routine returns true on success */ | |
128 | ||
129 | extern int | |
130 | get_longjmp_target PARAMS ((CORE_ADDR *)); | |
131 | ||
132 | #define GET_LONGJMP_TARGET(ADDR) get_longjmp_target(ADDR) |