[deliverable/binutils-gdb.git] / gdb / config / sparc / tm-sparclite.h

/* Macro definitions for GDB for a Fujitsu SPARClite.
   Copyright 1993 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#define TARGET_SPARCLITE 1	/* Still needed for non-multi-arch case */

#include "sparc/tm-sparc.h"

/* Note: we are not defining GDB_MULTI_ARCH for the sparclet target
   at this time, because we have not figured out how to detect the
   sparclet target from the bfd structure.  */

/* Sparclite regs, for debugging purposes */

enum {
  DIA1_REGNUM = 72,		/* debug instr address register 1 */
  DIA2_REGNUM = 73,		/* debug instr address register 2 */
  DDA1_REGNUM = 74,		/* debug data address register 1 */
  DDA2_REGNUM = 75,		/* debug data address register 2 */
  DDV1_REGNUM = 76,		/* debug data value register 1 */
  DDV2_REGNUM = 77,		/* debug data value register 2 */
  DCR_REGNUM  = 78,		/* debug control register */
  DSR_REGNUM  = 79		/* debug status regsiter */
};

/* overrides of tm-sparc.h */

#undef TARGET_BYTE_ORDER
#define TARGET_BYTE_ORDER_SELECTABLE

/* Select the sparclite disassembler.  Slightly different instruction set from
   the V8 sparc.  */

#undef TM_PRINT_INSN_MACH
#define TM_PRINT_INSN_MACH bfd_mach_sparc_sparclite

/* Amount PC must be decremented by after a hardware instruction breakpoint.
   This is often the number of bytes in BREAKPOINT
   but not always.  */

#define DECR_PC_AFTER_HW_BREAK 4

#if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
/*
 * The following defines must go away for MULTI_ARCH.
 */

#undef  FRAME_CHAIN_VALID
#define FRAME_CHAIN_VALID(FP,FI) func_frame_chain_valid (FP, FI)

#undef NUM_REGS
#define NUM_REGS 80

#undef REGISTER_BYTES
#define REGISTER_BYTES (32*4+32*4+8*4+8*4)

#undef REGISTER_NAMES
#define REGISTER_NAMES  \
{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",       \
  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",       \
  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",       \
  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",       \
                                                                \
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",       \
  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",       \
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",       \
                                                                \
  "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",        \
  "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" }

#define DIA1_REGNUM 72		/* debug instr address register 1 */
#define DIA2_REGNUM 73		/* debug instr address register 2 */
#define DDA1_REGNUM 74		/* debug data address register 1 */
#define DDA2_REGNUM 75		/* debug data address register 2 */
#define DDV1_REGNUM 76		/* debug data value register 1 */
#define DDV2_REGNUM 77		/* debug data value register 2 */
#define DCR_REGNUM 78		/* debug control register */
#define DSR_REGNUM 79		/* debug status regsiter */

#endif /* GDB_MULTI_ARCH */

#define TARGET_HW_BREAK_LIMIT 2
#define TARGET_HW_WATCH_LIMIT 2

/* Enable watchpoint macro's */

#define TARGET_HAS_HARDWARE_WATCHPOINTS

#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
	sparclite_check_watch_resources (type, cnt, ot)

/* When a hardware watchpoint fires off the PC will be left at the
   instruction which caused the watchpoint.  It will be necessary for
   GDB to step over the watchpoint. ***

   #define STOPPED_BY_WATCHPOINT(W) \
   ((W).kind == TARGET_WAITKIND_STOPPED \
   && (W).value.sig == TARGET_SIGNAL_TRAP \
   && ((int) read_register (IPSW_REGNUM) & 0x00100000))
 */

/* Use these macros for watchpoint insertion/deletion.  */
#define target_insert_watchpoint(addr, len, type) sparclite_insert_watchpoint (addr, len, type)
#define target_remove_watchpoint(addr, len, type) sparclite_remove_watchpoint (addr, len, type)
#define target_insert_hw_breakpoint(addr, len) sparclite_insert_hw_breakpoint (addr, len)
#define target_remove_hw_breakpoint(addr, len) sparclite_remove_hw_breakpoint (addr, len)
#define target_stopped_data_address() sparclite_stopped_data_address()
Commit	Line	Data
c906108c SS	1	/* Macro definitions for GDB for a Fujitsu SPARClite.
	2	Copyright 1993 Free Software Foundation, Inc.
	3
c5aa993b	4	This file is part of GDB.
c906108c	5
c5aa993b JM	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
c906108c	10
c5aa993b JM	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
c906108c	15
c5aa993b JM	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 59 Temple Place - Suite 330,
	19	Boston, MA 02111-1307, USA. */
c906108c	20
5af923b0	21	#define TARGET_SPARCLITE 1 /* Still needed for non-multi-arch case */
c906108c SS	22
	23	#include "sparc/tm-sparc.h"
	24
5af923b0 MS	25	/* Note: we are not defining GDB_MULTI_ARCH for the sparclet target
	26	at this time, because we have not figured out how to detect the
	27	sparclet target from the bfd structure. */
	28
	29	/* Sparclite regs, for debugging purposes */
	30
	31	enum {
	32	DIA1_REGNUM = 72, /* debug instr address register 1 */
	33	DIA2_REGNUM = 73, /* debug instr address register 2 */
	34	DDA1_REGNUM = 74, /* debug data address register 1 */
	35	DDA2_REGNUM = 75, /* debug data address register 2 */
	36	DDV1_REGNUM = 76, /* debug data value register 1 */
	37	DDV2_REGNUM = 77, /* debug data value register 2 */
	38	DCR_REGNUM = 78, /* debug control register */
	39	DSR_REGNUM = 79 /* debug status regsiter */
	40	};
	41
c906108c SS	42	/* overrides of tm-sparc.h */
	43
	44	#undef TARGET_BYTE_ORDER
	45	#define TARGET_BYTE_ORDER_SELECTABLE
	46
	47	/* Select the sparclite disassembler. Slightly different instruction set from
	48	the V8 sparc. */
	49
	50	#undef TM_PRINT_INSN_MACH
	51	#define TM_PRINT_INSN_MACH bfd_mach_sparc_sparclite
	52
	53	/* Amount PC must be decremented by after a hardware instruction breakpoint.
	54	This is often the number of bytes in BREAKPOINT
	55	but not always. */
	56
	57	#define DECR_PC_AFTER_HW_BREAK 4
	58
5af923b0 MS	59	#if !defined (GDB_MULTI_ARCH) \|\| (GDB_MULTI_ARCH == 0)
	60	/*
	61	* The following defines must go away for MULTI_ARCH.
	62	*/
	63
	64	#undef FRAME_CHAIN_VALID
	65	#define FRAME_CHAIN_VALID(FP,FI) func_frame_chain_valid (FP, FI)
c906108c	66
c5aa993b JM	67	#undef NUM_REGS
c5aa993b JM	68	#define NUM_REGS 80
c906108c SS	69
	70	#undef REGISTER_BYTES
	71	#define REGISTER_BYTES (324+324+84+84)
	72
	73	#undef REGISTER_NAMES
	74	#define REGISTER_NAMES \
	75	{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
	76	"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", \
	77	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
	78	"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", \
	79	\
	80	"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
	81	"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
	82	"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
	83	"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
	84	\
	85	"y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr", \
	86	"dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" }
	87
c5aa993b JM	88	#define DIA1_REGNUM 72 /* debug instr address register 1 */
	89	#define DIA2_REGNUM 73 /* debug instr address register 2 */
	90	#define DDA1_REGNUM 74 /* debug data address register 1 */
	91	#define DDA2_REGNUM 75 /* debug data address register 2 */
	92	#define DDV1_REGNUM 76 /* debug data value register 1 */
	93	#define DDV2_REGNUM 77 /* debug data value register 2 */
	94	#define DCR_REGNUM 78 /* debug control register */
	95	#define DSR_REGNUM 79 /* debug status regsiter */
c906108c	96
5af923b0 MS	97	#endif /* GDB_MULTI_ARCH */
5af923b0 MS	98
c906108c SS	99	#define TARGET_HW_BREAK_LIMIT 2
	100	#define TARGET_HW_WATCH_LIMIT 2
	101
	102	/* Enable watchpoint macro's */
	103
	104	#define TARGET_HAS_HARDWARE_WATCHPOINTS
	105
	106	#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \
	107	sparclite_check_watch_resources (type, cnt, ot)
	108
	109	/* When a hardware watchpoint fires off the PC will be left at the
	110	instruction which caused the watchpoint. It will be necessary for
	111	GDB to step over the watchpoint. ***
	112
c5aa993b JM	113	#define STOPPED_BY_WATCHPOINT(W) \
c5aa993b JM	114	((W).kind == TARGET_WAITKIND_STOPPED \
c906108c SS	115	&& (W).value.sig == TARGET_SIGNAL_TRAP \
c906108c SS	116	&& ((int) read_register (IPSW_REGNUM) & 0x00100000))
c5aa993b	117	*/
c906108c SS	118
	119	/* Use these macros for watchpoint insertion/deletion. */
	120	#define target_insert_watchpoint(addr, len, type) sparclite_insert_watchpoint (addr, len, type)
	121	#define target_remove_watchpoint(addr, len, type) sparclite_remove_watchpoint (addr, len, type)
	122	#define target_insert_hw_breakpoint(addr, len) sparclite_insert_hw_breakpoint (addr, len)
	123	#define target_remove_hw_breakpoint(addr, len) sparclite_remove_hw_breakpoint (addr, len)
	124	#define target_stopped_data_address() sparclite_stopped_data_address()