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29134980 OF |
1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
2 | Copyright 2001 Free Software Foundation, Inc. | |
3 | Contributed by Axis Communications AB. | |
4 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "symtab.h" | |
25 | #include "inferior.h" | |
26 | #include "gdbtypes.h" | |
27 | #include "gdbcore.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "target.h" | |
30 | #include "value.h" | |
31 | #include "opcode/cris.h" | |
32 | #include "arch-utils.h" | |
33 | #include "regcache.h" | |
34 | ||
35 | /* To get entry_point_address. */ | |
36 | #include "symfile.h" | |
37 | ||
38 | enum cris_num_regs | |
39 | { | |
40 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
41 | NUM_FREGS = 0, | |
42 | ||
43 | /* There are 16 general registers. */ | |
44 | NUM_GENREGS = 16, | |
45 | ||
46 | /* There are 16 special registers. */ | |
47 | NUM_SPECREGS = 16 | |
48 | }; | |
49 | ||
50 | /* Register numbers of various important registers. | |
51 | FP_REGNUM Contains address of executing stack frame. | |
52 | STR_REGNUM Contains the address of structure return values. | |
53 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
54 | ARG1_REGNUM Contains the first parameter to a function. | |
55 | ARG2_REGNUM Contains the second parameter to a function. | |
56 | ARG3_REGNUM Contains the third parameter to a function. | |
57 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. | |
58 | SP_REGNUM Contains address of top of stack. | |
59 | PC_REGNUM Contains address of next instruction. | |
60 | SRP_REGNUM Subroutine return pointer register. | |
61 | BRP_REGNUM Breakpoint return pointer register. */ | |
62 | ||
63 | /* FP_REGNUM = 8, SP_REGNUM = 14, and PC_REGNUM = 15 have been incorporated | |
64 | into the multi-arch framework. */ | |
65 | ||
66 | enum cris_regnums | |
67 | { | |
68 | /* Enums with respect to the general registers, valid for all | |
69 | CRIS versions. */ | |
70 | STR_REGNUM = 9, | |
71 | RET_REGNUM = 10, | |
72 | ARG1_REGNUM = 10, | |
73 | ARG2_REGNUM = 11, | |
74 | ARG3_REGNUM = 12, | |
75 | ARG4_REGNUM = 13, | |
76 | ||
77 | /* Enums with respect to the special registers, some of which may not be | |
78 | applicable to all CRIS versions. */ | |
79 | P0_REGNUM = 16, | |
80 | VR_REGNUM = 17, | |
81 | P2_REGNUM = 18, | |
82 | P3_REGNUM = 19, | |
83 | P4_REGNUM = 20, | |
84 | CCR_REGNUM = 21, | |
85 | MOF_REGNUM = 23, | |
86 | P8_REGNUM = 24, | |
87 | IBR_REGNUM = 25, | |
88 | IRP_REGNUM = 26, | |
89 | SRP_REGNUM = 27, | |
90 | BAR_REGNUM = 28, | |
2a9ecef2 | 91 | DCCR_REGNUM = 29, |
29134980 OF |
92 | BRP_REGNUM = 30, |
93 | USP_REGNUM = 31 | |
94 | }; | |
95 | ||
96 | extern const struct cris_spec_reg cris_spec_regs[]; | |
97 | ||
98 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
99 | register names and sizes.*/ | |
100 | static int usr_cmd_cris_version; | |
101 | ||
102 | /* Indicates whether to trust the above variable. */ | |
103 | static int usr_cmd_cris_version_valid = 0; | |
104 | ||
105 | /* CRIS mode, set via the user command 'set cris-mode'. Affects availability | |
106 | of some registers. */ | |
107 | static const char *usr_cmd_cris_mode; | |
108 | ||
109 | /* Indicates whether to trust the above variable. */ | |
110 | static int usr_cmd_cris_mode_valid = 0; | |
111 | ||
112 | static const char CRIS_MODE_USER[] = "CRIS_MODE_USER"; | |
113 | static const char CRIS_MODE_SUPERVISOR[] = "CRIS_MODE_SUPERVISOR"; | |
114 | static const char *cris_mode_enums[] = | |
115 | { | |
116 | CRIS_MODE_USER, | |
117 | CRIS_MODE_SUPERVISOR, | |
118 | 0 | |
119 | }; | |
120 | ||
121 | /* CRIS ABI, set via the user command 'set cris-abi'. | |
122 | There are two flavours: | |
123 | 1. Original ABI with 32-bit doubles, where arguments <= 4 bytes are | |
124 | passed by value. | |
125 | 2. New ABI with 64-bit doubles, where arguments <= 8 bytes are passed by | |
126 | value. */ | |
127 | static const char *usr_cmd_cris_abi; | |
128 | ||
129 | /* Indicates whether to trust the above variable. */ | |
130 | static int usr_cmd_cris_abi_valid = 0; | |
131 | ||
132 | /* These variables are strings instead of enums to make them usable as | |
133 | parameters to add_set_enum_cmd. */ | |
134 | static const char CRIS_ABI_ORIGINAL[] = "CRIS_ABI_ORIGINAL"; | |
135 | static const char CRIS_ABI_V2[] = "CRIS_ABI_V2"; | |
136 | static const char CRIS_ABI_SYMBOL[] = ".$CRIS_ABI_V2"; | |
137 | static const char *cris_abi_enums[] = | |
138 | { | |
139 | CRIS_ABI_ORIGINAL, | |
140 | CRIS_ABI_V2, | |
141 | 0 | |
142 | }; | |
143 | ||
144 | /* CRIS architecture specific information. */ | |
145 | struct gdbarch_tdep | |
146 | { | |
147 | int cris_version; | |
148 | const char *cris_mode; | |
149 | const char *cris_abi; | |
150 | }; | |
151 | ||
152 | /* Functions for accessing target dependent data. */ | |
153 | ||
154 | static int | |
155 | cris_version (void) | |
156 | { | |
157 | return (gdbarch_tdep (current_gdbarch)->cris_version); | |
158 | } | |
159 | ||
160 | static const char * | |
161 | cris_mode (void) | |
162 | { | |
163 | return (gdbarch_tdep (current_gdbarch)->cris_mode); | |
164 | } | |
165 | ||
166 | static const char * | |
167 | cris_abi (void) | |
168 | { | |
169 | return (gdbarch_tdep (current_gdbarch)->cris_abi); | |
170 | } | |
171 | ||
172 | /* For saving call-clobbered contents in R9 when returning structs. */ | |
173 | static CORE_ADDR struct_return_address; | |
174 | ||
175 | struct frame_extra_info | |
176 | { | |
177 | CORE_ADDR return_pc; | |
178 | int leaf_function; | |
179 | }; | |
180 | ||
181 | /* The instruction environment needed to find single-step breakpoints. */ | |
182 | typedef | |
183 | struct instruction_environment | |
184 | { | |
185 | unsigned long reg[NUM_GENREGS]; | |
186 | unsigned long preg[NUM_SPECREGS]; | |
187 | unsigned long branch_break_address; | |
188 | unsigned long delay_slot_pc; | |
189 | unsigned long prefix_value; | |
190 | int branch_found; | |
191 | int prefix_found; | |
192 | int invalid; | |
193 | int slot_needed; | |
194 | int delay_slot_pc_active; | |
195 | int xflag_found; | |
196 | int disable_interrupt; | |
197 | } inst_env_type; | |
198 | ||
199 | /* Save old breakpoints in order to restore the state before a single_step. | |
200 | At most, two breakpoints will have to be remembered. */ | |
201 | typedef | |
202 | char binsn_quantum[BREAKPOINT_MAX]; | |
203 | static binsn_quantum break_mem[2]; | |
204 | static CORE_ADDR next_pc = 0; | |
205 | static CORE_ADDR branch_target_address = 0; | |
206 | static unsigned char branch_break_inserted = 0; | |
207 | ||
208 | /* Machine-dependencies in CRIS for opcodes. */ | |
209 | ||
210 | /* Instruction sizes. */ | |
211 | enum cris_instruction_sizes | |
212 | { | |
213 | INST_BYTE_SIZE = 0, | |
214 | INST_WORD_SIZE = 1, | |
215 | INST_DWORD_SIZE = 2 | |
216 | }; | |
217 | ||
218 | /* Addressing modes. */ | |
219 | enum cris_addressing_modes | |
220 | { | |
221 | REGISTER_MODE = 1, | |
222 | INDIRECT_MODE = 2, | |
223 | AUTOINC_MODE = 3 | |
224 | }; | |
225 | ||
226 | /* Prefix addressing modes. */ | |
227 | enum cris_prefix_addressing_modes | |
228 | { | |
229 | PREFIX_INDEX_MODE = 2, | |
230 | PREFIX_ASSIGN_MODE = 3, | |
231 | ||
232 | /* Handle immediate byte offset addressing mode prefix format. */ | |
233 | PREFIX_OFFSET_MODE = 2 | |
234 | }; | |
235 | ||
236 | /* Masks for opcodes. */ | |
237 | enum cris_opcode_masks | |
238 | { | |
239 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
240 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
241 | SIGNED_BYTE_MASK = 0x80, | |
242 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
243 | SIGNED_WORD_MASK = 0x8000, | |
244 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
245 | SIGNED_DWORD_MASK = 0x80000000, | |
246 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
247 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
248 | }; | |
249 | ||
250 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
251 | Bit 15 - 12 Operand2 | |
252 | 11 - 10 Mode | |
253 | 9 - 6 Opcode | |
254 | 5 - 4 Size | |
255 | 3 - 0 Operand1 */ | |
256 | ||
257 | static int | |
258 | cris_get_operand2 (unsigned short insn) | |
259 | { | |
260 | return ((insn & 0xF000) >> 12); | |
261 | } | |
262 | ||
263 | static int | |
264 | cris_get_mode (unsigned short insn) | |
265 | { | |
266 | return ((insn & 0x0C00) >> 10); | |
267 | } | |
268 | ||
269 | static int | |
270 | cris_get_opcode (unsigned short insn) | |
271 | { | |
272 | return ((insn & 0x03C0) >> 6); | |
273 | } | |
274 | ||
275 | static int | |
276 | cris_get_size (unsigned short insn) | |
277 | { | |
278 | return ((insn & 0x0030) >> 4); | |
279 | } | |
280 | ||
281 | static int | |
282 | cris_get_operand1 (unsigned short insn) | |
283 | { | |
284 | return (insn & 0x000F); | |
285 | } | |
286 | ||
287 | /* Additional functions in order to handle opcodes. */ | |
288 | ||
289 | static int | |
290 | cris_get_wide_opcode (unsigned short insn) | |
291 | { | |
292 | return ((insn & 0x03E0) >> 5); | |
293 | } | |
294 | ||
295 | static int | |
296 | cris_get_short_size (unsigned short insn) | |
297 | { | |
298 | return ((insn & 0x0010) >> 4); | |
299 | } | |
300 | ||
301 | static int | |
302 | cris_get_quick_value (unsigned short insn) | |
303 | { | |
304 | return (insn & 0x003F); | |
305 | } | |
306 | ||
307 | static int | |
308 | cris_get_bdap_quick_offset (unsigned short insn) | |
309 | { | |
310 | return (insn & 0x00FF); | |
311 | } | |
312 | ||
313 | static int | |
314 | cris_get_branch_short_offset (unsigned short insn) | |
315 | { | |
316 | return (insn & 0x00FF); | |
317 | } | |
318 | ||
319 | static int | |
320 | cris_get_asr_shift_steps (unsigned long value) | |
321 | { | |
322 | return (value & 0x3F); | |
323 | } | |
324 | ||
325 | static int | |
326 | cris_get_asr_quick_shift_steps (unsigned short insn) | |
327 | { | |
328 | return (insn & 0x1F); | |
329 | } | |
330 | ||
331 | static int | |
332 | cris_get_clear_size (unsigned short insn) | |
333 | { | |
334 | return ((insn) & 0xC000); | |
335 | } | |
336 | ||
337 | static int | |
338 | cris_is_signed_extend_bit_on (unsigned short insn) | |
339 | { | |
340 | return (((insn) & 0x20) == 0x20); | |
341 | } | |
342 | ||
343 | static int | |
344 | cris_is_xflag_bit_on (unsigned short insn) | |
345 | { | |
346 | return (((insn) & 0x1000) == 0x1000); | |
347 | } | |
348 | ||
349 | static void | |
350 | cris_set_size_to_dword (unsigned short *insn) | |
351 | { | |
352 | *insn &= 0xFFCF; | |
353 | *insn |= 0x20; | |
354 | } | |
355 | ||
8535cb38 | 356 | static signed char |
29134980 OF |
357 | cris_get_signed_offset (unsigned short insn) |
358 | { | |
8535cb38 | 359 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
360 | } |
361 | ||
362 | /* Calls an op function given the op-type, working on the insn and the | |
363 | inst_env. */ | |
364 | static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); | |
365 | ||
366 | static CORE_ADDR cris_skip_prologue_main (CORE_ADDR pc, int frameless_p); | |
367 | ||
368 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, | |
369 | struct gdbarch_list *); | |
370 | ||
371 | static int cris_delayed_get_disassembler (bfd_vma, disassemble_info *); | |
372 | ||
373 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); | |
374 | ||
375 | static void cris_version_update (char *ignore_args, int from_tty, | |
376 | struct cmd_list_element *c); | |
377 | ||
378 | static void cris_mode_update (char *ignore_args, int from_tty, | |
379 | struct cmd_list_element *c); | |
380 | ||
381 | static void cris_abi_update (char *ignore_args, int from_tty, | |
382 | struct cmd_list_element *c); | |
383 | ||
384 | static CORE_ADDR bfd_lookup_symbol (bfd *, const char *); | |
385 | ||
386 | /* Frames information. The definition of the struct frame_info is | |
387 | ||
388 | CORE_ADDR frame | |
389 | CORE_ADDR pc | |
390 | int signal_handler_caller | |
391 | CORE_ADDR return_pc | |
392 | int leaf_function | |
393 | ||
394 | If the compilation option -fno-omit-frame-pointer is present the | |
395 | variable frame will be set to the content of R8 which is the frame | |
396 | pointer register. | |
397 | ||
398 | The variable pc contains the address where execution is performed | |
399 | in the present frame. The innermost frame contains the current content | |
400 | of the register PC. All other frames contain the content of the | |
401 | register PC in the next frame. | |
402 | ||
403 | The variable signal_handler_caller is non-zero when the frame is | |
404 | associated with the call of a signal handler. | |
405 | ||
406 | The variable return_pc contains the address where execution should be | |
407 | resumed when the present frame has finished, the return address. | |
408 | ||
409 | The variable leaf_function is 1 if the return address is in the register | |
410 | SRP, and 0 if it is on the stack. | |
411 | ||
412 | Prologue instructions C-code. | |
413 | The prologue may consist of (-fno-omit-frame-pointer) | |
414 | 1) 2) | |
415 | push srp | |
416 | push r8 push r8 | |
417 | move.d sp,r8 move.d sp,r8 | |
418 | subq X,sp subq X,sp | |
419 | movem rY,[sp] movem rY,[sp] | |
420 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
421 | ||
422 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
423 | ||
424 | Note that this assumption is extremely brittle, and will break at the | |
425 | slightest change in GCC's prologue. | |
426 | ||
427 | If local variables are declared or register contents are saved on stack | |
428 | the subq-instruction will be present with X as the number of bytes | |
429 | needed for storage. The reshuffle with respect to r8 may be performed | |
430 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
431 | The offset U should be representable by a signed 8-bit value in all cases. | |
432 | Thus, the prefix word is assumed to be immediate byte offset mode followed | |
433 | by another word containing the instruction. | |
434 | ||
435 | Degenerate cases: | |
436 | 3) | |
437 | push r8 | |
438 | move.d sp,r8 | |
439 | move.d r8,sp | |
440 | pop r8 | |
441 | ||
442 | Prologue instructions C++-code. | |
443 | Case 1) and 2) in the C-code may be followed by | |
444 | ||
445 | move.d r10,rS ; this | |
446 | move.d r11,rT ; P1 | |
447 | move.d r12,rU ; P2 | |
448 | move.d r13,rV ; P3 | |
449 | move.S [r8+U],rZ ; P4 | |
450 | ||
451 | if any of the call parameters are stored. The host expects these | |
452 | instructions to be executed in order to get the call parameters right. */ | |
453 | ||
454 | /* Examine the prologue of a function. The variable ip is the address of | |
455 | the first instruction of the prologue. The variable limit is the address | |
456 | of the first instruction after the prologue. The variable fi contains the | |
457 | information in struct frame_info. The variable frameless_p controls whether | |
458 | the entire prologue is examined (0) or just enough instructions to | |
459 | determine that it is a prologue (1). */ | |
460 | ||
461 | CORE_ADDR | |
462 | cris_examine (CORE_ADDR ip, CORE_ADDR limit, struct frame_info *fi, | |
463 | int frameless_p) | |
464 | { | |
465 | /* Present instruction. */ | |
466 | unsigned short insn; | |
467 | ||
468 | /* Next instruction, lookahead. */ | |
469 | unsigned short insn_next; | |
470 | int regno; | |
471 | ||
472 | /* Is there a push fp? */ | |
473 | int have_fp; | |
474 | ||
475 | /* Number of byte on stack used for local variables and movem. */ | |
476 | int val; | |
477 | ||
478 | /* Highest register number in a movem. */ | |
479 | int regsave; | |
480 | ||
481 | /* move.d r<source_register>,rS */ | |
482 | short source_register; | |
483 | ||
484 | /* This frame is with respect to a leaf until a push srp is found. */ | |
485 | fi->extra_info->leaf_function = 1; | |
486 | ||
487 | /* This frame is without the FP until a push fp is found. */ | |
488 | have_fp = 0; | |
489 | ||
490 | /* Assume nothing on stack. */ | |
491 | val = 0; | |
492 | regsave = -1; | |
493 | ||
494 | /* No information about register contents so far. */ | |
495 | ||
496 | /* We only want to know the end of the prologue when fi->saved_regs == 0. | |
497 | When the saved registers are allocated full information is required. */ | |
498 | if (fi->saved_regs) | |
499 | { | |
500 | for (regno = 0; regno < NUM_REGS; regno++) | |
501 | fi->saved_regs[regno] = 0; | |
502 | } | |
503 | ||
504 | /* Find the prologue instructions. */ | |
505 | do | |
506 | { | |
507 | insn = read_memory_unsigned_integer (ip, sizeof (short)); | |
508 | ip += sizeof (short); | |
509 | if (insn == 0xE1FC) | |
510 | { | |
511 | /* push <reg> 32 bit instruction */ | |
512 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); | |
513 | ip += sizeof (short); | |
514 | regno = cris_get_operand2 (insn_next); | |
515 | if (regno == (SRP_REGNUM - NUM_GENREGS)) | |
516 | { | |
517 | if (frameless_p) | |
518 | { | |
519 | return ip; | |
520 | } | |
521 | fi->extra_info->leaf_function = 0; | |
522 | } | |
523 | else if (regno == FP_REGNUM) | |
524 | { | |
525 | have_fp = 1; | |
526 | } | |
527 | } | |
528 | else if (insn == 0x866E) | |
529 | { | |
530 | /* move.d sp,r8 */ | |
531 | if (frameless_p) | |
532 | { | |
533 | return ip; | |
534 | } | |
535 | continue; | |
536 | } | |
537 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
538 | && cris_get_mode (insn) == 0x0000 | |
539 | && cris_get_opcode (insn) == 0x000A) | |
540 | { | |
541 | /* subq <val>,sp */ | |
542 | val = cris_get_quick_value (insn); | |
543 | } | |
544 | else if (cris_get_mode (insn) == 0x0002 | |
545 | && cris_get_opcode (insn) == 0x000F | |
546 | && cris_get_size (insn) == 0x0003 | |
547 | && cris_get_operand1 (insn) == SP_REGNUM) | |
548 | { | |
549 | /* movem r<regsave>,[sp] */ | |
550 | if (frameless_p) | |
551 | { | |
552 | return ip; | |
553 | } | |
554 | regsave = cris_get_operand2 (insn); | |
555 | } | |
556 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
557 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
558 | && (cris_get_signed_offset (insn) < 0)) | |
559 | { | |
560 | /* Immediate byte offset addressing prefix word with sp as base | |
561 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
562 | is between 64 and 128. | |
563 | movem r<regsave>,[sp=sp-<val>] */ | |
564 | val = -cris_get_signed_offset (insn); | |
565 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); | |
566 | ip += sizeof (short); | |
567 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE | |
568 | && cris_get_opcode (insn_next) == 0x000F | |
569 | && cris_get_size (insn_next) == 0x0003 | |
570 | && cris_get_operand1 (insn_next) == SP_REGNUM) | |
571 | { | |
572 | if (frameless_p) | |
573 | { | |
574 | return ip; | |
575 | } | |
576 | regsave = cris_get_operand2 (insn_next); | |
577 | } | |
578 | else | |
579 | { | |
580 | /* The prologue ended before the limit was reached. */ | |
581 | ip -= 2 * sizeof (short); | |
582 | break; | |
583 | } | |
584 | } | |
585 | else if (cris_get_mode (insn) == 0x0001 | |
586 | && cris_get_opcode (insn) == 0x0009 | |
587 | && cris_get_size (insn) == 0x0002) | |
588 | { | |
589 | /* move.d r<10..13>,r<0..15> */ | |
590 | if (frameless_p) | |
591 | { | |
592 | return ip; | |
593 | } | |
594 | source_register = cris_get_operand1 (insn); | |
2a9ecef2 OF |
595 | |
596 | /* FIXME? In the glibc solibs, the prologue might contain something | |
597 | like (this example taken from relocate_doit): | |
598 | move.d $pc,$r0 | |
599 | sub.d 0xfffef426,$r0 | |
600 | which isn't covered by the source_register check below. Question | |
601 | is whether to add a check for this combo, or make better use of | |
602 | the limit variable instead. */ | |
29134980 OF |
603 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
604 | { | |
605 | /* The prologue ended before the limit was reached. */ | |
606 | ip -= sizeof (short); | |
607 | break; | |
608 | } | |
609 | } | |
610 | else if (cris_get_operand2 (insn) == FP_REGNUM | |
611 | /* The size is a fixed-size. */ | |
612 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
613 | /* A negative offset. */ | |
614 | && (cris_get_signed_offset (insn) < 0)) | |
615 | { | |
616 | /* move.S rZ,[r8-U] (?) */ | |
617 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); | |
618 | ip += sizeof (short); | |
619 | regno = cris_get_operand2 (insn_next); | |
620 | if ((regno >= 0 && regno < SP_REGNUM) | |
621 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
622 | && cris_get_opcode (insn_next) == 0x000F) | |
623 | { | |
624 | /* move.S rZ,[r8-U] */ | |
625 | continue; | |
626 | } | |
627 | else | |
628 | { | |
629 | /* The prologue ended before the limit was reached. */ | |
630 | ip -= 2 * sizeof (short); | |
631 | break; | |
632 | } | |
633 | } | |
634 | else if (cris_get_operand2 (insn) == FP_REGNUM | |
635 | /* The size is a fixed-size. */ | |
636 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
637 | /* A positive offset. */ | |
638 | && (cris_get_signed_offset (insn) > 0)) | |
639 | { | |
640 | /* move.S [r8+U],rZ (?) */ | |
641 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); | |
642 | ip += sizeof (short); | |
643 | regno = cris_get_operand2 (insn_next); | |
644 | if ((regno >= 0 && regno < SP_REGNUM) | |
645 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
646 | && cris_get_opcode (insn_next) == 0x0009 | |
647 | && cris_get_operand1 (insn_next) == regno) | |
648 | { | |
649 | /* move.S [r8+U],rZ */ | |
650 | continue; | |
651 | } | |
652 | else | |
653 | { | |
654 | /* The prologue ended before the limit was reached. */ | |
655 | ip -= 2 * sizeof (short); | |
656 | break; | |
657 | } | |
658 | } | |
659 | else | |
660 | { | |
661 | /* The prologue ended before the limit was reached. */ | |
662 | ip -= sizeof (short); | |
663 | break; | |
664 | } | |
665 | } | |
666 | while (ip < limit); | |
667 | ||
668 | /* We only want to know the end of the prologue when | |
669 | fi->saved_regs == 0. */ | |
670 | if (!fi->saved_regs) | |
671 | return ip; | |
672 | ||
673 | if (have_fp) | |
674 | { | |
675 | fi->saved_regs[FP_REGNUM] = FRAME_FP (fi); | |
676 | ||
677 | /* Calculate the addresses. */ | |
678 | for (regno = regsave; regno >= 0; regno--) | |
679 | { | |
680 | fi->saved_regs[regno] = FRAME_FP (fi) - val; | |
681 | val -= 4; | |
682 | } | |
683 | if (fi->extra_info->leaf_function) | |
684 | { | |
685 | /* Set the register SP to contain the stack pointer of | |
686 | the caller. */ | |
687 | fi->saved_regs[SP_REGNUM] = FRAME_FP (fi) + 4; | |
688 | } | |
689 | else | |
690 | { | |
691 | /* Set the register SP to contain the stack pointer of | |
692 | the caller. */ | |
693 | fi->saved_regs[SP_REGNUM] = FRAME_FP (fi) + 8; | |
694 | ||
695 | /* Set the register SRP to contain the return address of | |
696 | the caller. */ | |
697 | fi->saved_regs[SRP_REGNUM] = FRAME_FP (fi) + 4; | |
698 | } | |
699 | } | |
700 | return ip; | |
701 | } | |
702 | ||
703 | /* Advance pc beyond any function entry prologue instructions at pc | |
704 | to reach some "real" code. */ | |
705 | ||
706 | CORE_ADDR | |
707 | cris_skip_prologue (CORE_ADDR pc) | |
708 | { | |
709 | return cris_skip_prologue_main (pc, 0); | |
710 | } | |
711 | ||
712 | /* As cris_skip_prologue, but stops as soon as it knows that the function | |
713 | has a frame. Its result is equal to its input pc if the function is | |
714 | frameless, unequal otherwise. */ | |
715 | ||
716 | CORE_ADDR | |
717 | cris_skip_prologue_frameless_p (CORE_ADDR pc) | |
718 | { | |
719 | return cris_skip_prologue_main (pc, 1); | |
720 | } | |
721 | ||
722 | /* Given a PC value corresponding to the start of a function, return the PC | |
723 | of the first instruction after the function prologue. */ | |
724 | ||
725 | CORE_ADDR | |
726 | cris_skip_prologue_main (CORE_ADDR pc, int frameless_p) | |
727 | { | |
728 | struct frame_info fi; | |
729 | static struct frame_extra_info fei; | |
730 | struct symtab_and_line sal = find_pc_line (pc, 0); | |
731 | int best_limit; | |
732 | CORE_ADDR pc_after_prologue; | |
733 | ||
734 | /* frame_info now contains dynamic memory. Since fi is a dummy here, | |
735 | I use static memory for extra_info, and don't bother allocating | |
736 | memory for saved_regs. */ | |
737 | fi.saved_regs = 0; | |
738 | fi.extra_info = &fei; | |
739 | ||
740 | /* If there is no symbol information then sal.end == 0, and we end up | |
741 | examining only the first instruction in the function prologue. | |
742 | Exaggerating the limit seems to be harmless. */ | |
743 | if (sal.end > 0) | |
744 | best_limit = sal.end; | |
745 | else | |
746 | best_limit = pc + 100; | |
747 | ||
748 | pc_after_prologue = cris_examine (pc, best_limit, &fi, frameless_p); | |
749 | return pc_after_prologue; | |
750 | } | |
751 | ||
752 | /* Use the program counter to determine the contents and size of a breakpoint | |
753 | instruction. It returns a pointer to a string of bytes that encode a | |
754 | breakpoint instruction, stores the length of the string to *lenptr, and | |
755 | adjusts pcptr (if necessary) to point to the actual memory location where | |
756 | the breakpoint should be inserted. */ | |
757 | ||
758 | unsigned char * | |
759 | cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) | |
760 | { | |
761 | static unsigned char break_insn[] = {0x38, 0xe9}; | |
762 | *lenptr = 2; | |
763 | ||
764 | return break_insn; | |
765 | } | |
766 | ||
767 | /* Returns the register SRP (subroutine return pointer) which must contain | |
768 | the content of the register PC after a function call. */ | |
769 | ||
770 | CORE_ADDR | |
771 | cris_saved_pc_after_call () | |
772 | { | |
773 | return read_register (SRP_REGNUM); | |
774 | } | |
775 | ||
776 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, | |
777 | 0 otherwise. */ | |
778 | ||
779 | int | |
780 | cris_spec_reg_applicable (struct cris_spec_reg spec_reg) | |
781 | { | |
782 | int version = cris_version (); | |
783 | ||
784 | switch (spec_reg.applicable_version) | |
785 | { | |
786 | case cris_ver_version_all: | |
787 | return 1; | |
788 | case cris_ver_warning: | |
789 | /* Indeterminate/obsolete. */ | |
790 | return 0; | |
791 | case cris_ver_sim: | |
792 | /* Simulator only. */ | |
793 | return 0; | |
794 | case cris_ver_v0_3: | |
795 | return (version >= 0 && version <= 3); | |
796 | case cris_ver_v3p: | |
797 | return (version >= 3); | |
798 | case cris_ver_v8: | |
799 | return (version == 8 || version == 9); | |
800 | case cris_ver_v8p: | |
801 | return (version >= 8); | |
802 | case cris_ver_v10p: | |
803 | return (version >= 10); | |
804 | default: | |
805 | /* Invalid cris version. */ | |
806 | return 0; | |
807 | } | |
808 | } | |
809 | ||
810 | /* Returns the register size in unit byte. Returns 0 for an unimplemented | |
811 | register, -1 for an invalid register. */ | |
812 | ||
813 | int | |
814 | cris_register_size (int regno) | |
815 | { | |
816 | int i; | |
817 | int spec_regno; | |
818 | ||
819 | if (regno >= 0 && regno < NUM_GENREGS) | |
820 | { | |
821 | /* General registers (R0 - R15) are 32 bits. */ | |
822 | return 4; | |
823 | } | |
824 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) | |
825 | { | |
826 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
827 | Adjust regno accordingly. */ | |
828 | spec_regno = regno - NUM_GENREGS; | |
829 | ||
830 | /* The entries in cris_spec_regs are stored in register number order, | |
831 | which means we can shortcut into the array when searching it. */ | |
832 | for (i = spec_regno; cris_spec_regs[i].name != NULL; i++) | |
833 | { | |
834 | if (cris_spec_regs[i].number == spec_regno | |
835 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
836 | /* Go with the first applicable register. */ | |
837 | return cris_spec_regs[i].reg_size; | |
838 | } | |
839 | /* Special register not applicable to this CRIS version. */ | |
840 | return 0; | |
841 | } | |
842 | else | |
843 | { | |
844 | /* Invalid register. */ | |
845 | return -1; | |
846 | } | |
847 | } | |
848 | ||
849 | /* Nonzero if regno should not be fetched from the target. This is the case | |
850 | for unimplemented (size 0) and non-existant registers. */ | |
851 | ||
852 | int | |
853 | cris_cannot_fetch_register (int regno) | |
854 | { | |
855 | return ((regno < 0 || regno >= NUM_REGS) | |
856 | || (cris_register_size (regno) == 0)); | |
857 | } | |
858 | ||
859 | /* Nonzero if regno should not be written to the target, for various | |
860 | reasons. */ | |
861 | ||
862 | int | |
863 | cris_cannot_store_register (int regno) | |
864 | { | |
865 | /* There are three kinds of registers we refuse to write to. | |
866 | 1. Those that not implemented. | |
867 | 2. Those that are read-only (depends on the processor mode). | |
868 | 3. Those registers to which a write has no effect. | |
869 | */ | |
870 | ||
871 | if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) | |
872 | /* Not implemented. */ | |
873 | return 1; | |
874 | ||
875 | else if (regno == VR_REGNUM) | |
876 | /* Read-only. */ | |
877 | return 1; | |
878 | ||
879 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
880 | /* Writing has no effect. */ | |
881 | return 1; | |
882 | ||
883 | else if (cris_mode () == CRIS_MODE_USER) | |
884 | { | |
885 | if (regno == IBR_REGNUM || regno == BAR_REGNUM || regno == BRP_REGNUM | |
886 | || regno == IRP_REGNUM) | |
887 | /* Read-only in user mode. */ | |
888 | return 1; | |
889 | } | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
894 | /* Returns the register offset for the first byte of register regno's space | |
895 | in the saved register state. Returns -1 for an invalid or unimplemented | |
896 | register. */ | |
897 | ||
898 | int | |
899 | cris_register_offset (int regno) | |
900 | { | |
901 | int i; | |
902 | int reg_size; | |
903 | int offset = 0; | |
904 | ||
905 | if (regno >= 0 && regno < NUM_REGS) | |
906 | { | |
907 | /* FIXME: The offsets should be cached and calculated only once, | |
908 | when the architecture being debugged has changed. */ | |
909 | for (i = 0; i < regno; i++) | |
910 | offset += cris_register_size (i); | |
911 | ||
912 | return offset; | |
913 | } | |
914 | else | |
915 | { | |
916 | /* Invalid register. */ | |
917 | return -1; | |
918 | } | |
919 | } | |
920 | ||
921 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type | |
922 | of data in register regno. */ | |
923 | ||
924 | struct type * | |
925 | cris_register_virtual_type (int regno) | |
926 | { | |
927 | if (regno == SP_REGNUM || regno == PC_REGNUM | |
928 | || (regno > P8_REGNUM && regno < USP_REGNUM)) | |
929 | { | |
930 | /* SP, PC, IBR, IRP, SRP, BAR, DCCR, BRP */ | |
931 | return lookup_pointer_type (builtin_type_void); | |
932 | } | |
933 | else if (regno == P8_REGNUM || regno == USP_REGNUM | |
934 | || (regno >= 0 && regno < SP_REGNUM)) | |
935 | { | |
936 | /* R0 - R13, P8, P15 */ | |
937 | return builtin_type_unsigned_long; | |
938 | } | |
939 | else if (regno > P3_REGNUM && regno < P8_REGNUM) | |
940 | { | |
941 | /* P4, CCR, DCR0, DCR1 */ | |
942 | return builtin_type_unsigned_short; | |
943 | } | |
944 | else if (regno > PC_REGNUM && regno < P4_REGNUM) | |
945 | { | |
946 | /* P0, P1, P2, P3 */ | |
947 | return builtin_type_unsigned_char; | |
948 | } | |
949 | else | |
950 | { | |
951 | /* Invalid register. */ | |
952 | return builtin_type_void; | |
953 | } | |
954 | } | |
955 | ||
956 | /* Stores a function return value of type type, where valbuf is the address | |
957 | of the value to be stored. */ | |
958 | ||
959 | /* In the original CRIS ABI, R10 is used to store return values. */ | |
960 | ||
961 | void | |
962 | cris_abi_original_store_return_value (struct type *type, char *valbuf) | |
963 | { | |
964 | int len = TYPE_LENGTH (type); | |
965 | ||
966 | if (len <= REGISTER_SIZE) | |
967 | write_register_bytes (REGISTER_BYTE (RET_REGNUM), valbuf, len); | |
968 | else | |
969 | internal_error (__FILE__, __LINE__, "cris_abi_original_store_return_value: type length too large."); | |
970 | } | |
971 | ||
972 | /* In the CRIS ABI V2, R10 and R11 are used to store return values. */ | |
973 | ||
974 | void | |
975 | cris_abi_v2_store_return_value (struct type *type, char *valbuf) | |
976 | { | |
977 | int len = TYPE_LENGTH (type); | |
978 | ||
979 | if (len <= 2 * REGISTER_SIZE) | |
980 | { | |
981 | /* Note that this works since R10 and R11 are consecutive registers. */ | |
982 | write_register_bytes (REGISTER_BYTE (RET_REGNUM), valbuf, len); | |
983 | } | |
984 | else | |
985 | internal_error (__FILE__, __LINE__, "cris_abi_v2_store_return_value: type length too large."); | |
986 | } | |
987 | ||
988 | /* Return the name of register regno as a string. Return NULL for an invalid or | |
989 | unimplemented register. */ | |
990 | ||
991 | char * | |
992 | cris_register_name (int regno) | |
993 | { | |
994 | static char *cris_genreg_names[] = | |
995 | { "r0", "r1", "r2", "r3", \ | |
996 | "r4", "r5", "r6", "r7", \ | |
997 | "r8", "r9", "r10", "r11", \ | |
998 | "r12", "r13", "sp", "pc" }; | |
999 | ||
1000 | int i; | |
1001 | int spec_regno; | |
1002 | ||
1003 | if (regno >= 0 && regno < NUM_GENREGS) | |
1004 | { | |
1005 | /* General register. */ | |
1006 | return cris_genreg_names[regno]; | |
1007 | } | |
1008 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) | |
1009 | { | |
1010 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1011 | Adjust regno accordingly. */ | |
1012 | spec_regno = regno - NUM_GENREGS; | |
1013 | ||
1014 | /* The entries in cris_spec_regs are stored in register number order, | |
1015 | which means we can shortcut into the array when searching it. */ | |
1016 | for (i = spec_regno; cris_spec_regs[i].name != NULL; i++) | |
1017 | { | |
1018 | if (cris_spec_regs[i].number == spec_regno | |
1019 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1020 | /* Go with the first applicable register. */ | |
1021 | return cris_spec_regs[i].name; | |
1022 | } | |
1023 | /* Special register not applicable to this CRIS version. */ | |
1024 | return NULL; | |
1025 | } | |
1026 | else | |
1027 | { | |
1028 | /* Invalid register. */ | |
1029 | return NULL; | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | int | |
1034 | cris_register_bytes_ok (long bytes) | |
1035 | { | |
1036 | return (bytes == REGISTER_BYTES); | |
1037 | } | |
1038 | ||
1039 | /* Extract from an array regbuf containing the raw register state a function | |
1040 | return value of type type, and copy that, in virtual format, into | |
1041 | valbuf. */ | |
1042 | ||
1043 | /* In the original CRIS ABI, R10 is used to return values. */ | |
1044 | ||
1045 | void | |
1046 | cris_abi_original_extract_return_value (struct type *type, char *regbuf, | |
1047 | char *valbuf) | |
1048 | { | |
1049 | int len = TYPE_LENGTH (type); | |
1050 | ||
1051 | if (len <= REGISTER_SIZE) | |
1052 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET_REGNUM), len); | |
1053 | else | |
1054 | internal_error (__FILE__, __LINE__, "cris_abi_original_extract_return_value: type length too large"); | |
1055 | } | |
1056 | ||
1057 | /* In the CRIS ABI V2, R10 and R11 are used to store return values. */ | |
1058 | ||
1059 | void | |
1060 | cris_abi_v2_extract_return_value (struct type *type, char *regbuf, | |
1061 | char *valbuf) | |
1062 | { | |
1063 | int len = TYPE_LENGTH (type); | |
1064 | ||
1065 | if (len <= 2 * REGISTER_SIZE) | |
1066 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET_REGNUM), len); | |
1067 | else | |
1068 | internal_error (__FILE__, __LINE__, "cris_abi_v2_extract_return_value: type length too large"); | |
1069 | } | |
1070 | ||
1071 | /* Store the address of the place in which to copy the structure the | |
1072 | subroutine will return. In the CRIS ABI, R9 is used in order to pass | |
1073 | the address of the allocated area where a structure return value must | |
1074 | be stored. R9 is call-clobbered, which means we must save it here for | |
1075 | later use. */ | |
1076 | ||
1077 | void | |
1078 | cris_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
1079 | { | |
1080 | write_register (STR_REGNUM, addr); | |
1081 | struct_return_address = addr; | |
1082 | } | |
1083 | ||
1084 | /* Extract from regbuf the address where a function should return a | |
1085 | structure value. It's not there in the CRIS ABI, so we must do it another | |
1086 | way. */ | |
1087 | ||
1088 | CORE_ADDR | |
1089 | cris_extract_struct_value_address (char *regbuf) | |
1090 | { | |
1091 | return struct_return_address; | |
1092 | } | |
1093 | ||
1094 | /* Returns 1 if a value of the given type being returned from a function | |
1095 | must have space allocated for it on the stack. gcc_p is true if the | |
1096 | function being considered is known to have been compiled by GCC. | |
1097 | In the CRIS ABI, structure return values are passed to the called | |
1098 | function by reference in register R9 to a caller-allocated area, so | |
1099 | this is always true. */ | |
1100 | ||
1101 | int | |
1102 | cris_use_struct_convention (int gcc_p, struct type *type) | |
1103 | { | |
1104 | return 1; | |
1105 | } | |
1106 | ||
1107 | /* Returns 1 if the given type will be passed by pointer rather than | |
1108 | directly. */ | |
1109 | ||
1110 | /* In the original CRIS ABI, arguments shorter than or equal to 32 bits are | |
1111 | passed by value. */ | |
1112 | ||
1113 | int | |
1114 | cris_abi_original_reg_struct_has_addr (int gcc_p, struct type *type) | |
1115 | { | |
1116 | return (TYPE_LENGTH (type) > 4); | |
1117 | } | |
1118 | ||
1119 | /* In the CRIS ABI V2, arguments shorter than or equal to 64 bits are passed | |
1120 | by value. */ | |
1121 | ||
1122 | int | |
1123 | cris_abi_v2_reg_struct_has_addr (int gcc_p, struct type *type) | |
1124 | { | |
1125 | return (TYPE_LENGTH (type) > 8); | |
1126 | } | |
1127 | ||
1128 | /* Returns 1 if the function invocation represented by fi does not have a | |
1129 | stack frame associated with it. Otherwise return 0. */ | |
1130 | ||
1131 | int | |
1132 | cris_frameless_function_invocation (struct frame_info *fi) | |
1133 | { | |
1134 | if (fi->signal_handler_caller) | |
1135 | return 0; | |
1136 | else | |
1137 | return frameless_look_for_prologue (fi); | |
1138 | } | |
1139 | ||
1140 | /* See frame.h. Determines the address of all registers in the current stack | |
1141 | frame storing each in frame->saved_regs. Space for frame->saved_regs shall | |
1142 | be allocated by FRAME_INIT_SAVED_REGS using either frame_saved_regs_zalloc | |
1143 | or frame_obstack_alloc. */ | |
1144 | ||
1145 | void | |
1146 | cris_frame_init_saved_regs (struct frame_info *fi) | |
1147 | { | |
1148 | CORE_ADDR ip; | |
1149 | struct symtab_and_line sal; | |
1150 | int best_limit; | |
1151 | char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame); | |
1152 | ||
1153 | /* Examine the entire prologue. */ | |
1154 | register int frameless_p = 0; | |
1155 | ||
1156 | /* Has this frame's registers already been initialized? */ | |
1157 | if (fi->saved_regs) | |
1158 | return; | |
1159 | ||
1160 | frame_saved_regs_zalloc (fi); | |
1161 | ||
1162 | if (dummy_regs) | |
1163 | { | |
1164 | /* I don't see this ever happening, considering the context in which | |
1165 | cris_frame_init_saved_regs is called (always when we're not in | |
1166 | a dummy frame). */ | |
1167 | memcpy (&fi->saved_regs, dummy_regs, sizeof (fi->saved_regs)); | |
1168 | } | |
1169 | else | |
1170 | { | |
1171 | ip = get_pc_function_start (fi->pc); | |
1172 | sal = find_pc_line (ip, 0); | |
1173 | ||
1174 | /* If there is no symbol information then sal.end == 0, and we end up | |
1175 | examining only the first instruction in the function prologue. | |
1176 | Exaggerating the limit seems to be harmless. */ | |
1177 | if (sal.end > 0) | |
1178 | best_limit = sal.end; | |
1179 | else | |
1180 | best_limit = ip + 100; | |
1181 | ||
1182 | cris_examine (ip, best_limit, fi, frameless_p); | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | /* Initialises the extra frame information at the creation of a new frame. | |
1187 | The inparameter fromleaf is 0 when the call is from create_new_frame. | |
1188 | When the call is from get_prev_frame_info, fromleaf is determined by | |
1189 | cris_frameless_function_invocation. */ | |
1190 | ||
1191 | void | |
1192 | cris_init_extra_frame_info (int fromleaf, struct frame_info *fi) | |
1193 | { | |
1194 | if (fi->next) | |
1195 | { | |
1196 | /* Called from get_prev_frame. */ | |
1197 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1198 | } | |
1199 | ||
1200 | fi->extra_info = (struct frame_extra_info *) | |
1201 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1202 | ||
1203 | fi->extra_info->return_pc = 0; | |
1204 | fi->extra_info->leaf_function = 0; | |
1205 | ||
1206 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
1207 | { | |
1208 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
1209 | by assuming it's always FP. */ | |
1210 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); | |
1211 | fi->extra_info->return_pc = | |
1212 | generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); | |
1213 | ||
1214 | /* FIXME: Is this necessarily true? */ | |
1215 | fi->extra_info->leaf_function = 0; | |
1216 | } | |
1217 | else | |
1218 | { | |
1219 | cris_frame_init_saved_regs (fi); | |
1220 | ||
1221 | /* Check fromleaf/frameless_function_invocation. (FIXME) */ | |
1222 | ||
1223 | if (fi->saved_regs[SRP_REGNUM] != 0) | |
1224 | { | |
1225 | /* SRP was saved on the stack; non-leaf function. */ | |
1226 | fi->extra_info->return_pc = | |
1227 | read_memory_integer (fi->saved_regs[SRP_REGNUM], | |
1228 | REGISTER_RAW_SIZE (SRP_REGNUM)); | |
1229 | } | |
1230 | else | |
1231 | { | |
1232 | /* SRP is still in a register; leaf function. */ | |
1233 | fi->extra_info->return_pc = read_register (SRP_REGNUM); | |
1234 | /* FIXME: Should leaf_function be set to 1 here? */ | |
1235 | fi->extra_info->leaf_function = 1; | |
1236 | } | |
1237 | } | |
1238 | } | |
1239 | ||
1240 | /* Return the content of the frame pointer in the present frame. In other | |
1241 | words, determine the address of the calling function's frame. */ | |
1242 | ||
1243 | CORE_ADDR | |
1244 | cris_frame_chain (struct frame_info *fi) | |
1245 | { | |
1246 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
1247 | { | |
1248 | return fi->frame; | |
1249 | } | |
1250 | else if (!inside_entry_file (fi->pc)) | |
1251 | { | |
1252 | return read_memory_unsigned_integer (FRAME_FP (fi), 4); | |
1253 | } | |
1254 | else | |
1255 | { | |
1256 | return 0; | |
1257 | } | |
1258 | } | |
1259 | ||
1260 | /* Return the saved PC (which equals the return address) of this frame. */ | |
1261 | ||
1262 | CORE_ADDR | |
1263 | cris_frame_saved_pc (struct frame_info *fi) | |
1264 | { | |
1265 | return fi->extra_info->return_pc; | |
1266 | } | |
1267 | ||
1268 | /* Return the address of the argument block for the frame described | |
1269 | by struct frame_info. */ | |
1270 | ||
1271 | CORE_ADDR | |
1272 | cris_frame_args_address (struct frame_info *fi) | |
1273 | { | |
1274 | return FRAME_FP (fi); | |
1275 | } | |
1276 | ||
1277 | /* Return the address of the locals block for the frame | |
1278 | described by struct frame_info. */ | |
1279 | ||
1280 | CORE_ADDR | |
1281 | cris_frame_locals_address (struct frame_info *fi) | |
1282 | { | |
1283 | return FRAME_FP (fi); | |
1284 | } | |
1285 | ||
1286 | /* Setup the function arguments for calling a function in the inferior. */ | |
1287 | ||
1288 | CORE_ADDR | |
1289 | cris_abi_original_push_arguments (int nargs, struct value **args, | |
1290 | CORE_ADDR sp, int struct_return, | |
1291 | CORE_ADDR struct_addr) | |
1292 | { | |
1293 | int stack_alloc; | |
1294 | int stack_offset; | |
1295 | int argreg; | |
1296 | int argnum; | |
1297 | struct type *type; | |
1298 | int len; | |
1299 | CORE_ADDR regval; | |
1300 | char *val; | |
1301 | ||
1302 | /* Data and parameters reside in different areas on the stack. | |
1303 | Both frame pointers grow toward higher addresses. */ | |
1304 | CORE_ADDR fp_params; | |
1305 | CORE_ADDR fp_data; | |
1306 | ||
1307 | /* Are we returning a value using a structure return or a normal value | |
1308 | return? struct_addr is the address of the reserved space for the return | |
1309 | structure to be written on the stack. */ | |
1310 | if (struct_return) | |
1311 | { | |
1312 | write_register (STR_REGNUM, struct_addr); | |
1313 | } | |
1314 | ||
1315 | /* Make sure there's space on the stack. Allocate space for data and a | |
1316 | parameter to refer to that data. */ | |
1317 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
1318 | stack_alloc += (TYPE_LENGTH (VALUE_TYPE (args[argnum])) + REGISTER_SIZE); | |
1319 | sp -= stack_alloc; | |
1320 | /* We may over-allocate a little here, but that won't hurt anything. */ | |
1321 | ||
1322 | /* Initialize stack frame pointers. */ | |
1323 | fp_params = sp; | |
1324 | fp_data = sp + (nargs * REGISTER_SIZE); | |
1325 | ||
1326 | /* Now load as many as possible of the first arguments into | |
1327 | registers, and push the rest onto the stack. */ | |
1328 | argreg = ARG1_REGNUM; | |
1329 | stack_offset = 0; | |
1330 | ||
1331 | for (argnum = 0; argnum < nargs; argnum++) | |
1332 | { | |
1333 | type = VALUE_TYPE (args[argnum]); | |
1334 | len = TYPE_LENGTH (type); | |
1335 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1336 | ||
1337 | if (len <= REGISTER_SIZE && argreg <= ARG4_REGNUM) | |
1338 | { | |
1339 | /* Data fits in a register; put it in the first available | |
1340 | register. */ | |
1341 | write_register (argreg, *(unsigned long *) val); | |
1342 | argreg++; | |
1343 | } | |
1344 | else if (len > REGISTER_SIZE && argreg <= ARG4_REGNUM) | |
1345 | { | |
1346 | /* Data does not fit in register; pass it on the stack and | |
1347 | put its address in the first available register. */ | |
1348 | write_memory (fp_data, val, len); | |
1349 | write_register (argreg, fp_data); | |
1350 | fp_data += len; | |
1351 | argreg++; | |
1352 | } | |
1353 | else if (len > REGISTER_SIZE) | |
1354 | { | |
1355 | /* Data does not fit in register; put both data and | |
1356 | parameter on the stack. */ | |
1357 | write_memory (fp_data, val, len); | |
1358 | write_memory (fp_params, (char *) (&fp_data), REGISTER_SIZE); | |
1359 | fp_data += len; | |
1360 | fp_params += REGISTER_SIZE; | |
1361 | } | |
1362 | else | |
1363 | { | |
1364 | /* Data fits in a register, but we are out of registers; | |
1365 | put the parameter on the stack. */ | |
1366 | write_memory (fp_params, val, REGISTER_SIZE); | |
1367 | fp_params += REGISTER_SIZE; | |
1368 | } | |
1369 | } | |
1370 | ||
1371 | return sp; | |
1372 | } | |
1373 | ||
1374 | CORE_ADDR | |
1375 | cris_abi_v2_push_arguments (int nargs, struct value **args, CORE_ADDR sp, | |
1376 | int struct_return, CORE_ADDR struct_addr) | |
1377 | { | |
1378 | int stack_alloc; | |
1379 | int stack_offset; | |
1380 | int argreg; | |
1381 | int argnum; | |
1382 | ||
1383 | CORE_ADDR regval; | |
1384 | ||
1385 | /* The function's arguments and memory allocated by gdb for the arguments to | |
1386 | point at reside in separate areas on the stack. | |
1387 | Both frame pointers grow toward higher addresses. */ | |
1388 | CORE_ADDR fp_arg; | |
1389 | CORE_ADDR fp_mem; | |
1390 | ||
1391 | /* Are we returning a value using a structure return or a normal value | |
1392 | return? struct_addr is the address of the reserved space for the return | |
1393 | structure to be written on the stack. */ | |
1394 | if (struct_return) | |
1395 | { | |
1396 | write_register (STR_REGNUM, struct_addr); | |
1397 | } | |
1398 | ||
1399 | /* Allocate enough to keep things word-aligned on both parts of the | |
1400 | stack. */ | |
1401 | stack_alloc = 0; | |
1402 | for (argnum = 0; argnum < nargs; argnum++) | |
1403 | { | |
1404 | int len; | |
1405 | int reg_demand; | |
1406 | ||
1407 | len = TYPE_LENGTH (VALUE_TYPE (args[argnum])); | |
1408 | reg_demand = (len / REGISTER_SIZE) + (len % REGISTER_SIZE != 0 ? 1 : 0); | |
1409 | ||
1410 | /* reg_demand * REGISTER_SIZE is the amount of memory we might need to | |
1411 | allocate for this argument. 2 * REGISTER_SIZE is the amount of stack | |
1412 | space we might need to pass the argument itself (either by value or by | |
1413 | reference). */ | |
1414 | stack_alloc += (reg_demand * REGISTER_SIZE + 2 * REGISTER_SIZE); | |
1415 | } | |
1416 | sp -= stack_alloc; | |
1417 | /* We may over-allocate a little here, but that won't hurt anything. */ | |
1418 | ||
1419 | /* Initialize frame pointers. */ | |
1420 | fp_arg = sp; | |
1421 | fp_mem = sp + (nargs * (2 * REGISTER_SIZE)); | |
1422 | ||
1423 | /* Now load as many as possible of the first arguments into registers, | |
1424 | and push the rest onto the stack. */ | |
1425 | argreg = ARG1_REGNUM; | |
1426 | stack_offset = 0; | |
1427 | ||
1428 | for (argnum = 0; argnum < nargs; argnum++) | |
1429 | { | |
1430 | int len; | |
1431 | char *val; | |
1432 | int reg_demand; | |
1433 | int i; | |
1434 | ||
1435 | len = TYPE_LENGTH (VALUE_TYPE (args[argnum])); | |
1436 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1437 | ||
1438 | /* How may registers worth of storage do we need for this argument? */ | |
1439 | reg_demand = (len / REGISTER_SIZE) + (len % REGISTER_SIZE != 0 ? 1 : 0); | |
1440 | ||
1441 | if (len <= (2 * REGISTER_SIZE) | |
1442 | && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
1443 | { | |
1444 | /* Data passed by value. Fits in available register(s). */ | |
1445 | for (i = 0; i < reg_demand; i++) | |
1446 | { | |
1447 | write_register (argreg, *(unsigned long *) val); | |
1448 | argreg++; | |
1449 | val += REGISTER_SIZE; | |
1450 | } | |
1451 | } | |
1452 | else if (len <= (2 * REGISTER_SIZE) && argreg <= ARG4_REGNUM) | |
1453 | { | |
1454 | /* Data passed by value. Does not fit in available register(s). | |
1455 | Use the register(s) first, then the stack. */ | |
1456 | for (i = 0; i < reg_demand; i++) | |
1457 | { | |
1458 | if (argreg <= ARG4_REGNUM) | |
1459 | { | |
1460 | write_register (argreg, *(unsigned long *) val); | |
1461 | argreg++; | |
1462 | val += REGISTER_SIZE; | |
1463 | } | |
1464 | else | |
1465 | { | |
1466 | /* I guess this memory write could write the remaining data | |
1467 | all at once instead of in REGISTER_SIZE chunks. */ | |
1468 | write_memory (fp_arg, val, REGISTER_SIZE); | |
1469 | fp_arg += REGISTER_SIZE; | |
1470 | val += REGISTER_SIZE; | |
1471 | } | |
1472 | } | |
1473 | } | |
1474 | else if (len > (2 * REGISTER_SIZE)) | |
1475 | { | |
1476 | /* Data passed by reference. Put it on the stack. */ | |
1477 | write_memory (fp_mem, val, len); | |
1478 | write_memory (fp_arg, (char *) (&fp_mem), REGISTER_SIZE); | |
1479 | ||
1480 | /* fp_mem need not be word-aligned since it's just a chunk of | |
1481 | memory being pointed at. That is, += len would do. */ | |
1482 | fp_mem += reg_demand * REGISTER_SIZE; | |
1483 | fp_arg += REGISTER_SIZE; | |
1484 | } | |
1485 | else | |
1486 | { | |
1487 | /* Data passed by value. No available registers. Put it on | |
1488 | the stack. */ | |
1489 | write_memory (fp_arg, val, len); | |
1490 | ||
1491 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
1492 | the function prologue. */ | |
1493 | fp_arg += reg_demand * REGISTER_SIZE; | |
1494 | } | |
1495 | } | |
1496 | ||
1497 | return sp; | |
1498 | } | |
1499 | ||
1500 | /* Never put the return address on the stack. The register SRP is pushed | |
1501 | by the called function unless it is a leaf-function. Due to the BRP | |
1502 | register the PC will change when continue is sent. */ | |
1503 | ||
1504 | CORE_ADDR | |
1505 | cris_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1506 | { | |
1507 | write_register (SRP_REGNUM, CALL_DUMMY_ADDRESS ()); | |
1508 | return sp; | |
1509 | } | |
1510 | ||
1511 | /* Restore the machine to the state it had before the current frame | |
1512 | was created. Discard the innermost frame from the stack and restore | |
1513 | all saved registers. */ | |
1514 | ||
1515 | void | |
1516 | cris_pop_frame () | |
1517 | { | |
1518 | register struct frame_info *fi = get_current_frame (); | |
1519 | register int regno; | |
1520 | register int stack_offset = 0; | |
1521 | ||
1522 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
1523 | { | |
1524 | /* This happens when we hit a breakpoint set at the entry point, | |
1525 | when returning from a dummy frame. */ | |
1526 | generic_pop_dummy_frame (); | |
1527 | } | |
1528 | else | |
1529 | { | |
1530 | cris_frame_init_saved_regs (fi); | |
1531 | ||
1532 | /* For each register, the address of where it was saved on entry to | |
1533 | the frame now lies in fi->saved_regs[regno], or zero if it was not | |
1534 | saved. This includes special registers such as PC and FP saved in | |
1535 | special ways in the stack frame. The SP_REGNUM is even more | |
1536 | special, the address here is the SP for the next frame, not the | |
1537 | address where the SP was saved. */ | |
1538 | ||
1539 | /* Restore general registers R0 - R7. They were pushed on the stack | |
1540 | after SP was saved. */ | |
1541 | for (regno = 0; regno < FP_REGNUM; regno++) | |
1542 | { | |
1543 | if (fi->saved_regs[regno]) | |
1544 | { | |
1545 | write_register (regno, | |
1546 | read_memory_integer (fi->saved_regs[regno], 4)); | |
1547 | } | |
1548 | } | |
1549 | ||
1550 | if (fi->saved_regs[FP_REGNUM]) | |
1551 | { | |
1552 | /* Pop the frame pointer (R8). It was pushed before SP | |
1553 | was saved. */ | |
1554 | write_register (FP_REGNUM, | |
1555 | read_memory_integer (fi->saved_regs[FP_REGNUM], 4)); | |
1556 | stack_offset += 4; | |
1557 | ||
1558 | /* Not a leaf function. */ | |
1559 | if (fi->saved_regs[SRP_REGNUM]) | |
1560 | { | |
1561 | /* SRP was pushed before SP was saved. */ | |
1562 | stack_offset += 4; | |
1563 | } | |
1564 | ||
1565 | /* Restore the SP and adjust for R8 and (possibly) SRP. */ | |
1566 | write_register (SP_REGNUM, fi->saved_regs[FP_REGNUM] + stack_offset); | |
1567 | } | |
1568 | else | |
1569 | { | |
1570 | /* Currently, we can't get the correct info into fi->saved_regs | |
1571 | without a frame pointer. */ | |
1572 | } | |
1573 | ||
1574 | /* Restore the PC. */ | |
1575 | write_register (PC_REGNUM, fi->extra_info->return_pc); | |
1576 | } | |
1577 | flush_cached_frames (); | |
1578 | } | |
1579 | ||
1580 | /* Calculates a value that measures how good inst_args constraints an | |
1581 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1582 | ||
1583 | static int | |
1584 | constraint (unsigned int insn, const signed char *inst_args, | |
1585 | inst_env_type *inst_env) | |
1586 | { | |
1587 | int retval = 0; | |
1588 | int tmp, i; | |
1589 | ||
1590 | const char *s = inst_args; | |
1591 | ||
1592 | for (; *s; s++) | |
1593 | switch (*s) | |
1594 | { | |
1595 | case 'm': | |
1596 | if ((insn & 0x30) == 0x30) | |
1597 | return -1; | |
1598 | break; | |
1599 | ||
1600 | case 'S': | |
1601 | /* A prefix operand. */ | |
1602 | if (inst_env->prefix_found) | |
1603 | break; | |
1604 | else | |
1605 | return -1; | |
1606 | ||
1607 | case 'B': | |
1608 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1609 | valid "push" size. In case of special register, it may be != 4. */ | |
1610 | if (inst_env->prefix_found) | |
1611 | break; | |
1612 | else | |
1613 | return -1; | |
1614 | ||
1615 | case 'D': | |
1616 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1617 | if (!retval) | |
1618 | return -1; | |
1619 | else | |
1620 | retval += 4; | |
1621 | break; | |
1622 | ||
1623 | case 'P': | |
1624 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1625 | |
1626 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1627 | { | |
1628 | /* Since we match four bits, we will give a value of | |
1629 | 4 - 1 = 3 in a match. If there is a corresponding | |
1630 | exact match of a special register in another pattern, it | |
1631 | will get a value of 4, which will be higher. This should | |
1632 | be correct in that an exact pattern would match better that | |
1633 | a general pattern. | |
1634 | Note that there is a reason for not returning zero; the | |
1635 | pattern for "clear" is partly matched in the bit-pattern | |
1636 | (the two lower bits must be zero), while the bit-pattern | |
1637 | for a move from a special register is matched in the | |
1638 | register constraint. | |
1639 | This also means we will will have a race condition if | |
1640 | there is a partly match in three bits in the bit pattern. */ | |
1641 | if (tmp == cris_spec_regs[i].number) | |
1642 | { | |
1643 | retval += 3; | |
1644 | break; | |
1645 | } | |
1646 | } | |
1647 | ||
1648 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
1649 | return -1; |
1650 | break; | |
1651 | } | |
1652 | return retval; | |
1653 | } | |
1654 | ||
1655 | /* Returns the number of bits set in the variable value. */ | |
1656 | ||
1657 | static int | |
1658 | number_of_bits (unsigned int value) | |
1659 | { | |
1660 | int number_of_bits = 0; | |
1661 | ||
1662 | while (value != 0) | |
1663 | { | |
1664 | number_of_bits += 1; | |
1665 | value &= (value - 1); | |
1666 | } | |
1667 | return number_of_bits; | |
1668 | } | |
1669 | ||
1670 | /* Finds the address that should contain the single step breakpoint(s). | |
1671 | It stems from code in cris-dis.c. */ | |
1672 | ||
1673 | static int | |
1674 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
1675 | { | |
1676 | int i; | |
1677 | int max_level_of_match = -1; | |
1678 | int max_matched = -1; | |
1679 | int level_of_match; | |
1680 | ||
1681 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
1682 | { | |
1683 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
1684 | && ((cris_opcodes[i].lose & insn) == 0)) | |
1685 | { | |
1686 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
1687 | if (level_of_match >= 0) | |
1688 | { | |
1689 | level_of_match += | |
1690 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
1691 | if (level_of_match > max_level_of_match) | |
1692 | { | |
1693 | max_matched = i; | |
1694 | max_level_of_match = level_of_match; | |
1695 | if (level_of_match == 16) | |
1696 | { | |
1697 | /* All bits matched, cannot find better. */ | |
1698 | break; | |
1699 | } | |
1700 | } | |
1701 | } | |
1702 | } | |
1703 | } | |
1704 | return max_matched; | |
1705 | } | |
1706 | ||
1707 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
1708 | actually an internal error. */ | |
1709 | ||
1710 | static int | |
1711 | find_step_target (inst_env_type *inst_env) | |
1712 | { | |
1713 | int i; | |
1714 | int offset; | |
1715 | unsigned short insn; | |
1716 | ||
1717 | /* Create a local register image and set the initial state. */ | |
1718 | for (i = 0; i < NUM_GENREGS; i++) | |
1719 | { | |
1720 | inst_env->reg[i] = (unsigned long) read_register (i); | |
1721 | } | |
1722 | offset = NUM_GENREGS; | |
1723 | for (i = 0; i < NUM_SPECREGS; i++) | |
1724 | { | |
1725 | inst_env->preg[i] = (unsigned long) read_register (offset + i); | |
1726 | } | |
1727 | inst_env->branch_found = 0; | |
1728 | inst_env->slot_needed = 0; | |
1729 | inst_env->delay_slot_pc_active = 0; | |
1730 | inst_env->prefix_found = 0; | |
1731 | inst_env->invalid = 0; | |
1732 | inst_env->xflag_found = 0; | |
1733 | inst_env->disable_interrupt = 0; | |
1734 | ||
1735 | /* Look for a step target. */ | |
1736 | do | |
1737 | { | |
1738 | /* Read an instruction from the client. */ | |
1739 | insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2); | |
1740 | ||
1741 | /* If the instruction is not in a delay slot the new content of the | |
1742 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
1743 | that simple. Since a instruction in a delay slot cannot change | |
1744 | the content of the PC, it does not matter what value PC will have. | |
1745 | Just make sure it is a valid instruction. */ | |
1746 | if (!inst_env->delay_slot_pc_active) | |
1747 | { | |
1748 | inst_env->reg[PC_REGNUM] += 2; | |
1749 | } | |
1750 | else | |
1751 | { | |
1752 | inst_env->delay_slot_pc_active = 0; | |
1753 | inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc; | |
1754 | } | |
1755 | /* Analyse the present instruction. */ | |
1756 | i = find_cris_op (insn, inst_env); | |
1757 | if (i == -1) | |
1758 | { | |
1759 | inst_env->invalid = 1; | |
1760 | } | |
1761 | else | |
1762 | { | |
1763 | cris_gdb_func (cris_opcodes[i].op, insn, inst_env); | |
1764 | } | |
1765 | } while (!inst_env->invalid | |
1766 | && (inst_env->prefix_found || inst_env->xflag_found | |
1767 | || inst_env->slot_needed)); | |
1768 | return i; | |
1769 | } | |
1770 | ||
1771 | /* There is no hardware single-step support. The function find_step_target | |
1772 | digs through the opcodes in order to find all possible targets. | |
1773 | Either one ordinary target or two targets for branches may be found. */ | |
1774 | ||
1775 | void | |
1776 | cris_software_single_step (enum target_signal ignore, int insert_breakpoints) | |
1777 | { | |
1778 | inst_env_type inst_env; | |
1779 | ||
1780 | if (insert_breakpoints) | |
1781 | { | |
1782 | /* Analyse the present instruction environment and insert | |
1783 | breakpoints. */ | |
1784 | int status = find_step_target (&inst_env); | |
1785 | if (status == -1) | |
1786 | { | |
1787 | /* Could not find a target. FIXME: Should do something. */ | |
1788 | } | |
1789 | else | |
1790 | { | |
1791 | /* Insert at most two breakpoints. One for the next PC content | |
1792 | and possibly another one for a branch, jump, etc. */ | |
1793 | next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM]; | |
1794 | target_insert_breakpoint (next_pc, break_mem[0]); | |
1795 | if (inst_env.branch_found | |
1796 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
1797 | { | |
1798 | branch_target_address = | |
1799 | (CORE_ADDR) inst_env.branch_break_address; | |
1800 | target_insert_breakpoint (branch_target_address, break_mem[1]); | |
1801 | branch_break_inserted = 1; | |
1802 | } | |
1803 | } | |
1804 | } | |
1805 | else | |
1806 | { | |
1807 | /* Remove breakpoints. */ | |
1808 | target_remove_breakpoint (next_pc, break_mem[0]); | |
1809 | if (branch_break_inserted) | |
1810 | { | |
1811 | target_remove_breakpoint (branch_target_address, break_mem[1]); | |
1812 | branch_break_inserted = 0; | |
1813 | } | |
1814 | } | |
1815 | } | |
1816 | ||
1817 | /* Calculates the prefix value for quick offset addressing mode. */ | |
1818 | ||
1819 | void | |
1820 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) | |
1821 | { | |
1822 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
1823 | instruction (not 100% sure). */ | |
1824 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1825 | { | |
1826 | inst_env->invalid = 1; | |
1827 | return; | |
1828 | } | |
1829 | ||
1830 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
1831 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
1832 | ||
1833 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
1834 | need updating. */ | |
1835 | inst_env->slot_needed = 0; | |
1836 | inst_env->prefix_found = 1; | |
1837 | } | |
1838 | ||
1839 | /* Updates the autoincrement register. The size of the increment is derived | |
1840 | from the size of the operation. The PC is always kept aligned on even | |
1841 | word addresses. */ | |
1842 | ||
1843 | void | |
1844 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) | |
1845 | { | |
1846 | if (size == INST_BYTE_SIZE) | |
1847 | { | |
1848 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
1849 | ||
1850 | /* The PC must be word aligned, so increase the PC with one | |
1851 | word even if the size is byte. */ | |
1852 | if (cris_get_operand1 (inst) == REG_PC) | |
1853 | { | |
1854 | inst_env->reg[REG_PC] += 1; | |
1855 | } | |
1856 | } | |
1857 | else if (size == INST_WORD_SIZE) | |
1858 | { | |
1859 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
1860 | } | |
1861 | else if (size == INST_DWORD_SIZE) | |
1862 | { | |
1863 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
1864 | } | |
1865 | else | |
1866 | { | |
1867 | /* Invalid size. */ | |
1868 | inst_env->invalid = 1; | |
1869 | } | |
1870 | } | |
1871 | ||
2a9ecef2 OF |
1872 | /* Just a forward declaration. */ |
1873 | ||
1874 | unsigned long | |
1875 | get_data_from_address (unsigned short *inst, CORE_ADDR address); | |
1876 | ||
29134980 OF |
1877 | /* Calculates the prefix value for the general case of offset addressing |
1878 | mode. */ | |
1879 | ||
1880 | void | |
1881 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) | |
1882 | { | |
1883 | ||
1884 | long offset; | |
1885 | ||
1886 | /* It's invalid to be in a delay slot. */ | |
1887 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1888 | { | |
1889 | inst_env->invalid = 1; | |
1890 | return; | |
1891 | } | |
1892 | ||
fa4e4598 OF |
1893 | /* The calculation of prefix_value used to be after process_autoincrement, |
1894 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
1895 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
1896 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
1897 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
1898 | ||
1899 | /* The offset is an indirection of the contents of the operand1 register. */ | |
1900 | inst_env->prefix_value += | |
2a9ecef2 OF |
1901 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]); |
1902 | ||
fa4e4598 OF |
1903 | if (cris_get_mode (inst) == AUTOINC_MODE) |
1904 | { | |
1905 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
1906 | } | |
1907 | ||
29134980 OF |
1908 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
1909 | need updating. */ | |
1910 | inst_env->slot_needed = 0; | |
1911 | inst_env->prefix_found = 1; | |
1912 | } | |
1913 | ||
1914 | /* Calculates the prefix value for the index addressing mode. */ | |
1915 | ||
1916 | void | |
1917 | biap_prefix (unsigned short inst, inst_env_type *inst_env) | |
1918 | { | |
1919 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
1920 | have a prefix to this instruction. So I will treat this as invalid. */ | |
1921 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1922 | { | |
1923 | inst_env->invalid = 1; | |
1924 | return; | |
1925 | } | |
1926 | ||
1927 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
1928 | ||
1929 | /* The offset is the operand2 value shifted the size of the instruction | |
1930 | to the left. */ | |
1931 | inst_env->prefix_value += | |
1932 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
1933 | ||
1934 | /* If the PC is operand1 (base) the address used is the address after | |
1935 | the main instruction, i.e. address + 2 (the PC is already compensated | |
1936 | for the prefix operation). */ | |
1937 | if (cris_get_operand1 (inst) == REG_PC) | |
1938 | { | |
1939 | inst_env->prefix_value += 2; | |
1940 | } | |
1941 | ||
1942 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
1943 | need updating. */ | |
1944 | inst_env->slot_needed = 0; | |
1945 | inst_env->xflag_found = 0; | |
1946 | inst_env->prefix_found = 1; | |
1947 | } | |
1948 | ||
1949 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
1950 | ||
1951 | void | |
1952 | dip_prefix (unsigned short inst, inst_env_type *inst_env) | |
1953 | { | |
1954 | ||
1955 | CORE_ADDR address; | |
1956 | ||
1957 | /* It's invalid to be in a delay slot. */ | |
1958 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1959 | { | |
1960 | inst_env->invalid = 1; | |
1961 | return; | |
1962 | } | |
1963 | ||
1964 | /* The prefix value is one dereference of the contents of the operand1 | |
1965 | register. */ | |
1966 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
1967 | inst_env->prefix_value = read_memory_unsigned_integer (address, 4); | |
1968 | ||
1969 | /* Check if the mode is autoincrement. */ | |
1970 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
1971 | { | |
1972 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
1973 | } | |
1974 | ||
1975 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
1976 | need updating. */ | |
1977 | inst_env->slot_needed = 0; | |
1978 | inst_env->xflag_found = 0; | |
1979 | inst_env->prefix_found = 1; | |
1980 | } | |
1981 | ||
1982 | /* Finds the destination for a branch with 8-bits offset. */ | |
1983 | ||
1984 | void | |
1985 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) | |
1986 | { | |
1987 | ||
1988 | short offset; | |
1989 | ||
1990 | /* If we have a prefix or are in a delay slot it's bad. */ | |
1991 | if (inst_env->slot_needed || inst_env->prefix_found) | |
1992 | { | |
1993 | inst_env->invalid = 1; | |
1994 | return; | |
1995 | } | |
1996 | ||
1997 | /* We have a branch, find out where the branch will land. */ | |
1998 | offset = cris_get_branch_short_offset (inst); | |
1999 | ||
2000 | /* Check if the offset is signed. */ | |
2001 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2002 | { | |
2003 | offset |= 0xFF00; | |
2004 | } | |
2005 | ||
2006 | /* The offset ends with the sign bit, set it to zero. The address | |
2007 | should always be word aligned. */ | |
2008 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2009 | ||
2010 | inst_env->branch_found = 1; | |
2011 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2012 | ||
2013 | inst_env->slot_needed = 1; | |
2014 | inst_env->prefix_found = 0; | |
2015 | inst_env->xflag_found = 0; | |
2016 | inst_env->disable_interrupt = 1; | |
2017 | } | |
2018 | ||
2019 | /* Finds the destination for a branch with 16-bits offset. */ | |
2020 | ||
2021 | void | |
2022 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) | |
2023 | { | |
2024 | short offset; | |
2025 | ||
2026 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2027 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2028 | { | |
2029 | inst_env->invalid = 1; | |
2030 | return; | |
2031 | } | |
2032 | ||
2033 | /* We have a branch, find out the offset for the branch. */ | |
2034 | offset = read_memory_integer (inst_env->reg[REG_PC], 2); | |
2035 | ||
2036 | /* The instruction is one word longer than normal, so add one word | |
2037 | to the PC. */ | |
2038 | inst_env->reg[REG_PC] += 2; | |
2039 | ||
2040 | inst_env->branch_found = 1; | |
2041 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2042 | ||
2043 | ||
2044 | inst_env->slot_needed = 1; | |
2045 | inst_env->prefix_found = 0; | |
2046 | inst_env->xflag_found = 0; | |
2047 | inst_env->disable_interrupt = 1; | |
2048 | } | |
2049 | ||
2050 | /* Handles the ABS instruction. */ | |
2051 | ||
2052 | void | |
2053 | abs_op (unsigned short inst, inst_env_type *inst_env) | |
2054 | { | |
2055 | ||
2056 | long value; | |
2057 | ||
2058 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2059 | if (inst_env->prefix_found) | |
2060 | { | |
2061 | inst_env->invalid = 1; | |
2062 | return; | |
2063 | } | |
2064 | ||
2065 | /* Check if the operation affects the PC. */ | |
2066 | if (cris_get_operand2 (inst) == REG_PC) | |
2067 | { | |
2068 | ||
2069 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2070 | if (inst_env->slot_needed) | |
2071 | { | |
2072 | inst_env->invalid = 1; | |
2073 | return; | |
2074 | } | |
2075 | ||
2076 | value = (long) inst_env->reg[REG_PC]; | |
2077 | ||
2078 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2079 | if (value != SIGNED_DWORD_MASK) | |
2080 | { | |
2081 | value = -value; | |
2082 | inst_env->reg[REG_PC] = (long) value; | |
2083 | } | |
2084 | } | |
2085 | ||
2086 | inst_env->slot_needed = 0; | |
2087 | inst_env->prefix_found = 0; | |
2088 | inst_env->xflag_found = 0; | |
2089 | inst_env->disable_interrupt = 0; | |
2090 | } | |
2091 | ||
2092 | /* Handles the ADDI instruction. */ | |
2093 | ||
2094 | void | |
2095 | addi_op (unsigned short inst, inst_env_type *inst_env) | |
2096 | { | |
2097 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2098 | a prefix. */ | |
2099 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2100 | { | |
2101 | inst_env->invalid = 1; | |
2102 | return; | |
2103 | } | |
2104 | ||
2105 | inst_env->slot_needed = 0; | |
2106 | inst_env->prefix_found = 0; | |
2107 | inst_env->xflag_found = 0; | |
2108 | inst_env->disable_interrupt = 0; | |
2109 | } | |
2110 | ||
2111 | /* Handles the ASR instruction. */ | |
2112 | ||
2113 | void | |
2114 | asr_op (unsigned short inst, inst_env_type *inst_env) | |
2115 | { | |
2116 | int shift_steps; | |
2117 | unsigned long value; | |
2118 | unsigned long signed_extend_mask = 0; | |
2119 | ||
2120 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2121 | if (inst_env->prefix_found) | |
2122 | { | |
2123 | inst_env->invalid = 1; | |
2124 | return; | |
2125 | } | |
2126 | ||
2127 | /* Check if the PC is the target register. */ | |
2128 | if (cris_get_operand2 (inst) == REG_PC) | |
2129 | { | |
2130 | /* It's invalid to change the PC in a delay slot. */ | |
2131 | if (inst_env->slot_needed) | |
2132 | { | |
2133 | inst_env->invalid = 1; | |
2134 | return; | |
2135 | } | |
2136 | /* Get the number of bits to shift. */ | |
2137 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
2138 | value = inst_env->reg[REG_PC]; | |
2139 | ||
2140 | /* Find out how many bits the operation should apply to. */ | |
2141 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2142 | { | |
2143 | if (value & SIGNED_BYTE_MASK) | |
2144 | { | |
2145 | signed_extend_mask = 0xFF; | |
2146 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2147 | signed_extend_mask = ~signed_extend_mask; | |
2148 | } | |
2149 | value = value >> shift_steps; | |
2150 | value |= signed_extend_mask; | |
2151 | value &= 0xFF; | |
2152 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2153 | inst_env->reg[REG_PC] |= value; | |
2154 | } | |
2155 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2156 | { | |
2157 | if (value & SIGNED_WORD_MASK) | |
2158 | { | |
2159 | signed_extend_mask = 0xFFFF; | |
2160 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2161 | signed_extend_mask = ~signed_extend_mask; | |
2162 | } | |
2163 | value = value >> shift_steps; | |
2164 | value |= signed_extend_mask; | |
2165 | value &= 0xFFFF; | |
2166 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2167 | inst_env->reg[REG_PC] |= value; | |
2168 | } | |
2169 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2170 | { | |
2171 | if (value & SIGNED_DWORD_MASK) | |
2172 | { | |
2173 | signed_extend_mask = 0xFFFFFFFF; | |
2174 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2175 | signed_extend_mask = ~signed_extend_mask; | |
2176 | } | |
2177 | value = value >> shift_steps; | |
2178 | value |= signed_extend_mask; | |
2179 | inst_env->reg[REG_PC] = value; | |
2180 | } | |
2181 | } | |
2182 | inst_env->slot_needed = 0; | |
2183 | inst_env->prefix_found = 0; | |
2184 | inst_env->xflag_found = 0; | |
2185 | inst_env->disable_interrupt = 0; | |
2186 | } | |
2187 | ||
2188 | /* Handles the ASRQ instruction. */ | |
2189 | ||
2190 | void | |
2191 | asrq_op (unsigned short inst, inst_env_type *inst_env) | |
2192 | { | |
2193 | ||
2194 | int shift_steps; | |
2195 | unsigned long value; | |
2196 | unsigned long signed_extend_mask = 0; | |
2197 | ||
2198 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2199 | if (inst_env->prefix_found) | |
2200 | { | |
2201 | inst_env->invalid = 1; | |
2202 | return; | |
2203 | } | |
2204 | ||
2205 | /* Check if the PC is the target register. */ | |
2206 | if (cris_get_operand2 (inst) == REG_PC) | |
2207 | { | |
2208 | ||
2209 | /* It's invalid to change the PC in a delay slot. */ | |
2210 | if (inst_env->slot_needed) | |
2211 | { | |
2212 | inst_env->invalid = 1; | |
2213 | return; | |
2214 | } | |
2215 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
2216 | want the the sign bit of the quick value. */ | |
2217 | shift_steps = cris_get_asr_shift_steps (inst); | |
2218 | value = inst_env->reg[REG_PC]; | |
2219 | if (value & SIGNED_DWORD_MASK) | |
2220 | { | |
2221 | signed_extend_mask = 0xFFFFFFFF; | |
2222 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2223 | signed_extend_mask = ~signed_extend_mask; | |
2224 | } | |
2225 | value = value >> shift_steps; | |
2226 | value |= signed_extend_mask; | |
2227 | inst_env->reg[REG_PC] = value; | |
2228 | } | |
2229 | inst_env->slot_needed = 0; | |
2230 | inst_env->prefix_found = 0; | |
2231 | inst_env->xflag_found = 0; | |
2232 | inst_env->disable_interrupt = 0; | |
2233 | } | |
2234 | ||
2235 | /* Handles the AX, EI and SETF instruction. */ | |
2236 | ||
2237 | void | |
2238 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) | |
2239 | { | |
2240 | if (inst_env->prefix_found) | |
2241 | { | |
2242 | inst_env->invalid = 1; | |
2243 | return; | |
2244 | } | |
2245 | /* Check if the instruction is setting the X flag. */ | |
2246 | if (cris_is_xflag_bit_on (inst)) | |
2247 | { | |
2248 | inst_env->xflag_found = 1; | |
2249 | } | |
2250 | else | |
2251 | { | |
2252 | inst_env->xflag_found = 0; | |
2253 | } | |
2254 | inst_env->slot_needed = 0; | |
2255 | inst_env->prefix_found = 0; | |
2256 | inst_env->disable_interrupt = 1; | |
2257 | } | |
2258 | ||
2259 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2260 | register. Note that check_assign assumes that the caller has checked that | |
2261 | there is a prefix to this instruction. The mode check depends on this. */ | |
2262 | ||
2263 | void | |
2264 | check_assign (unsigned short inst, inst_env_type *inst_env) | |
2265 | { | |
2266 | /* Check if it's an assign addressing mode. */ | |
2267 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2268 | { | |
2269 | /* Assign the prefix value to operand 1. */ | |
2270 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2271 | } | |
2272 | } | |
2273 | ||
2274 | /* Handles the 2-operand BOUND instruction. */ | |
2275 | ||
2276 | void | |
2277 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) | |
2278 | { | |
2279 | /* It's invalid to have the PC as the index operand. */ | |
2280 | if (cris_get_operand2 (inst) == REG_PC) | |
2281 | { | |
2282 | inst_env->invalid = 1; | |
2283 | return; | |
2284 | } | |
2285 | /* Check if we have a prefix. */ | |
2286 | if (inst_env->prefix_found) | |
2287 | { | |
2288 | check_assign (inst, inst_env); | |
2289 | } | |
2290 | /* Check if this is an autoincrement mode. */ | |
2291 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2292 | { | |
2293 | /* It's invalid to change the PC in a delay slot. */ | |
2294 | if (inst_env->slot_needed) | |
2295 | { | |
2296 | inst_env->invalid = 1; | |
2297 | return; | |
2298 | } | |
2299 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2300 | } | |
2301 | inst_env->slot_needed = 0; | |
2302 | inst_env->prefix_found = 0; | |
2303 | inst_env->xflag_found = 0; | |
2304 | inst_env->disable_interrupt = 0; | |
2305 | } | |
2306 | ||
2307 | /* Handles the 3-operand BOUND instruction. */ | |
2308 | ||
2309 | void | |
2310 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) | |
2311 | { | |
2312 | /* It's an error if we haven't got a prefix. And it's also an error | |
2313 | if the PC is the destination register. */ | |
2314 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2315 | { | |
2316 | inst_env->invalid = 1; | |
2317 | return; | |
2318 | } | |
2319 | inst_env->slot_needed = 0; | |
2320 | inst_env->prefix_found = 0; | |
2321 | inst_env->xflag_found = 0; | |
2322 | inst_env->disable_interrupt = 0; | |
2323 | } | |
2324 | ||
2325 | /* Clears the status flags in inst_env. */ | |
2326 | ||
2327 | void | |
2328 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) | |
2329 | { | |
2330 | /* It's an error if we have got a prefix. */ | |
2331 | if (inst_env->prefix_found) | |
2332 | { | |
2333 | inst_env->invalid = 1; | |
2334 | return; | |
2335 | } | |
2336 | ||
2337 | inst_env->slot_needed = 0; | |
2338 | inst_env->prefix_found = 0; | |
2339 | inst_env->xflag_found = 0; | |
2340 | inst_env->disable_interrupt = 0; | |
2341 | } | |
2342 | ||
2343 | /* Clears the status flags in inst_env. */ | |
2344 | ||
2345 | void | |
2346 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) | |
2347 | { | |
2348 | /* It's an error if we have got a prefix. */ | |
2349 | if (inst_env->prefix_found) | |
2350 | { | |
2351 | inst_env->invalid = 1; | |
2352 | return; | |
2353 | } | |
2354 | ||
2355 | inst_env->slot_needed = 0; | |
2356 | inst_env->prefix_found = 0; | |
2357 | inst_env->xflag_found = 0; | |
2358 | inst_env->disable_interrupt = 1; | |
2359 | } | |
2360 | ||
2361 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2362 | ||
2363 | void | |
2364 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) | |
2365 | { | |
2366 | /* Check if the target is the PC. */ | |
2367 | if (cris_get_operand2 (inst) == REG_PC) | |
2368 | { | |
2369 | /* The instruction will clear the instruction's size bits. */ | |
2370 | int clear_size = cris_get_clear_size (inst); | |
2371 | if (clear_size == INST_BYTE_SIZE) | |
2372 | { | |
2373 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2374 | } | |
2375 | if (clear_size == INST_WORD_SIZE) | |
2376 | { | |
2377 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2378 | } | |
2379 | if (clear_size == INST_DWORD_SIZE) | |
2380 | { | |
2381 | inst_env->delay_slot_pc = 0x0; | |
2382 | } | |
2383 | /* The jump will be delayed with one delay slot. So we need a delay | |
2384 | slot. */ | |
2385 | inst_env->slot_needed = 1; | |
2386 | inst_env->delay_slot_pc_active = 1; | |
2387 | } | |
2388 | else | |
2389 | { | |
2390 | /* The PC will not change => no delay slot. */ | |
2391 | inst_env->slot_needed = 0; | |
2392 | } | |
2393 | inst_env->prefix_found = 0; | |
2394 | inst_env->xflag_found = 0; | |
2395 | inst_env->disable_interrupt = 0; | |
2396 | } | |
2397 | ||
2398 | /* Handles the TEST instruction if it's in register mode. */ | |
2399 | ||
2400 | void | |
2401 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) | |
2402 | { | |
2403 | /* It's an error if we have got a prefix. */ | |
2404 | if (inst_env->prefix_found) | |
2405 | { | |
2406 | inst_env->invalid = 1; | |
2407 | return; | |
2408 | } | |
2409 | inst_env->slot_needed = 0; | |
2410 | inst_env->prefix_found = 0; | |
2411 | inst_env->xflag_found = 0; | |
2412 | inst_env->disable_interrupt = 0; | |
2413 | ||
2414 | } | |
2415 | ||
2416 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2417 | in register mode. */ | |
2418 | ||
2419 | void | |
2420 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) | |
2421 | { | |
2422 | /* Check if we are in a prefix mode. */ | |
2423 | if (inst_env->prefix_found) | |
2424 | { | |
2425 | /* The only way the PC can change is if this instruction is in | |
2426 | assign addressing mode. */ | |
2427 | check_assign (inst, inst_env); | |
2428 | } | |
2429 | /* Indirect mode can't change the PC so just check if the mode is | |
2430 | autoincrement. */ | |
2431 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2432 | { | |
2433 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2434 | } | |
2435 | inst_env->slot_needed = 0; | |
2436 | inst_env->prefix_found = 0; | |
2437 | inst_env->xflag_found = 0; | |
2438 | inst_env->disable_interrupt = 0; | |
2439 | } | |
2440 | ||
2441 | /* Checks that the PC isn't the destination register or the instructions has | |
2442 | a prefix. */ | |
2443 | ||
2444 | void | |
2445 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) | |
2446 | { | |
2447 | /* It's invalid to have the PC as the destination. The instruction can't | |
2448 | have a prefix. */ | |
2449 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2450 | { | |
2451 | inst_env->invalid = 1; | |
2452 | return; | |
2453 | } | |
2454 | ||
2455 | inst_env->slot_needed = 0; | |
2456 | inst_env->prefix_found = 0; | |
2457 | inst_env->xflag_found = 0; | |
2458 | inst_env->disable_interrupt = 0; | |
2459 | } | |
2460 | ||
2461 | /* Checks that the instruction doesn't have a prefix. */ | |
2462 | ||
2463 | void | |
2464 | break_op (unsigned short inst, inst_env_type *inst_env) | |
2465 | { | |
2466 | /* The instruction can't have a prefix. */ | |
2467 | if (inst_env->prefix_found) | |
2468 | { | |
2469 | inst_env->invalid = 1; | |
2470 | return; | |
2471 | } | |
2472 | ||
2473 | inst_env->slot_needed = 0; | |
2474 | inst_env->prefix_found = 0; | |
2475 | inst_env->xflag_found = 0; | |
2476 | inst_env->disable_interrupt = 1; | |
2477 | } | |
2478 | ||
2479 | /* Checks that the PC isn't the destination register and that the instruction | |
2480 | doesn't have a prefix. */ | |
2481 | ||
2482 | void | |
2483 | scc_op (unsigned short inst, inst_env_type *inst_env) | |
2484 | { | |
2485 | /* It's invalid to have the PC as the destination. The instruction can't | |
2486 | have a prefix. */ | |
2487 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2488 | { | |
2489 | inst_env->invalid = 1; | |
2490 | return; | |
2491 | } | |
2492 | ||
2493 | inst_env->slot_needed = 0; | |
2494 | inst_env->prefix_found = 0; | |
2495 | inst_env->xflag_found = 0; | |
2496 | inst_env->disable_interrupt = 1; | |
2497 | } | |
2498 | ||
2499 | /* Handles the register mode JUMP instruction. */ | |
2500 | ||
2501 | void | |
2502 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
2503 | { | |
2504 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2505 | you can't have a prefix. */ | |
2506 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2507 | { | |
2508 | inst_env->invalid = 1; | |
2509 | return; | |
2510 | } | |
2511 | ||
2512 | /* Just change the PC. */ | |
2513 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2514 | inst_env->slot_needed = 0; | |
2515 | inst_env->prefix_found = 0; | |
2516 | inst_env->xflag_found = 0; | |
2517 | inst_env->disable_interrupt = 1; | |
2518 | } | |
2519 | ||
2520 | /* Handles the JUMP instruction for all modes except register. */ | |
2521 | ||
2522 | void none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
2523 | { | |
2524 | unsigned long newpc; | |
2525 | CORE_ADDR address; | |
2526 | ||
2527 | /* It's invalid to do a JUMP in a delay slot. */ | |
2528 | if (inst_env->slot_needed) | |
2529 | { | |
2530 | inst_env->invalid = 1; | |
2531 | } | |
2532 | else | |
2533 | { | |
2534 | /* Check if we have a prefix. */ | |
2535 | if (inst_env->prefix_found) | |
2536 | { | |
2537 | check_assign (inst, inst_env); | |
2538 | ||
2539 | /* Get the new value for the the PC. */ | |
2540 | newpc = | |
2541 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
2542 | 4); | |
2543 | } | |
2544 | else | |
2545 | { | |
2546 | /* Get the new value for the PC. */ | |
2547 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2548 | newpc = read_memory_unsigned_integer (address, 4); | |
2549 | ||
2550 | /* Check if we should increment a register. */ | |
2551 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2552 | { | |
2553 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2554 | } | |
2555 | } | |
2556 | inst_env->reg[REG_PC] = newpc; | |
2557 | } | |
2558 | inst_env->slot_needed = 0; | |
2559 | inst_env->prefix_found = 0; | |
2560 | inst_env->xflag_found = 0; | |
2561 | inst_env->disable_interrupt = 1; | |
2562 | } | |
2563 | ||
2564 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2565 | ||
2566 | void | |
2567 | move_to_preg_op (unsigned short inst, inst_env_type *inst_env) | |
2568 | { | |
2569 | if (inst_env->prefix_found) | |
2570 | { | |
2571 | /* The instruction has a prefix that means we are only interested if | |
2572 | the instruction is in assign mode. */ | |
2573 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2574 | { | |
2575 | /* The prefix handles the problem if we are in a delay slot. */ | |
2576 | if (cris_get_operand1 (inst) == REG_PC) | |
2577 | { | |
2578 | /* Just take care of the assign. */ | |
2579 | check_assign (inst, inst_env); | |
2580 | } | |
2581 | } | |
2582 | } | |
2583 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2584 | { | |
2585 | /* The instruction doesn't have a prefix, the only case left that we | |
2586 | are interested in is the autoincrement mode. */ | |
2587 | if (cris_get_operand1 (inst) == REG_PC) | |
2588 | { | |
2589 | /* If the PC is to be incremented it's invalid to be in a | |
2590 | delay slot. */ | |
2591 | if (inst_env->slot_needed) | |
2592 | { | |
2593 | inst_env->invalid = 1; | |
2594 | return; | |
2595 | } | |
2a9ecef2 OF |
2596 | |
2597 | /* The increment depends on the size of the special register. */ | |
2598 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2599 | { |
2600 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2601 | } | |
2a9ecef2 | 2602 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2603 | { |
2604 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2605 | } | |
2606 | else | |
2607 | { | |
2608 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2609 | } | |
2610 | } | |
2611 | } | |
2612 | inst_env->slot_needed = 0; | |
2613 | inst_env->prefix_found = 0; | |
2614 | inst_env->xflag_found = 0; | |
2615 | inst_env->disable_interrupt = 1; | |
2616 | } | |
2617 | ||
2618 | /* Handles moves from special registers (aka P-register) for all modes | |
2619 | except register. */ | |
2620 | ||
2621 | void | |
2622 | none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) | |
2623 | { | |
2624 | if (inst_env->prefix_found) | |
2625 | { | |
2626 | /* The instruction has a prefix that means we are only interested if | |
2627 | the instruction is in assign mode. */ | |
2628 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2629 | { | |
2630 | /* The prefix handles the problem if we are in a delay slot. */ | |
2631 | if (cris_get_operand1 (inst) == REG_PC) | |
2632 | { | |
2633 | /* Just take care of the assign. */ | |
2634 | check_assign (inst, inst_env); | |
2635 | } | |
2636 | } | |
2637 | } | |
2638 | /* The instruction doesn't have a prefix, the only case left that we | |
2639 | are interested in is the autoincrement mode. */ | |
2640 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2641 | { | |
2642 | if (cris_get_operand1 (inst) == REG_PC) | |
2643 | { | |
2644 | /* If the PC is to be incremented it's invalid to be in a | |
2645 | delay slot. */ | |
2646 | if (inst_env->slot_needed) | |
2647 | { | |
2648 | inst_env->invalid = 1; | |
2649 | return; | |
2650 | } | |
2a9ecef2 OF |
2651 | |
2652 | /* The increment depends on the size of the special register. */ | |
2653 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2654 | { |
2655 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2656 | } | |
2a9ecef2 | 2657 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2658 | { |
2659 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2660 | } | |
2661 | else | |
2662 | { | |
2663 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2664 | } | |
2665 | } | |
2666 | } | |
2667 | inst_env->slot_needed = 0; | |
2668 | inst_env->prefix_found = 0; | |
2669 | inst_env->xflag_found = 0; | |
2670 | inst_env->disable_interrupt = 1; | |
2671 | } | |
2672 | ||
2673 | /* Handles moves from special registers (aka P-register) when the mode | |
2674 | is register. */ | |
2675 | ||
2676 | void | |
2677 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) | |
2678 | { | |
2679 | /* Register mode move from special register can't have a prefix. */ | |
2680 | if (inst_env->prefix_found) | |
2681 | { | |
2682 | inst_env->invalid = 1; | |
2683 | return; | |
2684 | } | |
2685 | ||
2686 | if (cris_get_operand1 (inst) == REG_PC) | |
2687 | { | |
2688 | /* It's invalid to change the PC in a delay slot. */ | |
2689 | if (inst_env->slot_needed) | |
2690 | { | |
2691 | inst_env->invalid = 1; | |
2692 | return; | |
2693 | } | |
2694 | /* The destination is the PC, the jump will have a delay slot. */ | |
2695 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
2696 | inst_env->slot_needed = 1; | |
2697 | inst_env->delay_slot_pc_active = 1; | |
2698 | } | |
2699 | else | |
2700 | { | |
2701 | /* If the destination isn't PC, there will be no jump. */ | |
2702 | inst_env->slot_needed = 0; | |
2703 | } | |
2704 | inst_env->prefix_found = 0; | |
2705 | inst_env->xflag_found = 0; | |
2706 | inst_env->disable_interrupt = 1; | |
2707 | } | |
2708 | ||
2709 | /* Handles the MOVEM from memory to general register instruction. */ | |
2710 | ||
2711 | void | |
2712 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) | |
2713 | { | |
2714 | if (inst_env->prefix_found) | |
2715 | { | |
2716 | /* The prefix handles the problem if we are in a delay slot. Is the | |
2717 | MOVEM instruction going to change the PC? */ | |
2718 | if (cris_get_operand2 (inst) >= REG_PC) | |
2719 | { | |
2720 | inst_env->reg[REG_PC] = | |
2721 | read_memory_unsigned_integer (inst_env->prefix_value, 4); | |
2722 | } | |
2723 | /* The assign value is the value after the increment. Normally, the | |
2724 | assign value is the value before the increment. */ | |
2725 | if ((cris_get_operand1 (inst) == REG_PC) | |
2726 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
2727 | { | |
2728 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
2729 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2730 | } | |
2731 | } | |
2732 | else | |
2733 | { | |
2734 | /* Is the MOVEM instruction going to change the PC? */ | |
2735 | if (cris_get_operand2 (inst) == REG_PC) | |
2736 | { | |
2737 | /* It's invalid to change the PC in a delay slot. */ | |
2738 | if (inst_env->slot_needed) | |
2739 | { | |
2740 | inst_env->invalid = 1; | |
2741 | return; | |
2742 | } | |
2743 | inst_env->reg[REG_PC] = | |
2744 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
2745 | 4); | |
2746 | } | |
2747 | /* The increment is not depending on the size, instead it's depending | |
2748 | on the number of registers loaded from memory. */ | |
2749 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
2750 | { | |
2751 | /* It's invalid to change the PC in a delay slot. */ | |
2752 | if (inst_env->slot_needed) | |
2753 | { | |
2754 | inst_env->invalid = 1; | |
2755 | return; | |
2756 | } | |
2757 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2758 | } | |
2759 | } | |
2760 | inst_env->slot_needed = 0; | |
2761 | inst_env->prefix_found = 0; | |
2762 | inst_env->xflag_found = 0; | |
2763 | inst_env->disable_interrupt = 0; | |
2764 | } | |
2765 | ||
2766 | /* Handles the MOVEM to memory from general register instruction. */ | |
2767 | ||
2768 | void | |
2769 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) | |
2770 | { | |
2771 | if (inst_env->prefix_found) | |
2772 | { | |
2773 | /* The assign value is the value after the increment. Normally, the | |
2774 | assign value is the value before the increment. */ | |
2775 | if ((cris_get_operand1 (inst) == REG_PC) && | |
2776 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
2777 | { | |
2778 | /* The prefix handles the problem if we are in a delay slot. */ | |
2779 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
2780 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2781 | } | |
2782 | } | |
2783 | else | |
2784 | { | |
2785 | /* The increment is not depending on the size, instead it's depending | |
2786 | on the number of registers loaded to memory. */ | |
2787 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
2788 | { | |
2789 | /* It's invalid to change the PC in a delay slot. */ | |
2790 | if (inst_env->slot_needed) | |
2791 | { | |
2792 | inst_env->invalid = 1; | |
2793 | return; | |
2794 | } | |
2795 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2796 | } | |
2797 | } | |
2798 | inst_env->slot_needed = 0; | |
2799 | inst_env->prefix_found = 0; | |
2800 | inst_env->xflag_found = 0; | |
2801 | inst_env->disable_interrupt = 0; | |
2802 | } | |
2803 | ||
2804 | /* Handles the pop instruction to a general register. | |
2805 | POP is a assembler macro for MOVE.D [SP+], Rd. */ | |
2806 | ||
2807 | void | |
2808 | reg_pop_op (unsigned short inst, inst_env_type *inst_env) | |
2809 | { | |
2810 | /* POP can't have a prefix. */ | |
2811 | if (inst_env->prefix_found) | |
2812 | { | |
2813 | inst_env->invalid = 1; | |
2814 | return; | |
2815 | } | |
2816 | if (cris_get_operand2 (inst) == REG_PC) | |
2817 | { | |
2818 | /* It's invalid to change the PC in a delay slot. */ | |
2819 | if (inst_env->slot_needed) | |
2820 | { | |
2821 | inst_env->invalid = 1; | |
2822 | return; | |
2823 | } | |
2824 | inst_env->reg[REG_PC] = | |
2825 | read_memory_unsigned_integer (inst_env->reg[REG_SP], 4); | |
2826 | } | |
2827 | inst_env->slot_needed = 0; | |
2828 | inst_env->prefix_found = 0; | |
2829 | inst_env->xflag_found = 0; | |
2830 | inst_env->disable_interrupt = 0; | |
2831 | } | |
2832 | ||
2833 | /* Handles moves from register to memory. */ | |
2834 | ||
2835 | void | |
2836 | move_reg_to_mem_index_inc_op (unsigned short inst, inst_env_type *inst_env) | |
2837 | { | |
2838 | /* Check if we have a prefix. */ | |
2839 | if (inst_env->prefix_found) | |
2840 | { | |
2841 | /* The only thing that can change the PC is an assign. */ | |
2842 | check_assign (inst, inst_env); | |
2843 | } | |
2844 | else if ((cris_get_operand1 (inst) == REG_PC) | |
2845 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
2846 | { | |
2847 | /* It's invalid to change the PC in a delay slot. */ | |
2848 | if (inst_env->slot_needed) | |
2849 | { | |
2850 | inst_env->invalid = 1; | |
2851 | return; | |
2852 | } | |
2853 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2854 | } | |
2855 | inst_env->slot_needed = 0; | |
2856 | inst_env->prefix_found = 0; | |
2857 | inst_env->xflag_found = 0; | |
2858 | inst_env->disable_interrupt = 0; | |
2859 | } | |
2860 | ||
2861 | /* Handles the intructions that's not yet implemented, by setting | |
2862 | inst_env->invalid to true. */ | |
2863 | ||
2864 | void | |
2865 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) | |
2866 | { | |
2867 | inst_env->invalid = 1; | |
2868 | } | |
2869 | ||
2870 | /* Handles the XOR instruction. */ | |
2871 | ||
2872 | void | |
2873 | xor_op (unsigned short inst, inst_env_type *inst_env) | |
2874 | { | |
2875 | /* XOR can't have a prefix. */ | |
2876 | if (inst_env->prefix_found) | |
2877 | { | |
2878 | inst_env->invalid = 1; | |
2879 | return; | |
2880 | } | |
2881 | ||
2882 | /* Check if the PC is the target. */ | |
2883 | if (cris_get_operand2 (inst) == REG_PC) | |
2884 | { | |
2885 | /* It's invalid to change the PC in a delay slot. */ | |
2886 | if (inst_env->slot_needed) | |
2887 | { | |
2888 | inst_env->invalid = 1; | |
2889 | return; | |
2890 | } | |
2891 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
2892 | } | |
2893 | inst_env->slot_needed = 0; | |
2894 | inst_env->prefix_found = 0; | |
2895 | inst_env->xflag_found = 0; | |
2896 | inst_env->disable_interrupt = 0; | |
2897 | } | |
2898 | ||
2899 | /* Handles the MULS instruction. */ | |
2900 | ||
2901 | void | |
2902 | muls_op (unsigned short inst, inst_env_type *inst_env) | |
2903 | { | |
2904 | /* MULS/U can't have a prefix. */ | |
2905 | if (inst_env->prefix_found) | |
2906 | { | |
2907 | inst_env->invalid = 1; | |
2908 | return; | |
2909 | } | |
2910 | ||
2911 | /* Consider it invalid if the PC is the target. */ | |
2912 | if (cris_get_operand2 (inst) == REG_PC) | |
2913 | { | |
2914 | inst_env->invalid = 1; | |
2915 | return; | |
2916 | } | |
2917 | inst_env->slot_needed = 0; | |
2918 | inst_env->prefix_found = 0; | |
2919 | inst_env->xflag_found = 0; | |
2920 | inst_env->disable_interrupt = 0; | |
2921 | } | |
2922 | ||
2923 | /* Handles the MULU instruction. */ | |
2924 | ||
2925 | void | |
2926 | mulu_op (unsigned short inst, inst_env_type *inst_env) | |
2927 | { | |
2928 | /* MULS/U can't have a prefix. */ | |
2929 | if (inst_env->prefix_found) | |
2930 | { | |
2931 | inst_env->invalid = 1; | |
2932 | return; | |
2933 | } | |
2934 | ||
2935 | /* Consider it invalid if the PC is the target. */ | |
2936 | if (cris_get_operand2 (inst) == REG_PC) | |
2937 | { | |
2938 | inst_env->invalid = 1; | |
2939 | return; | |
2940 | } | |
2941 | inst_env->slot_needed = 0; | |
2942 | inst_env->prefix_found = 0; | |
2943 | inst_env->xflag_found = 0; | |
2944 | inst_env->disable_interrupt = 0; | |
2945 | } | |
2946 | ||
2947 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. | |
2948 | The MOVE instruction is the move from source to register. */ | |
2949 | ||
2950 | void | |
2951 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, | |
2952 | unsigned long source1, unsigned long source2) | |
2953 | { | |
2954 | unsigned long pc_mask; | |
2955 | unsigned long operation_mask; | |
2956 | ||
2957 | /* Find out how many bits the operation should apply to. */ | |
2958 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2959 | { | |
2960 | pc_mask = 0xFFFFFF00; | |
2961 | operation_mask = 0xFF; | |
2962 | } | |
2963 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2964 | { | |
2965 | pc_mask = 0xFFFF0000; | |
2966 | operation_mask = 0xFFFF; | |
2967 | } | |
2968 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2969 | { | |
2970 | pc_mask = 0x0; | |
2971 | operation_mask = 0xFFFFFFFF; | |
2972 | } | |
2973 | else | |
2974 | { | |
2975 | /* The size is out of range. */ | |
2976 | inst_env->invalid = 1; | |
2977 | return; | |
2978 | } | |
2979 | ||
2980 | /* The instruction just works on uw_operation_mask bits. */ | |
2981 | source2 &= operation_mask; | |
2982 | source1 &= operation_mask; | |
2983 | ||
2984 | /* Now calculate the result. The opcode's 3 first bits separates | |
2985 | the different actions. */ | |
2986 | switch (cris_get_opcode (inst) & 7) | |
2987 | { | |
2988 | case 0: /* add */ | |
2989 | source1 += source2; | |
2990 | break; | |
2991 | ||
2992 | case 1: /* move */ | |
2993 | source1 = source2; | |
2994 | break; | |
2995 | ||
2996 | case 2: /* subtract */ | |
2997 | source1 -= source2; | |
2998 | break; | |
2999 | ||
3000 | case 3: /* compare */ | |
3001 | break; | |
3002 | ||
3003 | case 4: /* and */ | |
3004 | source1 &= source2; | |
3005 | break; | |
3006 | ||
3007 | case 5: /* or */ | |
3008 | source1 |= source2; | |
3009 | break; | |
3010 | ||
3011 | default: | |
3012 | inst_env->invalid = 1; | |
3013 | return; | |
3014 | ||
3015 | break; | |
3016 | } | |
3017 | ||
3018 | /* Make sure that the result doesn't contain more than the instruction | |
3019 | size bits. */ | |
3020 | source2 &= operation_mask; | |
3021 | ||
3022 | /* Calculate the new breakpoint address. */ | |
3023 | inst_env->reg[REG_PC] &= pc_mask; | |
3024 | inst_env->reg[REG_PC] |= source1; | |
3025 | ||
3026 | } | |
3027 | ||
3028 | /* Extends the value from either byte or word size to a dword. If the mode | |
3029 | is zero extend then the value is extended with zero. If instead the mode | |
3030 | is signed extend the sign bit of the value is taken into consideration. */ | |
3031 | ||
3032 | unsigned long | |
3033 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) | |
3034 | { | |
3035 | /* The size can be either byte or word, check which one it is. | |
3036 | Don't check the highest bit, it's indicating if it's a zero | |
3037 | or sign extend. */ | |
3038 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3039 | { | |
3040 | /* Word size. */ | |
3041 | value &= 0xFFFF; | |
3042 | ||
3043 | /* Check if the instruction is signed extend. If so, check if value has | |
3044 | the sign bit on. */ | |
3045 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3046 | { | |
3047 | value |= SIGNED_WORD_EXTEND_MASK; | |
3048 | } | |
3049 | } | |
3050 | else | |
3051 | { | |
3052 | /* Byte size. */ | |
3053 | value &= 0xFF; | |
3054 | ||
3055 | /* Check if the instruction is signed extend. If so, check if value has | |
3056 | the sign bit on. */ | |
3057 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3058 | { | |
3059 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3060 | } | |
3061 | } | |
3062 | /* The size should now be dword. */ | |
3063 | cris_set_size_to_dword (inst); | |
3064 | return value; | |
3065 | } | |
3066 | ||
3067 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3068 | instruction. The MOVE instruction is the move from source to register. */ | |
3069 | ||
3070 | void | |
3071 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, | |
3072 | inst_env_type *inst_env) | |
3073 | { | |
3074 | unsigned long operand1; | |
3075 | unsigned long operand2; | |
3076 | ||
3077 | /* It's invalid to have a prefix to the instruction. This is a register | |
3078 | mode instruction and can't have a prefix. */ | |
3079 | if (inst_env->prefix_found) | |
3080 | { | |
3081 | inst_env->invalid = 1; | |
3082 | return; | |
3083 | } | |
3084 | /* Check if the instruction has PC as its target. */ | |
3085 | if (cris_get_operand2 (inst) == REG_PC) | |
3086 | { | |
3087 | if (inst_env->slot_needed) | |
3088 | { | |
3089 | inst_env->invalid = 1; | |
3090 | return; | |
3091 | } | |
3092 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3093 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3094 | operand2 = inst_env->reg[REG_PC]; |
3095 | ||
3096 | /* Check if it's a extend, signed or zero instruction. */ | |
3097 | if (cris_get_opcode (inst) < 4) | |
3098 | { | |
3099 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3100 | } | |
3101 | /* Calculate the PC value after the instruction, i.e. where the | |
3102 | breakpoint should be. The order of the udw_operands is vital. */ | |
3103 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3104 | } | |
3105 | inst_env->slot_needed = 0; | |
3106 | inst_env->prefix_found = 0; | |
3107 | inst_env->xflag_found = 0; | |
3108 | inst_env->disable_interrupt = 0; | |
3109 | } | |
3110 | ||
3111 | /* Returns the data contained at address. The size of the data is derived from | |
3112 | the size of the operation. If the instruction is a zero or signed | |
3113 | extend instruction, the size field is changed in instruction. */ | |
3114 | ||
3115 | unsigned long | |
3116 | get_data_from_address (unsigned short *inst, CORE_ADDR address) | |
3117 | { | |
3118 | int size = cris_get_size (*inst); | |
3119 | unsigned long value; | |
3120 | ||
3121 | /* If it's an extend instruction we don't want the signed extend bit, | |
3122 | because it influences the size. */ | |
3123 | if (cris_get_opcode (*inst) < 4) | |
3124 | { | |
3125 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3126 | } | |
3127 | /* Is there a need for checking the size? Size should contain the number of | |
3128 | bytes to read. */ | |
3129 | size = 1 << size; | |
3130 | value = read_memory_unsigned_integer (address, size); | |
3131 | ||
3132 | /* Check if it's an extend, signed or zero instruction. */ | |
3133 | if (cris_get_opcode (*inst) < 4) | |
3134 | { | |
3135 | value = do_sign_or_zero_extend (value, inst); | |
3136 | } | |
3137 | return value; | |
3138 | } | |
3139 | ||
3140 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3141 | instructions. The MOVE instruction is the move from source to register. */ | |
3142 | ||
3143 | void | |
3144 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, | |
3145 | inst_env_type *inst_env) | |
3146 | { | |
3147 | unsigned long operand2; | |
3148 | unsigned long operand3; | |
3149 | ||
3150 | check_assign (inst, inst_env); | |
3151 | if (cris_get_operand2 (inst) == REG_PC) | |
3152 | { | |
3153 | operand2 = inst_env->reg[REG_PC]; | |
3154 | ||
3155 | /* Get the value of the third operand. */ | |
3156 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3157 | ||
3158 | /* Calculate the PC value after the instruction, i.e. where the | |
3159 | breakpoint should be. The order of the udw_operands is vital. */ | |
3160 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3161 | } | |
3162 | inst_env->slot_needed = 0; | |
3163 | inst_env->prefix_found = 0; | |
3164 | inst_env->xflag_found = 0; | |
3165 | inst_env->disable_interrupt = 0; | |
3166 | } | |
3167 | ||
3168 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3169 | OR instructions. Note that for this to work as expected, the calling | |
3170 | function must have made sure that there is a prefix to this instruction. */ | |
3171 | ||
3172 | void | |
3173 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, | |
3174 | inst_env_type *inst_env) | |
3175 | { | |
3176 | unsigned long operand2; | |
3177 | unsigned long operand3; | |
3178 | ||
3179 | if (cris_get_operand1 (inst) == REG_PC) | |
3180 | { | |
3181 | /* The PC will be changed by the instruction. */ | |
3182 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3183 | ||
3184 | /* Get the value of the third operand. */ | |
3185 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3186 | ||
3187 | /* Calculate the PC value after the instruction, i.e. where the | |
3188 | breakpoint should be. */ | |
3189 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3190 | } | |
3191 | inst_env->slot_needed = 0; | |
3192 | inst_env->prefix_found = 0; | |
3193 | inst_env->xflag_found = 0; | |
3194 | inst_env->disable_interrupt = 0; | |
3195 | } | |
3196 | ||
3197 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3198 | instructions. The MOVE instruction is the move from source to register. */ | |
3199 | ||
3200 | void | |
3201 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, | |
3202 | inst_env_type *inst_env) | |
3203 | { | |
3204 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3205 | { | |
3206 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3207 | SUB, AND or OR something weird is going on (if everything works these | |
3208 | instructions should end up in the three operand version). */ | |
3209 | inst_env->invalid = 1; | |
3210 | return; | |
3211 | } | |
3212 | else | |
3213 | { | |
3214 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3215 | so use it. */ | |
3216 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3217 | } | |
3218 | inst_env->slot_needed = 0; | |
3219 | inst_env->prefix_found = 0; | |
3220 | inst_env->xflag_found = 0; | |
3221 | inst_env->disable_interrupt = 0; | |
3222 | } | |
3223 | ||
3224 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3225 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3226 | source to register. */ | |
3227 | ||
3228 | void | |
3229 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, | |
3230 | inst_env_type *inst_env) | |
3231 | { | |
3232 | unsigned long operand1; | |
3233 | unsigned long operand2; | |
3234 | unsigned long operand3; | |
3235 | int size; | |
3236 | ||
3237 | /* The instruction is either an indirect or autoincrement addressing mode. | |
3238 | Check if the destination register is the PC. */ | |
3239 | if (cris_get_operand2 (inst) == REG_PC) | |
3240 | { | |
3241 | /* Must be done here, get_data_from_address may change the size | |
3242 | field. */ | |
3243 | size = cris_get_size (inst); | |
3244 | operand2 = inst_env->reg[REG_PC]; | |
3245 | ||
3246 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3247 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
3248 | operand3 = get_data_from_address (&inst, operand1); | |
3249 | ||
3250 | /* Calculate the PC value after the instruction, i.e. where the | |
3251 | breakpoint should be. The order of the udw_operands is vital. */ | |
3252 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3253 | } | |
3254 | /* If this is an autoincrement addressing mode, check if the increment | |
3255 | changes the PC. */ | |
3256 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3257 | { | |
3258 | /* Get the size field. */ | |
3259 | size = cris_get_size (inst); | |
3260 | ||
3261 | /* If it's an extend instruction we don't want the signed extend bit, | |
3262 | because it influences the size. */ | |
3263 | if (cris_get_opcode (inst) < 4) | |
3264 | { | |
3265 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3266 | } | |
3267 | process_autoincrement (size, inst, inst_env); | |
3268 | } | |
3269 | inst_env->slot_needed = 0; | |
3270 | inst_env->prefix_found = 0; | |
3271 | inst_env->xflag_found = 0; | |
3272 | inst_env->disable_interrupt = 0; | |
3273 | } | |
3274 | ||
3275 | /* Handles the two-operand addressing mode, all modes except register, for | |
3276 | the ADD, SUB CMP, AND and OR instruction. */ | |
3277 | ||
3278 | void | |
3279 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, | |
3280 | inst_env_type *inst_env) | |
3281 | { | |
3282 | if (inst_env->prefix_found) | |
3283 | { | |
3284 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3285 | { | |
3286 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3287 | } | |
3288 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3289 | { | |
3290 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3291 | } | |
3292 | else | |
3293 | { | |
3294 | /* The mode is invalid for a prefixed base instruction. */ | |
3295 | inst_env->invalid = 1; | |
3296 | return; | |
3297 | } | |
3298 | } | |
3299 | else | |
3300 | { | |
3301 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3302 | } | |
3303 | } | |
3304 | ||
3305 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3306 | ||
3307 | void | |
3308 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) | |
3309 | { | |
3310 | unsigned long operand1; | |
3311 | unsigned long operand2; | |
3312 | ||
3313 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3314 | instruction and can't have a prefix. */ | |
3315 | if (inst_env->prefix_found) | |
3316 | { | |
3317 | inst_env->invalid = 1; | |
3318 | return; | |
3319 | } | |
3320 | ||
3321 | /* Check if the instruction has PC as its target. */ | |
3322 | if (cris_get_operand2 (inst) == REG_PC) | |
3323 | { | |
3324 | if (inst_env->slot_needed) | |
3325 | { | |
3326 | inst_env->invalid = 1; | |
3327 | return; | |
3328 | } | |
3329 | operand1 = cris_get_quick_value (inst); | |
3330 | operand2 = inst_env->reg[REG_PC]; | |
3331 | ||
3332 | /* The size should now be dword. */ | |
3333 | cris_set_size_to_dword (&inst); | |
3334 | ||
3335 | /* Calculate the PC value after the instruction, i.e. where the | |
3336 | breakpoint should be. */ | |
3337 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3338 | } | |
3339 | inst_env->slot_needed = 0; | |
3340 | inst_env->prefix_found = 0; | |
3341 | inst_env->xflag_found = 0; | |
3342 | inst_env->disable_interrupt = 0; | |
3343 | } | |
3344 | ||
3345 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3346 | ||
3347 | void | |
3348 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) | |
3349 | { | |
3350 | unsigned long operand1; | |
3351 | unsigned long operand2; | |
3352 | ||
3353 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3354 | instruction and can't have a prefix. */ | |
3355 | if (inst_env->prefix_found) | |
3356 | { | |
3357 | inst_env->invalid = 1; | |
3358 | return; | |
3359 | } | |
3360 | /* Check if the instruction has PC as its target. */ | |
3361 | if (cris_get_operand2 (inst) == REG_PC) | |
3362 | { | |
3363 | if (inst_env->slot_needed) | |
3364 | { | |
3365 | inst_env->invalid = 1; | |
3366 | return; | |
3367 | } | |
3368 | /* The instruction has the PC as its target register. */ | |
3369 | operand1 = cris_get_quick_value (inst); | |
3370 | operand2 = inst_env->reg[REG_PC]; | |
3371 | ||
3372 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3373 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3374 | { | |
3375 | /* sign extend */ | |
3376 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3377 | } | |
3378 | /* The size should now be dword. */ | |
3379 | cris_set_size_to_dword (&inst); | |
3380 | ||
3381 | /* Calculate the PC value after the instruction, i.e. where the | |
3382 | breakpoint should be. */ | |
3383 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3384 | } | |
3385 | inst_env->slot_needed = 0; | |
3386 | inst_env->prefix_found = 0; | |
3387 | inst_env->xflag_found = 0; | |
3388 | inst_env->disable_interrupt = 0; | |
3389 | } | |
3390 | ||
3391 | /* Translate op_type to a function and call it. */ | |
3392 | ||
3393 | static void cris_gdb_func (enum cris_op_type op_type, unsigned short inst, | |
3394 | inst_env_type *inst_env) | |
3395 | { | |
3396 | switch (op_type) | |
3397 | { | |
3398 | case cris_not_implemented_op: | |
3399 | not_implemented_op (inst, inst_env); | |
3400 | break; | |
3401 | ||
3402 | case cris_abs_op: | |
3403 | abs_op (inst, inst_env); | |
3404 | break; | |
3405 | ||
3406 | case cris_addi_op: | |
3407 | addi_op (inst, inst_env); | |
3408 | break; | |
3409 | ||
3410 | case cris_asr_op: | |
3411 | asr_op (inst, inst_env); | |
3412 | break; | |
3413 | ||
3414 | case cris_asrq_op: | |
3415 | asrq_op (inst, inst_env); | |
3416 | break; | |
3417 | ||
3418 | case cris_ax_ei_setf_op: | |
3419 | ax_ei_setf_op (inst, inst_env); | |
3420 | break; | |
3421 | ||
3422 | case cris_bdap_prefix: | |
3423 | bdap_prefix (inst, inst_env); | |
3424 | break; | |
3425 | ||
3426 | case cris_biap_prefix: | |
3427 | biap_prefix (inst, inst_env); | |
3428 | break; | |
3429 | ||
3430 | case cris_break_op: | |
3431 | break_op (inst, inst_env); | |
3432 | break; | |
3433 | ||
3434 | case cris_btst_nop_op: | |
3435 | btst_nop_op (inst, inst_env); | |
3436 | break; | |
3437 | ||
3438 | case cris_clearf_di_op: | |
3439 | clearf_di_op (inst, inst_env); | |
3440 | break; | |
3441 | ||
3442 | case cris_dip_prefix: | |
3443 | dip_prefix (inst, inst_env); | |
3444 | break; | |
3445 | ||
3446 | case cris_dstep_logshift_mstep_neg_not_op: | |
3447 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3448 | break; | |
3449 | ||
3450 | case cris_eight_bit_offset_branch_op: | |
3451 | eight_bit_offset_branch_op (inst, inst_env); | |
3452 | break; | |
3453 | ||
3454 | case cris_move_mem_to_reg_movem_op: | |
3455 | move_mem_to_reg_movem_op (inst, inst_env); | |
3456 | break; | |
3457 | ||
3458 | case cris_move_reg_to_mem_movem_op: | |
3459 | move_reg_to_mem_movem_op (inst, inst_env); | |
3460 | break; | |
3461 | ||
3462 | case cris_move_to_preg_op: | |
3463 | move_to_preg_op (inst, inst_env); | |
3464 | break; | |
3465 | ||
3466 | case cris_muls_op: | |
3467 | muls_op (inst, inst_env); | |
3468 | break; | |
3469 | ||
3470 | case cris_mulu_op: | |
3471 | mulu_op (inst, inst_env); | |
3472 | break; | |
3473 | ||
3474 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3475 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3476 | break; | |
3477 | ||
3478 | case cris_none_reg_mode_clear_test_op: | |
3479 | none_reg_mode_clear_test_op (inst, inst_env); | |
3480 | break; | |
3481 | ||
3482 | case cris_none_reg_mode_jump_op: | |
3483 | none_reg_mode_jump_op (inst, inst_env); | |
3484 | break; | |
3485 | ||
3486 | case cris_none_reg_mode_move_from_preg_op: | |
3487 | none_reg_mode_move_from_preg_op (inst, inst_env); | |
3488 | break; | |
3489 | ||
3490 | case cris_quick_mode_add_sub_op: | |
3491 | quick_mode_add_sub_op (inst, inst_env); | |
3492 | break; | |
3493 | ||
3494 | case cris_quick_mode_and_cmp_move_or_op: | |
3495 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3496 | break; | |
3497 | ||
3498 | case cris_quick_mode_bdap_prefix: | |
3499 | quick_mode_bdap_prefix (inst, inst_env); | |
3500 | break; | |
3501 | ||
3502 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3503 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3504 | break; | |
3505 | ||
3506 | case cris_reg_mode_clear_op: | |
3507 | reg_mode_clear_op (inst, inst_env); | |
3508 | break; | |
3509 | ||
3510 | case cris_reg_mode_jump_op: | |
3511 | reg_mode_jump_op (inst, inst_env); | |
3512 | break; | |
3513 | ||
3514 | case cris_reg_mode_move_from_preg_op: | |
3515 | reg_mode_move_from_preg_op (inst, inst_env); | |
3516 | break; | |
3517 | ||
3518 | case cris_reg_mode_test_op: | |
3519 | reg_mode_test_op (inst, inst_env); | |
3520 | break; | |
3521 | ||
3522 | case cris_scc_op: | |
3523 | scc_op (inst, inst_env); | |
3524 | break; | |
3525 | ||
3526 | case cris_sixteen_bit_offset_branch_op: | |
3527 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3528 | break; | |
3529 | ||
3530 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3531 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3532 | break; | |
3533 | ||
3534 | case cris_three_operand_bound_op: | |
3535 | three_operand_bound_op (inst, inst_env); | |
3536 | break; | |
3537 | ||
3538 | case cris_two_operand_bound_op: | |
3539 | two_operand_bound_op (inst, inst_env); | |
3540 | break; | |
3541 | ||
3542 | case cris_xor_op: | |
3543 | xor_op (inst, inst_env); | |
3544 | break; | |
3545 | } | |
3546 | } | |
3547 | ||
3548 | /* This wrapper is to avoid cris_get_assembler being called before | |
3549 | exec_bfd has been set. */ | |
3550 | ||
3551 | static int | |
3552 | cris_delayed_get_disassembler (bfd_vma addr, disassemble_info *info) | |
3553 | { | |
3554 | tm_print_insn = cris_get_disassembler (exec_bfd); | |
2bf0cb65 | 3555 | return TARGET_PRINT_INSN (addr, info); |
29134980 OF |
3556 | } |
3557 | ||
3558 | void | |
3559 | _initialize_cris_tdep (void) | |
3560 | { | |
3561 | struct cmd_list_element *c; | |
3562 | ||
3563 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3564 | ||
3565 | /* Used in disassembly. */ | |
3566 | tm_print_insn = cris_delayed_get_disassembler; | |
3567 | ||
3568 | /* CRIS-specific user-commands. */ | |
3569 | c = add_set_cmd ("cris-version", class_support, var_integer, | |
3570 | (char *) &usr_cmd_cris_version, | |
3571 | "Set the current CRIS version.", &setlist); | |
3572 | c->function.sfunc = cris_version_update; | |
3573 | add_show_from_set (c, &showlist); | |
3574 | ||
3575 | c = add_set_enum_cmd ("cris-mode", class_support, cris_mode_enums, | |
3576 | &usr_cmd_cris_mode, | |
3577 | "Set the current CRIS mode.", &setlist); | |
3578 | c->function.sfunc = cris_mode_update; | |
3579 | add_show_from_set (c, &showlist); | |
3580 | ||
3581 | c = add_set_enum_cmd ("cris-abi", class_support, cris_abi_enums, | |
3582 | &usr_cmd_cris_abi, | |
3583 | "Set the current CRIS ABI version.", &setlist); | |
3584 | c->function.sfunc = cris_abi_update; | |
3585 | add_show_from_set (c, &showlist); | |
3586 | } | |
3587 | ||
3588 | /* Prints out all target specific values. */ | |
3589 | ||
3590 | static void | |
3591 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3592 | { | |
3593 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3594 | if (tdep != NULL) | |
3595 | { | |
3596 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
3597 | tdep->cris_version); | |
3598 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", | |
3599 | tdep->cris_mode); | |
3600 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_abi = %s\n", | |
3601 | tdep->cris_abi); | |
3602 | ||
3603 | } | |
3604 | } | |
3605 | ||
3606 | static void | |
3607 | cris_version_update (char *ignore_args, int from_tty, | |
3608 | struct cmd_list_element *c) | |
3609 | { | |
3610 | struct gdbarch_info info; | |
3611 | ||
3612 | /* From here on, trust the user's CRIS version setting. */ | |
3613 | if (c->type == set_cmd) | |
3614 | { | |
3615 | usr_cmd_cris_version_valid = 1; | |
3616 | ||
3617 | /* Update the current architecture, if needed. */ | |
3618 | memset (&info, 0, sizeof info); | |
3619 | if (!gdbarch_update_p (info)) | |
3620 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); | |
3621 | } | |
3622 | } | |
3623 | ||
3624 | static void | |
3625 | cris_mode_update (char *ignore_args, int from_tty, | |
3626 | struct cmd_list_element *c) | |
3627 | { | |
3628 | struct gdbarch_info info; | |
3629 | ||
3630 | /* From here on, trust the user's CRIS mode setting. */ | |
3631 | if (c->type == set_cmd) | |
3632 | { | |
3633 | usr_cmd_cris_mode_valid = 1; | |
3634 | ||
3635 | /* Update the current architecture, if needed. */ | |
3636 | memset (&info, 0, sizeof info); | |
3637 | if (!gdbarch_update_p (info)) | |
3638 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); | |
3639 | } | |
3640 | } | |
3641 | ||
3642 | static void | |
3643 | cris_abi_update (char *ignore_args, int from_tty, | |
3644 | struct cmd_list_element *c) | |
3645 | { | |
3646 | struct gdbarch_info info; | |
3647 | ||
3648 | /* From here on, trust the user's CRIS ABI setting. */ | |
3649 | if (c->type == set_cmd) | |
3650 | { | |
3651 | usr_cmd_cris_abi_valid = 1; | |
3652 | ||
3653 | /* Update the current architecture, if needed. */ | |
3654 | memset (&info, 0, sizeof info); | |
3655 | if (!gdbarch_update_p (info)) | |
3656 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); | |
3657 | } | |
3658 | } | |
3659 | ||
3660 | /* Copied from pa64solib.c, with a couple of minor changes. */ | |
3661 | ||
3662 | static CORE_ADDR | |
3663 | bfd_lookup_symbol (bfd *abfd, const char *symname) | |
3664 | { | |
3665 | unsigned int storage_needed; | |
3666 | asymbol *sym; | |
3667 | asymbol **symbol_table; | |
3668 | unsigned int number_of_symbols; | |
3669 | unsigned int i; | |
3670 | struct cleanup *back_to; | |
3671 | CORE_ADDR symaddr = 0; | |
3672 | ||
3673 | storage_needed = bfd_get_symtab_upper_bound (abfd); | |
3674 | ||
3675 | if (storage_needed > 0) | |
3676 | { | |
3677 | symbol_table = (asymbol **) xmalloc (storage_needed); | |
3678 | back_to = make_cleanup (free, (PTR) symbol_table); | |
3679 | number_of_symbols = bfd_canonicalize_symtab (abfd, symbol_table); | |
3680 | ||
3681 | for (i = 0; i < number_of_symbols; i++) | |
3682 | { | |
3683 | sym = *symbol_table++; | |
3684 | if (!strcmp (sym->name, symname)) | |
3685 | { | |
3686 | /* Bfd symbols are section relative. */ | |
3687 | symaddr = sym->value + sym->section->vma; | |
3688 | break; | |
3689 | } | |
3690 | } | |
3691 | do_cleanups (back_to); | |
3692 | } | |
3693 | return (symaddr); | |
3694 | } | |
3695 | ||
3696 | static struct gdbarch * | |
3697 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3698 | { | |
3699 | struct gdbarch *gdbarch; | |
3700 | struct gdbarch_tdep *tdep; | |
3701 | int cris_version; | |
3702 | const char *cris_mode; | |
3703 | const char *cris_abi; | |
3704 | CORE_ADDR cris_abi_sym = 0; | |
3705 | int register_bytes; | |
3706 | ||
3707 | if (usr_cmd_cris_version_valid) | |
3708 | { | |
3709 | /* Trust the user's CRIS version setting. */ | |
3710 | cris_version = usr_cmd_cris_version; | |
3711 | } | |
3712 | else | |
3713 | { | |
3714 | /* Assume it's CRIS version 10. */ | |
3715 | cris_version = 10; | |
3716 | } | |
3717 | ||
3718 | if (usr_cmd_cris_mode_valid) | |
3719 | { | |
3720 | /* Trust the user's CRIS mode setting. */ | |
3721 | cris_mode = usr_cmd_cris_mode; | |
3722 | } | |
3723 | else if (cris_version == 10) | |
3724 | { | |
3725 | /* Assume CRIS version 10 is in user mode. */ | |
3726 | cris_mode = CRIS_MODE_USER; | |
3727 | } | |
3728 | else | |
3729 | { | |
3730 | /* Strictly speaking, older CRIS version don't have a supervisor mode, | |
3731 | but we regard its only mode as supervisor mode. */ | |
3732 | cris_mode = CRIS_MODE_SUPERVISOR; | |
3733 | } | |
3734 | ||
3735 | if (usr_cmd_cris_abi_valid) | |
3736 | { | |
3737 | /* Trust the user's ABI setting. */ | |
3738 | cris_abi = usr_cmd_cris_abi; | |
3739 | } | |
3740 | else if (info.abfd) | |
3741 | { | |
3742 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
3743 | { | |
3744 | /* An elf target uses the new ABI. */ | |
3745 | cris_abi = CRIS_ABI_V2; | |
3746 | } | |
3747 | else if (bfd_get_flavour (info.abfd) == bfd_target_aout_flavour) | |
3748 | { | |
3749 | /* An a.out target may use either ABI. Look for hints in the | |
3750 | symbol table. */ | |
3751 | cris_abi_sym = bfd_lookup_symbol (info.abfd, CRIS_ABI_SYMBOL); | |
3752 | cris_abi = cris_abi_sym ? CRIS_ABI_V2 : CRIS_ABI_ORIGINAL; | |
3753 | } | |
3754 | else | |
3755 | { | |
3756 | /* Unknown bfd flavour. Assume it's the new ABI. */ | |
3757 | cris_abi = CRIS_ABI_V2; | |
3758 | } | |
3759 | } | |
3760 | else if (gdbarch_tdep (current_gdbarch)) | |
3761 | { | |
3762 | /* No bfd available. Stick with whatever ABI we're currently using. | |
3763 | (This is to avoid changing the ABI when the user updates the | |
3764 | architecture with the 'set cris-version' command.) */ | |
3765 | cris_abi = gdbarch_tdep (current_gdbarch)->cris_abi; | |
3766 | } | |
3767 | else | |
3768 | { | |
3769 | /* No bfd, and no current architecture available. Assume it's the | |
3770 | new ABI. */ | |
3771 | cris_abi = CRIS_ABI_V2; | |
3772 | } | |
3773 | ||
3774 | /* Make the current settings visible to the user. */ | |
3775 | usr_cmd_cris_version = cris_version; | |
3776 | usr_cmd_cris_mode = cris_mode; | |
3777 | usr_cmd_cris_abi = cris_abi; | |
3778 | ||
3779 | /* Find a candidate among the list of pre-declared architectures. Both | |
3780 | CRIS version and ABI must match. */ | |
3781 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
3782 | arches != NULL; | |
3783 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3784 | { | |
3785 | if ((gdbarch_tdep (arches->gdbarch)->cris_version == cris_version) | |
3786 | && (gdbarch_tdep (arches->gdbarch)->cris_mode == cris_mode) | |
3787 | && (gdbarch_tdep (arches->gdbarch)->cris_abi == cris_abi)) | |
3788 | return arches->gdbarch; | |
3789 | } | |
3790 | ||
3791 | /* No matching architecture was found. Create a new one. */ | |
3792 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
3793 | gdbarch = gdbarch_alloc (&info, tdep); | |
3794 | ||
3795 | tdep->cris_version = cris_version; | |
3796 | tdep->cris_mode = cris_mode; | |
3797 | tdep->cris_abi = cris_abi; | |
3798 | ||
3799 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
3800 | switch (info.byte_order) | |
3801 | { | |
3802 | case LITTLE_ENDIAN: | |
3803 | /* Ok. */ | |
3804 | break; | |
3805 | ||
3806 | case BIG_ENDIAN: | |
3807 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: big endian byte order in info"); | |
3808 | break; | |
3809 | ||
3810 | default: | |
3811 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown byte order in info"); | |
3812 | } | |
3813 | ||
3814 | /* Initialize the ABI dependent things. */ | |
3815 | if (tdep->cris_abi == CRIS_ABI_ORIGINAL) | |
3816 | { | |
3817 | set_gdbarch_double_bit (gdbarch, 32); | |
3818 | set_gdbarch_push_arguments (gdbarch, cris_abi_original_push_arguments); | |
3819 | set_gdbarch_store_return_value (gdbarch, | |
3820 | cris_abi_original_store_return_value); | |
3821 | set_gdbarch_extract_return_value | |
3822 | (gdbarch, cris_abi_original_extract_return_value); | |
3823 | set_gdbarch_reg_struct_has_addr | |
3824 | (gdbarch, cris_abi_original_reg_struct_has_addr); | |
3825 | } | |
3826 | else if (tdep->cris_abi == CRIS_ABI_V2) | |
3827 | { | |
3828 | set_gdbarch_double_bit (gdbarch, 64); | |
3829 | set_gdbarch_push_arguments (gdbarch, cris_abi_v2_push_arguments); | |
3830 | set_gdbarch_store_return_value (gdbarch, cris_abi_v2_store_return_value); | |
3831 | set_gdbarch_extract_return_value (gdbarch, | |
3832 | cris_abi_v2_extract_return_value); | |
3833 | set_gdbarch_reg_struct_has_addr (gdbarch, | |
3834 | cris_abi_v2_reg_struct_has_addr); | |
3835 | } | |
3836 | else | |
3837 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown CRIS ABI"); | |
3838 | ||
3839 | /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT, | |
3840 | which means we have to set this explicitly. */ | |
3841 | set_gdbarch_long_double_bit (gdbarch, 64); | |
3842 | ||
3843 | /* Floating point is IEEE compatible. */ | |
3844 | set_gdbarch_ieee_float (gdbarch, 1); | |
3845 | ||
3846 | /* There are 32 registers (some of which may not be implemented). */ | |
3847 | set_gdbarch_num_regs (gdbarch, 32); | |
3848 | set_gdbarch_sp_regnum (gdbarch, 14); | |
3849 | set_gdbarch_fp_regnum (gdbarch, 8); | |
3850 | set_gdbarch_pc_regnum (gdbarch, 15); | |
3851 | ||
3852 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
3853 | ||
3854 | /* Length of ordinary registers used in push_word and a few other places. | |
3855 | REGISTER_RAW_SIZE is the real way to know how big a register is. */ | |
3856 | set_gdbarch_register_size (gdbarch, 4); | |
3857 | ||
3858 | /* NEW */ | |
3859 | set_gdbarch_register_bytes_ok (gdbarch, cris_register_bytes_ok); | |
3860 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
3861 | ||
3862 | ||
3863 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
3864 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
3865 | ||
3866 | ||
3867 | /* The total amount of space needed to store (in an array called registers) | |
3868 | GDB's copy of the machine's register state. Note: We can not use | |
3869 | cris_register_size at this point, since it relies on current_gdbarch | |
3870 | being set. */ | |
3871 | switch (tdep->cris_version) | |
3872 | { | |
3873 | case 0: | |
3874 | case 1: | |
3875 | case 2: | |
3876 | case 3: | |
3877 | /* Support for these may be added later. */ | |
3878 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unsupported CRIS version"); | |
3879 | break; | |
3880 | ||
3881 | case 8: | |
3882 | case 9: | |
3883 | /* CRIS v8 and v9, a.k.a. ETRAX 100. General registers R0 - R15 | |
3884 | (32 bits), special registers P0 - P1 (8 bits), P4 - P5 (16 bits), | |
3885 | and P8 - P14 (32 bits). */ | |
3886 | register_bytes = (16 * 4) + (2 * 1) + (2 * 2) + (7 * 4); | |
3887 | break; | |
3888 | ||
3889 | case 10: | |
3890 | case 11: | |
3891 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
3892 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
3893 | register_bytes = (16 * 4) + (2 * 1) + (2 * 2) + (9 * 4); | |
3894 | break; | |
3895 | ||
3896 | default: | |
3897 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown CRIS version"); | |
3898 | } | |
3899 | ||
3900 | set_gdbarch_register_bytes (gdbarch, register_bytes); | |
3901 | ||
3902 | /* Returns the register offset for the first byte of register regno's space | |
3903 | in the saved register state. */ | |
3904 | set_gdbarch_register_byte (gdbarch, cris_register_offset); | |
3905 | ||
3906 | /* The length of the registers in the actual machine representation. */ | |
3907 | set_gdbarch_register_raw_size (gdbarch, cris_register_size); | |
3908 | ||
3909 | /* The largest value REGISTER_RAW_SIZE can have. */ | |
3910 | set_gdbarch_max_register_raw_size (gdbarch, 32); | |
3911 | ||
3912 | /* The length of the registers in the program's representation. */ | |
3913 | set_gdbarch_register_virtual_size (gdbarch, cris_register_size); | |
3914 | ||
3915 | /* The largest value REGISTER_VIRTUAL_SIZE can have. */ | |
3916 | set_gdbarch_max_register_virtual_size (gdbarch, 32); | |
3917 | ||
3918 | set_gdbarch_register_virtual_type (gdbarch, cris_register_virtual_type); | |
3919 | ||
3920 | /* Use generic dummy frames. */ | |
3921 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
3922 | ||
3923 | /* Where to execute the call in the memory segments. */ | |
3924 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
3925 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
3926 | ||
3927 | /* Start execution at the beginning of dummy. */ | |
3928 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
3929 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
3930 | ||
3931 | /* Set to 1 since call_dummy_breakpoint_offset was defined. */ | |
3932 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
3933 | ||
3934 | /* Read all about dummy frames in blockframe.c. */ | |
3935 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
3936 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); | |
3937 | ||
3938 | /* Defined to 1 to indicate that the target supports inferior function | |
3939 | calls. */ | |
3940 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
3941 | set_gdbarch_call_dummy_words (gdbarch, 0); | |
3942 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); | |
3943 | ||
3944 | /* No stack adjustment needed when peforming an inferior function call. */ | |
3945 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
3946 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
3947 | ||
3948 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
3949 | ||
3950 | /* No register requires conversion from raw format to virtual format. */ | |
3951 | set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not); | |
3952 | ||
3953 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
3954 | set_gdbarch_push_return_address (gdbarch, cris_push_return_address); | |
3955 | set_gdbarch_pop_frame (gdbarch, cris_pop_frame); | |
3956 | ||
3957 | set_gdbarch_store_struct_return (gdbarch, cris_store_struct_return); | |
3958 | set_gdbarch_extract_struct_value_address (gdbarch, | |
3959 | cris_extract_struct_value_address); | |
3960 | set_gdbarch_use_struct_convention (gdbarch, cris_use_struct_convention); | |
3961 | ||
3962 | set_gdbarch_frame_init_saved_regs (gdbarch, cris_frame_init_saved_regs); | |
3963 | set_gdbarch_init_extra_frame_info (gdbarch, cris_init_extra_frame_info); | |
3964 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); | |
3965 | set_gdbarch_prologue_frameless_p (gdbarch, generic_prologue_frameless_p); | |
3966 | ||
3967 | /* The stack grows downward. */ | |
3968 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3969 | ||
3970 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
3971 | ||
3972 | /* The PC must not be decremented after a breakpoint. (The breakpoint | |
3973 | handler takes care of that.) */ | |
3974 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
3975 | ||
3976 | /* Offset from address of function to start of its code. */ | |
3977 | set_gdbarch_function_start_offset (gdbarch, 0); | |
3978 | ||
3979 | /* The number of bytes at the start of arglist that are not really args, | |
3980 | 0 in the CRIS ABI. */ | |
3981 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
3982 | set_gdbarch_frameless_function_invocation | |
3983 | (gdbarch, cris_frameless_function_invocation); | |
3984 | set_gdbarch_frame_chain (gdbarch, cris_frame_chain); | |
3985 | set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid); | |
3986 | ||
3987 | set_gdbarch_frame_saved_pc (gdbarch, cris_frame_saved_pc); | |
3988 | set_gdbarch_frame_args_address (gdbarch, cris_frame_args_address); | |
3989 | set_gdbarch_frame_locals_address (gdbarch, cris_frame_locals_address); | |
3990 | set_gdbarch_saved_pc_after_call (gdbarch, cris_saved_pc_after_call); | |
3991 | ||
3992 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
3993 | ||
3994 | /* No extra stack alignment needed. Set to 1 by default. */ | |
3995 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); | |
3996 | ||
3997 | /* Helpful for backtracing and returning in a call dummy. */ | |
3998 | set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); | |
3999 | ||
4000 | return gdbarch; | |
4001 | } |