Commit | Line | Data |
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29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 | 2 | |
42a4f53d | 3 | Copyright (C) 2001-2019 Free Software Foundation, Inc. |
6b4d5c91 | 4 | |
29134980 OF |
5 | Contributed by Axis Communications AB. |
6 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
7 | ||
a9762ec7 | 8 | This file is part of GDB. |
29134980 | 9 | |
a9762ec7 JB |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 3 of the License, or | |
13 | (at your option) any later version. | |
29134980 | 14 | |
a9762ec7 JB |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
29134980 | 19 | |
a9762ec7 JB |
20 | You should have received a copy of the GNU General Public License |
21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
29134980 OF |
22 | |
23 | #include "defs.h" | |
d55e5aa6 TT |
24 | |
25 | /* Local non-gdb includes. */ | |
26 | #include "arch-utils.h" | |
27 | #include "cris-tdep.h" | |
28 | #include "dis-asm.h" | |
2e4b5889 | 29 | #include "dwarf2-frame.h" |
d55e5aa6 TT |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
32 | #include "frame.h" | |
29134980 | 33 | #include "gdbcmd.h" |
d55e5aa6 TT |
34 | #include "gdbcore.h" |
35 | #include "gdbtypes.h" | |
36 | #include "inferior.h" | |
37 | #include "objfiles.h" | |
29134980 | 38 | #include "opcode/cris.h" |
749c8b38 | 39 | #include "osabi.h" |
29134980 | 40 | #include "regcache.h" |
76a9d10f | 41 | #include "solib-svr4.h" |
d55e5aa6 TT |
42 | #include "solib.h" |
43 | #include "symtab.h" | |
44 | #include "target.h" | |
45 | #include "trad-frame.h" | |
46 | #include "value.h" | |
749c8b38 | 47 | |
29134980 OF |
48 | enum cris_num_regs |
49 | { | |
50 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
51 | NUM_FREGS = 0, | |
52 | ||
53 | /* There are 16 general registers. */ | |
54 | NUM_GENREGS = 16, | |
55 | ||
56 | /* There are 16 special registers. */ | |
c600d464 OF |
57 | NUM_SPECREGS = 16, |
58 | ||
59 | /* CRISv32 has a pseudo PC register, not noted here. */ | |
60 | ||
61 | /* CRISv32 has 16 support registers. */ | |
62 | NUM_SUPPREGS = 16 | |
29134980 OF |
63 | }; |
64 | ||
65 | /* Register numbers of various important registers. | |
2e4b5889 | 66 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
67 | STR_REGNUM Contains the address of structure return values. |
68 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
69 | ARG1_REGNUM Contains the first parameter to a function. | |
70 | ARG2_REGNUM Contains the second parameter to a function. | |
71 | ARG3_REGNUM Contains the third parameter to a function. | |
0963b4bd | 72 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. |
3e8c568d UW |
73 | gdbarch_sp_regnum Contains address of top of stack. |
74 | gdbarch_pc_regnum Contains address of next instruction. | |
29134980 OF |
75 | SRP_REGNUM Subroutine return pointer register. |
76 | BRP_REGNUM Breakpoint return pointer register. */ | |
77 | ||
29134980 OF |
78 | enum cris_regnums |
79 | { | |
80 | /* Enums with respect to the general registers, valid for all | |
c600d464 | 81 | CRIS versions. The frame pointer is always in R8. */ |
2e4b5889 | 82 | CRIS_FP_REGNUM = 8, |
c600d464 | 83 | /* ABI related registers. */ |
29134980 OF |
84 | STR_REGNUM = 9, |
85 | RET_REGNUM = 10, | |
86 | ARG1_REGNUM = 10, | |
87 | ARG2_REGNUM = 11, | |
88 | ARG3_REGNUM = 12, | |
89 | ARG4_REGNUM = 13, | |
90 | ||
c600d464 | 91 | /* Registers which happen to be common. */ |
29134980 | 92 | VR_REGNUM = 17, |
c600d464 OF |
93 | MOF_REGNUM = 23, |
94 | SRP_REGNUM = 27, | |
95 | ||
0963b4bd | 96 | /* CRISv10 et al. specific registers. */ |
c600d464 | 97 | P0_REGNUM = 16, |
29134980 OF |
98 | P4_REGNUM = 20, |
99 | CCR_REGNUM = 21, | |
29134980 OF |
100 | P8_REGNUM = 24, |
101 | IBR_REGNUM = 25, | |
102 | IRP_REGNUM = 26, | |
29134980 | 103 | BAR_REGNUM = 28, |
2a9ecef2 | 104 | DCCR_REGNUM = 29, |
29134980 | 105 | BRP_REGNUM = 30, |
c600d464 OF |
106 | USP_REGNUM = 31, |
107 | ||
108 | /* CRISv32 specific registers. */ | |
109 | ACR_REGNUM = 15, | |
110 | BZ_REGNUM = 16, | |
111 | PID_REGNUM = 18, | |
112 | SRS_REGNUM = 19, | |
113 | WZ_REGNUM = 20, | |
114 | EXS_REGNUM = 21, | |
115 | EDA_REGNUM = 22, | |
116 | DZ_REGNUM = 24, | |
117 | EBP_REGNUM = 25, | |
118 | ERP_REGNUM = 26, | |
119 | NRP_REGNUM = 28, | |
120 | CCS_REGNUM = 29, | |
121 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ | |
122 | SPC_REGNUM = 31, | |
123 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ | |
124 | ||
125 | S0_REGNUM = 33, | |
126 | S1_REGNUM = 34, | |
127 | S2_REGNUM = 35, | |
128 | S3_REGNUM = 36, | |
129 | S4_REGNUM = 37, | |
130 | S5_REGNUM = 38, | |
131 | S6_REGNUM = 39, | |
132 | S7_REGNUM = 40, | |
133 | S8_REGNUM = 41, | |
134 | S9_REGNUM = 42, | |
135 | S10_REGNUM = 43, | |
136 | S11_REGNUM = 44, | |
137 | S12_REGNUM = 45, | |
138 | S13_REGNUM = 46, | |
139 | S14_REGNUM = 47, | |
140 | S15_REGNUM = 48, | |
29134980 OF |
141 | }; |
142 | ||
143 | extern const struct cris_spec_reg cris_spec_regs[]; | |
144 | ||
145 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
0e6bdb31 | 146 | register names and sizes. */ |
e4286e57 | 147 | static unsigned int usr_cmd_cris_version; |
29134980 OF |
148 | |
149 | /* Indicates whether to trust the above variable. */ | |
150 | static int usr_cmd_cris_version_valid = 0; | |
151 | ||
41922353 OF |
152 | static const char cris_mode_normal[] = "normal"; |
153 | static const char cris_mode_guru[] = "guru"; | |
40478521 | 154 | static const char *const cris_modes[] = { |
0e6bdb31 OF |
155 | cris_mode_normal, |
156 | cris_mode_guru, | |
157 | 0 | |
158 | }; | |
159 | ||
160 | /* CRIS mode, set via the user command 'set cris-mode'. Affects | |
161 | type of break instruction among other things. */ | |
162 | static const char *usr_cmd_cris_mode = cris_mode_normal; | |
163 | ||
a5f6c8f5 OF |
164 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
165 | static int usr_cmd_cris_dwarf2_cfi = 1; | |
29134980 | 166 | |
a5f6c8f5 OF |
167 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
168 | ||
169 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ | |
170 | #define SIGTRAMP_OFFSET0 0 | |
171 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ | |
172 | #define SIGTRAMP_OFFSET1 4 | |
173 | ||
174 | static const unsigned short sigtramp_code[] = | |
175 | { | |
176 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ | |
177 | SIGTRAMP_INSN1 /* break 13 */ | |
178 | }; | |
179 | ||
180 | #define SIGTRAMP_LEN (sizeof sigtramp_code) | |
181 | ||
182 | /* Note: same length as normal sigtramp code. */ | |
183 | ||
184 | static const unsigned short rt_sigtramp_code[] = | |
29134980 | 185 | { |
a5f6c8f5 OF |
186 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
187 | SIGTRAMP_INSN1 /* break 13 */ | |
188 | }; | |
189 | ||
190 | /* If PC is in a sigtramp routine, return the address of the start of | |
191 | the routine. Otherwise, return 0. */ | |
192 | ||
193 | static CORE_ADDR | |
94afd7a6 | 194 | cris_sigtramp_start (struct frame_info *this_frame) |
a5f6c8f5 | 195 | { |
94afd7a6 | 196 | CORE_ADDR pc = get_frame_pc (this_frame); |
e2a2a3e8 | 197 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 | 198 | |
94afd7a6 | 199 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
200 | return 0; |
201 | ||
e2a2a3e8 | 202 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 203 | { |
e2a2a3e8 | 204 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
205 | return 0; |
206 | ||
207 | pc -= SIGTRAMP_OFFSET1; | |
94afd7a6 | 208 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
209 | return 0; |
210 | } | |
211 | ||
212 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) | |
213 | return 0; | |
214 | ||
215 | return pc; | |
216 | } | |
217 | ||
218 | /* If PC is in a RT sigtramp routine, return the address of the start of | |
219 | the routine. Otherwise, return 0. */ | |
220 | ||
221 | static CORE_ADDR | |
94afd7a6 | 222 | cris_rt_sigtramp_start (struct frame_info *this_frame) |
a5f6c8f5 | 223 | { |
94afd7a6 | 224 | CORE_ADDR pc = get_frame_pc (this_frame); |
e2a2a3e8 | 225 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 | 226 | |
94afd7a6 | 227 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
228 | return 0; |
229 | ||
e2a2a3e8 | 230 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 231 | { |
e2a2a3e8 | 232 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
233 | return 0; |
234 | ||
235 | pc -= SIGTRAMP_OFFSET1; | |
94afd7a6 | 236 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
a5f6c8f5 OF |
237 | return 0; |
238 | } | |
239 | ||
240 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) | |
241 | return 0; | |
242 | ||
243 | return pc; | |
244 | } | |
245 | ||
94afd7a6 UW |
246 | /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine, |
247 | return the address of the associated sigcontext structure. */ | |
a5f6c8f5 OF |
248 | |
249 | static CORE_ADDR | |
94afd7a6 | 250 | cris_sigcontext_addr (struct frame_info *this_frame) |
a5f6c8f5 | 251 | { |
e17a4113 UW |
252 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
253 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
a5f6c8f5 OF |
254 | CORE_ADDR pc; |
255 | CORE_ADDR sp; | |
e362b510 | 256 | gdb_byte buf[4]; |
a5f6c8f5 | 257 | |
e17a4113 UW |
258 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
259 | sp = extract_unsigned_integer (buf, 4, byte_order); | |
a5f6c8f5 OF |
260 | |
261 | /* Look for normal sigtramp frame first. */ | |
94afd7a6 | 262 | pc = cris_sigtramp_start (this_frame); |
a5f6c8f5 OF |
263 | if (pc) |
264 | { | |
265 | /* struct signal_frame (arch/cris/kernel/signal.c) contains | |
266 | struct sigcontext as its first member, meaning the SP points to | |
267 | it already. */ | |
268 | return sp; | |
269 | } | |
270 | ||
94afd7a6 | 271 | pc = cris_rt_sigtramp_start (this_frame); |
a5f6c8f5 OF |
272 | if (pc) |
273 | { | |
274 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains | |
275 | a struct ucontext, which in turn contains a struct sigcontext. | |
276 | Magic digging: | |
277 | 4 + 4 + 128 to struct ucontext, then | |
278 | 4 + 4 + 12 to struct sigcontext. */ | |
279 | return (sp + 156); | |
280 | } | |
281 | ||
8a3fe4f8 | 282 | error (_("Couldn't recognize signal trampoline.")); |
a5f6c8f5 | 283 | return 0; |
29134980 OF |
284 | } |
285 | ||
2e4b5889 | 286 | struct cris_unwind_cache |
29134980 | 287 | { |
2e4b5889 OF |
288 | /* The previous frame's inner most stack address. Used as this |
289 | frame ID's stack_addr. */ | |
290 | CORE_ADDR prev_sp; | |
291 | /* The frame's base, optionally used by the high-level debug info. */ | |
292 | CORE_ADDR base; | |
293 | int size; | |
294 | /* How far the SP and r8 (FP) have been offset from the start of | |
295 | the stack frame (as defined by the previous frame's stack | |
296 | pointer). */ | |
297 | LONGEST sp_offset; | |
298 | LONGEST r8_offset; | |
299 | int uses_frame; | |
300 | ||
301 | /* From old frame_extra_info struct. */ | |
29134980 OF |
302 | CORE_ADDR return_pc; |
303 | int leaf_function; | |
2e4b5889 OF |
304 | |
305 | /* Table indicating the location of each and every register. */ | |
306 | struct trad_frame_saved_reg *saved_regs; | |
29134980 OF |
307 | }; |
308 | ||
a5f6c8f5 | 309 | static struct cris_unwind_cache * |
94afd7a6 | 310 | cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame, |
a5f6c8f5 OF |
311 | void **this_cache) |
312 | { | |
94afd7a6 | 313 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
7fbe2eba | 314 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 315 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
a5f6c8f5 | 316 | struct cris_unwind_cache *info; |
a5f6c8f5 | 317 | CORE_ADDR addr; |
e362b510 | 318 | gdb_byte buf[4]; |
a5f6c8f5 OF |
319 | int i; |
320 | ||
321 | if ((*this_cache)) | |
9a3c8263 | 322 | return (struct cris_unwind_cache *) (*this_cache); |
a5f6c8f5 OF |
323 | |
324 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
325 | (*this_cache) = info; | |
94afd7a6 | 326 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
a5f6c8f5 OF |
327 | |
328 | /* Zero all fields. */ | |
329 | info->prev_sp = 0; | |
330 | info->base = 0; | |
331 | info->size = 0; | |
332 | info->sp_offset = 0; | |
333 | info->r8_offset = 0; | |
334 | info->uses_frame = 0; | |
335 | info->return_pc = 0; | |
336 | info->leaf_function = 0; | |
337 | ||
94afd7a6 | 338 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
e17a4113 | 339 | info->base = extract_unsigned_integer (buf, 4, byte_order); |
a5f6c8f5 | 340 | |
94afd7a6 | 341 | addr = cris_sigcontext_addr (this_frame); |
a5f6c8f5 OF |
342 | |
343 | /* Layout of the sigcontext struct: | |
344 | struct sigcontext { | |
345 | struct pt_regs regs; | |
346 | unsigned long oldmask; | |
347 | unsigned long usp; | |
348 | }; */ | |
349 | ||
c600d464 OF |
350 | if (tdep->cris_version == 10) |
351 | { | |
352 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in | |
353 | struct pt_regs. */ | |
354 | for (i = 0; i <= 13; i++) | |
355 | info->saved_regs[i].addr = addr + ((15 - i) * 4); | |
356 | ||
357 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); | |
358 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); | |
359 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); | |
360 | /* Note: IRP is off by 2 at this point. There's no point in correcting | |
361 | it though since that will mean that the backtrace will show a PC | |
362 | different from what is shown when stopped. */ | |
363 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); | |
7fbe2eba | 364 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 365 | = info->saved_regs[IRP_REGNUM]; |
7fbe2eba | 366 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4); |
c600d464 OF |
367 | } |
368 | else | |
369 | { | |
370 | /* CRISv32. */ | |
371 | /* R0 to R13 are stored in order at offset (1 * 4) in | |
372 | struct pt_regs. */ | |
373 | for (i = 0; i <= 13; i++) | |
374 | info->saved_regs[i].addr = addr + ((i + 1) * 4); | |
375 | ||
376 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); | |
377 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); | |
378 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); | |
379 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); | |
380 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); | |
381 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); | |
382 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); | |
383 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); | |
384 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); | |
385 | ||
386 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
387 | be wrong at this point. This problem manifests itself in the | |
388 | sigaltstack.exp test case, which occasionally generates FAILs when | |
0963b4bd | 389 | the signal is received while in a delay slot. |
c600d464 OF |
390 | |
391 | This could be solved by a couple of read_memory_unsigned_integer and a | |
392 | trad_frame_set_value. */ | |
7fbe2eba | 393 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 394 | = info->saved_regs[ERP_REGNUM]; |
c600d464 | 395 | |
7fbe2eba | 396 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr |
3e8c568d | 397 | = addr + (25 * 4); |
c600d464 | 398 | } |
a5f6c8f5 OF |
399 | |
400 | return info; | |
401 | } | |
402 | ||
403 | static void | |
94afd7a6 | 404 | cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
a5f6c8f5 OF |
405 | struct frame_id *this_id) |
406 | { | |
407 | struct cris_unwind_cache *cache = | |
94afd7a6 UW |
408 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
409 | (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame)); | |
a5f6c8f5 OF |
410 | } |
411 | ||
412 | /* Forward declaration. */ | |
413 | ||
94afd7a6 UW |
414 | static struct value *cris_frame_prev_register (struct frame_info *this_frame, |
415 | void **this_cache, int regnum); | |
416 | static struct value * | |
417 | cris_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
418 | void **this_cache, int regnum) | |
a5f6c8f5 OF |
419 | { |
420 | /* Make sure we've initialized the cache. */ | |
94afd7a6 UW |
421 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
422 | return cris_frame_prev_register (this_frame, this_cache, regnum); | |
423 | } | |
424 | ||
425 | static int | |
426 | cris_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
427 | struct frame_info *this_frame, | |
428 | void **this_cache) | |
429 | { | |
430 | if (cris_sigtramp_start (this_frame) | |
431 | || cris_rt_sigtramp_start (this_frame)) | |
432 | return 1; | |
433 | ||
434 | return 0; | |
a5f6c8f5 OF |
435 | } |
436 | ||
437 | static const struct frame_unwind cris_sigtramp_frame_unwind = | |
438 | { | |
439 | SIGTRAMP_FRAME, | |
8fbca658 | 440 | default_frame_unwind_stop_reason, |
a5f6c8f5 | 441 | cris_sigtramp_frame_this_id, |
94afd7a6 UW |
442 | cris_sigtramp_frame_prev_register, |
443 | NULL, | |
444 | cris_sigtramp_frame_sniffer | |
a5f6c8f5 OF |
445 | }; |
446 | ||
63807e1d | 447 | static int |
c600d464 OF |
448 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, |
449 | struct frame_info *this_frame) | |
450 | { | |
7fbe2eba | 451 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c600d464 OF |
452 | ULONGEST erp; |
453 | int ret = 0; | |
c600d464 | 454 | |
35488783 | 455 | if (tdep->cris_mode == cris_mode_guru) |
395f2fc2 | 456 | erp = get_frame_register_unsigned (this_frame, NRP_REGNUM); |
0e6bdb31 | 457 | else |
395f2fc2 | 458 | erp = get_frame_register_unsigned (this_frame, ERP_REGNUM); |
c600d464 OF |
459 | |
460 | if (erp & 0x1) | |
461 | { | |
462 | /* In delay slot - check if there's a breakpoint at the preceding | |
463 | instruction. */ | |
6c95b8df | 464 | if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1)) |
c600d464 OF |
465 | ret = 1; |
466 | } | |
467 | return ret; | |
468 | } | |
469 | ||
29134980 | 470 | /* The instruction environment needed to find single-step breakpoints. */ |
c600d464 | 471 | |
29134980 OF |
472 | typedef |
473 | struct instruction_environment | |
474 | { | |
475 | unsigned long reg[NUM_GENREGS]; | |
476 | unsigned long preg[NUM_SPECREGS]; | |
477 | unsigned long branch_break_address; | |
478 | unsigned long delay_slot_pc; | |
479 | unsigned long prefix_value; | |
480 | int branch_found; | |
481 | int prefix_found; | |
482 | int invalid; | |
483 | int slot_needed; | |
484 | int delay_slot_pc_active; | |
485 | int xflag_found; | |
486 | int disable_interrupt; | |
78c5b882 | 487 | enum bfd_endian byte_order; |
29134980 OF |
488 | } inst_env_type; |
489 | ||
29134980 OF |
490 | /* Machine-dependencies in CRIS for opcodes. */ |
491 | ||
492 | /* Instruction sizes. */ | |
493 | enum cris_instruction_sizes | |
494 | { | |
495 | INST_BYTE_SIZE = 0, | |
496 | INST_WORD_SIZE = 1, | |
497 | INST_DWORD_SIZE = 2 | |
498 | }; | |
499 | ||
500 | /* Addressing modes. */ | |
501 | enum cris_addressing_modes | |
502 | { | |
503 | REGISTER_MODE = 1, | |
504 | INDIRECT_MODE = 2, | |
505 | AUTOINC_MODE = 3 | |
506 | }; | |
507 | ||
508 | /* Prefix addressing modes. */ | |
509 | enum cris_prefix_addressing_modes | |
510 | { | |
511 | PREFIX_INDEX_MODE = 2, | |
512 | PREFIX_ASSIGN_MODE = 3, | |
513 | ||
514 | /* Handle immediate byte offset addressing mode prefix format. */ | |
515 | PREFIX_OFFSET_MODE = 2 | |
516 | }; | |
517 | ||
518 | /* Masks for opcodes. */ | |
519 | enum cris_opcode_masks | |
520 | { | |
521 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
522 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
523 | SIGNED_BYTE_MASK = 0x80, | |
524 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
525 | SIGNED_WORD_MASK = 0x8000, | |
526 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
527 | SIGNED_DWORD_MASK = 0x80000000, | |
528 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
529 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
530 | }; | |
531 | ||
532 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
533 | Bit 15 - 12 Operand2 | |
534 | 11 - 10 Mode | |
535 | 9 - 6 Opcode | |
536 | 5 - 4 Size | |
537 | 3 - 0 Operand1 */ | |
538 | ||
539 | static int | |
540 | cris_get_operand2 (unsigned short insn) | |
541 | { | |
542 | return ((insn & 0xF000) >> 12); | |
543 | } | |
544 | ||
545 | static int | |
546 | cris_get_mode (unsigned short insn) | |
547 | { | |
548 | return ((insn & 0x0C00) >> 10); | |
549 | } | |
550 | ||
551 | static int | |
552 | cris_get_opcode (unsigned short insn) | |
553 | { | |
554 | return ((insn & 0x03C0) >> 6); | |
555 | } | |
556 | ||
557 | static int | |
558 | cris_get_size (unsigned short insn) | |
559 | { | |
560 | return ((insn & 0x0030) >> 4); | |
561 | } | |
562 | ||
563 | static int | |
564 | cris_get_operand1 (unsigned short insn) | |
565 | { | |
566 | return (insn & 0x000F); | |
567 | } | |
568 | ||
569 | /* Additional functions in order to handle opcodes. */ | |
570 | ||
29134980 OF |
571 | static int |
572 | cris_get_quick_value (unsigned short insn) | |
573 | { | |
574 | return (insn & 0x003F); | |
575 | } | |
576 | ||
577 | static int | |
578 | cris_get_bdap_quick_offset (unsigned short insn) | |
579 | { | |
580 | return (insn & 0x00FF); | |
581 | } | |
582 | ||
583 | static int | |
584 | cris_get_branch_short_offset (unsigned short insn) | |
585 | { | |
586 | return (insn & 0x00FF); | |
587 | } | |
588 | ||
589 | static int | |
590 | cris_get_asr_shift_steps (unsigned long value) | |
591 | { | |
592 | return (value & 0x3F); | |
593 | } | |
594 | ||
29134980 OF |
595 | static int |
596 | cris_get_clear_size (unsigned short insn) | |
597 | { | |
598 | return ((insn) & 0xC000); | |
599 | } | |
600 | ||
601 | static int | |
602 | cris_is_signed_extend_bit_on (unsigned short insn) | |
603 | { | |
604 | return (((insn) & 0x20) == 0x20); | |
605 | } | |
606 | ||
607 | static int | |
608 | cris_is_xflag_bit_on (unsigned short insn) | |
609 | { | |
610 | return (((insn) & 0x1000) == 0x1000); | |
611 | } | |
612 | ||
613 | static void | |
614 | cris_set_size_to_dword (unsigned short *insn) | |
615 | { | |
616 | *insn &= 0xFFCF; | |
617 | *insn |= 0x20; | |
618 | } | |
619 | ||
8535cb38 | 620 | static signed char |
29134980 OF |
621 | cris_get_signed_offset (unsigned short insn) |
622 | { | |
8535cb38 | 623 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
624 | } |
625 | ||
626 | /* Calls an op function given the op-type, working on the insn and the | |
627 | inst_env. */ | |
be8626e0 MD |
628 | static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short, |
629 | inst_env_type *); | |
29134980 | 630 | |
29134980 OF |
631 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
632 | struct gdbarch_list *); | |
633 | ||
29134980 OF |
634 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
635 | ||
eb4c3f4a | 636 | static void set_cris_version (const char *ignore_args, int from_tty, |
a5f6c8f5 | 637 | struct cmd_list_element *c); |
29134980 | 638 | |
eb4c3f4a | 639 | static void set_cris_mode (const char *ignore_args, int from_tty, |
0e6bdb31 OF |
640 | struct cmd_list_element *c); |
641 | ||
eb4c3f4a | 642 | static void set_cris_dwarf2_cfi (const char *ignore_args, int from_tty, |
a5f6c8f5 | 643 | struct cmd_list_element *c); |
29134980 | 644 | |
2e4b5889 | 645 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
94afd7a6 | 646 | struct frame_info *this_frame, |
2e4b5889 OF |
647 | struct cris_unwind_cache *info); |
648 | ||
5114e29d | 649 | static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc, |
94afd7a6 | 650 | struct frame_info *this_frame, |
5114e29d OF |
651 | struct cris_unwind_cache *info); |
652 | ||
2e4b5889 | 653 | /* When arguments must be pushed onto the stack, they go on in reverse |
0963b4bd | 654 | order. The below implements a FILO (stack) to do this. |
a5f6c8f5 | 655 | Copied from d10v-tdep.c. */ |
2e4b5889 OF |
656 | |
657 | struct stack_item | |
658 | { | |
659 | int len; | |
660 | struct stack_item *prev; | |
7c543f7b | 661 | gdb_byte *data; |
2e4b5889 OF |
662 | }; |
663 | ||
664 | static struct stack_item * | |
948f8e3d | 665 | push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len) |
2e4b5889 | 666 | { |
8d749320 | 667 | struct stack_item *si = XNEW (struct stack_item); |
7c543f7b | 668 | si->data = (gdb_byte *) xmalloc (len); |
2e4b5889 OF |
669 | si->len = len; |
670 | si->prev = prev; | |
671 | memcpy (si->data, contents, len); | |
672 | return si; | |
673 | } | |
674 | ||
675 | static struct stack_item * | |
676 | pop_stack_item (struct stack_item *si) | |
677 | { | |
678 | struct stack_item *dead = si; | |
679 | si = si->prev; | |
680 | xfree (dead->data); | |
681 | xfree (dead); | |
682 | return si; | |
683 | } | |
684 | ||
685 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
686 | the saved registers of frame described by FRAME_INFO. This | |
687 | includes special registers such as pc and fp saved in special ways | |
688 | in the stack frame. sp is even more special: the address we return | |
a5f6c8f5 | 689 | for it IS the sp for the next frame. */ |
2e4b5889 | 690 | |
63807e1d | 691 | static struct cris_unwind_cache * |
94afd7a6 | 692 | cris_frame_unwind_cache (struct frame_info *this_frame, |
2e4b5889 OF |
693 | void **this_prologue_cache) |
694 | { | |
35488783 UW |
695 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
696 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2e4b5889 | 697 | struct cris_unwind_cache *info; |
2e4b5889 OF |
698 | |
699 | if ((*this_prologue_cache)) | |
9a3c8263 | 700 | return (struct cris_unwind_cache *) (*this_prologue_cache); |
2e4b5889 OF |
701 | |
702 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
703 | (*this_prologue_cache) = info; | |
94afd7a6 | 704 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
2e4b5889 OF |
705 | |
706 | /* Zero all fields. */ | |
707 | info->prev_sp = 0; | |
708 | info->base = 0; | |
709 | info->size = 0; | |
710 | info->sp_offset = 0; | |
711 | info->r8_offset = 0; | |
712 | info->uses_frame = 0; | |
713 | info->return_pc = 0; | |
714 | info->leaf_function = 0; | |
715 | ||
716 | /* Prologue analysis does the rest... */ | |
35488783 | 717 | if (tdep->cris_version == 32) |
94afd7a6 | 718 | crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info); |
5114e29d | 719 | else |
94afd7a6 | 720 | cris_scan_prologue (get_frame_func (this_frame), this_frame, info); |
2e4b5889 OF |
721 | |
722 | return info; | |
723 | } | |
724 | ||
725 | /* Given a GDB frame, determine the address of the calling function's | |
726 | frame. This will be used to create a new GDB frame struct. */ | |
727 | ||
728 | static void | |
94afd7a6 | 729 | cris_frame_this_id (struct frame_info *this_frame, |
2e4b5889 OF |
730 | void **this_prologue_cache, |
731 | struct frame_id *this_id) | |
732 | { | |
733 | struct cris_unwind_cache *info | |
94afd7a6 | 734 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
2e4b5889 OF |
735 | CORE_ADDR base; |
736 | CORE_ADDR func; | |
737 | struct frame_id id; | |
738 | ||
739 | /* The FUNC is easy. */ | |
94afd7a6 | 740 | func = get_frame_func (this_frame); |
2e4b5889 OF |
741 | |
742 | /* Hopefully the prologue analysis either correctly determined the | |
743 | frame's base (which is the SP from the previous frame), or set | |
744 | that base to "NULL". */ | |
745 | base = info->prev_sp; | |
746 | if (base == 0) | |
747 | return; | |
748 | ||
749 | id = frame_id_build (base, func); | |
750 | ||
751 | (*this_id) = id; | |
752 | } | |
753 | ||
94afd7a6 UW |
754 | static struct value * |
755 | cris_frame_prev_register (struct frame_info *this_frame, | |
756 | void **this_prologue_cache, int regnum) | |
2e4b5889 OF |
757 | { |
758 | struct cris_unwind_cache *info | |
94afd7a6 UW |
759 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
760 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2e4b5889 OF |
761 | } |
762 | ||
2e4b5889 OF |
763 | static CORE_ADDR |
764 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
765 | { | |
766 | /* Align to the size of an instruction (so that they can safely be | |
767 | pushed onto the stack). */ | |
768 | return sp & ~3; | |
769 | } | |
770 | ||
771 | static CORE_ADDR | |
772 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
82585c72 | 773 | CORE_ADDR sp, CORE_ADDR funaddr, |
2e4b5889 OF |
774 | struct value **args, int nargs, |
775 | struct type *value_type, | |
e4fd649a UW |
776 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
777 | struct regcache *regcache) | |
2e4b5889 OF |
778 | { |
779 | /* Allocate space sufficient for a breakpoint. */ | |
780 | sp = (sp - 4) & ~3; | |
781 | /* Store the address of that breakpoint */ | |
782 | *bp_addr = sp; | |
783 | /* CRIS always starts the call at the callee's entry point. */ | |
784 | *real_pc = funaddr; | |
785 | return sp; | |
786 | } | |
787 | ||
788 | static CORE_ADDR | |
7d9b040b | 789 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2e4b5889 OF |
790 | struct regcache *regcache, CORE_ADDR bp_addr, |
791 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
792 | function_call_return_method return_method, |
793 | CORE_ADDR struct_addr) | |
2e4b5889 | 794 | { |
e17a4113 | 795 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2e4b5889 OF |
796 | int argreg; |
797 | int argnum; | |
798 | ||
2e4b5889 OF |
799 | struct stack_item *si = NULL; |
800 | ||
a5f6c8f5 | 801 | /* Push the return address. */ |
2e4b5889 OF |
802 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
803 | ||
804 | /* Are we returning a value using a structure return or a normal value | |
805 | return? struct_addr is the address of the reserved space for the return | |
806 | structure to be written on the stack. */ | |
cf84fa6b AH |
807 | if (return_method == return_method_struct) |
808 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
2e4b5889 OF |
809 | |
810 | /* Now load as many as possible of the first arguments into registers, | |
811 | and push the rest onto the stack. */ | |
812 | argreg = ARG1_REGNUM; | |
2e4b5889 OF |
813 | |
814 | for (argnum = 0; argnum < nargs; argnum++) | |
815 | { | |
816 | int len; | |
948f8e3d | 817 | const gdb_byte *val; |
2e4b5889 OF |
818 | int reg_demand; |
819 | int i; | |
820 | ||
4991999e | 821 | len = TYPE_LENGTH (value_type (args[argnum])); |
948f8e3d | 822 | val = value_contents (args[argnum]); |
2e4b5889 OF |
823 | |
824 | /* How may registers worth of storage do we need for this argument? */ | |
825 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
826 | ||
827 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
828 | { | |
829 | /* Data passed by value. Fits in available register(s). */ | |
830 | for (i = 0; i < reg_demand; i++) | |
831 | { | |
b66f5587 | 832 | regcache->cooked_write (argreg, val); |
2e4b5889 OF |
833 | argreg++; |
834 | val += 4; | |
835 | } | |
836 | } | |
837 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) | |
838 | { | |
839 | /* Data passed by value. Does not fit in available register(s). | |
840 | Use the register(s) first, then the stack. */ | |
841 | for (i = 0; i < reg_demand; i++) | |
842 | { | |
843 | if (argreg <= ARG4_REGNUM) | |
844 | { | |
b66f5587 | 845 | regcache->cooked_write (argreg, val); |
2e4b5889 OF |
846 | argreg++; |
847 | val += 4; | |
848 | } | |
849 | else | |
850 | { | |
851 | /* Push item for later so that pushed arguments | |
852 | come in the right order. */ | |
853 | si = push_stack_item (si, val, 4); | |
854 | val += 4; | |
855 | } | |
856 | } | |
857 | } | |
858 | else if (len > (2 * 4)) | |
859 | { | |
f6e56ab3 UW |
860 | /* Data passed by reference. Push copy of data onto stack |
861 | and pass pointer to this copy as argument. */ | |
862 | sp = (sp - len) & ~3; | |
863 | write_memory (sp, val, len); | |
864 | ||
865 | if (argreg <= ARG4_REGNUM) | |
866 | { | |
867 | regcache_cooked_write_unsigned (regcache, argreg, sp); | |
868 | argreg++; | |
869 | } | |
870 | else | |
871 | { | |
872 | gdb_byte buf[4]; | |
e17a4113 | 873 | store_unsigned_integer (buf, 4, byte_order, sp); |
f6e56ab3 UW |
874 | si = push_stack_item (si, buf, 4); |
875 | } | |
2e4b5889 OF |
876 | } |
877 | else | |
878 | { | |
879 | /* Data passed by value. No available registers. Put it on | |
880 | the stack. */ | |
881 | si = push_stack_item (si, val, len); | |
882 | } | |
883 | } | |
884 | ||
885 | while (si) | |
886 | { | |
887 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
888 | the function prologue. */ | |
889 | sp = (sp - si->len) & ~3; | |
890 | write_memory (sp, si->data, si->len); | |
891 | si = pop_stack_item (si); | |
892 | } | |
893 | ||
894 | /* Finally, update the SP register. */ | |
7fbe2eba | 895 | regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp); |
2e4b5889 OF |
896 | |
897 | return sp; | |
898 | } | |
899 | ||
e2a2a3e8 OF |
900 | static const struct frame_unwind cris_frame_unwind = |
901 | { | |
2e4b5889 | 902 | NORMAL_FRAME, |
8fbca658 | 903 | default_frame_unwind_stop_reason, |
2e4b5889 | 904 | cris_frame_this_id, |
94afd7a6 UW |
905 | cris_frame_prev_register, |
906 | NULL, | |
907 | default_frame_sniffer | |
2e4b5889 OF |
908 | }; |
909 | ||
2e4b5889 | 910 | static CORE_ADDR |
94afd7a6 | 911 | cris_frame_base_address (struct frame_info *this_frame, void **this_cache) |
2e4b5889 OF |
912 | { |
913 | struct cris_unwind_cache *info | |
94afd7a6 | 914 | = cris_frame_unwind_cache (this_frame, this_cache); |
2e4b5889 OF |
915 | return info->base; |
916 | } | |
917 | ||
e2a2a3e8 OF |
918 | static const struct frame_base cris_frame_base = |
919 | { | |
2e4b5889 OF |
920 | &cris_frame_unwind, |
921 | cris_frame_base_address, | |
922 | cris_frame_base_address, | |
923 | cris_frame_base_address | |
924 | }; | |
925 | ||
29134980 OF |
926 | /* Frames information. The definition of the struct frame_info is |
927 | ||
928 | CORE_ADDR frame | |
929 | CORE_ADDR pc | |
5a203e44 | 930 | enum frame_type type; |
29134980 OF |
931 | CORE_ADDR return_pc |
932 | int leaf_function | |
933 | ||
934 | If the compilation option -fno-omit-frame-pointer is present the | |
935 | variable frame will be set to the content of R8 which is the frame | |
936 | pointer register. | |
937 | ||
938 | The variable pc contains the address where execution is performed | |
939 | in the present frame. The innermost frame contains the current content | |
940 | of the register PC. All other frames contain the content of the | |
941 | register PC in the next frame. | |
942 | ||
5a203e44 AC |
943 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
944 | (associated with a signal handler), dummy (associated with a dummy | |
945 | frame). | |
29134980 OF |
946 | |
947 | The variable return_pc contains the address where execution should be | |
948 | resumed when the present frame has finished, the return address. | |
949 | ||
950 | The variable leaf_function is 1 if the return address is in the register | |
951 | SRP, and 0 if it is on the stack. | |
952 | ||
953 | Prologue instructions C-code. | |
954 | The prologue may consist of (-fno-omit-frame-pointer) | |
955 | 1) 2) | |
956 | push srp | |
957 | push r8 push r8 | |
958 | move.d sp,r8 move.d sp,r8 | |
959 | subq X,sp subq X,sp | |
960 | movem rY,[sp] movem rY,[sp] | |
961 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
962 | ||
963 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
964 | ||
965 | Note that this assumption is extremely brittle, and will break at the | |
966 | slightest change in GCC's prologue. | |
967 | ||
968 | If local variables are declared or register contents are saved on stack | |
969 | the subq-instruction will be present with X as the number of bytes | |
970 | needed for storage. The reshuffle with respect to r8 may be performed | |
971 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
0963b4bd | 972 | The offset U should be representable by a signed 8-bit value in all cases. |
29134980 OF |
973 | Thus, the prefix word is assumed to be immediate byte offset mode followed |
974 | by another word containing the instruction. | |
975 | ||
976 | Degenerate cases: | |
977 | 3) | |
978 | push r8 | |
979 | move.d sp,r8 | |
980 | move.d r8,sp | |
981 | pop r8 | |
982 | ||
983 | Prologue instructions C++-code. | |
984 | Case 1) and 2) in the C-code may be followed by | |
985 | ||
986 | move.d r10,rS ; this | |
987 | move.d r11,rT ; P1 | |
988 | move.d r12,rU ; P2 | |
989 | move.d r13,rV ; P3 | |
990 | move.S [r8+U],rZ ; P4 | |
991 | ||
0963b4bd | 992 | if any of the call parameters are stored. The host expects these |
29134980 OF |
993 | instructions to be executed in order to get the call parameters right. */ |
994 | ||
995 | /* Examine the prologue of a function. The variable ip is the address of | |
996 | the first instruction of the prologue. The variable limit is the address | |
997 | of the first instruction after the prologue. The variable fi contains the | |
998 | information in struct frame_info. The variable frameless_p controls whether | |
999 | the entire prologue is examined (0) or just enough instructions to | |
1000 | determine that it is a prologue (1). */ | |
1001 | ||
a78f21af | 1002 | static CORE_ADDR |
94afd7a6 | 1003 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame, |
2e4b5889 | 1004 | struct cris_unwind_cache *info) |
29134980 | 1005 | { |
94afd7a6 | 1006 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 UW |
1007 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1008 | ||
29134980 OF |
1009 | /* Present instruction. */ |
1010 | unsigned short insn; | |
1011 | ||
1012 | /* Next instruction, lookahead. */ | |
1013 | unsigned short insn_next; | |
1014 | int regno; | |
1015 | ||
29134980 OF |
1016 | /* Number of byte on stack used for local variables and movem. */ |
1017 | int val; | |
1018 | ||
1019 | /* Highest register number in a movem. */ | |
1020 | int regsave; | |
1021 | ||
1022 | /* move.d r<source_register>,rS */ | |
1023 | short source_register; | |
1024 | ||
2e4b5889 OF |
1025 | /* Scan limit. */ |
1026 | int limit; | |
29134980 | 1027 | |
2e4b5889 OF |
1028 | /* This frame is with respect to a leaf until a push srp is found. */ |
1029 | if (info) | |
1030 | { | |
1031 | info->leaf_function = 1; | |
1032 | } | |
29134980 OF |
1033 | |
1034 | /* Assume nothing on stack. */ | |
1035 | val = 0; | |
1036 | regsave = -1; | |
1037 | ||
94afd7a6 | 1038 | /* If we were called without a this_frame, that means we were called |
2e4b5889 OF |
1039 | from cris_skip_prologue which already tried to find the end of the |
1040 | prologue through the symbol information. 64 instructions past current | |
1041 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
94afd7a6 | 1042 | limit = this_frame ? get_frame_pc (this_frame) : pc + 64; |
29134980 | 1043 | |
29134980 | 1044 | /* Find the prologue instructions. */ |
a5f6c8f5 | 1045 | while (pc > 0 && pc < limit) |
29134980 | 1046 | { |
e17a4113 | 1047 | insn = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1048 | pc += 2; |
29134980 OF |
1049 | if (insn == 0xE1FC) |
1050 | { | |
0963b4bd | 1051 | /* push <reg> 32 bit instruction. */ |
e17a4113 | 1052 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1053 | pc += 2; |
29134980 | 1054 | regno = cris_get_operand2 (insn_next); |
2e4b5889 OF |
1055 | if (info) |
1056 | { | |
1057 | info->sp_offset += 4; | |
1058 | } | |
dbbff683 OF |
1059 | /* This check, meant to recognize srp, used to be regno == |
1060 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
1061 | if (insn_next == 0xBE7E) | |
29134980 | 1062 | { |
2e4b5889 OF |
1063 | if (info) |
1064 | { | |
1065 | info->leaf_function = 0; | |
1066 | } | |
29134980 | 1067 | } |
b4206d25 OF |
1068 | else if (insn_next == 0x8FEE) |
1069 | { | |
1070 | /* push $r8 */ | |
1071 | if (info) | |
1072 | { | |
1073 | info->r8_offset = info->sp_offset; | |
1074 | } | |
1075 | } | |
29134980 OF |
1076 | } |
1077 | else if (insn == 0x866E) | |
1078 | { | |
1079 | /* move.d sp,r8 */ | |
2e4b5889 OF |
1080 | if (info) |
1081 | { | |
1082 | info->uses_frame = 1; | |
2e4b5889 | 1083 | } |
29134980 OF |
1084 | continue; |
1085 | } | |
7fbe2eba | 1086 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
29134980 OF |
1087 | && cris_get_mode (insn) == 0x0000 |
1088 | && cris_get_opcode (insn) == 0x000A) | |
1089 | { | |
1090 | /* subq <val>,sp */ | |
2e4b5889 OF |
1091 | if (info) |
1092 | { | |
1093 | info->sp_offset += cris_get_quick_value (insn); | |
1094 | } | |
29134980 OF |
1095 | } |
1096 | else if (cris_get_mode (insn) == 0x0002 | |
1097 | && cris_get_opcode (insn) == 0x000F | |
1098 | && cris_get_size (insn) == 0x0003 | |
7fbe2eba | 1099 | && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch)) |
29134980 OF |
1100 | { |
1101 | /* movem r<regsave>,[sp] */ | |
29134980 OF |
1102 | regsave = cris_get_operand2 (insn); |
1103 | } | |
7fbe2eba | 1104 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
29134980 OF |
1105 | && ((insn & 0x0F00) >> 8) == 0x0001 |
1106 | && (cris_get_signed_offset (insn) < 0)) | |
1107 | { | |
1108 | /* Immediate byte offset addressing prefix word with sp as base | |
1109 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
1110 | is between 64 and 128. | |
1111 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
1112 | if (info) |
1113 | { | |
1114 | info->sp_offset += -cris_get_signed_offset (insn); | |
1115 | } | |
e17a4113 | 1116 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1117 | pc += 2; |
29134980 OF |
1118 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
1119 | && cris_get_opcode (insn_next) == 0x000F | |
1120 | && cris_get_size (insn_next) == 0x0003 | |
3e8c568d | 1121 | && cris_get_operand1 (insn_next) == gdbarch_sp_regnum |
7fbe2eba | 1122 | (gdbarch)) |
29134980 | 1123 | { |
29134980 OF |
1124 | regsave = cris_get_operand2 (insn_next); |
1125 | } | |
1126 | else | |
1127 | { | |
1128 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1129 | pc -= 4; |
29134980 OF |
1130 | break; |
1131 | } | |
1132 | } | |
1133 | else if (cris_get_mode (insn) == 0x0001 | |
1134 | && cris_get_opcode (insn) == 0x0009 | |
1135 | && cris_get_size (insn) == 0x0002) | |
1136 | { | |
1137 | /* move.d r<10..13>,r<0..15> */ | |
29134980 | 1138 | source_register = cris_get_operand1 (insn); |
2a9ecef2 OF |
1139 | |
1140 | /* FIXME? In the glibc solibs, the prologue might contain something | |
1141 | like (this example taken from relocate_doit): | |
1142 | move.d $pc,$r0 | |
1143 | sub.d 0xfffef426,$r0 | |
1144 | which isn't covered by the source_register check below. Question | |
1145 | is whether to add a check for this combo, or make better use of | |
1146 | the limit variable instead. */ | |
29134980 OF |
1147 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
1148 | { | |
1149 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1150 | pc -= 2; |
29134980 OF |
1151 | break; |
1152 | } | |
1153 | } | |
2e4b5889 | 1154 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1155 | /* The size is a fixed-size. */ |
1156 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1157 | /* A negative offset. */ | |
1158 | && (cris_get_signed_offset (insn) < 0)) | |
1159 | { | |
1160 | /* move.S rZ,[r8-U] (?) */ | |
e17a4113 | 1161 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1162 | pc += 2; |
29134980 | 1163 | regno = cris_get_operand2 (insn_next); |
7fbe2eba | 1164 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
29134980 OF |
1165 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
1166 | && cris_get_opcode (insn_next) == 0x000F) | |
1167 | { | |
1168 | /* move.S rZ,[r8-U] */ | |
1169 | continue; | |
1170 | } | |
1171 | else | |
1172 | { | |
1173 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1174 | pc -= 4; |
29134980 OF |
1175 | break; |
1176 | } | |
1177 | } | |
2e4b5889 | 1178 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1179 | /* The size is a fixed-size. */ |
1180 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1181 | /* A positive offset. */ | |
1182 | && (cris_get_signed_offset (insn) > 0)) | |
1183 | { | |
1184 | /* move.S [r8+U],rZ (?) */ | |
e17a4113 | 1185 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1186 | pc += 2; |
29134980 | 1187 | regno = cris_get_operand2 (insn_next); |
7fbe2eba | 1188 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
29134980 OF |
1189 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
1190 | && cris_get_opcode (insn_next) == 0x0009 | |
1191 | && cris_get_operand1 (insn_next) == regno) | |
1192 | { | |
1193 | /* move.S [r8+U],rZ */ | |
1194 | continue; | |
1195 | } | |
1196 | else | |
1197 | { | |
1198 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1199 | pc -= 4; |
29134980 OF |
1200 | break; |
1201 | } | |
1202 | } | |
1203 | else | |
1204 | { | |
1205 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1206 | pc -= 2; |
29134980 OF |
1207 | break; |
1208 | } | |
1209 | } | |
29134980 | 1210 | |
94afd7a6 | 1211 | /* We only want to know the end of the prologue when this_frame and info |
2e4b5889 | 1212 | are NULL (called from cris_skip_prologue i.e.). */ |
94afd7a6 | 1213 | if (this_frame == NULL && info == NULL) |
2e4b5889 OF |
1214 | { |
1215 | return pc; | |
1216 | } | |
29134980 | 1217 | |
2e4b5889 OF |
1218 | info->size = info->sp_offset; |
1219 | ||
1220 | /* Compute the previous frame's stack pointer (which is also the | |
1221 | frame's ID's stack address), and this frame's base pointer. */ | |
1222 | if (info->uses_frame) | |
29134980 | 1223 | { |
2e4b5889 OF |
1224 | ULONGEST this_base; |
1225 | /* The SP was moved to the FP. This indicates that a new frame | |
1226 | was created. Get THIS frame's FP value by unwinding it from | |
1227 | the next frame. */ | |
94afd7a6 | 1228 | this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM); |
2e4b5889 | 1229 | info->base = this_base; |
b4206d25 OF |
1230 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
1231 | ||
2e4b5889 OF |
1232 | /* The FP points at the last saved register. Adjust the FP back |
1233 | to before the first saved register giving the SP. */ | |
1234 | info->prev_sp = info->base + info->r8_offset; | |
1235 | } | |
1236 | else | |
1237 | { | |
1238 | ULONGEST this_base; | |
1239 | /* Assume that the FP is this frame's SP but with that pushed | |
1240 | stack space added back. */ | |
94afd7a6 UW |
1241 | this_base = get_frame_register_unsigned (this_frame, |
1242 | gdbarch_sp_regnum (gdbarch)); | |
2e4b5889 OF |
1243 | info->base = this_base; |
1244 | info->prev_sp = info->base + info->size; | |
1245 | } | |
29134980 | 1246 | |
2e4b5889 OF |
1247 | /* Calculate the addresses for the saved registers on the stack. */ |
1248 | /* FIXME: The address calculation should really be done on the fly while | |
1249 | we're analyzing the prologue (we only hold one regsave value as it is | |
1250 | now). */ | |
1251 | val = info->sp_offset; | |
1252 | ||
1253 | for (regno = regsave; regno >= 0; regno--) | |
1254 | { | |
1255 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; | |
1256 | val -= 4; | |
1257 | } | |
1258 | ||
1259 | /* The previous frame's SP needed to be computed. Save the computed | |
1260 | value. */ | |
3e8c568d | 1261 | trad_frame_set_value (info->saved_regs, |
7fbe2eba | 1262 | gdbarch_sp_regnum (gdbarch), info->prev_sp); |
2e4b5889 OF |
1263 | |
1264 | if (!info->leaf_function) | |
1265 | { | |
b4206d25 OF |
1266 | /* SRP saved on the stack. But where? */ |
1267 | if (info->r8_offset == 0) | |
1268 | { | |
1269 | /* R8 not pushed yet. */ | |
1270 | info->saved_regs[SRP_REGNUM].addr = info->base; | |
1271 | } | |
1272 | else | |
1273 | { | |
1274 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
1275 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; | |
1276 | } | |
29134980 | 1277 | } |
2e4b5889 OF |
1278 | |
1279 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
7fbe2eba | 1280 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 1281 | = info->saved_regs[SRP_REGNUM]; |
2e4b5889 OF |
1282 | |
1283 | return pc; | |
29134980 OF |
1284 | } |
1285 | ||
5114e29d | 1286 | static CORE_ADDR |
94afd7a6 | 1287 | crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame, |
5114e29d OF |
1288 | struct cris_unwind_cache *info) |
1289 | { | |
94afd7a6 | 1290 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
5114e29d OF |
1291 | ULONGEST this_base; |
1292 | ||
1293 | /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not | |
1294 | meant to be a full-fledged prologue scanner. It is only needed for | |
1295 | the cases where we end up in code always lacking DWARF-2 CFI, notably: | |
1296 | ||
1297 | * PLT stubs (library calls) | |
1298 | * call dummys | |
1299 | * signal trampolines | |
1300 | ||
1301 | For those cases, it is assumed that there is no actual prologue; that | |
1302 | the stack pointer is not adjusted, and (as a consequence) the return | |
1303 | address is not pushed onto the stack. */ | |
1304 | ||
94afd7a6 | 1305 | /* We only want to know the end of the prologue when this_frame and info |
5114e29d | 1306 | are NULL (called from cris_skip_prologue i.e.). */ |
94afd7a6 | 1307 | if (this_frame == NULL && info == NULL) |
5114e29d OF |
1308 | { |
1309 | return pc; | |
1310 | } | |
1311 | ||
1312 | /* The SP is assumed to be unaltered. */ | |
94afd7a6 UW |
1313 | this_base = get_frame_register_unsigned (this_frame, |
1314 | gdbarch_sp_regnum (gdbarch)); | |
5114e29d OF |
1315 | info->base = this_base; |
1316 | info->prev_sp = this_base; | |
1317 | ||
1318 | /* The PC is assumed to be found in SRP. */ | |
7fbe2eba | 1319 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 1320 | = info->saved_regs[SRP_REGNUM]; |
5114e29d OF |
1321 | |
1322 | return pc; | |
1323 | } | |
1324 | ||
29134980 OF |
1325 | /* Advance pc beyond any function entry prologue instructions at pc |
1326 | to reach some "real" code. */ | |
1327 | ||
29134980 OF |
1328 | /* Given a PC value corresponding to the start of a function, return the PC |
1329 | of the first instruction after the function prologue. */ | |
1330 | ||
a78f21af | 1331 | static CORE_ADDR |
6093d2eb | 1332 | cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
29134980 | 1333 | { |
35488783 | 1334 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2e4b5889 OF |
1335 | CORE_ADDR func_addr, func_end; |
1336 | struct symtab_and_line sal; | |
29134980 OF |
1337 | CORE_ADDR pc_after_prologue; |
1338 | ||
2e4b5889 OF |
1339 | /* If we have line debugging information, then the end of the prologue |
1340 | should the first assembly instruction of the first source line. */ | |
1341 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1342 | { | |
1343 | sal = find_pc_line (func_addr, 0); | |
1344 | if (sal.end > 0 && sal.end < func_end) | |
1345 | return sal.end; | |
1346 | } | |
29134980 | 1347 | |
35488783 | 1348 | if (tdep->cris_version == 32) |
5114e29d OF |
1349 | pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL); |
1350 | else | |
1351 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); | |
1352 | ||
29134980 OF |
1353 | return pc_after_prologue; |
1354 | } | |
1355 | ||
cd6c3b4f YQ |
1356 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
1357 | ||
d19280ad YQ |
1358 | static int |
1359 | cris_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
1360 | { | |
1361 | return 2; | |
1362 | } | |
29134980 | 1363 | |
cd6c3b4f YQ |
1364 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
1365 | ||
d19280ad YQ |
1366 | static const gdb_byte * |
1367 | cris_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
29134980 | 1368 | { |
35488783 | 1369 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
0e6bdb31 OF |
1370 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
1371 | static unsigned char break15_insn[] = {0x3f, 0xe9}; | |
d19280ad YQ |
1372 | |
1373 | *size = kind; | |
29134980 | 1374 | |
35488783 | 1375 | if (tdep->cris_mode == cris_mode_guru) |
0e6bdb31 OF |
1376 | return break15_insn; |
1377 | else | |
1378 | return break8_insn; | |
29134980 OF |
1379 | } |
1380 | ||
29134980 OF |
1381 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1382 | 0 otherwise. */ | |
1383 | ||
a78f21af | 1384 | static int |
35488783 UW |
1385 | cris_spec_reg_applicable (struct gdbarch *gdbarch, |
1386 | struct cris_spec_reg spec_reg) | |
29134980 | 1387 | { |
35488783 | 1388 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e4286e57 | 1389 | unsigned int version = tdep->cris_version; |
29134980 OF |
1390 | |
1391 | switch (spec_reg.applicable_version) | |
1392 | { | |
1393 | case cris_ver_version_all: | |
1394 | return 1; | |
1395 | case cris_ver_warning: | |
1396 | /* Indeterminate/obsolete. */ | |
1397 | return 0; | |
29134980 | 1398 | case cris_ver_v0_3: |
b020ff80 | 1399 | return in_inclusive_range (version, 0U, 3U); |
29134980 OF |
1400 | case cris_ver_v3p: |
1401 | return (version >= 3); | |
1402 | case cris_ver_v8: | |
b020ff80 | 1403 | return in_inclusive_range (version, 8U, 9U); |
29134980 OF |
1404 | case cris_ver_v8p: |
1405 | return (version >= 8); | |
c600d464 | 1406 | case cris_ver_v0_10: |
b020ff80 | 1407 | return in_inclusive_range (version, 0U, 10U); |
c600d464 | 1408 | case cris_ver_v3_10: |
b020ff80 | 1409 | return in_inclusive_range (version, 3U, 10U); |
c600d464 | 1410 | case cris_ver_v8_10: |
b020ff80 | 1411 | return in_inclusive_range (version, 8U, 10U); |
c600d464 OF |
1412 | case cris_ver_v10: |
1413 | return (version == 10); | |
29134980 OF |
1414 | case cris_ver_v10p: |
1415 | return (version >= 10); | |
c600d464 OF |
1416 | case cris_ver_v32p: |
1417 | return (version >= 32); | |
29134980 OF |
1418 | default: |
1419 | /* Invalid cris version. */ | |
1420 | return 0; | |
1421 | } | |
1422 | } | |
1423 | ||
1d94326f AC |
1424 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
1425 | register, -1 for an invalid register. */ | |
1426 | ||
1427 | static int | |
be8626e0 | 1428 | cris_register_size (struct gdbarch *gdbarch, int regno) |
1d94326f AC |
1429 | { |
1430 | int i; | |
1431 | int spec_regno; | |
1432 | ||
1433 | if (regno >= 0 && regno < NUM_GENREGS) | |
1434 | { | |
1435 | /* General registers (R0 - R15) are 32 bits. */ | |
1436 | return 4; | |
1437 | } | |
c600d464 | 1438 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
1d94326f AC |
1439 | { |
1440 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1441 | Adjust regno accordingly. */ | |
1442 | spec_regno = regno - NUM_GENREGS; | |
1443 | ||
c600d464 | 1444 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
1d94326f AC |
1445 | { |
1446 | if (cris_spec_regs[i].number == spec_regno | |
35488783 | 1447 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
1d94326f AC |
1448 | /* Go with the first applicable register. */ |
1449 | return cris_spec_regs[i].reg_size; | |
1450 | } | |
1451 | /* Special register not applicable to this CRIS version. */ | |
1452 | return 0; | |
1453 | } | |
be8626e0 MD |
1454 | else if (regno >= gdbarch_pc_regnum (gdbarch) |
1455 | && regno < gdbarch_num_regs (gdbarch)) | |
1d94326f | 1456 | { |
c600d464 OF |
1457 | /* This will apply to CRISv32 only where there are additional registers |
1458 | after the special registers (pseudo PC and support registers). */ | |
1459 | return 4; | |
1d94326f | 1460 | } |
c600d464 OF |
1461 | |
1462 | ||
1463 | return -1; | |
1d94326f AC |
1464 | } |
1465 | ||
29134980 OF |
1466 | /* Nonzero if regno should not be fetched from the target. This is the case |
1467 | for unimplemented (size 0) and non-existant registers. */ | |
1468 | ||
a78f21af | 1469 | static int |
64a3914f | 1470 | cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
29134980 | 1471 | { |
64a3914f | 1472 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
be8626e0 | 1473 | || (cris_register_size (gdbarch, regno) == 0)); |
29134980 OF |
1474 | } |
1475 | ||
1476 | /* Nonzero if regno should not be written to the target, for various | |
1477 | reasons. */ | |
1478 | ||
a78f21af | 1479 | static int |
64a3914f | 1480 | cris_cannot_store_register (struct gdbarch *gdbarch, int regno) |
29134980 OF |
1481 | { |
1482 | /* There are three kinds of registers we refuse to write to. | |
1483 | 1. Those that not implemented. | |
1484 | 2. Those that are read-only (depends on the processor mode). | |
0963b4bd | 1485 | 3. Those registers to which a write has no effect. */ |
29134980 | 1486 | |
f57d151a | 1487 | if (regno < 0 |
64a3914f | 1488 | || regno >= gdbarch_num_regs (gdbarch) |
be8626e0 | 1489 | || cris_register_size (gdbarch, regno) == 0) |
29134980 OF |
1490 | /* Not implemented. */ |
1491 | return 1; | |
1492 | ||
1493 | else if (regno == VR_REGNUM) | |
1494 | /* Read-only. */ | |
1495 | return 1; | |
1496 | ||
1497 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1498 | /* Writing has no effect. */ | |
1499 | return 1; | |
1500 | ||
a5f6c8f5 OF |
1501 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
1502 | agent decide whether they are writable. */ | |
29134980 OF |
1503 | |
1504 | return 0; | |
1505 | } | |
1506 | ||
c600d464 OF |
1507 | /* Nonzero if regno should not be fetched from the target. This is the case |
1508 | for unimplemented (size 0) and non-existant registers. */ | |
1509 | ||
1510 | static int | |
64a3914f | 1511 | crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
c600d464 | 1512 | { |
64a3914f | 1513 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
be8626e0 | 1514 | || (cris_register_size (gdbarch, regno) == 0)); |
c600d464 OF |
1515 | } |
1516 | ||
1517 | /* Nonzero if regno should not be written to the target, for various | |
1518 | reasons. */ | |
1519 | ||
1520 | static int | |
64a3914f | 1521 | crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno) |
c600d464 OF |
1522 | { |
1523 | /* There are three kinds of registers we refuse to write to. | |
1524 | 1. Those that not implemented. | |
1525 | 2. Those that are read-only (depends on the processor mode). | |
0963b4bd | 1526 | 3. Those registers to which a write has no effect. */ |
c600d464 | 1527 | |
f57d151a | 1528 | if (regno < 0 |
64a3914f | 1529 | || regno >= gdbarch_num_regs (gdbarch) |
be8626e0 | 1530 | || cris_register_size (gdbarch, regno) == 0) |
c600d464 OF |
1531 | /* Not implemented. */ |
1532 | return 1; | |
1533 | ||
1534 | else if (regno == VR_REGNUM) | |
1535 | /* Read-only. */ | |
1536 | return 1; | |
1537 | ||
1538 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) | |
1539 | /* Writing has no effect. */ | |
1540 | return 1; | |
1541 | ||
1542 | /* Many special registers are read-only in user mode. Let the debug | |
1543 | agent decide whether they are writable. */ | |
1544 | ||
1545 | return 0; | |
1546 | } | |
1547 | ||
29134980 OF |
1548 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
1549 | of data in register regno. */ | |
1550 | ||
a78f21af | 1551 | static struct type * |
c1d546cd | 1552 | cris_register_type (struct gdbarch *gdbarch, int regno) |
29134980 | 1553 | { |
7fbe2eba | 1554 | if (regno == gdbarch_pc_regnum (gdbarch)) |
0dfff4cb | 1555 | return builtin_type (gdbarch)->builtin_func_ptr; |
7fbe2eba | 1556 | else if (regno == gdbarch_sp_regnum (gdbarch) |
3e8c568d | 1557 | || regno == CRIS_FP_REGNUM) |
0dfff4cb | 1558 | return builtin_type (gdbarch)->builtin_data_ptr; |
7fbe2eba | 1559 | else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
a5f6c8f5 OF |
1560 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) |
1561 | /* Note: R8 taken care of previous clause. */ | |
df4df182 | 1562 | return builtin_type (gdbarch)->builtin_uint32; |
a5f6c8f5 | 1563 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) |
df4df182 | 1564 | return builtin_type (gdbarch)->builtin_uint16; |
a5f6c8f5 | 1565 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) |
df4df182 | 1566 | return builtin_type (gdbarch)->builtin_uint8; |
29134980 | 1567 | else |
a5f6c8f5 | 1568 | /* Invalid (unimplemented) register. */ |
df4df182 | 1569 | return builtin_type (gdbarch)->builtin_int0; |
29134980 OF |
1570 | } |
1571 | ||
c600d464 OF |
1572 | static struct type * |
1573 | crisv32_register_type (struct gdbarch *gdbarch, int regno) | |
1574 | { | |
7fbe2eba | 1575 | if (regno == gdbarch_pc_regnum (gdbarch)) |
0dfff4cb | 1576 | return builtin_type (gdbarch)->builtin_func_ptr; |
7fbe2eba | 1577 | else if (regno == gdbarch_sp_regnum (gdbarch) |
3e8c568d | 1578 | || regno == CRIS_FP_REGNUM) |
0dfff4cb | 1579 | return builtin_type (gdbarch)->builtin_data_ptr; |
c600d464 OF |
1580 | else if ((regno >= 0 && regno <= ACR_REGNUM) |
1581 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) | |
1582 | || (regno == PID_REGNUM) | |
1583 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) | |
1584 | /* Note: R8 and SP taken care of by previous clause. */ | |
df4df182 | 1585 | return builtin_type (gdbarch)->builtin_uint32; |
c600d464 | 1586 | else if (regno == WZ_REGNUM) |
df4df182 | 1587 | return builtin_type (gdbarch)->builtin_uint16; |
c600d464 | 1588 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) |
df4df182 | 1589 | return builtin_type (gdbarch)->builtin_uint8; |
c600d464 OF |
1590 | else |
1591 | { | |
1592 | /* Invalid (unimplemented) register. Should not happen as there are | |
1593 | no unimplemented CRISv32 registers. */ | |
8a3fe4f8 | 1594 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
df4df182 | 1595 | return builtin_type (gdbarch)->builtin_int0; |
c600d464 OF |
1596 | } |
1597 | } | |
1598 | ||
2e4b5889 OF |
1599 | /* Stores a function return value of type type, where valbuf is the address |
1600 | of the value to be stored. */ | |
29134980 | 1601 | |
2e4b5889 | 1602 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1603 | |
2e4b5889 OF |
1604 | static void |
1605 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
948f8e3d | 1606 | const gdb_byte *valbuf) |
29134980 | 1607 | { |
ac7936df | 1608 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1609 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2e4b5889 | 1610 | ULONGEST val; |
bad43aa5 | 1611 | int len = TYPE_LENGTH (type); |
29134980 | 1612 | |
bad43aa5 | 1613 | if (len <= 4) |
29134980 | 1614 | { |
2e4b5889 | 1615 | /* Put the return value in R10. */ |
bad43aa5 | 1616 | val = extract_unsigned_integer (valbuf, len, byte_order); |
2e4b5889 | 1617 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
29134980 | 1618 | } |
bad43aa5 | 1619 | else if (len <= 8) |
29134980 | 1620 | { |
2e4b5889 | 1621 | /* Put the return value in R10 and R11. */ |
e17a4113 | 1622 | val = extract_unsigned_integer (valbuf, 4, byte_order); |
2e4b5889 | 1623 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
948f8e3d | 1624 | val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order); |
2e4b5889 | 1625 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); |
29134980 | 1626 | } |
2e4b5889 | 1627 | else |
8a3fe4f8 | 1628 | error (_("cris_store_return_value: type length too large.")); |
29134980 OF |
1629 | } |
1630 | ||
0963b4bd MS |
1631 | /* Return the name of register regno as a string. Return NULL for an |
1632 | invalid or unimplemented register. */ | |
29134980 | 1633 | |
c600d464 | 1634 | static const char * |
35488783 | 1635 | cris_special_register_name (struct gdbarch *gdbarch, int regno) |
c600d464 OF |
1636 | { |
1637 | int spec_regno; | |
1638 | int i; | |
1639 | ||
1640 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1641 | Adjust regno accordingly. */ | |
1642 | spec_regno = regno - NUM_GENREGS; | |
1643 | ||
1644 | /* Assume nothing about the layout of the cris_spec_regs struct | |
1645 | when searching. */ | |
1646 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1647 | { | |
1648 | if (cris_spec_regs[i].number == spec_regno | |
35488783 | 1649 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
c600d464 OF |
1650 | /* Go with the first applicable register. */ |
1651 | return cris_spec_regs[i].name; | |
1652 | } | |
1653 | /* Special register not applicable to this CRIS version. */ | |
1654 | return NULL; | |
1655 | } | |
1656 | ||
2e4b5889 | 1657 | static const char * |
d93859e2 | 1658 | cris_register_name (struct gdbarch *gdbarch, int regno) |
2e4b5889 | 1659 | { |
a121b7c1 | 1660 | static const char *cris_genreg_names[] = |
2e4b5889 OF |
1661 | { "r0", "r1", "r2", "r3", \ |
1662 | "r4", "r5", "r6", "r7", \ | |
1663 | "r8", "r9", "r10", "r11", \ | |
1664 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1665 | |
2e4b5889 | 1666 | if (regno >= 0 && regno < NUM_GENREGS) |
29134980 | 1667 | { |
2e4b5889 OF |
1668 | /* General register. */ |
1669 | return cris_genreg_names[regno]; | |
29134980 | 1670 | } |
d93859e2 | 1671 | else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch)) |
29134980 | 1672 | { |
35488783 | 1673 | return cris_special_register_name (gdbarch, regno); |
c600d464 OF |
1674 | } |
1675 | else | |
1676 | { | |
1677 | /* Invalid register. */ | |
2e4b5889 OF |
1678 | return NULL; |
1679 | } | |
c600d464 OF |
1680 | } |
1681 | ||
1682 | static const char * | |
d93859e2 | 1683 | crisv32_register_name (struct gdbarch *gdbarch, int regno) |
c600d464 | 1684 | { |
a121b7c1 | 1685 | static const char *crisv32_genreg_names[] = |
c600d464 OF |
1686 | { "r0", "r1", "r2", "r3", \ |
1687 | "r4", "r5", "r6", "r7", \ | |
1688 | "r8", "r9", "r10", "r11", \ | |
1689 | "r12", "r13", "sp", "acr" | |
1690 | }; | |
1691 | ||
a121b7c1 | 1692 | static const char *crisv32_sreg_names[] = |
c600d464 OF |
1693 | { "s0", "s1", "s2", "s3", \ |
1694 | "s4", "s5", "s6", "s7", \ | |
1695 | "s8", "s9", "s10", "s11", \ | |
1696 | "s12", "s13", "s14", "s15" | |
1697 | }; | |
1698 | ||
1699 | if (regno >= 0 && regno < NUM_GENREGS) | |
1700 | { | |
1701 | /* General register. */ | |
1702 | return crisv32_genreg_names[regno]; | |
1703 | } | |
1704 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) | |
1705 | { | |
35488783 | 1706 | return cris_special_register_name (gdbarch, regno); |
c600d464 | 1707 | } |
d93859e2 | 1708 | else if (regno == gdbarch_pc_regnum (gdbarch)) |
c600d464 OF |
1709 | { |
1710 | return "pc"; | |
1711 | } | |
1712 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) | |
1713 | { | |
1714 | return crisv32_sreg_names[regno - S0_REGNUM]; | |
1715 | } | |
2e4b5889 OF |
1716 | else |
1717 | { | |
1718 | /* Invalid register. */ | |
1719 | return NULL; | |
29134980 | 1720 | } |
29134980 OF |
1721 | } |
1722 | ||
a5f6c8f5 OF |
1723 | /* Convert DWARF register number REG to the appropriate register |
1724 | number used by GDB. */ | |
1725 | ||
2e4b5889 | 1726 | static int |
d3f73121 | 1727 | cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
29134980 | 1728 | { |
a5f6c8f5 OF |
1729 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
1730 | numbering, MOF is 18). | |
1731 | Adapted from gcc/config/cris/cris.h. */ | |
1732 | static int cris_dwarf_regmap[] = { | |
1733 | 0, 1, 2, 3, | |
1734 | 4, 5, 6, 7, | |
1735 | 8, 9, 10, 11, | |
1736 | 12, 13, 14, 15, | |
1737 | 27, -1, -1, -1, | |
1738 | -1, -1, -1, 23, | |
1739 | -1, -1, -1, 27, | |
1740 | -1, -1, -1, -1 | |
1741 | }; | |
1742 | int regnum = -1; | |
1743 | ||
1744 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) | |
1745 | regnum = cris_dwarf_regmap[reg]; | |
1746 | ||
a5f6c8f5 OF |
1747 | return regnum; |
1748 | } | |
1749 | ||
1750 | /* DWARF-2 frame support. */ | |
1751 | ||
1752 | static void | |
1753 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1754 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1755 | struct frame_info *this_frame) |
a5f6c8f5 OF |
1756 | { |
1757 | /* The return address column. */ | |
7fbe2eba | 1758 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
a5f6c8f5 OF |
1759 | reg->how = DWARF2_FRAME_REG_RA; |
1760 | ||
1761 | /* The call frame address. */ | |
7fbe2eba | 1762 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
a5f6c8f5 | 1763 | reg->how = DWARF2_FRAME_REG_CFA; |
29134980 OF |
1764 | } |
1765 | ||
2e4b5889 OF |
1766 | /* Extract from an array regbuf containing the raw register state a function |
1767 | return value of type type, and copy that, in virtual format, into | |
1768 | valbuf. */ | |
1769 | ||
1770 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1771 | |
2e4b5889 OF |
1772 | static void |
1773 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
948f8e3d | 1774 | gdb_byte *valbuf) |
29134980 | 1775 | { |
ac7936df | 1776 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1777 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2e4b5889 | 1778 | ULONGEST val; |
bad43aa5 | 1779 | int len = TYPE_LENGTH (type); |
29134980 | 1780 | |
bad43aa5 | 1781 | if (len <= 4) |
29134980 | 1782 | { |
2e4b5889 OF |
1783 | /* Get the return value from R10. */ |
1784 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
bad43aa5 | 1785 | store_unsigned_integer (valbuf, len, byte_order, val); |
29134980 | 1786 | } |
bad43aa5 | 1787 | else if (len <= 8) |
29134980 | 1788 | { |
2e4b5889 OF |
1789 | /* Get the return value from R10 and R11. */ |
1790 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
e17a4113 | 1791 | store_unsigned_integer (valbuf, 4, byte_order, val); |
2e4b5889 | 1792 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); |
948f8e3d | 1793 | store_unsigned_integer (valbuf + 4, len - 4, byte_order, val); |
29134980 | 1794 | } |
2e4b5889 | 1795 | else |
8a3fe4f8 | 1796 | error (_("cris_extract_return_value: type length too large")); |
2e4b5889 OF |
1797 | } |
1798 | ||
b4206d25 OF |
1799 | /* Handle the CRIS return value convention. */ |
1800 | ||
1801 | static enum return_value_convention | |
6a3a010b | 1802 | cris_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1803 | struct type *type, struct regcache *regcache, |
1804 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b4206d25 OF |
1805 | { |
1806 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1807 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1808 | || TYPE_LENGTH (type) > 8) | |
1809 | /* Structs, unions, and anything larger than 8 bytes (2 registers) | |
1810 | goes on the stack. */ | |
1811 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1812 | ||
1813 | if (readbuf) | |
1814 | cris_extract_return_value (type, regcache, readbuf); | |
1815 | if (writebuf) | |
1816 | cris_store_return_value (type, regcache, writebuf); | |
1817 | ||
1818 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1819 | } | |
1820 | ||
29134980 OF |
1821 | /* Calculates a value that measures how good inst_args constraints an |
1822 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1823 | ||
1824 | static int | |
948f8e3d | 1825 | constraint (unsigned int insn, const char *inst_args, |
29134980 OF |
1826 | inst_env_type *inst_env) |
1827 | { | |
1828 | int retval = 0; | |
1829 | int tmp, i; | |
1830 | ||
948f8e3d | 1831 | const gdb_byte *s = (const gdb_byte *) inst_args; |
29134980 OF |
1832 | |
1833 | for (; *s; s++) | |
1834 | switch (*s) | |
1835 | { | |
1836 | case 'm': | |
1837 | if ((insn & 0x30) == 0x30) | |
1838 | return -1; | |
1839 | break; | |
1840 | ||
1841 | case 'S': | |
1842 | /* A prefix operand. */ | |
1843 | if (inst_env->prefix_found) | |
1844 | break; | |
1845 | else | |
1846 | return -1; | |
1847 | ||
1848 | case 'B': | |
1849 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1850 | valid "push" size. In case of special register, it may be != 4. */ | |
1851 | if (inst_env->prefix_found) | |
1852 | break; | |
1853 | else | |
1854 | return -1; | |
1855 | ||
1856 | case 'D': | |
1857 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1858 | if (!retval) | |
1859 | return -1; | |
1860 | else | |
1861 | retval += 4; | |
1862 | break; | |
1863 | ||
1864 | case 'P': | |
1865 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1866 | |
1867 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1868 | { | |
1869 | /* Since we match four bits, we will give a value of | |
1870 | 4 - 1 = 3 in a match. If there is a corresponding | |
1871 | exact match of a special register in another pattern, it | |
1872 | will get a value of 4, which will be higher. This should | |
1873 | be correct in that an exact pattern would match better that | |
1874 | a general pattern. | |
1875 | Note that there is a reason for not returning zero; the | |
1876 | pattern for "clear" is partly matched in the bit-pattern | |
1877 | (the two lower bits must be zero), while the bit-pattern | |
1878 | for a move from a special register is matched in the | |
1879 | register constraint. | |
1880 | This also means we will will have a race condition if | |
1881 | there is a partly match in three bits in the bit pattern. */ | |
1882 | if (tmp == cris_spec_regs[i].number) | |
1883 | { | |
1884 | retval += 3; | |
1885 | break; | |
1886 | } | |
1887 | } | |
1888 | ||
1889 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
1890 | return -1; |
1891 | break; | |
1892 | } | |
1893 | return retval; | |
1894 | } | |
1895 | ||
1896 | /* Returns the number of bits set in the variable value. */ | |
1897 | ||
1898 | static int | |
1899 | number_of_bits (unsigned int value) | |
1900 | { | |
1901 | int number_of_bits = 0; | |
1902 | ||
1903 | while (value != 0) | |
1904 | { | |
1905 | number_of_bits += 1; | |
1906 | value &= (value - 1); | |
1907 | } | |
1908 | return number_of_bits; | |
1909 | } | |
1910 | ||
1911 | /* Finds the address that should contain the single step breakpoint(s). | |
1912 | It stems from code in cris-dis.c. */ | |
1913 | ||
1914 | static int | |
1915 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
1916 | { | |
1917 | int i; | |
1918 | int max_level_of_match = -1; | |
1919 | int max_matched = -1; | |
1920 | int level_of_match; | |
1921 | ||
1922 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
1923 | { | |
1924 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
c600d464 OF |
1925 | && ((cris_opcodes[i].lose & insn) == 0) |
1926 | /* Only CRISv10 instructions, please. */ | |
1927 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) | |
29134980 OF |
1928 | { |
1929 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
1930 | if (level_of_match >= 0) | |
1931 | { | |
1932 | level_of_match += | |
1933 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
1934 | if (level_of_match > max_level_of_match) | |
1935 | { | |
1936 | max_matched = i; | |
1937 | max_level_of_match = level_of_match; | |
1938 | if (level_of_match == 16) | |
1939 | { | |
1940 | /* All bits matched, cannot find better. */ | |
1941 | break; | |
1942 | } | |
1943 | } | |
1944 | } | |
1945 | } | |
1946 | } | |
1947 | return max_matched; | |
1948 | } | |
1949 | ||
1950 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
1951 | actually an internal error. */ | |
1952 | ||
1953 | static int | |
5b6e2eee | 1954 | find_step_target (struct regcache *regcache, inst_env_type *inst_env) |
29134980 OF |
1955 | { |
1956 | int i; | |
1957 | int offset; | |
1958 | unsigned short insn; | |
ac7936df | 1959 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1960 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
29134980 OF |
1961 | |
1962 | /* Create a local register image and set the initial state. */ | |
1963 | for (i = 0; i < NUM_GENREGS; i++) | |
1964 | { | |
0b1b3e42 | 1965 | inst_env->reg[i] = |
5b6e2eee | 1966 | (unsigned long) regcache_raw_get_unsigned (regcache, i); |
29134980 OF |
1967 | } |
1968 | offset = NUM_GENREGS; | |
1969 | for (i = 0; i < NUM_SPECREGS; i++) | |
1970 | { | |
0b1b3e42 | 1971 | inst_env->preg[i] = |
5b6e2eee | 1972 | (unsigned long) regcache_raw_get_unsigned (regcache, offset + i); |
29134980 OF |
1973 | } |
1974 | inst_env->branch_found = 0; | |
1975 | inst_env->slot_needed = 0; | |
1976 | inst_env->delay_slot_pc_active = 0; | |
1977 | inst_env->prefix_found = 0; | |
1978 | inst_env->invalid = 0; | |
1979 | inst_env->xflag_found = 0; | |
1980 | inst_env->disable_interrupt = 0; | |
e17a4113 | 1981 | inst_env->byte_order = byte_order; |
29134980 OF |
1982 | |
1983 | /* Look for a step target. */ | |
1984 | do | |
1985 | { | |
1986 | /* Read an instruction from the client. */ | |
3e8c568d | 1987 | insn = read_memory_unsigned_integer |
e17a4113 | 1988 | (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order); |
29134980 OF |
1989 | |
1990 | /* If the instruction is not in a delay slot the new content of the | |
1991 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
1992 | that simple. Since a instruction in a delay slot cannot change | |
1993 | the content of the PC, it does not matter what value PC will have. | |
1994 | Just make sure it is a valid instruction. */ | |
1995 | if (!inst_env->delay_slot_pc_active) | |
1996 | { | |
7fbe2eba | 1997 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2; |
29134980 OF |
1998 | } |
1999 | else | |
2000 | { | |
2001 | inst_env->delay_slot_pc_active = 0; | |
7fbe2eba | 2002 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 2003 | = inst_env->delay_slot_pc; |
29134980 OF |
2004 | } |
2005 | /* Analyse the present instruction. */ | |
2006 | i = find_cris_op (insn, inst_env); | |
2007 | if (i == -1) | |
2008 | { | |
2009 | inst_env->invalid = 1; | |
2010 | } | |
2011 | else | |
2012 | { | |
be8626e0 | 2013 | cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env); |
29134980 OF |
2014 | } |
2015 | } while (!inst_env->invalid | |
2016 | && (inst_env->prefix_found || inst_env->xflag_found | |
2017 | || inst_env->slot_needed)); | |
2018 | return i; | |
2019 | } | |
2020 | ||
2021 | /* There is no hardware single-step support. The function find_step_target | |
0963b4bd | 2022 | digs through the opcodes in order to find all possible targets. |
29134980 OF |
2023 | Either one ordinary target or two targets for branches may be found. */ |
2024 | ||
a0ff9e1a | 2025 | static std::vector<CORE_ADDR> |
f5ea389a | 2026 | cris_software_single_step (struct regcache *regcache) |
29134980 | 2027 | { |
ac7936df | 2028 | struct gdbarch *gdbarch = regcache->arch (); |
29134980 | 2029 | inst_env_type inst_env; |
a0ff9e1a | 2030 | std::vector<CORE_ADDR> next_pcs; |
8181d85f | 2031 | |
e0cd558a UW |
2032 | /* Analyse the present instruction environment and insert |
2033 | breakpoints. */ | |
5b6e2eee | 2034 | int status = find_step_target (regcache, &inst_env); |
e0cd558a | 2035 | if (status == -1) |
29134980 | 2036 | { |
e0cd558a UW |
2037 | /* Could not find a target. Things are likely to go downhill |
2038 | from here. */ | |
2039 | warning (_("CRIS software single step could not find a step target.")); | |
29134980 OF |
2040 | } |
2041 | else | |
e0cd558a UW |
2042 | { |
2043 | /* Insert at most two breakpoints. One for the next PC content | |
2044 | and possibly another one for a branch, jump, etc. */ | |
a6d9a66e UW |
2045 | CORE_ADDR next_pc |
2046 | = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)]; | |
93f9a11f | 2047 | |
a0ff9e1a | 2048 | next_pcs.push_back (next_pc); |
e0cd558a UW |
2049 | if (inst_env.branch_found |
2050 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
2051 | { | |
2052 | CORE_ADDR branch_target_address | |
2053 | = (CORE_ADDR) inst_env.branch_break_address; | |
93f9a11f | 2054 | |
a0ff9e1a | 2055 | next_pcs.push_back (branch_target_address); |
e0cd558a UW |
2056 | } |
2057 | } | |
e6590a1b | 2058 | |
93f9a11f | 2059 | return next_pcs; |
29134980 OF |
2060 | } |
2061 | ||
2062 | /* Calculates the prefix value for quick offset addressing mode. */ | |
2063 | ||
a78f21af | 2064 | static void |
29134980 OF |
2065 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2066 | { | |
2067 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
2068 | instruction (not 100% sure). */ | |
2069 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2070 | { | |
2071 | inst_env->invalid = 1; | |
2072 | return; | |
2073 | } | |
2074 | ||
2075 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
2076 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
2077 | ||
2078 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2079 | need updating. */ | |
2080 | inst_env->slot_needed = 0; | |
2081 | inst_env->prefix_found = 1; | |
2082 | } | |
2083 | ||
2084 | /* Updates the autoincrement register. The size of the increment is derived | |
2085 | from the size of the operation. The PC is always kept aligned on even | |
2086 | word addresses. */ | |
2087 | ||
a78f21af | 2088 | static void |
29134980 OF |
2089 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
2090 | { | |
2091 | if (size == INST_BYTE_SIZE) | |
2092 | { | |
2093 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
2094 | ||
2095 | /* The PC must be word aligned, so increase the PC with one | |
2096 | word even if the size is byte. */ | |
2097 | if (cris_get_operand1 (inst) == REG_PC) | |
2098 | { | |
2099 | inst_env->reg[REG_PC] += 1; | |
2100 | } | |
2101 | } | |
2102 | else if (size == INST_WORD_SIZE) | |
2103 | { | |
2104 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
2105 | } | |
2106 | else if (size == INST_DWORD_SIZE) | |
2107 | { | |
2108 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2109 | } | |
2110 | else | |
2111 | { | |
2112 | /* Invalid size. */ | |
2113 | inst_env->invalid = 1; | |
2114 | } | |
2115 | } | |
2116 | ||
2a9ecef2 OF |
2117 | /* Just a forward declaration. */ |
2118 | ||
a78f21af | 2119 | static unsigned long get_data_from_address (unsigned short *inst, |
e17a4113 UW |
2120 | CORE_ADDR address, |
2121 | enum bfd_endian byte_order); | |
2a9ecef2 | 2122 | |
29134980 OF |
2123 | /* Calculates the prefix value for the general case of offset addressing |
2124 | mode. */ | |
2125 | ||
a78f21af | 2126 | static void |
29134980 OF |
2127 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2128 | { | |
29134980 OF |
2129 | /* It's invalid to be in a delay slot. */ |
2130 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2131 | { | |
2132 | inst_env->invalid = 1; | |
2133 | return; | |
2134 | } | |
2135 | ||
fa4e4598 OF |
2136 | /* The calculation of prefix_value used to be after process_autoincrement, |
2137 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
2138 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
2139 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
2140 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
2141 | ||
2142 | /* The offset is an indirection of the contents of the operand1 register. */ | |
2143 | inst_env->prefix_value += | |
e17a4113 UW |
2144 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)], |
2145 | inst_env->byte_order); | |
2a9ecef2 | 2146 | |
fa4e4598 OF |
2147 | if (cris_get_mode (inst) == AUTOINC_MODE) |
2148 | { | |
2149 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2150 | } | |
2151 | ||
29134980 OF |
2152 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
2153 | need updating. */ | |
2154 | inst_env->slot_needed = 0; | |
2155 | inst_env->prefix_found = 1; | |
2156 | } | |
2157 | ||
2158 | /* Calculates the prefix value for the index addressing mode. */ | |
2159 | ||
a78f21af | 2160 | static void |
29134980 OF |
2161 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
2162 | { | |
2163 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
2164 | have a prefix to this instruction. So I will treat this as invalid. */ | |
2165 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2166 | { | |
2167 | inst_env->invalid = 1; | |
2168 | return; | |
2169 | } | |
2170 | ||
2171 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
2172 | ||
2173 | /* The offset is the operand2 value shifted the size of the instruction | |
2174 | to the left. */ | |
2175 | inst_env->prefix_value += | |
2176 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
2177 | ||
2178 | /* If the PC is operand1 (base) the address used is the address after | |
2179 | the main instruction, i.e. address + 2 (the PC is already compensated | |
2180 | for the prefix operation). */ | |
2181 | if (cris_get_operand1 (inst) == REG_PC) | |
2182 | { | |
2183 | inst_env->prefix_value += 2; | |
2184 | } | |
2185 | ||
2186 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2187 | need updating. */ | |
2188 | inst_env->slot_needed = 0; | |
2189 | inst_env->xflag_found = 0; | |
2190 | inst_env->prefix_found = 1; | |
2191 | } | |
2192 | ||
2193 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
2194 | ||
a78f21af | 2195 | static void |
29134980 OF |
2196 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
2197 | { | |
2198 | ||
2199 | CORE_ADDR address; | |
2200 | ||
2201 | /* It's invalid to be in a delay slot. */ | |
2202 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2203 | { | |
2204 | inst_env->invalid = 1; | |
2205 | return; | |
2206 | } | |
2207 | ||
2208 | /* The prefix value is one dereference of the contents of the operand1 | |
2209 | register. */ | |
2210 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 UW |
2211 | inst_env->prefix_value |
2212 | = read_memory_unsigned_integer (address, 4, inst_env->byte_order); | |
29134980 OF |
2213 | |
2214 | /* Check if the mode is autoincrement. */ | |
2215 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2216 | { | |
2217 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2218 | } | |
2219 | ||
2220 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2221 | need updating. */ | |
2222 | inst_env->slot_needed = 0; | |
2223 | inst_env->xflag_found = 0; | |
2224 | inst_env->prefix_found = 1; | |
2225 | } | |
2226 | ||
2227 | /* Finds the destination for a branch with 8-bits offset. */ | |
2228 | ||
a78f21af | 2229 | static void |
29134980 OF |
2230 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2231 | { | |
2232 | ||
2233 | short offset; | |
2234 | ||
2235 | /* If we have a prefix or are in a delay slot it's bad. */ | |
2236 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2237 | { | |
2238 | inst_env->invalid = 1; | |
2239 | return; | |
2240 | } | |
2241 | ||
2242 | /* We have a branch, find out where the branch will land. */ | |
2243 | offset = cris_get_branch_short_offset (inst); | |
2244 | ||
2245 | /* Check if the offset is signed. */ | |
2246 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2247 | { | |
2248 | offset |= 0xFF00; | |
2249 | } | |
2250 | ||
2251 | /* The offset ends with the sign bit, set it to zero. The address | |
2252 | should always be word aligned. */ | |
2253 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2254 | ||
2255 | inst_env->branch_found = 1; | |
2256 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2257 | ||
2258 | inst_env->slot_needed = 1; | |
2259 | inst_env->prefix_found = 0; | |
2260 | inst_env->xflag_found = 0; | |
2261 | inst_env->disable_interrupt = 1; | |
2262 | } | |
2263 | ||
2264 | /* Finds the destination for a branch with 16-bits offset. */ | |
2265 | ||
a78f21af | 2266 | static void |
29134980 OF |
2267 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2268 | { | |
2269 | short offset; | |
2270 | ||
2271 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2272 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2273 | { | |
2274 | inst_env->invalid = 1; | |
2275 | return; | |
2276 | } | |
2277 | ||
2278 | /* We have a branch, find out the offset for the branch. */ | |
0963b4bd MS |
2279 | offset = read_memory_integer (inst_env->reg[REG_PC], 2, |
2280 | inst_env->byte_order); | |
29134980 OF |
2281 | |
2282 | /* The instruction is one word longer than normal, so add one word | |
2283 | to the PC. */ | |
2284 | inst_env->reg[REG_PC] += 2; | |
2285 | ||
2286 | inst_env->branch_found = 1; | |
2287 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2288 | ||
2289 | ||
2290 | inst_env->slot_needed = 1; | |
2291 | inst_env->prefix_found = 0; | |
2292 | inst_env->xflag_found = 0; | |
2293 | inst_env->disable_interrupt = 1; | |
2294 | } | |
2295 | ||
2296 | /* Handles the ABS instruction. */ | |
2297 | ||
a78f21af | 2298 | static void |
29134980 OF |
2299 | abs_op (unsigned short inst, inst_env_type *inst_env) |
2300 | { | |
2301 | ||
2302 | long value; | |
2303 | ||
2304 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2305 | if (inst_env->prefix_found) | |
2306 | { | |
2307 | inst_env->invalid = 1; | |
2308 | return; | |
2309 | } | |
2310 | ||
2311 | /* Check if the operation affects the PC. */ | |
2312 | if (cris_get_operand2 (inst) == REG_PC) | |
2313 | { | |
2314 | ||
2315 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2316 | if (inst_env->slot_needed) | |
2317 | { | |
2318 | inst_env->invalid = 1; | |
2319 | return; | |
2320 | } | |
2321 | ||
2322 | value = (long) inst_env->reg[REG_PC]; | |
2323 | ||
2324 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2325 | if (value != SIGNED_DWORD_MASK) | |
2326 | { | |
2327 | value = -value; | |
2328 | inst_env->reg[REG_PC] = (long) value; | |
2329 | } | |
2330 | } | |
2331 | ||
2332 | inst_env->slot_needed = 0; | |
2333 | inst_env->prefix_found = 0; | |
2334 | inst_env->xflag_found = 0; | |
2335 | inst_env->disable_interrupt = 0; | |
2336 | } | |
2337 | ||
2338 | /* Handles the ADDI instruction. */ | |
2339 | ||
a78f21af | 2340 | static void |
29134980 OF |
2341 | addi_op (unsigned short inst, inst_env_type *inst_env) |
2342 | { | |
2343 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2344 | a prefix. */ | |
2345 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2346 | { | |
2347 | inst_env->invalid = 1; | |
2348 | return; | |
2349 | } | |
2350 | ||
2351 | inst_env->slot_needed = 0; | |
2352 | inst_env->prefix_found = 0; | |
2353 | inst_env->xflag_found = 0; | |
2354 | inst_env->disable_interrupt = 0; | |
2355 | } | |
2356 | ||
2357 | /* Handles the ASR instruction. */ | |
2358 | ||
a78f21af | 2359 | static void |
29134980 OF |
2360 | asr_op (unsigned short inst, inst_env_type *inst_env) |
2361 | { | |
2362 | int shift_steps; | |
2363 | unsigned long value; | |
2364 | unsigned long signed_extend_mask = 0; | |
2365 | ||
2366 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2367 | if (inst_env->prefix_found) | |
2368 | { | |
2369 | inst_env->invalid = 1; | |
2370 | return; | |
2371 | } | |
2372 | ||
2373 | /* Check if the PC is the target register. */ | |
2374 | if (cris_get_operand2 (inst) == REG_PC) | |
2375 | { | |
2376 | /* It's invalid to change the PC in a delay slot. */ | |
2377 | if (inst_env->slot_needed) | |
2378 | { | |
2379 | inst_env->invalid = 1; | |
2380 | return; | |
2381 | } | |
2382 | /* Get the number of bits to shift. */ | |
0963b4bd MS |
2383 | shift_steps |
2384 | = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
29134980 OF |
2385 | value = inst_env->reg[REG_PC]; |
2386 | ||
2387 | /* Find out how many bits the operation should apply to. */ | |
2388 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2389 | { | |
2390 | if (value & SIGNED_BYTE_MASK) | |
2391 | { | |
2392 | signed_extend_mask = 0xFF; | |
2393 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2394 | signed_extend_mask = ~signed_extend_mask; | |
2395 | } | |
2396 | value = value >> shift_steps; | |
2397 | value |= signed_extend_mask; | |
2398 | value &= 0xFF; | |
2399 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2400 | inst_env->reg[REG_PC] |= value; | |
2401 | } | |
2402 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2403 | { | |
2404 | if (value & SIGNED_WORD_MASK) | |
2405 | { | |
2406 | signed_extend_mask = 0xFFFF; | |
2407 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2408 | signed_extend_mask = ~signed_extend_mask; | |
2409 | } | |
2410 | value = value >> shift_steps; | |
2411 | value |= signed_extend_mask; | |
2412 | value &= 0xFFFF; | |
2413 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2414 | inst_env->reg[REG_PC] |= value; | |
2415 | } | |
2416 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2417 | { | |
2418 | if (value & SIGNED_DWORD_MASK) | |
2419 | { | |
2420 | signed_extend_mask = 0xFFFFFFFF; | |
2421 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2422 | signed_extend_mask = ~signed_extend_mask; | |
2423 | } | |
2424 | value = value >> shift_steps; | |
2425 | value |= signed_extend_mask; | |
2426 | inst_env->reg[REG_PC] = value; | |
2427 | } | |
2428 | } | |
2429 | inst_env->slot_needed = 0; | |
2430 | inst_env->prefix_found = 0; | |
2431 | inst_env->xflag_found = 0; | |
2432 | inst_env->disable_interrupt = 0; | |
2433 | } | |
2434 | ||
2435 | /* Handles the ASRQ instruction. */ | |
2436 | ||
a78f21af | 2437 | static void |
29134980 OF |
2438 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2439 | { | |
2440 | ||
2441 | int shift_steps; | |
2442 | unsigned long value; | |
2443 | unsigned long signed_extend_mask = 0; | |
2444 | ||
2445 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2446 | if (inst_env->prefix_found) | |
2447 | { | |
2448 | inst_env->invalid = 1; | |
2449 | return; | |
2450 | } | |
2451 | ||
2452 | /* Check if the PC is the target register. */ | |
2453 | if (cris_get_operand2 (inst) == REG_PC) | |
2454 | { | |
2455 | ||
2456 | /* It's invalid to change the PC in a delay slot. */ | |
2457 | if (inst_env->slot_needed) | |
2458 | { | |
2459 | inst_env->invalid = 1; | |
2460 | return; | |
2461 | } | |
2462 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
b021a221 | 2463 | want the sign bit of the quick value. */ |
29134980 OF |
2464 | shift_steps = cris_get_asr_shift_steps (inst); |
2465 | value = inst_env->reg[REG_PC]; | |
2466 | if (value & SIGNED_DWORD_MASK) | |
2467 | { | |
2468 | signed_extend_mask = 0xFFFFFFFF; | |
2469 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2470 | signed_extend_mask = ~signed_extend_mask; | |
2471 | } | |
2472 | value = value >> shift_steps; | |
2473 | value |= signed_extend_mask; | |
2474 | inst_env->reg[REG_PC] = value; | |
2475 | } | |
2476 | inst_env->slot_needed = 0; | |
2477 | inst_env->prefix_found = 0; | |
2478 | inst_env->xflag_found = 0; | |
2479 | inst_env->disable_interrupt = 0; | |
2480 | } | |
2481 | ||
2482 | /* Handles the AX, EI and SETF instruction. */ | |
2483 | ||
a78f21af | 2484 | static void |
29134980 OF |
2485 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2486 | { | |
2487 | if (inst_env->prefix_found) | |
2488 | { | |
2489 | inst_env->invalid = 1; | |
2490 | return; | |
2491 | } | |
2492 | /* Check if the instruction is setting the X flag. */ | |
2493 | if (cris_is_xflag_bit_on (inst)) | |
2494 | { | |
2495 | inst_env->xflag_found = 1; | |
2496 | } | |
2497 | else | |
2498 | { | |
2499 | inst_env->xflag_found = 0; | |
2500 | } | |
2501 | inst_env->slot_needed = 0; | |
2502 | inst_env->prefix_found = 0; | |
2503 | inst_env->disable_interrupt = 1; | |
2504 | } | |
2505 | ||
2506 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2507 | register. Note that check_assign assumes that the caller has checked that | |
2508 | there is a prefix to this instruction. The mode check depends on this. */ | |
2509 | ||
a78f21af | 2510 | static void |
29134980 OF |
2511 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2512 | { | |
2513 | /* Check if it's an assign addressing mode. */ | |
2514 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2515 | { | |
2516 | /* Assign the prefix value to operand 1. */ | |
2517 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2518 | } | |
2519 | } | |
2520 | ||
2521 | /* Handles the 2-operand BOUND instruction. */ | |
2522 | ||
a78f21af | 2523 | static void |
29134980 OF |
2524 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2525 | { | |
2526 | /* It's invalid to have the PC as the index operand. */ | |
2527 | if (cris_get_operand2 (inst) == REG_PC) | |
2528 | { | |
2529 | inst_env->invalid = 1; | |
2530 | return; | |
2531 | } | |
2532 | /* Check if we have a prefix. */ | |
2533 | if (inst_env->prefix_found) | |
2534 | { | |
2535 | check_assign (inst, inst_env); | |
2536 | } | |
2537 | /* Check if this is an autoincrement mode. */ | |
2538 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2539 | { | |
2540 | /* It's invalid to change the PC in a delay slot. */ | |
2541 | if (inst_env->slot_needed) | |
2542 | { | |
2543 | inst_env->invalid = 1; | |
2544 | return; | |
2545 | } | |
2546 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2547 | } | |
2548 | inst_env->slot_needed = 0; | |
2549 | inst_env->prefix_found = 0; | |
2550 | inst_env->xflag_found = 0; | |
2551 | inst_env->disable_interrupt = 0; | |
2552 | } | |
2553 | ||
2554 | /* Handles the 3-operand BOUND instruction. */ | |
2555 | ||
a78f21af | 2556 | static void |
29134980 OF |
2557 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2558 | { | |
2559 | /* It's an error if we haven't got a prefix. And it's also an error | |
2560 | if the PC is the destination register. */ | |
2561 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2562 | { | |
2563 | inst_env->invalid = 1; | |
2564 | return; | |
2565 | } | |
2566 | inst_env->slot_needed = 0; | |
2567 | inst_env->prefix_found = 0; | |
2568 | inst_env->xflag_found = 0; | |
2569 | inst_env->disable_interrupt = 0; | |
2570 | } | |
2571 | ||
2572 | /* Clears the status flags in inst_env. */ | |
2573 | ||
a78f21af | 2574 | static void |
29134980 OF |
2575 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2576 | { | |
2577 | /* It's an error if we have got a prefix. */ | |
2578 | if (inst_env->prefix_found) | |
2579 | { | |
2580 | inst_env->invalid = 1; | |
2581 | return; | |
2582 | } | |
2583 | ||
2584 | inst_env->slot_needed = 0; | |
2585 | inst_env->prefix_found = 0; | |
2586 | inst_env->xflag_found = 0; | |
2587 | inst_env->disable_interrupt = 0; | |
2588 | } | |
2589 | ||
2590 | /* Clears the status flags in inst_env. */ | |
2591 | ||
a78f21af | 2592 | static void |
29134980 OF |
2593 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2594 | { | |
2595 | /* It's an error if we have got a prefix. */ | |
2596 | if (inst_env->prefix_found) | |
2597 | { | |
2598 | inst_env->invalid = 1; | |
2599 | return; | |
2600 | } | |
2601 | ||
2602 | inst_env->slot_needed = 0; | |
2603 | inst_env->prefix_found = 0; | |
2604 | inst_env->xflag_found = 0; | |
2605 | inst_env->disable_interrupt = 1; | |
2606 | } | |
2607 | ||
2608 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2609 | ||
a78f21af | 2610 | static void |
29134980 OF |
2611 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2612 | { | |
2613 | /* Check if the target is the PC. */ | |
2614 | if (cris_get_operand2 (inst) == REG_PC) | |
2615 | { | |
2616 | /* The instruction will clear the instruction's size bits. */ | |
2617 | int clear_size = cris_get_clear_size (inst); | |
2618 | if (clear_size == INST_BYTE_SIZE) | |
2619 | { | |
2620 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2621 | } | |
2622 | if (clear_size == INST_WORD_SIZE) | |
2623 | { | |
2624 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2625 | } | |
2626 | if (clear_size == INST_DWORD_SIZE) | |
2627 | { | |
2628 | inst_env->delay_slot_pc = 0x0; | |
2629 | } | |
2630 | /* The jump will be delayed with one delay slot. So we need a delay | |
2631 | slot. */ | |
2632 | inst_env->slot_needed = 1; | |
2633 | inst_env->delay_slot_pc_active = 1; | |
2634 | } | |
2635 | else | |
2636 | { | |
2637 | /* The PC will not change => no delay slot. */ | |
2638 | inst_env->slot_needed = 0; | |
2639 | } | |
2640 | inst_env->prefix_found = 0; | |
2641 | inst_env->xflag_found = 0; | |
2642 | inst_env->disable_interrupt = 0; | |
2643 | } | |
2644 | ||
2645 | /* Handles the TEST instruction if it's in register mode. */ | |
2646 | ||
a78f21af | 2647 | static void |
29134980 OF |
2648 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2649 | { | |
2650 | /* It's an error if we have got a prefix. */ | |
2651 | if (inst_env->prefix_found) | |
2652 | { | |
2653 | inst_env->invalid = 1; | |
2654 | return; | |
2655 | } | |
2656 | inst_env->slot_needed = 0; | |
2657 | inst_env->prefix_found = 0; | |
2658 | inst_env->xflag_found = 0; | |
2659 | inst_env->disable_interrupt = 0; | |
2660 | ||
2661 | } | |
2662 | ||
2663 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2664 | in register mode. */ | |
2665 | ||
a78f21af | 2666 | static void |
29134980 OF |
2667 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2668 | { | |
2669 | /* Check if we are in a prefix mode. */ | |
2670 | if (inst_env->prefix_found) | |
2671 | { | |
2672 | /* The only way the PC can change is if this instruction is in | |
2673 | assign addressing mode. */ | |
2674 | check_assign (inst, inst_env); | |
2675 | } | |
2676 | /* Indirect mode can't change the PC so just check if the mode is | |
2677 | autoincrement. */ | |
2678 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2679 | { | |
2680 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2681 | } | |
2682 | inst_env->slot_needed = 0; | |
2683 | inst_env->prefix_found = 0; | |
2684 | inst_env->xflag_found = 0; | |
2685 | inst_env->disable_interrupt = 0; | |
2686 | } | |
2687 | ||
2688 | /* Checks that the PC isn't the destination register or the instructions has | |
2689 | a prefix. */ | |
2690 | ||
a78f21af | 2691 | static void |
29134980 OF |
2692 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2693 | { | |
2694 | /* It's invalid to have the PC as the destination. The instruction can't | |
2695 | have a prefix. */ | |
2696 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2697 | { | |
2698 | inst_env->invalid = 1; | |
2699 | return; | |
2700 | } | |
2701 | ||
2702 | inst_env->slot_needed = 0; | |
2703 | inst_env->prefix_found = 0; | |
2704 | inst_env->xflag_found = 0; | |
2705 | inst_env->disable_interrupt = 0; | |
2706 | } | |
2707 | ||
2708 | /* Checks that the instruction doesn't have a prefix. */ | |
2709 | ||
a78f21af | 2710 | static void |
29134980 OF |
2711 | break_op (unsigned short inst, inst_env_type *inst_env) |
2712 | { | |
2713 | /* The instruction can't have a prefix. */ | |
2714 | if (inst_env->prefix_found) | |
2715 | { | |
2716 | inst_env->invalid = 1; | |
2717 | return; | |
2718 | } | |
2719 | ||
2720 | inst_env->slot_needed = 0; | |
2721 | inst_env->prefix_found = 0; | |
2722 | inst_env->xflag_found = 0; | |
2723 | inst_env->disable_interrupt = 1; | |
2724 | } | |
2725 | ||
2726 | /* Checks that the PC isn't the destination register and that the instruction | |
2727 | doesn't have a prefix. */ | |
2728 | ||
a78f21af | 2729 | static void |
29134980 OF |
2730 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2731 | { | |
2732 | /* It's invalid to have the PC as the destination. The instruction can't | |
2733 | have a prefix. */ | |
2734 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2735 | { | |
2736 | inst_env->invalid = 1; | |
2737 | return; | |
2738 | } | |
2739 | ||
2740 | inst_env->slot_needed = 0; | |
2741 | inst_env->prefix_found = 0; | |
2742 | inst_env->xflag_found = 0; | |
2743 | inst_env->disable_interrupt = 1; | |
2744 | } | |
2745 | ||
2746 | /* Handles the register mode JUMP instruction. */ | |
2747 | ||
a78f21af | 2748 | static void |
29134980 OF |
2749 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2750 | { | |
2751 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2752 | you can't have a prefix. */ | |
2753 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2754 | { | |
2755 | inst_env->invalid = 1; | |
2756 | return; | |
2757 | } | |
2758 | ||
2759 | /* Just change the PC. */ | |
2760 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2761 | inst_env->slot_needed = 0; | |
2762 | inst_env->prefix_found = 0; | |
2763 | inst_env->xflag_found = 0; | |
2764 | inst_env->disable_interrupt = 1; | |
2765 | } | |
2766 | ||
2767 | /* Handles the JUMP instruction for all modes except register. */ | |
2768 | ||
a78f21af AC |
2769 | static void |
2770 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2771 | { |
2772 | unsigned long newpc; | |
2773 | CORE_ADDR address; | |
2774 | ||
2775 | /* It's invalid to do a JUMP in a delay slot. */ | |
2776 | if (inst_env->slot_needed) | |
2777 | { | |
2778 | inst_env->invalid = 1; | |
2779 | } | |
2780 | else | |
2781 | { | |
2782 | /* Check if we have a prefix. */ | |
2783 | if (inst_env->prefix_found) | |
2784 | { | |
2785 | check_assign (inst, inst_env); | |
2786 | ||
b021a221 | 2787 | /* Get the new value for the PC. */ |
29134980 OF |
2788 | newpc = |
2789 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
e17a4113 | 2790 | 4, inst_env->byte_order); |
29134980 OF |
2791 | } |
2792 | else | |
2793 | { | |
2794 | /* Get the new value for the PC. */ | |
2795 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 UW |
2796 | newpc = read_memory_unsigned_integer (address, |
2797 | 4, inst_env->byte_order); | |
29134980 OF |
2798 | |
2799 | /* Check if we should increment a register. */ | |
2800 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2801 | { | |
2802 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2803 | } | |
2804 | } | |
2805 | inst_env->reg[REG_PC] = newpc; | |
2806 | } | |
2807 | inst_env->slot_needed = 0; | |
2808 | inst_env->prefix_found = 0; | |
2809 | inst_env->xflag_found = 0; | |
2810 | inst_env->disable_interrupt = 1; | |
2811 | } | |
2812 | ||
2813 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2814 | ||
a78f21af | 2815 | static void |
be8626e0 MD |
2816 | move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
2817 | inst_env_type *inst_env) | |
29134980 OF |
2818 | { |
2819 | if (inst_env->prefix_found) | |
2820 | { | |
2821 | /* The instruction has a prefix that means we are only interested if | |
2822 | the instruction is in assign mode. */ | |
2823 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2824 | { | |
2825 | /* The prefix handles the problem if we are in a delay slot. */ | |
2826 | if (cris_get_operand1 (inst) == REG_PC) | |
2827 | { | |
2828 | /* Just take care of the assign. */ | |
2829 | check_assign (inst, inst_env); | |
2830 | } | |
2831 | } | |
2832 | } | |
2833 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2834 | { | |
2835 | /* The instruction doesn't have a prefix, the only case left that we | |
2836 | are interested in is the autoincrement mode. */ | |
2837 | if (cris_get_operand1 (inst) == REG_PC) | |
2838 | { | |
2839 | /* If the PC is to be incremented it's invalid to be in a | |
2840 | delay slot. */ | |
2841 | if (inst_env->slot_needed) | |
2842 | { | |
2843 | inst_env->invalid = 1; | |
2844 | return; | |
2845 | } | |
2a9ecef2 OF |
2846 | |
2847 | /* The increment depends on the size of the special register. */ | |
be8626e0 | 2848 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) |
29134980 OF |
2849 | { |
2850 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2851 | } | |
be8626e0 | 2852 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) |
29134980 OF |
2853 | { |
2854 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2855 | } | |
2856 | else | |
2857 | { | |
2858 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2859 | } | |
2860 | } | |
2861 | } | |
2862 | inst_env->slot_needed = 0; | |
2863 | inst_env->prefix_found = 0; | |
2864 | inst_env->xflag_found = 0; | |
2865 | inst_env->disable_interrupt = 1; | |
2866 | } | |
2867 | ||
2868 | /* Handles moves from special registers (aka P-register) for all modes | |
2869 | except register. */ | |
2870 | ||
a78f21af | 2871 | static void |
be8626e0 MD |
2872 | none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
2873 | inst_env_type *inst_env) | |
29134980 OF |
2874 | { |
2875 | if (inst_env->prefix_found) | |
2876 | { | |
2877 | /* The instruction has a prefix that means we are only interested if | |
2878 | the instruction is in assign mode. */ | |
2879 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2880 | { | |
2881 | /* The prefix handles the problem if we are in a delay slot. */ | |
2882 | if (cris_get_operand1 (inst) == REG_PC) | |
2883 | { | |
2884 | /* Just take care of the assign. */ | |
2885 | check_assign (inst, inst_env); | |
2886 | } | |
2887 | } | |
2888 | } | |
2889 | /* The instruction doesn't have a prefix, the only case left that we | |
2890 | are interested in is the autoincrement mode. */ | |
2891 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2892 | { | |
2893 | if (cris_get_operand1 (inst) == REG_PC) | |
2894 | { | |
2895 | /* If the PC is to be incremented it's invalid to be in a | |
2896 | delay slot. */ | |
2897 | if (inst_env->slot_needed) | |
2898 | { | |
2899 | inst_env->invalid = 1; | |
2900 | return; | |
2901 | } | |
2a9ecef2 OF |
2902 | |
2903 | /* The increment depends on the size of the special register. */ | |
be8626e0 | 2904 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) |
29134980 OF |
2905 | { |
2906 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2907 | } | |
be8626e0 | 2908 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) |
29134980 OF |
2909 | { |
2910 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2911 | } | |
2912 | else | |
2913 | { | |
2914 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2915 | } | |
2916 | } | |
2917 | } | |
2918 | inst_env->slot_needed = 0; | |
2919 | inst_env->prefix_found = 0; | |
2920 | inst_env->xflag_found = 0; | |
2921 | inst_env->disable_interrupt = 1; | |
2922 | } | |
2923 | ||
2924 | /* Handles moves from special registers (aka P-register) when the mode | |
2925 | is register. */ | |
2926 | ||
a78f21af | 2927 | static void |
29134980 OF |
2928 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2929 | { | |
2930 | /* Register mode move from special register can't have a prefix. */ | |
2931 | if (inst_env->prefix_found) | |
2932 | { | |
2933 | inst_env->invalid = 1; | |
2934 | return; | |
2935 | } | |
2936 | ||
2937 | if (cris_get_operand1 (inst) == REG_PC) | |
2938 | { | |
2939 | /* It's invalid to change the PC in a delay slot. */ | |
2940 | if (inst_env->slot_needed) | |
2941 | { | |
2942 | inst_env->invalid = 1; | |
2943 | return; | |
2944 | } | |
2945 | /* The destination is the PC, the jump will have a delay slot. */ | |
2946 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
2947 | inst_env->slot_needed = 1; | |
2948 | inst_env->delay_slot_pc_active = 1; | |
2949 | } | |
2950 | else | |
2951 | { | |
2952 | /* If the destination isn't PC, there will be no jump. */ | |
2953 | inst_env->slot_needed = 0; | |
2954 | } | |
2955 | inst_env->prefix_found = 0; | |
2956 | inst_env->xflag_found = 0; | |
2957 | inst_env->disable_interrupt = 1; | |
2958 | } | |
2959 | ||
2960 | /* Handles the MOVEM from memory to general register instruction. */ | |
2961 | ||
a78f21af | 2962 | static void |
29134980 OF |
2963 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
2964 | { | |
2965 | if (inst_env->prefix_found) | |
2966 | { | |
2967 | /* The prefix handles the problem if we are in a delay slot. Is the | |
2968 | MOVEM instruction going to change the PC? */ | |
2969 | if (cris_get_operand2 (inst) >= REG_PC) | |
2970 | { | |
2971 | inst_env->reg[REG_PC] = | |
e17a4113 UW |
2972 | read_memory_unsigned_integer (inst_env->prefix_value, |
2973 | 4, inst_env->byte_order); | |
29134980 OF |
2974 | } |
2975 | /* The assign value is the value after the increment. Normally, the | |
2976 | assign value is the value before the increment. */ | |
2977 | if ((cris_get_operand1 (inst) == REG_PC) | |
2978 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
2979 | { | |
2980 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
2981 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2982 | } | |
2983 | } | |
2984 | else | |
2985 | { | |
2986 | /* Is the MOVEM instruction going to change the PC? */ | |
2987 | if (cris_get_operand2 (inst) == REG_PC) | |
2988 | { | |
2989 | /* It's invalid to change the PC in a delay slot. */ | |
2990 | if (inst_env->slot_needed) | |
2991 | { | |
2992 | inst_env->invalid = 1; | |
2993 | return; | |
2994 | } | |
2995 | inst_env->reg[REG_PC] = | |
2996 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
e17a4113 | 2997 | 4, inst_env->byte_order); |
29134980 OF |
2998 | } |
2999 | /* The increment is not depending on the size, instead it's depending | |
3000 | on the number of registers loaded from memory. */ | |
0963b4bd MS |
3001 | if ((cris_get_operand1 (inst) == REG_PC) |
3002 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
29134980 OF |
3003 | { |
3004 | /* It's invalid to change the PC in a delay slot. */ | |
3005 | if (inst_env->slot_needed) | |
3006 | { | |
3007 | inst_env->invalid = 1; | |
3008 | return; | |
3009 | } | |
3010 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3011 | } | |
3012 | } | |
3013 | inst_env->slot_needed = 0; | |
3014 | inst_env->prefix_found = 0; | |
3015 | inst_env->xflag_found = 0; | |
3016 | inst_env->disable_interrupt = 0; | |
3017 | } | |
3018 | ||
3019 | /* Handles the MOVEM to memory from general register instruction. */ | |
3020 | ||
a78f21af | 3021 | static void |
29134980 OF |
3022 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
3023 | { | |
3024 | if (inst_env->prefix_found) | |
3025 | { | |
3026 | /* The assign value is the value after the increment. Normally, the | |
3027 | assign value is the value before the increment. */ | |
5aafa1cc PM |
3028 | if ((cris_get_operand1 (inst) == REG_PC) |
3029 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
29134980 OF |
3030 | { |
3031 | /* The prefix handles the problem if we are in a delay slot. */ | |
3032 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3033 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3034 | } | |
3035 | } | |
3036 | else | |
3037 | { | |
3038 | /* The increment is not depending on the size, instead it's depending | |
3039 | on the number of registers loaded to memory. */ | |
0963b4bd MS |
3040 | if ((cris_get_operand1 (inst) == REG_PC) |
3041 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
29134980 OF |
3042 | { |
3043 | /* It's invalid to change the PC in a delay slot. */ | |
3044 | if (inst_env->slot_needed) | |
3045 | { | |
3046 | inst_env->invalid = 1; | |
3047 | return; | |
3048 | } | |
3049 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3050 | } | |
3051 | } | |
3052 | inst_env->slot_needed = 0; | |
3053 | inst_env->prefix_found = 0; | |
3054 | inst_env->xflag_found = 0; | |
3055 | inst_env->disable_interrupt = 0; | |
3056 | } | |
3057 | ||
29134980 OF |
3058 | /* Handles the intructions that's not yet implemented, by setting |
3059 | inst_env->invalid to true. */ | |
3060 | ||
a78f21af | 3061 | static void |
29134980 OF |
3062 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
3063 | { | |
3064 | inst_env->invalid = 1; | |
3065 | } | |
3066 | ||
3067 | /* Handles the XOR instruction. */ | |
3068 | ||
a78f21af | 3069 | static void |
29134980 OF |
3070 | xor_op (unsigned short inst, inst_env_type *inst_env) |
3071 | { | |
3072 | /* XOR can't have a prefix. */ | |
3073 | if (inst_env->prefix_found) | |
3074 | { | |
3075 | inst_env->invalid = 1; | |
3076 | return; | |
3077 | } | |
3078 | ||
3079 | /* Check if the PC is the target. */ | |
3080 | if (cris_get_operand2 (inst) == REG_PC) | |
3081 | { | |
3082 | /* It's invalid to change the PC in a delay slot. */ | |
3083 | if (inst_env->slot_needed) | |
3084 | { | |
3085 | inst_env->invalid = 1; | |
3086 | return; | |
3087 | } | |
3088 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
3089 | } | |
3090 | inst_env->slot_needed = 0; | |
3091 | inst_env->prefix_found = 0; | |
3092 | inst_env->xflag_found = 0; | |
3093 | inst_env->disable_interrupt = 0; | |
3094 | } | |
3095 | ||
3096 | /* Handles the MULS instruction. */ | |
3097 | ||
a78f21af | 3098 | static void |
29134980 OF |
3099 | muls_op (unsigned short inst, inst_env_type *inst_env) |
3100 | { | |
3101 | /* MULS/U can't have a prefix. */ | |
3102 | if (inst_env->prefix_found) | |
3103 | { | |
3104 | inst_env->invalid = 1; | |
3105 | return; | |
3106 | } | |
3107 | ||
3108 | /* Consider it invalid if the PC is the target. */ | |
3109 | if (cris_get_operand2 (inst) == REG_PC) | |
3110 | { | |
3111 | inst_env->invalid = 1; | |
3112 | return; | |
3113 | } | |
3114 | inst_env->slot_needed = 0; | |
3115 | inst_env->prefix_found = 0; | |
3116 | inst_env->xflag_found = 0; | |
3117 | inst_env->disable_interrupt = 0; | |
3118 | } | |
3119 | ||
3120 | /* Handles the MULU instruction. */ | |
3121 | ||
a78f21af | 3122 | static void |
29134980 OF |
3123 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
3124 | { | |
3125 | /* MULS/U can't have a prefix. */ | |
3126 | if (inst_env->prefix_found) | |
3127 | { | |
3128 | inst_env->invalid = 1; | |
3129 | return; | |
3130 | } | |
3131 | ||
3132 | /* Consider it invalid if the PC is the target. */ | |
3133 | if (cris_get_operand2 (inst) == REG_PC) | |
3134 | { | |
3135 | inst_env->invalid = 1; | |
3136 | return; | |
3137 | } | |
3138 | inst_env->slot_needed = 0; | |
3139 | inst_env->prefix_found = 0; | |
3140 | inst_env->xflag_found = 0; | |
3141 | inst_env->disable_interrupt = 0; | |
3142 | } | |
3143 | ||
0963b4bd | 3144 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. |
29134980 OF |
3145 | The MOVE instruction is the move from source to register. */ |
3146 | ||
a78f21af | 3147 | static void |
29134980 OF |
3148 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
3149 | unsigned long source1, unsigned long source2) | |
3150 | { | |
3151 | unsigned long pc_mask; | |
3152 | unsigned long operation_mask; | |
3153 | ||
3154 | /* Find out how many bits the operation should apply to. */ | |
3155 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
3156 | { | |
3157 | pc_mask = 0xFFFFFF00; | |
3158 | operation_mask = 0xFF; | |
3159 | } | |
3160 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
3161 | { | |
3162 | pc_mask = 0xFFFF0000; | |
3163 | operation_mask = 0xFFFF; | |
3164 | } | |
3165 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
3166 | { | |
3167 | pc_mask = 0x0; | |
3168 | operation_mask = 0xFFFFFFFF; | |
3169 | } | |
3170 | else | |
3171 | { | |
3172 | /* The size is out of range. */ | |
3173 | inst_env->invalid = 1; | |
3174 | return; | |
3175 | } | |
3176 | ||
3177 | /* The instruction just works on uw_operation_mask bits. */ | |
3178 | source2 &= operation_mask; | |
3179 | source1 &= operation_mask; | |
3180 | ||
3181 | /* Now calculate the result. The opcode's 3 first bits separates | |
3182 | the different actions. */ | |
3183 | switch (cris_get_opcode (inst) & 7) | |
3184 | { | |
3185 | case 0: /* add */ | |
3186 | source1 += source2; | |
3187 | break; | |
3188 | ||
3189 | case 1: /* move */ | |
3190 | source1 = source2; | |
3191 | break; | |
3192 | ||
3193 | case 2: /* subtract */ | |
3194 | source1 -= source2; | |
3195 | break; | |
3196 | ||
3197 | case 3: /* compare */ | |
3198 | break; | |
3199 | ||
3200 | case 4: /* and */ | |
3201 | source1 &= source2; | |
3202 | break; | |
3203 | ||
3204 | case 5: /* or */ | |
3205 | source1 |= source2; | |
3206 | break; | |
3207 | ||
3208 | default: | |
3209 | inst_env->invalid = 1; | |
3210 | return; | |
3211 | ||
3212 | break; | |
3213 | } | |
3214 | ||
3215 | /* Make sure that the result doesn't contain more than the instruction | |
3216 | size bits. */ | |
3217 | source2 &= operation_mask; | |
3218 | ||
3219 | /* Calculate the new breakpoint address. */ | |
3220 | inst_env->reg[REG_PC] &= pc_mask; | |
3221 | inst_env->reg[REG_PC] |= source1; | |
3222 | ||
3223 | } | |
3224 | ||
3225 | /* Extends the value from either byte or word size to a dword. If the mode | |
3226 | is zero extend then the value is extended with zero. If instead the mode | |
3227 | is signed extend the sign bit of the value is taken into consideration. */ | |
3228 | ||
a78f21af | 3229 | static unsigned long |
29134980 OF |
3230 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
3231 | { | |
3232 | /* The size can be either byte or word, check which one it is. | |
3233 | Don't check the highest bit, it's indicating if it's a zero | |
3234 | or sign extend. */ | |
3235 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3236 | { | |
3237 | /* Word size. */ | |
3238 | value &= 0xFFFF; | |
3239 | ||
3240 | /* Check if the instruction is signed extend. If so, check if value has | |
3241 | the sign bit on. */ | |
3242 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3243 | { | |
3244 | value |= SIGNED_WORD_EXTEND_MASK; | |
3245 | } | |
3246 | } | |
3247 | else | |
3248 | { | |
3249 | /* Byte size. */ | |
3250 | value &= 0xFF; | |
3251 | ||
3252 | /* Check if the instruction is signed extend. If so, check if value has | |
3253 | the sign bit on. */ | |
3254 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3255 | { | |
3256 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3257 | } | |
3258 | } | |
3259 | /* The size should now be dword. */ | |
3260 | cris_set_size_to_dword (inst); | |
3261 | return value; | |
3262 | } | |
3263 | ||
3264 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3265 | instruction. The MOVE instruction is the move from source to register. */ | |
3266 | ||
a78f21af | 3267 | static void |
29134980 OF |
3268 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3269 | inst_env_type *inst_env) | |
3270 | { | |
3271 | unsigned long operand1; | |
3272 | unsigned long operand2; | |
3273 | ||
3274 | /* It's invalid to have a prefix to the instruction. This is a register | |
3275 | mode instruction and can't have a prefix. */ | |
3276 | if (inst_env->prefix_found) | |
3277 | { | |
3278 | inst_env->invalid = 1; | |
3279 | return; | |
3280 | } | |
3281 | /* Check if the instruction has PC as its target. */ | |
3282 | if (cris_get_operand2 (inst) == REG_PC) | |
3283 | { | |
3284 | if (inst_env->slot_needed) | |
3285 | { | |
3286 | inst_env->invalid = 1; | |
3287 | return; | |
3288 | } | |
3289 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3290 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3291 | operand2 = inst_env->reg[REG_PC]; |
3292 | ||
3293 | /* Check if it's a extend, signed or zero instruction. */ | |
3294 | if (cris_get_opcode (inst) < 4) | |
3295 | { | |
3296 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3297 | } | |
3298 | /* Calculate the PC value after the instruction, i.e. where the | |
3299 | breakpoint should be. The order of the udw_operands is vital. */ | |
3300 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3301 | } | |
3302 | inst_env->slot_needed = 0; | |
3303 | inst_env->prefix_found = 0; | |
3304 | inst_env->xflag_found = 0; | |
3305 | inst_env->disable_interrupt = 0; | |
3306 | } | |
3307 | ||
3308 | /* Returns the data contained at address. The size of the data is derived from | |
3309 | the size of the operation. If the instruction is a zero or signed | |
3310 | extend instruction, the size field is changed in instruction. */ | |
3311 | ||
a78f21af | 3312 | static unsigned long |
0963b4bd MS |
3313 | get_data_from_address (unsigned short *inst, CORE_ADDR address, |
3314 | enum bfd_endian byte_order) | |
29134980 OF |
3315 | { |
3316 | int size = cris_get_size (*inst); | |
3317 | unsigned long value; | |
3318 | ||
3319 | /* If it's an extend instruction we don't want the signed extend bit, | |
3320 | because it influences the size. */ | |
3321 | if (cris_get_opcode (*inst) < 4) | |
3322 | { | |
3323 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3324 | } | |
3325 | /* Is there a need for checking the size? Size should contain the number of | |
3326 | bytes to read. */ | |
3327 | size = 1 << size; | |
e17a4113 | 3328 | value = read_memory_unsigned_integer (address, size, byte_order); |
29134980 OF |
3329 | |
3330 | /* Check if it's an extend, signed or zero instruction. */ | |
3331 | if (cris_get_opcode (*inst) < 4) | |
3332 | { | |
3333 | value = do_sign_or_zero_extend (value, inst); | |
3334 | } | |
3335 | return value; | |
3336 | } | |
3337 | ||
3338 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3339 | instructions. The MOVE instruction is the move from source to register. */ | |
3340 | ||
a78f21af | 3341 | static void |
29134980 OF |
3342 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
3343 | inst_env_type *inst_env) | |
3344 | { | |
3345 | unsigned long operand2; | |
3346 | unsigned long operand3; | |
3347 | ||
3348 | check_assign (inst, inst_env); | |
3349 | if (cris_get_operand2 (inst) == REG_PC) | |
3350 | { | |
3351 | operand2 = inst_env->reg[REG_PC]; | |
3352 | ||
3353 | /* Get the value of the third operand. */ | |
e17a4113 UW |
3354 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
3355 | inst_env->byte_order); | |
29134980 OF |
3356 | |
3357 | /* Calculate the PC value after the instruction, i.e. where the | |
3358 | breakpoint should be. The order of the udw_operands is vital. */ | |
3359 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3360 | } | |
3361 | inst_env->slot_needed = 0; | |
3362 | inst_env->prefix_found = 0; | |
3363 | inst_env->xflag_found = 0; | |
3364 | inst_env->disable_interrupt = 0; | |
3365 | } | |
3366 | ||
3367 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3368 | OR instructions. Note that for this to work as expected, the calling | |
3369 | function must have made sure that there is a prefix to this instruction. */ | |
3370 | ||
a78f21af | 3371 | static void |
29134980 OF |
3372 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
3373 | inst_env_type *inst_env) | |
3374 | { | |
3375 | unsigned long operand2; | |
3376 | unsigned long operand3; | |
3377 | ||
3378 | if (cris_get_operand1 (inst) == REG_PC) | |
3379 | { | |
3380 | /* The PC will be changed by the instruction. */ | |
3381 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3382 | ||
3383 | /* Get the value of the third operand. */ | |
e17a4113 UW |
3384 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
3385 | inst_env->byte_order); | |
29134980 OF |
3386 | |
3387 | /* Calculate the PC value after the instruction, i.e. where the | |
3388 | breakpoint should be. */ | |
3389 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3390 | } | |
3391 | inst_env->slot_needed = 0; | |
3392 | inst_env->prefix_found = 0; | |
3393 | inst_env->xflag_found = 0; | |
3394 | inst_env->disable_interrupt = 0; | |
3395 | } | |
3396 | ||
3397 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3398 | instructions. The MOVE instruction is the move from source to register. */ | |
3399 | ||
a78f21af | 3400 | static void |
29134980 OF |
3401 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
3402 | inst_env_type *inst_env) | |
3403 | { | |
3404 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3405 | { | |
3406 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3407 | SUB, AND or OR something weird is going on (if everything works these | |
3408 | instructions should end up in the three operand version). */ | |
3409 | inst_env->invalid = 1; | |
3410 | return; | |
3411 | } | |
3412 | else | |
3413 | { | |
3414 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3415 | so use it. */ | |
3416 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3417 | } | |
3418 | inst_env->slot_needed = 0; | |
3419 | inst_env->prefix_found = 0; | |
3420 | inst_env->xflag_found = 0; | |
3421 | inst_env->disable_interrupt = 0; | |
3422 | } | |
3423 | ||
3424 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3425 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3426 | source to register. */ | |
3427 | ||
a78f21af | 3428 | static void |
29134980 OF |
3429 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
3430 | inst_env_type *inst_env) | |
3431 | { | |
3432 | unsigned long operand1; | |
3433 | unsigned long operand2; | |
3434 | unsigned long operand3; | |
3435 | int size; | |
3436 | ||
0963b4bd | 3437 | /* The instruction is either an indirect or autoincrement addressing mode. |
29134980 OF |
3438 | Check if the destination register is the PC. */ |
3439 | if (cris_get_operand2 (inst) == REG_PC) | |
3440 | { | |
3441 | /* Must be done here, get_data_from_address may change the size | |
3442 | field. */ | |
3443 | size = cris_get_size (inst); | |
3444 | operand2 = inst_env->reg[REG_PC]; | |
3445 | ||
3446 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3447 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 | 3448 | operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order); |
29134980 OF |
3449 | |
3450 | /* Calculate the PC value after the instruction, i.e. where the | |
3451 | breakpoint should be. The order of the udw_operands is vital. */ | |
3452 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3453 | } | |
3454 | /* If this is an autoincrement addressing mode, check if the increment | |
3455 | changes the PC. */ | |
0963b4bd MS |
3456 | if ((cris_get_operand1 (inst) == REG_PC) |
3457 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
29134980 OF |
3458 | { |
3459 | /* Get the size field. */ | |
3460 | size = cris_get_size (inst); | |
3461 | ||
3462 | /* If it's an extend instruction we don't want the signed extend bit, | |
3463 | because it influences the size. */ | |
3464 | if (cris_get_opcode (inst) < 4) | |
3465 | { | |
3466 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3467 | } | |
3468 | process_autoincrement (size, inst, inst_env); | |
3469 | } | |
3470 | inst_env->slot_needed = 0; | |
3471 | inst_env->prefix_found = 0; | |
3472 | inst_env->xflag_found = 0; | |
3473 | inst_env->disable_interrupt = 0; | |
3474 | } | |
3475 | ||
3476 | /* Handles the two-operand addressing mode, all modes except register, for | |
3477 | the ADD, SUB CMP, AND and OR instruction. */ | |
3478 | ||
a78f21af | 3479 | static void |
29134980 OF |
3480 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3481 | inst_env_type *inst_env) | |
3482 | { | |
3483 | if (inst_env->prefix_found) | |
3484 | { | |
3485 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3486 | { | |
3487 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3488 | } | |
3489 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3490 | { | |
3491 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3492 | } | |
3493 | else | |
3494 | { | |
3495 | /* The mode is invalid for a prefixed base instruction. */ | |
3496 | inst_env->invalid = 1; | |
3497 | return; | |
3498 | } | |
3499 | } | |
3500 | else | |
3501 | { | |
3502 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3503 | } | |
3504 | } | |
3505 | ||
3506 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3507 | ||
a78f21af | 3508 | static void |
29134980 OF |
3509 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3510 | { | |
3511 | unsigned long operand1; | |
3512 | unsigned long operand2; | |
3513 | ||
3514 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3515 | instruction and can't have a prefix. */ | |
3516 | if (inst_env->prefix_found) | |
3517 | { | |
3518 | inst_env->invalid = 1; | |
3519 | return; | |
3520 | } | |
3521 | ||
3522 | /* Check if the instruction has PC as its target. */ | |
3523 | if (cris_get_operand2 (inst) == REG_PC) | |
3524 | { | |
3525 | if (inst_env->slot_needed) | |
3526 | { | |
3527 | inst_env->invalid = 1; | |
3528 | return; | |
3529 | } | |
3530 | operand1 = cris_get_quick_value (inst); | |
3531 | operand2 = inst_env->reg[REG_PC]; | |
3532 | ||
3533 | /* The size should now be dword. */ | |
3534 | cris_set_size_to_dword (&inst); | |
3535 | ||
3536 | /* Calculate the PC value after the instruction, i.e. where the | |
3537 | breakpoint should be. */ | |
3538 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3539 | } | |
3540 | inst_env->slot_needed = 0; | |
3541 | inst_env->prefix_found = 0; | |
3542 | inst_env->xflag_found = 0; | |
3543 | inst_env->disable_interrupt = 0; | |
3544 | } | |
3545 | ||
3546 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3547 | ||
a78f21af | 3548 | static void |
29134980 OF |
3549 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3550 | { | |
3551 | unsigned long operand1; | |
3552 | unsigned long operand2; | |
3553 | ||
3554 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3555 | instruction and can't have a prefix. */ | |
3556 | if (inst_env->prefix_found) | |
3557 | { | |
3558 | inst_env->invalid = 1; | |
3559 | return; | |
3560 | } | |
3561 | /* Check if the instruction has PC as its target. */ | |
3562 | if (cris_get_operand2 (inst) == REG_PC) | |
3563 | { | |
3564 | if (inst_env->slot_needed) | |
3565 | { | |
3566 | inst_env->invalid = 1; | |
3567 | return; | |
3568 | } | |
3569 | /* The instruction has the PC as its target register. */ | |
3570 | operand1 = cris_get_quick_value (inst); | |
3571 | operand2 = inst_env->reg[REG_PC]; | |
3572 | ||
3573 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3574 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3575 | { | |
3576 | /* sign extend */ | |
3577 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3578 | } | |
3579 | /* The size should now be dword. */ | |
3580 | cris_set_size_to_dword (&inst); | |
3581 | ||
3582 | /* Calculate the PC value after the instruction, i.e. where the | |
3583 | breakpoint should be. */ | |
3584 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3585 | } | |
3586 | inst_env->slot_needed = 0; | |
3587 | inst_env->prefix_found = 0; | |
3588 | inst_env->xflag_found = 0; | |
3589 | inst_env->disable_interrupt = 0; | |
3590 | } | |
3591 | ||
3592 | /* Translate op_type to a function and call it. */ | |
3593 | ||
a78f21af | 3594 | static void |
be8626e0 MD |
3595 | cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type, |
3596 | unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
3597 | { |
3598 | switch (op_type) | |
3599 | { | |
3600 | case cris_not_implemented_op: | |
3601 | not_implemented_op (inst, inst_env); | |
3602 | break; | |
3603 | ||
3604 | case cris_abs_op: | |
3605 | abs_op (inst, inst_env); | |
3606 | break; | |
3607 | ||
3608 | case cris_addi_op: | |
3609 | addi_op (inst, inst_env); | |
3610 | break; | |
3611 | ||
3612 | case cris_asr_op: | |
3613 | asr_op (inst, inst_env); | |
3614 | break; | |
3615 | ||
3616 | case cris_asrq_op: | |
3617 | asrq_op (inst, inst_env); | |
3618 | break; | |
3619 | ||
3620 | case cris_ax_ei_setf_op: | |
3621 | ax_ei_setf_op (inst, inst_env); | |
3622 | break; | |
3623 | ||
3624 | case cris_bdap_prefix: | |
3625 | bdap_prefix (inst, inst_env); | |
3626 | break; | |
3627 | ||
3628 | case cris_biap_prefix: | |
3629 | biap_prefix (inst, inst_env); | |
3630 | break; | |
3631 | ||
3632 | case cris_break_op: | |
3633 | break_op (inst, inst_env); | |
3634 | break; | |
3635 | ||
3636 | case cris_btst_nop_op: | |
3637 | btst_nop_op (inst, inst_env); | |
3638 | break; | |
3639 | ||
3640 | case cris_clearf_di_op: | |
3641 | clearf_di_op (inst, inst_env); | |
3642 | break; | |
3643 | ||
3644 | case cris_dip_prefix: | |
3645 | dip_prefix (inst, inst_env); | |
3646 | break; | |
3647 | ||
3648 | case cris_dstep_logshift_mstep_neg_not_op: | |
3649 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3650 | break; | |
3651 | ||
3652 | case cris_eight_bit_offset_branch_op: | |
3653 | eight_bit_offset_branch_op (inst, inst_env); | |
3654 | break; | |
3655 | ||
3656 | case cris_move_mem_to_reg_movem_op: | |
3657 | move_mem_to_reg_movem_op (inst, inst_env); | |
3658 | break; | |
3659 | ||
3660 | case cris_move_reg_to_mem_movem_op: | |
3661 | move_reg_to_mem_movem_op (inst, inst_env); | |
3662 | break; | |
3663 | ||
3664 | case cris_move_to_preg_op: | |
be8626e0 | 3665 | move_to_preg_op (gdbarch, inst, inst_env); |
29134980 OF |
3666 | break; |
3667 | ||
3668 | case cris_muls_op: | |
3669 | muls_op (inst, inst_env); | |
3670 | break; | |
3671 | ||
3672 | case cris_mulu_op: | |
3673 | mulu_op (inst, inst_env); | |
3674 | break; | |
3675 | ||
3676 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3677 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3678 | break; | |
3679 | ||
3680 | case cris_none_reg_mode_clear_test_op: | |
3681 | none_reg_mode_clear_test_op (inst, inst_env); | |
3682 | break; | |
3683 | ||
3684 | case cris_none_reg_mode_jump_op: | |
3685 | none_reg_mode_jump_op (inst, inst_env); | |
3686 | break; | |
3687 | ||
3688 | case cris_none_reg_mode_move_from_preg_op: | |
be8626e0 | 3689 | none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env); |
29134980 OF |
3690 | break; |
3691 | ||
3692 | case cris_quick_mode_add_sub_op: | |
3693 | quick_mode_add_sub_op (inst, inst_env); | |
3694 | break; | |
3695 | ||
3696 | case cris_quick_mode_and_cmp_move_or_op: | |
3697 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3698 | break; | |
3699 | ||
3700 | case cris_quick_mode_bdap_prefix: | |
3701 | quick_mode_bdap_prefix (inst, inst_env); | |
3702 | break; | |
3703 | ||
3704 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3705 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3706 | break; | |
3707 | ||
3708 | case cris_reg_mode_clear_op: | |
3709 | reg_mode_clear_op (inst, inst_env); | |
3710 | break; | |
3711 | ||
3712 | case cris_reg_mode_jump_op: | |
3713 | reg_mode_jump_op (inst, inst_env); | |
3714 | break; | |
3715 | ||
3716 | case cris_reg_mode_move_from_preg_op: | |
3717 | reg_mode_move_from_preg_op (inst, inst_env); | |
3718 | break; | |
3719 | ||
3720 | case cris_reg_mode_test_op: | |
3721 | reg_mode_test_op (inst, inst_env); | |
3722 | break; | |
3723 | ||
3724 | case cris_scc_op: | |
3725 | scc_op (inst, inst_env); | |
3726 | break; | |
3727 | ||
3728 | case cris_sixteen_bit_offset_branch_op: | |
3729 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3730 | break; | |
3731 | ||
3732 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3733 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3734 | break; | |
3735 | ||
3736 | case cris_three_operand_bound_op: | |
3737 | three_operand_bound_op (inst, inst_env); | |
3738 | break; | |
3739 | ||
3740 | case cris_two_operand_bound_op: | |
3741 | two_operand_bound_op (inst, inst_env); | |
3742 | break; | |
3743 | ||
3744 | case cris_xor_op: | |
3745 | xor_op (inst, inst_env); | |
3746 | break; | |
3747 | } | |
3748 | } | |
3749 | ||
18b3c2f5 RW |
3750 | /* Originally from <asm/elf.h>. */ |
3751 | typedef unsigned char cris_elf_greg_t[4]; | |
dbbff683 OF |
3752 | |
3753 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
c600d464 | 3754 | #define CRISV10_ELF_NGREG 35 |
18b3c2f5 | 3755 | typedef cris_elf_greg_t cris_elf_gregset_t[CRISV10_ELF_NGREG]; |
c600d464 OF |
3756 | |
3757 | #define CRISV32_ELF_NGREG 32 | |
18b3c2f5 | 3758 | typedef cris_elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; |
dbbff683 | 3759 | |
18b3c2f5 | 3760 | /* Unpack a cris_elf_gregset_t into GDB's register cache. */ |
dbbff683 | 3761 | |
a78f21af | 3762 | static void |
18b3c2f5 | 3763 | cris_supply_gregset (struct regcache *regcache, cris_elf_gregset_t *gregsetp) |
dbbff683 | 3764 | { |
ac7936df | 3765 | struct gdbarch *gdbarch = regcache->arch (); |
7fbe2eba | 3766 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
dbbff683 | 3767 | int i; |
18b3c2f5 | 3768 | cris_elf_greg_t *regp = *gregsetp; |
dbbff683 OF |
3769 | |
3770 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3771 | knows about the actual size of each register so that's no problem. */ | |
3772 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3773 | { | |
73e1c03f | 3774 | regcache->raw_supply (i, (char *)®p[i]); |
dbbff683 | 3775 | } |
c600d464 OF |
3776 | |
3777 | if (tdep->cris_version == 32) | |
3778 | { | |
3779 | /* Needed to set pseudo-register PC for CRISv32. */ | |
3780 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
3781 | be wrong. Issue a warning to alert the user. */ | |
73e1c03f SM |
3782 | regcache->raw_supply (gdbarch_pc_regnum (gdbarch), |
3783 | (char *)®p[ERP_REGNUM]); | |
c600d464 OF |
3784 | |
3785 | if (*(char *)®p[ERP_REGNUM] & 0x1) | |
3786 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); | |
3787 | } | |
dbbff683 OF |
3788 | } |
3789 | ||
3790 | /* Use a local version of this function to get the correct types for | |
3791 | regsets, until multi-arch core support is ready. */ | |
3792 | ||
3793 | static void | |
9eefc95f UW |
3794 | fetch_core_registers (struct regcache *regcache, |
3795 | char *core_reg_sect, unsigned core_reg_size, | |
dbbff683 OF |
3796 | int which, CORE_ADDR reg_addr) |
3797 | { | |
18b3c2f5 | 3798 | cris_elf_gregset_t gregset; |
dbbff683 OF |
3799 | |
3800 | switch (which) | |
3801 | { | |
3802 | case 0: | |
18b3c2f5 | 3803 | if (core_reg_size != sizeof (cris_elf_gregset_t) |
c600d464 | 3804 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) |
dbbff683 | 3805 | { |
8a3fe4f8 | 3806 | warning (_("wrong size gregset struct in core file")); |
dbbff683 OF |
3807 | } |
3808 | else | |
3809 | { | |
3810 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
9eefc95f | 3811 | cris_supply_gregset (regcache, &gregset); |
dbbff683 OF |
3812 | } |
3813 | ||
3814 | default: | |
3815 | /* We've covered all the kinds of registers we know about here, | |
3816 | so this must be something we wouldn't know what to do with | |
3817 | anyway. Just ignore it. */ | |
3818 | break; | |
3819 | } | |
3820 | } | |
3821 | ||
3822 | static struct core_fns cris_elf_core_fns = | |
3823 | { | |
3824 | bfd_target_elf_flavour, /* core_flavour */ | |
3825 | default_check_format, /* check_format */ | |
3826 | default_core_sniffer, /* core_sniffer */ | |
3827 | fetch_core_registers, /* core_read_registers */ | |
3828 | NULL /* next */ | |
3829 | }; | |
3830 | ||
29134980 OF |
3831 | void |
3832 | _initialize_cris_tdep (void) | |
3833 | { | |
29134980 OF |
3834 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); |
3835 | ||
29134980 | 3836 | /* CRIS-specific user-commands. */ |
addb4faf PA |
3837 | add_setshow_zuinteger_cmd ("cris-version", class_support, |
3838 | &usr_cmd_cris_version, | |
3839 | _("Set the current CRIS version."), | |
3840 | _("Show the current CRIS version."), | |
3841 | _("\ | |
bdd56253 OF |
3842 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ |
3843 | Defaults to 10. "), | |
addb4faf PA |
3844 | set_cris_version, |
3845 | NULL, /* FIXME: i18n: Current CRIS version | |
3846 | is %s. */ | |
3847 | &setlist, &showlist); | |
0e6bdb31 OF |
3848 | |
3849 | add_setshow_enum_cmd ("cris-mode", class_support, | |
3850 | cris_modes, &usr_cmd_cris_mode, | |
3851 | _("Set the current CRIS mode."), | |
3852 | _("Show the current CRIS mode."), | |
bdd56253 OF |
3853 | _("\ |
3854 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ | |
3855 | Makes GDB use the NRP register instead of the ERP register in certain cases."), | |
0e6bdb31 OF |
3856 | set_cris_mode, |
3857 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ | |
3858 | &setlist, &showlist); | |
dbbff683 | 3859 | |
a5f6c8f5 OF |
3860 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
3861 | &usr_cmd_cris_dwarf2_cfi, | |
7915a72c AC |
3862 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
3863 | _("Show the usage of Dwarf-2 CFI for CRIS."), | |
bdd56253 | 3864 | _("Set this to \"off\" if using gcc-cris < R59."), |
2c5b56ce | 3865 | set_cris_dwarf2_cfi, |
0963b4bd MS |
3866 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI |
3867 | for CRIS is %d. */ | |
a5f6c8f5 OF |
3868 | &setlist, &showlist); |
3869 | ||
52bd1401 | 3870 | deprecated_add_core_fns (&cris_elf_core_fns); |
29134980 OF |
3871 | } |
3872 | ||
3873 | /* Prints out all target specific values. */ | |
3874 | ||
3875 | static void | |
3876 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3877 | { | |
7fbe2eba | 3878 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
29134980 OF |
3879 | if (tdep != NULL) |
3880 | { | |
3881 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
3882 | tdep->cris_version); | |
0e6bdb31 OF |
3883 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
3884 | tdep->cris_mode); | |
a5f6c8f5 OF |
3885 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
3886 | tdep->cris_dwarf2_cfi); | |
29134980 OF |
3887 | } |
3888 | } | |
3889 | ||
3890 | static void | |
eb4c3f4a | 3891 | set_cris_version (const char *ignore_args, int from_tty, |
a5f6c8f5 | 3892 | struct cmd_list_element *c) |
29134980 OF |
3893 | { |
3894 | struct gdbarch_info info; | |
3895 | ||
a5f6c8f5 | 3896 | usr_cmd_cris_version_valid = 1; |
29134980 | 3897 | |
a5f6c8f5 OF |
3898 | /* Update the current architecture, if needed. */ |
3899 | gdbarch_info_init (&info); | |
3900 | if (!gdbarch_update_p (info)) | |
3901 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 3902 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
3903 | } |
3904 | ||
0e6bdb31 | 3905 | static void |
eb4c3f4a | 3906 | set_cris_mode (const char *ignore_args, int from_tty, |
0e6bdb31 OF |
3907 | struct cmd_list_element *c) |
3908 | { | |
3909 | struct gdbarch_info info; | |
3910 | ||
3911 | /* Update the current architecture, if needed. */ | |
3912 | gdbarch_info_init (&info); | |
3913 | if (!gdbarch_update_p (info)) | |
3914 | internal_error (__FILE__, __LINE__, | |
3915 | "cris_gdbarch_update: failed to update architecture."); | |
3916 | } | |
3917 | ||
29134980 | 3918 | static void |
eb4c3f4a | 3919 | set_cris_dwarf2_cfi (const char *ignore_args, int from_tty, |
a5f6c8f5 | 3920 | struct cmd_list_element *c) |
29134980 OF |
3921 | { |
3922 | struct gdbarch_info info; | |
a5f6c8f5 OF |
3923 | |
3924 | /* Update the current architecture, if needed. */ | |
3925 | gdbarch_info_init (&info); | |
3926 | if (!gdbarch_update_p (info)) | |
3927 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 3928 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
3929 | } |
3930 | ||
29134980 OF |
3931 | static struct gdbarch * |
3932 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3933 | { | |
3934 | struct gdbarch *gdbarch; | |
3935 | struct gdbarch_tdep *tdep; | |
e4286e57 | 3936 | unsigned int cris_version; |
29134980 OF |
3937 | |
3938 | if (usr_cmd_cris_version_valid) | |
3939 | { | |
3940 | /* Trust the user's CRIS version setting. */ | |
3941 | cris_version = usr_cmd_cris_version; | |
3942 | } | |
c600d464 OF |
3943 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
3944 | { | |
3945 | cris_version = 32; | |
3946 | } | |
29134980 OF |
3947 | else |
3948 | { | |
3949 | /* Assume it's CRIS version 10. */ | |
3950 | cris_version = 10; | |
3951 | } | |
3952 | ||
29134980 OF |
3953 | /* Make the current settings visible to the user. */ |
3954 | usr_cmd_cris_version = cris_version; | |
29134980 | 3955 | |
0e6bdb31 | 3956 | /* Find a candidate among the list of pre-declared architectures. */ |
29134980 OF |
3957 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
3958 | arches != NULL; | |
3959 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3960 | { | |
a5f6c8f5 OF |
3961 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
3962 | == usr_cmd_cris_version) | |
0e6bdb31 OF |
3963 | && (gdbarch_tdep (arches->gdbarch)->cris_mode |
3964 | == usr_cmd_cris_mode) | |
a5f6c8f5 OF |
3965 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi |
3966 | == usr_cmd_cris_dwarf2_cfi)) | |
29134980 OF |
3967 | return arches->gdbarch; |
3968 | } | |
3969 | ||
3970 | /* No matching architecture was found. Create a new one. */ | |
cdd238da | 3971 | tdep = XCNEW (struct gdbarch_tdep); |
7cf1de6c | 3972 | info.byte_order = BFD_ENDIAN_LITTLE; |
29134980 OF |
3973 | gdbarch = gdbarch_alloc (&info, tdep); |
3974 | ||
a5f6c8f5 | 3975 | tdep->cris_version = usr_cmd_cris_version; |
0e6bdb31 | 3976 | tdep->cris_mode = usr_cmd_cris_mode; |
a5f6c8f5 | 3977 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
29134980 | 3978 | |
b4206d25 | 3979 | set_gdbarch_return_value (gdbarch, cris_return_value); |
29134980 | 3980 | set_gdbarch_sp_regnum (gdbarch, 14); |
c600d464 OF |
3981 | |
3982 | /* Length of ordinary registers used in push_word and a few other | |
3983 | places. register_size() is the real way to know how big a | |
3984 | register is. */ | |
a5f6c8f5 | 3985 | |
2e4b5889 | 3986 | set_gdbarch_double_bit (gdbarch, 64); |
ea06eb3d | 3987 | /* The default definition of a long double is 2 * gdbarch_double_bit, |
2e4b5889 | 3988 | which means we have to set this explicitly. */ |
c600d464 | 3989 | set_gdbarch_long_double_bit (gdbarch, 64); |
29134980 | 3990 | |
29134980 OF |
3991 | /* The total amount of space needed to store (in an array called registers) |
3992 | GDB's copy of the machine's register state. Note: We can not use | |
d93859e2 | 3993 | cris_register_size at this point, since it relies on gdbarch |
29134980 OF |
3994 | being set. */ |
3995 | switch (tdep->cris_version) | |
3996 | { | |
3997 | case 0: | |
3998 | case 1: | |
3999 | case 2: | |
4000 | case 3: | |
29134980 OF |
4001 | case 8: |
4002 | case 9: | |
a5f6c8f5 | 4003 | /* Old versions; not supported. */ |
114d7832 | 4004 | return 0; |
29134980 OF |
4005 | |
4006 | case 10: | |
4007 | case 11: | |
4008 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
4009 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
c600d464 OF |
4010 | set_gdbarch_pc_regnum (gdbarch, 15); |
4011 | set_gdbarch_register_type (gdbarch, cris_register_type); | |
4012 | /* There are 32 registers (some of which may not be implemented). */ | |
4013 | set_gdbarch_num_regs (gdbarch, 32); | |
4014 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
4015 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
4016 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
4017 | ||
4018 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
4019 | break; | |
4020 | ||
4021 | case 32: | |
4022 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers | |
4023 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) | |
4024 | and pseudo-register PC (32 bits). */ | |
4025 | set_gdbarch_pc_regnum (gdbarch, 32); | |
4026 | set_gdbarch_register_type (gdbarch, crisv32_register_type); | |
4027 | /* 32 registers + pseudo-register PC + 16 support registers. */ | |
4028 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); | |
4029 | set_gdbarch_register_name (gdbarch, crisv32_register_name); | |
4030 | ||
4031 | set_gdbarch_cannot_store_register | |
4032 | (gdbarch, crisv32_cannot_store_register); | |
4033 | set_gdbarch_cannot_fetch_register | |
4034 | (gdbarch, crisv32_cannot_fetch_register); | |
4035 | ||
4036 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
4037 | ||
4038 | set_gdbarch_single_step_through_delay | |
4039 | (gdbarch, crisv32_single_step_through_delay); | |
4040 | ||
29134980 OF |
4041 | break; |
4042 | ||
4043 | default: | |
114d7832 PA |
4044 | /* Unknown version. */ |
4045 | return 0; | |
29134980 OF |
4046 | } |
4047 | ||
c600d464 OF |
4048 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
4049 | have the same ABI). */ | |
2e4b5889 OF |
4050 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
4051 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
4052 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 4053 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
4054 | |
4055 | /* The stack grows downward. */ | |
4056 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4057 | ||
04180708 YQ |
4058 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, cris_breakpoint_kind_from_pc); |
4059 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, cris_sw_breakpoint_from_kind); | |
29134980 | 4060 | |
a5f6c8f5 OF |
4061 | if (tdep->cris_dwarf2_cfi == 1) |
4062 | { | |
4063 | /* Hook in the Dwarf-2 frame sniffer. */ | |
4064 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); | |
4065 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); | |
94afd7a6 | 4066 | dwarf2_append_unwinders (gdbarch); |
a5f6c8f5 OF |
4067 | } |
4068 | ||
0e6bdb31 OF |
4069 | if (tdep->cris_mode != cris_mode_guru) |
4070 | { | |
94afd7a6 | 4071 | frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind); |
0e6bdb31 | 4072 | } |
a5f6c8f5 | 4073 | |
94afd7a6 | 4074 | frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind); |
2e4b5889 | 4075 | frame_base_set_default (gdbarch, &cris_frame_base); |
6c0e89ed | 4076 | |
749c8b38 RW |
4077 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4078 | gdbarch_init_osabi (info, gdbarch); | |
4079 | ||
29134980 OF |
4080 | return gdbarch; |
4081 | } |