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29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 | 2 | |
6aba47ca | 3 | Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
76a9d10f | 4 | Free Software Foundation, Inc. |
6b4d5c91 | 5 | |
29134980 OF |
6 | Contributed by Axis Communications AB. |
7 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
8 | ||
9 | This file is part of GDB. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
23 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
24 | Boston, MA 02110-1301, USA. */ | |
29134980 OF |
25 | |
26 | #include "defs.h" | |
27 | #include "frame.h" | |
2e4b5889 OF |
28 | #include "frame-unwind.h" |
29 | #include "frame-base.h" | |
30 | #include "trad-frame.h" | |
31 | #include "dwarf2-frame.h" | |
29134980 OF |
32 | #include "symtab.h" |
33 | #include "inferior.h" | |
34 | #include "gdbtypes.h" | |
35 | #include "gdbcore.h" | |
36 | #include "gdbcmd.h" | |
37 | #include "target.h" | |
38 | #include "value.h" | |
39 | #include "opcode/cris.h" | |
40 | #include "arch-utils.h" | |
41 | #include "regcache.h" | |
36482093 | 42 | #include "gdb_assert.h" |
29134980 OF |
43 | |
44 | /* To get entry_point_address. */ | |
9ab9195f | 45 | #include "objfiles.h" |
29134980 | 46 | |
a5f6c8f5 | 47 | #include "solib.h" /* Support for shared libraries. */ |
76a9d10f | 48 | #include "solib-svr4.h" |
9bbe19fb | 49 | #include "gdb_string.h" |
a89aa300 | 50 | #include "dis-asm.h" |
dbbff683 | 51 | |
29134980 OF |
52 | enum cris_num_regs |
53 | { | |
54 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
55 | NUM_FREGS = 0, | |
56 | ||
57 | /* There are 16 general registers. */ | |
58 | NUM_GENREGS = 16, | |
59 | ||
60 | /* There are 16 special registers. */ | |
c600d464 OF |
61 | NUM_SPECREGS = 16, |
62 | ||
63 | /* CRISv32 has a pseudo PC register, not noted here. */ | |
64 | ||
65 | /* CRISv32 has 16 support registers. */ | |
66 | NUM_SUPPREGS = 16 | |
29134980 OF |
67 | }; |
68 | ||
69 | /* Register numbers of various important registers. | |
2e4b5889 | 70 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
71 | STR_REGNUM Contains the address of structure return values. |
72 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
73 | ARG1_REGNUM Contains the first parameter to a function. | |
74 | ARG2_REGNUM Contains the second parameter to a function. | |
75 | ARG3_REGNUM Contains the third parameter to a function. | |
76 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. | |
77 | SP_REGNUM Contains address of top of stack. | |
78 | PC_REGNUM Contains address of next instruction. | |
79 | SRP_REGNUM Subroutine return pointer register. | |
80 | BRP_REGNUM Breakpoint return pointer register. */ | |
81 | ||
29134980 OF |
82 | enum cris_regnums |
83 | { | |
84 | /* Enums with respect to the general registers, valid for all | |
c600d464 | 85 | CRIS versions. The frame pointer is always in R8. */ |
2e4b5889 | 86 | CRIS_FP_REGNUM = 8, |
c600d464 | 87 | /* ABI related registers. */ |
29134980 OF |
88 | STR_REGNUM = 9, |
89 | RET_REGNUM = 10, | |
90 | ARG1_REGNUM = 10, | |
91 | ARG2_REGNUM = 11, | |
92 | ARG3_REGNUM = 12, | |
93 | ARG4_REGNUM = 13, | |
94 | ||
c600d464 | 95 | /* Registers which happen to be common. */ |
29134980 | 96 | VR_REGNUM = 17, |
c600d464 OF |
97 | MOF_REGNUM = 23, |
98 | SRP_REGNUM = 27, | |
99 | ||
100 | /* CRISv10 et. al. specific registers. */ | |
101 | P0_REGNUM = 16, | |
29134980 OF |
102 | P4_REGNUM = 20, |
103 | CCR_REGNUM = 21, | |
29134980 OF |
104 | P8_REGNUM = 24, |
105 | IBR_REGNUM = 25, | |
106 | IRP_REGNUM = 26, | |
29134980 | 107 | BAR_REGNUM = 28, |
2a9ecef2 | 108 | DCCR_REGNUM = 29, |
29134980 | 109 | BRP_REGNUM = 30, |
c600d464 OF |
110 | USP_REGNUM = 31, |
111 | ||
112 | /* CRISv32 specific registers. */ | |
113 | ACR_REGNUM = 15, | |
114 | BZ_REGNUM = 16, | |
115 | PID_REGNUM = 18, | |
116 | SRS_REGNUM = 19, | |
117 | WZ_REGNUM = 20, | |
118 | EXS_REGNUM = 21, | |
119 | EDA_REGNUM = 22, | |
120 | DZ_REGNUM = 24, | |
121 | EBP_REGNUM = 25, | |
122 | ERP_REGNUM = 26, | |
123 | NRP_REGNUM = 28, | |
124 | CCS_REGNUM = 29, | |
125 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ | |
126 | SPC_REGNUM = 31, | |
127 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ | |
128 | ||
129 | S0_REGNUM = 33, | |
130 | S1_REGNUM = 34, | |
131 | S2_REGNUM = 35, | |
132 | S3_REGNUM = 36, | |
133 | S4_REGNUM = 37, | |
134 | S5_REGNUM = 38, | |
135 | S6_REGNUM = 39, | |
136 | S7_REGNUM = 40, | |
137 | S8_REGNUM = 41, | |
138 | S9_REGNUM = 42, | |
139 | S10_REGNUM = 43, | |
140 | S11_REGNUM = 44, | |
141 | S12_REGNUM = 45, | |
142 | S13_REGNUM = 46, | |
143 | S14_REGNUM = 47, | |
144 | S15_REGNUM = 48, | |
29134980 OF |
145 | }; |
146 | ||
147 | extern const struct cris_spec_reg cris_spec_regs[]; | |
148 | ||
149 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
0e6bdb31 OF |
150 | register names and sizes. */ |
151 | static int usr_cmd_cris_version; | |
29134980 OF |
152 | |
153 | /* Indicates whether to trust the above variable. */ | |
154 | static int usr_cmd_cris_version_valid = 0; | |
155 | ||
41922353 OF |
156 | static const char cris_mode_normal[] = "normal"; |
157 | static const char cris_mode_guru[] = "guru"; | |
0e6bdb31 OF |
158 | static const char *cris_modes[] = { |
159 | cris_mode_normal, | |
160 | cris_mode_guru, | |
161 | 0 | |
162 | }; | |
163 | ||
164 | /* CRIS mode, set via the user command 'set cris-mode'. Affects | |
165 | type of break instruction among other things. */ | |
166 | static const char *usr_cmd_cris_mode = cris_mode_normal; | |
167 | ||
a5f6c8f5 OF |
168 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
169 | static int usr_cmd_cris_dwarf2_cfi = 1; | |
29134980 | 170 | |
29134980 OF |
171 | /* CRIS architecture specific information. */ |
172 | struct gdbarch_tdep | |
173 | { | |
0e6bdb31 OF |
174 | int cris_version; |
175 | const char *cris_mode; | |
a5f6c8f5 | 176 | int cris_dwarf2_cfi; |
29134980 OF |
177 | }; |
178 | ||
179 | /* Functions for accessing target dependent data. */ | |
180 | ||
181 | static int | |
182 | cris_version (void) | |
183 | { | |
184 | return (gdbarch_tdep (current_gdbarch)->cris_version); | |
185 | } | |
186 | ||
0e6bdb31 OF |
187 | static const char * |
188 | cris_mode (void) | |
189 | { | |
190 | return (gdbarch_tdep (current_gdbarch)->cris_mode); | |
191 | } | |
192 | ||
a5f6c8f5 OF |
193 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
194 | ||
195 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ | |
196 | #define SIGTRAMP_OFFSET0 0 | |
197 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ | |
198 | #define SIGTRAMP_OFFSET1 4 | |
199 | ||
200 | static const unsigned short sigtramp_code[] = | |
201 | { | |
202 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ | |
203 | SIGTRAMP_INSN1 /* break 13 */ | |
204 | }; | |
205 | ||
206 | #define SIGTRAMP_LEN (sizeof sigtramp_code) | |
207 | ||
208 | /* Note: same length as normal sigtramp code. */ | |
209 | ||
210 | static const unsigned short rt_sigtramp_code[] = | |
29134980 | 211 | { |
a5f6c8f5 OF |
212 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
213 | SIGTRAMP_INSN1 /* break 13 */ | |
214 | }; | |
215 | ||
216 | /* If PC is in a sigtramp routine, return the address of the start of | |
217 | the routine. Otherwise, return 0. */ | |
218 | ||
219 | static CORE_ADDR | |
220 | cris_sigtramp_start (struct frame_info *next_frame) | |
221 | { | |
222 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
e2a2a3e8 | 223 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 OF |
224 | |
225 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
226 | return 0; | |
227 | ||
e2a2a3e8 | 228 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 229 | { |
e2a2a3e8 | 230 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
231 | return 0; |
232 | ||
233 | pc -= SIGTRAMP_OFFSET1; | |
234 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
235 | return 0; | |
236 | } | |
237 | ||
238 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) | |
239 | return 0; | |
240 | ||
241 | return pc; | |
242 | } | |
243 | ||
244 | /* If PC is in a RT sigtramp routine, return the address of the start of | |
245 | the routine. Otherwise, return 0. */ | |
246 | ||
247 | static CORE_ADDR | |
248 | cris_rt_sigtramp_start (struct frame_info *next_frame) | |
249 | { | |
250 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
e2a2a3e8 | 251 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 OF |
252 | |
253 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
254 | return 0; | |
255 | ||
e2a2a3e8 | 256 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 257 | { |
e2a2a3e8 | 258 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
259 | return 0; |
260 | ||
261 | pc -= SIGTRAMP_OFFSET1; | |
262 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
263 | return 0; | |
264 | } | |
265 | ||
266 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) | |
267 | return 0; | |
268 | ||
269 | return pc; | |
270 | } | |
271 | ||
272 | /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp | |
273 | routine, return the address of the associated sigcontext structure. */ | |
274 | ||
275 | static CORE_ADDR | |
276 | cris_sigcontext_addr (struct frame_info *next_frame) | |
277 | { | |
278 | CORE_ADDR pc; | |
279 | CORE_ADDR sp; | |
280 | char buf[4]; | |
281 | ||
282 | frame_unwind_register (next_frame, SP_REGNUM, buf); | |
283 | sp = extract_unsigned_integer (buf, 4); | |
284 | ||
285 | /* Look for normal sigtramp frame first. */ | |
286 | pc = cris_sigtramp_start (next_frame); | |
287 | if (pc) | |
288 | { | |
289 | /* struct signal_frame (arch/cris/kernel/signal.c) contains | |
290 | struct sigcontext as its first member, meaning the SP points to | |
291 | it already. */ | |
292 | return sp; | |
293 | } | |
294 | ||
295 | pc = cris_rt_sigtramp_start (next_frame); | |
296 | if (pc) | |
297 | { | |
298 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains | |
299 | a struct ucontext, which in turn contains a struct sigcontext. | |
300 | Magic digging: | |
301 | 4 + 4 + 128 to struct ucontext, then | |
302 | 4 + 4 + 12 to struct sigcontext. */ | |
303 | return (sp + 156); | |
304 | } | |
305 | ||
8a3fe4f8 | 306 | error (_("Couldn't recognize signal trampoline.")); |
a5f6c8f5 | 307 | return 0; |
29134980 OF |
308 | } |
309 | ||
2e4b5889 | 310 | struct cris_unwind_cache |
29134980 | 311 | { |
2e4b5889 OF |
312 | /* The previous frame's inner most stack address. Used as this |
313 | frame ID's stack_addr. */ | |
314 | CORE_ADDR prev_sp; | |
315 | /* The frame's base, optionally used by the high-level debug info. */ | |
316 | CORE_ADDR base; | |
317 | int size; | |
318 | /* How far the SP and r8 (FP) have been offset from the start of | |
319 | the stack frame (as defined by the previous frame's stack | |
320 | pointer). */ | |
321 | LONGEST sp_offset; | |
322 | LONGEST r8_offset; | |
323 | int uses_frame; | |
324 | ||
325 | /* From old frame_extra_info struct. */ | |
29134980 OF |
326 | CORE_ADDR return_pc; |
327 | int leaf_function; | |
2e4b5889 OF |
328 | |
329 | /* Table indicating the location of each and every register. */ | |
330 | struct trad_frame_saved_reg *saved_regs; | |
29134980 OF |
331 | }; |
332 | ||
a5f6c8f5 OF |
333 | static struct cris_unwind_cache * |
334 | cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame, | |
335 | void **this_cache) | |
336 | { | |
337 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
338 | struct cris_unwind_cache *info; | |
339 | CORE_ADDR pc; | |
340 | CORE_ADDR sp; | |
341 | CORE_ADDR addr; | |
342 | char buf[4]; | |
343 | int i; | |
344 | ||
345 | if ((*this_cache)) | |
346 | return (*this_cache); | |
347 | ||
348 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
349 | (*this_cache) = info; | |
350 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
351 | ||
352 | /* Zero all fields. */ | |
353 | info->prev_sp = 0; | |
354 | info->base = 0; | |
355 | info->size = 0; | |
356 | info->sp_offset = 0; | |
357 | info->r8_offset = 0; | |
358 | info->uses_frame = 0; | |
359 | info->return_pc = 0; | |
360 | info->leaf_function = 0; | |
361 | ||
362 | frame_unwind_register (next_frame, SP_REGNUM, buf); | |
363 | info->base = extract_unsigned_integer (buf, 4); | |
364 | ||
365 | addr = cris_sigcontext_addr (next_frame); | |
366 | ||
367 | /* Layout of the sigcontext struct: | |
368 | struct sigcontext { | |
369 | struct pt_regs regs; | |
370 | unsigned long oldmask; | |
371 | unsigned long usp; | |
372 | }; */ | |
373 | ||
c600d464 OF |
374 | if (tdep->cris_version == 10) |
375 | { | |
376 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in | |
377 | struct pt_regs. */ | |
378 | for (i = 0; i <= 13; i++) | |
379 | info->saved_regs[i].addr = addr + ((15 - i) * 4); | |
380 | ||
381 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); | |
382 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); | |
383 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); | |
384 | /* Note: IRP is off by 2 at this point. There's no point in correcting | |
385 | it though since that will mean that the backtrace will show a PC | |
386 | different from what is shown when stopped. */ | |
387 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); | |
388 | info->saved_regs[PC_REGNUM] = info->saved_regs[IRP_REGNUM]; | |
389 | info->saved_regs[SP_REGNUM].addr = addr + (24 * 4); | |
390 | } | |
391 | else | |
392 | { | |
393 | /* CRISv32. */ | |
394 | /* R0 to R13 are stored in order at offset (1 * 4) in | |
395 | struct pt_regs. */ | |
396 | for (i = 0; i <= 13; i++) | |
397 | info->saved_regs[i].addr = addr + ((i + 1) * 4); | |
398 | ||
399 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); | |
400 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); | |
401 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); | |
402 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); | |
403 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); | |
404 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); | |
405 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); | |
406 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); | |
407 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); | |
408 | ||
409 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
410 | be wrong at this point. This problem manifests itself in the | |
411 | sigaltstack.exp test case, which occasionally generates FAILs when | |
412 | the signal is received while in a delay slot. | |
413 | ||
414 | This could be solved by a couple of read_memory_unsigned_integer and a | |
415 | trad_frame_set_value. */ | |
416 | info->saved_regs[PC_REGNUM] = info->saved_regs[ERP_REGNUM]; | |
417 | ||
418 | info->saved_regs[SP_REGNUM].addr = addr + (25 * 4); | |
419 | } | |
a5f6c8f5 OF |
420 | |
421 | return info; | |
422 | } | |
423 | ||
424 | static void | |
425 | cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
426 | struct frame_id *this_id) | |
427 | { | |
428 | struct cris_unwind_cache *cache = | |
429 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
430 | (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame)); | |
431 | } | |
432 | ||
433 | /* Forward declaration. */ | |
434 | ||
435 | static void cris_frame_prev_register (struct frame_info *next_frame, | |
436 | void **this_prologue_cache, | |
437 | int regnum, int *optimizedp, | |
438 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 439 | int *realnump, gdb_byte *bufferp); |
a5f6c8f5 OF |
440 | static void |
441 | cris_sigtramp_frame_prev_register (struct frame_info *next_frame, | |
442 | void **this_cache, | |
443 | int regnum, int *optimizedp, | |
444 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 445 | int *realnump, gdb_byte *valuep) |
a5f6c8f5 OF |
446 | { |
447 | /* Make sure we've initialized the cache. */ | |
448 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
449 | cris_frame_prev_register (next_frame, this_cache, regnum, | |
450 | optimizedp, lvalp, addrp, realnump, valuep); | |
451 | } | |
452 | ||
453 | static const struct frame_unwind cris_sigtramp_frame_unwind = | |
454 | { | |
455 | SIGTRAMP_FRAME, | |
456 | cris_sigtramp_frame_this_id, | |
457 | cris_sigtramp_frame_prev_register | |
458 | }; | |
459 | ||
460 | static const struct frame_unwind * | |
461 | cris_sigtramp_frame_sniffer (struct frame_info *next_frame) | |
462 | { | |
463 | if (cris_sigtramp_start (next_frame) | |
464 | || cris_rt_sigtramp_start (next_frame)) | |
465 | return &cris_sigtramp_frame_unwind; | |
466 | ||
467 | return NULL; | |
468 | } | |
469 | ||
c600d464 OF |
470 | int |
471 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, | |
472 | struct frame_info *this_frame) | |
473 | { | |
474 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
475 | ULONGEST erp; | |
476 | int ret = 0; | |
477 | char buf[4]; | |
478 | ||
0e6bdb31 OF |
479 | if (cris_mode () == cris_mode_guru) |
480 | { | |
481 | frame_unwind_register (this_frame, NRP_REGNUM, buf); | |
482 | } | |
483 | else | |
484 | { | |
485 | frame_unwind_register (this_frame, ERP_REGNUM, buf); | |
486 | } | |
487 | ||
c600d464 OF |
488 | erp = extract_unsigned_integer (buf, 4); |
489 | ||
490 | if (erp & 0x1) | |
491 | { | |
492 | /* In delay slot - check if there's a breakpoint at the preceding | |
493 | instruction. */ | |
494 | if (breakpoint_here_p (erp & ~0x1)) | |
495 | ret = 1; | |
496 | } | |
497 | return ret; | |
498 | } | |
499 | ||
500 | /* Hardware watchpoint support. */ | |
501 | ||
502 | /* We support 6 hardware data watchpoints, but cannot trigger on execute | |
503 | (any combination of read/write is fine). */ | |
504 | ||
505 | int | |
506 | cris_can_use_hardware_watchpoint (int type, int count, int other) | |
507 | { | |
508 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
509 | ||
510 | /* No bookkeeping is done here; it is handled by the remote debug agent. */ | |
511 | ||
512 | if (tdep->cris_version != 32) | |
513 | return 0; | |
514 | else | |
515 | /* CRISv32: Six data watchpoints, one for instructions. */ | |
516 | return (((type == bp_read_watchpoint || type == bp_access_watchpoint | |
517 | || type == bp_hardware_watchpoint) && count <= 6) | |
518 | || (type == bp_hardware_breakpoint && count <= 1)); | |
519 | } | |
520 | ||
521 | /* The CRISv32 hardware data watchpoints work by specifying ranges, | |
522 | which have no alignment or length restrictions. */ | |
523 | ||
524 | int | |
525 | cris_region_ok_for_watchpoint (CORE_ADDR addr, int len) | |
526 | { | |
527 | return 1; | |
528 | } | |
529 | ||
530 | /* If the inferior has some watchpoint that triggered, return the | |
531 | address associated with that watchpoint. Otherwise, return | |
532 | zero. */ | |
533 | ||
534 | CORE_ADDR | |
535 | cris_stopped_data_address (void) | |
536 | { | |
537 | CORE_ADDR eda; | |
1b5a9a8f | 538 | eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM); |
c600d464 OF |
539 | return eda; |
540 | } | |
541 | ||
29134980 | 542 | /* The instruction environment needed to find single-step breakpoints. */ |
c600d464 | 543 | |
29134980 OF |
544 | typedef |
545 | struct instruction_environment | |
546 | { | |
547 | unsigned long reg[NUM_GENREGS]; | |
548 | unsigned long preg[NUM_SPECREGS]; | |
549 | unsigned long branch_break_address; | |
550 | unsigned long delay_slot_pc; | |
551 | unsigned long prefix_value; | |
552 | int branch_found; | |
553 | int prefix_found; | |
554 | int invalid; | |
555 | int slot_needed; | |
556 | int delay_slot_pc_active; | |
557 | int xflag_found; | |
558 | int disable_interrupt; | |
559 | } inst_env_type; | |
560 | ||
29134980 OF |
561 | /* Machine-dependencies in CRIS for opcodes. */ |
562 | ||
563 | /* Instruction sizes. */ | |
564 | enum cris_instruction_sizes | |
565 | { | |
566 | INST_BYTE_SIZE = 0, | |
567 | INST_WORD_SIZE = 1, | |
568 | INST_DWORD_SIZE = 2 | |
569 | }; | |
570 | ||
571 | /* Addressing modes. */ | |
572 | enum cris_addressing_modes | |
573 | { | |
574 | REGISTER_MODE = 1, | |
575 | INDIRECT_MODE = 2, | |
576 | AUTOINC_MODE = 3 | |
577 | }; | |
578 | ||
579 | /* Prefix addressing modes. */ | |
580 | enum cris_prefix_addressing_modes | |
581 | { | |
582 | PREFIX_INDEX_MODE = 2, | |
583 | PREFIX_ASSIGN_MODE = 3, | |
584 | ||
585 | /* Handle immediate byte offset addressing mode prefix format. */ | |
586 | PREFIX_OFFSET_MODE = 2 | |
587 | }; | |
588 | ||
589 | /* Masks for opcodes. */ | |
590 | enum cris_opcode_masks | |
591 | { | |
592 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
593 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
594 | SIGNED_BYTE_MASK = 0x80, | |
595 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
596 | SIGNED_WORD_MASK = 0x8000, | |
597 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
598 | SIGNED_DWORD_MASK = 0x80000000, | |
599 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
600 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
601 | }; | |
602 | ||
603 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
604 | Bit 15 - 12 Operand2 | |
605 | 11 - 10 Mode | |
606 | 9 - 6 Opcode | |
607 | 5 - 4 Size | |
608 | 3 - 0 Operand1 */ | |
609 | ||
610 | static int | |
611 | cris_get_operand2 (unsigned short insn) | |
612 | { | |
613 | return ((insn & 0xF000) >> 12); | |
614 | } | |
615 | ||
616 | static int | |
617 | cris_get_mode (unsigned short insn) | |
618 | { | |
619 | return ((insn & 0x0C00) >> 10); | |
620 | } | |
621 | ||
622 | static int | |
623 | cris_get_opcode (unsigned short insn) | |
624 | { | |
625 | return ((insn & 0x03C0) >> 6); | |
626 | } | |
627 | ||
628 | static int | |
629 | cris_get_size (unsigned short insn) | |
630 | { | |
631 | return ((insn & 0x0030) >> 4); | |
632 | } | |
633 | ||
634 | static int | |
635 | cris_get_operand1 (unsigned short insn) | |
636 | { | |
637 | return (insn & 0x000F); | |
638 | } | |
639 | ||
640 | /* Additional functions in order to handle opcodes. */ | |
641 | ||
29134980 OF |
642 | static int |
643 | cris_get_quick_value (unsigned short insn) | |
644 | { | |
645 | return (insn & 0x003F); | |
646 | } | |
647 | ||
648 | static int | |
649 | cris_get_bdap_quick_offset (unsigned short insn) | |
650 | { | |
651 | return (insn & 0x00FF); | |
652 | } | |
653 | ||
654 | static int | |
655 | cris_get_branch_short_offset (unsigned short insn) | |
656 | { | |
657 | return (insn & 0x00FF); | |
658 | } | |
659 | ||
660 | static int | |
661 | cris_get_asr_shift_steps (unsigned long value) | |
662 | { | |
663 | return (value & 0x3F); | |
664 | } | |
665 | ||
29134980 OF |
666 | static int |
667 | cris_get_clear_size (unsigned short insn) | |
668 | { | |
669 | return ((insn) & 0xC000); | |
670 | } | |
671 | ||
672 | static int | |
673 | cris_is_signed_extend_bit_on (unsigned short insn) | |
674 | { | |
675 | return (((insn) & 0x20) == 0x20); | |
676 | } | |
677 | ||
678 | static int | |
679 | cris_is_xflag_bit_on (unsigned short insn) | |
680 | { | |
681 | return (((insn) & 0x1000) == 0x1000); | |
682 | } | |
683 | ||
684 | static void | |
685 | cris_set_size_to_dword (unsigned short *insn) | |
686 | { | |
687 | *insn &= 0xFFCF; | |
688 | *insn |= 0x20; | |
689 | } | |
690 | ||
8535cb38 | 691 | static signed char |
29134980 OF |
692 | cris_get_signed_offset (unsigned short insn) |
693 | { | |
8535cb38 | 694 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
695 | } |
696 | ||
697 | /* Calls an op function given the op-type, working on the insn and the | |
698 | inst_env. */ | |
699 | static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); | |
700 | ||
29134980 OF |
701 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
702 | struct gdbarch_list *); | |
703 | ||
29134980 OF |
704 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
705 | ||
a5f6c8f5 OF |
706 | static void set_cris_version (char *ignore_args, int from_tty, |
707 | struct cmd_list_element *c); | |
29134980 | 708 | |
0e6bdb31 OF |
709 | static void set_cris_mode (char *ignore_args, int from_tty, |
710 | struct cmd_list_element *c); | |
711 | ||
a5f6c8f5 OF |
712 | static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
713 | struct cmd_list_element *c); | |
29134980 | 714 | |
2e4b5889 OF |
715 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
716 | struct frame_info *next_frame, | |
717 | struct cris_unwind_cache *info); | |
718 | ||
5114e29d OF |
719 | static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc, |
720 | struct frame_info *next_frame, | |
721 | struct cris_unwind_cache *info); | |
722 | ||
2e4b5889 OF |
723 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, |
724 | struct frame_info *next_frame); | |
725 | ||
726 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, | |
727 | struct frame_info *next_frame); | |
728 | ||
729 | /* When arguments must be pushed onto the stack, they go on in reverse | |
a5f6c8f5 OF |
730 | order. The below implements a FILO (stack) to do this. |
731 | Copied from d10v-tdep.c. */ | |
2e4b5889 OF |
732 | |
733 | struct stack_item | |
734 | { | |
735 | int len; | |
736 | struct stack_item *prev; | |
737 | void *data; | |
738 | }; | |
739 | ||
740 | static struct stack_item * | |
741 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
742 | { | |
743 | struct stack_item *si; | |
744 | si = xmalloc (sizeof (struct stack_item)); | |
745 | si->data = xmalloc (len); | |
746 | si->len = len; | |
747 | si->prev = prev; | |
748 | memcpy (si->data, contents, len); | |
749 | return si; | |
750 | } | |
751 | ||
752 | static struct stack_item * | |
753 | pop_stack_item (struct stack_item *si) | |
754 | { | |
755 | struct stack_item *dead = si; | |
756 | si = si->prev; | |
757 | xfree (dead->data); | |
758 | xfree (dead); | |
759 | return si; | |
760 | } | |
761 | ||
762 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
763 | the saved registers of frame described by FRAME_INFO. This | |
764 | includes special registers such as pc and fp saved in special ways | |
765 | in the stack frame. sp is even more special: the address we return | |
a5f6c8f5 | 766 | for it IS the sp for the next frame. */ |
2e4b5889 OF |
767 | |
768 | struct cris_unwind_cache * | |
769 | cris_frame_unwind_cache (struct frame_info *next_frame, | |
770 | void **this_prologue_cache) | |
771 | { | |
772 | CORE_ADDR pc; | |
773 | struct cris_unwind_cache *info; | |
774 | int i; | |
775 | ||
776 | if ((*this_prologue_cache)) | |
777 | return (*this_prologue_cache); | |
778 | ||
779 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
780 | (*this_prologue_cache) = info; | |
781 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
782 | ||
783 | /* Zero all fields. */ | |
784 | info->prev_sp = 0; | |
785 | info->base = 0; | |
786 | info->size = 0; | |
787 | info->sp_offset = 0; | |
788 | info->r8_offset = 0; | |
789 | info->uses_frame = 0; | |
790 | info->return_pc = 0; | |
791 | info->leaf_function = 0; | |
792 | ||
793 | /* Prologue analysis does the rest... */ | |
5114e29d | 794 | if (cris_version () == 32) |
93d42b30 DJ |
795 | crisv32_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME), |
796 | next_frame, info); | |
5114e29d | 797 | else |
93d42b30 DJ |
798 | cris_scan_prologue (frame_func_unwind (next_frame, NORMAL_FRAME), |
799 | next_frame, info); | |
2e4b5889 OF |
800 | |
801 | return info; | |
802 | } | |
803 | ||
804 | /* Given a GDB frame, determine the address of the calling function's | |
805 | frame. This will be used to create a new GDB frame struct. */ | |
806 | ||
807 | static void | |
808 | cris_frame_this_id (struct frame_info *next_frame, | |
809 | void **this_prologue_cache, | |
810 | struct frame_id *this_id) | |
811 | { | |
812 | struct cris_unwind_cache *info | |
813 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
814 | CORE_ADDR base; | |
815 | CORE_ADDR func; | |
816 | struct frame_id id; | |
817 | ||
818 | /* The FUNC is easy. */ | |
93d42b30 | 819 | func = frame_func_unwind (next_frame, NORMAL_FRAME); |
2e4b5889 OF |
820 | |
821 | /* Hopefully the prologue analysis either correctly determined the | |
822 | frame's base (which is the SP from the previous frame), or set | |
823 | that base to "NULL". */ | |
824 | base = info->prev_sp; | |
825 | if (base == 0) | |
826 | return; | |
827 | ||
828 | id = frame_id_build (base, func); | |
829 | ||
830 | (*this_id) = id; | |
831 | } | |
832 | ||
833 | static void | |
834 | cris_frame_prev_register (struct frame_info *next_frame, | |
835 | void **this_prologue_cache, | |
836 | int regnum, int *optimizedp, | |
837 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 838 | int *realnump, gdb_byte *bufferp) |
2e4b5889 OF |
839 | { |
840 | struct cris_unwind_cache *info | |
841 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
1f67027d AC |
842 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
843 | optimizedp, lvalp, addrp, realnump, bufferp); | |
2e4b5889 OF |
844 | } |
845 | ||
846 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
847 | dummy frame. The frame ID's base needs to match the TOS value | |
848 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
849 | breakpoint. */ | |
850 | ||
851 | static struct frame_id | |
852 | cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
853 | { | |
854 | return frame_id_build (cris_unwind_sp (gdbarch, next_frame), | |
855 | frame_pc_unwind (next_frame)); | |
856 | } | |
857 | ||
858 | static CORE_ADDR | |
859 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
860 | { | |
861 | /* Align to the size of an instruction (so that they can safely be | |
862 | pushed onto the stack). */ | |
863 | return sp & ~3; | |
864 | } | |
865 | ||
866 | static CORE_ADDR | |
867 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
868 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
869 | struct value **args, int nargs, | |
870 | struct type *value_type, | |
e4fd649a UW |
871 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
872 | struct regcache *regcache) | |
2e4b5889 OF |
873 | { |
874 | /* Allocate space sufficient for a breakpoint. */ | |
875 | sp = (sp - 4) & ~3; | |
876 | /* Store the address of that breakpoint */ | |
877 | *bp_addr = sp; | |
878 | /* CRIS always starts the call at the callee's entry point. */ | |
879 | *real_pc = funaddr; | |
880 | return sp; | |
881 | } | |
882 | ||
883 | static CORE_ADDR | |
7d9b040b | 884 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2e4b5889 OF |
885 | struct regcache *regcache, CORE_ADDR bp_addr, |
886 | int nargs, struct value **args, CORE_ADDR sp, | |
887 | int struct_return, CORE_ADDR struct_addr) | |
888 | { | |
889 | int stack_alloc; | |
890 | int stack_offset; | |
891 | int argreg; | |
892 | int argnum; | |
893 | ||
894 | CORE_ADDR regval; | |
895 | ||
896 | /* The function's arguments and memory allocated by gdb for the arguments to | |
897 | point at reside in separate areas on the stack. | |
898 | Both frame pointers grow toward higher addresses. */ | |
899 | CORE_ADDR fp_arg; | |
900 | CORE_ADDR fp_mem; | |
901 | ||
902 | struct stack_item *si = NULL; | |
903 | ||
a5f6c8f5 | 904 | /* Push the return address. */ |
2e4b5889 OF |
905 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
906 | ||
907 | /* Are we returning a value using a structure return or a normal value | |
908 | return? struct_addr is the address of the reserved space for the return | |
909 | structure to be written on the stack. */ | |
910 | if (struct_return) | |
911 | { | |
912 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
913 | } | |
914 | ||
915 | /* Now load as many as possible of the first arguments into registers, | |
916 | and push the rest onto the stack. */ | |
917 | argreg = ARG1_REGNUM; | |
918 | stack_offset = 0; | |
919 | ||
920 | for (argnum = 0; argnum < nargs; argnum++) | |
921 | { | |
922 | int len; | |
923 | char *val; | |
924 | int reg_demand; | |
925 | int i; | |
926 | ||
4991999e | 927 | len = TYPE_LENGTH (value_type (args[argnum])); |
0fd88904 | 928 | val = (char *) value_contents (args[argnum]); |
2e4b5889 OF |
929 | |
930 | /* How may registers worth of storage do we need for this argument? */ | |
931 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
932 | ||
933 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
934 | { | |
935 | /* Data passed by value. Fits in available register(s). */ | |
936 | for (i = 0; i < reg_demand; i++) | |
937 | { | |
938 | regcache_cooked_write_unsigned (regcache, argreg, | |
939 | *(unsigned long *) val); | |
940 | argreg++; | |
941 | val += 4; | |
942 | } | |
943 | } | |
944 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) | |
945 | { | |
946 | /* Data passed by value. Does not fit in available register(s). | |
947 | Use the register(s) first, then the stack. */ | |
948 | for (i = 0; i < reg_demand; i++) | |
949 | { | |
950 | if (argreg <= ARG4_REGNUM) | |
951 | { | |
952 | regcache_cooked_write_unsigned (regcache, argreg, | |
953 | *(unsigned long *) val); | |
954 | argreg++; | |
955 | val += 4; | |
956 | } | |
957 | else | |
958 | { | |
959 | /* Push item for later so that pushed arguments | |
960 | come in the right order. */ | |
961 | si = push_stack_item (si, val, 4); | |
962 | val += 4; | |
963 | } | |
964 | } | |
965 | } | |
966 | else if (len > (2 * 4)) | |
967 | { | |
968 | /* FIXME */ | |
e2e0b3e5 | 969 | internal_error (__FILE__, __LINE__, _("We don't do this")); |
2e4b5889 OF |
970 | } |
971 | else | |
972 | { | |
973 | /* Data passed by value. No available registers. Put it on | |
974 | the stack. */ | |
975 | si = push_stack_item (si, val, len); | |
976 | } | |
977 | } | |
978 | ||
979 | while (si) | |
980 | { | |
981 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
982 | the function prologue. */ | |
983 | sp = (sp - si->len) & ~3; | |
984 | write_memory (sp, si->data, si->len); | |
985 | si = pop_stack_item (si); | |
986 | } | |
987 | ||
988 | /* Finally, update the SP register. */ | |
989 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
990 | ||
991 | return sp; | |
992 | } | |
993 | ||
e2a2a3e8 OF |
994 | static const struct frame_unwind cris_frame_unwind = |
995 | { | |
2e4b5889 OF |
996 | NORMAL_FRAME, |
997 | cris_frame_this_id, | |
998 | cris_frame_prev_register | |
999 | }; | |
1000 | ||
1001 | const struct frame_unwind * | |
1002 | cris_frame_sniffer (struct frame_info *next_frame) | |
1003 | { | |
1004 | return &cris_frame_unwind; | |
1005 | } | |
1006 | ||
1007 | static CORE_ADDR | |
1008 | cris_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1009 | { | |
1010 | struct cris_unwind_cache *info | |
1011 | = cris_frame_unwind_cache (next_frame, this_cache); | |
1012 | return info->base; | |
1013 | } | |
1014 | ||
e2a2a3e8 OF |
1015 | static const struct frame_base cris_frame_base = |
1016 | { | |
2e4b5889 OF |
1017 | &cris_frame_unwind, |
1018 | cris_frame_base_address, | |
1019 | cris_frame_base_address, | |
1020 | cris_frame_base_address | |
1021 | }; | |
1022 | ||
29134980 OF |
1023 | /* Frames information. The definition of the struct frame_info is |
1024 | ||
1025 | CORE_ADDR frame | |
1026 | CORE_ADDR pc | |
5a203e44 | 1027 | enum frame_type type; |
29134980 OF |
1028 | CORE_ADDR return_pc |
1029 | int leaf_function | |
1030 | ||
1031 | If the compilation option -fno-omit-frame-pointer is present the | |
1032 | variable frame will be set to the content of R8 which is the frame | |
1033 | pointer register. | |
1034 | ||
1035 | The variable pc contains the address where execution is performed | |
1036 | in the present frame. The innermost frame contains the current content | |
1037 | of the register PC. All other frames contain the content of the | |
1038 | register PC in the next frame. | |
1039 | ||
5a203e44 AC |
1040 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
1041 | (associated with a signal handler), dummy (associated with a dummy | |
1042 | frame). | |
29134980 OF |
1043 | |
1044 | The variable return_pc contains the address where execution should be | |
1045 | resumed when the present frame has finished, the return address. | |
1046 | ||
1047 | The variable leaf_function is 1 if the return address is in the register | |
1048 | SRP, and 0 if it is on the stack. | |
1049 | ||
1050 | Prologue instructions C-code. | |
1051 | The prologue may consist of (-fno-omit-frame-pointer) | |
1052 | 1) 2) | |
1053 | push srp | |
1054 | push r8 push r8 | |
1055 | move.d sp,r8 move.d sp,r8 | |
1056 | subq X,sp subq X,sp | |
1057 | movem rY,[sp] movem rY,[sp] | |
1058 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
1059 | ||
1060 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
1061 | ||
1062 | Note that this assumption is extremely brittle, and will break at the | |
1063 | slightest change in GCC's prologue. | |
1064 | ||
1065 | If local variables are declared or register contents are saved on stack | |
1066 | the subq-instruction will be present with X as the number of bytes | |
1067 | needed for storage. The reshuffle with respect to r8 may be performed | |
1068 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
1069 | The offset U should be representable by a signed 8-bit value in all cases. | |
1070 | Thus, the prefix word is assumed to be immediate byte offset mode followed | |
1071 | by another word containing the instruction. | |
1072 | ||
1073 | Degenerate cases: | |
1074 | 3) | |
1075 | push r8 | |
1076 | move.d sp,r8 | |
1077 | move.d r8,sp | |
1078 | pop r8 | |
1079 | ||
1080 | Prologue instructions C++-code. | |
1081 | Case 1) and 2) in the C-code may be followed by | |
1082 | ||
1083 | move.d r10,rS ; this | |
1084 | move.d r11,rT ; P1 | |
1085 | move.d r12,rU ; P2 | |
1086 | move.d r13,rV ; P3 | |
1087 | move.S [r8+U],rZ ; P4 | |
1088 | ||
1089 | if any of the call parameters are stored. The host expects these | |
1090 | instructions to be executed in order to get the call parameters right. */ | |
1091 | ||
1092 | /* Examine the prologue of a function. The variable ip is the address of | |
1093 | the first instruction of the prologue. The variable limit is the address | |
1094 | of the first instruction after the prologue. The variable fi contains the | |
1095 | information in struct frame_info. The variable frameless_p controls whether | |
1096 | the entire prologue is examined (0) or just enough instructions to | |
1097 | determine that it is a prologue (1). */ | |
1098 | ||
a78f21af | 1099 | static CORE_ADDR |
2e4b5889 OF |
1100 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
1101 | struct cris_unwind_cache *info) | |
29134980 OF |
1102 | { |
1103 | /* Present instruction. */ | |
1104 | unsigned short insn; | |
1105 | ||
1106 | /* Next instruction, lookahead. */ | |
1107 | unsigned short insn_next; | |
1108 | int regno; | |
1109 | ||
1110 | /* Is there a push fp? */ | |
1111 | int have_fp; | |
1112 | ||
1113 | /* Number of byte on stack used for local variables and movem. */ | |
1114 | int val; | |
1115 | ||
1116 | /* Highest register number in a movem. */ | |
1117 | int regsave; | |
1118 | ||
1119 | /* move.d r<source_register>,rS */ | |
1120 | short source_register; | |
1121 | ||
2e4b5889 OF |
1122 | /* Scan limit. */ |
1123 | int limit; | |
29134980 | 1124 | |
2e4b5889 OF |
1125 | /* This frame is with respect to a leaf until a push srp is found. */ |
1126 | if (info) | |
1127 | { | |
1128 | info->leaf_function = 1; | |
1129 | } | |
29134980 OF |
1130 | |
1131 | /* Assume nothing on stack. */ | |
1132 | val = 0; | |
1133 | regsave = -1; | |
1134 | ||
2e4b5889 OF |
1135 | /* If we were called without a next_frame, that means we were called |
1136 | from cris_skip_prologue which already tried to find the end of the | |
1137 | prologue through the symbol information. 64 instructions past current | |
1138 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
1139 | limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64; | |
29134980 | 1140 | |
29134980 | 1141 | /* Find the prologue instructions. */ |
a5f6c8f5 | 1142 | while (pc > 0 && pc < limit) |
29134980 | 1143 | { |
2e4b5889 OF |
1144 | insn = read_memory_unsigned_integer (pc, 2); |
1145 | pc += 2; | |
29134980 OF |
1146 | if (insn == 0xE1FC) |
1147 | { | |
1148 | /* push <reg> 32 bit instruction */ | |
2e4b5889 OF |
1149 | insn_next = read_memory_unsigned_integer (pc, 2); |
1150 | pc += 2; | |
29134980 | 1151 | regno = cris_get_operand2 (insn_next); |
2e4b5889 OF |
1152 | if (info) |
1153 | { | |
1154 | info->sp_offset += 4; | |
1155 | } | |
dbbff683 OF |
1156 | /* This check, meant to recognize srp, used to be regno == |
1157 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
1158 | if (insn_next == 0xBE7E) | |
29134980 | 1159 | { |
2e4b5889 OF |
1160 | if (info) |
1161 | { | |
1162 | info->leaf_function = 0; | |
1163 | } | |
29134980 | 1164 | } |
b4206d25 OF |
1165 | else if (insn_next == 0x8FEE) |
1166 | { | |
1167 | /* push $r8 */ | |
1168 | if (info) | |
1169 | { | |
1170 | info->r8_offset = info->sp_offset; | |
1171 | } | |
1172 | } | |
29134980 OF |
1173 | } |
1174 | else if (insn == 0x866E) | |
1175 | { | |
1176 | /* move.d sp,r8 */ | |
2e4b5889 OF |
1177 | if (info) |
1178 | { | |
1179 | info->uses_frame = 1; | |
2e4b5889 | 1180 | } |
29134980 OF |
1181 | continue; |
1182 | } | |
1183 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
1184 | && cris_get_mode (insn) == 0x0000 | |
1185 | && cris_get_opcode (insn) == 0x000A) | |
1186 | { | |
1187 | /* subq <val>,sp */ | |
2e4b5889 OF |
1188 | if (info) |
1189 | { | |
1190 | info->sp_offset += cris_get_quick_value (insn); | |
1191 | } | |
29134980 OF |
1192 | } |
1193 | else if (cris_get_mode (insn) == 0x0002 | |
1194 | && cris_get_opcode (insn) == 0x000F | |
1195 | && cris_get_size (insn) == 0x0003 | |
1196 | && cris_get_operand1 (insn) == SP_REGNUM) | |
1197 | { | |
1198 | /* movem r<regsave>,[sp] */ | |
29134980 OF |
1199 | regsave = cris_get_operand2 (insn); |
1200 | } | |
1201 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
1202 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1203 | && (cris_get_signed_offset (insn) < 0)) | |
1204 | { | |
1205 | /* Immediate byte offset addressing prefix word with sp as base | |
1206 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
1207 | is between 64 and 128. | |
1208 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
1209 | if (info) |
1210 | { | |
1211 | info->sp_offset += -cris_get_signed_offset (insn); | |
1212 | } | |
1213 | insn_next = read_memory_unsigned_integer (pc, 2); | |
1214 | pc += 2; | |
29134980 OF |
1215 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
1216 | && cris_get_opcode (insn_next) == 0x000F | |
1217 | && cris_get_size (insn_next) == 0x0003 | |
1218 | && cris_get_operand1 (insn_next) == SP_REGNUM) | |
1219 | { | |
29134980 OF |
1220 | regsave = cris_get_operand2 (insn_next); |
1221 | } | |
1222 | else | |
1223 | { | |
1224 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1225 | pc -= 4; |
29134980 OF |
1226 | break; |
1227 | } | |
1228 | } | |
1229 | else if (cris_get_mode (insn) == 0x0001 | |
1230 | && cris_get_opcode (insn) == 0x0009 | |
1231 | && cris_get_size (insn) == 0x0002) | |
1232 | { | |
1233 | /* move.d r<10..13>,r<0..15> */ | |
29134980 | 1234 | source_register = cris_get_operand1 (insn); |
2a9ecef2 OF |
1235 | |
1236 | /* FIXME? In the glibc solibs, the prologue might contain something | |
1237 | like (this example taken from relocate_doit): | |
1238 | move.d $pc,$r0 | |
1239 | sub.d 0xfffef426,$r0 | |
1240 | which isn't covered by the source_register check below. Question | |
1241 | is whether to add a check for this combo, or make better use of | |
1242 | the limit variable instead. */ | |
29134980 OF |
1243 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
1244 | { | |
1245 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1246 | pc -= 2; |
29134980 OF |
1247 | break; |
1248 | } | |
1249 | } | |
2e4b5889 | 1250 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1251 | /* The size is a fixed-size. */ |
1252 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1253 | /* A negative offset. */ | |
1254 | && (cris_get_signed_offset (insn) < 0)) | |
1255 | { | |
1256 | /* move.S rZ,[r8-U] (?) */ | |
2e4b5889 OF |
1257 | insn_next = read_memory_unsigned_integer (pc, 2); |
1258 | pc += 2; | |
29134980 OF |
1259 | regno = cris_get_operand2 (insn_next); |
1260 | if ((regno >= 0 && regno < SP_REGNUM) | |
1261 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1262 | && cris_get_opcode (insn_next) == 0x000F) | |
1263 | { | |
1264 | /* move.S rZ,[r8-U] */ | |
1265 | continue; | |
1266 | } | |
1267 | else | |
1268 | { | |
1269 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1270 | pc -= 4; |
29134980 OF |
1271 | break; |
1272 | } | |
1273 | } | |
2e4b5889 | 1274 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1275 | /* The size is a fixed-size. */ |
1276 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1277 | /* A positive offset. */ | |
1278 | && (cris_get_signed_offset (insn) > 0)) | |
1279 | { | |
1280 | /* move.S [r8+U],rZ (?) */ | |
2e4b5889 OF |
1281 | insn_next = read_memory_unsigned_integer (pc, 2); |
1282 | pc += 2; | |
29134980 OF |
1283 | regno = cris_get_operand2 (insn_next); |
1284 | if ((regno >= 0 && regno < SP_REGNUM) | |
1285 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1286 | && cris_get_opcode (insn_next) == 0x0009 | |
1287 | && cris_get_operand1 (insn_next) == regno) | |
1288 | { | |
1289 | /* move.S [r8+U],rZ */ | |
1290 | continue; | |
1291 | } | |
1292 | else | |
1293 | { | |
1294 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1295 | pc -= 4; |
29134980 OF |
1296 | break; |
1297 | } | |
1298 | } | |
1299 | else | |
1300 | { | |
1301 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1302 | pc -= 2; |
29134980 OF |
1303 | break; |
1304 | } | |
1305 | } | |
29134980 | 1306 | |
2e4b5889 OF |
1307 | /* We only want to know the end of the prologue when next_frame and info |
1308 | are NULL (called from cris_skip_prologue i.e.). */ | |
1309 | if (next_frame == NULL && info == NULL) | |
1310 | { | |
1311 | return pc; | |
1312 | } | |
29134980 | 1313 | |
2e4b5889 OF |
1314 | info->size = info->sp_offset; |
1315 | ||
1316 | /* Compute the previous frame's stack pointer (which is also the | |
1317 | frame's ID's stack address), and this frame's base pointer. */ | |
1318 | if (info->uses_frame) | |
29134980 | 1319 | { |
2e4b5889 OF |
1320 | ULONGEST this_base; |
1321 | /* The SP was moved to the FP. This indicates that a new frame | |
1322 | was created. Get THIS frame's FP value by unwinding it from | |
1323 | the next frame. */ | |
1324 | frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM, | |
1325 | &this_base); | |
1326 | info->base = this_base; | |
b4206d25 OF |
1327 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
1328 | ||
2e4b5889 OF |
1329 | /* The FP points at the last saved register. Adjust the FP back |
1330 | to before the first saved register giving the SP. */ | |
1331 | info->prev_sp = info->base + info->r8_offset; | |
1332 | } | |
1333 | else | |
1334 | { | |
1335 | ULONGEST this_base; | |
1336 | /* Assume that the FP is this frame's SP but with that pushed | |
1337 | stack space added back. */ | |
1338 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); | |
1339 | info->base = this_base; | |
1340 | info->prev_sp = info->base + info->size; | |
1341 | } | |
29134980 | 1342 | |
2e4b5889 OF |
1343 | /* Calculate the addresses for the saved registers on the stack. */ |
1344 | /* FIXME: The address calculation should really be done on the fly while | |
1345 | we're analyzing the prologue (we only hold one regsave value as it is | |
1346 | now). */ | |
1347 | val = info->sp_offset; | |
1348 | ||
1349 | for (regno = regsave; regno >= 0; regno--) | |
1350 | { | |
1351 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; | |
1352 | val -= 4; | |
1353 | } | |
1354 | ||
1355 | /* The previous frame's SP needed to be computed. Save the computed | |
1356 | value. */ | |
1357 | trad_frame_set_value (info->saved_regs, SP_REGNUM, info->prev_sp); | |
1358 | ||
1359 | if (!info->leaf_function) | |
1360 | { | |
b4206d25 OF |
1361 | /* SRP saved on the stack. But where? */ |
1362 | if (info->r8_offset == 0) | |
1363 | { | |
1364 | /* R8 not pushed yet. */ | |
1365 | info->saved_regs[SRP_REGNUM].addr = info->base; | |
1366 | } | |
1367 | else | |
1368 | { | |
1369 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
1370 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; | |
1371 | } | |
29134980 | 1372 | } |
2e4b5889 OF |
1373 | |
1374 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
1375 | info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM]; | |
1376 | ||
1377 | return pc; | |
29134980 OF |
1378 | } |
1379 | ||
5114e29d OF |
1380 | static CORE_ADDR |
1381 | crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, | |
1382 | struct cris_unwind_cache *info) | |
1383 | { | |
1384 | ULONGEST this_base; | |
1385 | ||
1386 | /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not | |
1387 | meant to be a full-fledged prologue scanner. It is only needed for | |
1388 | the cases where we end up in code always lacking DWARF-2 CFI, notably: | |
1389 | ||
1390 | * PLT stubs (library calls) | |
1391 | * call dummys | |
1392 | * signal trampolines | |
1393 | ||
1394 | For those cases, it is assumed that there is no actual prologue; that | |
1395 | the stack pointer is not adjusted, and (as a consequence) the return | |
1396 | address is not pushed onto the stack. */ | |
1397 | ||
1398 | /* We only want to know the end of the prologue when next_frame and info | |
1399 | are NULL (called from cris_skip_prologue i.e.). */ | |
1400 | if (next_frame == NULL && info == NULL) | |
1401 | { | |
1402 | return pc; | |
1403 | } | |
1404 | ||
1405 | /* The SP is assumed to be unaltered. */ | |
1406 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); | |
1407 | info->base = this_base; | |
1408 | info->prev_sp = this_base; | |
1409 | ||
1410 | /* The PC is assumed to be found in SRP. */ | |
1411 | info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM]; | |
1412 | ||
1413 | return pc; | |
1414 | } | |
1415 | ||
29134980 OF |
1416 | /* Advance pc beyond any function entry prologue instructions at pc |
1417 | to reach some "real" code. */ | |
1418 | ||
29134980 OF |
1419 | /* Given a PC value corresponding to the start of a function, return the PC |
1420 | of the first instruction after the function prologue. */ | |
1421 | ||
a78f21af | 1422 | static CORE_ADDR |
2e4b5889 | 1423 | cris_skip_prologue (CORE_ADDR pc) |
29134980 | 1424 | { |
2e4b5889 OF |
1425 | CORE_ADDR func_addr, func_end; |
1426 | struct symtab_and_line sal; | |
29134980 OF |
1427 | CORE_ADDR pc_after_prologue; |
1428 | ||
2e4b5889 OF |
1429 | /* If we have line debugging information, then the end of the prologue |
1430 | should the first assembly instruction of the first source line. */ | |
1431 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1432 | { | |
1433 | sal = find_pc_line (func_addr, 0); | |
1434 | if (sal.end > 0 && sal.end < func_end) | |
1435 | return sal.end; | |
1436 | } | |
29134980 | 1437 | |
5114e29d OF |
1438 | if (cris_version () == 32) |
1439 | pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL); | |
1440 | else | |
1441 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); | |
1442 | ||
29134980 OF |
1443 | return pc_after_prologue; |
1444 | } | |
1445 | ||
2e4b5889 OF |
1446 | static CORE_ADDR |
1447 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1448 | { | |
1449 | ULONGEST pc; | |
1450 | frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc); | |
1451 | return pc; | |
1452 | } | |
1453 | ||
1454 | static CORE_ADDR | |
1455 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1456 | { | |
1457 | ULONGEST sp; | |
1458 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &sp); | |
1459 | return sp; | |
1460 | } | |
1461 | ||
29134980 OF |
1462 | /* Use the program counter to determine the contents and size of a breakpoint |
1463 | instruction. It returns a pointer to a string of bytes that encode a | |
1464 | breakpoint instruction, stores the length of the string to *lenptr, and | |
1465 | adjusts pcptr (if necessary) to point to the actual memory location where | |
1466 | the breakpoint should be inserted. */ | |
1467 | ||
a78f21af | 1468 | static const unsigned char * |
29134980 OF |
1469 | cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
1470 | { | |
0e6bdb31 OF |
1471 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
1472 | static unsigned char break15_insn[] = {0x3f, 0xe9}; | |
29134980 OF |
1473 | *lenptr = 2; |
1474 | ||
0e6bdb31 OF |
1475 | if (cris_mode () == cris_mode_guru) |
1476 | return break15_insn; | |
1477 | else | |
1478 | return break8_insn; | |
29134980 OF |
1479 | } |
1480 | ||
29134980 OF |
1481 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1482 | 0 otherwise. */ | |
1483 | ||
a78f21af | 1484 | static int |
29134980 OF |
1485 | cris_spec_reg_applicable (struct cris_spec_reg spec_reg) |
1486 | { | |
1487 | int version = cris_version (); | |
1488 | ||
1489 | switch (spec_reg.applicable_version) | |
1490 | { | |
1491 | case cris_ver_version_all: | |
1492 | return 1; | |
1493 | case cris_ver_warning: | |
1494 | /* Indeterminate/obsolete. */ | |
1495 | return 0; | |
29134980 OF |
1496 | case cris_ver_v0_3: |
1497 | return (version >= 0 && version <= 3); | |
1498 | case cris_ver_v3p: | |
1499 | return (version >= 3); | |
1500 | case cris_ver_v8: | |
1501 | return (version == 8 || version == 9); | |
1502 | case cris_ver_v8p: | |
1503 | return (version >= 8); | |
c600d464 OF |
1504 | case cris_ver_v0_10: |
1505 | return (version >= 0 && version <= 10); | |
1506 | case cris_ver_v3_10: | |
1507 | return (version >= 3 && version <= 10); | |
1508 | case cris_ver_v8_10: | |
1509 | return (version >= 8 && version <= 10); | |
1510 | case cris_ver_v10: | |
1511 | return (version == 10); | |
29134980 OF |
1512 | case cris_ver_v10p: |
1513 | return (version >= 10); | |
c600d464 OF |
1514 | case cris_ver_v32p: |
1515 | return (version >= 32); | |
29134980 OF |
1516 | default: |
1517 | /* Invalid cris version. */ | |
1518 | return 0; | |
1519 | } | |
1520 | } | |
1521 | ||
1d94326f AC |
1522 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
1523 | register, -1 for an invalid register. */ | |
1524 | ||
1525 | static int | |
1526 | cris_register_size (int regno) | |
1527 | { | |
c600d464 | 1528 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1d94326f AC |
1529 | int i; |
1530 | int spec_regno; | |
1531 | ||
1532 | if (regno >= 0 && regno < NUM_GENREGS) | |
1533 | { | |
1534 | /* General registers (R0 - R15) are 32 bits. */ | |
1535 | return 4; | |
1536 | } | |
c600d464 | 1537 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
1d94326f AC |
1538 | { |
1539 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1540 | Adjust regno accordingly. */ | |
1541 | spec_regno = regno - NUM_GENREGS; | |
1542 | ||
c600d464 | 1543 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
1d94326f AC |
1544 | { |
1545 | if (cris_spec_regs[i].number == spec_regno | |
1546 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1547 | /* Go with the first applicable register. */ | |
1548 | return cris_spec_regs[i].reg_size; | |
1549 | } | |
1550 | /* Special register not applicable to this CRIS version. */ | |
1551 | return 0; | |
1552 | } | |
f57d151a | 1553 | else if (regno >= PC_REGNUM && regno < gdbarch_num_regs (current_gdbarch)) |
1d94326f | 1554 | { |
c600d464 OF |
1555 | /* This will apply to CRISv32 only where there are additional registers |
1556 | after the special registers (pseudo PC and support registers). */ | |
1557 | return 4; | |
1d94326f | 1558 | } |
c600d464 OF |
1559 | |
1560 | ||
1561 | return -1; | |
1d94326f AC |
1562 | } |
1563 | ||
29134980 OF |
1564 | /* Nonzero if regno should not be fetched from the target. This is the case |
1565 | for unimplemented (size 0) and non-existant registers. */ | |
1566 | ||
a78f21af | 1567 | static int |
29134980 OF |
1568 | cris_cannot_fetch_register (int regno) |
1569 | { | |
f57d151a | 1570 | return ((regno < 0 || regno >= gdbarch_num_regs (current_gdbarch)) |
29134980 OF |
1571 | || (cris_register_size (regno) == 0)); |
1572 | } | |
1573 | ||
1574 | /* Nonzero if regno should not be written to the target, for various | |
1575 | reasons. */ | |
1576 | ||
a78f21af | 1577 | static int |
29134980 OF |
1578 | cris_cannot_store_register (int regno) |
1579 | { | |
1580 | /* There are three kinds of registers we refuse to write to. | |
1581 | 1. Those that not implemented. | |
1582 | 2. Those that are read-only (depends on the processor mode). | |
1583 | 3. Those registers to which a write has no effect. | |
1584 | */ | |
1585 | ||
f57d151a UW |
1586 | if (regno < 0 |
1587 | || regno >= gdbarch_num_regs (current_gdbarch) | |
1588 | || cris_register_size (regno) == 0) | |
29134980 OF |
1589 | /* Not implemented. */ |
1590 | return 1; | |
1591 | ||
1592 | else if (regno == VR_REGNUM) | |
1593 | /* Read-only. */ | |
1594 | return 1; | |
1595 | ||
1596 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1597 | /* Writing has no effect. */ | |
1598 | return 1; | |
1599 | ||
a5f6c8f5 OF |
1600 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
1601 | agent decide whether they are writable. */ | |
29134980 OF |
1602 | |
1603 | return 0; | |
1604 | } | |
1605 | ||
c600d464 OF |
1606 | /* Nonzero if regno should not be fetched from the target. This is the case |
1607 | for unimplemented (size 0) and non-existant registers. */ | |
1608 | ||
1609 | static int | |
1610 | crisv32_cannot_fetch_register (int regno) | |
1611 | { | |
f57d151a | 1612 | return ((regno < 0 || regno >= gdbarch_num_regs (current_gdbarch)) |
c600d464 OF |
1613 | || (cris_register_size (regno) == 0)); |
1614 | } | |
1615 | ||
1616 | /* Nonzero if regno should not be written to the target, for various | |
1617 | reasons. */ | |
1618 | ||
1619 | static int | |
1620 | crisv32_cannot_store_register (int regno) | |
1621 | { | |
1622 | /* There are three kinds of registers we refuse to write to. | |
1623 | 1. Those that not implemented. | |
1624 | 2. Those that are read-only (depends on the processor mode). | |
1625 | 3. Those registers to which a write has no effect. | |
1626 | */ | |
1627 | ||
f57d151a UW |
1628 | if (regno < 0 |
1629 | || regno >= gdbarch_num_regs (current_gdbarch) | |
1630 | || cris_register_size (regno) == 0) | |
c600d464 OF |
1631 | /* Not implemented. */ |
1632 | return 1; | |
1633 | ||
1634 | else if (regno == VR_REGNUM) | |
1635 | /* Read-only. */ | |
1636 | return 1; | |
1637 | ||
1638 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) | |
1639 | /* Writing has no effect. */ | |
1640 | return 1; | |
1641 | ||
1642 | /* Many special registers are read-only in user mode. Let the debug | |
1643 | agent decide whether they are writable. */ | |
1644 | ||
1645 | return 0; | |
1646 | } | |
1647 | ||
29134980 OF |
1648 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
1649 | of data in register regno. */ | |
1650 | ||
a78f21af | 1651 | static struct type * |
c1d546cd | 1652 | cris_register_type (struct gdbarch *gdbarch, int regno) |
29134980 | 1653 | { |
a5f6c8f5 OF |
1654 | if (regno == PC_REGNUM) |
1655 | return builtin_type_void_func_ptr; | |
1656 | else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) | |
1657 | return builtin_type_void_data_ptr; | |
1658 | else if ((regno >= 0 && regno < SP_REGNUM) | |
1659 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) | |
1660 | /* Note: R8 taken care of previous clause. */ | |
1661 | return builtin_type_uint32; | |
1662 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) | |
1663 | return builtin_type_uint16; | |
1664 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) | |
1665 | return builtin_type_uint8; | |
29134980 | 1666 | else |
a5f6c8f5 OF |
1667 | /* Invalid (unimplemented) register. */ |
1668 | return builtin_type_int0; | |
29134980 OF |
1669 | } |
1670 | ||
c600d464 OF |
1671 | static struct type * |
1672 | crisv32_register_type (struct gdbarch *gdbarch, int regno) | |
1673 | { | |
1674 | if (regno == PC_REGNUM) | |
1675 | return builtin_type_void_func_ptr; | |
1676 | else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) | |
1677 | return builtin_type_void_data_ptr; | |
1678 | else if ((regno >= 0 && regno <= ACR_REGNUM) | |
1679 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) | |
1680 | || (regno == PID_REGNUM) | |
1681 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) | |
1682 | /* Note: R8 and SP taken care of by previous clause. */ | |
1683 | return builtin_type_uint32; | |
1684 | else if (regno == WZ_REGNUM) | |
1685 | return builtin_type_uint16; | |
1686 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) | |
1687 | return builtin_type_uint8; | |
1688 | else | |
1689 | { | |
1690 | /* Invalid (unimplemented) register. Should not happen as there are | |
1691 | no unimplemented CRISv32 registers. */ | |
8a3fe4f8 | 1692 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
c600d464 OF |
1693 | return builtin_type_int0; |
1694 | } | |
1695 | } | |
1696 | ||
2e4b5889 OF |
1697 | /* Stores a function return value of type type, where valbuf is the address |
1698 | of the value to be stored. */ | |
29134980 | 1699 | |
2e4b5889 | 1700 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1701 | |
2e4b5889 OF |
1702 | static void |
1703 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
1704 | const void *valbuf) | |
29134980 | 1705 | { |
2e4b5889 OF |
1706 | ULONGEST val; |
1707 | int len = TYPE_LENGTH (type); | |
29134980 | 1708 | |
2e4b5889 | 1709 | if (len <= 4) |
29134980 | 1710 | { |
2e4b5889 OF |
1711 | /* Put the return value in R10. */ |
1712 | val = extract_unsigned_integer (valbuf, len); | |
1713 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
29134980 | 1714 | } |
2e4b5889 | 1715 | else if (len <= 8) |
29134980 | 1716 | { |
2e4b5889 OF |
1717 | /* Put the return value in R10 and R11. */ |
1718 | val = extract_unsigned_integer (valbuf, 4); | |
1719 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
1720 | val = extract_unsigned_integer ((char *)valbuf + 4, len - 4); | |
1721 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); | |
29134980 | 1722 | } |
2e4b5889 | 1723 | else |
8a3fe4f8 | 1724 | error (_("cris_store_return_value: type length too large.")); |
29134980 OF |
1725 | } |
1726 | ||
2e4b5889 OF |
1727 | /* Return the name of register regno as a string. Return NULL for an invalid or |
1728 | unimplemented register. */ | |
29134980 | 1729 | |
c600d464 OF |
1730 | static const char * |
1731 | cris_special_register_name (int regno) | |
1732 | { | |
1733 | int spec_regno; | |
1734 | int i; | |
1735 | ||
1736 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1737 | Adjust regno accordingly. */ | |
1738 | spec_regno = regno - NUM_GENREGS; | |
1739 | ||
1740 | /* Assume nothing about the layout of the cris_spec_regs struct | |
1741 | when searching. */ | |
1742 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1743 | { | |
1744 | if (cris_spec_regs[i].number == spec_regno | |
1745 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1746 | /* Go with the first applicable register. */ | |
1747 | return cris_spec_regs[i].name; | |
1748 | } | |
1749 | /* Special register not applicable to this CRIS version. */ | |
1750 | return NULL; | |
1751 | } | |
1752 | ||
2e4b5889 OF |
1753 | static const char * |
1754 | cris_register_name (int regno) | |
1755 | { | |
1756 | static char *cris_genreg_names[] = | |
1757 | { "r0", "r1", "r2", "r3", \ | |
1758 | "r4", "r5", "r6", "r7", \ | |
1759 | "r8", "r9", "r10", "r11", \ | |
1760 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1761 | |
2e4b5889 | 1762 | if (regno >= 0 && regno < NUM_GENREGS) |
29134980 | 1763 | { |
2e4b5889 OF |
1764 | /* General register. */ |
1765 | return cris_genreg_names[regno]; | |
29134980 | 1766 | } |
f57d151a | 1767 | else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (current_gdbarch)) |
29134980 | 1768 | { |
c600d464 OF |
1769 | return cris_special_register_name (regno); |
1770 | } | |
1771 | else | |
1772 | { | |
1773 | /* Invalid register. */ | |
2e4b5889 OF |
1774 | return NULL; |
1775 | } | |
c600d464 OF |
1776 | } |
1777 | ||
1778 | static const char * | |
1779 | crisv32_register_name (int regno) | |
1780 | { | |
1781 | static char *crisv32_genreg_names[] = | |
1782 | { "r0", "r1", "r2", "r3", \ | |
1783 | "r4", "r5", "r6", "r7", \ | |
1784 | "r8", "r9", "r10", "r11", \ | |
1785 | "r12", "r13", "sp", "acr" | |
1786 | }; | |
1787 | ||
1788 | static char *crisv32_sreg_names[] = | |
1789 | { "s0", "s1", "s2", "s3", \ | |
1790 | "s4", "s5", "s6", "s7", \ | |
1791 | "s8", "s9", "s10", "s11", \ | |
1792 | "s12", "s13", "s14", "s15" | |
1793 | }; | |
1794 | ||
1795 | if (regno >= 0 && regno < NUM_GENREGS) | |
1796 | { | |
1797 | /* General register. */ | |
1798 | return crisv32_genreg_names[regno]; | |
1799 | } | |
1800 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) | |
1801 | { | |
1802 | return cris_special_register_name (regno); | |
1803 | } | |
1804 | else if (regno == PC_REGNUM) | |
1805 | { | |
1806 | return "pc"; | |
1807 | } | |
1808 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) | |
1809 | { | |
1810 | return crisv32_sreg_names[regno - S0_REGNUM]; | |
1811 | } | |
2e4b5889 OF |
1812 | else |
1813 | { | |
1814 | /* Invalid register. */ | |
1815 | return NULL; | |
29134980 | 1816 | } |
29134980 OF |
1817 | } |
1818 | ||
a5f6c8f5 OF |
1819 | /* Convert DWARF register number REG to the appropriate register |
1820 | number used by GDB. */ | |
1821 | ||
2e4b5889 | 1822 | static int |
a5f6c8f5 | 1823 | cris_dwarf2_reg_to_regnum (int reg) |
29134980 | 1824 | { |
a5f6c8f5 OF |
1825 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
1826 | numbering, MOF is 18). | |
1827 | Adapted from gcc/config/cris/cris.h. */ | |
1828 | static int cris_dwarf_regmap[] = { | |
1829 | 0, 1, 2, 3, | |
1830 | 4, 5, 6, 7, | |
1831 | 8, 9, 10, 11, | |
1832 | 12, 13, 14, 15, | |
1833 | 27, -1, -1, -1, | |
1834 | -1, -1, -1, 23, | |
1835 | -1, -1, -1, 27, | |
1836 | -1, -1, -1, -1 | |
1837 | }; | |
1838 | int regnum = -1; | |
1839 | ||
1840 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) | |
1841 | regnum = cris_dwarf_regmap[reg]; | |
1842 | ||
1843 | if (regnum == -1) | |
8a3fe4f8 | 1844 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
a5f6c8f5 OF |
1845 | |
1846 | return regnum; | |
1847 | } | |
1848 | ||
1849 | /* DWARF-2 frame support. */ | |
1850 | ||
1851 | static void | |
1852 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 DM |
1853 | struct dwarf2_frame_state_reg *reg, |
1854 | struct frame_info *next_frame) | |
a5f6c8f5 OF |
1855 | { |
1856 | /* The return address column. */ | |
1857 | if (regnum == PC_REGNUM) | |
1858 | reg->how = DWARF2_FRAME_REG_RA; | |
1859 | ||
1860 | /* The call frame address. */ | |
1861 | else if (regnum == SP_REGNUM) | |
1862 | reg->how = DWARF2_FRAME_REG_CFA; | |
29134980 OF |
1863 | } |
1864 | ||
2e4b5889 OF |
1865 | /* Extract from an array regbuf containing the raw register state a function |
1866 | return value of type type, and copy that, in virtual format, into | |
1867 | valbuf. */ | |
1868 | ||
1869 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1870 | |
2e4b5889 OF |
1871 | static void |
1872 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
1873 | void *valbuf) | |
29134980 | 1874 | { |
2e4b5889 OF |
1875 | ULONGEST val; |
1876 | int len = TYPE_LENGTH (type); | |
29134980 | 1877 | |
2e4b5889 | 1878 | if (len <= 4) |
29134980 | 1879 | { |
2e4b5889 OF |
1880 | /* Get the return value from R10. */ |
1881 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1882 | store_unsigned_integer (valbuf, len, val); | |
29134980 | 1883 | } |
2e4b5889 | 1884 | else if (len <= 8) |
29134980 | 1885 | { |
2e4b5889 OF |
1886 | /* Get the return value from R10 and R11. */ |
1887 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1888 | store_unsigned_integer (valbuf, 4, val); | |
1889 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); | |
1890 | store_unsigned_integer ((char *)valbuf + 4, len - 4, val); | |
29134980 | 1891 | } |
2e4b5889 | 1892 | else |
8a3fe4f8 | 1893 | error (_("cris_extract_return_value: type length too large")); |
2e4b5889 OF |
1894 | } |
1895 | ||
b4206d25 OF |
1896 | /* Handle the CRIS return value convention. */ |
1897 | ||
1898 | static enum return_value_convention | |
1899 | cris_return_value (struct gdbarch *gdbarch, struct type *type, | |
e2a2a3e8 OF |
1900 | struct regcache *regcache, gdb_byte *readbuf, |
1901 | const gdb_byte *writebuf) | |
b4206d25 OF |
1902 | { |
1903 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1904 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1905 | || TYPE_LENGTH (type) > 8) | |
1906 | /* Structs, unions, and anything larger than 8 bytes (2 registers) | |
1907 | goes on the stack. */ | |
1908 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1909 | ||
1910 | if (readbuf) | |
1911 | cris_extract_return_value (type, regcache, readbuf); | |
1912 | if (writebuf) | |
1913 | cris_store_return_value (type, regcache, writebuf); | |
1914 | ||
1915 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1916 | } | |
1917 | ||
2e4b5889 OF |
1918 | /* Returns 1 if the given type will be passed by pointer rather than |
1919 | directly. */ | |
1920 | ||
1921 | /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed | |
1922 | by value. */ | |
1923 | ||
1924 | static int | |
1925 | cris_reg_struct_has_addr (int gcc_p, struct type *type) | |
1926 | { | |
1927 | return (TYPE_LENGTH (type) > 8); | |
29134980 OF |
1928 | } |
1929 | ||
1930 | /* Calculates a value that measures how good inst_args constraints an | |
1931 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1932 | ||
1933 | static int | |
1934 | constraint (unsigned int insn, const signed char *inst_args, | |
1935 | inst_env_type *inst_env) | |
1936 | { | |
1937 | int retval = 0; | |
1938 | int tmp, i; | |
1939 | ||
1940 | const char *s = inst_args; | |
1941 | ||
1942 | for (; *s; s++) | |
1943 | switch (*s) | |
1944 | { | |
1945 | case 'm': | |
1946 | if ((insn & 0x30) == 0x30) | |
1947 | return -1; | |
1948 | break; | |
1949 | ||
1950 | case 'S': | |
1951 | /* A prefix operand. */ | |
1952 | if (inst_env->prefix_found) | |
1953 | break; | |
1954 | else | |
1955 | return -1; | |
1956 | ||
1957 | case 'B': | |
1958 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1959 | valid "push" size. In case of special register, it may be != 4. */ | |
1960 | if (inst_env->prefix_found) | |
1961 | break; | |
1962 | else | |
1963 | return -1; | |
1964 | ||
1965 | case 'D': | |
1966 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1967 | if (!retval) | |
1968 | return -1; | |
1969 | else | |
1970 | retval += 4; | |
1971 | break; | |
1972 | ||
1973 | case 'P': | |
1974 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1975 | |
1976 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1977 | { | |
1978 | /* Since we match four bits, we will give a value of | |
1979 | 4 - 1 = 3 in a match. If there is a corresponding | |
1980 | exact match of a special register in another pattern, it | |
1981 | will get a value of 4, which will be higher. This should | |
1982 | be correct in that an exact pattern would match better that | |
1983 | a general pattern. | |
1984 | Note that there is a reason for not returning zero; the | |
1985 | pattern for "clear" is partly matched in the bit-pattern | |
1986 | (the two lower bits must be zero), while the bit-pattern | |
1987 | for a move from a special register is matched in the | |
1988 | register constraint. | |
1989 | This also means we will will have a race condition if | |
1990 | there is a partly match in three bits in the bit pattern. */ | |
1991 | if (tmp == cris_spec_regs[i].number) | |
1992 | { | |
1993 | retval += 3; | |
1994 | break; | |
1995 | } | |
1996 | } | |
1997 | ||
1998 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
1999 | return -1; |
2000 | break; | |
2001 | } | |
2002 | return retval; | |
2003 | } | |
2004 | ||
2005 | /* Returns the number of bits set in the variable value. */ | |
2006 | ||
2007 | static int | |
2008 | number_of_bits (unsigned int value) | |
2009 | { | |
2010 | int number_of_bits = 0; | |
2011 | ||
2012 | while (value != 0) | |
2013 | { | |
2014 | number_of_bits += 1; | |
2015 | value &= (value - 1); | |
2016 | } | |
2017 | return number_of_bits; | |
2018 | } | |
2019 | ||
2020 | /* Finds the address that should contain the single step breakpoint(s). | |
2021 | It stems from code in cris-dis.c. */ | |
2022 | ||
2023 | static int | |
2024 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
2025 | { | |
2026 | int i; | |
2027 | int max_level_of_match = -1; | |
2028 | int max_matched = -1; | |
2029 | int level_of_match; | |
2030 | ||
2031 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
2032 | { | |
2033 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
c600d464 OF |
2034 | && ((cris_opcodes[i].lose & insn) == 0) |
2035 | /* Only CRISv10 instructions, please. */ | |
2036 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) | |
29134980 OF |
2037 | { |
2038 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
2039 | if (level_of_match >= 0) | |
2040 | { | |
2041 | level_of_match += | |
2042 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
2043 | if (level_of_match > max_level_of_match) | |
2044 | { | |
2045 | max_matched = i; | |
2046 | max_level_of_match = level_of_match; | |
2047 | if (level_of_match == 16) | |
2048 | { | |
2049 | /* All bits matched, cannot find better. */ | |
2050 | break; | |
2051 | } | |
2052 | } | |
2053 | } | |
2054 | } | |
2055 | } | |
2056 | return max_matched; | |
2057 | } | |
2058 | ||
2059 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
2060 | actually an internal error. */ | |
2061 | ||
2062 | static int | |
0b1b3e42 | 2063 | find_step_target (struct frame_info *frame, inst_env_type *inst_env) |
29134980 OF |
2064 | { |
2065 | int i; | |
2066 | int offset; | |
2067 | unsigned short insn; | |
2068 | ||
2069 | /* Create a local register image and set the initial state. */ | |
2070 | for (i = 0; i < NUM_GENREGS; i++) | |
2071 | { | |
0b1b3e42 UW |
2072 | inst_env->reg[i] = |
2073 | (unsigned long) get_frame_register_unsigned (frame, i); | |
29134980 OF |
2074 | } |
2075 | offset = NUM_GENREGS; | |
2076 | for (i = 0; i < NUM_SPECREGS; i++) | |
2077 | { | |
0b1b3e42 UW |
2078 | inst_env->preg[i] = |
2079 | (unsigned long) get_frame_register_unsigned (frame, offset + i); | |
29134980 OF |
2080 | } |
2081 | inst_env->branch_found = 0; | |
2082 | inst_env->slot_needed = 0; | |
2083 | inst_env->delay_slot_pc_active = 0; | |
2084 | inst_env->prefix_found = 0; | |
2085 | inst_env->invalid = 0; | |
2086 | inst_env->xflag_found = 0; | |
2087 | inst_env->disable_interrupt = 0; | |
2088 | ||
2089 | /* Look for a step target. */ | |
2090 | do | |
2091 | { | |
2092 | /* Read an instruction from the client. */ | |
2093 | insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2); | |
2094 | ||
2095 | /* If the instruction is not in a delay slot the new content of the | |
2096 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
2097 | that simple. Since a instruction in a delay slot cannot change | |
2098 | the content of the PC, it does not matter what value PC will have. | |
2099 | Just make sure it is a valid instruction. */ | |
2100 | if (!inst_env->delay_slot_pc_active) | |
2101 | { | |
2102 | inst_env->reg[PC_REGNUM] += 2; | |
2103 | } | |
2104 | else | |
2105 | { | |
2106 | inst_env->delay_slot_pc_active = 0; | |
2107 | inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc; | |
2108 | } | |
2109 | /* Analyse the present instruction. */ | |
2110 | i = find_cris_op (insn, inst_env); | |
2111 | if (i == -1) | |
2112 | { | |
2113 | inst_env->invalid = 1; | |
2114 | } | |
2115 | else | |
2116 | { | |
2117 | cris_gdb_func (cris_opcodes[i].op, insn, inst_env); | |
2118 | } | |
2119 | } while (!inst_env->invalid | |
2120 | && (inst_env->prefix_found || inst_env->xflag_found | |
2121 | || inst_env->slot_needed)); | |
2122 | return i; | |
2123 | } | |
2124 | ||
2125 | /* There is no hardware single-step support. The function find_step_target | |
2126 | digs through the opcodes in order to find all possible targets. | |
2127 | Either one ordinary target or two targets for branches may be found. */ | |
2128 | ||
e6590a1b | 2129 | static int |
0b1b3e42 | 2130 | cris_software_single_step (struct frame_info *frame) |
29134980 OF |
2131 | { |
2132 | inst_env_type inst_env; | |
8181d85f | 2133 | |
e0cd558a UW |
2134 | /* Analyse the present instruction environment and insert |
2135 | breakpoints. */ | |
0b1b3e42 | 2136 | int status = find_step_target (frame, &inst_env); |
e0cd558a | 2137 | if (status == -1) |
29134980 | 2138 | { |
e0cd558a UW |
2139 | /* Could not find a target. Things are likely to go downhill |
2140 | from here. */ | |
2141 | warning (_("CRIS software single step could not find a step target.")); | |
29134980 OF |
2142 | } |
2143 | else | |
e0cd558a UW |
2144 | { |
2145 | /* Insert at most two breakpoints. One for the next PC content | |
2146 | and possibly another one for a branch, jump, etc. */ | |
2147 | CORE_ADDR next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM]; | |
2148 | insert_single_step_breakpoint (next_pc); | |
2149 | if (inst_env.branch_found | |
2150 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
2151 | { | |
2152 | CORE_ADDR branch_target_address | |
2153 | = (CORE_ADDR) inst_env.branch_break_address; | |
2154 | insert_single_step_breakpoint (branch_target_address); | |
2155 | } | |
2156 | } | |
e6590a1b UW |
2157 | |
2158 | return 1; | |
29134980 OF |
2159 | } |
2160 | ||
2161 | /* Calculates the prefix value for quick offset addressing mode. */ | |
2162 | ||
a78f21af | 2163 | static void |
29134980 OF |
2164 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2165 | { | |
2166 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
2167 | instruction (not 100% sure). */ | |
2168 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2169 | { | |
2170 | inst_env->invalid = 1; | |
2171 | return; | |
2172 | } | |
2173 | ||
2174 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
2175 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
2176 | ||
2177 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2178 | need updating. */ | |
2179 | inst_env->slot_needed = 0; | |
2180 | inst_env->prefix_found = 1; | |
2181 | } | |
2182 | ||
2183 | /* Updates the autoincrement register. The size of the increment is derived | |
2184 | from the size of the operation. The PC is always kept aligned on even | |
2185 | word addresses. */ | |
2186 | ||
a78f21af | 2187 | static void |
29134980 OF |
2188 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
2189 | { | |
2190 | if (size == INST_BYTE_SIZE) | |
2191 | { | |
2192 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
2193 | ||
2194 | /* The PC must be word aligned, so increase the PC with one | |
2195 | word even if the size is byte. */ | |
2196 | if (cris_get_operand1 (inst) == REG_PC) | |
2197 | { | |
2198 | inst_env->reg[REG_PC] += 1; | |
2199 | } | |
2200 | } | |
2201 | else if (size == INST_WORD_SIZE) | |
2202 | { | |
2203 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
2204 | } | |
2205 | else if (size == INST_DWORD_SIZE) | |
2206 | { | |
2207 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2208 | } | |
2209 | else | |
2210 | { | |
2211 | /* Invalid size. */ | |
2212 | inst_env->invalid = 1; | |
2213 | } | |
2214 | } | |
2215 | ||
2a9ecef2 OF |
2216 | /* Just a forward declaration. */ |
2217 | ||
a78f21af AC |
2218 | static unsigned long get_data_from_address (unsigned short *inst, |
2219 | CORE_ADDR address); | |
2a9ecef2 | 2220 | |
29134980 OF |
2221 | /* Calculates the prefix value for the general case of offset addressing |
2222 | mode. */ | |
2223 | ||
a78f21af | 2224 | static void |
29134980 OF |
2225 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2226 | { | |
2227 | ||
2228 | long offset; | |
2229 | ||
2230 | /* It's invalid to be in a delay slot. */ | |
2231 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2232 | { | |
2233 | inst_env->invalid = 1; | |
2234 | return; | |
2235 | } | |
2236 | ||
fa4e4598 OF |
2237 | /* The calculation of prefix_value used to be after process_autoincrement, |
2238 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
2239 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
2240 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
2241 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
2242 | ||
2243 | /* The offset is an indirection of the contents of the operand1 register. */ | |
2244 | inst_env->prefix_value += | |
2a9ecef2 OF |
2245 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]); |
2246 | ||
fa4e4598 OF |
2247 | if (cris_get_mode (inst) == AUTOINC_MODE) |
2248 | { | |
2249 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2250 | } | |
2251 | ||
29134980 OF |
2252 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
2253 | need updating. */ | |
2254 | inst_env->slot_needed = 0; | |
2255 | inst_env->prefix_found = 1; | |
2256 | } | |
2257 | ||
2258 | /* Calculates the prefix value for the index addressing mode. */ | |
2259 | ||
a78f21af | 2260 | static void |
29134980 OF |
2261 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
2262 | { | |
2263 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
2264 | have a prefix to this instruction. So I will treat this as invalid. */ | |
2265 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2266 | { | |
2267 | inst_env->invalid = 1; | |
2268 | return; | |
2269 | } | |
2270 | ||
2271 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
2272 | ||
2273 | /* The offset is the operand2 value shifted the size of the instruction | |
2274 | to the left. */ | |
2275 | inst_env->prefix_value += | |
2276 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
2277 | ||
2278 | /* If the PC is operand1 (base) the address used is the address after | |
2279 | the main instruction, i.e. address + 2 (the PC is already compensated | |
2280 | for the prefix operation). */ | |
2281 | if (cris_get_operand1 (inst) == REG_PC) | |
2282 | { | |
2283 | inst_env->prefix_value += 2; | |
2284 | } | |
2285 | ||
2286 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2287 | need updating. */ | |
2288 | inst_env->slot_needed = 0; | |
2289 | inst_env->xflag_found = 0; | |
2290 | inst_env->prefix_found = 1; | |
2291 | } | |
2292 | ||
2293 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
2294 | ||
a78f21af | 2295 | static void |
29134980 OF |
2296 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
2297 | { | |
2298 | ||
2299 | CORE_ADDR address; | |
2300 | ||
2301 | /* It's invalid to be in a delay slot. */ | |
2302 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2303 | { | |
2304 | inst_env->invalid = 1; | |
2305 | return; | |
2306 | } | |
2307 | ||
2308 | /* The prefix value is one dereference of the contents of the operand1 | |
2309 | register. */ | |
2310 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2311 | inst_env->prefix_value = read_memory_unsigned_integer (address, 4); | |
2312 | ||
2313 | /* Check if the mode is autoincrement. */ | |
2314 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2315 | { | |
2316 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2317 | } | |
2318 | ||
2319 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2320 | need updating. */ | |
2321 | inst_env->slot_needed = 0; | |
2322 | inst_env->xflag_found = 0; | |
2323 | inst_env->prefix_found = 1; | |
2324 | } | |
2325 | ||
2326 | /* Finds the destination for a branch with 8-bits offset. */ | |
2327 | ||
a78f21af | 2328 | static void |
29134980 OF |
2329 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2330 | { | |
2331 | ||
2332 | short offset; | |
2333 | ||
2334 | /* If we have a prefix or are in a delay slot it's bad. */ | |
2335 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2336 | { | |
2337 | inst_env->invalid = 1; | |
2338 | return; | |
2339 | } | |
2340 | ||
2341 | /* We have a branch, find out where the branch will land. */ | |
2342 | offset = cris_get_branch_short_offset (inst); | |
2343 | ||
2344 | /* Check if the offset is signed. */ | |
2345 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2346 | { | |
2347 | offset |= 0xFF00; | |
2348 | } | |
2349 | ||
2350 | /* The offset ends with the sign bit, set it to zero. The address | |
2351 | should always be word aligned. */ | |
2352 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2353 | ||
2354 | inst_env->branch_found = 1; | |
2355 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2356 | ||
2357 | inst_env->slot_needed = 1; | |
2358 | inst_env->prefix_found = 0; | |
2359 | inst_env->xflag_found = 0; | |
2360 | inst_env->disable_interrupt = 1; | |
2361 | } | |
2362 | ||
2363 | /* Finds the destination for a branch with 16-bits offset. */ | |
2364 | ||
a78f21af | 2365 | static void |
29134980 OF |
2366 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2367 | { | |
2368 | short offset; | |
2369 | ||
2370 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2371 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2372 | { | |
2373 | inst_env->invalid = 1; | |
2374 | return; | |
2375 | } | |
2376 | ||
2377 | /* We have a branch, find out the offset for the branch. */ | |
2378 | offset = read_memory_integer (inst_env->reg[REG_PC], 2); | |
2379 | ||
2380 | /* The instruction is one word longer than normal, so add one word | |
2381 | to the PC. */ | |
2382 | inst_env->reg[REG_PC] += 2; | |
2383 | ||
2384 | inst_env->branch_found = 1; | |
2385 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2386 | ||
2387 | ||
2388 | inst_env->slot_needed = 1; | |
2389 | inst_env->prefix_found = 0; | |
2390 | inst_env->xflag_found = 0; | |
2391 | inst_env->disable_interrupt = 1; | |
2392 | } | |
2393 | ||
2394 | /* Handles the ABS instruction. */ | |
2395 | ||
a78f21af | 2396 | static void |
29134980 OF |
2397 | abs_op (unsigned short inst, inst_env_type *inst_env) |
2398 | { | |
2399 | ||
2400 | long value; | |
2401 | ||
2402 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2403 | if (inst_env->prefix_found) | |
2404 | { | |
2405 | inst_env->invalid = 1; | |
2406 | return; | |
2407 | } | |
2408 | ||
2409 | /* Check if the operation affects the PC. */ | |
2410 | if (cris_get_operand2 (inst) == REG_PC) | |
2411 | { | |
2412 | ||
2413 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2414 | if (inst_env->slot_needed) | |
2415 | { | |
2416 | inst_env->invalid = 1; | |
2417 | return; | |
2418 | } | |
2419 | ||
2420 | value = (long) inst_env->reg[REG_PC]; | |
2421 | ||
2422 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2423 | if (value != SIGNED_DWORD_MASK) | |
2424 | { | |
2425 | value = -value; | |
2426 | inst_env->reg[REG_PC] = (long) value; | |
2427 | } | |
2428 | } | |
2429 | ||
2430 | inst_env->slot_needed = 0; | |
2431 | inst_env->prefix_found = 0; | |
2432 | inst_env->xflag_found = 0; | |
2433 | inst_env->disable_interrupt = 0; | |
2434 | } | |
2435 | ||
2436 | /* Handles the ADDI instruction. */ | |
2437 | ||
a78f21af | 2438 | static void |
29134980 OF |
2439 | addi_op (unsigned short inst, inst_env_type *inst_env) |
2440 | { | |
2441 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2442 | a prefix. */ | |
2443 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2444 | { | |
2445 | inst_env->invalid = 1; | |
2446 | return; | |
2447 | } | |
2448 | ||
2449 | inst_env->slot_needed = 0; | |
2450 | inst_env->prefix_found = 0; | |
2451 | inst_env->xflag_found = 0; | |
2452 | inst_env->disable_interrupt = 0; | |
2453 | } | |
2454 | ||
2455 | /* Handles the ASR instruction. */ | |
2456 | ||
a78f21af | 2457 | static void |
29134980 OF |
2458 | asr_op (unsigned short inst, inst_env_type *inst_env) |
2459 | { | |
2460 | int shift_steps; | |
2461 | unsigned long value; | |
2462 | unsigned long signed_extend_mask = 0; | |
2463 | ||
2464 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2465 | if (inst_env->prefix_found) | |
2466 | { | |
2467 | inst_env->invalid = 1; | |
2468 | return; | |
2469 | } | |
2470 | ||
2471 | /* Check if the PC is the target register. */ | |
2472 | if (cris_get_operand2 (inst) == REG_PC) | |
2473 | { | |
2474 | /* It's invalid to change the PC in a delay slot. */ | |
2475 | if (inst_env->slot_needed) | |
2476 | { | |
2477 | inst_env->invalid = 1; | |
2478 | return; | |
2479 | } | |
2480 | /* Get the number of bits to shift. */ | |
2481 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
2482 | value = inst_env->reg[REG_PC]; | |
2483 | ||
2484 | /* Find out how many bits the operation should apply to. */ | |
2485 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2486 | { | |
2487 | if (value & SIGNED_BYTE_MASK) | |
2488 | { | |
2489 | signed_extend_mask = 0xFF; | |
2490 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2491 | signed_extend_mask = ~signed_extend_mask; | |
2492 | } | |
2493 | value = value >> shift_steps; | |
2494 | value |= signed_extend_mask; | |
2495 | value &= 0xFF; | |
2496 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2497 | inst_env->reg[REG_PC] |= value; | |
2498 | } | |
2499 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2500 | { | |
2501 | if (value & SIGNED_WORD_MASK) | |
2502 | { | |
2503 | signed_extend_mask = 0xFFFF; | |
2504 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2505 | signed_extend_mask = ~signed_extend_mask; | |
2506 | } | |
2507 | value = value >> shift_steps; | |
2508 | value |= signed_extend_mask; | |
2509 | value &= 0xFFFF; | |
2510 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2511 | inst_env->reg[REG_PC] |= value; | |
2512 | } | |
2513 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2514 | { | |
2515 | if (value & SIGNED_DWORD_MASK) | |
2516 | { | |
2517 | signed_extend_mask = 0xFFFFFFFF; | |
2518 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2519 | signed_extend_mask = ~signed_extend_mask; | |
2520 | } | |
2521 | value = value >> shift_steps; | |
2522 | value |= signed_extend_mask; | |
2523 | inst_env->reg[REG_PC] = value; | |
2524 | } | |
2525 | } | |
2526 | inst_env->slot_needed = 0; | |
2527 | inst_env->prefix_found = 0; | |
2528 | inst_env->xflag_found = 0; | |
2529 | inst_env->disable_interrupt = 0; | |
2530 | } | |
2531 | ||
2532 | /* Handles the ASRQ instruction. */ | |
2533 | ||
a78f21af | 2534 | static void |
29134980 OF |
2535 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2536 | { | |
2537 | ||
2538 | int shift_steps; | |
2539 | unsigned long value; | |
2540 | unsigned long signed_extend_mask = 0; | |
2541 | ||
2542 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2543 | if (inst_env->prefix_found) | |
2544 | { | |
2545 | inst_env->invalid = 1; | |
2546 | return; | |
2547 | } | |
2548 | ||
2549 | /* Check if the PC is the target register. */ | |
2550 | if (cris_get_operand2 (inst) == REG_PC) | |
2551 | { | |
2552 | ||
2553 | /* It's invalid to change the PC in a delay slot. */ | |
2554 | if (inst_env->slot_needed) | |
2555 | { | |
2556 | inst_env->invalid = 1; | |
2557 | return; | |
2558 | } | |
2559 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
2560 | want the the sign bit of the quick value. */ | |
2561 | shift_steps = cris_get_asr_shift_steps (inst); | |
2562 | value = inst_env->reg[REG_PC]; | |
2563 | if (value & SIGNED_DWORD_MASK) | |
2564 | { | |
2565 | signed_extend_mask = 0xFFFFFFFF; | |
2566 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2567 | signed_extend_mask = ~signed_extend_mask; | |
2568 | } | |
2569 | value = value >> shift_steps; | |
2570 | value |= signed_extend_mask; | |
2571 | inst_env->reg[REG_PC] = value; | |
2572 | } | |
2573 | inst_env->slot_needed = 0; | |
2574 | inst_env->prefix_found = 0; | |
2575 | inst_env->xflag_found = 0; | |
2576 | inst_env->disable_interrupt = 0; | |
2577 | } | |
2578 | ||
2579 | /* Handles the AX, EI and SETF instruction. */ | |
2580 | ||
a78f21af | 2581 | static void |
29134980 OF |
2582 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2583 | { | |
2584 | if (inst_env->prefix_found) | |
2585 | { | |
2586 | inst_env->invalid = 1; | |
2587 | return; | |
2588 | } | |
2589 | /* Check if the instruction is setting the X flag. */ | |
2590 | if (cris_is_xflag_bit_on (inst)) | |
2591 | { | |
2592 | inst_env->xflag_found = 1; | |
2593 | } | |
2594 | else | |
2595 | { | |
2596 | inst_env->xflag_found = 0; | |
2597 | } | |
2598 | inst_env->slot_needed = 0; | |
2599 | inst_env->prefix_found = 0; | |
2600 | inst_env->disable_interrupt = 1; | |
2601 | } | |
2602 | ||
2603 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2604 | register. Note that check_assign assumes that the caller has checked that | |
2605 | there is a prefix to this instruction. The mode check depends on this. */ | |
2606 | ||
a78f21af | 2607 | static void |
29134980 OF |
2608 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2609 | { | |
2610 | /* Check if it's an assign addressing mode. */ | |
2611 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2612 | { | |
2613 | /* Assign the prefix value to operand 1. */ | |
2614 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2615 | } | |
2616 | } | |
2617 | ||
2618 | /* Handles the 2-operand BOUND instruction. */ | |
2619 | ||
a78f21af | 2620 | static void |
29134980 OF |
2621 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2622 | { | |
2623 | /* It's invalid to have the PC as the index operand. */ | |
2624 | if (cris_get_operand2 (inst) == REG_PC) | |
2625 | { | |
2626 | inst_env->invalid = 1; | |
2627 | return; | |
2628 | } | |
2629 | /* Check if we have a prefix. */ | |
2630 | if (inst_env->prefix_found) | |
2631 | { | |
2632 | check_assign (inst, inst_env); | |
2633 | } | |
2634 | /* Check if this is an autoincrement mode. */ | |
2635 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2636 | { | |
2637 | /* It's invalid to change the PC in a delay slot. */ | |
2638 | if (inst_env->slot_needed) | |
2639 | { | |
2640 | inst_env->invalid = 1; | |
2641 | return; | |
2642 | } | |
2643 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2644 | } | |
2645 | inst_env->slot_needed = 0; | |
2646 | inst_env->prefix_found = 0; | |
2647 | inst_env->xflag_found = 0; | |
2648 | inst_env->disable_interrupt = 0; | |
2649 | } | |
2650 | ||
2651 | /* Handles the 3-operand BOUND instruction. */ | |
2652 | ||
a78f21af | 2653 | static void |
29134980 OF |
2654 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2655 | { | |
2656 | /* It's an error if we haven't got a prefix. And it's also an error | |
2657 | if the PC is the destination register. */ | |
2658 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2659 | { | |
2660 | inst_env->invalid = 1; | |
2661 | return; | |
2662 | } | |
2663 | inst_env->slot_needed = 0; | |
2664 | inst_env->prefix_found = 0; | |
2665 | inst_env->xflag_found = 0; | |
2666 | inst_env->disable_interrupt = 0; | |
2667 | } | |
2668 | ||
2669 | /* Clears the status flags in inst_env. */ | |
2670 | ||
a78f21af | 2671 | static void |
29134980 OF |
2672 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2673 | { | |
2674 | /* It's an error if we have got a prefix. */ | |
2675 | if (inst_env->prefix_found) | |
2676 | { | |
2677 | inst_env->invalid = 1; | |
2678 | return; | |
2679 | } | |
2680 | ||
2681 | inst_env->slot_needed = 0; | |
2682 | inst_env->prefix_found = 0; | |
2683 | inst_env->xflag_found = 0; | |
2684 | inst_env->disable_interrupt = 0; | |
2685 | } | |
2686 | ||
2687 | /* Clears the status flags in inst_env. */ | |
2688 | ||
a78f21af | 2689 | static void |
29134980 OF |
2690 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2691 | { | |
2692 | /* It's an error if we have got a prefix. */ | |
2693 | if (inst_env->prefix_found) | |
2694 | { | |
2695 | inst_env->invalid = 1; | |
2696 | return; | |
2697 | } | |
2698 | ||
2699 | inst_env->slot_needed = 0; | |
2700 | inst_env->prefix_found = 0; | |
2701 | inst_env->xflag_found = 0; | |
2702 | inst_env->disable_interrupt = 1; | |
2703 | } | |
2704 | ||
2705 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2706 | ||
a78f21af | 2707 | static void |
29134980 OF |
2708 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2709 | { | |
2710 | /* Check if the target is the PC. */ | |
2711 | if (cris_get_operand2 (inst) == REG_PC) | |
2712 | { | |
2713 | /* The instruction will clear the instruction's size bits. */ | |
2714 | int clear_size = cris_get_clear_size (inst); | |
2715 | if (clear_size == INST_BYTE_SIZE) | |
2716 | { | |
2717 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2718 | } | |
2719 | if (clear_size == INST_WORD_SIZE) | |
2720 | { | |
2721 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2722 | } | |
2723 | if (clear_size == INST_DWORD_SIZE) | |
2724 | { | |
2725 | inst_env->delay_slot_pc = 0x0; | |
2726 | } | |
2727 | /* The jump will be delayed with one delay slot. So we need a delay | |
2728 | slot. */ | |
2729 | inst_env->slot_needed = 1; | |
2730 | inst_env->delay_slot_pc_active = 1; | |
2731 | } | |
2732 | else | |
2733 | { | |
2734 | /* The PC will not change => no delay slot. */ | |
2735 | inst_env->slot_needed = 0; | |
2736 | } | |
2737 | inst_env->prefix_found = 0; | |
2738 | inst_env->xflag_found = 0; | |
2739 | inst_env->disable_interrupt = 0; | |
2740 | } | |
2741 | ||
2742 | /* Handles the TEST instruction if it's in register mode. */ | |
2743 | ||
a78f21af | 2744 | static void |
29134980 OF |
2745 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2746 | { | |
2747 | /* It's an error if we have got a prefix. */ | |
2748 | if (inst_env->prefix_found) | |
2749 | { | |
2750 | inst_env->invalid = 1; | |
2751 | return; | |
2752 | } | |
2753 | inst_env->slot_needed = 0; | |
2754 | inst_env->prefix_found = 0; | |
2755 | inst_env->xflag_found = 0; | |
2756 | inst_env->disable_interrupt = 0; | |
2757 | ||
2758 | } | |
2759 | ||
2760 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2761 | in register mode. */ | |
2762 | ||
a78f21af | 2763 | static void |
29134980 OF |
2764 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2765 | { | |
2766 | /* Check if we are in a prefix mode. */ | |
2767 | if (inst_env->prefix_found) | |
2768 | { | |
2769 | /* The only way the PC can change is if this instruction is in | |
2770 | assign addressing mode. */ | |
2771 | check_assign (inst, inst_env); | |
2772 | } | |
2773 | /* Indirect mode can't change the PC so just check if the mode is | |
2774 | autoincrement. */ | |
2775 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2776 | { | |
2777 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2778 | } | |
2779 | inst_env->slot_needed = 0; | |
2780 | inst_env->prefix_found = 0; | |
2781 | inst_env->xflag_found = 0; | |
2782 | inst_env->disable_interrupt = 0; | |
2783 | } | |
2784 | ||
2785 | /* Checks that the PC isn't the destination register or the instructions has | |
2786 | a prefix. */ | |
2787 | ||
a78f21af | 2788 | static void |
29134980 OF |
2789 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2790 | { | |
2791 | /* It's invalid to have the PC as the destination. The instruction can't | |
2792 | have a prefix. */ | |
2793 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2794 | { | |
2795 | inst_env->invalid = 1; | |
2796 | return; | |
2797 | } | |
2798 | ||
2799 | inst_env->slot_needed = 0; | |
2800 | inst_env->prefix_found = 0; | |
2801 | inst_env->xflag_found = 0; | |
2802 | inst_env->disable_interrupt = 0; | |
2803 | } | |
2804 | ||
2805 | /* Checks that the instruction doesn't have a prefix. */ | |
2806 | ||
a78f21af | 2807 | static void |
29134980 OF |
2808 | break_op (unsigned short inst, inst_env_type *inst_env) |
2809 | { | |
2810 | /* The instruction can't have a prefix. */ | |
2811 | if (inst_env->prefix_found) | |
2812 | { | |
2813 | inst_env->invalid = 1; | |
2814 | return; | |
2815 | } | |
2816 | ||
2817 | inst_env->slot_needed = 0; | |
2818 | inst_env->prefix_found = 0; | |
2819 | inst_env->xflag_found = 0; | |
2820 | inst_env->disable_interrupt = 1; | |
2821 | } | |
2822 | ||
2823 | /* Checks that the PC isn't the destination register and that the instruction | |
2824 | doesn't have a prefix. */ | |
2825 | ||
a78f21af | 2826 | static void |
29134980 OF |
2827 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2828 | { | |
2829 | /* It's invalid to have the PC as the destination. The instruction can't | |
2830 | have a prefix. */ | |
2831 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2832 | { | |
2833 | inst_env->invalid = 1; | |
2834 | return; | |
2835 | } | |
2836 | ||
2837 | inst_env->slot_needed = 0; | |
2838 | inst_env->prefix_found = 0; | |
2839 | inst_env->xflag_found = 0; | |
2840 | inst_env->disable_interrupt = 1; | |
2841 | } | |
2842 | ||
2843 | /* Handles the register mode JUMP instruction. */ | |
2844 | ||
a78f21af | 2845 | static void |
29134980 OF |
2846 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2847 | { | |
2848 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2849 | you can't have a prefix. */ | |
2850 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2851 | { | |
2852 | inst_env->invalid = 1; | |
2853 | return; | |
2854 | } | |
2855 | ||
2856 | /* Just change the PC. */ | |
2857 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2858 | inst_env->slot_needed = 0; | |
2859 | inst_env->prefix_found = 0; | |
2860 | inst_env->xflag_found = 0; | |
2861 | inst_env->disable_interrupt = 1; | |
2862 | } | |
2863 | ||
2864 | /* Handles the JUMP instruction for all modes except register. */ | |
2865 | ||
a78f21af AC |
2866 | static void |
2867 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2868 | { |
2869 | unsigned long newpc; | |
2870 | CORE_ADDR address; | |
2871 | ||
2872 | /* It's invalid to do a JUMP in a delay slot. */ | |
2873 | if (inst_env->slot_needed) | |
2874 | { | |
2875 | inst_env->invalid = 1; | |
2876 | } | |
2877 | else | |
2878 | { | |
2879 | /* Check if we have a prefix. */ | |
2880 | if (inst_env->prefix_found) | |
2881 | { | |
2882 | check_assign (inst, inst_env); | |
2883 | ||
2884 | /* Get the new value for the the PC. */ | |
2885 | newpc = | |
2886 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
2887 | 4); | |
2888 | } | |
2889 | else | |
2890 | { | |
2891 | /* Get the new value for the PC. */ | |
2892 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2893 | newpc = read_memory_unsigned_integer (address, 4); | |
2894 | ||
2895 | /* Check if we should increment a register. */ | |
2896 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2897 | { | |
2898 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2899 | } | |
2900 | } | |
2901 | inst_env->reg[REG_PC] = newpc; | |
2902 | } | |
2903 | inst_env->slot_needed = 0; | |
2904 | inst_env->prefix_found = 0; | |
2905 | inst_env->xflag_found = 0; | |
2906 | inst_env->disable_interrupt = 1; | |
2907 | } | |
2908 | ||
2909 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2910 | ||
a78f21af | 2911 | static void |
29134980 OF |
2912 | move_to_preg_op (unsigned short inst, inst_env_type *inst_env) |
2913 | { | |
2914 | if (inst_env->prefix_found) | |
2915 | { | |
2916 | /* The instruction has a prefix that means we are only interested if | |
2917 | the instruction is in assign mode. */ | |
2918 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2919 | { | |
2920 | /* The prefix handles the problem if we are in a delay slot. */ | |
2921 | if (cris_get_operand1 (inst) == REG_PC) | |
2922 | { | |
2923 | /* Just take care of the assign. */ | |
2924 | check_assign (inst, inst_env); | |
2925 | } | |
2926 | } | |
2927 | } | |
2928 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2929 | { | |
2930 | /* The instruction doesn't have a prefix, the only case left that we | |
2931 | are interested in is the autoincrement mode. */ | |
2932 | if (cris_get_operand1 (inst) == REG_PC) | |
2933 | { | |
2934 | /* If the PC is to be incremented it's invalid to be in a | |
2935 | delay slot. */ | |
2936 | if (inst_env->slot_needed) | |
2937 | { | |
2938 | inst_env->invalid = 1; | |
2939 | return; | |
2940 | } | |
2a9ecef2 OF |
2941 | |
2942 | /* The increment depends on the size of the special register. */ | |
2943 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2944 | { |
2945 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2946 | } | |
2a9ecef2 | 2947 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2948 | { |
2949 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2950 | } | |
2951 | else | |
2952 | { | |
2953 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2954 | } | |
2955 | } | |
2956 | } | |
2957 | inst_env->slot_needed = 0; | |
2958 | inst_env->prefix_found = 0; | |
2959 | inst_env->xflag_found = 0; | |
2960 | inst_env->disable_interrupt = 1; | |
2961 | } | |
2962 | ||
2963 | /* Handles moves from special registers (aka P-register) for all modes | |
2964 | except register. */ | |
2965 | ||
a78f21af | 2966 | static void |
29134980 OF |
2967 | none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2968 | { | |
2969 | if (inst_env->prefix_found) | |
2970 | { | |
2971 | /* The instruction has a prefix that means we are only interested if | |
2972 | the instruction is in assign mode. */ | |
2973 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2974 | { | |
2975 | /* The prefix handles the problem if we are in a delay slot. */ | |
2976 | if (cris_get_operand1 (inst) == REG_PC) | |
2977 | { | |
2978 | /* Just take care of the assign. */ | |
2979 | check_assign (inst, inst_env); | |
2980 | } | |
2981 | } | |
2982 | } | |
2983 | /* The instruction doesn't have a prefix, the only case left that we | |
2984 | are interested in is the autoincrement mode. */ | |
2985 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2986 | { | |
2987 | if (cris_get_operand1 (inst) == REG_PC) | |
2988 | { | |
2989 | /* If the PC is to be incremented it's invalid to be in a | |
2990 | delay slot. */ | |
2991 | if (inst_env->slot_needed) | |
2992 | { | |
2993 | inst_env->invalid = 1; | |
2994 | return; | |
2995 | } | |
2a9ecef2 OF |
2996 | |
2997 | /* The increment depends on the size of the special register. */ | |
2998 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2999 | { |
3000 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
3001 | } | |
2a9ecef2 | 3002 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
3003 | { |
3004 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
3005 | } | |
3006 | else | |
3007 | { | |
3008 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
3009 | } | |
3010 | } | |
3011 | } | |
3012 | inst_env->slot_needed = 0; | |
3013 | inst_env->prefix_found = 0; | |
3014 | inst_env->xflag_found = 0; | |
3015 | inst_env->disable_interrupt = 1; | |
3016 | } | |
3017 | ||
3018 | /* Handles moves from special registers (aka P-register) when the mode | |
3019 | is register. */ | |
3020 | ||
a78f21af | 3021 | static void |
29134980 OF |
3022 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
3023 | { | |
3024 | /* Register mode move from special register can't have a prefix. */ | |
3025 | if (inst_env->prefix_found) | |
3026 | { | |
3027 | inst_env->invalid = 1; | |
3028 | return; | |
3029 | } | |
3030 | ||
3031 | if (cris_get_operand1 (inst) == REG_PC) | |
3032 | { | |
3033 | /* It's invalid to change the PC in a delay slot. */ | |
3034 | if (inst_env->slot_needed) | |
3035 | { | |
3036 | inst_env->invalid = 1; | |
3037 | return; | |
3038 | } | |
3039 | /* The destination is the PC, the jump will have a delay slot. */ | |
3040 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
3041 | inst_env->slot_needed = 1; | |
3042 | inst_env->delay_slot_pc_active = 1; | |
3043 | } | |
3044 | else | |
3045 | { | |
3046 | /* If the destination isn't PC, there will be no jump. */ | |
3047 | inst_env->slot_needed = 0; | |
3048 | } | |
3049 | inst_env->prefix_found = 0; | |
3050 | inst_env->xflag_found = 0; | |
3051 | inst_env->disable_interrupt = 1; | |
3052 | } | |
3053 | ||
3054 | /* Handles the MOVEM from memory to general register instruction. */ | |
3055 | ||
a78f21af | 3056 | static void |
29134980 OF |
3057 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
3058 | { | |
3059 | if (inst_env->prefix_found) | |
3060 | { | |
3061 | /* The prefix handles the problem if we are in a delay slot. Is the | |
3062 | MOVEM instruction going to change the PC? */ | |
3063 | if (cris_get_operand2 (inst) >= REG_PC) | |
3064 | { | |
3065 | inst_env->reg[REG_PC] = | |
3066 | read_memory_unsigned_integer (inst_env->prefix_value, 4); | |
3067 | } | |
3068 | /* The assign value is the value after the increment. Normally, the | |
3069 | assign value is the value before the increment. */ | |
3070 | if ((cris_get_operand1 (inst) == REG_PC) | |
3071 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3072 | { | |
3073 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3074 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3075 | } | |
3076 | } | |
3077 | else | |
3078 | { | |
3079 | /* Is the MOVEM instruction going to change the PC? */ | |
3080 | if (cris_get_operand2 (inst) == REG_PC) | |
3081 | { | |
3082 | /* It's invalid to change the PC in a delay slot. */ | |
3083 | if (inst_env->slot_needed) | |
3084 | { | |
3085 | inst_env->invalid = 1; | |
3086 | return; | |
3087 | } | |
3088 | inst_env->reg[REG_PC] = | |
3089 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
3090 | 4); | |
3091 | } | |
3092 | /* The increment is not depending on the size, instead it's depending | |
3093 | on the number of registers loaded from memory. */ | |
3094 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3095 | { | |
3096 | /* It's invalid to change the PC in a delay slot. */ | |
3097 | if (inst_env->slot_needed) | |
3098 | { | |
3099 | inst_env->invalid = 1; | |
3100 | return; | |
3101 | } | |
3102 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3103 | } | |
3104 | } | |
3105 | inst_env->slot_needed = 0; | |
3106 | inst_env->prefix_found = 0; | |
3107 | inst_env->xflag_found = 0; | |
3108 | inst_env->disable_interrupt = 0; | |
3109 | } | |
3110 | ||
3111 | /* Handles the MOVEM to memory from general register instruction. */ | |
3112 | ||
a78f21af | 3113 | static void |
29134980 OF |
3114 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
3115 | { | |
3116 | if (inst_env->prefix_found) | |
3117 | { | |
3118 | /* The assign value is the value after the increment. Normally, the | |
3119 | assign value is the value before the increment. */ | |
3120 | if ((cris_get_operand1 (inst) == REG_PC) && | |
3121 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3122 | { | |
3123 | /* The prefix handles the problem if we are in a delay slot. */ | |
3124 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3125 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3126 | } | |
3127 | } | |
3128 | else | |
3129 | { | |
3130 | /* The increment is not depending on the size, instead it's depending | |
3131 | on the number of registers loaded to memory. */ | |
3132 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3133 | { | |
3134 | /* It's invalid to change the PC in a delay slot. */ | |
3135 | if (inst_env->slot_needed) | |
3136 | { | |
3137 | inst_env->invalid = 1; | |
3138 | return; | |
3139 | } | |
3140 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3141 | } | |
3142 | } | |
3143 | inst_env->slot_needed = 0; | |
3144 | inst_env->prefix_found = 0; | |
3145 | inst_env->xflag_found = 0; | |
3146 | inst_env->disable_interrupt = 0; | |
3147 | } | |
3148 | ||
29134980 OF |
3149 | /* Handles the intructions that's not yet implemented, by setting |
3150 | inst_env->invalid to true. */ | |
3151 | ||
a78f21af | 3152 | static void |
29134980 OF |
3153 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
3154 | { | |
3155 | inst_env->invalid = 1; | |
3156 | } | |
3157 | ||
3158 | /* Handles the XOR instruction. */ | |
3159 | ||
a78f21af | 3160 | static void |
29134980 OF |
3161 | xor_op (unsigned short inst, inst_env_type *inst_env) |
3162 | { | |
3163 | /* XOR can't have a prefix. */ | |
3164 | if (inst_env->prefix_found) | |
3165 | { | |
3166 | inst_env->invalid = 1; | |
3167 | return; | |
3168 | } | |
3169 | ||
3170 | /* Check if the PC is the target. */ | |
3171 | if (cris_get_operand2 (inst) == REG_PC) | |
3172 | { | |
3173 | /* It's invalid to change the PC in a delay slot. */ | |
3174 | if (inst_env->slot_needed) | |
3175 | { | |
3176 | inst_env->invalid = 1; | |
3177 | return; | |
3178 | } | |
3179 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
3180 | } | |
3181 | inst_env->slot_needed = 0; | |
3182 | inst_env->prefix_found = 0; | |
3183 | inst_env->xflag_found = 0; | |
3184 | inst_env->disable_interrupt = 0; | |
3185 | } | |
3186 | ||
3187 | /* Handles the MULS instruction. */ | |
3188 | ||
a78f21af | 3189 | static void |
29134980 OF |
3190 | muls_op (unsigned short inst, inst_env_type *inst_env) |
3191 | { | |
3192 | /* MULS/U can't have a prefix. */ | |
3193 | if (inst_env->prefix_found) | |
3194 | { | |
3195 | inst_env->invalid = 1; | |
3196 | return; | |
3197 | } | |
3198 | ||
3199 | /* Consider it invalid if the PC is the target. */ | |
3200 | if (cris_get_operand2 (inst) == REG_PC) | |
3201 | { | |
3202 | inst_env->invalid = 1; | |
3203 | return; | |
3204 | } | |
3205 | inst_env->slot_needed = 0; | |
3206 | inst_env->prefix_found = 0; | |
3207 | inst_env->xflag_found = 0; | |
3208 | inst_env->disable_interrupt = 0; | |
3209 | } | |
3210 | ||
3211 | /* Handles the MULU instruction. */ | |
3212 | ||
a78f21af | 3213 | static void |
29134980 OF |
3214 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
3215 | { | |
3216 | /* MULS/U can't have a prefix. */ | |
3217 | if (inst_env->prefix_found) | |
3218 | { | |
3219 | inst_env->invalid = 1; | |
3220 | return; | |
3221 | } | |
3222 | ||
3223 | /* Consider it invalid if the PC is the target. */ | |
3224 | if (cris_get_operand2 (inst) == REG_PC) | |
3225 | { | |
3226 | inst_env->invalid = 1; | |
3227 | return; | |
3228 | } | |
3229 | inst_env->slot_needed = 0; | |
3230 | inst_env->prefix_found = 0; | |
3231 | inst_env->xflag_found = 0; | |
3232 | inst_env->disable_interrupt = 0; | |
3233 | } | |
3234 | ||
3235 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. | |
3236 | The MOVE instruction is the move from source to register. */ | |
3237 | ||
a78f21af | 3238 | static void |
29134980 OF |
3239 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
3240 | unsigned long source1, unsigned long source2) | |
3241 | { | |
3242 | unsigned long pc_mask; | |
3243 | unsigned long operation_mask; | |
3244 | ||
3245 | /* Find out how many bits the operation should apply to. */ | |
3246 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
3247 | { | |
3248 | pc_mask = 0xFFFFFF00; | |
3249 | operation_mask = 0xFF; | |
3250 | } | |
3251 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
3252 | { | |
3253 | pc_mask = 0xFFFF0000; | |
3254 | operation_mask = 0xFFFF; | |
3255 | } | |
3256 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
3257 | { | |
3258 | pc_mask = 0x0; | |
3259 | operation_mask = 0xFFFFFFFF; | |
3260 | } | |
3261 | else | |
3262 | { | |
3263 | /* The size is out of range. */ | |
3264 | inst_env->invalid = 1; | |
3265 | return; | |
3266 | } | |
3267 | ||
3268 | /* The instruction just works on uw_operation_mask bits. */ | |
3269 | source2 &= operation_mask; | |
3270 | source1 &= operation_mask; | |
3271 | ||
3272 | /* Now calculate the result. The opcode's 3 first bits separates | |
3273 | the different actions. */ | |
3274 | switch (cris_get_opcode (inst) & 7) | |
3275 | { | |
3276 | case 0: /* add */ | |
3277 | source1 += source2; | |
3278 | break; | |
3279 | ||
3280 | case 1: /* move */ | |
3281 | source1 = source2; | |
3282 | break; | |
3283 | ||
3284 | case 2: /* subtract */ | |
3285 | source1 -= source2; | |
3286 | break; | |
3287 | ||
3288 | case 3: /* compare */ | |
3289 | break; | |
3290 | ||
3291 | case 4: /* and */ | |
3292 | source1 &= source2; | |
3293 | break; | |
3294 | ||
3295 | case 5: /* or */ | |
3296 | source1 |= source2; | |
3297 | break; | |
3298 | ||
3299 | default: | |
3300 | inst_env->invalid = 1; | |
3301 | return; | |
3302 | ||
3303 | break; | |
3304 | } | |
3305 | ||
3306 | /* Make sure that the result doesn't contain more than the instruction | |
3307 | size bits. */ | |
3308 | source2 &= operation_mask; | |
3309 | ||
3310 | /* Calculate the new breakpoint address. */ | |
3311 | inst_env->reg[REG_PC] &= pc_mask; | |
3312 | inst_env->reg[REG_PC] |= source1; | |
3313 | ||
3314 | } | |
3315 | ||
3316 | /* Extends the value from either byte or word size to a dword. If the mode | |
3317 | is zero extend then the value is extended with zero. If instead the mode | |
3318 | is signed extend the sign bit of the value is taken into consideration. */ | |
3319 | ||
a78f21af | 3320 | static unsigned long |
29134980 OF |
3321 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
3322 | { | |
3323 | /* The size can be either byte or word, check which one it is. | |
3324 | Don't check the highest bit, it's indicating if it's a zero | |
3325 | or sign extend. */ | |
3326 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3327 | { | |
3328 | /* Word size. */ | |
3329 | value &= 0xFFFF; | |
3330 | ||
3331 | /* Check if the instruction is signed extend. If so, check if value has | |
3332 | the sign bit on. */ | |
3333 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3334 | { | |
3335 | value |= SIGNED_WORD_EXTEND_MASK; | |
3336 | } | |
3337 | } | |
3338 | else | |
3339 | { | |
3340 | /* Byte size. */ | |
3341 | value &= 0xFF; | |
3342 | ||
3343 | /* Check if the instruction is signed extend. If so, check if value has | |
3344 | the sign bit on. */ | |
3345 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3346 | { | |
3347 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3348 | } | |
3349 | } | |
3350 | /* The size should now be dword. */ | |
3351 | cris_set_size_to_dword (inst); | |
3352 | return value; | |
3353 | } | |
3354 | ||
3355 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3356 | instruction. The MOVE instruction is the move from source to register. */ | |
3357 | ||
a78f21af | 3358 | static void |
29134980 OF |
3359 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3360 | inst_env_type *inst_env) | |
3361 | { | |
3362 | unsigned long operand1; | |
3363 | unsigned long operand2; | |
3364 | ||
3365 | /* It's invalid to have a prefix to the instruction. This is a register | |
3366 | mode instruction and can't have a prefix. */ | |
3367 | if (inst_env->prefix_found) | |
3368 | { | |
3369 | inst_env->invalid = 1; | |
3370 | return; | |
3371 | } | |
3372 | /* Check if the instruction has PC as its target. */ | |
3373 | if (cris_get_operand2 (inst) == REG_PC) | |
3374 | { | |
3375 | if (inst_env->slot_needed) | |
3376 | { | |
3377 | inst_env->invalid = 1; | |
3378 | return; | |
3379 | } | |
3380 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3381 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3382 | operand2 = inst_env->reg[REG_PC]; |
3383 | ||
3384 | /* Check if it's a extend, signed or zero instruction. */ | |
3385 | if (cris_get_opcode (inst) < 4) | |
3386 | { | |
3387 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3388 | } | |
3389 | /* Calculate the PC value after the instruction, i.e. where the | |
3390 | breakpoint should be. The order of the udw_operands is vital. */ | |
3391 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3392 | } | |
3393 | inst_env->slot_needed = 0; | |
3394 | inst_env->prefix_found = 0; | |
3395 | inst_env->xflag_found = 0; | |
3396 | inst_env->disable_interrupt = 0; | |
3397 | } | |
3398 | ||
3399 | /* Returns the data contained at address. The size of the data is derived from | |
3400 | the size of the operation. If the instruction is a zero or signed | |
3401 | extend instruction, the size field is changed in instruction. */ | |
3402 | ||
a78f21af | 3403 | static unsigned long |
29134980 OF |
3404 | get_data_from_address (unsigned short *inst, CORE_ADDR address) |
3405 | { | |
3406 | int size = cris_get_size (*inst); | |
3407 | unsigned long value; | |
3408 | ||
3409 | /* If it's an extend instruction we don't want the signed extend bit, | |
3410 | because it influences the size. */ | |
3411 | if (cris_get_opcode (*inst) < 4) | |
3412 | { | |
3413 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3414 | } | |
3415 | /* Is there a need for checking the size? Size should contain the number of | |
3416 | bytes to read. */ | |
3417 | size = 1 << size; | |
3418 | value = read_memory_unsigned_integer (address, size); | |
3419 | ||
3420 | /* Check if it's an extend, signed or zero instruction. */ | |
3421 | if (cris_get_opcode (*inst) < 4) | |
3422 | { | |
3423 | value = do_sign_or_zero_extend (value, inst); | |
3424 | } | |
3425 | return value; | |
3426 | } | |
3427 | ||
3428 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3429 | instructions. The MOVE instruction is the move from source to register. */ | |
3430 | ||
a78f21af | 3431 | static void |
29134980 OF |
3432 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
3433 | inst_env_type *inst_env) | |
3434 | { | |
3435 | unsigned long operand2; | |
3436 | unsigned long operand3; | |
3437 | ||
3438 | check_assign (inst, inst_env); | |
3439 | if (cris_get_operand2 (inst) == REG_PC) | |
3440 | { | |
3441 | operand2 = inst_env->reg[REG_PC]; | |
3442 | ||
3443 | /* Get the value of the third operand. */ | |
3444 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3445 | ||
3446 | /* Calculate the PC value after the instruction, i.e. where the | |
3447 | breakpoint should be. The order of the udw_operands is vital. */ | |
3448 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3449 | } | |
3450 | inst_env->slot_needed = 0; | |
3451 | inst_env->prefix_found = 0; | |
3452 | inst_env->xflag_found = 0; | |
3453 | inst_env->disable_interrupt = 0; | |
3454 | } | |
3455 | ||
3456 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3457 | OR instructions. Note that for this to work as expected, the calling | |
3458 | function must have made sure that there is a prefix to this instruction. */ | |
3459 | ||
a78f21af | 3460 | static void |
29134980 OF |
3461 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
3462 | inst_env_type *inst_env) | |
3463 | { | |
3464 | unsigned long operand2; | |
3465 | unsigned long operand3; | |
3466 | ||
3467 | if (cris_get_operand1 (inst) == REG_PC) | |
3468 | { | |
3469 | /* The PC will be changed by the instruction. */ | |
3470 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3471 | ||
3472 | /* Get the value of the third operand. */ | |
3473 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3474 | ||
3475 | /* Calculate the PC value after the instruction, i.e. where the | |
3476 | breakpoint should be. */ | |
3477 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3478 | } | |
3479 | inst_env->slot_needed = 0; | |
3480 | inst_env->prefix_found = 0; | |
3481 | inst_env->xflag_found = 0; | |
3482 | inst_env->disable_interrupt = 0; | |
3483 | } | |
3484 | ||
3485 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3486 | instructions. The MOVE instruction is the move from source to register. */ | |
3487 | ||
a78f21af | 3488 | static void |
29134980 OF |
3489 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
3490 | inst_env_type *inst_env) | |
3491 | { | |
3492 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3493 | { | |
3494 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3495 | SUB, AND or OR something weird is going on (if everything works these | |
3496 | instructions should end up in the three operand version). */ | |
3497 | inst_env->invalid = 1; | |
3498 | return; | |
3499 | } | |
3500 | else | |
3501 | { | |
3502 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3503 | so use it. */ | |
3504 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3505 | } | |
3506 | inst_env->slot_needed = 0; | |
3507 | inst_env->prefix_found = 0; | |
3508 | inst_env->xflag_found = 0; | |
3509 | inst_env->disable_interrupt = 0; | |
3510 | } | |
3511 | ||
3512 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3513 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3514 | source to register. */ | |
3515 | ||
a78f21af | 3516 | static void |
29134980 OF |
3517 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
3518 | inst_env_type *inst_env) | |
3519 | { | |
3520 | unsigned long operand1; | |
3521 | unsigned long operand2; | |
3522 | unsigned long operand3; | |
3523 | int size; | |
3524 | ||
3525 | /* The instruction is either an indirect or autoincrement addressing mode. | |
3526 | Check if the destination register is the PC. */ | |
3527 | if (cris_get_operand2 (inst) == REG_PC) | |
3528 | { | |
3529 | /* Must be done here, get_data_from_address may change the size | |
3530 | field. */ | |
3531 | size = cris_get_size (inst); | |
3532 | operand2 = inst_env->reg[REG_PC]; | |
3533 | ||
3534 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3535 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
3536 | operand3 = get_data_from_address (&inst, operand1); | |
3537 | ||
3538 | /* Calculate the PC value after the instruction, i.e. where the | |
3539 | breakpoint should be. The order of the udw_operands is vital. */ | |
3540 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3541 | } | |
3542 | /* If this is an autoincrement addressing mode, check if the increment | |
3543 | changes the PC. */ | |
3544 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3545 | { | |
3546 | /* Get the size field. */ | |
3547 | size = cris_get_size (inst); | |
3548 | ||
3549 | /* If it's an extend instruction we don't want the signed extend bit, | |
3550 | because it influences the size. */ | |
3551 | if (cris_get_opcode (inst) < 4) | |
3552 | { | |
3553 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3554 | } | |
3555 | process_autoincrement (size, inst, inst_env); | |
3556 | } | |
3557 | inst_env->slot_needed = 0; | |
3558 | inst_env->prefix_found = 0; | |
3559 | inst_env->xflag_found = 0; | |
3560 | inst_env->disable_interrupt = 0; | |
3561 | } | |
3562 | ||
3563 | /* Handles the two-operand addressing mode, all modes except register, for | |
3564 | the ADD, SUB CMP, AND and OR instruction. */ | |
3565 | ||
a78f21af | 3566 | static void |
29134980 OF |
3567 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3568 | inst_env_type *inst_env) | |
3569 | { | |
3570 | if (inst_env->prefix_found) | |
3571 | { | |
3572 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3573 | { | |
3574 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3575 | } | |
3576 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3577 | { | |
3578 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3579 | } | |
3580 | else | |
3581 | { | |
3582 | /* The mode is invalid for a prefixed base instruction. */ | |
3583 | inst_env->invalid = 1; | |
3584 | return; | |
3585 | } | |
3586 | } | |
3587 | else | |
3588 | { | |
3589 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3590 | } | |
3591 | } | |
3592 | ||
3593 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3594 | ||
a78f21af | 3595 | static void |
29134980 OF |
3596 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3597 | { | |
3598 | unsigned long operand1; | |
3599 | unsigned long operand2; | |
3600 | ||
3601 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3602 | instruction and can't have a prefix. */ | |
3603 | if (inst_env->prefix_found) | |
3604 | { | |
3605 | inst_env->invalid = 1; | |
3606 | return; | |
3607 | } | |
3608 | ||
3609 | /* Check if the instruction has PC as its target. */ | |
3610 | if (cris_get_operand2 (inst) == REG_PC) | |
3611 | { | |
3612 | if (inst_env->slot_needed) | |
3613 | { | |
3614 | inst_env->invalid = 1; | |
3615 | return; | |
3616 | } | |
3617 | operand1 = cris_get_quick_value (inst); | |
3618 | operand2 = inst_env->reg[REG_PC]; | |
3619 | ||
3620 | /* The size should now be dword. */ | |
3621 | cris_set_size_to_dword (&inst); | |
3622 | ||
3623 | /* Calculate the PC value after the instruction, i.e. where the | |
3624 | breakpoint should be. */ | |
3625 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3626 | } | |
3627 | inst_env->slot_needed = 0; | |
3628 | inst_env->prefix_found = 0; | |
3629 | inst_env->xflag_found = 0; | |
3630 | inst_env->disable_interrupt = 0; | |
3631 | } | |
3632 | ||
3633 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3634 | ||
a78f21af | 3635 | static void |
29134980 OF |
3636 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3637 | { | |
3638 | unsigned long operand1; | |
3639 | unsigned long operand2; | |
3640 | ||
3641 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3642 | instruction and can't have a prefix. */ | |
3643 | if (inst_env->prefix_found) | |
3644 | { | |
3645 | inst_env->invalid = 1; | |
3646 | return; | |
3647 | } | |
3648 | /* Check if the instruction has PC as its target. */ | |
3649 | if (cris_get_operand2 (inst) == REG_PC) | |
3650 | { | |
3651 | if (inst_env->slot_needed) | |
3652 | { | |
3653 | inst_env->invalid = 1; | |
3654 | return; | |
3655 | } | |
3656 | /* The instruction has the PC as its target register. */ | |
3657 | operand1 = cris_get_quick_value (inst); | |
3658 | operand2 = inst_env->reg[REG_PC]; | |
3659 | ||
3660 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3661 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3662 | { | |
3663 | /* sign extend */ | |
3664 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3665 | } | |
3666 | /* The size should now be dword. */ | |
3667 | cris_set_size_to_dword (&inst); | |
3668 | ||
3669 | /* Calculate the PC value after the instruction, i.e. where the | |
3670 | breakpoint should be. */ | |
3671 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3672 | } | |
3673 | inst_env->slot_needed = 0; | |
3674 | inst_env->prefix_found = 0; | |
3675 | inst_env->xflag_found = 0; | |
3676 | inst_env->disable_interrupt = 0; | |
3677 | } | |
3678 | ||
3679 | /* Translate op_type to a function and call it. */ | |
3680 | ||
a78f21af AC |
3681 | static void |
3682 | cris_gdb_func (enum cris_op_type op_type, unsigned short inst, | |
3683 | inst_env_type *inst_env) | |
29134980 OF |
3684 | { |
3685 | switch (op_type) | |
3686 | { | |
3687 | case cris_not_implemented_op: | |
3688 | not_implemented_op (inst, inst_env); | |
3689 | break; | |
3690 | ||
3691 | case cris_abs_op: | |
3692 | abs_op (inst, inst_env); | |
3693 | break; | |
3694 | ||
3695 | case cris_addi_op: | |
3696 | addi_op (inst, inst_env); | |
3697 | break; | |
3698 | ||
3699 | case cris_asr_op: | |
3700 | asr_op (inst, inst_env); | |
3701 | break; | |
3702 | ||
3703 | case cris_asrq_op: | |
3704 | asrq_op (inst, inst_env); | |
3705 | break; | |
3706 | ||
3707 | case cris_ax_ei_setf_op: | |
3708 | ax_ei_setf_op (inst, inst_env); | |
3709 | break; | |
3710 | ||
3711 | case cris_bdap_prefix: | |
3712 | bdap_prefix (inst, inst_env); | |
3713 | break; | |
3714 | ||
3715 | case cris_biap_prefix: | |
3716 | biap_prefix (inst, inst_env); | |
3717 | break; | |
3718 | ||
3719 | case cris_break_op: | |
3720 | break_op (inst, inst_env); | |
3721 | break; | |
3722 | ||
3723 | case cris_btst_nop_op: | |
3724 | btst_nop_op (inst, inst_env); | |
3725 | break; | |
3726 | ||
3727 | case cris_clearf_di_op: | |
3728 | clearf_di_op (inst, inst_env); | |
3729 | break; | |
3730 | ||
3731 | case cris_dip_prefix: | |
3732 | dip_prefix (inst, inst_env); | |
3733 | break; | |
3734 | ||
3735 | case cris_dstep_logshift_mstep_neg_not_op: | |
3736 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3737 | break; | |
3738 | ||
3739 | case cris_eight_bit_offset_branch_op: | |
3740 | eight_bit_offset_branch_op (inst, inst_env); | |
3741 | break; | |
3742 | ||
3743 | case cris_move_mem_to_reg_movem_op: | |
3744 | move_mem_to_reg_movem_op (inst, inst_env); | |
3745 | break; | |
3746 | ||
3747 | case cris_move_reg_to_mem_movem_op: | |
3748 | move_reg_to_mem_movem_op (inst, inst_env); | |
3749 | break; | |
3750 | ||
3751 | case cris_move_to_preg_op: | |
3752 | move_to_preg_op (inst, inst_env); | |
3753 | break; | |
3754 | ||
3755 | case cris_muls_op: | |
3756 | muls_op (inst, inst_env); | |
3757 | break; | |
3758 | ||
3759 | case cris_mulu_op: | |
3760 | mulu_op (inst, inst_env); | |
3761 | break; | |
3762 | ||
3763 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3764 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3765 | break; | |
3766 | ||
3767 | case cris_none_reg_mode_clear_test_op: | |
3768 | none_reg_mode_clear_test_op (inst, inst_env); | |
3769 | break; | |
3770 | ||
3771 | case cris_none_reg_mode_jump_op: | |
3772 | none_reg_mode_jump_op (inst, inst_env); | |
3773 | break; | |
3774 | ||
3775 | case cris_none_reg_mode_move_from_preg_op: | |
3776 | none_reg_mode_move_from_preg_op (inst, inst_env); | |
3777 | break; | |
3778 | ||
3779 | case cris_quick_mode_add_sub_op: | |
3780 | quick_mode_add_sub_op (inst, inst_env); | |
3781 | break; | |
3782 | ||
3783 | case cris_quick_mode_and_cmp_move_or_op: | |
3784 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3785 | break; | |
3786 | ||
3787 | case cris_quick_mode_bdap_prefix: | |
3788 | quick_mode_bdap_prefix (inst, inst_env); | |
3789 | break; | |
3790 | ||
3791 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3792 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3793 | break; | |
3794 | ||
3795 | case cris_reg_mode_clear_op: | |
3796 | reg_mode_clear_op (inst, inst_env); | |
3797 | break; | |
3798 | ||
3799 | case cris_reg_mode_jump_op: | |
3800 | reg_mode_jump_op (inst, inst_env); | |
3801 | break; | |
3802 | ||
3803 | case cris_reg_mode_move_from_preg_op: | |
3804 | reg_mode_move_from_preg_op (inst, inst_env); | |
3805 | break; | |
3806 | ||
3807 | case cris_reg_mode_test_op: | |
3808 | reg_mode_test_op (inst, inst_env); | |
3809 | break; | |
3810 | ||
3811 | case cris_scc_op: | |
3812 | scc_op (inst, inst_env); | |
3813 | break; | |
3814 | ||
3815 | case cris_sixteen_bit_offset_branch_op: | |
3816 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3817 | break; | |
3818 | ||
3819 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3820 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3821 | break; | |
3822 | ||
3823 | case cris_three_operand_bound_op: | |
3824 | three_operand_bound_op (inst, inst_env); | |
3825 | break; | |
3826 | ||
3827 | case cris_two_operand_bound_op: | |
3828 | two_operand_bound_op (inst, inst_env); | |
3829 | break; | |
3830 | ||
3831 | case cris_xor_op: | |
3832 | xor_op (inst, inst_env); | |
3833 | break; | |
3834 | } | |
3835 | } | |
3836 | ||
3837 | /* This wrapper is to avoid cris_get_assembler being called before | |
3838 | exec_bfd has been set. */ | |
3839 | ||
3840 | static int | |
a89aa300 | 3841 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
29134980 | 3842 | { |
a89aa300 | 3843 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
36482093 AC |
3844 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
3845 | disassembler, even when there is no BFD. Does something like | |
3846 | "gdb; target remote; disassmeble *0x123" work? */ | |
3847 | gdb_assert (exec_bfd != NULL); | |
a5f6c8f5 | 3848 | print_insn = cris_get_disassembler (exec_bfd); |
36482093 AC |
3849 | gdb_assert (print_insn != NULL); |
3850 | return print_insn (addr, info); | |
29134980 OF |
3851 | } |
3852 | ||
dbbff683 OF |
3853 | /* Copied from <asm/elf.h>. */ |
3854 | typedef unsigned long elf_greg_t; | |
3855 | ||
3856 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
c600d464 OF |
3857 | #define CRISV10_ELF_NGREG 35 |
3858 | typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG]; | |
3859 | ||
3860 | #define CRISV32_ELF_NGREG 32 | |
3861 | typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; | |
dbbff683 OF |
3862 | |
3863 | /* Unpack an elf_gregset_t into GDB's register cache. */ | |
3864 | ||
a78f21af | 3865 | static void |
c6b4e5a2 | 3866 | cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp) |
dbbff683 | 3867 | { |
c600d464 | 3868 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
dbbff683 OF |
3869 | int i; |
3870 | elf_greg_t *regp = *gregsetp; | |
3871 | static char zerobuf[4] = {0}; | |
3872 | ||
3873 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3874 | knows about the actual size of each register so that's no problem. */ | |
3875 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3876 | { | |
c6b4e5a2 | 3877 | regcache_raw_supply (regcache, i, (char *)®p[i]); |
dbbff683 | 3878 | } |
c600d464 OF |
3879 | |
3880 | if (tdep->cris_version == 32) | |
3881 | { | |
3882 | /* Needed to set pseudo-register PC for CRISv32. */ | |
3883 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
3884 | be wrong. Issue a warning to alert the user. */ | |
c6b4e5a2 | 3885 | regcache_raw_supply (regcache, PC_REGNUM, |
c600d464 OF |
3886 | (char *)®p[ERP_REGNUM]); |
3887 | ||
3888 | if (*(char *)®p[ERP_REGNUM] & 0x1) | |
3889 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); | |
3890 | } | |
dbbff683 OF |
3891 | } |
3892 | ||
3893 | /* Use a local version of this function to get the correct types for | |
3894 | regsets, until multi-arch core support is ready. */ | |
3895 | ||
3896 | static void | |
9eefc95f UW |
3897 | fetch_core_registers (struct regcache *regcache, |
3898 | char *core_reg_sect, unsigned core_reg_size, | |
dbbff683 OF |
3899 | int which, CORE_ADDR reg_addr) |
3900 | { | |
3901 | elf_gregset_t gregset; | |
3902 | ||
3903 | switch (which) | |
3904 | { | |
3905 | case 0: | |
c600d464 OF |
3906 | if (core_reg_size != sizeof (elf_gregset_t) |
3907 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) | |
dbbff683 | 3908 | { |
8a3fe4f8 | 3909 | warning (_("wrong size gregset struct in core file")); |
dbbff683 OF |
3910 | } |
3911 | else | |
3912 | { | |
3913 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
9eefc95f | 3914 | cris_supply_gregset (regcache, &gregset); |
dbbff683 OF |
3915 | } |
3916 | ||
3917 | default: | |
3918 | /* We've covered all the kinds of registers we know about here, | |
3919 | so this must be something we wouldn't know what to do with | |
3920 | anyway. Just ignore it. */ | |
3921 | break; | |
3922 | } | |
3923 | } | |
3924 | ||
3925 | static struct core_fns cris_elf_core_fns = | |
3926 | { | |
3927 | bfd_target_elf_flavour, /* core_flavour */ | |
3928 | default_check_format, /* check_format */ | |
3929 | default_core_sniffer, /* core_sniffer */ | |
3930 | fetch_core_registers, /* core_read_registers */ | |
3931 | NULL /* next */ | |
3932 | }; | |
3933 | ||
a78f21af AC |
3934 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
3935 | ||
29134980 OF |
3936 | void |
3937 | _initialize_cris_tdep (void) | |
3938 | { | |
a5f6c8f5 OF |
3939 | static struct cmd_list_element *cris_set_cmdlist; |
3940 | static struct cmd_list_element *cris_show_cmdlist; | |
3941 | ||
29134980 OF |
3942 | struct cmd_list_element *c; |
3943 | ||
3944 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3945 | ||
29134980 | 3946 | /* CRIS-specific user-commands. */ |
a5f6c8f5 OF |
3947 | add_setshow_uinteger_cmd ("cris-version", class_support, |
3948 | &usr_cmd_cris_version, | |
7915a72c AC |
3949 | _("Set the current CRIS version."), |
3950 | _("Show the current CRIS version."), | |
bdd56253 OF |
3951 | _("\ |
3952 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ | |
3953 | Defaults to 10. "), | |
2c5b56ce | 3954 | set_cris_version, |
7915a72c | 3955 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ |
a5f6c8f5 | 3956 | &setlist, &showlist); |
0e6bdb31 OF |
3957 | |
3958 | add_setshow_enum_cmd ("cris-mode", class_support, | |
3959 | cris_modes, &usr_cmd_cris_mode, | |
3960 | _("Set the current CRIS mode."), | |
3961 | _("Show the current CRIS mode."), | |
bdd56253 OF |
3962 | _("\ |
3963 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ | |
3964 | Makes GDB use the NRP register instead of the ERP register in certain cases."), | |
0e6bdb31 OF |
3965 | set_cris_mode, |
3966 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ | |
3967 | &setlist, &showlist); | |
dbbff683 | 3968 | |
a5f6c8f5 OF |
3969 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
3970 | &usr_cmd_cris_dwarf2_cfi, | |
7915a72c AC |
3971 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
3972 | _("Show the usage of Dwarf-2 CFI for CRIS."), | |
bdd56253 | 3973 | _("Set this to \"off\" if using gcc-cris < R59."), |
2c5b56ce | 3974 | set_cris_dwarf2_cfi, |
7915a72c | 3975 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */ |
a5f6c8f5 OF |
3976 | &setlist, &showlist); |
3977 | ||
52bd1401 | 3978 | deprecated_add_core_fns (&cris_elf_core_fns); |
29134980 OF |
3979 | } |
3980 | ||
3981 | /* Prints out all target specific values. */ | |
3982 | ||
3983 | static void | |
3984 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3985 | { | |
3986 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3987 | if (tdep != NULL) | |
3988 | { | |
3989 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
3990 | tdep->cris_version); | |
0e6bdb31 OF |
3991 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
3992 | tdep->cris_mode); | |
a5f6c8f5 OF |
3993 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
3994 | tdep->cris_dwarf2_cfi); | |
29134980 OF |
3995 | } |
3996 | } | |
3997 | ||
3998 | static void | |
a5f6c8f5 OF |
3999 | set_cris_version (char *ignore_args, int from_tty, |
4000 | struct cmd_list_element *c) | |
29134980 OF |
4001 | { |
4002 | struct gdbarch_info info; | |
4003 | ||
a5f6c8f5 | 4004 | usr_cmd_cris_version_valid = 1; |
29134980 | 4005 | |
a5f6c8f5 OF |
4006 | /* Update the current architecture, if needed. */ |
4007 | gdbarch_info_init (&info); | |
4008 | if (!gdbarch_update_p (info)) | |
4009 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4010 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4011 | } |
4012 | ||
0e6bdb31 OF |
4013 | static void |
4014 | set_cris_mode (char *ignore_args, int from_tty, | |
4015 | struct cmd_list_element *c) | |
4016 | { | |
4017 | struct gdbarch_info info; | |
4018 | ||
4019 | /* Update the current architecture, if needed. */ | |
4020 | gdbarch_info_init (&info); | |
4021 | if (!gdbarch_update_p (info)) | |
4022 | internal_error (__FILE__, __LINE__, | |
4023 | "cris_gdbarch_update: failed to update architecture."); | |
4024 | } | |
4025 | ||
29134980 | 4026 | static void |
a5f6c8f5 OF |
4027 | set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
4028 | struct cmd_list_element *c) | |
29134980 OF |
4029 | { |
4030 | struct gdbarch_info info; | |
a5f6c8f5 OF |
4031 | |
4032 | /* Update the current architecture, if needed. */ | |
4033 | gdbarch_info_init (&info); | |
4034 | if (!gdbarch_update_p (info)) | |
4035 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4036 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4037 | } |
4038 | ||
29134980 OF |
4039 | static struct gdbarch * |
4040 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
4041 | { | |
4042 | struct gdbarch *gdbarch; | |
4043 | struct gdbarch_tdep *tdep; | |
4044 | int cris_version; | |
29134980 OF |
4045 | |
4046 | if (usr_cmd_cris_version_valid) | |
4047 | { | |
4048 | /* Trust the user's CRIS version setting. */ | |
4049 | cris_version = usr_cmd_cris_version; | |
4050 | } | |
c600d464 OF |
4051 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
4052 | { | |
4053 | cris_version = 32; | |
4054 | } | |
29134980 OF |
4055 | else |
4056 | { | |
4057 | /* Assume it's CRIS version 10. */ | |
4058 | cris_version = 10; | |
4059 | } | |
4060 | ||
29134980 OF |
4061 | /* Make the current settings visible to the user. */ |
4062 | usr_cmd_cris_version = cris_version; | |
29134980 | 4063 | |
0e6bdb31 | 4064 | /* Find a candidate among the list of pre-declared architectures. */ |
29134980 OF |
4065 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
4066 | arches != NULL; | |
4067 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4068 | { | |
a5f6c8f5 OF |
4069 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
4070 | == usr_cmd_cris_version) | |
0e6bdb31 OF |
4071 | && (gdbarch_tdep (arches->gdbarch)->cris_mode |
4072 | == usr_cmd_cris_mode) | |
a5f6c8f5 OF |
4073 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi |
4074 | == usr_cmd_cris_dwarf2_cfi)) | |
29134980 OF |
4075 | return arches->gdbarch; |
4076 | } | |
4077 | ||
4078 | /* No matching architecture was found. Create a new one. */ | |
4079 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4080 | gdbarch = gdbarch_alloc (&info, tdep); | |
4081 | ||
a5f6c8f5 | 4082 | tdep->cris_version = usr_cmd_cris_version; |
0e6bdb31 | 4083 | tdep->cris_mode = usr_cmd_cris_mode; |
a5f6c8f5 | 4084 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
29134980 OF |
4085 | |
4086 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
4087 | switch (info.byte_order) | |
4088 | { | |
778eb05e | 4089 | case BFD_ENDIAN_LITTLE: |
29134980 OF |
4090 | /* Ok. */ |
4091 | break; | |
4092 | ||
d7449b42 | 4093 | case BFD_ENDIAN_BIG: |
e2e0b3e5 | 4094 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info")); |
29134980 OF |
4095 | break; |
4096 | ||
4097 | default: | |
e2e0b3e5 | 4098 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info")); |
29134980 OF |
4099 | } |
4100 | ||
b4206d25 | 4101 | set_gdbarch_return_value (gdbarch, cris_return_value); |
2e4b5889 OF |
4102 | set_gdbarch_deprecated_reg_struct_has_addr (gdbarch, |
4103 | cris_reg_struct_has_addr); | |
b5622e8d | 4104 | set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); |
29134980 | 4105 | |
29134980 | 4106 | set_gdbarch_sp_regnum (gdbarch, 14); |
c600d464 OF |
4107 | |
4108 | /* Length of ordinary registers used in push_word and a few other | |
4109 | places. register_size() is the real way to know how big a | |
4110 | register is. */ | |
a5f6c8f5 | 4111 | |
2e4b5889 | 4112 | set_gdbarch_double_bit (gdbarch, 64); |
ea06eb3d | 4113 | /* The default definition of a long double is 2 * gdbarch_double_bit, |
2e4b5889 | 4114 | which means we have to set this explicitly. */ |
c600d464 | 4115 | set_gdbarch_long_double_bit (gdbarch, 64); |
29134980 | 4116 | |
29134980 OF |
4117 | /* The total amount of space needed to store (in an array called registers) |
4118 | GDB's copy of the machine's register state. Note: We can not use | |
4119 | cris_register_size at this point, since it relies on current_gdbarch | |
4120 | being set. */ | |
4121 | switch (tdep->cris_version) | |
4122 | { | |
4123 | case 0: | |
4124 | case 1: | |
4125 | case 2: | |
4126 | case 3: | |
29134980 OF |
4127 | case 8: |
4128 | case 9: | |
a5f6c8f5 OF |
4129 | /* Old versions; not supported. */ |
4130 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4131 | _("cris_gdbarch_init: unsupported CRIS version")); |
29134980 OF |
4132 | break; |
4133 | ||
4134 | case 10: | |
4135 | case 11: | |
4136 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
4137 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
c600d464 OF |
4138 | set_gdbarch_pc_regnum (gdbarch, 15); |
4139 | set_gdbarch_register_type (gdbarch, cris_register_type); | |
4140 | /* There are 32 registers (some of which may not be implemented). */ | |
4141 | set_gdbarch_num_regs (gdbarch, 32); | |
4142 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
4143 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
4144 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
4145 | ||
4146 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
4147 | break; | |
4148 | ||
4149 | case 32: | |
4150 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers | |
4151 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) | |
4152 | and pseudo-register PC (32 bits). */ | |
4153 | set_gdbarch_pc_regnum (gdbarch, 32); | |
4154 | set_gdbarch_register_type (gdbarch, crisv32_register_type); | |
4155 | /* 32 registers + pseudo-register PC + 16 support registers. */ | |
4156 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); | |
4157 | set_gdbarch_register_name (gdbarch, crisv32_register_name); | |
4158 | ||
4159 | set_gdbarch_cannot_store_register | |
4160 | (gdbarch, crisv32_cannot_store_register); | |
4161 | set_gdbarch_cannot_fetch_register | |
4162 | (gdbarch, crisv32_cannot_fetch_register); | |
4163 | ||
4164 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
4165 | ||
4166 | set_gdbarch_single_step_through_delay | |
4167 | (gdbarch, crisv32_single_step_through_delay); | |
4168 | ||
29134980 OF |
4169 | break; |
4170 | ||
4171 | default: | |
c600d464 | 4172 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 4173 | _("cris_gdbarch_init: unknown CRIS version")); |
29134980 OF |
4174 | } |
4175 | ||
c600d464 OF |
4176 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
4177 | have the same ABI). */ | |
2e4b5889 OF |
4178 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
4179 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
4180 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 4181 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
4182 | |
4183 | /* The stack grows downward. */ | |
4184 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4185 | ||
4186 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
4187 | ||
2e4b5889 OF |
4188 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
4189 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); | |
4190 | set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id); | |
4191 | ||
a5f6c8f5 OF |
4192 | if (tdep->cris_dwarf2_cfi == 1) |
4193 | { | |
4194 | /* Hook in the Dwarf-2 frame sniffer. */ | |
4195 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); | |
4196 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); | |
4197 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
4198 | } | |
4199 | ||
0e6bdb31 OF |
4200 | if (tdep->cris_mode != cris_mode_guru) |
4201 | { | |
4202 | frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer); | |
4203 | } | |
a5f6c8f5 | 4204 | |
2e4b5889 OF |
4205 | frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer); |
4206 | frame_base_set_default (gdbarch, &cris_frame_base); | |
6c0e89ed | 4207 | |
76a9d10f MK |
4208 | set_solib_svr4_fetch_link_map_offsets |
4209 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
dbbff683 | 4210 | |
36482093 AC |
4211 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
4212 | disassembler, even when there is no BFD. Does something like | |
4213 | "gdb; target remote; disassmeble *0x123" work? */ | |
4214 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); | |
4215 | ||
29134980 OF |
4216 | return gdbarch; |
4217 | } |