Commit | Line | Data |
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29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 | 2 | |
0fd88904 AC |
3 | Copyright 2001, 2002, 2003, 2004, 2005 Free Software Foundation, |
4 | Inc. | |
6b4d5c91 | 5 | |
29134980 OF |
6 | Contributed by Axis Communications AB. |
7 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
8 | ||
9 | This file is part of GDB. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
2e4b5889 OF |
27 | #include "frame-unwind.h" |
28 | #include "frame-base.h" | |
29 | #include "trad-frame.h" | |
30 | #include "dwarf2-frame.h" | |
29134980 OF |
31 | #include "symtab.h" |
32 | #include "inferior.h" | |
33 | #include "gdbtypes.h" | |
34 | #include "gdbcore.h" | |
35 | #include "gdbcmd.h" | |
36 | #include "target.h" | |
37 | #include "value.h" | |
38 | #include "opcode/cris.h" | |
39 | #include "arch-utils.h" | |
40 | #include "regcache.h" | |
36482093 | 41 | #include "gdb_assert.h" |
29134980 OF |
42 | |
43 | /* To get entry_point_address. */ | |
9ab9195f | 44 | #include "objfiles.h" |
29134980 | 45 | |
a5f6c8f5 | 46 | #include "solib.h" /* Support for shared libraries. */ |
dbbff683 | 47 | #include "solib-svr4.h" /* For struct link_map_offsets. */ |
9bbe19fb | 48 | #include "gdb_string.h" |
a89aa300 | 49 | #include "dis-asm.h" |
dbbff683 | 50 | |
29134980 OF |
51 | enum cris_num_regs |
52 | { | |
53 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
54 | NUM_FREGS = 0, | |
55 | ||
56 | /* There are 16 general registers. */ | |
57 | NUM_GENREGS = 16, | |
58 | ||
59 | /* There are 16 special registers. */ | |
c600d464 OF |
60 | NUM_SPECREGS = 16, |
61 | ||
62 | /* CRISv32 has a pseudo PC register, not noted here. */ | |
63 | ||
64 | /* CRISv32 has 16 support registers. */ | |
65 | NUM_SUPPREGS = 16 | |
29134980 OF |
66 | }; |
67 | ||
68 | /* Register numbers of various important registers. | |
2e4b5889 | 69 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
70 | STR_REGNUM Contains the address of structure return values. |
71 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
72 | ARG1_REGNUM Contains the first parameter to a function. | |
73 | ARG2_REGNUM Contains the second parameter to a function. | |
74 | ARG3_REGNUM Contains the third parameter to a function. | |
75 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. | |
76 | SP_REGNUM Contains address of top of stack. | |
77 | PC_REGNUM Contains address of next instruction. | |
78 | SRP_REGNUM Subroutine return pointer register. | |
79 | BRP_REGNUM Breakpoint return pointer register. */ | |
80 | ||
29134980 OF |
81 | enum cris_regnums |
82 | { | |
83 | /* Enums with respect to the general registers, valid for all | |
c600d464 | 84 | CRIS versions. The frame pointer is always in R8. */ |
2e4b5889 | 85 | CRIS_FP_REGNUM = 8, |
c600d464 | 86 | /* ABI related registers. */ |
29134980 OF |
87 | STR_REGNUM = 9, |
88 | RET_REGNUM = 10, | |
89 | ARG1_REGNUM = 10, | |
90 | ARG2_REGNUM = 11, | |
91 | ARG3_REGNUM = 12, | |
92 | ARG4_REGNUM = 13, | |
93 | ||
c600d464 | 94 | /* Registers which happen to be common. */ |
29134980 | 95 | VR_REGNUM = 17, |
c600d464 OF |
96 | MOF_REGNUM = 23, |
97 | SRP_REGNUM = 27, | |
98 | ||
99 | /* CRISv10 et. al. specific registers. */ | |
100 | P0_REGNUM = 16, | |
29134980 OF |
101 | P4_REGNUM = 20, |
102 | CCR_REGNUM = 21, | |
29134980 OF |
103 | P8_REGNUM = 24, |
104 | IBR_REGNUM = 25, | |
105 | IRP_REGNUM = 26, | |
29134980 | 106 | BAR_REGNUM = 28, |
2a9ecef2 | 107 | DCCR_REGNUM = 29, |
29134980 | 108 | BRP_REGNUM = 30, |
c600d464 OF |
109 | USP_REGNUM = 31, |
110 | ||
111 | /* CRISv32 specific registers. */ | |
112 | ACR_REGNUM = 15, | |
113 | BZ_REGNUM = 16, | |
114 | PID_REGNUM = 18, | |
115 | SRS_REGNUM = 19, | |
116 | WZ_REGNUM = 20, | |
117 | EXS_REGNUM = 21, | |
118 | EDA_REGNUM = 22, | |
119 | DZ_REGNUM = 24, | |
120 | EBP_REGNUM = 25, | |
121 | ERP_REGNUM = 26, | |
122 | NRP_REGNUM = 28, | |
123 | CCS_REGNUM = 29, | |
124 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ | |
125 | SPC_REGNUM = 31, | |
126 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ | |
127 | ||
128 | S0_REGNUM = 33, | |
129 | S1_REGNUM = 34, | |
130 | S2_REGNUM = 35, | |
131 | S3_REGNUM = 36, | |
132 | S4_REGNUM = 37, | |
133 | S5_REGNUM = 38, | |
134 | S6_REGNUM = 39, | |
135 | S7_REGNUM = 40, | |
136 | S8_REGNUM = 41, | |
137 | S9_REGNUM = 42, | |
138 | S10_REGNUM = 43, | |
139 | S11_REGNUM = 44, | |
140 | S12_REGNUM = 45, | |
141 | S13_REGNUM = 46, | |
142 | S14_REGNUM = 47, | |
143 | S15_REGNUM = 48, | |
29134980 OF |
144 | }; |
145 | ||
146 | extern const struct cris_spec_reg cris_spec_regs[]; | |
147 | ||
148 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
0e6bdb31 OF |
149 | register names and sizes. */ |
150 | static int usr_cmd_cris_version; | |
29134980 OF |
151 | |
152 | /* Indicates whether to trust the above variable. */ | |
153 | static int usr_cmd_cris_version_valid = 0; | |
154 | ||
41922353 OF |
155 | static const char cris_mode_normal[] = "normal"; |
156 | static const char cris_mode_guru[] = "guru"; | |
0e6bdb31 OF |
157 | static const char *cris_modes[] = { |
158 | cris_mode_normal, | |
159 | cris_mode_guru, | |
160 | 0 | |
161 | }; | |
162 | ||
163 | /* CRIS mode, set via the user command 'set cris-mode'. Affects | |
164 | type of break instruction among other things. */ | |
165 | static const char *usr_cmd_cris_mode = cris_mode_normal; | |
166 | ||
a5f6c8f5 OF |
167 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
168 | static int usr_cmd_cris_dwarf2_cfi = 1; | |
29134980 | 169 | |
29134980 OF |
170 | /* CRIS architecture specific information. */ |
171 | struct gdbarch_tdep | |
172 | { | |
0e6bdb31 OF |
173 | int cris_version; |
174 | const char *cris_mode; | |
a5f6c8f5 | 175 | int cris_dwarf2_cfi; |
29134980 OF |
176 | }; |
177 | ||
178 | /* Functions for accessing target dependent data. */ | |
179 | ||
180 | static int | |
181 | cris_version (void) | |
182 | { | |
183 | return (gdbarch_tdep (current_gdbarch)->cris_version); | |
184 | } | |
185 | ||
0e6bdb31 OF |
186 | static const char * |
187 | cris_mode (void) | |
188 | { | |
189 | return (gdbarch_tdep (current_gdbarch)->cris_mode); | |
190 | } | |
191 | ||
a5f6c8f5 OF |
192 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
193 | ||
194 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ | |
195 | #define SIGTRAMP_OFFSET0 0 | |
196 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ | |
197 | #define SIGTRAMP_OFFSET1 4 | |
198 | ||
199 | static const unsigned short sigtramp_code[] = | |
200 | { | |
201 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ | |
202 | SIGTRAMP_INSN1 /* break 13 */ | |
203 | }; | |
204 | ||
205 | #define SIGTRAMP_LEN (sizeof sigtramp_code) | |
206 | ||
207 | /* Note: same length as normal sigtramp code. */ | |
208 | ||
209 | static const unsigned short rt_sigtramp_code[] = | |
29134980 | 210 | { |
a5f6c8f5 OF |
211 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
212 | SIGTRAMP_INSN1 /* break 13 */ | |
213 | }; | |
214 | ||
215 | /* If PC is in a sigtramp routine, return the address of the start of | |
216 | the routine. Otherwise, return 0. */ | |
217 | ||
218 | static CORE_ADDR | |
219 | cris_sigtramp_start (struct frame_info *next_frame) | |
220 | { | |
221 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
e2a2a3e8 | 222 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 OF |
223 | |
224 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
225 | return 0; | |
226 | ||
e2a2a3e8 | 227 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 228 | { |
e2a2a3e8 | 229 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
230 | return 0; |
231 | ||
232 | pc -= SIGTRAMP_OFFSET1; | |
233 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
234 | return 0; | |
235 | } | |
236 | ||
237 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) | |
238 | return 0; | |
239 | ||
240 | return pc; | |
241 | } | |
242 | ||
243 | /* If PC is in a RT sigtramp routine, return the address of the start of | |
244 | the routine. Otherwise, return 0. */ | |
245 | ||
246 | static CORE_ADDR | |
247 | cris_rt_sigtramp_start (struct frame_info *next_frame) | |
248 | { | |
249 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
e2a2a3e8 | 250 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 OF |
251 | |
252 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
253 | return 0; | |
254 | ||
e2a2a3e8 | 255 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 256 | { |
e2a2a3e8 | 257 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
258 | return 0; |
259 | ||
260 | pc -= SIGTRAMP_OFFSET1; | |
261 | if (!safe_frame_unwind_memory (next_frame, pc, buf, SIGTRAMP_LEN)) | |
262 | return 0; | |
263 | } | |
264 | ||
265 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) | |
266 | return 0; | |
267 | ||
268 | return pc; | |
269 | } | |
270 | ||
271 | /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp | |
272 | routine, return the address of the associated sigcontext structure. */ | |
273 | ||
274 | static CORE_ADDR | |
275 | cris_sigcontext_addr (struct frame_info *next_frame) | |
276 | { | |
277 | CORE_ADDR pc; | |
278 | CORE_ADDR sp; | |
279 | char buf[4]; | |
280 | ||
281 | frame_unwind_register (next_frame, SP_REGNUM, buf); | |
282 | sp = extract_unsigned_integer (buf, 4); | |
283 | ||
284 | /* Look for normal sigtramp frame first. */ | |
285 | pc = cris_sigtramp_start (next_frame); | |
286 | if (pc) | |
287 | { | |
288 | /* struct signal_frame (arch/cris/kernel/signal.c) contains | |
289 | struct sigcontext as its first member, meaning the SP points to | |
290 | it already. */ | |
291 | return sp; | |
292 | } | |
293 | ||
294 | pc = cris_rt_sigtramp_start (next_frame); | |
295 | if (pc) | |
296 | { | |
297 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains | |
298 | a struct ucontext, which in turn contains a struct sigcontext. | |
299 | Magic digging: | |
300 | 4 + 4 + 128 to struct ucontext, then | |
301 | 4 + 4 + 12 to struct sigcontext. */ | |
302 | return (sp + 156); | |
303 | } | |
304 | ||
8a3fe4f8 | 305 | error (_("Couldn't recognize signal trampoline.")); |
a5f6c8f5 | 306 | return 0; |
29134980 OF |
307 | } |
308 | ||
2e4b5889 | 309 | struct cris_unwind_cache |
29134980 | 310 | { |
2e4b5889 OF |
311 | /* The previous frame's inner most stack address. Used as this |
312 | frame ID's stack_addr. */ | |
313 | CORE_ADDR prev_sp; | |
314 | /* The frame's base, optionally used by the high-level debug info. */ | |
315 | CORE_ADDR base; | |
316 | int size; | |
317 | /* How far the SP and r8 (FP) have been offset from the start of | |
318 | the stack frame (as defined by the previous frame's stack | |
319 | pointer). */ | |
320 | LONGEST sp_offset; | |
321 | LONGEST r8_offset; | |
322 | int uses_frame; | |
323 | ||
324 | /* From old frame_extra_info struct. */ | |
29134980 OF |
325 | CORE_ADDR return_pc; |
326 | int leaf_function; | |
2e4b5889 OF |
327 | |
328 | /* Table indicating the location of each and every register. */ | |
329 | struct trad_frame_saved_reg *saved_regs; | |
29134980 OF |
330 | }; |
331 | ||
a5f6c8f5 OF |
332 | static struct cris_unwind_cache * |
333 | cris_sigtramp_frame_unwind_cache (struct frame_info *next_frame, | |
334 | void **this_cache) | |
335 | { | |
336 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
337 | struct cris_unwind_cache *info; | |
338 | CORE_ADDR pc; | |
339 | CORE_ADDR sp; | |
340 | CORE_ADDR addr; | |
341 | char buf[4]; | |
342 | int i; | |
343 | ||
344 | if ((*this_cache)) | |
345 | return (*this_cache); | |
346 | ||
347 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
348 | (*this_cache) = info; | |
349 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
350 | ||
351 | /* Zero all fields. */ | |
352 | info->prev_sp = 0; | |
353 | info->base = 0; | |
354 | info->size = 0; | |
355 | info->sp_offset = 0; | |
356 | info->r8_offset = 0; | |
357 | info->uses_frame = 0; | |
358 | info->return_pc = 0; | |
359 | info->leaf_function = 0; | |
360 | ||
361 | frame_unwind_register (next_frame, SP_REGNUM, buf); | |
362 | info->base = extract_unsigned_integer (buf, 4); | |
363 | ||
364 | addr = cris_sigcontext_addr (next_frame); | |
365 | ||
366 | /* Layout of the sigcontext struct: | |
367 | struct sigcontext { | |
368 | struct pt_regs regs; | |
369 | unsigned long oldmask; | |
370 | unsigned long usp; | |
371 | }; */ | |
372 | ||
c600d464 OF |
373 | if (tdep->cris_version == 10) |
374 | { | |
375 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in | |
376 | struct pt_regs. */ | |
377 | for (i = 0; i <= 13; i++) | |
378 | info->saved_regs[i].addr = addr + ((15 - i) * 4); | |
379 | ||
380 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); | |
381 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); | |
382 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); | |
383 | /* Note: IRP is off by 2 at this point. There's no point in correcting | |
384 | it though since that will mean that the backtrace will show a PC | |
385 | different from what is shown when stopped. */ | |
386 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); | |
387 | info->saved_regs[PC_REGNUM] = info->saved_regs[IRP_REGNUM]; | |
388 | info->saved_regs[SP_REGNUM].addr = addr + (24 * 4); | |
389 | } | |
390 | else | |
391 | { | |
392 | /* CRISv32. */ | |
393 | /* R0 to R13 are stored in order at offset (1 * 4) in | |
394 | struct pt_regs. */ | |
395 | for (i = 0; i <= 13; i++) | |
396 | info->saved_regs[i].addr = addr + ((i + 1) * 4); | |
397 | ||
398 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); | |
399 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); | |
400 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); | |
401 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); | |
402 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); | |
403 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); | |
404 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); | |
405 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); | |
406 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); | |
407 | ||
408 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
409 | be wrong at this point. This problem manifests itself in the | |
410 | sigaltstack.exp test case, which occasionally generates FAILs when | |
411 | the signal is received while in a delay slot. | |
412 | ||
413 | This could be solved by a couple of read_memory_unsigned_integer and a | |
414 | trad_frame_set_value. */ | |
415 | info->saved_regs[PC_REGNUM] = info->saved_regs[ERP_REGNUM]; | |
416 | ||
417 | info->saved_regs[SP_REGNUM].addr = addr + (25 * 4); | |
418 | } | |
a5f6c8f5 OF |
419 | |
420 | return info; | |
421 | } | |
422 | ||
423 | static void | |
424 | cris_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
425 | struct frame_id *this_id) | |
426 | { | |
427 | struct cris_unwind_cache *cache = | |
428 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
429 | (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame)); | |
430 | } | |
431 | ||
432 | /* Forward declaration. */ | |
433 | ||
434 | static void cris_frame_prev_register (struct frame_info *next_frame, | |
435 | void **this_prologue_cache, | |
436 | int regnum, int *optimizedp, | |
437 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 438 | int *realnump, gdb_byte *bufferp); |
a5f6c8f5 OF |
439 | static void |
440 | cris_sigtramp_frame_prev_register (struct frame_info *next_frame, | |
441 | void **this_cache, | |
442 | int regnum, int *optimizedp, | |
443 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 444 | int *realnump, gdb_byte *valuep) |
a5f6c8f5 OF |
445 | { |
446 | /* Make sure we've initialized the cache. */ | |
447 | cris_sigtramp_frame_unwind_cache (next_frame, this_cache); | |
448 | cris_frame_prev_register (next_frame, this_cache, regnum, | |
449 | optimizedp, lvalp, addrp, realnump, valuep); | |
450 | } | |
451 | ||
452 | static const struct frame_unwind cris_sigtramp_frame_unwind = | |
453 | { | |
454 | SIGTRAMP_FRAME, | |
455 | cris_sigtramp_frame_this_id, | |
456 | cris_sigtramp_frame_prev_register | |
457 | }; | |
458 | ||
459 | static const struct frame_unwind * | |
460 | cris_sigtramp_frame_sniffer (struct frame_info *next_frame) | |
461 | { | |
462 | if (cris_sigtramp_start (next_frame) | |
463 | || cris_rt_sigtramp_start (next_frame)) | |
464 | return &cris_sigtramp_frame_unwind; | |
465 | ||
466 | return NULL; | |
467 | } | |
468 | ||
c600d464 OF |
469 | int |
470 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, | |
471 | struct frame_info *this_frame) | |
472 | { | |
473 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
474 | ULONGEST erp; | |
475 | int ret = 0; | |
476 | char buf[4]; | |
477 | ||
0e6bdb31 OF |
478 | if (cris_mode () == cris_mode_guru) |
479 | { | |
480 | frame_unwind_register (this_frame, NRP_REGNUM, buf); | |
481 | } | |
482 | else | |
483 | { | |
484 | frame_unwind_register (this_frame, ERP_REGNUM, buf); | |
485 | } | |
486 | ||
c600d464 OF |
487 | erp = extract_unsigned_integer (buf, 4); |
488 | ||
489 | if (erp & 0x1) | |
490 | { | |
491 | /* In delay slot - check if there's a breakpoint at the preceding | |
492 | instruction. */ | |
493 | if (breakpoint_here_p (erp & ~0x1)) | |
494 | ret = 1; | |
495 | } | |
496 | return ret; | |
497 | } | |
498 | ||
499 | /* Hardware watchpoint support. */ | |
500 | ||
501 | /* We support 6 hardware data watchpoints, but cannot trigger on execute | |
502 | (any combination of read/write is fine). */ | |
503 | ||
504 | int | |
505 | cris_can_use_hardware_watchpoint (int type, int count, int other) | |
506 | { | |
507 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
508 | ||
509 | /* No bookkeeping is done here; it is handled by the remote debug agent. */ | |
510 | ||
511 | if (tdep->cris_version != 32) | |
512 | return 0; | |
513 | else | |
514 | /* CRISv32: Six data watchpoints, one for instructions. */ | |
515 | return (((type == bp_read_watchpoint || type == bp_access_watchpoint | |
516 | || type == bp_hardware_watchpoint) && count <= 6) | |
517 | || (type == bp_hardware_breakpoint && count <= 1)); | |
518 | } | |
519 | ||
520 | /* The CRISv32 hardware data watchpoints work by specifying ranges, | |
521 | which have no alignment or length restrictions. */ | |
522 | ||
523 | int | |
524 | cris_region_ok_for_watchpoint (CORE_ADDR addr, int len) | |
525 | { | |
526 | return 1; | |
527 | } | |
528 | ||
529 | /* If the inferior has some watchpoint that triggered, return the | |
530 | address associated with that watchpoint. Otherwise, return | |
531 | zero. */ | |
532 | ||
533 | CORE_ADDR | |
534 | cris_stopped_data_address (void) | |
535 | { | |
536 | CORE_ADDR eda; | |
537 | eda = read_register (EDA_REGNUM); | |
538 | return eda; | |
539 | } | |
540 | ||
29134980 | 541 | /* The instruction environment needed to find single-step breakpoints. */ |
c600d464 | 542 | |
29134980 OF |
543 | typedef |
544 | struct instruction_environment | |
545 | { | |
546 | unsigned long reg[NUM_GENREGS]; | |
547 | unsigned long preg[NUM_SPECREGS]; | |
548 | unsigned long branch_break_address; | |
549 | unsigned long delay_slot_pc; | |
550 | unsigned long prefix_value; | |
551 | int branch_found; | |
552 | int prefix_found; | |
553 | int invalid; | |
554 | int slot_needed; | |
555 | int delay_slot_pc_active; | |
556 | int xflag_found; | |
557 | int disable_interrupt; | |
558 | } inst_env_type; | |
559 | ||
560 | /* Save old breakpoints in order to restore the state before a single_step. | |
561 | At most, two breakpoints will have to be remembered. */ | |
562 | typedef | |
563 | char binsn_quantum[BREAKPOINT_MAX]; | |
564 | static binsn_quantum break_mem[2]; | |
565 | static CORE_ADDR next_pc = 0; | |
566 | static CORE_ADDR branch_target_address = 0; | |
567 | static unsigned char branch_break_inserted = 0; | |
568 | ||
569 | /* Machine-dependencies in CRIS for opcodes. */ | |
570 | ||
571 | /* Instruction sizes. */ | |
572 | enum cris_instruction_sizes | |
573 | { | |
574 | INST_BYTE_SIZE = 0, | |
575 | INST_WORD_SIZE = 1, | |
576 | INST_DWORD_SIZE = 2 | |
577 | }; | |
578 | ||
579 | /* Addressing modes. */ | |
580 | enum cris_addressing_modes | |
581 | { | |
582 | REGISTER_MODE = 1, | |
583 | INDIRECT_MODE = 2, | |
584 | AUTOINC_MODE = 3 | |
585 | }; | |
586 | ||
587 | /* Prefix addressing modes. */ | |
588 | enum cris_prefix_addressing_modes | |
589 | { | |
590 | PREFIX_INDEX_MODE = 2, | |
591 | PREFIX_ASSIGN_MODE = 3, | |
592 | ||
593 | /* Handle immediate byte offset addressing mode prefix format. */ | |
594 | PREFIX_OFFSET_MODE = 2 | |
595 | }; | |
596 | ||
597 | /* Masks for opcodes. */ | |
598 | enum cris_opcode_masks | |
599 | { | |
600 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
601 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
602 | SIGNED_BYTE_MASK = 0x80, | |
603 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
604 | SIGNED_WORD_MASK = 0x8000, | |
605 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
606 | SIGNED_DWORD_MASK = 0x80000000, | |
607 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
608 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
609 | }; | |
610 | ||
611 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
612 | Bit 15 - 12 Operand2 | |
613 | 11 - 10 Mode | |
614 | 9 - 6 Opcode | |
615 | 5 - 4 Size | |
616 | 3 - 0 Operand1 */ | |
617 | ||
618 | static int | |
619 | cris_get_operand2 (unsigned short insn) | |
620 | { | |
621 | return ((insn & 0xF000) >> 12); | |
622 | } | |
623 | ||
624 | static int | |
625 | cris_get_mode (unsigned short insn) | |
626 | { | |
627 | return ((insn & 0x0C00) >> 10); | |
628 | } | |
629 | ||
630 | static int | |
631 | cris_get_opcode (unsigned short insn) | |
632 | { | |
633 | return ((insn & 0x03C0) >> 6); | |
634 | } | |
635 | ||
636 | static int | |
637 | cris_get_size (unsigned short insn) | |
638 | { | |
639 | return ((insn & 0x0030) >> 4); | |
640 | } | |
641 | ||
642 | static int | |
643 | cris_get_operand1 (unsigned short insn) | |
644 | { | |
645 | return (insn & 0x000F); | |
646 | } | |
647 | ||
648 | /* Additional functions in order to handle opcodes. */ | |
649 | ||
29134980 OF |
650 | static int |
651 | cris_get_quick_value (unsigned short insn) | |
652 | { | |
653 | return (insn & 0x003F); | |
654 | } | |
655 | ||
656 | static int | |
657 | cris_get_bdap_quick_offset (unsigned short insn) | |
658 | { | |
659 | return (insn & 0x00FF); | |
660 | } | |
661 | ||
662 | static int | |
663 | cris_get_branch_short_offset (unsigned short insn) | |
664 | { | |
665 | return (insn & 0x00FF); | |
666 | } | |
667 | ||
668 | static int | |
669 | cris_get_asr_shift_steps (unsigned long value) | |
670 | { | |
671 | return (value & 0x3F); | |
672 | } | |
673 | ||
29134980 OF |
674 | static int |
675 | cris_get_clear_size (unsigned short insn) | |
676 | { | |
677 | return ((insn) & 0xC000); | |
678 | } | |
679 | ||
680 | static int | |
681 | cris_is_signed_extend_bit_on (unsigned short insn) | |
682 | { | |
683 | return (((insn) & 0x20) == 0x20); | |
684 | } | |
685 | ||
686 | static int | |
687 | cris_is_xflag_bit_on (unsigned short insn) | |
688 | { | |
689 | return (((insn) & 0x1000) == 0x1000); | |
690 | } | |
691 | ||
692 | static void | |
693 | cris_set_size_to_dword (unsigned short *insn) | |
694 | { | |
695 | *insn &= 0xFFCF; | |
696 | *insn |= 0x20; | |
697 | } | |
698 | ||
8535cb38 | 699 | static signed char |
29134980 OF |
700 | cris_get_signed_offset (unsigned short insn) |
701 | { | |
8535cb38 | 702 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
703 | } |
704 | ||
705 | /* Calls an op function given the op-type, working on the insn and the | |
706 | inst_env. */ | |
707 | static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); | |
708 | ||
29134980 OF |
709 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
710 | struct gdbarch_list *); | |
711 | ||
29134980 OF |
712 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
713 | ||
a5f6c8f5 OF |
714 | static void set_cris_version (char *ignore_args, int from_tty, |
715 | struct cmd_list_element *c); | |
29134980 | 716 | |
0e6bdb31 OF |
717 | static void set_cris_mode (char *ignore_args, int from_tty, |
718 | struct cmd_list_element *c); | |
719 | ||
a5f6c8f5 OF |
720 | static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
721 | struct cmd_list_element *c); | |
29134980 | 722 | |
2e4b5889 OF |
723 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
724 | struct frame_info *next_frame, | |
725 | struct cris_unwind_cache *info); | |
726 | ||
727 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, | |
728 | struct frame_info *next_frame); | |
729 | ||
730 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, | |
731 | struct frame_info *next_frame); | |
732 | ||
733 | /* When arguments must be pushed onto the stack, they go on in reverse | |
a5f6c8f5 OF |
734 | order. The below implements a FILO (stack) to do this. |
735 | Copied from d10v-tdep.c. */ | |
2e4b5889 OF |
736 | |
737 | struct stack_item | |
738 | { | |
739 | int len; | |
740 | struct stack_item *prev; | |
741 | void *data; | |
742 | }; | |
743 | ||
744 | static struct stack_item * | |
745 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
746 | { | |
747 | struct stack_item *si; | |
748 | si = xmalloc (sizeof (struct stack_item)); | |
749 | si->data = xmalloc (len); | |
750 | si->len = len; | |
751 | si->prev = prev; | |
752 | memcpy (si->data, contents, len); | |
753 | return si; | |
754 | } | |
755 | ||
756 | static struct stack_item * | |
757 | pop_stack_item (struct stack_item *si) | |
758 | { | |
759 | struct stack_item *dead = si; | |
760 | si = si->prev; | |
761 | xfree (dead->data); | |
762 | xfree (dead); | |
763 | return si; | |
764 | } | |
765 | ||
766 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
767 | the saved registers of frame described by FRAME_INFO. This | |
768 | includes special registers such as pc and fp saved in special ways | |
769 | in the stack frame. sp is even more special: the address we return | |
a5f6c8f5 | 770 | for it IS the sp for the next frame. */ |
2e4b5889 OF |
771 | |
772 | struct cris_unwind_cache * | |
773 | cris_frame_unwind_cache (struct frame_info *next_frame, | |
774 | void **this_prologue_cache) | |
775 | { | |
776 | CORE_ADDR pc; | |
777 | struct cris_unwind_cache *info; | |
778 | int i; | |
779 | ||
780 | if ((*this_prologue_cache)) | |
781 | return (*this_prologue_cache); | |
782 | ||
783 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
784 | (*this_prologue_cache) = info; | |
785 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
786 | ||
787 | /* Zero all fields. */ | |
788 | info->prev_sp = 0; | |
789 | info->base = 0; | |
790 | info->size = 0; | |
791 | info->sp_offset = 0; | |
792 | info->r8_offset = 0; | |
793 | info->uses_frame = 0; | |
794 | info->return_pc = 0; | |
795 | info->leaf_function = 0; | |
796 | ||
797 | /* Prologue analysis does the rest... */ | |
798 | cris_scan_prologue (frame_func_unwind (next_frame), next_frame, info); | |
799 | ||
800 | return info; | |
801 | } | |
802 | ||
803 | /* Given a GDB frame, determine the address of the calling function's | |
804 | frame. This will be used to create a new GDB frame struct. */ | |
805 | ||
806 | static void | |
807 | cris_frame_this_id (struct frame_info *next_frame, | |
808 | void **this_prologue_cache, | |
809 | struct frame_id *this_id) | |
810 | { | |
811 | struct cris_unwind_cache *info | |
812 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
813 | CORE_ADDR base; | |
814 | CORE_ADDR func; | |
815 | struct frame_id id; | |
816 | ||
817 | /* The FUNC is easy. */ | |
818 | func = frame_func_unwind (next_frame); | |
819 | ||
820 | /* Hopefully the prologue analysis either correctly determined the | |
821 | frame's base (which is the SP from the previous frame), or set | |
822 | that base to "NULL". */ | |
823 | base = info->prev_sp; | |
824 | if (base == 0) | |
825 | return; | |
826 | ||
827 | id = frame_id_build (base, func); | |
828 | ||
829 | (*this_id) = id; | |
830 | } | |
831 | ||
832 | static void | |
833 | cris_frame_prev_register (struct frame_info *next_frame, | |
834 | void **this_prologue_cache, | |
835 | int regnum, int *optimizedp, | |
836 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
e2a2a3e8 | 837 | int *realnump, gdb_byte *bufferp) |
2e4b5889 OF |
838 | { |
839 | struct cris_unwind_cache *info | |
840 | = cris_frame_unwind_cache (next_frame, this_prologue_cache); | |
1f67027d AC |
841 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
842 | optimizedp, lvalp, addrp, realnump, bufferp); | |
2e4b5889 OF |
843 | } |
844 | ||
845 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
846 | dummy frame. The frame ID's base needs to match the TOS value | |
847 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
848 | breakpoint. */ | |
849 | ||
850 | static struct frame_id | |
851 | cris_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
852 | { | |
853 | return frame_id_build (cris_unwind_sp (gdbarch, next_frame), | |
854 | frame_pc_unwind (next_frame)); | |
855 | } | |
856 | ||
857 | static CORE_ADDR | |
858 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
859 | { | |
860 | /* Align to the size of an instruction (so that they can safely be | |
861 | pushed onto the stack). */ | |
862 | return sp & ~3; | |
863 | } | |
864 | ||
865 | static CORE_ADDR | |
866 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
867 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
868 | struct value **args, int nargs, | |
869 | struct type *value_type, | |
870 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
871 | { | |
872 | /* Allocate space sufficient for a breakpoint. */ | |
873 | sp = (sp - 4) & ~3; | |
874 | /* Store the address of that breakpoint */ | |
875 | *bp_addr = sp; | |
876 | /* CRIS always starts the call at the callee's entry point. */ | |
877 | *real_pc = funaddr; | |
878 | return sp; | |
879 | } | |
880 | ||
881 | static CORE_ADDR | |
7d9b040b | 882 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2e4b5889 OF |
883 | struct regcache *regcache, CORE_ADDR bp_addr, |
884 | int nargs, struct value **args, CORE_ADDR sp, | |
885 | int struct_return, CORE_ADDR struct_addr) | |
886 | { | |
887 | int stack_alloc; | |
888 | int stack_offset; | |
889 | int argreg; | |
890 | int argnum; | |
891 | ||
892 | CORE_ADDR regval; | |
893 | ||
894 | /* The function's arguments and memory allocated by gdb for the arguments to | |
895 | point at reside in separate areas on the stack. | |
896 | Both frame pointers grow toward higher addresses. */ | |
897 | CORE_ADDR fp_arg; | |
898 | CORE_ADDR fp_mem; | |
899 | ||
900 | struct stack_item *si = NULL; | |
901 | ||
a5f6c8f5 | 902 | /* Push the return address. */ |
2e4b5889 OF |
903 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
904 | ||
905 | /* Are we returning a value using a structure return or a normal value | |
906 | return? struct_addr is the address of the reserved space for the return | |
907 | structure to be written on the stack. */ | |
908 | if (struct_return) | |
909 | { | |
910 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
911 | } | |
912 | ||
913 | /* Now load as many as possible of the first arguments into registers, | |
914 | and push the rest onto the stack. */ | |
915 | argreg = ARG1_REGNUM; | |
916 | stack_offset = 0; | |
917 | ||
918 | for (argnum = 0; argnum < nargs; argnum++) | |
919 | { | |
920 | int len; | |
921 | char *val; | |
922 | int reg_demand; | |
923 | int i; | |
924 | ||
4991999e | 925 | len = TYPE_LENGTH (value_type (args[argnum])); |
0fd88904 | 926 | val = (char *) value_contents (args[argnum]); |
2e4b5889 OF |
927 | |
928 | /* How may registers worth of storage do we need for this argument? */ | |
929 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
930 | ||
931 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) | |
932 | { | |
933 | /* Data passed by value. Fits in available register(s). */ | |
934 | for (i = 0; i < reg_demand; i++) | |
935 | { | |
936 | regcache_cooked_write_unsigned (regcache, argreg, | |
937 | *(unsigned long *) val); | |
938 | argreg++; | |
939 | val += 4; | |
940 | } | |
941 | } | |
942 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) | |
943 | { | |
944 | /* Data passed by value. Does not fit in available register(s). | |
945 | Use the register(s) first, then the stack. */ | |
946 | for (i = 0; i < reg_demand; i++) | |
947 | { | |
948 | if (argreg <= ARG4_REGNUM) | |
949 | { | |
950 | regcache_cooked_write_unsigned (regcache, argreg, | |
951 | *(unsigned long *) val); | |
952 | argreg++; | |
953 | val += 4; | |
954 | } | |
955 | else | |
956 | { | |
957 | /* Push item for later so that pushed arguments | |
958 | come in the right order. */ | |
959 | si = push_stack_item (si, val, 4); | |
960 | val += 4; | |
961 | } | |
962 | } | |
963 | } | |
964 | else if (len > (2 * 4)) | |
965 | { | |
966 | /* FIXME */ | |
e2e0b3e5 | 967 | internal_error (__FILE__, __LINE__, _("We don't do this")); |
2e4b5889 OF |
968 | } |
969 | else | |
970 | { | |
971 | /* Data passed by value. No available registers. Put it on | |
972 | the stack. */ | |
973 | si = push_stack_item (si, val, len); | |
974 | } | |
975 | } | |
976 | ||
977 | while (si) | |
978 | { | |
979 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
980 | the function prologue. */ | |
981 | sp = (sp - si->len) & ~3; | |
982 | write_memory (sp, si->data, si->len); | |
983 | si = pop_stack_item (si); | |
984 | } | |
985 | ||
986 | /* Finally, update the SP register. */ | |
987 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
988 | ||
989 | return sp; | |
990 | } | |
991 | ||
e2a2a3e8 OF |
992 | static const struct frame_unwind cris_frame_unwind = |
993 | { | |
2e4b5889 OF |
994 | NORMAL_FRAME, |
995 | cris_frame_this_id, | |
996 | cris_frame_prev_register | |
997 | }; | |
998 | ||
999 | const struct frame_unwind * | |
1000 | cris_frame_sniffer (struct frame_info *next_frame) | |
1001 | { | |
1002 | return &cris_frame_unwind; | |
1003 | } | |
1004 | ||
1005 | static CORE_ADDR | |
1006 | cris_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1007 | { | |
1008 | struct cris_unwind_cache *info | |
1009 | = cris_frame_unwind_cache (next_frame, this_cache); | |
1010 | return info->base; | |
1011 | } | |
1012 | ||
e2a2a3e8 OF |
1013 | static const struct frame_base cris_frame_base = |
1014 | { | |
2e4b5889 OF |
1015 | &cris_frame_unwind, |
1016 | cris_frame_base_address, | |
1017 | cris_frame_base_address, | |
1018 | cris_frame_base_address | |
1019 | }; | |
1020 | ||
29134980 OF |
1021 | /* Frames information. The definition of the struct frame_info is |
1022 | ||
1023 | CORE_ADDR frame | |
1024 | CORE_ADDR pc | |
5a203e44 | 1025 | enum frame_type type; |
29134980 OF |
1026 | CORE_ADDR return_pc |
1027 | int leaf_function | |
1028 | ||
1029 | If the compilation option -fno-omit-frame-pointer is present the | |
1030 | variable frame will be set to the content of R8 which is the frame | |
1031 | pointer register. | |
1032 | ||
1033 | The variable pc contains the address where execution is performed | |
1034 | in the present frame. The innermost frame contains the current content | |
1035 | of the register PC. All other frames contain the content of the | |
1036 | register PC in the next frame. | |
1037 | ||
5a203e44 AC |
1038 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
1039 | (associated with a signal handler), dummy (associated with a dummy | |
1040 | frame). | |
29134980 OF |
1041 | |
1042 | The variable return_pc contains the address where execution should be | |
1043 | resumed when the present frame has finished, the return address. | |
1044 | ||
1045 | The variable leaf_function is 1 if the return address is in the register | |
1046 | SRP, and 0 if it is on the stack. | |
1047 | ||
1048 | Prologue instructions C-code. | |
1049 | The prologue may consist of (-fno-omit-frame-pointer) | |
1050 | 1) 2) | |
1051 | push srp | |
1052 | push r8 push r8 | |
1053 | move.d sp,r8 move.d sp,r8 | |
1054 | subq X,sp subq X,sp | |
1055 | movem rY,[sp] movem rY,[sp] | |
1056 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
1057 | ||
1058 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
1059 | ||
1060 | Note that this assumption is extremely brittle, and will break at the | |
1061 | slightest change in GCC's prologue. | |
1062 | ||
1063 | If local variables are declared or register contents are saved on stack | |
1064 | the subq-instruction will be present with X as the number of bytes | |
1065 | needed for storage. The reshuffle with respect to r8 may be performed | |
1066 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
1067 | The offset U should be representable by a signed 8-bit value in all cases. | |
1068 | Thus, the prefix word is assumed to be immediate byte offset mode followed | |
1069 | by another word containing the instruction. | |
1070 | ||
1071 | Degenerate cases: | |
1072 | 3) | |
1073 | push r8 | |
1074 | move.d sp,r8 | |
1075 | move.d r8,sp | |
1076 | pop r8 | |
1077 | ||
1078 | Prologue instructions C++-code. | |
1079 | Case 1) and 2) in the C-code may be followed by | |
1080 | ||
1081 | move.d r10,rS ; this | |
1082 | move.d r11,rT ; P1 | |
1083 | move.d r12,rU ; P2 | |
1084 | move.d r13,rV ; P3 | |
1085 | move.S [r8+U],rZ ; P4 | |
1086 | ||
1087 | if any of the call parameters are stored. The host expects these | |
1088 | instructions to be executed in order to get the call parameters right. */ | |
1089 | ||
1090 | /* Examine the prologue of a function. The variable ip is the address of | |
1091 | the first instruction of the prologue. The variable limit is the address | |
1092 | of the first instruction after the prologue. The variable fi contains the | |
1093 | information in struct frame_info. The variable frameless_p controls whether | |
1094 | the entire prologue is examined (0) or just enough instructions to | |
1095 | determine that it is a prologue (1). */ | |
1096 | ||
a78f21af | 1097 | static CORE_ADDR |
2e4b5889 OF |
1098 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
1099 | struct cris_unwind_cache *info) | |
29134980 OF |
1100 | { |
1101 | /* Present instruction. */ | |
1102 | unsigned short insn; | |
1103 | ||
1104 | /* Next instruction, lookahead. */ | |
1105 | unsigned short insn_next; | |
1106 | int regno; | |
1107 | ||
1108 | /* Is there a push fp? */ | |
1109 | int have_fp; | |
1110 | ||
1111 | /* Number of byte on stack used for local variables and movem. */ | |
1112 | int val; | |
1113 | ||
1114 | /* Highest register number in a movem. */ | |
1115 | int regsave; | |
1116 | ||
1117 | /* move.d r<source_register>,rS */ | |
1118 | short source_register; | |
1119 | ||
2e4b5889 OF |
1120 | /* Scan limit. */ |
1121 | int limit; | |
29134980 | 1122 | |
2e4b5889 OF |
1123 | /* This frame is with respect to a leaf until a push srp is found. */ |
1124 | if (info) | |
1125 | { | |
1126 | info->leaf_function = 1; | |
1127 | } | |
29134980 OF |
1128 | |
1129 | /* Assume nothing on stack. */ | |
1130 | val = 0; | |
1131 | regsave = -1; | |
1132 | ||
2e4b5889 OF |
1133 | /* If we were called without a next_frame, that means we were called |
1134 | from cris_skip_prologue which already tried to find the end of the | |
1135 | prologue through the symbol information. 64 instructions past current | |
1136 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
1137 | limit = next_frame ? frame_pc_unwind (next_frame) : pc + 64; | |
29134980 | 1138 | |
29134980 | 1139 | /* Find the prologue instructions. */ |
a5f6c8f5 | 1140 | while (pc > 0 && pc < limit) |
29134980 | 1141 | { |
2e4b5889 OF |
1142 | insn = read_memory_unsigned_integer (pc, 2); |
1143 | pc += 2; | |
29134980 OF |
1144 | if (insn == 0xE1FC) |
1145 | { | |
1146 | /* push <reg> 32 bit instruction */ | |
2e4b5889 OF |
1147 | insn_next = read_memory_unsigned_integer (pc, 2); |
1148 | pc += 2; | |
29134980 | 1149 | regno = cris_get_operand2 (insn_next); |
2e4b5889 OF |
1150 | if (info) |
1151 | { | |
1152 | info->sp_offset += 4; | |
1153 | } | |
dbbff683 OF |
1154 | /* This check, meant to recognize srp, used to be regno == |
1155 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
1156 | if (insn_next == 0xBE7E) | |
29134980 | 1157 | { |
2e4b5889 OF |
1158 | if (info) |
1159 | { | |
1160 | info->leaf_function = 0; | |
1161 | } | |
29134980 | 1162 | } |
b4206d25 OF |
1163 | else if (insn_next == 0x8FEE) |
1164 | { | |
1165 | /* push $r8 */ | |
1166 | if (info) | |
1167 | { | |
1168 | info->r8_offset = info->sp_offset; | |
1169 | } | |
1170 | } | |
29134980 OF |
1171 | } |
1172 | else if (insn == 0x866E) | |
1173 | { | |
1174 | /* move.d sp,r8 */ | |
2e4b5889 OF |
1175 | if (info) |
1176 | { | |
1177 | info->uses_frame = 1; | |
2e4b5889 | 1178 | } |
29134980 OF |
1179 | continue; |
1180 | } | |
1181 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
1182 | && cris_get_mode (insn) == 0x0000 | |
1183 | && cris_get_opcode (insn) == 0x000A) | |
1184 | { | |
1185 | /* subq <val>,sp */ | |
2e4b5889 OF |
1186 | if (info) |
1187 | { | |
1188 | info->sp_offset += cris_get_quick_value (insn); | |
1189 | } | |
29134980 OF |
1190 | } |
1191 | else if (cris_get_mode (insn) == 0x0002 | |
1192 | && cris_get_opcode (insn) == 0x000F | |
1193 | && cris_get_size (insn) == 0x0003 | |
1194 | && cris_get_operand1 (insn) == SP_REGNUM) | |
1195 | { | |
1196 | /* movem r<regsave>,[sp] */ | |
29134980 OF |
1197 | regsave = cris_get_operand2 (insn); |
1198 | } | |
1199 | else if (cris_get_operand2 (insn) == SP_REGNUM | |
1200 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1201 | && (cris_get_signed_offset (insn) < 0)) | |
1202 | { | |
1203 | /* Immediate byte offset addressing prefix word with sp as base | |
1204 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
1205 | is between 64 and 128. | |
1206 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
1207 | if (info) |
1208 | { | |
1209 | info->sp_offset += -cris_get_signed_offset (insn); | |
1210 | } | |
1211 | insn_next = read_memory_unsigned_integer (pc, 2); | |
1212 | pc += 2; | |
29134980 OF |
1213 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
1214 | && cris_get_opcode (insn_next) == 0x000F | |
1215 | && cris_get_size (insn_next) == 0x0003 | |
1216 | && cris_get_operand1 (insn_next) == SP_REGNUM) | |
1217 | { | |
29134980 OF |
1218 | regsave = cris_get_operand2 (insn_next); |
1219 | } | |
1220 | else | |
1221 | { | |
1222 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1223 | pc -= 4; |
29134980 OF |
1224 | break; |
1225 | } | |
1226 | } | |
1227 | else if (cris_get_mode (insn) == 0x0001 | |
1228 | && cris_get_opcode (insn) == 0x0009 | |
1229 | && cris_get_size (insn) == 0x0002) | |
1230 | { | |
1231 | /* move.d r<10..13>,r<0..15> */ | |
29134980 | 1232 | source_register = cris_get_operand1 (insn); |
2a9ecef2 OF |
1233 | |
1234 | /* FIXME? In the glibc solibs, the prologue might contain something | |
1235 | like (this example taken from relocate_doit): | |
1236 | move.d $pc,$r0 | |
1237 | sub.d 0xfffef426,$r0 | |
1238 | which isn't covered by the source_register check below. Question | |
1239 | is whether to add a check for this combo, or make better use of | |
1240 | the limit variable instead. */ | |
29134980 OF |
1241 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
1242 | { | |
1243 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1244 | pc -= 2; |
29134980 OF |
1245 | break; |
1246 | } | |
1247 | } | |
2e4b5889 | 1248 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1249 | /* The size is a fixed-size. */ |
1250 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1251 | /* A negative offset. */ | |
1252 | && (cris_get_signed_offset (insn) < 0)) | |
1253 | { | |
1254 | /* move.S rZ,[r8-U] (?) */ | |
2e4b5889 OF |
1255 | insn_next = read_memory_unsigned_integer (pc, 2); |
1256 | pc += 2; | |
29134980 OF |
1257 | regno = cris_get_operand2 (insn_next); |
1258 | if ((regno >= 0 && regno < SP_REGNUM) | |
1259 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1260 | && cris_get_opcode (insn_next) == 0x000F) | |
1261 | { | |
1262 | /* move.S rZ,[r8-U] */ | |
1263 | continue; | |
1264 | } | |
1265 | else | |
1266 | { | |
1267 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1268 | pc -= 4; |
29134980 OF |
1269 | break; |
1270 | } | |
1271 | } | |
2e4b5889 | 1272 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
29134980 OF |
1273 | /* The size is a fixed-size. */ |
1274 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1275 | /* A positive offset. */ | |
1276 | && (cris_get_signed_offset (insn) > 0)) | |
1277 | { | |
1278 | /* move.S [r8+U],rZ (?) */ | |
2e4b5889 OF |
1279 | insn_next = read_memory_unsigned_integer (pc, 2); |
1280 | pc += 2; | |
29134980 OF |
1281 | regno = cris_get_operand2 (insn_next); |
1282 | if ((regno >= 0 && regno < SP_REGNUM) | |
1283 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1284 | && cris_get_opcode (insn_next) == 0x0009 | |
1285 | && cris_get_operand1 (insn_next) == regno) | |
1286 | { | |
1287 | /* move.S [r8+U],rZ */ | |
1288 | continue; | |
1289 | } | |
1290 | else | |
1291 | { | |
1292 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1293 | pc -= 4; |
29134980 OF |
1294 | break; |
1295 | } | |
1296 | } | |
1297 | else | |
1298 | { | |
1299 | /* The prologue ended before the limit was reached. */ | |
2e4b5889 | 1300 | pc -= 2; |
29134980 OF |
1301 | break; |
1302 | } | |
1303 | } | |
29134980 | 1304 | |
2e4b5889 OF |
1305 | /* We only want to know the end of the prologue when next_frame and info |
1306 | are NULL (called from cris_skip_prologue i.e.). */ | |
1307 | if (next_frame == NULL && info == NULL) | |
1308 | { | |
1309 | return pc; | |
1310 | } | |
29134980 | 1311 | |
2e4b5889 OF |
1312 | info->size = info->sp_offset; |
1313 | ||
1314 | /* Compute the previous frame's stack pointer (which is also the | |
1315 | frame's ID's stack address), and this frame's base pointer. */ | |
1316 | if (info->uses_frame) | |
29134980 | 1317 | { |
2e4b5889 OF |
1318 | ULONGEST this_base; |
1319 | /* The SP was moved to the FP. This indicates that a new frame | |
1320 | was created. Get THIS frame's FP value by unwinding it from | |
1321 | the next frame. */ | |
1322 | frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM, | |
1323 | &this_base); | |
1324 | info->base = this_base; | |
b4206d25 OF |
1325 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
1326 | ||
2e4b5889 OF |
1327 | /* The FP points at the last saved register. Adjust the FP back |
1328 | to before the first saved register giving the SP. */ | |
1329 | info->prev_sp = info->base + info->r8_offset; | |
1330 | } | |
1331 | else | |
1332 | { | |
1333 | ULONGEST this_base; | |
1334 | /* Assume that the FP is this frame's SP but with that pushed | |
1335 | stack space added back. */ | |
1336 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &this_base); | |
1337 | info->base = this_base; | |
1338 | info->prev_sp = info->base + info->size; | |
1339 | } | |
29134980 | 1340 | |
2e4b5889 OF |
1341 | /* Calculate the addresses for the saved registers on the stack. */ |
1342 | /* FIXME: The address calculation should really be done on the fly while | |
1343 | we're analyzing the prologue (we only hold one regsave value as it is | |
1344 | now). */ | |
1345 | val = info->sp_offset; | |
1346 | ||
1347 | for (regno = regsave; regno >= 0; regno--) | |
1348 | { | |
1349 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; | |
1350 | val -= 4; | |
1351 | } | |
1352 | ||
1353 | /* The previous frame's SP needed to be computed. Save the computed | |
1354 | value. */ | |
1355 | trad_frame_set_value (info->saved_regs, SP_REGNUM, info->prev_sp); | |
1356 | ||
1357 | if (!info->leaf_function) | |
1358 | { | |
b4206d25 OF |
1359 | /* SRP saved on the stack. But where? */ |
1360 | if (info->r8_offset == 0) | |
1361 | { | |
1362 | /* R8 not pushed yet. */ | |
1363 | info->saved_regs[SRP_REGNUM].addr = info->base; | |
1364 | } | |
1365 | else | |
1366 | { | |
1367 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
1368 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; | |
1369 | } | |
29134980 | 1370 | } |
2e4b5889 OF |
1371 | |
1372 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
1373 | info->saved_regs[PC_REGNUM] = info->saved_regs[SRP_REGNUM]; | |
1374 | ||
1375 | return pc; | |
29134980 OF |
1376 | } |
1377 | ||
1378 | /* Advance pc beyond any function entry prologue instructions at pc | |
1379 | to reach some "real" code. */ | |
1380 | ||
29134980 OF |
1381 | /* Given a PC value corresponding to the start of a function, return the PC |
1382 | of the first instruction after the function prologue. */ | |
1383 | ||
a78f21af | 1384 | static CORE_ADDR |
2e4b5889 | 1385 | cris_skip_prologue (CORE_ADDR pc) |
29134980 | 1386 | { |
2e4b5889 OF |
1387 | CORE_ADDR func_addr, func_end; |
1388 | struct symtab_and_line sal; | |
29134980 OF |
1389 | CORE_ADDR pc_after_prologue; |
1390 | ||
2e4b5889 OF |
1391 | /* If we have line debugging information, then the end of the prologue |
1392 | should the first assembly instruction of the first source line. */ | |
1393 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1394 | { | |
1395 | sal = find_pc_line (func_addr, 0); | |
1396 | if (sal.end > 0 && sal.end < func_end) | |
1397 | return sal.end; | |
1398 | } | |
29134980 | 1399 | |
2e4b5889 | 1400 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); |
29134980 OF |
1401 | return pc_after_prologue; |
1402 | } | |
1403 | ||
2e4b5889 OF |
1404 | static CORE_ADDR |
1405 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1406 | { | |
1407 | ULONGEST pc; | |
1408 | frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc); | |
1409 | return pc; | |
1410 | } | |
1411 | ||
1412 | static CORE_ADDR | |
1413 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1414 | { | |
1415 | ULONGEST sp; | |
1416 | frame_unwind_unsigned_register (next_frame, SP_REGNUM, &sp); | |
1417 | return sp; | |
1418 | } | |
1419 | ||
29134980 OF |
1420 | /* Use the program counter to determine the contents and size of a breakpoint |
1421 | instruction. It returns a pointer to a string of bytes that encode a | |
1422 | breakpoint instruction, stores the length of the string to *lenptr, and | |
1423 | adjusts pcptr (if necessary) to point to the actual memory location where | |
1424 | the breakpoint should be inserted. */ | |
1425 | ||
a78f21af | 1426 | static const unsigned char * |
29134980 OF |
1427 | cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
1428 | { | |
0e6bdb31 OF |
1429 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
1430 | static unsigned char break15_insn[] = {0x3f, 0xe9}; | |
29134980 OF |
1431 | *lenptr = 2; |
1432 | ||
0e6bdb31 OF |
1433 | if (cris_mode () == cris_mode_guru) |
1434 | return break15_insn; | |
1435 | else | |
1436 | return break8_insn; | |
29134980 OF |
1437 | } |
1438 | ||
29134980 OF |
1439 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1440 | 0 otherwise. */ | |
1441 | ||
a78f21af | 1442 | static int |
29134980 OF |
1443 | cris_spec_reg_applicable (struct cris_spec_reg spec_reg) |
1444 | { | |
1445 | int version = cris_version (); | |
1446 | ||
1447 | switch (spec_reg.applicable_version) | |
1448 | { | |
1449 | case cris_ver_version_all: | |
1450 | return 1; | |
1451 | case cris_ver_warning: | |
1452 | /* Indeterminate/obsolete. */ | |
1453 | return 0; | |
29134980 OF |
1454 | case cris_ver_v0_3: |
1455 | return (version >= 0 && version <= 3); | |
1456 | case cris_ver_v3p: | |
1457 | return (version >= 3); | |
1458 | case cris_ver_v8: | |
1459 | return (version == 8 || version == 9); | |
1460 | case cris_ver_v8p: | |
1461 | return (version >= 8); | |
c600d464 OF |
1462 | case cris_ver_v0_10: |
1463 | return (version >= 0 && version <= 10); | |
1464 | case cris_ver_v3_10: | |
1465 | return (version >= 3 && version <= 10); | |
1466 | case cris_ver_v8_10: | |
1467 | return (version >= 8 && version <= 10); | |
1468 | case cris_ver_v10: | |
1469 | return (version == 10); | |
29134980 OF |
1470 | case cris_ver_v10p: |
1471 | return (version >= 10); | |
c600d464 OF |
1472 | case cris_ver_v32p: |
1473 | return (version >= 32); | |
29134980 OF |
1474 | default: |
1475 | /* Invalid cris version. */ | |
1476 | return 0; | |
1477 | } | |
1478 | } | |
1479 | ||
1d94326f AC |
1480 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
1481 | register, -1 for an invalid register. */ | |
1482 | ||
1483 | static int | |
1484 | cris_register_size (int regno) | |
1485 | { | |
c600d464 | 1486 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1d94326f AC |
1487 | int i; |
1488 | int spec_regno; | |
1489 | ||
1490 | if (regno >= 0 && regno < NUM_GENREGS) | |
1491 | { | |
1492 | /* General registers (R0 - R15) are 32 bits. */ | |
1493 | return 4; | |
1494 | } | |
c600d464 | 1495 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
1d94326f AC |
1496 | { |
1497 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1498 | Adjust regno accordingly. */ | |
1499 | spec_regno = regno - NUM_GENREGS; | |
1500 | ||
c600d464 | 1501 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
1d94326f AC |
1502 | { |
1503 | if (cris_spec_regs[i].number == spec_regno | |
1504 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1505 | /* Go with the first applicable register. */ | |
1506 | return cris_spec_regs[i].reg_size; | |
1507 | } | |
1508 | /* Special register not applicable to this CRIS version. */ | |
1509 | return 0; | |
1510 | } | |
c600d464 | 1511 | else if (regno >= PC_REGNUM && regno < NUM_REGS) |
1d94326f | 1512 | { |
c600d464 OF |
1513 | /* This will apply to CRISv32 only where there are additional registers |
1514 | after the special registers (pseudo PC and support registers). */ | |
1515 | return 4; | |
1d94326f | 1516 | } |
c600d464 OF |
1517 | |
1518 | ||
1519 | return -1; | |
1d94326f AC |
1520 | } |
1521 | ||
29134980 OF |
1522 | /* Nonzero if regno should not be fetched from the target. This is the case |
1523 | for unimplemented (size 0) and non-existant registers. */ | |
1524 | ||
a78f21af | 1525 | static int |
29134980 OF |
1526 | cris_cannot_fetch_register (int regno) |
1527 | { | |
1528 | return ((regno < 0 || regno >= NUM_REGS) | |
1529 | || (cris_register_size (regno) == 0)); | |
1530 | } | |
1531 | ||
1532 | /* Nonzero if regno should not be written to the target, for various | |
1533 | reasons. */ | |
1534 | ||
a78f21af | 1535 | static int |
29134980 OF |
1536 | cris_cannot_store_register (int regno) |
1537 | { | |
1538 | /* There are three kinds of registers we refuse to write to. | |
1539 | 1. Those that not implemented. | |
1540 | 2. Those that are read-only (depends on the processor mode). | |
1541 | 3. Those registers to which a write has no effect. | |
1542 | */ | |
1543 | ||
1544 | if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) | |
1545 | /* Not implemented. */ | |
1546 | return 1; | |
1547 | ||
1548 | else if (regno == VR_REGNUM) | |
1549 | /* Read-only. */ | |
1550 | return 1; | |
1551 | ||
1552 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1553 | /* Writing has no effect. */ | |
1554 | return 1; | |
1555 | ||
a5f6c8f5 OF |
1556 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
1557 | agent decide whether they are writable. */ | |
29134980 OF |
1558 | |
1559 | return 0; | |
1560 | } | |
1561 | ||
c600d464 OF |
1562 | /* Nonzero if regno should not be fetched from the target. This is the case |
1563 | for unimplemented (size 0) and non-existant registers. */ | |
1564 | ||
1565 | static int | |
1566 | crisv32_cannot_fetch_register (int regno) | |
1567 | { | |
1568 | return ((regno < 0 || regno >= NUM_REGS) | |
1569 | || (cris_register_size (regno) == 0)); | |
1570 | } | |
1571 | ||
1572 | /* Nonzero if regno should not be written to the target, for various | |
1573 | reasons. */ | |
1574 | ||
1575 | static int | |
1576 | crisv32_cannot_store_register (int regno) | |
1577 | { | |
1578 | /* There are three kinds of registers we refuse to write to. | |
1579 | 1. Those that not implemented. | |
1580 | 2. Those that are read-only (depends on the processor mode). | |
1581 | 3. Those registers to which a write has no effect. | |
1582 | */ | |
1583 | ||
1584 | if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) | |
1585 | /* Not implemented. */ | |
1586 | return 1; | |
1587 | ||
1588 | else if (regno == VR_REGNUM) | |
1589 | /* Read-only. */ | |
1590 | return 1; | |
1591 | ||
1592 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) | |
1593 | /* Writing has no effect. */ | |
1594 | return 1; | |
1595 | ||
1596 | /* Many special registers are read-only in user mode. Let the debug | |
1597 | agent decide whether they are writable. */ | |
1598 | ||
1599 | return 0; | |
1600 | } | |
1601 | ||
29134980 OF |
1602 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
1603 | of data in register regno. */ | |
1604 | ||
a78f21af | 1605 | static struct type * |
c1d546cd | 1606 | cris_register_type (struct gdbarch *gdbarch, int regno) |
29134980 | 1607 | { |
a5f6c8f5 OF |
1608 | if (regno == PC_REGNUM) |
1609 | return builtin_type_void_func_ptr; | |
1610 | else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) | |
1611 | return builtin_type_void_data_ptr; | |
1612 | else if ((regno >= 0 && regno < SP_REGNUM) | |
1613 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) | |
1614 | /* Note: R8 taken care of previous clause. */ | |
1615 | return builtin_type_uint32; | |
1616 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) | |
1617 | return builtin_type_uint16; | |
1618 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) | |
1619 | return builtin_type_uint8; | |
29134980 | 1620 | else |
a5f6c8f5 OF |
1621 | /* Invalid (unimplemented) register. */ |
1622 | return builtin_type_int0; | |
29134980 OF |
1623 | } |
1624 | ||
c600d464 OF |
1625 | static struct type * |
1626 | crisv32_register_type (struct gdbarch *gdbarch, int regno) | |
1627 | { | |
1628 | if (regno == PC_REGNUM) | |
1629 | return builtin_type_void_func_ptr; | |
1630 | else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM) | |
1631 | return builtin_type_void_data_ptr; | |
1632 | else if ((regno >= 0 && regno <= ACR_REGNUM) | |
1633 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) | |
1634 | || (regno == PID_REGNUM) | |
1635 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) | |
1636 | /* Note: R8 and SP taken care of by previous clause. */ | |
1637 | return builtin_type_uint32; | |
1638 | else if (regno == WZ_REGNUM) | |
1639 | return builtin_type_uint16; | |
1640 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) | |
1641 | return builtin_type_uint8; | |
1642 | else | |
1643 | { | |
1644 | /* Invalid (unimplemented) register. Should not happen as there are | |
1645 | no unimplemented CRISv32 registers. */ | |
8a3fe4f8 | 1646 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
c600d464 OF |
1647 | return builtin_type_int0; |
1648 | } | |
1649 | } | |
1650 | ||
2e4b5889 OF |
1651 | /* Stores a function return value of type type, where valbuf is the address |
1652 | of the value to be stored. */ | |
29134980 | 1653 | |
2e4b5889 | 1654 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1655 | |
2e4b5889 OF |
1656 | static void |
1657 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
1658 | const void *valbuf) | |
29134980 | 1659 | { |
2e4b5889 OF |
1660 | ULONGEST val; |
1661 | int len = TYPE_LENGTH (type); | |
29134980 | 1662 | |
2e4b5889 | 1663 | if (len <= 4) |
29134980 | 1664 | { |
2e4b5889 OF |
1665 | /* Put the return value in R10. */ |
1666 | val = extract_unsigned_integer (valbuf, len); | |
1667 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
29134980 | 1668 | } |
2e4b5889 | 1669 | else if (len <= 8) |
29134980 | 1670 | { |
2e4b5889 OF |
1671 | /* Put the return value in R10 and R11. */ |
1672 | val = extract_unsigned_integer (valbuf, 4); | |
1673 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); | |
1674 | val = extract_unsigned_integer ((char *)valbuf + 4, len - 4); | |
1675 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); | |
29134980 | 1676 | } |
2e4b5889 | 1677 | else |
8a3fe4f8 | 1678 | error (_("cris_store_return_value: type length too large.")); |
29134980 OF |
1679 | } |
1680 | ||
2e4b5889 OF |
1681 | /* Return the name of register regno as a string. Return NULL for an invalid or |
1682 | unimplemented register. */ | |
29134980 | 1683 | |
c600d464 OF |
1684 | static const char * |
1685 | cris_special_register_name (int regno) | |
1686 | { | |
1687 | int spec_regno; | |
1688 | int i; | |
1689 | ||
1690 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1691 | Adjust regno accordingly. */ | |
1692 | spec_regno = regno - NUM_GENREGS; | |
1693 | ||
1694 | /* Assume nothing about the layout of the cris_spec_regs struct | |
1695 | when searching. */ | |
1696 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1697 | { | |
1698 | if (cris_spec_regs[i].number == spec_regno | |
1699 | && cris_spec_reg_applicable (cris_spec_regs[i])) | |
1700 | /* Go with the first applicable register. */ | |
1701 | return cris_spec_regs[i].name; | |
1702 | } | |
1703 | /* Special register not applicable to this CRIS version. */ | |
1704 | return NULL; | |
1705 | } | |
1706 | ||
2e4b5889 OF |
1707 | static const char * |
1708 | cris_register_name (int regno) | |
1709 | { | |
1710 | static char *cris_genreg_names[] = | |
1711 | { "r0", "r1", "r2", "r3", \ | |
1712 | "r4", "r5", "r6", "r7", \ | |
1713 | "r8", "r9", "r10", "r11", \ | |
1714 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1715 | |
2e4b5889 | 1716 | if (regno >= 0 && regno < NUM_GENREGS) |
29134980 | 1717 | { |
2e4b5889 OF |
1718 | /* General register. */ |
1719 | return cris_genreg_names[regno]; | |
29134980 | 1720 | } |
2e4b5889 | 1721 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) |
29134980 | 1722 | { |
c600d464 OF |
1723 | return cris_special_register_name (regno); |
1724 | } | |
1725 | else | |
1726 | { | |
1727 | /* Invalid register. */ | |
2e4b5889 OF |
1728 | return NULL; |
1729 | } | |
c600d464 OF |
1730 | } |
1731 | ||
1732 | static const char * | |
1733 | crisv32_register_name (int regno) | |
1734 | { | |
1735 | static char *crisv32_genreg_names[] = | |
1736 | { "r0", "r1", "r2", "r3", \ | |
1737 | "r4", "r5", "r6", "r7", \ | |
1738 | "r8", "r9", "r10", "r11", \ | |
1739 | "r12", "r13", "sp", "acr" | |
1740 | }; | |
1741 | ||
1742 | static char *crisv32_sreg_names[] = | |
1743 | { "s0", "s1", "s2", "s3", \ | |
1744 | "s4", "s5", "s6", "s7", \ | |
1745 | "s8", "s9", "s10", "s11", \ | |
1746 | "s12", "s13", "s14", "s15" | |
1747 | }; | |
1748 | ||
1749 | if (regno >= 0 && regno < NUM_GENREGS) | |
1750 | { | |
1751 | /* General register. */ | |
1752 | return crisv32_genreg_names[regno]; | |
1753 | } | |
1754 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) | |
1755 | { | |
1756 | return cris_special_register_name (regno); | |
1757 | } | |
1758 | else if (regno == PC_REGNUM) | |
1759 | { | |
1760 | return "pc"; | |
1761 | } | |
1762 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) | |
1763 | { | |
1764 | return crisv32_sreg_names[regno - S0_REGNUM]; | |
1765 | } | |
2e4b5889 OF |
1766 | else |
1767 | { | |
1768 | /* Invalid register. */ | |
1769 | return NULL; | |
29134980 | 1770 | } |
29134980 OF |
1771 | } |
1772 | ||
a5f6c8f5 OF |
1773 | /* Convert DWARF register number REG to the appropriate register |
1774 | number used by GDB. */ | |
1775 | ||
2e4b5889 | 1776 | static int |
a5f6c8f5 | 1777 | cris_dwarf2_reg_to_regnum (int reg) |
29134980 | 1778 | { |
a5f6c8f5 OF |
1779 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
1780 | numbering, MOF is 18). | |
1781 | Adapted from gcc/config/cris/cris.h. */ | |
1782 | static int cris_dwarf_regmap[] = { | |
1783 | 0, 1, 2, 3, | |
1784 | 4, 5, 6, 7, | |
1785 | 8, 9, 10, 11, | |
1786 | 12, 13, 14, 15, | |
1787 | 27, -1, -1, -1, | |
1788 | -1, -1, -1, 23, | |
1789 | -1, -1, -1, 27, | |
1790 | -1, -1, -1, -1 | |
1791 | }; | |
1792 | int regnum = -1; | |
1793 | ||
1794 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) | |
1795 | regnum = cris_dwarf_regmap[reg]; | |
1796 | ||
1797 | if (regnum == -1) | |
8a3fe4f8 | 1798 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
a5f6c8f5 OF |
1799 | |
1800 | return regnum; | |
1801 | } | |
1802 | ||
1803 | /* DWARF-2 frame support. */ | |
1804 | ||
1805 | static void | |
1806 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1807 | struct dwarf2_frame_state_reg *reg) | |
1808 | { | |
1809 | /* The return address column. */ | |
1810 | if (regnum == PC_REGNUM) | |
1811 | reg->how = DWARF2_FRAME_REG_RA; | |
1812 | ||
1813 | /* The call frame address. */ | |
1814 | else if (regnum == SP_REGNUM) | |
1815 | reg->how = DWARF2_FRAME_REG_CFA; | |
29134980 OF |
1816 | } |
1817 | ||
2e4b5889 OF |
1818 | /* Extract from an array regbuf containing the raw register state a function |
1819 | return value of type type, and copy that, in virtual format, into | |
1820 | valbuf. */ | |
1821 | ||
1822 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1823 | |
2e4b5889 OF |
1824 | static void |
1825 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
1826 | void *valbuf) | |
29134980 | 1827 | { |
2e4b5889 OF |
1828 | ULONGEST val; |
1829 | int len = TYPE_LENGTH (type); | |
29134980 | 1830 | |
2e4b5889 | 1831 | if (len <= 4) |
29134980 | 1832 | { |
2e4b5889 OF |
1833 | /* Get the return value from R10. */ |
1834 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1835 | store_unsigned_integer (valbuf, len, val); | |
29134980 | 1836 | } |
2e4b5889 | 1837 | else if (len <= 8) |
29134980 | 1838 | { |
2e4b5889 OF |
1839 | /* Get the return value from R10 and R11. */ |
1840 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
1841 | store_unsigned_integer (valbuf, 4, val); | |
1842 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); | |
1843 | store_unsigned_integer ((char *)valbuf + 4, len - 4, val); | |
29134980 | 1844 | } |
2e4b5889 | 1845 | else |
8a3fe4f8 | 1846 | error (_("cris_extract_return_value: type length too large")); |
2e4b5889 OF |
1847 | } |
1848 | ||
b4206d25 OF |
1849 | /* Handle the CRIS return value convention. */ |
1850 | ||
1851 | static enum return_value_convention | |
1852 | cris_return_value (struct gdbarch *gdbarch, struct type *type, | |
e2a2a3e8 OF |
1853 | struct regcache *regcache, gdb_byte *readbuf, |
1854 | const gdb_byte *writebuf) | |
b4206d25 OF |
1855 | { |
1856 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1857 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
1858 | || TYPE_LENGTH (type) > 8) | |
1859 | /* Structs, unions, and anything larger than 8 bytes (2 registers) | |
1860 | goes on the stack. */ | |
1861 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1862 | ||
1863 | if (readbuf) | |
1864 | cris_extract_return_value (type, regcache, readbuf); | |
1865 | if (writebuf) | |
1866 | cris_store_return_value (type, regcache, writebuf); | |
1867 | ||
1868 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1869 | } | |
1870 | ||
2e4b5889 OF |
1871 | /* Returns 1 if the given type will be passed by pointer rather than |
1872 | directly. */ | |
1873 | ||
1874 | /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed | |
1875 | by value. */ | |
1876 | ||
1877 | static int | |
1878 | cris_reg_struct_has_addr (int gcc_p, struct type *type) | |
1879 | { | |
1880 | return (TYPE_LENGTH (type) > 8); | |
29134980 OF |
1881 | } |
1882 | ||
1883 | /* Calculates a value that measures how good inst_args constraints an | |
1884 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1885 | ||
1886 | static int | |
1887 | constraint (unsigned int insn, const signed char *inst_args, | |
1888 | inst_env_type *inst_env) | |
1889 | { | |
1890 | int retval = 0; | |
1891 | int tmp, i; | |
1892 | ||
1893 | const char *s = inst_args; | |
1894 | ||
1895 | for (; *s; s++) | |
1896 | switch (*s) | |
1897 | { | |
1898 | case 'm': | |
1899 | if ((insn & 0x30) == 0x30) | |
1900 | return -1; | |
1901 | break; | |
1902 | ||
1903 | case 'S': | |
1904 | /* A prefix operand. */ | |
1905 | if (inst_env->prefix_found) | |
1906 | break; | |
1907 | else | |
1908 | return -1; | |
1909 | ||
1910 | case 'B': | |
1911 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for | |
1912 | valid "push" size. In case of special register, it may be != 4. */ | |
1913 | if (inst_env->prefix_found) | |
1914 | break; | |
1915 | else | |
1916 | return -1; | |
1917 | ||
1918 | case 'D': | |
1919 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); | |
1920 | if (!retval) | |
1921 | return -1; | |
1922 | else | |
1923 | retval += 4; | |
1924 | break; | |
1925 | ||
1926 | case 'P': | |
1927 | tmp = (insn >> 0xC) & 0xF; | |
fa4e4598 OF |
1928 | |
1929 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1930 | { | |
1931 | /* Since we match four bits, we will give a value of | |
1932 | 4 - 1 = 3 in a match. If there is a corresponding | |
1933 | exact match of a special register in another pattern, it | |
1934 | will get a value of 4, which will be higher. This should | |
1935 | be correct in that an exact pattern would match better that | |
1936 | a general pattern. | |
1937 | Note that there is a reason for not returning zero; the | |
1938 | pattern for "clear" is partly matched in the bit-pattern | |
1939 | (the two lower bits must be zero), while the bit-pattern | |
1940 | for a move from a special register is matched in the | |
1941 | register constraint. | |
1942 | This also means we will will have a race condition if | |
1943 | there is a partly match in three bits in the bit pattern. */ | |
1944 | if (tmp == cris_spec_regs[i].number) | |
1945 | { | |
1946 | retval += 3; | |
1947 | break; | |
1948 | } | |
1949 | } | |
1950 | ||
1951 | if (cris_spec_regs[i].name == NULL) | |
29134980 OF |
1952 | return -1; |
1953 | break; | |
1954 | } | |
1955 | return retval; | |
1956 | } | |
1957 | ||
1958 | /* Returns the number of bits set in the variable value. */ | |
1959 | ||
1960 | static int | |
1961 | number_of_bits (unsigned int value) | |
1962 | { | |
1963 | int number_of_bits = 0; | |
1964 | ||
1965 | while (value != 0) | |
1966 | { | |
1967 | number_of_bits += 1; | |
1968 | value &= (value - 1); | |
1969 | } | |
1970 | return number_of_bits; | |
1971 | } | |
1972 | ||
1973 | /* Finds the address that should contain the single step breakpoint(s). | |
1974 | It stems from code in cris-dis.c. */ | |
1975 | ||
1976 | static int | |
1977 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
1978 | { | |
1979 | int i; | |
1980 | int max_level_of_match = -1; | |
1981 | int max_matched = -1; | |
1982 | int level_of_match; | |
1983 | ||
1984 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
1985 | { | |
1986 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
c600d464 OF |
1987 | && ((cris_opcodes[i].lose & insn) == 0) |
1988 | /* Only CRISv10 instructions, please. */ | |
1989 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) | |
29134980 OF |
1990 | { |
1991 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
1992 | if (level_of_match >= 0) | |
1993 | { | |
1994 | level_of_match += | |
1995 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
1996 | if (level_of_match > max_level_of_match) | |
1997 | { | |
1998 | max_matched = i; | |
1999 | max_level_of_match = level_of_match; | |
2000 | if (level_of_match == 16) | |
2001 | { | |
2002 | /* All bits matched, cannot find better. */ | |
2003 | break; | |
2004 | } | |
2005 | } | |
2006 | } | |
2007 | } | |
2008 | } | |
2009 | return max_matched; | |
2010 | } | |
2011 | ||
2012 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
2013 | actually an internal error. */ | |
2014 | ||
2015 | static int | |
2016 | find_step_target (inst_env_type *inst_env) | |
2017 | { | |
2018 | int i; | |
2019 | int offset; | |
2020 | unsigned short insn; | |
2021 | ||
2022 | /* Create a local register image and set the initial state. */ | |
2023 | for (i = 0; i < NUM_GENREGS; i++) | |
2024 | { | |
2025 | inst_env->reg[i] = (unsigned long) read_register (i); | |
2026 | } | |
2027 | offset = NUM_GENREGS; | |
2028 | for (i = 0; i < NUM_SPECREGS; i++) | |
2029 | { | |
2030 | inst_env->preg[i] = (unsigned long) read_register (offset + i); | |
2031 | } | |
2032 | inst_env->branch_found = 0; | |
2033 | inst_env->slot_needed = 0; | |
2034 | inst_env->delay_slot_pc_active = 0; | |
2035 | inst_env->prefix_found = 0; | |
2036 | inst_env->invalid = 0; | |
2037 | inst_env->xflag_found = 0; | |
2038 | inst_env->disable_interrupt = 0; | |
2039 | ||
2040 | /* Look for a step target. */ | |
2041 | do | |
2042 | { | |
2043 | /* Read an instruction from the client. */ | |
2044 | insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2); | |
2045 | ||
2046 | /* If the instruction is not in a delay slot the new content of the | |
2047 | PC is [PC] + 2. If the instruction is in a delay slot it is not | |
2048 | that simple. Since a instruction in a delay slot cannot change | |
2049 | the content of the PC, it does not matter what value PC will have. | |
2050 | Just make sure it is a valid instruction. */ | |
2051 | if (!inst_env->delay_slot_pc_active) | |
2052 | { | |
2053 | inst_env->reg[PC_REGNUM] += 2; | |
2054 | } | |
2055 | else | |
2056 | { | |
2057 | inst_env->delay_slot_pc_active = 0; | |
2058 | inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc; | |
2059 | } | |
2060 | /* Analyse the present instruction. */ | |
2061 | i = find_cris_op (insn, inst_env); | |
2062 | if (i == -1) | |
2063 | { | |
2064 | inst_env->invalid = 1; | |
2065 | } | |
2066 | else | |
2067 | { | |
2068 | cris_gdb_func (cris_opcodes[i].op, insn, inst_env); | |
2069 | } | |
2070 | } while (!inst_env->invalid | |
2071 | && (inst_env->prefix_found || inst_env->xflag_found | |
2072 | || inst_env->slot_needed)); | |
2073 | return i; | |
2074 | } | |
2075 | ||
2076 | /* There is no hardware single-step support. The function find_step_target | |
2077 | digs through the opcodes in order to find all possible targets. | |
2078 | Either one ordinary target or two targets for branches may be found. */ | |
2079 | ||
a78f21af | 2080 | static void |
29134980 OF |
2081 | cris_software_single_step (enum target_signal ignore, int insert_breakpoints) |
2082 | { | |
2083 | inst_env_type inst_env; | |
2084 | ||
2085 | if (insert_breakpoints) | |
2086 | { | |
2087 | /* Analyse the present instruction environment and insert | |
2088 | breakpoints. */ | |
2089 | int status = find_step_target (&inst_env); | |
2090 | if (status == -1) | |
2091 | { | |
c600d464 OF |
2092 | /* Could not find a target. Things are likely to go downhill |
2093 | from here. */ | |
8a3fe4f8 | 2094 | warning (_("CRIS software single step could not find a step target.")); |
29134980 OF |
2095 | } |
2096 | else | |
2097 | { | |
2098 | /* Insert at most two breakpoints. One for the next PC content | |
2099 | and possibly another one for a branch, jump, etc. */ | |
2100 | next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM]; | |
2101 | target_insert_breakpoint (next_pc, break_mem[0]); | |
2102 | if (inst_env.branch_found | |
2103 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
2104 | { | |
2105 | branch_target_address = | |
2106 | (CORE_ADDR) inst_env.branch_break_address; | |
2107 | target_insert_breakpoint (branch_target_address, break_mem[1]); | |
2108 | branch_break_inserted = 1; | |
2109 | } | |
2110 | } | |
2111 | } | |
2112 | else | |
2113 | { | |
2114 | /* Remove breakpoints. */ | |
2115 | target_remove_breakpoint (next_pc, break_mem[0]); | |
2116 | if (branch_break_inserted) | |
2117 | { | |
2118 | target_remove_breakpoint (branch_target_address, break_mem[1]); | |
2119 | branch_break_inserted = 0; | |
2120 | } | |
2121 | } | |
2122 | } | |
2123 | ||
2124 | /* Calculates the prefix value for quick offset addressing mode. */ | |
2125 | ||
a78f21af | 2126 | static void |
29134980 OF |
2127 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2128 | { | |
2129 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
2130 | instruction (not 100% sure). */ | |
2131 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2132 | { | |
2133 | inst_env->invalid = 1; | |
2134 | return; | |
2135 | } | |
2136 | ||
2137 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
2138 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
2139 | ||
2140 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2141 | need updating. */ | |
2142 | inst_env->slot_needed = 0; | |
2143 | inst_env->prefix_found = 1; | |
2144 | } | |
2145 | ||
2146 | /* Updates the autoincrement register. The size of the increment is derived | |
2147 | from the size of the operation. The PC is always kept aligned on even | |
2148 | word addresses. */ | |
2149 | ||
a78f21af | 2150 | static void |
29134980 OF |
2151 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
2152 | { | |
2153 | if (size == INST_BYTE_SIZE) | |
2154 | { | |
2155 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
2156 | ||
2157 | /* The PC must be word aligned, so increase the PC with one | |
2158 | word even if the size is byte. */ | |
2159 | if (cris_get_operand1 (inst) == REG_PC) | |
2160 | { | |
2161 | inst_env->reg[REG_PC] += 1; | |
2162 | } | |
2163 | } | |
2164 | else if (size == INST_WORD_SIZE) | |
2165 | { | |
2166 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
2167 | } | |
2168 | else if (size == INST_DWORD_SIZE) | |
2169 | { | |
2170 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2171 | } | |
2172 | else | |
2173 | { | |
2174 | /* Invalid size. */ | |
2175 | inst_env->invalid = 1; | |
2176 | } | |
2177 | } | |
2178 | ||
2a9ecef2 OF |
2179 | /* Just a forward declaration. */ |
2180 | ||
a78f21af AC |
2181 | static unsigned long get_data_from_address (unsigned short *inst, |
2182 | CORE_ADDR address); | |
2a9ecef2 | 2183 | |
29134980 OF |
2184 | /* Calculates the prefix value for the general case of offset addressing |
2185 | mode. */ | |
2186 | ||
a78f21af | 2187 | static void |
29134980 OF |
2188 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2189 | { | |
2190 | ||
2191 | long offset; | |
2192 | ||
2193 | /* It's invalid to be in a delay slot. */ | |
2194 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2195 | { | |
2196 | inst_env->invalid = 1; | |
2197 | return; | |
2198 | } | |
2199 | ||
fa4e4598 OF |
2200 | /* The calculation of prefix_value used to be after process_autoincrement, |
2201 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
2202 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
2203 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
2204 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
2205 | ||
2206 | /* The offset is an indirection of the contents of the operand1 register. */ | |
2207 | inst_env->prefix_value += | |
2a9ecef2 OF |
2208 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)]); |
2209 | ||
fa4e4598 OF |
2210 | if (cris_get_mode (inst) == AUTOINC_MODE) |
2211 | { | |
2212 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2213 | } | |
2214 | ||
29134980 OF |
2215 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
2216 | need updating. */ | |
2217 | inst_env->slot_needed = 0; | |
2218 | inst_env->prefix_found = 1; | |
2219 | } | |
2220 | ||
2221 | /* Calculates the prefix value for the index addressing mode. */ | |
2222 | ||
a78f21af | 2223 | static void |
29134980 OF |
2224 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
2225 | { | |
2226 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
2227 | have a prefix to this instruction. So I will treat this as invalid. */ | |
2228 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2229 | { | |
2230 | inst_env->invalid = 1; | |
2231 | return; | |
2232 | } | |
2233 | ||
2234 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
2235 | ||
2236 | /* The offset is the operand2 value shifted the size of the instruction | |
2237 | to the left. */ | |
2238 | inst_env->prefix_value += | |
2239 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
2240 | ||
2241 | /* If the PC is operand1 (base) the address used is the address after | |
2242 | the main instruction, i.e. address + 2 (the PC is already compensated | |
2243 | for the prefix operation). */ | |
2244 | if (cris_get_operand1 (inst) == REG_PC) | |
2245 | { | |
2246 | inst_env->prefix_value += 2; | |
2247 | } | |
2248 | ||
2249 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2250 | need updating. */ | |
2251 | inst_env->slot_needed = 0; | |
2252 | inst_env->xflag_found = 0; | |
2253 | inst_env->prefix_found = 1; | |
2254 | } | |
2255 | ||
2256 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
2257 | ||
a78f21af | 2258 | static void |
29134980 OF |
2259 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
2260 | { | |
2261 | ||
2262 | CORE_ADDR address; | |
2263 | ||
2264 | /* It's invalid to be in a delay slot. */ | |
2265 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2266 | { | |
2267 | inst_env->invalid = 1; | |
2268 | return; | |
2269 | } | |
2270 | ||
2271 | /* The prefix value is one dereference of the contents of the operand1 | |
2272 | register. */ | |
2273 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2274 | inst_env->prefix_value = read_memory_unsigned_integer (address, 4); | |
2275 | ||
2276 | /* Check if the mode is autoincrement. */ | |
2277 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2278 | { | |
2279 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2280 | } | |
2281 | ||
2282 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2283 | need updating. */ | |
2284 | inst_env->slot_needed = 0; | |
2285 | inst_env->xflag_found = 0; | |
2286 | inst_env->prefix_found = 1; | |
2287 | } | |
2288 | ||
2289 | /* Finds the destination for a branch with 8-bits offset. */ | |
2290 | ||
a78f21af | 2291 | static void |
29134980 OF |
2292 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2293 | { | |
2294 | ||
2295 | short offset; | |
2296 | ||
2297 | /* If we have a prefix or are in a delay slot it's bad. */ | |
2298 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2299 | { | |
2300 | inst_env->invalid = 1; | |
2301 | return; | |
2302 | } | |
2303 | ||
2304 | /* We have a branch, find out where the branch will land. */ | |
2305 | offset = cris_get_branch_short_offset (inst); | |
2306 | ||
2307 | /* Check if the offset is signed. */ | |
2308 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2309 | { | |
2310 | offset |= 0xFF00; | |
2311 | } | |
2312 | ||
2313 | /* The offset ends with the sign bit, set it to zero. The address | |
2314 | should always be word aligned. */ | |
2315 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2316 | ||
2317 | inst_env->branch_found = 1; | |
2318 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2319 | ||
2320 | inst_env->slot_needed = 1; | |
2321 | inst_env->prefix_found = 0; | |
2322 | inst_env->xflag_found = 0; | |
2323 | inst_env->disable_interrupt = 1; | |
2324 | } | |
2325 | ||
2326 | /* Finds the destination for a branch with 16-bits offset. */ | |
2327 | ||
a78f21af | 2328 | static void |
29134980 OF |
2329 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2330 | { | |
2331 | short offset; | |
2332 | ||
2333 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2334 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2335 | { | |
2336 | inst_env->invalid = 1; | |
2337 | return; | |
2338 | } | |
2339 | ||
2340 | /* We have a branch, find out the offset for the branch. */ | |
2341 | offset = read_memory_integer (inst_env->reg[REG_PC], 2); | |
2342 | ||
2343 | /* The instruction is one word longer than normal, so add one word | |
2344 | to the PC. */ | |
2345 | inst_env->reg[REG_PC] += 2; | |
2346 | ||
2347 | inst_env->branch_found = 1; | |
2348 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2349 | ||
2350 | ||
2351 | inst_env->slot_needed = 1; | |
2352 | inst_env->prefix_found = 0; | |
2353 | inst_env->xflag_found = 0; | |
2354 | inst_env->disable_interrupt = 1; | |
2355 | } | |
2356 | ||
2357 | /* Handles the ABS instruction. */ | |
2358 | ||
a78f21af | 2359 | static void |
29134980 OF |
2360 | abs_op (unsigned short inst, inst_env_type *inst_env) |
2361 | { | |
2362 | ||
2363 | long value; | |
2364 | ||
2365 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2366 | if (inst_env->prefix_found) | |
2367 | { | |
2368 | inst_env->invalid = 1; | |
2369 | return; | |
2370 | } | |
2371 | ||
2372 | /* Check if the operation affects the PC. */ | |
2373 | if (cris_get_operand2 (inst) == REG_PC) | |
2374 | { | |
2375 | ||
2376 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2377 | if (inst_env->slot_needed) | |
2378 | { | |
2379 | inst_env->invalid = 1; | |
2380 | return; | |
2381 | } | |
2382 | ||
2383 | value = (long) inst_env->reg[REG_PC]; | |
2384 | ||
2385 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2386 | if (value != SIGNED_DWORD_MASK) | |
2387 | { | |
2388 | value = -value; | |
2389 | inst_env->reg[REG_PC] = (long) value; | |
2390 | } | |
2391 | } | |
2392 | ||
2393 | inst_env->slot_needed = 0; | |
2394 | inst_env->prefix_found = 0; | |
2395 | inst_env->xflag_found = 0; | |
2396 | inst_env->disable_interrupt = 0; | |
2397 | } | |
2398 | ||
2399 | /* Handles the ADDI instruction. */ | |
2400 | ||
a78f21af | 2401 | static void |
29134980 OF |
2402 | addi_op (unsigned short inst, inst_env_type *inst_env) |
2403 | { | |
2404 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2405 | a prefix. */ | |
2406 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2407 | { | |
2408 | inst_env->invalid = 1; | |
2409 | return; | |
2410 | } | |
2411 | ||
2412 | inst_env->slot_needed = 0; | |
2413 | inst_env->prefix_found = 0; | |
2414 | inst_env->xflag_found = 0; | |
2415 | inst_env->disable_interrupt = 0; | |
2416 | } | |
2417 | ||
2418 | /* Handles the ASR instruction. */ | |
2419 | ||
a78f21af | 2420 | static void |
29134980 OF |
2421 | asr_op (unsigned short inst, inst_env_type *inst_env) |
2422 | { | |
2423 | int shift_steps; | |
2424 | unsigned long value; | |
2425 | unsigned long signed_extend_mask = 0; | |
2426 | ||
2427 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2428 | if (inst_env->prefix_found) | |
2429 | { | |
2430 | inst_env->invalid = 1; | |
2431 | return; | |
2432 | } | |
2433 | ||
2434 | /* Check if the PC is the target register. */ | |
2435 | if (cris_get_operand2 (inst) == REG_PC) | |
2436 | { | |
2437 | /* It's invalid to change the PC in a delay slot. */ | |
2438 | if (inst_env->slot_needed) | |
2439 | { | |
2440 | inst_env->invalid = 1; | |
2441 | return; | |
2442 | } | |
2443 | /* Get the number of bits to shift. */ | |
2444 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
2445 | value = inst_env->reg[REG_PC]; | |
2446 | ||
2447 | /* Find out how many bits the operation should apply to. */ | |
2448 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
2449 | { | |
2450 | if (value & SIGNED_BYTE_MASK) | |
2451 | { | |
2452 | signed_extend_mask = 0xFF; | |
2453 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2454 | signed_extend_mask = ~signed_extend_mask; | |
2455 | } | |
2456 | value = value >> shift_steps; | |
2457 | value |= signed_extend_mask; | |
2458 | value &= 0xFF; | |
2459 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2460 | inst_env->reg[REG_PC] |= value; | |
2461 | } | |
2462 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
2463 | { | |
2464 | if (value & SIGNED_WORD_MASK) | |
2465 | { | |
2466 | signed_extend_mask = 0xFFFF; | |
2467 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2468 | signed_extend_mask = ~signed_extend_mask; | |
2469 | } | |
2470 | value = value >> shift_steps; | |
2471 | value |= signed_extend_mask; | |
2472 | value &= 0xFFFF; | |
2473 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2474 | inst_env->reg[REG_PC] |= value; | |
2475 | } | |
2476 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
2477 | { | |
2478 | if (value & SIGNED_DWORD_MASK) | |
2479 | { | |
2480 | signed_extend_mask = 0xFFFFFFFF; | |
2481 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2482 | signed_extend_mask = ~signed_extend_mask; | |
2483 | } | |
2484 | value = value >> shift_steps; | |
2485 | value |= signed_extend_mask; | |
2486 | inst_env->reg[REG_PC] = value; | |
2487 | } | |
2488 | } | |
2489 | inst_env->slot_needed = 0; | |
2490 | inst_env->prefix_found = 0; | |
2491 | inst_env->xflag_found = 0; | |
2492 | inst_env->disable_interrupt = 0; | |
2493 | } | |
2494 | ||
2495 | /* Handles the ASRQ instruction. */ | |
2496 | ||
a78f21af | 2497 | static void |
29134980 OF |
2498 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2499 | { | |
2500 | ||
2501 | int shift_steps; | |
2502 | unsigned long value; | |
2503 | unsigned long signed_extend_mask = 0; | |
2504 | ||
2505 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2506 | if (inst_env->prefix_found) | |
2507 | { | |
2508 | inst_env->invalid = 1; | |
2509 | return; | |
2510 | } | |
2511 | ||
2512 | /* Check if the PC is the target register. */ | |
2513 | if (cris_get_operand2 (inst) == REG_PC) | |
2514 | { | |
2515 | ||
2516 | /* It's invalid to change the PC in a delay slot. */ | |
2517 | if (inst_env->slot_needed) | |
2518 | { | |
2519 | inst_env->invalid = 1; | |
2520 | return; | |
2521 | } | |
2522 | /* The shift size is given as a 5 bit quick value, i.e. we don't | |
2523 | want the the sign bit of the quick value. */ | |
2524 | shift_steps = cris_get_asr_shift_steps (inst); | |
2525 | value = inst_env->reg[REG_PC]; | |
2526 | if (value & SIGNED_DWORD_MASK) | |
2527 | { | |
2528 | signed_extend_mask = 0xFFFFFFFF; | |
2529 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2530 | signed_extend_mask = ~signed_extend_mask; | |
2531 | } | |
2532 | value = value >> shift_steps; | |
2533 | value |= signed_extend_mask; | |
2534 | inst_env->reg[REG_PC] = value; | |
2535 | } | |
2536 | inst_env->slot_needed = 0; | |
2537 | inst_env->prefix_found = 0; | |
2538 | inst_env->xflag_found = 0; | |
2539 | inst_env->disable_interrupt = 0; | |
2540 | } | |
2541 | ||
2542 | /* Handles the AX, EI and SETF instruction. */ | |
2543 | ||
a78f21af | 2544 | static void |
29134980 OF |
2545 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2546 | { | |
2547 | if (inst_env->prefix_found) | |
2548 | { | |
2549 | inst_env->invalid = 1; | |
2550 | return; | |
2551 | } | |
2552 | /* Check if the instruction is setting the X flag. */ | |
2553 | if (cris_is_xflag_bit_on (inst)) | |
2554 | { | |
2555 | inst_env->xflag_found = 1; | |
2556 | } | |
2557 | else | |
2558 | { | |
2559 | inst_env->xflag_found = 0; | |
2560 | } | |
2561 | inst_env->slot_needed = 0; | |
2562 | inst_env->prefix_found = 0; | |
2563 | inst_env->disable_interrupt = 1; | |
2564 | } | |
2565 | ||
2566 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2567 | register. Note that check_assign assumes that the caller has checked that | |
2568 | there is a prefix to this instruction. The mode check depends on this. */ | |
2569 | ||
a78f21af | 2570 | static void |
29134980 OF |
2571 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2572 | { | |
2573 | /* Check if it's an assign addressing mode. */ | |
2574 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2575 | { | |
2576 | /* Assign the prefix value to operand 1. */ | |
2577 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2578 | } | |
2579 | } | |
2580 | ||
2581 | /* Handles the 2-operand BOUND instruction. */ | |
2582 | ||
a78f21af | 2583 | static void |
29134980 OF |
2584 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2585 | { | |
2586 | /* It's invalid to have the PC as the index operand. */ | |
2587 | if (cris_get_operand2 (inst) == REG_PC) | |
2588 | { | |
2589 | inst_env->invalid = 1; | |
2590 | return; | |
2591 | } | |
2592 | /* Check if we have a prefix. */ | |
2593 | if (inst_env->prefix_found) | |
2594 | { | |
2595 | check_assign (inst, inst_env); | |
2596 | } | |
2597 | /* Check if this is an autoincrement mode. */ | |
2598 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2599 | { | |
2600 | /* It's invalid to change the PC in a delay slot. */ | |
2601 | if (inst_env->slot_needed) | |
2602 | { | |
2603 | inst_env->invalid = 1; | |
2604 | return; | |
2605 | } | |
2606 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2607 | } | |
2608 | inst_env->slot_needed = 0; | |
2609 | inst_env->prefix_found = 0; | |
2610 | inst_env->xflag_found = 0; | |
2611 | inst_env->disable_interrupt = 0; | |
2612 | } | |
2613 | ||
2614 | /* Handles the 3-operand BOUND instruction. */ | |
2615 | ||
a78f21af | 2616 | static void |
29134980 OF |
2617 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2618 | { | |
2619 | /* It's an error if we haven't got a prefix. And it's also an error | |
2620 | if the PC is the destination register. */ | |
2621 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2622 | { | |
2623 | inst_env->invalid = 1; | |
2624 | return; | |
2625 | } | |
2626 | inst_env->slot_needed = 0; | |
2627 | inst_env->prefix_found = 0; | |
2628 | inst_env->xflag_found = 0; | |
2629 | inst_env->disable_interrupt = 0; | |
2630 | } | |
2631 | ||
2632 | /* Clears the status flags in inst_env. */ | |
2633 | ||
a78f21af | 2634 | static void |
29134980 OF |
2635 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2636 | { | |
2637 | /* It's an error if we have got a prefix. */ | |
2638 | if (inst_env->prefix_found) | |
2639 | { | |
2640 | inst_env->invalid = 1; | |
2641 | return; | |
2642 | } | |
2643 | ||
2644 | inst_env->slot_needed = 0; | |
2645 | inst_env->prefix_found = 0; | |
2646 | inst_env->xflag_found = 0; | |
2647 | inst_env->disable_interrupt = 0; | |
2648 | } | |
2649 | ||
2650 | /* Clears the status flags in inst_env. */ | |
2651 | ||
a78f21af | 2652 | static void |
29134980 OF |
2653 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2654 | { | |
2655 | /* It's an error if we have got a prefix. */ | |
2656 | if (inst_env->prefix_found) | |
2657 | { | |
2658 | inst_env->invalid = 1; | |
2659 | return; | |
2660 | } | |
2661 | ||
2662 | inst_env->slot_needed = 0; | |
2663 | inst_env->prefix_found = 0; | |
2664 | inst_env->xflag_found = 0; | |
2665 | inst_env->disable_interrupt = 1; | |
2666 | } | |
2667 | ||
2668 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2669 | ||
a78f21af | 2670 | static void |
29134980 OF |
2671 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2672 | { | |
2673 | /* Check if the target is the PC. */ | |
2674 | if (cris_get_operand2 (inst) == REG_PC) | |
2675 | { | |
2676 | /* The instruction will clear the instruction's size bits. */ | |
2677 | int clear_size = cris_get_clear_size (inst); | |
2678 | if (clear_size == INST_BYTE_SIZE) | |
2679 | { | |
2680 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2681 | } | |
2682 | if (clear_size == INST_WORD_SIZE) | |
2683 | { | |
2684 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2685 | } | |
2686 | if (clear_size == INST_DWORD_SIZE) | |
2687 | { | |
2688 | inst_env->delay_slot_pc = 0x0; | |
2689 | } | |
2690 | /* The jump will be delayed with one delay slot. So we need a delay | |
2691 | slot. */ | |
2692 | inst_env->slot_needed = 1; | |
2693 | inst_env->delay_slot_pc_active = 1; | |
2694 | } | |
2695 | else | |
2696 | { | |
2697 | /* The PC will not change => no delay slot. */ | |
2698 | inst_env->slot_needed = 0; | |
2699 | } | |
2700 | inst_env->prefix_found = 0; | |
2701 | inst_env->xflag_found = 0; | |
2702 | inst_env->disable_interrupt = 0; | |
2703 | } | |
2704 | ||
2705 | /* Handles the TEST instruction if it's in register mode. */ | |
2706 | ||
a78f21af | 2707 | static void |
29134980 OF |
2708 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2709 | { | |
2710 | /* It's an error if we have got a prefix. */ | |
2711 | if (inst_env->prefix_found) | |
2712 | { | |
2713 | inst_env->invalid = 1; | |
2714 | return; | |
2715 | } | |
2716 | inst_env->slot_needed = 0; | |
2717 | inst_env->prefix_found = 0; | |
2718 | inst_env->xflag_found = 0; | |
2719 | inst_env->disable_interrupt = 0; | |
2720 | ||
2721 | } | |
2722 | ||
2723 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2724 | in register mode. */ | |
2725 | ||
a78f21af | 2726 | static void |
29134980 OF |
2727 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2728 | { | |
2729 | /* Check if we are in a prefix mode. */ | |
2730 | if (inst_env->prefix_found) | |
2731 | { | |
2732 | /* The only way the PC can change is if this instruction is in | |
2733 | assign addressing mode. */ | |
2734 | check_assign (inst, inst_env); | |
2735 | } | |
2736 | /* Indirect mode can't change the PC so just check if the mode is | |
2737 | autoincrement. */ | |
2738 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2739 | { | |
2740 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2741 | } | |
2742 | inst_env->slot_needed = 0; | |
2743 | inst_env->prefix_found = 0; | |
2744 | inst_env->xflag_found = 0; | |
2745 | inst_env->disable_interrupt = 0; | |
2746 | } | |
2747 | ||
2748 | /* Checks that the PC isn't the destination register or the instructions has | |
2749 | a prefix. */ | |
2750 | ||
a78f21af | 2751 | static void |
29134980 OF |
2752 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2753 | { | |
2754 | /* It's invalid to have the PC as the destination. The instruction can't | |
2755 | have a prefix. */ | |
2756 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2757 | { | |
2758 | inst_env->invalid = 1; | |
2759 | return; | |
2760 | } | |
2761 | ||
2762 | inst_env->slot_needed = 0; | |
2763 | inst_env->prefix_found = 0; | |
2764 | inst_env->xflag_found = 0; | |
2765 | inst_env->disable_interrupt = 0; | |
2766 | } | |
2767 | ||
2768 | /* Checks that the instruction doesn't have a prefix. */ | |
2769 | ||
a78f21af | 2770 | static void |
29134980 OF |
2771 | break_op (unsigned short inst, inst_env_type *inst_env) |
2772 | { | |
2773 | /* The instruction can't have a prefix. */ | |
2774 | if (inst_env->prefix_found) | |
2775 | { | |
2776 | inst_env->invalid = 1; | |
2777 | return; | |
2778 | } | |
2779 | ||
2780 | inst_env->slot_needed = 0; | |
2781 | inst_env->prefix_found = 0; | |
2782 | inst_env->xflag_found = 0; | |
2783 | inst_env->disable_interrupt = 1; | |
2784 | } | |
2785 | ||
2786 | /* Checks that the PC isn't the destination register and that the instruction | |
2787 | doesn't have a prefix. */ | |
2788 | ||
a78f21af | 2789 | static void |
29134980 OF |
2790 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2791 | { | |
2792 | /* It's invalid to have the PC as the destination. The instruction can't | |
2793 | have a prefix. */ | |
2794 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2795 | { | |
2796 | inst_env->invalid = 1; | |
2797 | return; | |
2798 | } | |
2799 | ||
2800 | inst_env->slot_needed = 0; | |
2801 | inst_env->prefix_found = 0; | |
2802 | inst_env->xflag_found = 0; | |
2803 | inst_env->disable_interrupt = 1; | |
2804 | } | |
2805 | ||
2806 | /* Handles the register mode JUMP instruction. */ | |
2807 | ||
a78f21af | 2808 | static void |
29134980 OF |
2809 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2810 | { | |
2811 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2812 | you can't have a prefix. */ | |
2813 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2814 | { | |
2815 | inst_env->invalid = 1; | |
2816 | return; | |
2817 | } | |
2818 | ||
2819 | /* Just change the PC. */ | |
2820 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2821 | inst_env->slot_needed = 0; | |
2822 | inst_env->prefix_found = 0; | |
2823 | inst_env->xflag_found = 0; | |
2824 | inst_env->disable_interrupt = 1; | |
2825 | } | |
2826 | ||
2827 | /* Handles the JUMP instruction for all modes except register. */ | |
2828 | ||
a78f21af AC |
2829 | static void |
2830 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2831 | { |
2832 | unsigned long newpc; | |
2833 | CORE_ADDR address; | |
2834 | ||
2835 | /* It's invalid to do a JUMP in a delay slot. */ | |
2836 | if (inst_env->slot_needed) | |
2837 | { | |
2838 | inst_env->invalid = 1; | |
2839 | } | |
2840 | else | |
2841 | { | |
2842 | /* Check if we have a prefix. */ | |
2843 | if (inst_env->prefix_found) | |
2844 | { | |
2845 | check_assign (inst, inst_env); | |
2846 | ||
2847 | /* Get the new value for the the PC. */ | |
2848 | newpc = | |
2849 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
2850 | 4); | |
2851 | } | |
2852 | else | |
2853 | { | |
2854 | /* Get the new value for the PC. */ | |
2855 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2856 | newpc = read_memory_unsigned_integer (address, 4); | |
2857 | ||
2858 | /* Check if we should increment a register. */ | |
2859 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2860 | { | |
2861 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2862 | } | |
2863 | } | |
2864 | inst_env->reg[REG_PC] = newpc; | |
2865 | } | |
2866 | inst_env->slot_needed = 0; | |
2867 | inst_env->prefix_found = 0; | |
2868 | inst_env->xflag_found = 0; | |
2869 | inst_env->disable_interrupt = 1; | |
2870 | } | |
2871 | ||
2872 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2873 | ||
a78f21af | 2874 | static void |
29134980 OF |
2875 | move_to_preg_op (unsigned short inst, inst_env_type *inst_env) |
2876 | { | |
2877 | if (inst_env->prefix_found) | |
2878 | { | |
2879 | /* The instruction has a prefix that means we are only interested if | |
2880 | the instruction is in assign mode. */ | |
2881 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2882 | { | |
2883 | /* The prefix handles the problem if we are in a delay slot. */ | |
2884 | if (cris_get_operand1 (inst) == REG_PC) | |
2885 | { | |
2886 | /* Just take care of the assign. */ | |
2887 | check_assign (inst, inst_env); | |
2888 | } | |
2889 | } | |
2890 | } | |
2891 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2892 | { | |
2893 | /* The instruction doesn't have a prefix, the only case left that we | |
2894 | are interested in is the autoincrement mode. */ | |
2895 | if (cris_get_operand1 (inst) == REG_PC) | |
2896 | { | |
2897 | /* If the PC is to be incremented it's invalid to be in a | |
2898 | delay slot. */ | |
2899 | if (inst_env->slot_needed) | |
2900 | { | |
2901 | inst_env->invalid = 1; | |
2902 | return; | |
2903 | } | |
2a9ecef2 OF |
2904 | |
2905 | /* The increment depends on the size of the special register. */ | |
2906 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2907 | { |
2908 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2909 | } | |
2a9ecef2 | 2910 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2911 | { |
2912 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2913 | } | |
2914 | else | |
2915 | { | |
2916 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2917 | } | |
2918 | } | |
2919 | } | |
2920 | inst_env->slot_needed = 0; | |
2921 | inst_env->prefix_found = 0; | |
2922 | inst_env->xflag_found = 0; | |
2923 | inst_env->disable_interrupt = 1; | |
2924 | } | |
2925 | ||
2926 | /* Handles moves from special registers (aka P-register) for all modes | |
2927 | except register. */ | |
2928 | ||
a78f21af | 2929 | static void |
29134980 OF |
2930 | none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2931 | { | |
2932 | if (inst_env->prefix_found) | |
2933 | { | |
2934 | /* The instruction has a prefix that means we are only interested if | |
2935 | the instruction is in assign mode. */ | |
2936 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2937 | { | |
2938 | /* The prefix handles the problem if we are in a delay slot. */ | |
2939 | if (cris_get_operand1 (inst) == REG_PC) | |
2940 | { | |
2941 | /* Just take care of the assign. */ | |
2942 | check_assign (inst, inst_env); | |
2943 | } | |
2944 | } | |
2945 | } | |
2946 | /* The instruction doesn't have a prefix, the only case left that we | |
2947 | are interested in is the autoincrement mode. */ | |
2948 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2949 | { | |
2950 | if (cris_get_operand1 (inst) == REG_PC) | |
2951 | { | |
2952 | /* If the PC is to be incremented it's invalid to be in a | |
2953 | delay slot. */ | |
2954 | if (inst_env->slot_needed) | |
2955 | { | |
2956 | inst_env->invalid = 1; | |
2957 | return; | |
2958 | } | |
2a9ecef2 OF |
2959 | |
2960 | /* The increment depends on the size of the special register. */ | |
2961 | if (cris_register_size (cris_get_operand2 (inst)) == 1) | |
29134980 OF |
2962 | { |
2963 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2964 | } | |
2a9ecef2 | 2965 | else if (cris_register_size (cris_get_operand2 (inst)) == 2) |
29134980 OF |
2966 | { |
2967 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2968 | } | |
2969 | else | |
2970 | { | |
2971 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2972 | } | |
2973 | } | |
2974 | } | |
2975 | inst_env->slot_needed = 0; | |
2976 | inst_env->prefix_found = 0; | |
2977 | inst_env->xflag_found = 0; | |
2978 | inst_env->disable_interrupt = 1; | |
2979 | } | |
2980 | ||
2981 | /* Handles moves from special registers (aka P-register) when the mode | |
2982 | is register. */ | |
2983 | ||
a78f21af | 2984 | static void |
29134980 OF |
2985 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2986 | { | |
2987 | /* Register mode move from special register can't have a prefix. */ | |
2988 | if (inst_env->prefix_found) | |
2989 | { | |
2990 | inst_env->invalid = 1; | |
2991 | return; | |
2992 | } | |
2993 | ||
2994 | if (cris_get_operand1 (inst) == REG_PC) | |
2995 | { | |
2996 | /* It's invalid to change the PC in a delay slot. */ | |
2997 | if (inst_env->slot_needed) | |
2998 | { | |
2999 | inst_env->invalid = 1; | |
3000 | return; | |
3001 | } | |
3002 | /* The destination is the PC, the jump will have a delay slot. */ | |
3003 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
3004 | inst_env->slot_needed = 1; | |
3005 | inst_env->delay_slot_pc_active = 1; | |
3006 | } | |
3007 | else | |
3008 | { | |
3009 | /* If the destination isn't PC, there will be no jump. */ | |
3010 | inst_env->slot_needed = 0; | |
3011 | } | |
3012 | inst_env->prefix_found = 0; | |
3013 | inst_env->xflag_found = 0; | |
3014 | inst_env->disable_interrupt = 1; | |
3015 | } | |
3016 | ||
3017 | /* Handles the MOVEM from memory to general register instruction. */ | |
3018 | ||
a78f21af | 3019 | static void |
29134980 OF |
3020 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
3021 | { | |
3022 | if (inst_env->prefix_found) | |
3023 | { | |
3024 | /* The prefix handles the problem if we are in a delay slot. Is the | |
3025 | MOVEM instruction going to change the PC? */ | |
3026 | if (cris_get_operand2 (inst) >= REG_PC) | |
3027 | { | |
3028 | inst_env->reg[REG_PC] = | |
3029 | read_memory_unsigned_integer (inst_env->prefix_value, 4); | |
3030 | } | |
3031 | /* The assign value is the value after the increment. Normally, the | |
3032 | assign value is the value before the increment. */ | |
3033 | if ((cris_get_operand1 (inst) == REG_PC) | |
3034 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3035 | { | |
3036 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3037 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3038 | } | |
3039 | } | |
3040 | else | |
3041 | { | |
3042 | /* Is the MOVEM instruction going to change the PC? */ | |
3043 | if (cris_get_operand2 (inst) == REG_PC) | |
3044 | { | |
3045 | /* It's invalid to change the PC in a delay slot. */ | |
3046 | if (inst_env->slot_needed) | |
3047 | { | |
3048 | inst_env->invalid = 1; | |
3049 | return; | |
3050 | } | |
3051 | inst_env->reg[REG_PC] = | |
3052 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
3053 | 4); | |
3054 | } | |
3055 | /* The increment is not depending on the size, instead it's depending | |
3056 | on the number of registers loaded from memory. */ | |
3057 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3058 | { | |
3059 | /* It's invalid to change the PC in a delay slot. */ | |
3060 | if (inst_env->slot_needed) | |
3061 | { | |
3062 | inst_env->invalid = 1; | |
3063 | return; | |
3064 | } | |
3065 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3066 | } | |
3067 | } | |
3068 | inst_env->slot_needed = 0; | |
3069 | inst_env->prefix_found = 0; | |
3070 | inst_env->xflag_found = 0; | |
3071 | inst_env->disable_interrupt = 0; | |
3072 | } | |
3073 | ||
3074 | /* Handles the MOVEM to memory from general register instruction. */ | |
3075 | ||
a78f21af | 3076 | static void |
29134980 OF |
3077 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
3078 | { | |
3079 | if (inst_env->prefix_found) | |
3080 | { | |
3081 | /* The assign value is the value after the increment. Normally, the | |
3082 | assign value is the value before the increment. */ | |
3083 | if ((cris_get_operand1 (inst) == REG_PC) && | |
3084 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) | |
3085 | { | |
3086 | /* The prefix handles the problem if we are in a delay slot. */ | |
3087 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3088 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3089 | } | |
3090 | } | |
3091 | else | |
3092 | { | |
3093 | /* The increment is not depending on the size, instead it's depending | |
3094 | on the number of registers loaded to memory. */ | |
3095 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3096 | { | |
3097 | /* It's invalid to change the PC in a delay slot. */ | |
3098 | if (inst_env->slot_needed) | |
3099 | { | |
3100 | inst_env->invalid = 1; | |
3101 | return; | |
3102 | } | |
3103 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3104 | } | |
3105 | } | |
3106 | inst_env->slot_needed = 0; | |
3107 | inst_env->prefix_found = 0; | |
3108 | inst_env->xflag_found = 0; | |
3109 | inst_env->disable_interrupt = 0; | |
3110 | } | |
3111 | ||
29134980 OF |
3112 | /* Handles the intructions that's not yet implemented, by setting |
3113 | inst_env->invalid to true. */ | |
3114 | ||
a78f21af | 3115 | static void |
29134980 OF |
3116 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
3117 | { | |
3118 | inst_env->invalid = 1; | |
3119 | } | |
3120 | ||
3121 | /* Handles the XOR instruction. */ | |
3122 | ||
a78f21af | 3123 | static void |
29134980 OF |
3124 | xor_op (unsigned short inst, inst_env_type *inst_env) |
3125 | { | |
3126 | /* XOR can't have a prefix. */ | |
3127 | if (inst_env->prefix_found) | |
3128 | { | |
3129 | inst_env->invalid = 1; | |
3130 | return; | |
3131 | } | |
3132 | ||
3133 | /* Check if the PC is the target. */ | |
3134 | if (cris_get_operand2 (inst) == REG_PC) | |
3135 | { | |
3136 | /* It's invalid to change the PC in a delay slot. */ | |
3137 | if (inst_env->slot_needed) | |
3138 | { | |
3139 | inst_env->invalid = 1; | |
3140 | return; | |
3141 | } | |
3142 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; | |
3143 | } | |
3144 | inst_env->slot_needed = 0; | |
3145 | inst_env->prefix_found = 0; | |
3146 | inst_env->xflag_found = 0; | |
3147 | inst_env->disable_interrupt = 0; | |
3148 | } | |
3149 | ||
3150 | /* Handles the MULS instruction. */ | |
3151 | ||
a78f21af | 3152 | static void |
29134980 OF |
3153 | muls_op (unsigned short inst, inst_env_type *inst_env) |
3154 | { | |
3155 | /* MULS/U can't have a prefix. */ | |
3156 | if (inst_env->prefix_found) | |
3157 | { | |
3158 | inst_env->invalid = 1; | |
3159 | return; | |
3160 | } | |
3161 | ||
3162 | /* Consider it invalid if the PC is the target. */ | |
3163 | if (cris_get_operand2 (inst) == REG_PC) | |
3164 | { | |
3165 | inst_env->invalid = 1; | |
3166 | return; | |
3167 | } | |
3168 | inst_env->slot_needed = 0; | |
3169 | inst_env->prefix_found = 0; | |
3170 | inst_env->xflag_found = 0; | |
3171 | inst_env->disable_interrupt = 0; | |
3172 | } | |
3173 | ||
3174 | /* Handles the MULU instruction. */ | |
3175 | ||
a78f21af | 3176 | static void |
29134980 OF |
3177 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
3178 | { | |
3179 | /* MULS/U can't have a prefix. */ | |
3180 | if (inst_env->prefix_found) | |
3181 | { | |
3182 | inst_env->invalid = 1; | |
3183 | return; | |
3184 | } | |
3185 | ||
3186 | /* Consider it invalid if the PC is the target. */ | |
3187 | if (cris_get_operand2 (inst) == REG_PC) | |
3188 | { | |
3189 | inst_env->invalid = 1; | |
3190 | return; | |
3191 | } | |
3192 | inst_env->slot_needed = 0; | |
3193 | inst_env->prefix_found = 0; | |
3194 | inst_env->xflag_found = 0; | |
3195 | inst_env->disable_interrupt = 0; | |
3196 | } | |
3197 | ||
3198 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. | |
3199 | The MOVE instruction is the move from source to register. */ | |
3200 | ||
a78f21af | 3201 | static void |
29134980 OF |
3202 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
3203 | unsigned long source1, unsigned long source2) | |
3204 | { | |
3205 | unsigned long pc_mask; | |
3206 | unsigned long operation_mask; | |
3207 | ||
3208 | /* Find out how many bits the operation should apply to. */ | |
3209 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
3210 | { | |
3211 | pc_mask = 0xFFFFFF00; | |
3212 | operation_mask = 0xFF; | |
3213 | } | |
3214 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
3215 | { | |
3216 | pc_mask = 0xFFFF0000; | |
3217 | operation_mask = 0xFFFF; | |
3218 | } | |
3219 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
3220 | { | |
3221 | pc_mask = 0x0; | |
3222 | operation_mask = 0xFFFFFFFF; | |
3223 | } | |
3224 | else | |
3225 | { | |
3226 | /* The size is out of range. */ | |
3227 | inst_env->invalid = 1; | |
3228 | return; | |
3229 | } | |
3230 | ||
3231 | /* The instruction just works on uw_operation_mask bits. */ | |
3232 | source2 &= operation_mask; | |
3233 | source1 &= operation_mask; | |
3234 | ||
3235 | /* Now calculate the result. The opcode's 3 first bits separates | |
3236 | the different actions. */ | |
3237 | switch (cris_get_opcode (inst) & 7) | |
3238 | { | |
3239 | case 0: /* add */ | |
3240 | source1 += source2; | |
3241 | break; | |
3242 | ||
3243 | case 1: /* move */ | |
3244 | source1 = source2; | |
3245 | break; | |
3246 | ||
3247 | case 2: /* subtract */ | |
3248 | source1 -= source2; | |
3249 | break; | |
3250 | ||
3251 | case 3: /* compare */ | |
3252 | break; | |
3253 | ||
3254 | case 4: /* and */ | |
3255 | source1 &= source2; | |
3256 | break; | |
3257 | ||
3258 | case 5: /* or */ | |
3259 | source1 |= source2; | |
3260 | break; | |
3261 | ||
3262 | default: | |
3263 | inst_env->invalid = 1; | |
3264 | return; | |
3265 | ||
3266 | break; | |
3267 | } | |
3268 | ||
3269 | /* Make sure that the result doesn't contain more than the instruction | |
3270 | size bits. */ | |
3271 | source2 &= operation_mask; | |
3272 | ||
3273 | /* Calculate the new breakpoint address. */ | |
3274 | inst_env->reg[REG_PC] &= pc_mask; | |
3275 | inst_env->reg[REG_PC] |= source1; | |
3276 | ||
3277 | } | |
3278 | ||
3279 | /* Extends the value from either byte or word size to a dword. If the mode | |
3280 | is zero extend then the value is extended with zero. If instead the mode | |
3281 | is signed extend the sign bit of the value is taken into consideration. */ | |
3282 | ||
a78f21af | 3283 | static unsigned long |
29134980 OF |
3284 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
3285 | { | |
3286 | /* The size can be either byte or word, check which one it is. | |
3287 | Don't check the highest bit, it's indicating if it's a zero | |
3288 | or sign extend. */ | |
3289 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3290 | { | |
3291 | /* Word size. */ | |
3292 | value &= 0xFFFF; | |
3293 | ||
3294 | /* Check if the instruction is signed extend. If so, check if value has | |
3295 | the sign bit on. */ | |
3296 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) | |
3297 | { | |
3298 | value |= SIGNED_WORD_EXTEND_MASK; | |
3299 | } | |
3300 | } | |
3301 | else | |
3302 | { | |
3303 | /* Byte size. */ | |
3304 | value &= 0xFF; | |
3305 | ||
3306 | /* Check if the instruction is signed extend. If so, check if value has | |
3307 | the sign bit on. */ | |
3308 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) | |
3309 | { | |
3310 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3311 | } | |
3312 | } | |
3313 | /* The size should now be dword. */ | |
3314 | cris_set_size_to_dword (inst); | |
3315 | return value; | |
3316 | } | |
3317 | ||
3318 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3319 | instruction. The MOVE instruction is the move from source to register. */ | |
3320 | ||
a78f21af | 3321 | static void |
29134980 OF |
3322 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3323 | inst_env_type *inst_env) | |
3324 | { | |
3325 | unsigned long operand1; | |
3326 | unsigned long operand2; | |
3327 | ||
3328 | /* It's invalid to have a prefix to the instruction. This is a register | |
3329 | mode instruction and can't have a prefix. */ | |
3330 | if (inst_env->prefix_found) | |
3331 | { | |
3332 | inst_env->invalid = 1; | |
3333 | return; | |
3334 | } | |
3335 | /* Check if the instruction has PC as its target. */ | |
3336 | if (cris_get_operand2 (inst) == REG_PC) | |
3337 | { | |
3338 | if (inst_env->slot_needed) | |
3339 | { | |
3340 | inst_env->invalid = 1; | |
3341 | return; | |
3342 | } | |
3343 | /* The instruction has the PC as its target register. */ | |
7ab98e9e | 3344 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3345 | operand2 = inst_env->reg[REG_PC]; |
3346 | ||
3347 | /* Check if it's a extend, signed or zero instruction. */ | |
3348 | if (cris_get_opcode (inst) < 4) | |
3349 | { | |
3350 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3351 | } | |
3352 | /* Calculate the PC value after the instruction, i.e. where the | |
3353 | breakpoint should be. The order of the udw_operands is vital. */ | |
3354 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3355 | } | |
3356 | inst_env->slot_needed = 0; | |
3357 | inst_env->prefix_found = 0; | |
3358 | inst_env->xflag_found = 0; | |
3359 | inst_env->disable_interrupt = 0; | |
3360 | } | |
3361 | ||
3362 | /* Returns the data contained at address. The size of the data is derived from | |
3363 | the size of the operation. If the instruction is a zero or signed | |
3364 | extend instruction, the size field is changed in instruction. */ | |
3365 | ||
a78f21af | 3366 | static unsigned long |
29134980 OF |
3367 | get_data_from_address (unsigned short *inst, CORE_ADDR address) |
3368 | { | |
3369 | int size = cris_get_size (*inst); | |
3370 | unsigned long value; | |
3371 | ||
3372 | /* If it's an extend instruction we don't want the signed extend bit, | |
3373 | because it influences the size. */ | |
3374 | if (cris_get_opcode (*inst) < 4) | |
3375 | { | |
3376 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3377 | } | |
3378 | /* Is there a need for checking the size? Size should contain the number of | |
3379 | bytes to read. */ | |
3380 | size = 1 << size; | |
3381 | value = read_memory_unsigned_integer (address, size); | |
3382 | ||
3383 | /* Check if it's an extend, signed or zero instruction. */ | |
3384 | if (cris_get_opcode (*inst) < 4) | |
3385 | { | |
3386 | value = do_sign_or_zero_extend (value, inst); | |
3387 | } | |
3388 | return value; | |
3389 | } | |
3390 | ||
3391 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3392 | instructions. The MOVE instruction is the move from source to register. */ | |
3393 | ||
a78f21af | 3394 | static void |
29134980 OF |
3395 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
3396 | inst_env_type *inst_env) | |
3397 | { | |
3398 | unsigned long operand2; | |
3399 | unsigned long operand3; | |
3400 | ||
3401 | check_assign (inst, inst_env); | |
3402 | if (cris_get_operand2 (inst) == REG_PC) | |
3403 | { | |
3404 | operand2 = inst_env->reg[REG_PC]; | |
3405 | ||
3406 | /* Get the value of the third operand. */ | |
3407 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3408 | ||
3409 | /* Calculate the PC value after the instruction, i.e. where the | |
3410 | breakpoint should be. The order of the udw_operands is vital. */ | |
3411 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3412 | } | |
3413 | inst_env->slot_needed = 0; | |
3414 | inst_env->prefix_found = 0; | |
3415 | inst_env->xflag_found = 0; | |
3416 | inst_env->disable_interrupt = 0; | |
3417 | } | |
3418 | ||
3419 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3420 | OR instructions. Note that for this to work as expected, the calling | |
3421 | function must have made sure that there is a prefix to this instruction. */ | |
3422 | ||
a78f21af | 3423 | static void |
29134980 OF |
3424 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
3425 | inst_env_type *inst_env) | |
3426 | { | |
3427 | unsigned long operand2; | |
3428 | unsigned long operand3; | |
3429 | ||
3430 | if (cris_get_operand1 (inst) == REG_PC) | |
3431 | { | |
3432 | /* The PC will be changed by the instruction. */ | |
3433 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3434 | ||
3435 | /* Get the value of the third operand. */ | |
3436 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); | |
3437 | ||
3438 | /* Calculate the PC value after the instruction, i.e. where the | |
3439 | breakpoint should be. */ | |
3440 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3441 | } | |
3442 | inst_env->slot_needed = 0; | |
3443 | inst_env->prefix_found = 0; | |
3444 | inst_env->xflag_found = 0; | |
3445 | inst_env->disable_interrupt = 0; | |
3446 | } | |
3447 | ||
3448 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3449 | instructions. The MOVE instruction is the move from source to register. */ | |
3450 | ||
a78f21af | 3451 | static void |
29134980 OF |
3452 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
3453 | inst_env_type *inst_env) | |
3454 | { | |
3455 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3456 | { | |
3457 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
3458 | SUB, AND or OR something weird is going on (if everything works these | |
3459 | instructions should end up in the three operand version). */ | |
3460 | inst_env->invalid = 1; | |
3461 | return; | |
3462 | } | |
3463 | else | |
3464 | { | |
3465 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
3466 | so use it. */ | |
3467 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3468 | } | |
3469 | inst_env->slot_needed = 0; | |
3470 | inst_env->prefix_found = 0; | |
3471 | inst_env->xflag_found = 0; | |
3472 | inst_env->disable_interrupt = 0; | |
3473 | } | |
3474 | ||
3475 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3476 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3477 | source to register. */ | |
3478 | ||
a78f21af | 3479 | static void |
29134980 OF |
3480 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
3481 | inst_env_type *inst_env) | |
3482 | { | |
3483 | unsigned long operand1; | |
3484 | unsigned long operand2; | |
3485 | unsigned long operand3; | |
3486 | int size; | |
3487 | ||
3488 | /* The instruction is either an indirect or autoincrement addressing mode. | |
3489 | Check if the destination register is the PC. */ | |
3490 | if (cris_get_operand2 (inst) == REG_PC) | |
3491 | { | |
3492 | /* Must be done here, get_data_from_address may change the size | |
3493 | field. */ | |
3494 | size = cris_get_size (inst); | |
3495 | operand2 = inst_env->reg[REG_PC]; | |
3496 | ||
3497 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3498 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
3499 | operand3 = get_data_from_address (&inst, operand1); | |
3500 | ||
3501 | /* Calculate the PC value after the instruction, i.e. where the | |
3502 | breakpoint should be. The order of the udw_operands is vital. */ | |
3503 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); | |
3504 | } | |
3505 | /* If this is an autoincrement addressing mode, check if the increment | |
3506 | changes the PC. */ | |
3507 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) | |
3508 | { | |
3509 | /* Get the size field. */ | |
3510 | size = cris_get_size (inst); | |
3511 | ||
3512 | /* If it's an extend instruction we don't want the signed extend bit, | |
3513 | because it influences the size. */ | |
3514 | if (cris_get_opcode (inst) < 4) | |
3515 | { | |
3516 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3517 | } | |
3518 | process_autoincrement (size, inst, inst_env); | |
3519 | } | |
3520 | inst_env->slot_needed = 0; | |
3521 | inst_env->prefix_found = 0; | |
3522 | inst_env->xflag_found = 0; | |
3523 | inst_env->disable_interrupt = 0; | |
3524 | } | |
3525 | ||
3526 | /* Handles the two-operand addressing mode, all modes except register, for | |
3527 | the ADD, SUB CMP, AND and OR instruction. */ | |
3528 | ||
a78f21af | 3529 | static void |
29134980 OF |
3530 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
3531 | inst_env_type *inst_env) | |
3532 | { | |
3533 | if (inst_env->prefix_found) | |
3534 | { | |
3535 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
3536 | { | |
3537 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3538 | } | |
3539 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
3540 | { | |
3541 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3542 | } | |
3543 | else | |
3544 | { | |
3545 | /* The mode is invalid for a prefixed base instruction. */ | |
3546 | inst_env->invalid = 1; | |
3547 | return; | |
3548 | } | |
3549 | } | |
3550 | else | |
3551 | { | |
3552 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3553 | } | |
3554 | } | |
3555 | ||
3556 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3557 | ||
a78f21af | 3558 | static void |
29134980 OF |
3559 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3560 | { | |
3561 | unsigned long operand1; | |
3562 | unsigned long operand2; | |
3563 | ||
3564 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3565 | instruction and can't have a prefix. */ | |
3566 | if (inst_env->prefix_found) | |
3567 | { | |
3568 | inst_env->invalid = 1; | |
3569 | return; | |
3570 | } | |
3571 | ||
3572 | /* Check if the instruction has PC as its target. */ | |
3573 | if (cris_get_operand2 (inst) == REG_PC) | |
3574 | { | |
3575 | if (inst_env->slot_needed) | |
3576 | { | |
3577 | inst_env->invalid = 1; | |
3578 | return; | |
3579 | } | |
3580 | operand1 = cris_get_quick_value (inst); | |
3581 | operand2 = inst_env->reg[REG_PC]; | |
3582 | ||
3583 | /* The size should now be dword. */ | |
3584 | cris_set_size_to_dword (&inst); | |
3585 | ||
3586 | /* Calculate the PC value after the instruction, i.e. where the | |
3587 | breakpoint should be. */ | |
3588 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3589 | } | |
3590 | inst_env->slot_needed = 0; | |
3591 | inst_env->prefix_found = 0; | |
3592 | inst_env->xflag_found = 0; | |
3593 | inst_env->disable_interrupt = 0; | |
3594 | } | |
3595 | ||
3596 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3597 | ||
a78f21af | 3598 | static void |
29134980 OF |
3599 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3600 | { | |
3601 | unsigned long operand1; | |
3602 | unsigned long operand2; | |
3603 | ||
3604 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3605 | instruction and can't have a prefix. */ | |
3606 | if (inst_env->prefix_found) | |
3607 | { | |
3608 | inst_env->invalid = 1; | |
3609 | return; | |
3610 | } | |
3611 | /* Check if the instruction has PC as its target. */ | |
3612 | if (cris_get_operand2 (inst) == REG_PC) | |
3613 | { | |
3614 | if (inst_env->slot_needed) | |
3615 | { | |
3616 | inst_env->invalid = 1; | |
3617 | return; | |
3618 | } | |
3619 | /* The instruction has the PC as its target register. */ | |
3620 | operand1 = cris_get_quick_value (inst); | |
3621 | operand2 = inst_env->reg[REG_PC]; | |
3622 | ||
3623 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3624 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
3625 | { | |
3626 | /* sign extend */ | |
3627 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3628 | } | |
3629 | /* The size should now be dword. */ | |
3630 | cris_set_size_to_dword (&inst); | |
3631 | ||
3632 | /* Calculate the PC value after the instruction, i.e. where the | |
3633 | breakpoint should be. */ | |
3634 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); | |
3635 | } | |
3636 | inst_env->slot_needed = 0; | |
3637 | inst_env->prefix_found = 0; | |
3638 | inst_env->xflag_found = 0; | |
3639 | inst_env->disable_interrupt = 0; | |
3640 | } | |
3641 | ||
3642 | /* Translate op_type to a function and call it. */ | |
3643 | ||
a78f21af AC |
3644 | static void |
3645 | cris_gdb_func (enum cris_op_type op_type, unsigned short inst, | |
3646 | inst_env_type *inst_env) | |
29134980 OF |
3647 | { |
3648 | switch (op_type) | |
3649 | { | |
3650 | case cris_not_implemented_op: | |
3651 | not_implemented_op (inst, inst_env); | |
3652 | break; | |
3653 | ||
3654 | case cris_abs_op: | |
3655 | abs_op (inst, inst_env); | |
3656 | break; | |
3657 | ||
3658 | case cris_addi_op: | |
3659 | addi_op (inst, inst_env); | |
3660 | break; | |
3661 | ||
3662 | case cris_asr_op: | |
3663 | asr_op (inst, inst_env); | |
3664 | break; | |
3665 | ||
3666 | case cris_asrq_op: | |
3667 | asrq_op (inst, inst_env); | |
3668 | break; | |
3669 | ||
3670 | case cris_ax_ei_setf_op: | |
3671 | ax_ei_setf_op (inst, inst_env); | |
3672 | break; | |
3673 | ||
3674 | case cris_bdap_prefix: | |
3675 | bdap_prefix (inst, inst_env); | |
3676 | break; | |
3677 | ||
3678 | case cris_biap_prefix: | |
3679 | biap_prefix (inst, inst_env); | |
3680 | break; | |
3681 | ||
3682 | case cris_break_op: | |
3683 | break_op (inst, inst_env); | |
3684 | break; | |
3685 | ||
3686 | case cris_btst_nop_op: | |
3687 | btst_nop_op (inst, inst_env); | |
3688 | break; | |
3689 | ||
3690 | case cris_clearf_di_op: | |
3691 | clearf_di_op (inst, inst_env); | |
3692 | break; | |
3693 | ||
3694 | case cris_dip_prefix: | |
3695 | dip_prefix (inst, inst_env); | |
3696 | break; | |
3697 | ||
3698 | case cris_dstep_logshift_mstep_neg_not_op: | |
3699 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3700 | break; | |
3701 | ||
3702 | case cris_eight_bit_offset_branch_op: | |
3703 | eight_bit_offset_branch_op (inst, inst_env); | |
3704 | break; | |
3705 | ||
3706 | case cris_move_mem_to_reg_movem_op: | |
3707 | move_mem_to_reg_movem_op (inst, inst_env); | |
3708 | break; | |
3709 | ||
3710 | case cris_move_reg_to_mem_movem_op: | |
3711 | move_reg_to_mem_movem_op (inst, inst_env); | |
3712 | break; | |
3713 | ||
3714 | case cris_move_to_preg_op: | |
3715 | move_to_preg_op (inst, inst_env); | |
3716 | break; | |
3717 | ||
3718 | case cris_muls_op: | |
3719 | muls_op (inst, inst_env); | |
3720 | break; | |
3721 | ||
3722 | case cris_mulu_op: | |
3723 | mulu_op (inst, inst_env); | |
3724 | break; | |
3725 | ||
3726 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3727 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3728 | break; | |
3729 | ||
3730 | case cris_none_reg_mode_clear_test_op: | |
3731 | none_reg_mode_clear_test_op (inst, inst_env); | |
3732 | break; | |
3733 | ||
3734 | case cris_none_reg_mode_jump_op: | |
3735 | none_reg_mode_jump_op (inst, inst_env); | |
3736 | break; | |
3737 | ||
3738 | case cris_none_reg_mode_move_from_preg_op: | |
3739 | none_reg_mode_move_from_preg_op (inst, inst_env); | |
3740 | break; | |
3741 | ||
3742 | case cris_quick_mode_add_sub_op: | |
3743 | quick_mode_add_sub_op (inst, inst_env); | |
3744 | break; | |
3745 | ||
3746 | case cris_quick_mode_and_cmp_move_or_op: | |
3747 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3748 | break; | |
3749 | ||
3750 | case cris_quick_mode_bdap_prefix: | |
3751 | quick_mode_bdap_prefix (inst, inst_env); | |
3752 | break; | |
3753 | ||
3754 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3755 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3756 | break; | |
3757 | ||
3758 | case cris_reg_mode_clear_op: | |
3759 | reg_mode_clear_op (inst, inst_env); | |
3760 | break; | |
3761 | ||
3762 | case cris_reg_mode_jump_op: | |
3763 | reg_mode_jump_op (inst, inst_env); | |
3764 | break; | |
3765 | ||
3766 | case cris_reg_mode_move_from_preg_op: | |
3767 | reg_mode_move_from_preg_op (inst, inst_env); | |
3768 | break; | |
3769 | ||
3770 | case cris_reg_mode_test_op: | |
3771 | reg_mode_test_op (inst, inst_env); | |
3772 | break; | |
3773 | ||
3774 | case cris_scc_op: | |
3775 | scc_op (inst, inst_env); | |
3776 | break; | |
3777 | ||
3778 | case cris_sixteen_bit_offset_branch_op: | |
3779 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3780 | break; | |
3781 | ||
3782 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3783 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3784 | break; | |
3785 | ||
3786 | case cris_three_operand_bound_op: | |
3787 | three_operand_bound_op (inst, inst_env); | |
3788 | break; | |
3789 | ||
3790 | case cris_two_operand_bound_op: | |
3791 | two_operand_bound_op (inst, inst_env); | |
3792 | break; | |
3793 | ||
3794 | case cris_xor_op: | |
3795 | xor_op (inst, inst_env); | |
3796 | break; | |
3797 | } | |
3798 | } | |
3799 | ||
3800 | /* This wrapper is to avoid cris_get_assembler being called before | |
3801 | exec_bfd has been set. */ | |
3802 | ||
3803 | static int | |
a89aa300 | 3804 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
29134980 | 3805 | { |
a89aa300 | 3806 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
36482093 AC |
3807 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
3808 | disassembler, even when there is no BFD. Does something like | |
3809 | "gdb; target remote; disassmeble *0x123" work? */ | |
3810 | gdb_assert (exec_bfd != NULL); | |
a5f6c8f5 | 3811 | print_insn = cris_get_disassembler (exec_bfd); |
36482093 AC |
3812 | gdb_assert (print_insn != NULL); |
3813 | return print_insn (addr, info); | |
29134980 OF |
3814 | } |
3815 | ||
dbbff683 OF |
3816 | /* Copied from <asm/elf.h>. */ |
3817 | typedef unsigned long elf_greg_t; | |
3818 | ||
3819 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
c600d464 OF |
3820 | #define CRISV10_ELF_NGREG 35 |
3821 | typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG]; | |
3822 | ||
3823 | #define CRISV32_ELF_NGREG 32 | |
3824 | typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; | |
dbbff683 OF |
3825 | |
3826 | /* Unpack an elf_gregset_t into GDB's register cache. */ | |
3827 | ||
a78f21af | 3828 | static void |
dbbff683 OF |
3829 | supply_gregset (elf_gregset_t *gregsetp) |
3830 | { | |
c600d464 | 3831 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
dbbff683 OF |
3832 | int i; |
3833 | elf_greg_t *regp = *gregsetp; | |
3834 | static char zerobuf[4] = {0}; | |
3835 | ||
3836 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3837 | knows about the actual size of each register so that's no problem. */ | |
3838 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3839 | { | |
23a6d369 | 3840 | regcache_raw_supply (current_regcache, i, (char *)®p[i]); |
dbbff683 | 3841 | } |
c600d464 OF |
3842 | |
3843 | if (tdep->cris_version == 32) | |
3844 | { | |
3845 | /* Needed to set pseudo-register PC for CRISv32. */ | |
3846 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
3847 | be wrong. Issue a warning to alert the user. */ | |
3848 | regcache_raw_supply (current_regcache, PC_REGNUM, | |
3849 | (char *)®p[ERP_REGNUM]); | |
3850 | ||
3851 | if (*(char *)®p[ERP_REGNUM] & 0x1) | |
3852 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); | |
3853 | } | |
dbbff683 OF |
3854 | } |
3855 | ||
3856 | /* Use a local version of this function to get the correct types for | |
3857 | regsets, until multi-arch core support is ready. */ | |
3858 | ||
3859 | static void | |
3860 | fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, | |
3861 | int which, CORE_ADDR reg_addr) | |
3862 | { | |
3863 | elf_gregset_t gregset; | |
3864 | ||
3865 | switch (which) | |
3866 | { | |
3867 | case 0: | |
c600d464 OF |
3868 | if (core_reg_size != sizeof (elf_gregset_t) |
3869 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) | |
dbbff683 | 3870 | { |
8a3fe4f8 | 3871 | warning (_("wrong size gregset struct in core file")); |
dbbff683 OF |
3872 | } |
3873 | else | |
3874 | { | |
3875 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); | |
3876 | supply_gregset (&gregset); | |
3877 | } | |
3878 | ||
3879 | default: | |
3880 | /* We've covered all the kinds of registers we know about here, | |
3881 | so this must be something we wouldn't know what to do with | |
3882 | anyway. Just ignore it. */ | |
3883 | break; | |
3884 | } | |
3885 | } | |
3886 | ||
3887 | static struct core_fns cris_elf_core_fns = | |
3888 | { | |
3889 | bfd_target_elf_flavour, /* core_flavour */ | |
3890 | default_check_format, /* check_format */ | |
3891 | default_core_sniffer, /* core_sniffer */ | |
3892 | fetch_core_registers, /* core_read_registers */ | |
3893 | NULL /* next */ | |
3894 | }; | |
3895 | ||
3896 | /* Fetch (and possibly build) an appropriate link_map_offsets | |
8605d56e AC |
3897 | structure for native GNU/Linux CRIS targets using the struct |
3898 | offsets defined in link.h (but without actual reference to that | |
3899 | file). | |
dbbff683 | 3900 | |
8605d56e AC |
3901 | This makes it possible to access GNU/Linux CRIS shared libraries |
3902 | from a GDB that was not built on an GNU/Linux CRIS host (for cross | |
3903 | debugging). | |
dbbff683 OF |
3904 | |
3905 | See gdb/solib-svr4.h for an explanation of these fields. */ | |
3906 | ||
a78f21af | 3907 | static struct link_map_offsets * |
dbbff683 OF |
3908 | cris_linux_svr4_fetch_link_map_offsets (void) |
3909 | { | |
3910 | static struct link_map_offsets lmo; | |
3911 | static struct link_map_offsets *lmp = NULL; | |
3912 | ||
3913 | if (lmp == NULL) | |
3914 | { | |
3915 | lmp = &lmo; | |
3916 | ||
3917 | lmo.r_debug_size = 8; /* The actual size is 20 bytes, but | |
3918 | this is all we need. */ | |
3919 | lmo.r_map_offset = 4; | |
3920 | lmo.r_map_size = 4; | |
3921 | ||
3922 | lmo.link_map_size = 20; | |
3923 | ||
3924 | lmo.l_addr_offset = 0; | |
3925 | lmo.l_addr_size = 4; | |
3926 | ||
3927 | lmo.l_name_offset = 4; | |
3928 | lmo.l_name_size = 4; | |
3929 | ||
3930 | lmo.l_next_offset = 12; | |
3931 | lmo.l_next_size = 4; | |
3932 | ||
3933 | lmo.l_prev_offset = 16; | |
3934 | lmo.l_prev_size = 4; | |
3935 | } | |
3936 | ||
3937 | return lmp; | |
3938 | } | |
3939 | ||
a78f21af AC |
3940 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
3941 | ||
29134980 OF |
3942 | void |
3943 | _initialize_cris_tdep (void) | |
3944 | { | |
a5f6c8f5 OF |
3945 | static struct cmd_list_element *cris_set_cmdlist; |
3946 | static struct cmd_list_element *cris_show_cmdlist; | |
3947 | ||
29134980 OF |
3948 | struct cmd_list_element *c; |
3949 | ||
3950 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); | |
3951 | ||
29134980 | 3952 | /* CRIS-specific user-commands. */ |
a5f6c8f5 OF |
3953 | add_setshow_uinteger_cmd ("cris-version", class_support, |
3954 | &usr_cmd_cris_version, | |
7915a72c AC |
3955 | _("Set the current CRIS version."), |
3956 | _("Show the current CRIS version."), | |
bdd56253 OF |
3957 | _("\ |
3958 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ | |
3959 | Defaults to 10. "), | |
2c5b56ce | 3960 | set_cris_version, |
7915a72c | 3961 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ |
a5f6c8f5 | 3962 | &setlist, &showlist); |
0e6bdb31 OF |
3963 | |
3964 | add_setshow_enum_cmd ("cris-mode", class_support, | |
3965 | cris_modes, &usr_cmd_cris_mode, | |
3966 | _("Set the current CRIS mode."), | |
3967 | _("Show the current CRIS mode."), | |
bdd56253 OF |
3968 | _("\ |
3969 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ | |
3970 | Makes GDB use the NRP register instead of the ERP register in certain cases."), | |
0e6bdb31 OF |
3971 | set_cris_mode, |
3972 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ | |
3973 | &setlist, &showlist); | |
dbbff683 | 3974 | |
a5f6c8f5 OF |
3975 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
3976 | &usr_cmd_cris_dwarf2_cfi, | |
7915a72c AC |
3977 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
3978 | _("Show the usage of Dwarf-2 CFI for CRIS."), | |
bdd56253 | 3979 | _("Set this to \"off\" if using gcc-cris < R59."), |
2c5b56ce | 3980 | set_cris_dwarf2_cfi, |
7915a72c | 3981 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */ |
a5f6c8f5 OF |
3982 | &setlist, &showlist); |
3983 | ||
52bd1401 | 3984 | deprecated_add_core_fns (&cris_elf_core_fns); |
29134980 OF |
3985 | } |
3986 | ||
3987 | /* Prints out all target specific values. */ | |
3988 | ||
3989 | static void | |
3990 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3991 | { | |
3992 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3993 | if (tdep != NULL) | |
3994 | { | |
3995 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", | |
3996 | tdep->cris_version); | |
0e6bdb31 OF |
3997 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
3998 | tdep->cris_mode); | |
a5f6c8f5 OF |
3999 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
4000 | tdep->cris_dwarf2_cfi); | |
29134980 OF |
4001 | } |
4002 | } | |
4003 | ||
4004 | static void | |
a5f6c8f5 OF |
4005 | set_cris_version (char *ignore_args, int from_tty, |
4006 | struct cmd_list_element *c) | |
29134980 OF |
4007 | { |
4008 | struct gdbarch_info info; | |
4009 | ||
a5f6c8f5 | 4010 | usr_cmd_cris_version_valid = 1; |
29134980 | 4011 | |
a5f6c8f5 OF |
4012 | /* Update the current architecture, if needed. */ |
4013 | gdbarch_info_init (&info); | |
4014 | if (!gdbarch_update_p (info)) | |
4015 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4016 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4017 | } |
4018 | ||
0e6bdb31 OF |
4019 | static void |
4020 | set_cris_mode (char *ignore_args, int from_tty, | |
4021 | struct cmd_list_element *c) | |
4022 | { | |
4023 | struct gdbarch_info info; | |
4024 | ||
4025 | /* Update the current architecture, if needed. */ | |
4026 | gdbarch_info_init (&info); | |
4027 | if (!gdbarch_update_p (info)) | |
4028 | internal_error (__FILE__, __LINE__, | |
4029 | "cris_gdbarch_update: failed to update architecture."); | |
4030 | } | |
4031 | ||
29134980 | 4032 | static void |
a5f6c8f5 OF |
4033 | set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
4034 | struct cmd_list_element *c) | |
29134980 OF |
4035 | { |
4036 | struct gdbarch_info info; | |
a5f6c8f5 OF |
4037 | |
4038 | /* Update the current architecture, if needed. */ | |
4039 | gdbarch_info_init (&info); | |
4040 | if (!gdbarch_update_p (info)) | |
4041 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4042 | _("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
4043 | } |
4044 | ||
29134980 OF |
4045 | static struct gdbarch * |
4046 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
4047 | { | |
4048 | struct gdbarch *gdbarch; | |
4049 | struct gdbarch_tdep *tdep; | |
4050 | int cris_version; | |
29134980 OF |
4051 | |
4052 | if (usr_cmd_cris_version_valid) | |
4053 | { | |
4054 | /* Trust the user's CRIS version setting. */ | |
4055 | cris_version = usr_cmd_cris_version; | |
4056 | } | |
c600d464 OF |
4057 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
4058 | { | |
4059 | cris_version = 32; | |
4060 | } | |
29134980 OF |
4061 | else |
4062 | { | |
4063 | /* Assume it's CRIS version 10. */ | |
4064 | cris_version = 10; | |
4065 | } | |
4066 | ||
29134980 OF |
4067 | /* Make the current settings visible to the user. */ |
4068 | usr_cmd_cris_version = cris_version; | |
29134980 | 4069 | |
0e6bdb31 | 4070 | /* Find a candidate among the list of pre-declared architectures. */ |
29134980 OF |
4071 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
4072 | arches != NULL; | |
4073 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4074 | { | |
a5f6c8f5 OF |
4075 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
4076 | == usr_cmd_cris_version) | |
0e6bdb31 OF |
4077 | && (gdbarch_tdep (arches->gdbarch)->cris_mode |
4078 | == usr_cmd_cris_mode) | |
a5f6c8f5 OF |
4079 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi |
4080 | == usr_cmd_cris_dwarf2_cfi)) | |
29134980 OF |
4081 | return arches->gdbarch; |
4082 | } | |
4083 | ||
4084 | /* No matching architecture was found. Create a new one. */ | |
4085 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
4086 | gdbarch = gdbarch_alloc (&info, tdep); | |
4087 | ||
a5f6c8f5 | 4088 | tdep->cris_version = usr_cmd_cris_version; |
0e6bdb31 | 4089 | tdep->cris_mode = usr_cmd_cris_mode; |
a5f6c8f5 | 4090 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
29134980 OF |
4091 | |
4092 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ | |
4093 | switch (info.byte_order) | |
4094 | { | |
778eb05e | 4095 | case BFD_ENDIAN_LITTLE: |
29134980 OF |
4096 | /* Ok. */ |
4097 | break; | |
4098 | ||
d7449b42 | 4099 | case BFD_ENDIAN_BIG: |
e2e0b3e5 | 4100 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: big endian byte order in info")); |
29134980 OF |
4101 | break; |
4102 | ||
4103 | default: | |
e2e0b3e5 | 4104 | internal_error (__FILE__, __LINE__, _("cris_gdbarch_init: unknown byte order in info")); |
29134980 OF |
4105 | } |
4106 | ||
b4206d25 | 4107 | set_gdbarch_return_value (gdbarch, cris_return_value); |
2e4b5889 OF |
4108 | set_gdbarch_deprecated_reg_struct_has_addr (gdbarch, |
4109 | cris_reg_struct_has_addr); | |
b5622e8d | 4110 | set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); |
29134980 | 4111 | |
29134980 | 4112 | set_gdbarch_sp_regnum (gdbarch, 14); |
c600d464 OF |
4113 | |
4114 | /* Length of ordinary registers used in push_word and a few other | |
4115 | places. register_size() is the real way to know how big a | |
4116 | register is. */ | |
a5f6c8f5 | 4117 | |
2e4b5889 OF |
4118 | set_gdbarch_double_bit (gdbarch, 64); |
4119 | /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT, | |
4120 | which means we have to set this explicitly. */ | |
c600d464 | 4121 | set_gdbarch_long_double_bit (gdbarch, 64); |
29134980 | 4122 | |
29134980 OF |
4123 | /* The total amount of space needed to store (in an array called registers) |
4124 | GDB's copy of the machine's register state. Note: We can not use | |
4125 | cris_register_size at this point, since it relies on current_gdbarch | |
4126 | being set. */ | |
4127 | switch (tdep->cris_version) | |
4128 | { | |
4129 | case 0: | |
4130 | case 1: | |
4131 | case 2: | |
4132 | case 3: | |
29134980 OF |
4133 | case 8: |
4134 | case 9: | |
a5f6c8f5 OF |
4135 | /* Old versions; not supported. */ |
4136 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 4137 | _("cris_gdbarch_init: unsupported CRIS version")); |
29134980 OF |
4138 | break; |
4139 | ||
4140 | case 10: | |
4141 | case 11: | |
4142 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
4143 | P7 (32 bits), and P15 (32 bits) have been implemented. */ | |
c600d464 OF |
4144 | set_gdbarch_pc_regnum (gdbarch, 15); |
4145 | set_gdbarch_register_type (gdbarch, cris_register_type); | |
4146 | /* There are 32 registers (some of which may not be implemented). */ | |
4147 | set_gdbarch_num_regs (gdbarch, 32); | |
4148 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
4149 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
4150 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
4151 | ||
4152 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
4153 | break; | |
4154 | ||
4155 | case 32: | |
4156 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers | |
4157 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) | |
4158 | and pseudo-register PC (32 bits). */ | |
4159 | set_gdbarch_pc_regnum (gdbarch, 32); | |
4160 | set_gdbarch_register_type (gdbarch, crisv32_register_type); | |
4161 | /* 32 registers + pseudo-register PC + 16 support registers. */ | |
4162 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); | |
4163 | set_gdbarch_register_name (gdbarch, crisv32_register_name); | |
4164 | ||
4165 | set_gdbarch_cannot_store_register | |
4166 | (gdbarch, crisv32_cannot_store_register); | |
4167 | set_gdbarch_cannot_fetch_register | |
4168 | (gdbarch, crisv32_cannot_fetch_register); | |
4169 | ||
4170 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
4171 | ||
4172 | set_gdbarch_single_step_through_delay | |
4173 | (gdbarch, crisv32_single_step_through_delay); | |
4174 | ||
29134980 OF |
4175 | break; |
4176 | ||
4177 | default: | |
c600d464 | 4178 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 4179 | _("cris_gdbarch_init: unknown CRIS version")); |
29134980 OF |
4180 | } |
4181 | ||
c600d464 OF |
4182 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
4183 | have the same ABI). */ | |
2e4b5889 OF |
4184 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
4185 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
4186 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 4187 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
4188 | |
4189 | /* The stack grows downward. */ | |
4190 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4191 | ||
4192 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); | |
4193 | ||
2e4b5889 OF |
4194 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
4195 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); | |
4196 | set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id); | |
4197 | ||
a5f6c8f5 OF |
4198 | if (tdep->cris_dwarf2_cfi == 1) |
4199 | { | |
4200 | /* Hook in the Dwarf-2 frame sniffer. */ | |
4201 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); | |
4202 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); | |
4203 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
4204 | } | |
4205 | ||
0e6bdb31 OF |
4206 | if (tdep->cris_mode != cris_mode_guru) |
4207 | { | |
4208 | frame_unwind_append_sniffer (gdbarch, cris_sigtramp_frame_sniffer); | |
4209 | } | |
a5f6c8f5 | 4210 | |
2e4b5889 OF |
4211 | frame_unwind_append_sniffer (gdbarch, cris_frame_sniffer); |
4212 | frame_base_set_default (gdbarch, &cris_frame_base); | |
6c0e89ed | 4213 | |
dbbff683 OF |
4214 | /* Use target_specific function to define link map offsets. */ |
4215 | set_solib_svr4_fetch_link_map_offsets | |
4216 | (gdbarch, cris_linux_svr4_fetch_link_map_offsets); | |
4217 | ||
36482093 AC |
4218 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
4219 | disassembler, even when there is no BFD. Does something like | |
4220 | "gdb; target remote; disassmeble *0x123" work? */ | |
4221 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); | |
4222 | ||
29134980 OF |
4223 | return gdbarch; |
4224 | } |