Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
d9fcf2fb | 2 | Copyright (C) 1996, 1997, 2000 Free Software Foundation, Inc. |
c906108c | 3 | |
c5aa993b | 4 | This file is part of GDB. |
c906108c | 5 | |
c5aa993b JM |
6 | This program is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
c906108c | 10 | |
c5aa993b JM |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
c906108c | 15 | |
c5aa993b JM |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
20 | |
21 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
22 | ||
23 | #include "defs.h" | |
24 | #include "frame.h" | |
25 | #include "obstack.h" | |
26 | #include "symtab.h" | |
27 | #include "gdbtypes.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdb_string.h" | |
31 | #include "value.h" | |
32 | #include "inferior.h" | |
c5aa993b | 33 | #include "dis-asm.h" |
c906108c SS |
34 | #include "symfile.h" |
35 | #include "objfiles.h" | |
104c1213 | 36 | #include "language.h" |
28d069e6 | 37 | #include "arch-utils.h" |
c906108c | 38 | |
f0d4cc9e | 39 | #include "floatformat.h" |
4ce44c66 JM |
40 | #include "sim-d10v.h" |
41 | ||
42 | #undef XMALLOC | |
43 | #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE))) | |
44 | ||
cce74817 | 45 | struct frame_extra_info |
c5aa993b JM |
46 | { |
47 | CORE_ADDR return_pc; | |
48 | int frameless; | |
49 | int size; | |
50 | }; | |
cce74817 | 51 | |
4ce44c66 JM |
52 | struct gdbarch_tdep |
53 | { | |
54 | int a0_regnum; | |
55 | int nr_dmap_regs; | |
56 | unsigned long (*dmap_register) (int nr); | |
57 | unsigned long (*imap_register) (int nr); | |
58 | int (*register_sim_regno) (int nr); | |
59 | }; | |
60 | ||
61 | /* These are the addresses the D10V-EVA board maps data and | |
62 | instruction memory to. */ | |
cce74817 | 63 | |
cff3e48b | 64 | #define DMEM_START 0x2000000 |
cce74817 JM |
65 | #define IMEM_START 0x1000000 |
66 | #define STACK_START 0x0007ffe | |
67 | ||
4ce44c66 JM |
68 | /* d10v register names. */ |
69 | ||
70 | enum | |
71 | { | |
72 | R0_REGNUM = 0, | |
73 | LR_REGNUM = 13, | |
74 | PSW_REGNUM = 16, | |
75 | NR_IMAP_REGS = 2, | |
76 | NR_A_REGS = 2 | |
77 | }; | |
78 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) | |
79 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
80 | ||
81 | /* d10v calling convention. */ | |
cce74817 JM |
82 | |
83 | #define ARG1_REGNUM R0_REGNUM | |
84 | #define ARGN_REGNUM 3 | |
85 | #define RET1_REGNUM R0_REGNUM | |
86 | ||
392a587b JM |
87 | /* Local functions */ |
88 | ||
a14ed312 | 89 | extern void _initialize_d10v_tdep (void); |
392a587b | 90 | |
a14ed312 | 91 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 92 | |
a14ed312 | 93 | static void d10v_eva_get_trace_data (void); |
c906108c | 94 | |
a14ed312 KB |
95 | static int prologue_find_regs (unsigned short op, struct frame_info *fi, |
96 | CORE_ADDR addr); | |
cce74817 | 97 | |
a14ed312 | 98 | extern void d10v_frame_init_saved_regs (struct frame_info *); |
cce74817 | 99 | |
a14ed312 | 100 | static void do_d10v_pop_frame (struct frame_info *fi); |
cce74817 | 101 | |
c906108c SS |
102 | int |
103 | d10v_frame_chain_valid (chain, frame) | |
104 | CORE_ADDR chain; | |
c5aa993b | 105 | struct frame_info *frame; /* not used here */ |
c906108c SS |
106 | { |
107 | return ((chain) != 0 && (frame) != 0 && (frame)->pc > IMEM_START); | |
108 | } | |
109 | ||
23964bcd | 110 | static CORE_ADDR |
489137c0 AC |
111 | d10v_stack_align (CORE_ADDR len) |
112 | { | |
113 | return (len + 1) & ~1; | |
114 | } | |
c906108c SS |
115 | |
116 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
117 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
118 | and TYPE is the type (which is known to be struct, union or array). | |
119 | ||
120 | The d10v returns anything less than 8 bytes in size in | |
121 | registers. */ | |
122 | ||
123 | int | |
fba45db2 | 124 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c SS |
125 | { |
126 | return (TYPE_LENGTH (type) > 8); | |
127 | } | |
128 | ||
129 | ||
392a587b | 130 | unsigned char * |
fba45db2 | 131 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 132 | { |
c5aa993b JM |
133 | static unsigned char breakpoint[] = |
134 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
135 | *lenptr = sizeof (breakpoint); |
136 | return breakpoint; | |
137 | } | |
138 | ||
4ce44c66 JM |
139 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
140 | when the reg_nr isn't valid. */ | |
141 | ||
142 | enum ts2_regnums | |
143 | { | |
144 | TS2_IMAP0_REGNUM = 32, | |
145 | TS2_DMAP_REGNUM = 34, | |
146 | TS2_NR_DMAP_REGS = 1, | |
147 | TS2_A0_REGNUM = 35 | |
148 | }; | |
149 | ||
150 | static char * | |
151 | d10v_ts2_register_name (int reg_nr) | |
392a587b | 152 | { |
c5aa993b JM |
153 | static char *register_names[] = |
154 | { | |
155 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
156 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
157 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
158 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
159 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
160 | }; |
161 | if (reg_nr < 0) | |
162 | return NULL; | |
163 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
164 | return NULL; | |
c5aa993b | 165 | return register_names[reg_nr]; |
392a587b JM |
166 | } |
167 | ||
4ce44c66 JM |
168 | enum ts3_regnums |
169 | { | |
170 | TS3_IMAP0_REGNUM = 36, | |
171 | TS3_DMAP0_REGNUM = 38, | |
172 | TS3_NR_DMAP_REGS = 4, | |
173 | TS3_A0_REGNUM = 32 | |
174 | }; | |
175 | ||
176 | static char * | |
177 | d10v_ts3_register_name (int reg_nr) | |
178 | { | |
179 | static char *register_names[] = | |
180 | { | |
181 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
182 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
183 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
184 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
185 | "a0", "a1", | |
186 | "spi", "spu", | |
187 | "imap0", "imap1", | |
188 | "dmap0", "dmap1", "dmap2", "dmap3" | |
189 | }; | |
190 | if (reg_nr < 0) | |
191 | return NULL; | |
192 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
193 | return NULL; | |
194 | return register_names[reg_nr]; | |
195 | } | |
196 | ||
197 | /* Access the DMAP/IMAP registers in a target independant way. */ | |
198 | ||
199 | static unsigned long | |
200 | d10v_ts2_dmap_register (int reg_nr) | |
201 | { | |
202 | switch (reg_nr) | |
203 | { | |
204 | case 0: | |
205 | case 1: | |
206 | return 0x2000; | |
207 | case 2: | |
208 | return read_register (TS2_DMAP_REGNUM); | |
209 | default: | |
210 | return 0; | |
211 | } | |
212 | } | |
213 | ||
214 | static unsigned long | |
215 | d10v_ts3_dmap_register (int reg_nr) | |
216 | { | |
217 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
218 | } | |
219 | ||
220 | static unsigned long | |
221 | d10v_dmap_register (int reg_nr) | |
222 | { | |
223 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
224 | } | |
225 | ||
226 | static unsigned long | |
227 | d10v_ts2_imap_register (int reg_nr) | |
228 | { | |
229 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
230 | } | |
231 | ||
232 | static unsigned long | |
233 | d10v_ts3_imap_register (int reg_nr) | |
234 | { | |
235 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
236 | } | |
237 | ||
238 | static unsigned long | |
239 | d10v_imap_register (int reg_nr) | |
240 | { | |
241 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
242 | } | |
243 | ||
244 | /* MAP GDB's internal register numbering (determined by the layout fo | |
245 | the REGISTER_BYTE array) onto the simulator's register | |
246 | numbering. */ | |
247 | ||
248 | static int | |
249 | d10v_ts2_register_sim_regno (int nr) | |
250 | { | |
251 | if (nr >= TS2_IMAP0_REGNUM | |
252 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
253 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
254 | if (nr == TS2_DMAP_REGNUM) | |
255 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
256 | if (nr >= TS2_A0_REGNUM | |
257 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
258 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
259 | return nr; | |
260 | } | |
261 | ||
262 | static int | |
263 | d10v_ts3_register_sim_regno (int nr) | |
264 | { | |
265 | if (nr >= TS3_IMAP0_REGNUM | |
266 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
267 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
268 | if (nr >= TS3_DMAP0_REGNUM | |
269 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
270 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
271 | if (nr >= TS3_A0_REGNUM | |
272 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
273 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
274 | return nr; | |
275 | } | |
276 | ||
277 | int | |
278 | d10v_register_sim_regno (int nr) | |
279 | { | |
280 | return gdbarch_tdep (current_gdbarch)->register_sim_regno (nr); | |
281 | } | |
392a587b JM |
282 | |
283 | /* Index within `registers' of the first byte of the space for | |
284 | register REG_NR. */ | |
285 | ||
286 | int | |
fba45db2 | 287 | d10v_register_byte (int reg_nr) |
392a587b | 288 | { |
4ce44c66 | 289 | if (reg_nr < A0_REGNUM) |
392a587b | 290 | return (reg_nr * 2); |
4ce44c66 JM |
291 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
292 | return (A0_REGNUM * 2 | |
293 | + (reg_nr - A0_REGNUM) * 8); | |
294 | else | |
295 | return (A0_REGNUM * 2 | |
296 | + NR_A_REGS * 8 | |
297 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
298 | } |
299 | ||
300 | /* Number of bytes of storage in the actual machine representation for | |
301 | register REG_NR. */ | |
302 | ||
303 | int | |
fba45db2 | 304 | d10v_register_raw_size (int reg_nr) |
392a587b | 305 | { |
4ce44c66 JM |
306 | if (reg_nr < A0_REGNUM) |
307 | return 2; | |
308 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
309 | return 8; |
310 | else | |
311 | return 2; | |
312 | } | |
313 | ||
314 | /* Number of bytes of storage in the program's representation | |
315 | for register N. */ | |
316 | ||
317 | int | |
fba45db2 | 318 | d10v_register_virtual_size (int reg_nr) |
392a587b | 319 | { |
4ce44c66 | 320 | return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr)); |
392a587b JM |
321 | } |
322 | ||
323 | /* Return the GDB type object for the "standard" data type | |
324 | of data in register N. */ | |
325 | ||
326 | struct type * | |
fba45db2 | 327 | d10v_register_virtual_type (int reg_nr) |
392a587b | 328 | { |
4ce44c66 JM |
329 | if (reg_nr >= A0_REGNUM |
330 | && reg_nr < (A0_REGNUM + NR_A_REGS)) | |
331 | return builtin_type_int64; | |
332 | else if (reg_nr == PC_REGNUM | |
333 | || reg_nr == SP_REGNUM) | |
334 | return builtin_type_int32; | |
392a587b | 335 | else |
4ce44c66 | 336 | return builtin_type_int16; |
392a587b JM |
337 | } |
338 | ||
392a587b | 339 | /* convert $pc and $sp to/from virtual addresses */ |
ac9a91a7 | 340 | int |
fba45db2 | 341 | d10v_register_convertible (int nr) |
ac9a91a7 JM |
342 | { |
343 | return ((nr) == PC_REGNUM || (nr) == SP_REGNUM); | |
344 | } | |
345 | ||
346 | void | |
fba45db2 KB |
347 | d10v_register_convert_to_virtual (int regnum, struct type *type, char *from, |
348 | char *to) | |
ac9a91a7 JM |
349 | { |
350 | ULONGEST x = extract_unsigned_integer (from, REGISTER_RAW_SIZE (regnum)); | |
351 | if (regnum == PC_REGNUM) | |
352 | x = (x << 2) | IMEM_START; | |
353 | else | |
354 | x |= DMEM_START; | |
355 | store_unsigned_integer (to, TYPE_LENGTH (type), x); | |
392a587b | 356 | } |
ac9a91a7 JM |
357 | |
358 | void | |
fba45db2 KB |
359 | d10v_register_convert_to_raw (struct type *type, int regnum, char *from, |
360 | char *to) | |
ac9a91a7 JM |
361 | { |
362 | ULONGEST x = extract_unsigned_integer (from, TYPE_LENGTH (type)); | |
363 | x &= 0x3ffff; | |
364 | if (regnum == PC_REGNUM) | |
365 | x >>= 2; | |
366 | store_unsigned_integer (to, 2, x); | |
392a587b | 367 | } |
ac9a91a7 | 368 | |
392a587b JM |
369 | |
370 | CORE_ADDR | |
fba45db2 | 371 | d10v_make_daddr (CORE_ADDR x) |
392a587b JM |
372 | { |
373 | return ((x) | DMEM_START); | |
374 | } | |
375 | ||
376 | CORE_ADDR | |
fba45db2 | 377 | d10v_make_iaddr (CORE_ADDR x) |
392a587b JM |
378 | { |
379 | return (((x) << 2) | IMEM_START); | |
380 | } | |
381 | ||
382 | int | |
fba45db2 | 383 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
384 | { |
385 | return (((x) & 0x3000000) == DMEM_START); | |
386 | } | |
387 | ||
388 | int | |
fba45db2 | 389 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
390 | { |
391 | return (((x) & 0x3000000) == IMEM_START); | |
392 | } | |
393 | ||
394 | ||
395 | CORE_ADDR | |
fba45db2 | 396 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
397 | { |
398 | return (((x) >> 2) & 0xffff); | |
399 | } | |
400 | ||
401 | CORE_ADDR | |
fba45db2 | 402 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
403 | { |
404 | return ((x) & 0xffff); | |
405 | } | |
406 | ||
407 | /* Store the address of the place in which to copy the structure the | |
408 | subroutine will return. This is called from call_function. | |
409 | ||
410 | We store structs through a pointer passed in the first Argument | |
411 | register. */ | |
412 | ||
413 | void | |
fba45db2 | 414 | d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
392a587b JM |
415 | { |
416 | write_register (ARG1_REGNUM, (addr)); | |
417 | } | |
418 | ||
419 | /* Write into appropriate registers a function return value | |
420 | of type TYPE, given in virtual format. | |
421 | ||
422 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
423 | ||
424 | void | |
fba45db2 | 425 | d10v_store_return_value (struct type *type, char *valbuf) |
392a587b JM |
426 | { |
427 | write_register_bytes (REGISTER_BYTE (RET1_REGNUM), | |
428 | valbuf, | |
429 | TYPE_LENGTH (type)); | |
430 | } | |
431 | ||
432 | /* Extract from an array REGBUF containing the (raw) register state | |
433 | the address in which a function should return its structure value, | |
434 | as a CORE_ADDR (or an expression that can be used as one). */ | |
435 | ||
436 | CORE_ADDR | |
fba45db2 | 437 | d10v_extract_struct_value_address (char *regbuf) |
392a587b JM |
438 | { |
439 | return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM), | |
440 | REGISTER_RAW_SIZE (ARG1_REGNUM)) | |
441 | | DMEM_START); | |
442 | } | |
443 | ||
444 | CORE_ADDR | |
fba45db2 | 445 | d10v_frame_saved_pc (struct frame_info *frame) |
392a587b | 446 | { |
cce74817 | 447 | return ((frame)->extra_info->return_pc); |
392a587b JM |
448 | } |
449 | ||
450 | CORE_ADDR | |
fba45db2 | 451 | d10v_frame_args_address (struct frame_info *fi) |
392a587b JM |
452 | { |
453 | return (fi)->frame; | |
454 | } | |
455 | ||
456 | CORE_ADDR | |
fba45db2 | 457 | d10v_frame_locals_address (struct frame_info *fi) |
392a587b JM |
458 | { |
459 | return (fi)->frame; | |
460 | } | |
461 | ||
462 | /* Immediately after a function call, return the saved pc. We can't | |
463 | use frame->return_pc beause that is determined by reading R13 off | |
464 | the stack and that may not be written yet. */ | |
465 | ||
466 | CORE_ADDR | |
fba45db2 | 467 | d10v_saved_pc_after_call (struct frame_info *frame) |
392a587b | 468 | { |
c5aa993b | 469 | return ((read_register (LR_REGNUM) << 2) |
392a587b JM |
470 | | IMEM_START); |
471 | } | |
472 | ||
c906108c SS |
473 | /* Discard from the stack the innermost frame, restoring all saved |
474 | registers. */ | |
475 | ||
476 | void | |
fba45db2 | 477 | d10v_pop_frame (void) |
cce74817 JM |
478 | { |
479 | generic_pop_current_frame (do_d10v_pop_frame); | |
480 | } | |
481 | ||
482 | static void | |
fba45db2 | 483 | do_d10v_pop_frame (struct frame_info *fi) |
c906108c SS |
484 | { |
485 | CORE_ADDR fp; | |
486 | int regnum; | |
c906108c SS |
487 | char raw_buffer[8]; |
488 | ||
cce74817 | 489 | fp = FRAME_FP (fi); |
c906108c SS |
490 | /* fill out fsr with the address of where each */ |
491 | /* register was stored in the frame */ | |
cce74817 | 492 | d10v_frame_init_saved_regs (fi); |
c5aa993b | 493 | |
c906108c | 494 | /* now update the current registers with the old values */ |
4ce44c66 | 495 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) |
c906108c | 496 | { |
cce74817 | 497 | if (fi->saved_regs[regnum]) |
c906108c | 498 | { |
c5aa993b JM |
499 | read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); |
500 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
501 | } |
502 | } | |
503 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
504 | { | |
cce74817 | 505 | if (fi->saved_regs[regnum]) |
c906108c | 506 | { |
c5aa993b | 507 | write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum))); |
c906108c SS |
508 | } |
509 | } | |
cce74817 | 510 | if (fi->saved_regs[PSW_REGNUM]) |
c906108c | 511 | { |
c5aa993b | 512 | write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); |
c906108c SS |
513 | } |
514 | ||
515 | write_register (PC_REGNUM, read_register (LR_REGNUM)); | |
cce74817 | 516 | write_register (SP_REGNUM, fp + fi->extra_info->size); |
c906108c SS |
517 | target_store_registers (-1); |
518 | flush_cached_frames (); | |
519 | } | |
520 | ||
c5aa993b | 521 | static int |
fba45db2 | 522 | check_prologue (unsigned short op) |
c906108c SS |
523 | { |
524 | /* st rn, @-sp */ | |
525 | if ((op & 0x7E1F) == 0x6C1F) | |
526 | return 1; | |
527 | ||
528 | /* st2w rn, @-sp */ | |
529 | if ((op & 0x7E3F) == 0x6E1F) | |
530 | return 1; | |
531 | ||
532 | /* subi sp, n */ | |
533 | if ((op & 0x7FE1) == 0x01E1) | |
534 | return 1; | |
535 | ||
536 | /* mv r11, sp */ | |
537 | if (op == 0x417E) | |
538 | return 1; | |
539 | ||
540 | /* nop */ | |
541 | if (op == 0x5E00) | |
542 | return 1; | |
543 | ||
544 | /* st rn, @sp */ | |
545 | if ((op & 0x7E1F) == 0x681E) | |
546 | return 1; | |
547 | ||
548 | /* st2w rn, @sp */ | |
c5aa993b JM |
549 | if ((op & 0x7E3F) == 0x3A1E) |
550 | return 1; | |
c906108c SS |
551 | |
552 | return 0; | |
553 | } | |
554 | ||
555 | CORE_ADDR | |
fba45db2 | 556 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
557 | { |
558 | unsigned long op; | |
559 | unsigned short op1, op2; | |
560 | CORE_ADDR func_addr, func_end; | |
561 | struct symtab_and_line sal; | |
562 | ||
563 | /* If we have line debugging information, then the end of the */ | |
564 | /* prologue should the first assembly instruction of the first source line */ | |
565 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
566 | { | |
567 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 568 | if (sal.end && sal.end < func_end) |
c906108c SS |
569 | return sal.end; |
570 | } | |
c5aa993b JM |
571 | |
572 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
573 | return pc; /* Can't access it -- assume no prologue. */ |
574 | ||
575 | while (1) | |
576 | { | |
c5aa993b | 577 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
578 | if ((op & 0xC0000000) == 0xC0000000) |
579 | { | |
580 | /* long instruction */ | |
c5aa993b JM |
581 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
582 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
583 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
584 | break; |
585 | } | |
586 | else | |
587 | { | |
588 | /* short instructions */ | |
589 | if ((op & 0xC0000000) == 0x80000000) | |
590 | { | |
591 | op2 = (op & 0x3FFF8000) >> 15; | |
592 | op1 = op & 0x7FFF; | |
c5aa993b JM |
593 | } |
594 | else | |
c906108c SS |
595 | { |
596 | op1 = (op & 0x3FFF8000) >> 15; | |
597 | op2 = op & 0x7FFF; | |
598 | } | |
c5aa993b | 599 | if (check_prologue (op1)) |
c906108c | 600 | { |
c5aa993b | 601 | if (!check_prologue (op2)) |
c906108c SS |
602 | { |
603 | /* if the previous opcode was really part of the prologue */ | |
604 | /* and not just a NOP, then we want to break after both instructions */ | |
605 | if (op1 != 0x5E00) | |
606 | pc += 4; | |
607 | break; | |
608 | } | |
609 | } | |
610 | else | |
611 | break; | |
612 | } | |
613 | pc += 4; | |
614 | } | |
615 | return pc; | |
616 | } | |
617 | ||
618 | /* Given a GDB frame, determine the address of the calling function's frame. | |
619 | This will be used to create a new GDB frame struct, and then | |
620 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
c5aa993b | 621 | */ |
c906108c SS |
622 | |
623 | CORE_ADDR | |
fba45db2 | 624 | d10v_frame_chain (struct frame_info *fi) |
c906108c | 625 | { |
cce74817 | 626 | d10v_frame_init_saved_regs (fi); |
c906108c | 627 | |
cce74817 JM |
628 | if (fi->extra_info->return_pc == IMEM_START |
629 | || inside_entry_file (fi->extra_info->return_pc)) | |
c5aa993b | 630 | return (CORE_ADDR) 0; |
c906108c | 631 | |
cce74817 | 632 | if (!fi->saved_regs[FP_REGNUM]) |
c906108c | 633 | { |
cce74817 JM |
634 | if (!fi->saved_regs[SP_REGNUM] |
635 | || fi->saved_regs[SP_REGNUM] == STACK_START) | |
c5aa993b JM |
636 | return (CORE_ADDR) 0; |
637 | ||
cce74817 | 638 | return fi->saved_regs[SP_REGNUM]; |
c906108c SS |
639 | } |
640 | ||
c5aa993b JM |
641 | if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
642 | REGISTER_RAW_SIZE (FP_REGNUM))) | |
643 | return (CORE_ADDR) 0; | |
c906108c | 644 | |
cce74817 | 645 | return D10V_MAKE_DADDR (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
c5aa993b JM |
646 | REGISTER_RAW_SIZE (FP_REGNUM))); |
647 | } | |
c906108c SS |
648 | |
649 | static int next_addr, uses_frame; | |
650 | ||
c5aa993b | 651 | static int |
fba45db2 | 652 | prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr) |
c906108c SS |
653 | { |
654 | int n; | |
655 | ||
656 | /* st rn, @-sp */ | |
657 | if ((op & 0x7E1F) == 0x6C1F) | |
658 | { | |
659 | n = (op & 0x1E0) >> 5; | |
660 | next_addr -= 2; | |
cce74817 | 661 | fi->saved_regs[n] = next_addr; |
c906108c SS |
662 | return 1; |
663 | } | |
664 | ||
665 | /* st2w rn, @-sp */ | |
666 | else if ((op & 0x7E3F) == 0x6E1F) | |
667 | { | |
668 | n = (op & 0x1E0) >> 5; | |
669 | next_addr -= 4; | |
cce74817 | 670 | fi->saved_regs[n] = next_addr; |
c5aa993b | 671 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
672 | return 1; |
673 | } | |
674 | ||
675 | /* subi sp, n */ | |
676 | if ((op & 0x7FE1) == 0x01E1) | |
677 | { | |
678 | n = (op & 0x1E) >> 1; | |
679 | if (n == 0) | |
680 | n = 16; | |
681 | next_addr -= n; | |
682 | return 1; | |
683 | } | |
684 | ||
685 | /* mv r11, sp */ | |
686 | if (op == 0x417E) | |
687 | { | |
688 | uses_frame = 1; | |
689 | return 1; | |
690 | } | |
691 | ||
692 | /* nop */ | |
693 | if (op == 0x5E00) | |
694 | return 1; | |
695 | ||
696 | /* st rn, @sp */ | |
697 | if ((op & 0x7E1F) == 0x681E) | |
698 | { | |
699 | n = (op & 0x1E0) >> 5; | |
cce74817 | 700 | fi->saved_regs[n] = next_addr; |
c906108c SS |
701 | return 1; |
702 | } | |
703 | ||
704 | /* st2w rn, @sp */ | |
705 | if ((op & 0x7E3F) == 0x3A1E) | |
706 | { | |
707 | n = (op & 0x1E0) >> 5; | |
cce74817 | 708 | fi->saved_regs[n] = next_addr; |
c5aa993b | 709 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
710 | return 1; |
711 | } | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
cce74817 JM |
716 | /* Put here the code to store, into fi->saved_regs, the addresses of |
717 | the saved registers of frame described by FRAME_INFO. This | |
718 | includes special registers such as pc and fp saved in special ways | |
719 | in the stack frame. sp is even more special: the address we return | |
720 | for it IS the sp for the next frame. */ | |
721 | ||
c906108c | 722 | void |
fba45db2 | 723 | d10v_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
724 | { |
725 | CORE_ADDR fp, pc; | |
726 | unsigned long op; | |
727 | unsigned short op1, op2; | |
728 | int i; | |
729 | ||
730 | fp = fi->frame; | |
cce74817 | 731 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
732 | next_addr = 0; |
733 | ||
734 | pc = get_pc_function_start (fi->pc); | |
735 | ||
736 | uses_frame = 0; | |
737 | while (1) | |
738 | { | |
c5aa993b | 739 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
740 | if ((op & 0xC0000000) == 0xC0000000) |
741 | { | |
742 | /* long instruction */ | |
743 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
744 | { | |
745 | /* add3 sp,sp,n */ | |
746 | short n = op & 0xFFFF; | |
747 | next_addr += n; | |
748 | } | |
749 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
750 | { | |
751 | /* st rn, @(offset,sp) */ | |
752 | short offset = op & 0xFFFF; | |
753 | short n = (op >> 20) & 0xF; | |
cce74817 | 754 | fi->saved_regs[n] = next_addr + offset; |
c906108c SS |
755 | } |
756 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
757 | { | |
758 | /* st2w rn, @(offset,sp) */ | |
759 | short offset = op & 0xFFFF; | |
760 | short n = (op >> 20) & 0xF; | |
cce74817 | 761 | fi->saved_regs[n] = next_addr + offset; |
c5aa993b | 762 | fi->saved_regs[n + 1] = next_addr + offset + 2; |
c906108c SS |
763 | } |
764 | else | |
765 | break; | |
766 | } | |
767 | else | |
768 | { | |
769 | /* short instructions */ | |
770 | if ((op & 0xC0000000) == 0x80000000) | |
771 | { | |
772 | op2 = (op & 0x3FFF8000) >> 15; | |
773 | op1 = op & 0x7FFF; | |
c5aa993b JM |
774 | } |
775 | else | |
c906108c SS |
776 | { |
777 | op1 = (op & 0x3FFF8000) >> 15; | |
778 | op2 = op & 0x7FFF; | |
779 | } | |
c5aa993b | 780 | if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc)) |
c906108c SS |
781 | break; |
782 | } | |
783 | pc += 4; | |
784 | } | |
c5aa993b | 785 | |
cce74817 | 786 | fi->extra_info->size = -next_addr; |
c906108c SS |
787 | |
788 | if (!(fp & 0xffff)) | |
c5aa993b | 789 | fp = D10V_MAKE_DADDR (read_register (SP_REGNUM)); |
c906108c | 790 | |
c5aa993b | 791 | for (i = 0; i < NUM_REGS - 1; i++) |
cce74817 | 792 | if (fi->saved_regs[i]) |
c906108c | 793 | { |
c5aa993b | 794 | fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]); |
c906108c SS |
795 | } |
796 | ||
cce74817 | 797 | if (fi->saved_regs[LR_REGNUM]) |
c906108c | 798 | { |
cce74817 JM |
799 | CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM)); |
800 | fi->extra_info->return_pc = D10V_MAKE_IADDR (return_pc); | |
c906108c SS |
801 | } |
802 | else | |
803 | { | |
c5aa993b | 804 | fi->extra_info->return_pc = D10V_MAKE_IADDR (read_register (LR_REGNUM)); |
c906108c | 805 | } |
c5aa993b | 806 | |
c906108c | 807 | /* th SP is not normally (ever?) saved, but check anyway */ |
cce74817 | 808 | if (!fi->saved_regs[SP_REGNUM]) |
c906108c SS |
809 | { |
810 | /* if the FP was saved, that means the current FP is valid, */ | |
811 | /* otherwise, it isn't being used, so we use the SP instead */ | |
812 | if (uses_frame) | |
c5aa993b | 813 | fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size; |
c906108c SS |
814 | else |
815 | { | |
cce74817 JM |
816 | fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size; |
817 | fi->extra_info->frameless = 1; | |
818 | fi->saved_regs[FP_REGNUM] = 0; | |
c906108c SS |
819 | } |
820 | } | |
821 | } | |
822 | ||
823 | void | |
fba45db2 | 824 | d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 825 | { |
cce74817 JM |
826 | fi->extra_info = (struct frame_extra_info *) |
827 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
828 | frame_saved_regs_zalloc (fi); | |
829 | ||
830 | fi->extra_info->frameless = 0; | |
831 | fi->extra_info->size = 0; | |
832 | fi->extra_info->return_pc = 0; | |
c906108c SS |
833 | |
834 | /* The call dummy doesn't save any registers on the stack, so we can | |
835 | return now. */ | |
836 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
837 | { | |
838 | return; | |
839 | } | |
840 | else | |
841 | { | |
cce74817 | 842 | d10v_frame_init_saved_regs (fi); |
c906108c SS |
843 | } |
844 | } | |
845 | ||
846 | static void | |
fba45db2 | 847 | show_regs (char *args, int from_tty) |
c906108c SS |
848 | { |
849 | int a; | |
d4f3574e SS |
850 | printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
851 | (long) read_register (PC_REGNUM), | |
852 | (long) D10V_MAKE_IADDR (read_register (PC_REGNUM)), | |
853 | (long) read_register (PSW_REGNUM), | |
854 | (long) read_register (24), | |
855 | (long) read_register (25), | |
856 | (long) read_register (23)); | |
857 | printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
858 | (long) read_register (0), | |
859 | (long) read_register (1), | |
860 | (long) read_register (2), | |
861 | (long) read_register (3), | |
862 | (long) read_register (4), | |
863 | (long) read_register (5), | |
864 | (long) read_register (6), | |
865 | (long) read_register (7)); | |
866 | printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
867 | (long) read_register (8), | |
868 | (long) read_register (9), | |
869 | (long) read_register (10), | |
870 | (long) read_register (11), | |
871 | (long) read_register (12), | |
872 | (long) read_register (13), | |
873 | (long) read_register (14), | |
874 | (long) read_register (15)); | |
4ce44c66 JM |
875 | for (a = 0; a < NR_IMAP_REGS; a++) |
876 | { | |
877 | if (a > 0) | |
878 | printf_filtered (" "); | |
879 | printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); | |
880 | } | |
881 | if (NR_DMAP_REGS == 1) | |
882 | printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); | |
883 | else | |
884 | { | |
885 | for (a = 0; a < NR_DMAP_REGS; a++) | |
886 | { | |
887 | printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); | |
888 | } | |
889 | printf_filtered ("\n"); | |
890 | } | |
891 | printf_filtered ("A0-A%d", NR_A_REGS - 1); | |
892 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) | |
c906108c SS |
893 | { |
894 | char num[MAX_REGISTER_RAW_SIZE]; | |
895 | int i; | |
896 | printf_filtered (" "); | |
c5aa993b | 897 | read_register_gen (a, (char *) &num); |
c906108c SS |
898 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) |
899 | { | |
900 | printf_filtered ("%02x", (num[i] & 0xff)); | |
901 | } | |
902 | } | |
903 | printf_filtered ("\n"); | |
904 | } | |
905 | ||
906 | CORE_ADDR | |
fba45db2 | 907 | d10v_read_pc (int pid) |
c906108c SS |
908 | { |
909 | int save_pid; | |
910 | CORE_ADDR pc; | |
911 | CORE_ADDR retval; | |
912 | ||
913 | save_pid = inferior_pid; | |
914 | inferior_pid = pid; | |
915 | pc = (int) read_register (PC_REGNUM); | |
916 | inferior_pid = save_pid; | |
917 | retval = D10V_MAKE_IADDR (pc); | |
918 | return retval; | |
919 | } | |
920 | ||
921 | void | |
fba45db2 | 922 | d10v_write_pc (CORE_ADDR val, int pid) |
c906108c SS |
923 | { |
924 | int save_pid; | |
925 | ||
926 | save_pid = inferior_pid; | |
927 | inferior_pid = pid; | |
928 | write_register (PC_REGNUM, D10V_CONVERT_IADDR_TO_RAW (val)); | |
929 | inferior_pid = save_pid; | |
930 | } | |
931 | ||
932 | CORE_ADDR | |
fba45db2 | 933 | d10v_read_sp (void) |
c906108c SS |
934 | { |
935 | return (D10V_MAKE_DADDR (read_register (SP_REGNUM))); | |
936 | } | |
937 | ||
938 | void | |
fba45db2 | 939 | d10v_write_sp (CORE_ADDR val) |
c906108c SS |
940 | { |
941 | write_register (SP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val)); | |
942 | } | |
943 | ||
944 | void | |
fba45db2 | 945 | d10v_write_fp (CORE_ADDR val) |
c906108c SS |
946 | { |
947 | write_register (FP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val)); | |
948 | } | |
949 | ||
950 | CORE_ADDR | |
fba45db2 | 951 | d10v_read_fp (void) |
c906108c | 952 | { |
c5aa993b | 953 | return (D10V_MAKE_DADDR (read_register (FP_REGNUM))); |
c906108c SS |
954 | } |
955 | ||
956 | /* Function: push_return_address (pc) | |
957 | Set up the return address for the inferior function call. | |
958 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
c5aa993b | 959 | |
c906108c | 960 | CORE_ADDR |
fba45db2 | 961 | d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c SS |
962 | { |
963 | write_register (LR_REGNUM, D10V_CONVERT_IADDR_TO_RAW (CALL_DUMMY_ADDRESS ())); | |
964 | return sp; | |
965 | } | |
c5aa993b | 966 | |
c906108c | 967 | |
7a292a7a SS |
968 | /* When arguments must be pushed onto the stack, they go on in reverse |
969 | order. The below implements a FILO (stack) to do this. */ | |
970 | ||
971 | struct stack_item | |
972 | { | |
973 | int len; | |
974 | struct stack_item *prev; | |
975 | void *data; | |
976 | }; | |
977 | ||
a14ed312 KB |
978 | static struct stack_item *push_stack_item (struct stack_item *prev, |
979 | void *contents, int len); | |
7a292a7a | 980 | static struct stack_item * |
fba45db2 | 981 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
982 | { |
983 | struct stack_item *si; | |
984 | si = xmalloc (sizeof (struct stack_item)); | |
985 | si->data = xmalloc (len); | |
986 | si->len = len; | |
987 | si->prev = prev; | |
988 | memcpy (si->data, contents, len); | |
989 | return si; | |
990 | } | |
991 | ||
a14ed312 | 992 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 993 | static struct stack_item * |
fba45db2 | 994 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
995 | { |
996 | struct stack_item *dead = si; | |
997 | si = si->prev; | |
998 | free (dead->data); | |
999 | free (dead); | |
1000 | return si; | |
1001 | } | |
1002 | ||
1003 | ||
c906108c | 1004 | CORE_ADDR |
fba45db2 KB |
1005 | d10v_push_arguments (int nargs, value_ptr *args, CORE_ADDR sp, |
1006 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
1007 | { |
1008 | int i; | |
1009 | int regnum = ARG1_REGNUM; | |
7a292a7a | 1010 | struct stack_item *si = NULL; |
c5aa993b | 1011 | |
c906108c SS |
1012 | /* Fill in registers and arg lists */ |
1013 | for (i = 0; i < nargs; i++) | |
1014 | { | |
1015 | value_ptr arg = args[i]; | |
1016 | struct type *type = check_typedef (VALUE_TYPE (arg)); | |
1017 | char *contents = VALUE_CONTENTS (arg); | |
1018 | int len = TYPE_LENGTH (type); | |
1019 | /* printf ("push: type=%d len=%d\n", type->code, len); */ | |
1020 | if (TYPE_CODE (type) == TYPE_CODE_PTR) | |
1021 | { | |
1022 | /* pointers require special handling - first convert and | |
1023 | then store */ | |
1024 | long val = extract_signed_integer (contents, len); | |
1025 | len = 2; | |
1026 | if (TYPE_TARGET_TYPE (type) | |
1027 | && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)) | |
1028 | { | |
1029 | /* function pointer */ | |
1030 | val = D10V_CONVERT_IADDR_TO_RAW (val); | |
1031 | } | |
1032 | else if (D10V_IADDR_P (val)) | |
1033 | { | |
1034 | /* also function pointer! */ | |
1035 | val = D10V_CONVERT_DADDR_TO_RAW (val); | |
1036 | } | |
1037 | else | |
1038 | { | |
1039 | /* data pointer */ | |
1040 | val &= 0xFFFF; | |
1041 | } | |
1042 | if (regnum <= ARGN_REGNUM) | |
1043 | write_register (regnum++, val & 0xffff); | |
1044 | else | |
1045 | { | |
1046 | char ptr[2]; | |
7a292a7a | 1047 | /* arg will go onto stack */ |
0f71a2f6 | 1048 | store_address (ptr, 2, val & 0xffff); |
7a292a7a | 1049 | si = push_stack_item (si, ptr, 2); |
c906108c SS |
1050 | } |
1051 | } | |
1052 | else | |
1053 | { | |
1054 | int aligned_regnum = (regnum + 1) & ~1; | |
1055 | if (len <= 2 && regnum <= ARGN_REGNUM) | |
1056 | /* fits in a single register, do not align */ | |
1057 | { | |
1058 | long val = extract_unsigned_integer (contents, len); | |
1059 | write_register (regnum++, val); | |
1060 | } | |
1061 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1062 | /* value fits in remaining registers, store keeping left | |
c5aa993b | 1063 | aligned */ |
c906108c SS |
1064 | { |
1065 | int b; | |
1066 | regnum = aligned_regnum; | |
1067 | for (b = 0; b < (len & ~1); b += 2) | |
1068 | { | |
1069 | long val = extract_unsigned_integer (&contents[b], 2); | |
1070 | write_register (regnum++, val); | |
1071 | } | |
1072 | if (b < len) | |
1073 | { | |
1074 | long val = extract_unsigned_integer (&contents[b], 1); | |
1075 | write_register (regnum++, (val << 8)); | |
1076 | } | |
1077 | } | |
1078 | else | |
1079 | { | |
7a292a7a | 1080 | /* arg will go onto stack */ |
c5aa993b | 1081 | regnum = ARGN_REGNUM + 1; |
7a292a7a | 1082 | si = push_stack_item (si, contents, len); |
c906108c SS |
1083 | } |
1084 | } | |
1085 | } | |
7a292a7a SS |
1086 | |
1087 | while (si) | |
1088 | { | |
1089 | sp = (sp - si->len) & ~1; | |
1090 | write_memory (sp, si->data, si->len); | |
1091 | si = pop_stack_item (si); | |
1092 | } | |
c5aa993b | 1093 | |
c906108c SS |
1094 | return sp; |
1095 | } | |
1096 | ||
1097 | ||
1098 | /* Given a return value in `regbuf' with a type `valtype', | |
1099 | extract and copy its value into `valbuf'. */ | |
1100 | ||
1101 | void | |
1102 | d10v_extract_return_value (type, regbuf, valbuf) | |
1103 | struct type *type; | |
1104 | char regbuf[REGISTER_BYTES]; | |
1105 | char *valbuf; | |
1106 | { | |
1107 | int len; | |
1108 | /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */ | |
1109 | if (TYPE_CODE (type) == TYPE_CODE_PTR | |
1110 | && TYPE_TARGET_TYPE (type) | |
1111 | && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)) | |
1112 | { | |
1113 | /* pointer to function */ | |
1114 | int num; | |
1115 | short snum; | |
1116 | snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
c5aa993b | 1117 | store_address (valbuf, 4, D10V_MAKE_IADDR (snum)); |
c906108c | 1118 | } |
c5aa993b | 1119 | else if (TYPE_CODE (type) == TYPE_CODE_PTR) |
c906108c SS |
1120 | { |
1121 | /* pointer to data */ | |
1122 | int num; | |
1123 | short snum; | |
1124 | snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
c5aa993b | 1125 | store_address (valbuf, 4, D10V_MAKE_DADDR (snum)); |
c906108c SS |
1126 | } |
1127 | else | |
1128 | { | |
1129 | len = TYPE_LENGTH (type); | |
1130 | if (len == 1) | |
1131 | { | |
1132 | unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
1133 | store_unsigned_integer (valbuf, 1, c); | |
1134 | } | |
1135 | else if ((len & 1) == 0) | |
1136 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len); | |
1137 | else | |
1138 | { | |
1139 | /* For return values of odd size, the first byte is in the | |
c5aa993b JM |
1140 | least significant part of the first register. The |
1141 | remaining bytes in remaining registers. Interestingly, | |
1142 | when such values are passed in, the last byte is in the | |
1143 | most significant byte of that same register - wierd. */ | |
c906108c SS |
1144 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); |
1145 | } | |
1146 | } | |
1147 | } | |
1148 | ||
c2c6d25f JM |
1149 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1150 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1151 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1152 | (segmentation fault). Since the simulator knows all about how the | |
1153 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1154 | |
4ce44c66 | 1155 | static void |
c2c6d25f JM |
1156 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1157 | CORE_ADDR *targ_addr, int *targ_len) | |
1158 | { | |
4ce44c66 JM |
1159 | long out_addr; |
1160 | long out_len; | |
1161 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1162 | &out_addr, | |
1163 | d10v_dmap_register, | |
1164 | d10v_imap_register); | |
1165 | *targ_addr = out_addr; | |
1166 | *targ_len = out_len; | |
c2c6d25f JM |
1167 | } |
1168 | ||
4ce44c66 | 1169 | |
c906108c SS |
1170 | /* The following code implements access to, and display of, the D10V's |
1171 | instruction trace buffer. The buffer consists of 64K or more | |
1172 | 4-byte words of data, of which each words includes an 8-bit count, | |
1173 | an 8-bit segment number, and a 16-bit instruction address. | |
1174 | ||
1175 | In theory, the trace buffer is continuously capturing instruction | |
1176 | data that the CPU presents on its "debug bus", but in practice, the | |
1177 | ROMified GDB stub only enables tracing when it continues or steps | |
1178 | the program, and stops tracing when the program stops; so it | |
1179 | actually works for GDB to read the buffer counter out of memory and | |
1180 | then read each trace word. The counter records where the tracing | |
1181 | stops, but there is no record of where it started, so we remember | |
1182 | the PC when we resumed and then search backwards in the trace | |
1183 | buffer for a word that includes that address. This is not perfect, | |
1184 | because you will miss trace data if the resumption PC is the target | |
1185 | of a branch. (The value of the buffer counter is semi-random, any | |
1186 | trace data from a previous program stop is gone.) */ | |
1187 | ||
1188 | /* The address of the last word recorded in the trace buffer. */ | |
1189 | ||
1190 | #define DBBC_ADDR (0xd80000) | |
1191 | ||
1192 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1193 | ||
1194 | #define TRACE_BUFFER_BASE (0xf40000) | |
1195 | ||
a14ed312 | 1196 | static void trace_command (char *, int); |
c906108c | 1197 | |
a14ed312 | 1198 | static void untrace_command (char *, int); |
c906108c | 1199 | |
a14ed312 | 1200 | static void trace_info (char *, int); |
c906108c | 1201 | |
a14ed312 | 1202 | static void tdisassemble_command (char *, int); |
c906108c | 1203 | |
a14ed312 | 1204 | static void display_trace (int, int); |
c906108c SS |
1205 | |
1206 | /* True when instruction traces are being collected. */ | |
1207 | ||
1208 | static int tracing; | |
1209 | ||
1210 | /* Remembered PC. */ | |
1211 | ||
1212 | static CORE_ADDR last_pc; | |
1213 | ||
1214 | /* True when trace output should be displayed whenever program stops. */ | |
1215 | ||
1216 | static int trace_display; | |
1217 | ||
1218 | /* True when trace listing should include source lines. */ | |
1219 | ||
1220 | static int default_trace_show_source = 1; | |
1221 | ||
c5aa993b JM |
1222 | struct trace_buffer |
1223 | { | |
1224 | int size; | |
1225 | short *counts; | |
1226 | CORE_ADDR *addrs; | |
1227 | } | |
1228 | trace_data; | |
c906108c SS |
1229 | |
1230 | static void | |
fba45db2 | 1231 | trace_command (char *args, int from_tty) |
c906108c SS |
1232 | { |
1233 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1234 | trace_data.size = 0; | |
1235 | if (trace_data.counts == NULL) | |
c5aa993b | 1236 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1237 | if (trace_data.addrs == NULL) |
c5aa993b | 1238 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1239 | |
1240 | tracing = 1; | |
1241 | ||
1242 | printf_filtered ("Tracing is now on.\n"); | |
1243 | } | |
1244 | ||
1245 | static void | |
fba45db2 | 1246 | untrace_command (char *args, int from_tty) |
c906108c SS |
1247 | { |
1248 | tracing = 0; | |
1249 | ||
1250 | printf_filtered ("Tracing is now off.\n"); | |
1251 | } | |
1252 | ||
1253 | static void | |
fba45db2 | 1254 | trace_info (char *args, int from_tty) |
c906108c SS |
1255 | { |
1256 | int i; | |
1257 | ||
1258 | if (trace_data.size) | |
1259 | { | |
1260 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1261 | ||
1262 | for (i = 0; i < trace_data.size; ++i) | |
1263 | { | |
d4f3574e SS |
1264 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1265 | i, | |
1266 | trace_data.counts[i], | |
c906108c | 1267 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1268 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1269 | } |
1270 | } | |
1271 | else | |
1272 | printf_filtered ("No entries in trace buffer.\n"); | |
1273 | ||
1274 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1275 | } | |
1276 | ||
1277 | /* Print the instruction at address MEMADDR in debugged memory, | |
1278 | on STREAM. Returns length of the instruction, in bytes. */ | |
1279 | ||
1280 | static int | |
fba45db2 | 1281 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1282 | { |
1283 | /* If there's no disassembler, something is very wrong. */ | |
1284 | if (tm_print_insn == NULL) | |
11cf8741 | 1285 | internal_error ("print_insn: no disassembler"); |
c906108c SS |
1286 | |
1287 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1288 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; | |
1289 | else | |
1290 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
1291 | return (*tm_print_insn) (memaddr, &tm_print_insn_info); | |
1292 | } | |
1293 | ||
392a587b | 1294 | static void |
fba45db2 | 1295 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1296 | { |
1297 | if (!tracing) | |
1298 | return; | |
1299 | ||
1300 | last_pc = read_register (PC_REGNUM); | |
1301 | } | |
1302 | ||
1303 | /* Collect trace data from the target board and format it into a form | |
1304 | more useful for display. */ | |
1305 | ||
392a587b | 1306 | static void |
fba45db2 | 1307 | d10v_eva_get_trace_data (void) |
c906108c SS |
1308 | { |
1309 | int count, i, j, oldsize; | |
1310 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1311 | unsigned int last_trace, trace_word, next_word; | |
1312 | unsigned int *tmpspace; | |
1313 | ||
1314 | if (!tracing) | |
1315 | return; | |
1316 | ||
c5aa993b | 1317 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1318 | |
1319 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1320 | ||
1321 | /* Collect buffer contents from the target, stopping when we reach | |
1322 | the word recorded when execution resumed. */ | |
1323 | ||
1324 | count = 0; | |
1325 | while (last_trace > 0) | |
1326 | { | |
1327 | QUIT; | |
1328 | trace_word = | |
1329 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1330 | trace_addr = trace_word & 0xffff; | |
1331 | last_trace -= 4; | |
1332 | /* Ignore an apparently nonsensical entry. */ | |
1333 | if (trace_addr == 0xffd5) | |
1334 | continue; | |
1335 | tmpspace[count++] = trace_word; | |
1336 | if (trace_addr == last_pc) | |
1337 | break; | |
1338 | if (count > 65535) | |
1339 | break; | |
1340 | } | |
1341 | ||
1342 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1343 | include the last instruction executed and transforming the address | |
1344 | into something that GDB likes. */ | |
1345 | ||
1346 | for (i = 0; i < count; ++i) | |
1347 | { | |
1348 | trace_word = tmpspace[i]; | |
1349 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1350 | trace_addr = trace_word & 0xffff; | |
1351 | next_cnt = (next_word >> 24) & 0xff; | |
1352 | j = trace_data.size + count - i - 1; | |
1353 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1354 | trace_data.counts[j] = next_cnt + 1; | |
1355 | } | |
1356 | ||
1357 | oldsize = trace_data.size; | |
1358 | trace_data.size += count; | |
1359 | ||
1360 | free (tmpspace); | |
1361 | ||
1362 | if (trace_display) | |
1363 | display_trace (oldsize, trace_data.size); | |
1364 | } | |
1365 | ||
1366 | static void | |
fba45db2 | 1367 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1368 | { |
1369 | int i, count; | |
1370 | CORE_ADDR low, high; | |
1371 | char *space_index; | |
1372 | ||
1373 | if (!arg) | |
1374 | { | |
1375 | low = 0; | |
1376 | high = trace_data.size; | |
1377 | } | |
1378 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1379 | { | |
1380 | low = parse_and_eval_address (arg); | |
1381 | high = low + 5; | |
1382 | } | |
1383 | else | |
1384 | { | |
1385 | /* Two arguments. */ | |
1386 | *space_index = '\0'; | |
1387 | low = parse_and_eval_address (arg); | |
1388 | high = parse_and_eval_address (space_index + 1); | |
1389 | if (high < low) | |
1390 | high = low; | |
1391 | } | |
1392 | ||
d4f3574e | 1393 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1394 | |
1395 | display_trace (low, high); | |
1396 | ||
1397 | printf_filtered ("End of trace dump.\n"); | |
1398 | gdb_flush (gdb_stdout); | |
1399 | } | |
1400 | ||
1401 | static void | |
fba45db2 | 1402 | display_trace (int low, int high) |
c906108c SS |
1403 | { |
1404 | int i, count, trace_show_source, first, suppress; | |
1405 | CORE_ADDR next_address; | |
1406 | ||
1407 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1408 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1409 | { |
1410 | trace_show_source = 0; | |
1411 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1412 | printf_filtered ("Trace will not display any source.\n"); | |
1413 | } | |
1414 | ||
1415 | first = 1; | |
1416 | suppress = 0; | |
1417 | for (i = low; i < high; ++i) | |
1418 | { | |
1419 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1420 | count = trace_data.counts[i]; |
c906108c SS |
1421 | while (count-- > 0) |
1422 | { | |
1423 | QUIT; | |
1424 | if (trace_show_source) | |
1425 | { | |
1426 | struct symtab_and_line sal, sal_prev; | |
1427 | ||
1428 | sal_prev = find_pc_line (next_address - 4, 0); | |
1429 | sal = find_pc_line (next_address, 0); | |
1430 | ||
1431 | if (sal.symtab) | |
1432 | { | |
1433 | if (first || sal.line != sal_prev.line) | |
1434 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1435 | suppress = 0; | |
1436 | } | |
1437 | else | |
1438 | { | |
1439 | if (!suppress) | |
1440 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1441 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1442 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1443 | suppress = 1; |
1444 | } | |
1445 | } | |
1446 | first = 0; | |
1447 | print_address (next_address, gdb_stdout); | |
1448 | printf_filtered (":"); | |
1449 | printf_filtered ("\t"); | |
1450 | wrap_here (" "); | |
1451 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1452 | printf_filtered ("\n"); | |
1453 | gdb_flush (gdb_stdout); | |
1454 | } | |
1455 | } | |
1456 | } | |
1457 | ||
ac9a91a7 | 1458 | |
0f71a2f6 | 1459 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1460 | |
0f71a2f6 | 1461 | static struct gdbarch * |
fba45db2 | 1462 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1463 | { |
c5aa993b JM |
1464 | static LONGEST d10v_call_dummy_words[] = |
1465 | {0}; | |
0f71a2f6 | 1466 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1467 | int d10v_num_regs; |
1468 | struct gdbarch_tdep *tdep; | |
1469 | gdbarch_register_name_ftype *d10v_register_name; | |
0f71a2f6 | 1470 | |
4ce44c66 JM |
1471 | /* Find a candidate among the list of pre-declared architectures. */ |
1472 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1473 | if (arches != NULL) |
1474 | return arches->gdbarch; | |
4ce44c66 JM |
1475 | |
1476 | /* None found, create a new architecture from the information | |
1477 | provided. */ | |
1478 | tdep = XMALLOC (struct gdbarch_tdep); | |
1479 | gdbarch = gdbarch_alloc (&info, tdep); | |
1480 | ||
1481 | switch (info.bfd_arch_info->mach) | |
1482 | { | |
1483 | case bfd_mach_d10v_ts2: | |
1484 | d10v_num_regs = 37; | |
1485 | d10v_register_name = d10v_ts2_register_name; | |
1486 | tdep->a0_regnum = TS2_A0_REGNUM; | |
1487 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
1488 | tdep->register_sim_regno = d10v_ts2_register_sim_regno; | |
1489 | tdep->dmap_register = d10v_ts2_dmap_register; | |
1490 | tdep->imap_register = d10v_ts2_imap_register; | |
1491 | break; | |
1492 | default: | |
1493 | case bfd_mach_d10v_ts3: | |
1494 | d10v_num_regs = 42; | |
1495 | d10v_register_name = d10v_ts3_register_name; | |
1496 | tdep->a0_regnum = TS3_A0_REGNUM; | |
1497 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
1498 | tdep->register_sim_regno = d10v_ts3_register_sim_regno; | |
1499 | tdep->dmap_register = d10v_ts3_dmap_register; | |
1500 | tdep->imap_register = d10v_ts3_imap_register; | |
1501 | break; | |
1502 | } | |
0f71a2f6 JM |
1503 | |
1504 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1505 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1506 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
1507 | set_gdbarch_write_fp (gdbarch, d10v_write_fp); | |
1508 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); | |
1509 | set_gdbarch_write_sp (gdbarch, d10v_write_sp); | |
1510 | ||
1511 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1512 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1513 | set_gdbarch_fp_regnum (gdbarch, 11); | |
1514 | set_gdbarch_pc_regnum (gdbarch, 18); | |
1515 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1516 | set_gdbarch_register_size (gdbarch, 2); | |
1517 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1518 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1519 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
1520 | set_gdbarch_max_register_raw_size (gdbarch, 8); | |
1521 | set_gdbarch_register_virtual_size (gdbarch, d10v_register_virtual_size); | |
1522 | set_gdbarch_max_register_virtual_size (gdbarch, 8); | |
1523 | set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); | |
1524 | ||
1525 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1526 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1527 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1528 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1529 | set_gdbarch_long_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1530 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1531 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1532 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1533 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1534 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1535 | switch (info.byte_order) |
1536 | { | |
1537 | case BIG_ENDIAN: | |
1538 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
1539 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1540 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1541 | break; | |
1542 | case LITTLE_ENDIAN: | |
1543 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
1544 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1545 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1546 | break; | |
1547 | default: | |
1548 | internal_error ("d10v_gdbarch_init: bad byte order for float format"); | |
1549 | } | |
0f71a2f6 JM |
1550 | |
1551 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
1552 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
1553 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
1554 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
1555 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
1556 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
1557 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
1558 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
1559 | set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); | |
1560 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); | |
1561 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
1562 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
1563 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
1564 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
1565 | ||
1566 | set_gdbarch_register_convertible (gdbarch, d10v_register_convertible); | |
1567 | set_gdbarch_register_convert_to_virtual (gdbarch, d10v_register_convert_to_virtual); | |
1568 | set_gdbarch_register_convert_to_raw (gdbarch, d10v_register_convert_to_raw); | |
1569 | ||
1570 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); | |
1571 | set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); | |
1572 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
1573 | set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); | |
1574 | ||
1575 | set_gdbarch_d10v_make_daddr (gdbarch, d10v_make_daddr); | |
1576 | set_gdbarch_d10v_make_iaddr (gdbarch, d10v_make_iaddr); | |
1577 | set_gdbarch_d10v_daddr_p (gdbarch, d10v_daddr_p); | |
1578 | set_gdbarch_d10v_iaddr_p (gdbarch, d10v_iaddr_p); | |
1579 | set_gdbarch_d10v_convert_daddr_to_raw (gdbarch, d10v_convert_daddr_to_raw); | |
1580 | set_gdbarch_d10v_convert_iaddr_to_raw (gdbarch, d10v_convert_iaddr_to_raw); | |
1581 | ||
1582 | set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); | |
1583 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); | |
1584 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
1585 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); | |
1586 | ||
1587 | set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs); | |
1588 | set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info); | |
1589 | ||
1590 | set_gdbarch_pop_frame (gdbarch, d10v_pop_frame); | |
1591 | ||
1592 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); | |
1593 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1594 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1595 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1596 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1597 | ||
1598 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1599 | ||
1600 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1601 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
1602 | set_gdbarch_frame_chain (gdbarch, d10v_frame_chain); | |
1603 | set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid); | |
1604 | set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc); | |
1605 | set_gdbarch_frame_args_address (gdbarch, d10v_frame_args_address); | |
1606 | set_gdbarch_frame_locals_address (gdbarch, d10v_frame_locals_address); | |
1607 | set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); | |
1608 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
23964bcd | 1609 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 JM |
1610 | |
1611 | return gdbarch; | |
1612 | } | |
1613 | ||
1614 | ||
507f3c78 KB |
1615 | extern void (*target_resume_hook) (void); |
1616 | extern void (*target_wait_loop_hook) (void); | |
c906108c SS |
1617 | |
1618 | void | |
fba45db2 | 1619 | _initialize_d10v_tdep (void) |
c906108c | 1620 | { |
0f71a2f6 JM |
1621 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1622 | ||
c906108c SS |
1623 | tm_print_insn = print_insn_d10v; |
1624 | ||
1625 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1626 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1627 | ||
1628 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
1629 | ||
cff3e48b | 1630 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1631 | "Enable tracing of instruction execution."); |
1632 | ||
cff3e48b | 1633 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1634 | "Disable tracing of instruction execution."); |
1635 | ||
cff3e48b | 1636 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1637 | "Disassemble the trace buffer.\n\ |
1638 | Two optional arguments specify a range of trace buffer entries\n\ | |
1639 | as reported by info trace (NOT addresses!)."); | |
1640 | ||
cff3e48b | 1641 | add_info ("itrace", trace_info, |
c906108c SS |
1642 | "Display info about the trace data buffer."); |
1643 | ||
cff3e48b | 1644 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1645 | var_integer, (char *) &trace_display, |
1646 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1647 | &showlist); |
cff3e48b | 1648 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1649 | var_integer, (char *) &default_trace_show_source, |
1650 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1651 | &showlist); |
1652 | ||
c5aa993b | 1653 | } |