Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
349c5d5f | 2 | |
51603483 | 3 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software |
349c5d5f | 4 | Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
c906108c SS |
27 | #include "symtab.h" |
28 | #include "gdbtypes.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdb_string.h" | |
32 | #include "value.h" | |
33 | #include "inferior.h" | |
c5aa993b | 34 | #include "dis-asm.h" |
c906108c SS |
35 | #include "symfile.h" |
36 | #include "objfiles.h" | |
104c1213 | 37 | #include "language.h" |
28d069e6 | 38 | #include "arch-utils.h" |
4e052eda | 39 | #include "regcache.h" |
c906108c | 40 | |
f0d4cc9e | 41 | #include "floatformat.h" |
b91b96f4 | 42 | #include "gdb/sim-d10v.h" |
8238d0bf | 43 | #include "sim-regno.h" |
4ce44c66 | 44 | |
cce74817 | 45 | struct frame_extra_info |
c5aa993b JM |
46 | { |
47 | CORE_ADDR return_pc; | |
48 | int frameless; | |
49 | int size; | |
50 | }; | |
cce74817 | 51 | |
4ce44c66 JM |
52 | struct gdbarch_tdep |
53 | { | |
54 | int a0_regnum; | |
55 | int nr_dmap_regs; | |
56 | unsigned long (*dmap_register) (int nr); | |
57 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
58 | }; |
59 | ||
60 | /* These are the addresses the D10V-EVA board maps data and | |
61 | instruction memory to. */ | |
cce74817 | 62 | |
78eac43e MS |
63 | enum memspace { |
64 | DMEM_START = 0x2000000, | |
65 | IMEM_START = 0x1000000, | |
66 | STACK_START = 0x200bffe | |
67 | }; | |
cce74817 | 68 | |
4ce44c66 JM |
69 | /* d10v register names. */ |
70 | ||
71 | enum | |
72 | { | |
73 | R0_REGNUM = 0, | |
78eac43e MS |
74 | R3_REGNUM = 3, |
75 | _FP_REGNUM = 11, | |
4ce44c66 | 76 | LR_REGNUM = 13, |
78eac43e | 77 | _SP_REGNUM = 15, |
4ce44c66 | 78 | PSW_REGNUM = 16, |
78eac43e | 79 | _PC_REGNUM = 18, |
4ce44c66 | 80 | NR_IMAP_REGS = 2, |
78eac43e MS |
81 | NR_A_REGS = 2, |
82 | TS2_NUM_REGS = 37, | |
83 | TS3_NUM_REGS = 42, | |
84 | /* d10v calling convention. */ | |
85 | ARG1_REGNUM = R0_REGNUM, | |
86 | ARGN_REGNUM = R3_REGNUM, | |
87 | RET1_REGNUM = R0_REGNUM, | |
4ce44c66 | 88 | }; |
78eac43e | 89 | |
4ce44c66 JM |
90 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) |
91 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
92 | ||
392a587b JM |
93 | /* Local functions */ |
94 | ||
a14ed312 | 95 | extern void _initialize_d10v_tdep (void); |
392a587b | 96 | |
095a4c96 EZ |
97 | static CORE_ADDR d10v_read_sp (void); |
98 | ||
99 | static CORE_ADDR d10v_read_fp (void); | |
100 | ||
a14ed312 | 101 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 102 | |
a14ed312 | 103 | static void d10v_eva_get_trace_data (void); |
c906108c | 104 | |
a14ed312 KB |
105 | static int prologue_find_regs (unsigned short op, struct frame_info *fi, |
106 | CORE_ADDR addr); | |
cce74817 | 107 | |
f5e1cf12 | 108 | static void d10v_frame_init_saved_regs (struct frame_info *); |
cce74817 | 109 | |
a14ed312 | 110 | static void do_d10v_pop_frame (struct frame_info *fi); |
cce74817 | 111 | |
f5e1cf12 | 112 | static int |
72623009 | 113 | d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame) |
c906108c | 114 | { |
51603483 | 115 | return (get_frame_pc (frame) > IMEM_START); |
c906108c SS |
116 | } |
117 | ||
23964bcd | 118 | static CORE_ADDR |
489137c0 AC |
119 | d10v_stack_align (CORE_ADDR len) |
120 | { | |
121 | return (len + 1) & ~1; | |
122 | } | |
c906108c SS |
123 | |
124 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
125 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
126 | and TYPE is the type (which is known to be struct, union or array). | |
127 | ||
128 | The d10v returns anything less than 8 bytes in size in | |
129 | registers. */ | |
130 | ||
f5e1cf12 | 131 | static int |
fba45db2 | 132 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 133 | { |
02da6206 JSC |
134 | long alignment; |
135 | int i; | |
136 | /* The d10v only passes a struct in a register when that structure | |
137 | has an alignment that matches the size of a register. */ | |
138 | /* If the structure doesn't fit in 4 registers, put it on the | |
139 | stack. */ | |
140 | if (TYPE_LENGTH (type) > 8) | |
141 | return 1; | |
142 | /* If the struct contains only one field, don't put it on the stack | |
143 | - gcc can fit it in one or more registers. */ | |
144 | if (TYPE_NFIELDS (type) == 1) | |
145 | return 0; | |
146 | alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); | |
147 | for (i = 1; i < TYPE_NFIELDS (type); i++) | |
148 | { | |
149 | /* If the alignment changes, just assume it goes on the | |
150 | stack. */ | |
151 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) | |
152 | return 1; | |
153 | } | |
154 | /* If the alignment is suitable for the d10v's 16 bit registers, | |
155 | don't put it on the stack. */ | |
156 | if (alignment == 2 || alignment == 4) | |
157 | return 0; | |
158 | return 1; | |
c906108c SS |
159 | } |
160 | ||
161 | ||
f4f9705a | 162 | static const unsigned char * |
fba45db2 | 163 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 164 | { |
c5aa993b JM |
165 | static unsigned char breakpoint[] = |
166 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
167 | *lenptr = sizeof (breakpoint); |
168 | return breakpoint; | |
169 | } | |
170 | ||
4ce44c66 JM |
171 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
172 | when the reg_nr isn't valid. */ | |
173 | ||
174 | enum ts2_regnums | |
175 | { | |
176 | TS2_IMAP0_REGNUM = 32, | |
177 | TS2_DMAP_REGNUM = 34, | |
178 | TS2_NR_DMAP_REGS = 1, | |
179 | TS2_A0_REGNUM = 35 | |
180 | }; | |
181 | ||
fa88f677 | 182 | static const char * |
4ce44c66 | 183 | d10v_ts2_register_name (int reg_nr) |
392a587b | 184 | { |
c5aa993b JM |
185 | static char *register_names[] = |
186 | { | |
187 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
188 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
189 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
190 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
191 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
192 | }; |
193 | if (reg_nr < 0) | |
194 | return NULL; | |
195 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
196 | return NULL; | |
c5aa993b | 197 | return register_names[reg_nr]; |
392a587b JM |
198 | } |
199 | ||
4ce44c66 JM |
200 | enum ts3_regnums |
201 | { | |
202 | TS3_IMAP0_REGNUM = 36, | |
203 | TS3_DMAP0_REGNUM = 38, | |
204 | TS3_NR_DMAP_REGS = 4, | |
205 | TS3_A0_REGNUM = 32 | |
206 | }; | |
207 | ||
fa88f677 | 208 | static const char * |
4ce44c66 JM |
209 | d10v_ts3_register_name (int reg_nr) |
210 | { | |
211 | static char *register_names[] = | |
212 | { | |
213 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
214 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
215 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
216 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
217 | "a0", "a1", | |
218 | "spi", "spu", | |
219 | "imap0", "imap1", | |
220 | "dmap0", "dmap1", "dmap2", "dmap3" | |
221 | }; | |
222 | if (reg_nr < 0) | |
223 | return NULL; | |
224 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
225 | return NULL; | |
226 | return register_names[reg_nr]; | |
227 | } | |
228 | ||
bf93dfed JB |
229 | /* Access the DMAP/IMAP registers in a target independent way. |
230 | ||
231 | Divide the D10V's 64k data space into four 16k segments: | |
232 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
233 | 0xc000 -- 0xffff. | |
234 | ||
235 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
236 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
237 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
238 | unified memory or instruction memory, under the control of the | |
239 | single DMAP register. | |
240 | ||
241 | On the TS3, there are four DMAP registers, each of which controls | |
242 | one of the segments. */ | |
4ce44c66 JM |
243 | |
244 | static unsigned long | |
245 | d10v_ts2_dmap_register (int reg_nr) | |
246 | { | |
247 | switch (reg_nr) | |
248 | { | |
249 | case 0: | |
250 | case 1: | |
251 | return 0x2000; | |
252 | case 2: | |
253 | return read_register (TS2_DMAP_REGNUM); | |
254 | default: | |
255 | return 0; | |
256 | } | |
257 | } | |
258 | ||
259 | static unsigned long | |
260 | d10v_ts3_dmap_register (int reg_nr) | |
261 | { | |
262 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
263 | } | |
264 | ||
265 | static unsigned long | |
266 | d10v_dmap_register (int reg_nr) | |
267 | { | |
268 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
269 | } | |
270 | ||
271 | static unsigned long | |
272 | d10v_ts2_imap_register (int reg_nr) | |
273 | { | |
274 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
275 | } | |
276 | ||
277 | static unsigned long | |
278 | d10v_ts3_imap_register (int reg_nr) | |
279 | { | |
280 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
281 | } | |
282 | ||
283 | static unsigned long | |
284 | d10v_imap_register (int reg_nr) | |
285 | { | |
286 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
287 | } | |
288 | ||
289 | /* MAP GDB's internal register numbering (determined by the layout fo | |
290 | the REGISTER_BYTE array) onto the simulator's register | |
291 | numbering. */ | |
292 | ||
293 | static int | |
294 | d10v_ts2_register_sim_regno (int nr) | |
295 | { | |
8238d0bf AC |
296 | if (legacy_register_sim_regno (nr) < 0) |
297 | return legacy_register_sim_regno (nr); | |
4ce44c66 JM |
298 | if (nr >= TS2_IMAP0_REGNUM |
299 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
300 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
301 | if (nr == TS2_DMAP_REGNUM) | |
302 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
303 | if (nr >= TS2_A0_REGNUM | |
304 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
305 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
306 | return nr; | |
307 | } | |
308 | ||
309 | static int | |
310 | d10v_ts3_register_sim_regno (int nr) | |
311 | { | |
8238d0bf AC |
312 | if (legacy_register_sim_regno (nr) < 0) |
313 | return legacy_register_sim_regno (nr); | |
4ce44c66 JM |
314 | if (nr >= TS3_IMAP0_REGNUM |
315 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
316 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
317 | if (nr >= TS3_DMAP0_REGNUM | |
318 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
319 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
320 | if (nr >= TS3_A0_REGNUM | |
321 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
322 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
323 | return nr; | |
324 | } | |
325 | ||
392a587b JM |
326 | /* Index within `registers' of the first byte of the space for |
327 | register REG_NR. */ | |
328 | ||
f5e1cf12 | 329 | static int |
fba45db2 | 330 | d10v_register_byte (int reg_nr) |
392a587b | 331 | { |
4ce44c66 | 332 | if (reg_nr < A0_REGNUM) |
392a587b | 333 | return (reg_nr * 2); |
4ce44c66 JM |
334 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
335 | return (A0_REGNUM * 2 | |
336 | + (reg_nr - A0_REGNUM) * 8); | |
337 | else | |
338 | return (A0_REGNUM * 2 | |
339 | + NR_A_REGS * 8 | |
340 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
341 | } |
342 | ||
343 | /* Number of bytes of storage in the actual machine representation for | |
344 | register REG_NR. */ | |
345 | ||
f5e1cf12 | 346 | static int |
fba45db2 | 347 | d10v_register_raw_size (int reg_nr) |
392a587b | 348 | { |
4ce44c66 JM |
349 | if (reg_nr < A0_REGNUM) |
350 | return 2; | |
351 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
352 | return 8; |
353 | else | |
354 | return 2; | |
355 | } | |
356 | ||
392a587b JM |
357 | /* Return the GDB type object for the "standard" data type |
358 | of data in register N. */ | |
359 | ||
f5e1cf12 | 360 | static struct type * |
fba45db2 | 361 | d10v_register_virtual_type (int reg_nr) |
392a587b | 362 | { |
75af7f68 JB |
363 | if (reg_nr == PC_REGNUM) |
364 | return builtin_type_void_func_ptr; | |
095a4c96 EZ |
365 | if (reg_nr == _SP_REGNUM || reg_nr == _FP_REGNUM) |
366 | return builtin_type_void_data_ptr; | |
75af7f68 | 367 | else if (reg_nr >= A0_REGNUM |
4ce44c66 JM |
368 | && reg_nr < (A0_REGNUM + NR_A_REGS)) |
369 | return builtin_type_int64; | |
392a587b | 370 | else |
4ce44c66 | 371 | return builtin_type_int16; |
392a587b JM |
372 | } |
373 | ||
f5e1cf12 | 374 | static int |
fba45db2 | 375 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
376 | { |
377 | return (((x) & 0x3000000) == DMEM_START); | |
378 | } | |
379 | ||
f5e1cf12 | 380 | static int |
fba45db2 | 381 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
382 | { |
383 | return (((x) & 0x3000000) == IMEM_START); | |
384 | } | |
385 | ||
169a7369 MS |
386 | static CORE_ADDR |
387 | d10v_make_daddr (CORE_ADDR x) | |
388 | { | |
389 | return ((x) | DMEM_START); | |
390 | } | |
391 | ||
392 | static CORE_ADDR | |
393 | d10v_make_iaddr (CORE_ADDR x) | |
394 | { | |
395 | if (d10v_iaddr_p (x)) | |
396 | return x; /* Idempotency -- x is already in the IMEM space. */ | |
397 | else | |
398 | return (((x) << 2) | IMEM_START); | |
399 | } | |
392a587b | 400 | |
f5e1cf12 | 401 | static CORE_ADDR |
fba45db2 | 402 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
403 | { |
404 | return (((x) >> 2) & 0xffff); | |
405 | } | |
406 | ||
f5e1cf12 | 407 | static CORE_ADDR |
fba45db2 | 408 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
409 | { |
410 | return ((x) & 0xffff); | |
411 | } | |
412 | ||
75af7f68 JB |
413 | static void |
414 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
415 | { | |
416 | /* Is it a code address? */ | |
417 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
418 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
419 | { | |
75af7f68 JB |
420 | store_unsigned_integer (buf, TYPE_LENGTH (type), |
421 | d10v_convert_iaddr_to_raw (addr)); | |
422 | } | |
423 | else | |
424 | { | |
425 | /* Strip off any upper segment bits. */ | |
426 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
427 | d10v_convert_daddr_to_raw (addr)); | |
428 | } | |
429 | } | |
430 | ||
431 | static CORE_ADDR | |
432 | d10v_pointer_to_address (struct type *type, void *buf) | |
433 | { | |
434 | CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type)); | |
435 | ||
436 | /* Is it a code address? */ | |
437 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
74a9bb82 FF |
438 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
439 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
75af7f68 JB |
440 | return d10v_make_iaddr (addr); |
441 | else | |
442 | return d10v_make_daddr (addr); | |
443 | } | |
444 | ||
095a4c96 EZ |
445 | /* Don't do anything if we have an integer, this way users can type 'x |
446 | <addr>' w/o having gdb outsmart them. The internal gdb conversions | |
447 | to the correct space are taken care of in the pointer_to_address | |
448 | function. If we don't do this, 'x $fp' wouldn't work. */ | |
fc0c74b1 AC |
449 | static CORE_ADDR |
450 | d10v_integer_to_address (struct type *type, void *buf) | |
451 | { | |
452 | LONGEST val; | |
453 | val = unpack_long (type, buf); | |
095a4c96 | 454 | return val; |
fc0c74b1 | 455 | } |
75af7f68 | 456 | |
392a587b JM |
457 | /* Store the address of the place in which to copy the structure the |
458 | subroutine will return. This is called from call_function. | |
459 | ||
460 | We store structs through a pointer passed in the first Argument | |
461 | register. */ | |
462 | ||
f5e1cf12 | 463 | static void |
fba45db2 | 464 | d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
392a587b JM |
465 | { |
466 | write_register (ARG1_REGNUM, (addr)); | |
467 | } | |
468 | ||
469 | /* Write into appropriate registers a function return value | |
470 | of type TYPE, given in virtual format. | |
471 | ||
472 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
473 | ||
f5e1cf12 | 474 | static void |
fba45db2 | 475 | d10v_store_return_value (struct type *type, char *valbuf) |
392a587b | 476 | { |
3d79a47c MS |
477 | char tmp = 0; |
478 | /* Only char return values need to be shifted right within R0. */ | |
479 | if (TYPE_LENGTH (type) == 1 | |
480 | && TYPE_CODE (type) == TYPE_CODE_INT) | |
481 | { | |
73937e03 AC |
482 | /* zero the high byte */ |
483 | deprecated_write_register_bytes (REGISTER_BYTE (RET1_REGNUM), &tmp, 1); | |
484 | /* copy the low byte */ | |
485 | deprecated_write_register_bytes (REGISTER_BYTE (RET1_REGNUM) + 1, | |
486 | valbuf, 1); | |
3d79a47c MS |
487 | } |
488 | else | |
73937e03 AC |
489 | deprecated_write_register_bytes (REGISTER_BYTE (RET1_REGNUM), |
490 | valbuf, TYPE_LENGTH (type)); | |
392a587b JM |
491 | } |
492 | ||
493 | /* Extract from an array REGBUF containing the (raw) register state | |
494 | the address in which a function should return its structure value, | |
495 | as a CORE_ADDR (or an expression that can be used as one). */ | |
496 | ||
f5e1cf12 | 497 | static CORE_ADDR |
fba45db2 | 498 | d10v_extract_struct_value_address (char *regbuf) |
392a587b JM |
499 | { |
500 | return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM), | |
501 | REGISTER_RAW_SIZE (ARG1_REGNUM)) | |
502 | | DMEM_START); | |
503 | } | |
504 | ||
f5e1cf12 | 505 | static CORE_ADDR |
fba45db2 | 506 | d10v_frame_saved_pc (struct frame_info *frame) |
392a587b | 507 | { |
50abf9e5 AC |
508 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame)) |
509 | return d10v_make_iaddr (deprecated_read_register_dummy (get_frame_pc (frame), | |
135c175f AC |
510 | frame->frame, |
511 | PC_REGNUM)); | |
78eac43e MS |
512 | else |
513 | return ((frame)->extra_info->return_pc); | |
392a587b JM |
514 | } |
515 | ||
392a587b JM |
516 | /* Immediately after a function call, return the saved pc. We can't |
517 | use frame->return_pc beause that is determined by reading R13 off | |
518 | the stack and that may not be written yet. */ | |
519 | ||
f5e1cf12 | 520 | static CORE_ADDR |
fba45db2 | 521 | d10v_saved_pc_after_call (struct frame_info *frame) |
392a587b | 522 | { |
c5aa993b | 523 | return ((read_register (LR_REGNUM) << 2) |
392a587b JM |
524 | | IMEM_START); |
525 | } | |
526 | ||
c906108c SS |
527 | /* Discard from the stack the innermost frame, restoring all saved |
528 | registers. */ | |
529 | ||
f5e1cf12 | 530 | static void |
fba45db2 | 531 | d10v_pop_frame (void) |
cce74817 JM |
532 | { |
533 | generic_pop_current_frame (do_d10v_pop_frame); | |
534 | } | |
535 | ||
536 | static void | |
fba45db2 | 537 | do_d10v_pop_frame (struct frame_info *fi) |
c906108c SS |
538 | { |
539 | CORE_ADDR fp; | |
540 | int regnum; | |
c906108c SS |
541 | char raw_buffer[8]; |
542 | ||
c193f6ac | 543 | fp = get_frame_base (fi); |
c906108c SS |
544 | /* fill out fsr with the address of where each */ |
545 | /* register was stored in the frame */ | |
cce74817 | 546 | d10v_frame_init_saved_regs (fi); |
c5aa993b | 547 | |
c906108c | 548 | /* now update the current registers with the old values */ |
4ce44c66 | 549 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) |
c906108c | 550 | { |
b2fb4676 | 551 | if (get_frame_saved_regs (fi)[regnum]) |
c906108c | 552 | { |
b2fb4676 | 553 | read_memory (get_frame_saved_regs (fi)[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); |
73937e03 AC |
554 | deprecated_write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, |
555 | REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
556 | } |
557 | } | |
558 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
559 | { | |
b2fb4676 | 560 | if (get_frame_saved_regs (fi)[regnum]) |
c906108c | 561 | { |
b2fb4676 | 562 | write_register (regnum, read_memory_unsigned_integer (get_frame_saved_regs (fi)[regnum], REGISTER_RAW_SIZE (regnum))); |
c906108c SS |
563 | } |
564 | } | |
b2fb4676 | 565 | if (get_frame_saved_regs (fi)[PSW_REGNUM]) |
c906108c | 566 | { |
b2fb4676 | 567 | write_register (PSW_REGNUM, read_memory_unsigned_integer (get_frame_saved_regs (fi)[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); |
c906108c SS |
568 | } |
569 | ||
570 | write_register (PC_REGNUM, read_register (LR_REGNUM)); | |
cce74817 | 571 | write_register (SP_REGNUM, fp + fi->extra_info->size); |
c906108c SS |
572 | target_store_registers (-1); |
573 | flush_cached_frames (); | |
574 | } | |
575 | ||
c5aa993b | 576 | static int |
fba45db2 | 577 | check_prologue (unsigned short op) |
c906108c SS |
578 | { |
579 | /* st rn, @-sp */ | |
580 | if ((op & 0x7E1F) == 0x6C1F) | |
581 | return 1; | |
582 | ||
583 | /* st2w rn, @-sp */ | |
584 | if ((op & 0x7E3F) == 0x6E1F) | |
585 | return 1; | |
586 | ||
587 | /* subi sp, n */ | |
588 | if ((op & 0x7FE1) == 0x01E1) | |
589 | return 1; | |
590 | ||
591 | /* mv r11, sp */ | |
592 | if (op == 0x417E) | |
593 | return 1; | |
594 | ||
595 | /* nop */ | |
596 | if (op == 0x5E00) | |
597 | return 1; | |
598 | ||
599 | /* st rn, @sp */ | |
600 | if ((op & 0x7E1F) == 0x681E) | |
601 | return 1; | |
602 | ||
603 | /* st2w rn, @sp */ | |
c5aa993b JM |
604 | if ((op & 0x7E3F) == 0x3A1E) |
605 | return 1; | |
c906108c SS |
606 | |
607 | return 0; | |
608 | } | |
609 | ||
f5e1cf12 | 610 | static CORE_ADDR |
fba45db2 | 611 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
612 | { |
613 | unsigned long op; | |
614 | unsigned short op1, op2; | |
615 | CORE_ADDR func_addr, func_end; | |
616 | struct symtab_and_line sal; | |
617 | ||
618 | /* If we have line debugging information, then the end of the */ | |
619 | /* prologue should the first assembly instruction of the first source line */ | |
620 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
621 | { | |
622 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 623 | if (sal.end && sal.end < func_end) |
c906108c SS |
624 | return sal.end; |
625 | } | |
c5aa993b JM |
626 | |
627 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
628 | return pc; /* Can't access it -- assume no prologue. */ |
629 | ||
630 | while (1) | |
631 | { | |
c5aa993b | 632 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
633 | if ((op & 0xC0000000) == 0xC0000000) |
634 | { | |
635 | /* long instruction */ | |
c5aa993b JM |
636 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
637 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
638 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
639 | break; |
640 | } | |
641 | else | |
642 | { | |
643 | /* short instructions */ | |
644 | if ((op & 0xC0000000) == 0x80000000) | |
645 | { | |
646 | op2 = (op & 0x3FFF8000) >> 15; | |
647 | op1 = op & 0x7FFF; | |
c5aa993b JM |
648 | } |
649 | else | |
c906108c SS |
650 | { |
651 | op1 = (op & 0x3FFF8000) >> 15; | |
652 | op2 = op & 0x7FFF; | |
653 | } | |
c5aa993b | 654 | if (check_prologue (op1)) |
c906108c | 655 | { |
c5aa993b | 656 | if (!check_prologue (op2)) |
c906108c SS |
657 | { |
658 | /* if the previous opcode was really part of the prologue */ | |
659 | /* and not just a NOP, then we want to break after both instructions */ | |
660 | if (op1 != 0x5E00) | |
661 | pc += 4; | |
662 | break; | |
663 | } | |
664 | } | |
665 | else | |
666 | break; | |
667 | } | |
668 | pc += 4; | |
669 | } | |
670 | return pc; | |
671 | } | |
672 | ||
a5afb99f AC |
673 | /* Given a GDB frame, determine the address of the calling function's |
674 | frame. This will be used to create a new GDB frame struct, and | |
675 | then INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC will be | |
676 | called for the new frame. */ | |
c906108c | 677 | |
f5e1cf12 | 678 | static CORE_ADDR |
fba45db2 | 679 | d10v_frame_chain (struct frame_info *fi) |
c906108c | 680 | { |
78eac43e MS |
681 | CORE_ADDR addr; |
682 | ||
683 | /* A generic call dummy's frame is the same as caller's. */ | |
50abf9e5 | 684 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame, fi->frame)) |
78eac43e MS |
685 | return fi->frame; |
686 | ||
cce74817 | 687 | d10v_frame_init_saved_regs (fi); |
c906108c | 688 | |
78eac43e | 689 | |
cce74817 JM |
690 | if (fi->extra_info->return_pc == IMEM_START |
691 | || inside_entry_file (fi->extra_info->return_pc)) | |
78eac43e MS |
692 | { |
693 | /* This is meant to halt the backtrace at "_start". | |
694 | Make sure we don't halt it at a generic dummy frame. */ | |
ae45cd16 | 695 | if (!DEPRECATED_PC_IN_CALL_DUMMY (fi->extra_info->return_pc, 0, 0)) |
78eac43e MS |
696 | return (CORE_ADDR) 0; |
697 | } | |
c906108c | 698 | |
b2fb4676 | 699 | if (!get_frame_saved_regs (fi)[FP_REGNUM]) |
c906108c | 700 | { |
b2fb4676 AC |
701 | if (!get_frame_saved_regs (fi)[SP_REGNUM] |
702 | || get_frame_saved_regs (fi)[SP_REGNUM] == STACK_START) | |
c5aa993b JM |
703 | return (CORE_ADDR) 0; |
704 | ||
b2fb4676 | 705 | return get_frame_saved_regs (fi)[SP_REGNUM]; |
c906108c SS |
706 | } |
707 | ||
b2fb4676 | 708 | addr = read_memory_unsigned_integer (get_frame_saved_regs (fi)[FP_REGNUM], |
78eac43e MS |
709 | REGISTER_RAW_SIZE (FP_REGNUM)); |
710 | if (addr == 0) | |
c5aa993b | 711 | return (CORE_ADDR) 0; |
c906108c | 712 | |
78eac43e | 713 | return d10v_make_daddr (addr); |
c5aa993b | 714 | } |
c906108c SS |
715 | |
716 | static int next_addr, uses_frame; | |
717 | ||
c5aa993b | 718 | static int |
fba45db2 | 719 | prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr) |
c906108c SS |
720 | { |
721 | int n; | |
722 | ||
723 | /* st rn, @-sp */ | |
724 | if ((op & 0x7E1F) == 0x6C1F) | |
725 | { | |
726 | n = (op & 0x1E0) >> 5; | |
727 | next_addr -= 2; | |
b2fb4676 | 728 | get_frame_saved_regs (fi)[n] = next_addr; |
c906108c SS |
729 | return 1; |
730 | } | |
731 | ||
732 | /* st2w rn, @-sp */ | |
733 | else if ((op & 0x7E3F) == 0x6E1F) | |
734 | { | |
735 | n = (op & 0x1E0) >> 5; | |
736 | next_addr -= 4; | |
b2fb4676 AC |
737 | get_frame_saved_regs (fi)[n] = next_addr; |
738 | get_frame_saved_regs (fi)[n + 1] = next_addr + 2; | |
c906108c SS |
739 | return 1; |
740 | } | |
741 | ||
742 | /* subi sp, n */ | |
743 | if ((op & 0x7FE1) == 0x01E1) | |
744 | { | |
745 | n = (op & 0x1E) >> 1; | |
746 | if (n == 0) | |
747 | n = 16; | |
748 | next_addr -= n; | |
749 | return 1; | |
750 | } | |
751 | ||
752 | /* mv r11, sp */ | |
753 | if (op == 0x417E) | |
754 | { | |
755 | uses_frame = 1; | |
756 | return 1; | |
757 | } | |
758 | ||
759 | /* nop */ | |
760 | if (op == 0x5E00) | |
761 | return 1; | |
762 | ||
763 | /* st rn, @sp */ | |
764 | if ((op & 0x7E1F) == 0x681E) | |
765 | { | |
766 | n = (op & 0x1E0) >> 5; | |
b2fb4676 | 767 | get_frame_saved_regs (fi)[n] = next_addr; |
c906108c SS |
768 | return 1; |
769 | } | |
770 | ||
771 | /* st2w rn, @sp */ | |
772 | if ((op & 0x7E3F) == 0x3A1E) | |
773 | { | |
774 | n = (op & 0x1E0) >> 5; | |
b2fb4676 AC |
775 | get_frame_saved_regs (fi)[n] = next_addr; |
776 | get_frame_saved_regs (fi)[n + 1] = next_addr + 2; | |
c906108c SS |
777 | return 1; |
778 | } | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
cce74817 JM |
783 | /* Put here the code to store, into fi->saved_regs, the addresses of |
784 | the saved registers of frame described by FRAME_INFO. This | |
785 | includes special registers such as pc and fp saved in special ways | |
786 | in the stack frame. sp is even more special: the address we return | |
787 | for it IS the sp for the next frame. */ | |
788 | ||
f5e1cf12 | 789 | static void |
fba45db2 | 790 | d10v_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
791 | { |
792 | CORE_ADDR fp, pc; | |
793 | unsigned long op; | |
794 | unsigned short op1, op2; | |
795 | int i; | |
796 | ||
797 | fp = fi->frame; | |
b2fb4676 | 798 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
799 | next_addr = 0; |
800 | ||
50abf9e5 | 801 | pc = get_pc_function_start (get_frame_pc (fi)); |
c906108c SS |
802 | |
803 | uses_frame = 0; | |
804 | while (1) | |
805 | { | |
c5aa993b | 806 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
807 | if ((op & 0xC0000000) == 0xC0000000) |
808 | { | |
809 | /* long instruction */ | |
810 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
811 | { | |
812 | /* add3 sp,sp,n */ | |
813 | short n = op & 0xFFFF; | |
814 | next_addr += n; | |
815 | } | |
816 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
817 | { | |
818 | /* st rn, @(offset,sp) */ | |
819 | short offset = op & 0xFFFF; | |
820 | short n = (op >> 20) & 0xF; | |
b2fb4676 | 821 | get_frame_saved_regs (fi)[n] = next_addr + offset; |
c906108c SS |
822 | } |
823 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
824 | { | |
825 | /* st2w rn, @(offset,sp) */ | |
826 | short offset = op & 0xFFFF; | |
827 | short n = (op >> 20) & 0xF; | |
b2fb4676 AC |
828 | get_frame_saved_regs (fi)[n] = next_addr + offset; |
829 | get_frame_saved_regs (fi)[n + 1] = next_addr + offset + 2; | |
c906108c SS |
830 | } |
831 | else | |
832 | break; | |
833 | } | |
834 | else | |
835 | { | |
836 | /* short instructions */ | |
837 | if ((op & 0xC0000000) == 0x80000000) | |
838 | { | |
839 | op2 = (op & 0x3FFF8000) >> 15; | |
840 | op1 = op & 0x7FFF; | |
c5aa993b JM |
841 | } |
842 | else | |
c906108c SS |
843 | { |
844 | op1 = (op & 0x3FFF8000) >> 15; | |
845 | op2 = op & 0x7FFF; | |
846 | } | |
78eac43e MS |
847 | if (!prologue_find_regs (op1, fi, pc) |
848 | || !prologue_find_regs (op2, fi, pc)) | |
c906108c SS |
849 | break; |
850 | } | |
851 | pc += 4; | |
852 | } | |
c5aa993b | 853 | |
cce74817 | 854 | fi->extra_info->size = -next_addr; |
c906108c SS |
855 | |
856 | if (!(fp & 0xffff)) | |
095a4c96 | 857 | fp = d10v_read_sp (); |
c906108c | 858 | |
c5aa993b | 859 | for (i = 0; i < NUM_REGS - 1; i++) |
b2fb4676 | 860 | if (get_frame_saved_regs (fi)[i]) |
c906108c | 861 | { |
b2fb4676 | 862 | get_frame_saved_regs (fi)[i] = fp - (next_addr - get_frame_saved_regs (fi)[i]); |
c906108c SS |
863 | } |
864 | ||
b2fb4676 | 865 | if (get_frame_saved_regs (fi)[LR_REGNUM]) |
c906108c | 866 | { |
78eac43e | 867 | CORE_ADDR return_pc |
b2fb4676 | 868 | = read_memory_unsigned_integer (get_frame_saved_regs (fi)[LR_REGNUM], |
78eac43e | 869 | REGISTER_RAW_SIZE (LR_REGNUM)); |
7b570125 | 870 | fi->extra_info->return_pc = d10v_make_iaddr (return_pc); |
c906108c SS |
871 | } |
872 | else | |
873 | { | |
7b570125 | 874 | fi->extra_info->return_pc = d10v_make_iaddr (read_register (LR_REGNUM)); |
c906108c | 875 | } |
c5aa993b | 876 | |
78eac43e | 877 | /* The SP is not normally (ever?) saved, but check anyway */ |
b2fb4676 | 878 | if (!get_frame_saved_regs (fi)[SP_REGNUM]) |
c906108c SS |
879 | { |
880 | /* if the FP was saved, that means the current FP is valid, */ | |
881 | /* otherwise, it isn't being used, so we use the SP instead */ | |
882 | if (uses_frame) | |
b2fb4676 | 883 | get_frame_saved_regs (fi)[SP_REGNUM] |
095a4c96 | 884 | = d10v_read_fp () + fi->extra_info->size; |
c906108c SS |
885 | else |
886 | { | |
b2fb4676 | 887 | get_frame_saved_regs (fi)[SP_REGNUM] = fp + fi->extra_info->size; |
cce74817 | 888 | fi->extra_info->frameless = 1; |
b2fb4676 | 889 | get_frame_saved_regs (fi)[FP_REGNUM] = 0; |
c906108c SS |
890 | } |
891 | } | |
892 | } | |
893 | ||
f5e1cf12 | 894 | static void |
fba45db2 | 895 | d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 896 | { |
cce74817 JM |
897 | fi->extra_info = (struct frame_extra_info *) |
898 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
899 | frame_saved_regs_zalloc (fi); | |
900 | ||
901 | fi->extra_info->frameless = 0; | |
902 | fi->extra_info->size = 0; | |
903 | fi->extra_info->return_pc = 0; | |
c906108c | 904 | |
50abf9e5 | 905 | /* If get_frame_pc (fi) is zero, but this is not the outermost frame, |
78eac43e | 906 | then let's snatch the return_pc from the callee, so that |
ae45cd16 | 907 | DEPRECATED_PC_IN_CALL_DUMMY will work. */ |
50abf9e5 AC |
908 | if (get_frame_pc (fi) == 0 && fi->level != 0 && fi->next != NULL) |
909 | deprecated_update_frame_pc_hack (fi, d10v_frame_saved_pc (fi->next)); | |
78eac43e | 910 | |
c906108c SS |
911 | /* The call dummy doesn't save any registers on the stack, so we can |
912 | return now. */ | |
50abf9e5 | 913 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame, fi->frame)) |
c906108c SS |
914 | { |
915 | return; | |
916 | } | |
917 | else | |
918 | { | |
cce74817 | 919 | d10v_frame_init_saved_regs (fi); |
c906108c SS |
920 | } |
921 | } | |
922 | ||
923 | static void | |
fba45db2 | 924 | show_regs (char *args, int from_tty) |
c906108c SS |
925 | { |
926 | int a; | |
d4f3574e SS |
927 | printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
928 | (long) read_register (PC_REGNUM), | |
7b570125 | 929 | (long) d10v_make_iaddr (read_register (PC_REGNUM)), |
d4f3574e SS |
930 | (long) read_register (PSW_REGNUM), |
931 | (long) read_register (24), | |
932 | (long) read_register (25), | |
933 | (long) read_register (23)); | |
934 | printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
935 | (long) read_register (0), | |
936 | (long) read_register (1), | |
937 | (long) read_register (2), | |
938 | (long) read_register (3), | |
939 | (long) read_register (4), | |
940 | (long) read_register (5), | |
941 | (long) read_register (6), | |
942 | (long) read_register (7)); | |
943 | printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
944 | (long) read_register (8), | |
945 | (long) read_register (9), | |
946 | (long) read_register (10), | |
947 | (long) read_register (11), | |
948 | (long) read_register (12), | |
949 | (long) read_register (13), | |
950 | (long) read_register (14), | |
951 | (long) read_register (15)); | |
4ce44c66 JM |
952 | for (a = 0; a < NR_IMAP_REGS; a++) |
953 | { | |
954 | if (a > 0) | |
955 | printf_filtered (" "); | |
956 | printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); | |
957 | } | |
958 | if (NR_DMAP_REGS == 1) | |
959 | printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); | |
960 | else | |
961 | { | |
962 | for (a = 0; a < NR_DMAP_REGS; a++) | |
963 | { | |
964 | printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); | |
965 | } | |
966 | printf_filtered ("\n"); | |
967 | } | |
968 | printf_filtered ("A0-A%d", NR_A_REGS - 1); | |
969 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) | |
c906108c SS |
970 | { |
971 | char num[MAX_REGISTER_RAW_SIZE]; | |
972 | int i; | |
973 | printf_filtered (" "); | |
4caf0990 | 974 | deprecated_read_register_gen (a, (char *) &num); |
c906108c SS |
975 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) |
976 | { | |
977 | printf_filtered ("%02x", (num[i] & 0xff)); | |
978 | } | |
979 | } | |
980 | printf_filtered ("\n"); | |
981 | } | |
982 | ||
f5e1cf12 | 983 | static CORE_ADDR |
39f77062 | 984 | d10v_read_pc (ptid_t ptid) |
c906108c | 985 | { |
39f77062 | 986 | ptid_t save_ptid; |
c906108c SS |
987 | CORE_ADDR pc; |
988 | CORE_ADDR retval; | |
989 | ||
39f77062 KB |
990 | save_ptid = inferior_ptid; |
991 | inferior_ptid = ptid; | |
c906108c | 992 | pc = (int) read_register (PC_REGNUM); |
39f77062 | 993 | inferior_ptid = save_ptid; |
7b570125 | 994 | retval = d10v_make_iaddr (pc); |
c906108c SS |
995 | return retval; |
996 | } | |
997 | ||
f5e1cf12 | 998 | static void |
39f77062 | 999 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 1000 | { |
39f77062 | 1001 | ptid_t save_ptid; |
c906108c | 1002 | |
39f77062 KB |
1003 | save_ptid = inferior_ptid; |
1004 | inferior_ptid = ptid; | |
7b570125 | 1005 | write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 1006 | inferior_ptid = save_ptid; |
c906108c SS |
1007 | } |
1008 | ||
f5e1cf12 | 1009 | static CORE_ADDR |
fba45db2 | 1010 | d10v_read_sp (void) |
c906108c | 1011 | { |
7b570125 | 1012 | return (d10v_make_daddr (read_register (SP_REGNUM))); |
c906108c SS |
1013 | } |
1014 | ||
f5e1cf12 | 1015 | static void |
fba45db2 | 1016 | d10v_write_sp (CORE_ADDR val) |
c906108c | 1017 | { |
7b570125 | 1018 | write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val)); |
c906108c SS |
1019 | } |
1020 | ||
f5e1cf12 | 1021 | static CORE_ADDR |
fba45db2 | 1022 | d10v_read_fp (void) |
c906108c | 1023 | { |
7b570125 | 1024 | return (d10v_make_daddr (read_register (FP_REGNUM))); |
c906108c SS |
1025 | } |
1026 | ||
1027 | /* Function: push_return_address (pc) | |
1028 | Set up the return address for the inferior function call. | |
1029 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
c5aa993b | 1030 | |
f5e1cf12 | 1031 | static CORE_ADDR |
fba45db2 | 1032 | d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 1033 | { |
7b570125 | 1034 | write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ())); |
c906108c SS |
1035 | return sp; |
1036 | } | |
c5aa993b | 1037 | |
c906108c | 1038 | |
7a292a7a SS |
1039 | /* When arguments must be pushed onto the stack, they go on in reverse |
1040 | order. The below implements a FILO (stack) to do this. */ | |
1041 | ||
1042 | struct stack_item | |
1043 | { | |
1044 | int len; | |
1045 | struct stack_item *prev; | |
1046 | void *data; | |
1047 | }; | |
1048 | ||
a14ed312 KB |
1049 | static struct stack_item *push_stack_item (struct stack_item *prev, |
1050 | void *contents, int len); | |
7a292a7a | 1051 | static struct stack_item * |
fba45db2 | 1052 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
1053 | { |
1054 | struct stack_item *si; | |
1055 | si = xmalloc (sizeof (struct stack_item)); | |
1056 | si->data = xmalloc (len); | |
1057 | si->len = len; | |
1058 | si->prev = prev; | |
1059 | memcpy (si->data, contents, len); | |
1060 | return si; | |
1061 | } | |
1062 | ||
a14ed312 | 1063 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 1064 | static struct stack_item * |
fba45db2 | 1065 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
1066 | { |
1067 | struct stack_item *dead = si; | |
1068 | si = si->prev; | |
b8c9b27d KB |
1069 | xfree (dead->data); |
1070 | xfree (dead); | |
7a292a7a SS |
1071 | return si; |
1072 | } | |
1073 | ||
1074 | ||
f5e1cf12 | 1075 | static CORE_ADDR |
ea7c478f | 1076 | d10v_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
fba45db2 | 1077 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
1078 | { |
1079 | int i; | |
1080 | int regnum = ARG1_REGNUM; | |
7a292a7a | 1081 | struct stack_item *si = NULL; |
7bd91a28 MS |
1082 | long val; |
1083 | ||
1084 | /* If struct_return is true, then the struct return address will | |
1085 | consume one argument-passing register. No need to actually | |
1086 | write the value to the register -- that's done by | |
1087 | d10v_store_struct_return(). */ | |
1088 | ||
1089 | if (struct_return) | |
1090 | regnum++; | |
c5aa993b | 1091 | |
c906108c SS |
1092 | /* Fill in registers and arg lists */ |
1093 | for (i = 0; i < nargs; i++) | |
1094 | { | |
ea7c478f | 1095 | struct value *arg = args[i]; |
c906108c SS |
1096 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
1097 | char *contents = VALUE_CONTENTS (arg); | |
1098 | int len = TYPE_LENGTH (type); | |
7bd91a28 MS |
1099 | int aligned_regnum = (regnum + 1) & ~1; |
1100 | ||
8b279e7a | 1101 | /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */ |
7bd91a28 MS |
1102 | if (len <= 2 && regnum <= ARGN_REGNUM) |
1103 | /* fits in a single register, do not align */ | |
1104 | { | |
1105 | val = extract_unsigned_integer (contents, len); | |
1106 | write_register (regnum++, val); | |
1107 | } | |
1108 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1109 | /* value fits in remaining registers, store keeping left | |
1110 | aligned */ | |
c906108c | 1111 | { |
7bd91a28 MS |
1112 | int b; |
1113 | regnum = aligned_regnum; | |
1114 | for (b = 0; b < (len & ~1); b += 2) | |
c906108c | 1115 | { |
7bd91a28 | 1116 | val = extract_unsigned_integer (&contents[b], 2); |
c906108c SS |
1117 | write_register (regnum++, val); |
1118 | } | |
7bd91a28 | 1119 | if (b < len) |
c906108c | 1120 | { |
7bd91a28 MS |
1121 | val = extract_unsigned_integer (&contents[b], 1); |
1122 | write_register (regnum++, (val << 8)); | |
c906108c SS |
1123 | } |
1124 | } | |
7bd91a28 MS |
1125 | else |
1126 | { | |
1127 | /* arg will go onto stack */ | |
1128 | regnum = ARGN_REGNUM + 1; | |
1129 | si = push_stack_item (si, contents, len); | |
1130 | } | |
c906108c | 1131 | } |
7a292a7a SS |
1132 | |
1133 | while (si) | |
1134 | { | |
1135 | sp = (sp - si->len) & ~1; | |
1136 | write_memory (sp, si->data, si->len); | |
1137 | si = pop_stack_item (si); | |
1138 | } | |
c5aa993b | 1139 | |
c906108c SS |
1140 | return sp; |
1141 | } | |
1142 | ||
1143 | ||
1144 | /* Given a return value in `regbuf' with a type `valtype', | |
1145 | extract and copy its value into `valbuf'. */ | |
1146 | ||
f5e1cf12 | 1147 | static void |
72623009 KB |
1148 | d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES], |
1149 | char *valbuf) | |
c906108c SS |
1150 | { |
1151 | int len; | |
3d79a47c MS |
1152 | #if 0 |
1153 | printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type), | |
1154 | TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, | |
1155 | (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), | |
1156 | REGISTER_RAW_SIZE (RET1_REGNUM))); | |
1157 | #endif | |
1158 | len = TYPE_LENGTH (type); | |
1159 | if (len == 1) | |
c906108c | 1160 | { |
3d79a47c MS |
1161 | unsigned short c; |
1162 | ||
1163 | c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), | |
1164 | REGISTER_RAW_SIZE (RET1_REGNUM)); | |
1165 | store_unsigned_integer (valbuf, 1, c); | |
1166 | } | |
1167 | else if ((len & 1) == 0) | |
1168 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len); | |
1169 | else | |
1170 | { | |
1171 | /* For return values of odd size, the first byte is in the | |
1172 | least significant part of the first register. The | |
1173 | remaining bytes in remaining registers. Interestingly, | |
1174 | when such values are passed in, the last byte is in the | |
1175 | most significant byte of that same register - wierd. */ | |
1176 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); | |
c906108c SS |
1177 | } |
1178 | } | |
1179 | ||
c2c6d25f JM |
1180 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1181 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1182 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1183 | (segmentation fault). Since the simulator knows all about how the | |
1184 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1185 | |
4ce44c66 | 1186 | static void |
c2c6d25f JM |
1187 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1188 | CORE_ADDR *targ_addr, int *targ_len) | |
1189 | { | |
4ce44c66 JM |
1190 | long out_addr; |
1191 | long out_len; | |
1192 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1193 | &out_addr, | |
1194 | d10v_dmap_register, | |
1195 | d10v_imap_register); | |
1196 | *targ_addr = out_addr; | |
1197 | *targ_len = out_len; | |
c2c6d25f JM |
1198 | } |
1199 | ||
4ce44c66 | 1200 | |
c906108c SS |
1201 | /* The following code implements access to, and display of, the D10V's |
1202 | instruction trace buffer. The buffer consists of 64K or more | |
1203 | 4-byte words of data, of which each words includes an 8-bit count, | |
1204 | an 8-bit segment number, and a 16-bit instruction address. | |
1205 | ||
1206 | In theory, the trace buffer is continuously capturing instruction | |
1207 | data that the CPU presents on its "debug bus", but in practice, the | |
1208 | ROMified GDB stub only enables tracing when it continues or steps | |
1209 | the program, and stops tracing when the program stops; so it | |
1210 | actually works for GDB to read the buffer counter out of memory and | |
1211 | then read each trace word. The counter records where the tracing | |
1212 | stops, but there is no record of where it started, so we remember | |
1213 | the PC when we resumed and then search backwards in the trace | |
1214 | buffer for a word that includes that address. This is not perfect, | |
1215 | because you will miss trace data if the resumption PC is the target | |
1216 | of a branch. (The value of the buffer counter is semi-random, any | |
1217 | trace data from a previous program stop is gone.) */ | |
1218 | ||
1219 | /* The address of the last word recorded in the trace buffer. */ | |
1220 | ||
1221 | #define DBBC_ADDR (0xd80000) | |
1222 | ||
1223 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1224 | ||
1225 | #define TRACE_BUFFER_BASE (0xf40000) | |
1226 | ||
a14ed312 | 1227 | static void trace_command (char *, int); |
c906108c | 1228 | |
a14ed312 | 1229 | static void untrace_command (char *, int); |
c906108c | 1230 | |
a14ed312 | 1231 | static void trace_info (char *, int); |
c906108c | 1232 | |
a14ed312 | 1233 | static void tdisassemble_command (char *, int); |
c906108c | 1234 | |
a14ed312 | 1235 | static void display_trace (int, int); |
c906108c SS |
1236 | |
1237 | /* True when instruction traces are being collected. */ | |
1238 | ||
1239 | static int tracing; | |
1240 | ||
1241 | /* Remembered PC. */ | |
1242 | ||
1243 | static CORE_ADDR last_pc; | |
1244 | ||
1245 | /* True when trace output should be displayed whenever program stops. */ | |
1246 | ||
1247 | static int trace_display; | |
1248 | ||
1249 | /* True when trace listing should include source lines. */ | |
1250 | ||
1251 | static int default_trace_show_source = 1; | |
1252 | ||
c5aa993b JM |
1253 | struct trace_buffer |
1254 | { | |
1255 | int size; | |
1256 | short *counts; | |
1257 | CORE_ADDR *addrs; | |
1258 | } | |
1259 | trace_data; | |
c906108c SS |
1260 | |
1261 | static void | |
fba45db2 | 1262 | trace_command (char *args, int from_tty) |
c906108c SS |
1263 | { |
1264 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1265 | trace_data.size = 0; | |
1266 | if (trace_data.counts == NULL) | |
c5aa993b | 1267 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1268 | if (trace_data.addrs == NULL) |
c5aa993b | 1269 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1270 | |
1271 | tracing = 1; | |
1272 | ||
1273 | printf_filtered ("Tracing is now on.\n"); | |
1274 | } | |
1275 | ||
1276 | static void | |
fba45db2 | 1277 | untrace_command (char *args, int from_tty) |
c906108c SS |
1278 | { |
1279 | tracing = 0; | |
1280 | ||
1281 | printf_filtered ("Tracing is now off.\n"); | |
1282 | } | |
1283 | ||
1284 | static void | |
fba45db2 | 1285 | trace_info (char *args, int from_tty) |
c906108c SS |
1286 | { |
1287 | int i; | |
1288 | ||
1289 | if (trace_data.size) | |
1290 | { | |
1291 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1292 | ||
1293 | for (i = 0; i < trace_data.size; ++i) | |
1294 | { | |
d4f3574e SS |
1295 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1296 | i, | |
1297 | trace_data.counts[i], | |
c906108c | 1298 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1299 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1300 | } |
1301 | } | |
1302 | else | |
1303 | printf_filtered ("No entries in trace buffer.\n"); | |
1304 | ||
1305 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1306 | } | |
1307 | ||
1308 | /* Print the instruction at address MEMADDR in debugged memory, | |
1309 | on STREAM. Returns length of the instruction, in bytes. */ | |
1310 | ||
1311 | static int | |
fba45db2 | 1312 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1313 | { |
1314 | /* If there's no disassembler, something is very wrong. */ | |
1315 | if (tm_print_insn == NULL) | |
8e65ff28 AC |
1316 | internal_error (__FILE__, __LINE__, |
1317 | "print_insn: no disassembler"); | |
c906108c | 1318 | |
d7449b42 | 1319 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1320 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; |
1321 | else | |
1322 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
2bf0cb65 | 1323 | return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info); |
c906108c SS |
1324 | } |
1325 | ||
392a587b | 1326 | static void |
fba45db2 | 1327 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1328 | { |
1329 | if (!tracing) | |
1330 | return; | |
1331 | ||
1332 | last_pc = read_register (PC_REGNUM); | |
1333 | } | |
1334 | ||
1335 | /* Collect trace data from the target board and format it into a form | |
1336 | more useful for display. */ | |
1337 | ||
392a587b | 1338 | static void |
fba45db2 | 1339 | d10v_eva_get_trace_data (void) |
c906108c SS |
1340 | { |
1341 | int count, i, j, oldsize; | |
1342 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1343 | unsigned int last_trace, trace_word, next_word; | |
1344 | unsigned int *tmpspace; | |
1345 | ||
1346 | if (!tracing) | |
1347 | return; | |
1348 | ||
c5aa993b | 1349 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1350 | |
1351 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1352 | ||
1353 | /* Collect buffer contents from the target, stopping when we reach | |
1354 | the word recorded when execution resumed. */ | |
1355 | ||
1356 | count = 0; | |
1357 | while (last_trace > 0) | |
1358 | { | |
1359 | QUIT; | |
1360 | trace_word = | |
1361 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1362 | trace_addr = trace_word & 0xffff; | |
1363 | last_trace -= 4; | |
1364 | /* Ignore an apparently nonsensical entry. */ | |
1365 | if (trace_addr == 0xffd5) | |
1366 | continue; | |
1367 | tmpspace[count++] = trace_word; | |
1368 | if (trace_addr == last_pc) | |
1369 | break; | |
1370 | if (count > 65535) | |
1371 | break; | |
1372 | } | |
1373 | ||
1374 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1375 | include the last instruction executed and transforming the address | |
1376 | into something that GDB likes. */ | |
1377 | ||
1378 | for (i = 0; i < count; ++i) | |
1379 | { | |
1380 | trace_word = tmpspace[i]; | |
1381 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1382 | trace_addr = trace_word & 0xffff; | |
1383 | next_cnt = (next_word >> 24) & 0xff; | |
1384 | j = trace_data.size + count - i - 1; | |
1385 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1386 | trace_data.counts[j] = next_cnt + 1; | |
1387 | } | |
1388 | ||
1389 | oldsize = trace_data.size; | |
1390 | trace_data.size += count; | |
1391 | ||
b8c9b27d | 1392 | xfree (tmpspace); |
c906108c SS |
1393 | |
1394 | if (trace_display) | |
1395 | display_trace (oldsize, trace_data.size); | |
1396 | } | |
1397 | ||
1398 | static void | |
fba45db2 | 1399 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1400 | { |
1401 | int i, count; | |
1402 | CORE_ADDR low, high; | |
1403 | char *space_index; | |
1404 | ||
1405 | if (!arg) | |
1406 | { | |
1407 | low = 0; | |
1408 | high = trace_data.size; | |
1409 | } | |
1410 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1411 | { | |
1412 | low = parse_and_eval_address (arg); | |
1413 | high = low + 5; | |
1414 | } | |
1415 | else | |
1416 | { | |
1417 | /* Two arguments. */ | |
1418 | *space_index = '\0'; | |
1419 | low = parse_and_eval_address (arg); | |
1420 | high = parse_and_eval_address (space_index + 1); | |
1421 | if (high < low) | |
1422 | high = low; | |
1423 | } | |
1424 | ||
d4f3574e | 1425 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1426 | |
1427 | display_trace (low, high); | |
1428 | ||
1429 | printf_filtered ("End of trace dump.\n"); | |
1430 | gdb_flush (gdb_stdout); | |
1431 | } | |
1432 | ||
1433 | static void | |
fba45db2 | 1434 | display_trace (int low, int high) |
c906108c SS |
1435 | { |
1436 | int i, count, trace_show_source, first, suppress; | |
1437 | CORE_ADDR next_address; | |
1438 | ||
1439 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1440 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1441 | { |
1442 | trace_show_source = 0; | |
1443 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1444 | printf_filtered ("Trace will not display any source.\n"); | |
1445 | } | |
1446 | ||
1447 | first = 1; | |
1448 | suppress = 0; | |
1449 | for (i = low; i < high; ++i) | |
1450 | { | |
1451 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1452 | count = trace_data.counts[i]; |
c906108c SS |
1453 | while (count-- > 0) |
1454 | { | |
1455 | QUIT; | |
1456 | if (trace_show_source) | |
1457 | { | |
1458 | struct symtab_and_line sal, sal_prev; | |
1459 | ||
1460 | sal_prev = find_pc_line (next_address - 4, 0); | |
1461 | sal = find_pc_line (next_address, 0); | |
1462 | ||
1463 | if (sal.symtab) | |
1464 | { | |
1465 | if (first || sal.line != sal_prev.line) | |
1466 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1467 | suppress = 0; | |
1468 | } | |
1469 | else | |
1470 | { | |
1471 | if (!suppress) | |
1472 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1473 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1474 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1475 | suppress = 1; |
1476 | } | |
1477 | } | |
1478 | first = 0; | |
1479 | print_address (next_address, gdb_stdout); | |
1480 | printf_filtered (":"); | |
1481 | printf_filtered ("\t"); | |
1482 | wrap_here (" "); | |
1483 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1484 | printf_filtered ("\n"); | |
1485 | gdb_flush (gdb_stdout); | |
1486 | } | |
1487 | } | |
1488 | } | |
1489 | ||
ac9a91a7 | 1490 | |
0f71a2f6 | 1491 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1492 | |
0f71a2f6 | 1493 | static struct gdbarch * |
fba45db2 | 1494 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1495 | { |
c5aa993b JM |
1496 | static LONGEST d10v_call_dummy_words[] = |
1497 | {0}; | |
0f71a2f6 | 1498 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1499 | int d10v_num_regs; |
1500 | struct gdbarch_tdep *tdep; | |
1501 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1502 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1503 | |
4ce44c66 JM |
1504 | /* Find a candidate among the list of pre-declared architectures. */ |
1505 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1506 | if (arches != NULL) |
1507 | return arches->gdbarch; | |
4ce44c66 JM |
1508 | |
1509 | /* None found, create a new architecture from the information | |
1510 | provided. */ | |
1511 | tdep = XMALLOC (struct gdbarch_tdep); | |
1512 | gdbarch = gdbarch_alloc (&info, tdep); | |
1513 | ||
a5afb99f AC |
1514 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is |
1515 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ | |
1516 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); | |
1517 | ||
4ce44c66 JM |
1518 | switch (info.bfd_arch_info->mach) |
1519 | { | |
1520 | case bfd_mach_d10v_ts2: | |
1521 | d10v_num_regs = 37; | |
1522 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1523 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1524 | tdep->a0_regnum = TS2_A0_REGNUM; |
1525 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1526 | tdep->dmap_register = d10v_ts2_dmap_register; |
1527 | tdep->imap_register = d10v_ts2_imap_register; | |
1528 | break; | |
1529 | default: | |
1530 | case bfd_mach_d10v_ts3: | |
1531 | d10v_num_regs = 42; | |
1532 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1533 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1534 | tdep->a0_regnum = TS3_A0_REGNUM; |
1535 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1536 | tdep->dmap_register = d10v_ts3_dmap_register; |
1537 | tdep->imap_register = d10v_ts3_imap_register; | |
1538 | break; | |
1539 | } | |
0f71a2f6 JM |
1540 | |
1541 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1542 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1543 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
0f71a2f6 JM |
1544 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); |
1545 | set_gdbarch_write_sp (gdbarch, d10v_write_sp); | |
1546 | ||
1547 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1548 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1549 | set_gdbarch_fp_regnum (gdbarch, 11); | |
1550 | set_gdbarch_pc_regnum (gdbarch, 18); | |
1551 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1552 | set_gdbarch_register_size (gdbarch, 2); | |
1553 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1554 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1555 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
1556 | set_gdbarch_max_register_raw_size (gdbarch, 8); | |
8b279e7a | 1557 | set_gdbarch_register_virtual_size (gdbarch, generic_register_size); |
0f71a2f6 JM |
1558 | set_gdbarch_max_register_virtual_size (gdbarch, 8); |
1559 | set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); | |
1560 | ||
75af7f68 JB |
1561 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1562 | set_gdbarch_addr_bit (gdbarch, 32); | |
1563 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1564 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1565 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1566 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1567 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1568 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1569 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e AC |
1570 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1571 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1572 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1573 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1574 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1575 | switch (info.byte_order) |
1576 | { | |
d7449b42 | 1577 | case BFD_ENDIAN_BIG: |
f0d4cc9e AC |
1578 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
1579 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1580 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1581 | break; | |
778eb05e | 1582 | case BFD_ENDIAN_LITTLE: |
f0d4cc9e AC |
1583 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
1584 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1585 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1586 | break; | |
1587 | default: | |
8e65ff28 AC |
1588 | internal_error (__FILE__, __LINE__, |
1589 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1590 | } |
0f71a2f6 | 1591 | |
0f71a2f6 | 1592 | set_gdbarch_call_dummy_length (gdbarch, 0); |
0f71a2f6 JM |
1593 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
1594 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
1595 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
1596 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
0f71a2f6 JM |
1597 | set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); |
1598 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); | |
1599 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
1600 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
0f71a2f6 JM |
1601 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); |
1602 | ||
26e9b323 | 1603 | set_gdbarch_deprecated_extract_return_value (gdbarch, d10v_extract_return_value); |
0f71a2f6 JM |
1604 | set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); |
1605 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
1606 | set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); | |
1607 | ||
0f71a2f6 | 1608 | set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); |
ebba8386 | 1609 | set_gdbarch_deprecated_store_return_value (gdbarch, d10v_store_return_value); |
26e9b323 | 1610 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); |
0f71a2f6 JM |
1611 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); |
1612 | ||
1613 | set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs); | |
1614 | set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info); | |
1615 | ||
1616 | set_gdbarch_pop_frame (gdbarch, d10v_pop_frame); | |
1617 | ||
1618 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); | |
1619 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1620 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1621 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1622 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1623 | ||
1624 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1625 | ||
1626 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1627 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
1628 | set_gdbarch_frame_chain (gdbarch, d10v_frame_chain); | |
1629 | set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid); | |
1630 | set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc); | |
f4ded5b1 | 1631 | |
0f71a2f6 JM |
1632 | set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); |
1633 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
23964bcd | 1634 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1635 | |
7c7651b2 | 1636 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
0a49d05e | 1637 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); |
7c7651b2 | 1638 | |
0f71a2f6 JM |
1639 | return gdbarch; |
1640 | } | |
1641 | ||
1642 | ||
507f3c78 KB |
1643 | extern void (*target_resume_hook) (void); |
1644 | extern void (*target_wait_loop_hook) (void); | |
c906108c SS |
1645 | |
1646 | void | |
fba45db2 | 1647 | _initialize_d10v_tdep (void) |
c906108c | 1648 | { |
0f71a2f6 JM |
1649 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1650 | ||
c906108c SS |
1651 | tm_print_insn = print_insn_d10v; |
1652 | ||
1653 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1654 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1655 | ||
1656 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
1657 | ||
cff3e48b | 1658 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1659 | "Enable tracing of instruction execution."); |
1660 | ||
cff3e48b | 1661 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1662 | "Disable tracing of instruction execution."); |
1663 | ||
cff3e48b | 1664 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1665 | "Disassemble the trace buffer.\n\ |
1666 | Two optional arguments specify a range of trace buffer entries\n\ | |
1667 | as reported by info trace (NOT addresses!)."); | |
1668 | ||
cff3e48b | 1669 | add_info ("itrace", trace_info, |
c906108c SS |
1670 | "Display info about the trace data buffer."); |
1671 | ||
cff3e48b | 1672 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1673 | var_integer, (char *) &trace_display, |
1674 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1675 | &showlist); |
cff3e48b | 1676 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1677 | var_integer, (char *) &default_trace_show_source, |
1678 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1679 | &showlist); |
1680 | ||
c5aa993b | 1681 | } |