Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
b6ba6518 KB |
2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 |
3 | Free Software Foundation, Inc. | |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "obstack.h" | |
27 | #include "symtab.h" | |
28 | #include "gdbtypes.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdb_string.h" | |
32 | #include "value.h" | |
33 | #include "inferior.h" | |
c5aa993b | 34 | #include "dis-asm.h" |
c906108c SS |
35 | #include "symfile.h" |
36 | #include "objfiles.h" | |
104c1213 | 37 | #include "language.h" |
28d069e6 | 38 | #include "arch-utils.h" |
4e052eda | 39 | #include "regcache.h" |
c906108c | 40 | |
f0d4cc9e | 41 | #include "floatformat.h" |
4ce44c66 JM |
42 | #include "sim-d10v.h" |
43 | ||
44 | #undef XMALLOC | |
45 | #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE))) | |
46 | ||
cce74817 | 47 | struct frame_extra_info |
c5aa993b JM |
48 | { |
49 | CORE_ADDR return_pc; | |
50 | int frameless; | |
51 | int size; | |
52 | }; | |
cce74817 | 53 | |
4ce44c66 JM |
54 | struct gdbarch_tdep |
55 | { | |
56 | int a0_regnum; | |
57 | int nr_dmap_regs; | |
58 | unsigned long (*dmap_register) (int nr); | |
59 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
60 | }; |
61 | ||
62 | /* These are the addresses the D10V-EVA board maps data and | |
63 | instruction memory to. */ | |
cce74817 | 64 | |
cff3e48b | 65 | #define DMEM_START 0x2000000 |
cce74817 JM |
66 | #define IMEM_START 0x1000000 |
67 | #define STACK_START 0x0007ffe | |
68 | ||
4ce44c66 JM |
69 | /* d10v register names. */ |
70 | ||
71 | enum | |
72 | { | |
73 | R0_REGNUM = 0, | |
74 | LR_REGNUM = 13, | |
75 | PSW_REGNUM = 16, | |
76 | NR_IMAP_REGS = 2, | |
77 | NR_A_REGS = 2 | |
78 | }; | |
79 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) | |
80 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
81 | ||
82 | /* d10v calling convention. */ | |
cce74817 JM |
83 | |
84 | #define ARG1_REGNUM R0_REGNUM | |
85 | #define ARGN_REGNUM 3 | |
86 | #define RET1_REGNUM R0_REGNUM | |
87 | ||
392a587b JM |
88 | /* Local functions */ |
89 | ||
a14ed312 | 90 | extern void _initialize_d10v_tdep (void); |
392a587b | 91 | |
a14ed312 | 92 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 93 | |
a14ed312 | 94 | static void d10v_eva_get_trace_data (void); |
c906108c | 95 | |
a14ed312 KB |
96 | static int prologue_find_regs (unsigned short op, struct frame_info *fi, |
97 | CORE_ADDR addr); | |
cce74817 | 98 | |
f5e1cf12 | 99 | static void d10v_frame_init_saved_regs (struct frame_info *); |
cce74817 | 100 | |
a14ed312 | 101 | static void do_d10v_pop_frame (struct frame_info *fi); |
cce74817 | 102 | |
f5e1cf12 | 103 | static int |
72623009 | 104 | d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame) |
c906108c | 105 | { |
02da6206 JSC |
106 | return ((chain) != 0 && (frame) != 0 |
107 | && (frame)->pc > IMEM_START | |
108 | && !inside_entry_file (FRAME_SAVED_PC (frame))); | |
c906108c SS |
109 | } |
110 | ||
23964bcd | 111 | static CORE_ADDR |
489137c0 AC |
112 | d10v_stack_align (CORE_ADDR len) |
113 | { | |
114 | return (len + 1) & ~1; | |
115 | } | |
c906108c SS |
116 | |
117 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
118 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
119 | and TYPE is the type (which is known to be struct, union or array). | |
120 | ||
121 | The d10v returns anything less than 8 bytes in size in | |
122 | registers. */ | |
123 | ||
f5e1cf12 | 124 | static int |
fba45db2 | 125 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 126 | { |
02da6206 JSC |
127 | long alignment; |
128 | int i; | |
129 | /* The d10v only passes a struct in a register when that structure | |
130 | has an alignment that matches the size of a register. */ | |
131 | /* If the structure doesn't fit in 4 registers, put it on the | |
132 | stack. */ | |
133 | if (TYPE_LENGTH (type) > 8) | |
134 | return 1; | |
135 | /* If the struct contains only one field, don't put it on the stack | |
136 | - gcc can fit it in one or more registers. */ | |
137 | if (TYPE_NFIELDS (type) == 1) | |
138 | return 0; | |
139 | alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); | |
140 | for (i = 1; i < TYPE_NFIELDS (type); i++) | |
141 | { | |
142 | /* If the alignment changes, just assume it goes on the | |
143 | stack. */ | |
144 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) | |
145 | return 1; | |
146 | } | |
147 | /* If the alignment is suitable for the d10v's 16 bit registers, | |
148 | don't put it on the stack. */ | |
149 | if (alignment == 2 || alignment == 4) | |
150 | return 0; | |
151 | return 1; | |
c906108c SS |
152 | } |
153 | ||
154 | ||
f5e1cf12 | 155 | static unsigned char * |
fba45db2 | 156 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 157 | { |
c5aa993b JM |
158 | static unsigned char breakpoint[] = |
159 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
160 | *lenptr = sizeof (breakpoint); |
161 | return breakpoint; | |
162 | } | |
163 | ||
4ce44c66 JM |
164 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
165 | when the reg_nr isn't valid. */ | |
166 | ||
167 | enum ts2_regnums | |
168 | { | |
169 | TS2_IMAP0_REGNUM = 32, | |
170 | TS2_DMAP_REGNUM = 34, | |
171 | TS2_NR_DMAP_REGS = 1, | |
172 | TS2_A0_REGNUM = 35 | |
173 | }; | |
174 | ||
175 | static char * | |
176 | d10v_ts2_register_name (int reg_nr) | |
392a587b | 177 | { |
c5aa993b JM |
178 | static char *register_names[] = |
179 | { | |
180 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
181 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
182 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
183 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
184 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
185 | }; |
186 | if (reg_nr < 0) | |
187 | return NULL; | |
188 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
189 | return NULL; | |
c5aa993b | 190 | return register_names[reg_nr]; |
392a587b JM |
191 | } |
192 | ||
4ce44c66 JM |
193 | enum ts3_regnums |
194 | { | |
195 | TS3_IMAP0_REGNUM = 36, | |
196 | TS3_DMAP0_REGNUM = 38, | |
197 | TS3_NR_DMAP_REGS = 4, | |
198 | TS3_A0_REGNUM = 32 | |
199 | }; | |
200 | ||
201 | static char * | |
202 | d10v_ts3_register_name (int reg_nr) | |
203 | { | |
204 | static char *register_names[] = | |
205 | { | |
206 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
207 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
208 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
209 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
210 | "a0", "a1", | |
211 | "spi", "spu", | |
212 | "imap0", "imap1", | |
213 | "dmap0", "dmap1", "dmap2", "dmap3" | |
214 | }; | |
215 | if (reg_nr < 0) | |
216 | return NULL; | |
217 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
218 | return NULL; | |
219 | return register_names[reg_nr]; | |
220 | } | |
221 | ||
bf93dfed JB |
222 | /* Access the DMAP/IMAP registers in a target independent way. |
223 | ||
224 | Divide the D10V's 64k data space into four 16k segments: | |
225 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
226 | 0xc000 -- 0xffff. | |
227 | ||
228 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
229 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
230 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
231 | unified memory or instruction memory, under the control of the | |
232 | single DMAP register. | |
233 | ||
234 | On the TS3, there are four DMAP registers, each of which controls | |
235 | one of the segments. */ | |
4ce44c66 JM |
236 | |
237 | static unsigned long | |
238 | d10v_ts2_dmap_register (int reg_nr) | |
239 | { | |
240 | switch (reg_nr) | |
241 | { | |
242 | case 0: | |
243 | case 1: | |
244 | return 0x2000; | |
245 | case 2: | |
246 | return read_register (TS2_DMAP_REGNUM); | |
247 | default: | |
248 | return 0; | |
249 | } | |
250 | } | |
251 | ||
252 | static unsigned long | |
253 | d10v_ts3_dmap_register (int reg_nr) | |
254 | { | |
255 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
256 | } | |
257 | ||
258 | static unsigned long | |
259 | d10v_dmap_register (int reg_nr) | |
260 | { | |
261 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
262 | } | |
263 | ||
264 | static unsigned long | |
265 | d10v_ts2_imap_register (int reg_nr) | |
266 | { | |
267 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
268 | } | |
269 | ||
270 | static unsigned long | |
271 | d10v_ts3_imap_register (int reg_nr) | |
272 | { | |
273 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
274 | } | |
275 | ||
276 | static unsigned long | |
277 | d10v_imap_register (int reg_nr) | |
278 | { | |
279 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
280 | } | |
281 | ||
282 | /* MAP GDB's internal register numbering (determined by the layout fo | |
283 | the REGISTER_BYTE array) onto the simulator's register | |
284 | numbering. */ | |
285 | ||
286 | static int | |
287 | d10v_ts2_register_sim_regno (int nr) | |
288 | { | |
289 | if (nr >= TS2_IMAP0_REGNUM | |
290 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
291 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
292 | if (nr == TS2_DMAP_REGNUM) | |
293 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
294 | if (nr >= TS2_A0_REGNUM | |
295 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
296 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
297 | return nr; | |
298 | } | |
299 | ||
300 | static int | |
301 | d10v_ts3_register_sim_regno (int nr) | |
302 | { | |
303 | if (nr >= TS3_IMAP0_REGNUM | |
304 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
305 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
306 | if (nr >= TS3_DMAP0_REGNUM | |
307 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
308 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
309 | if (nr >= TS3_A0_REGNUM | |
310 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
311 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
312 | return nr; | |
313 | } | |
314 | ||
392a587b JM |
315 | /* Index within `registers' of the first byte of the space for |
316 | register REG_NR. */ | |
317 | ||
f5e1cf12 | 318 | static int |
fba45db2 | 319 | d10v_register_byte (int reg_nr) |
392a587b | 320 | { |
4ce44c66 | 321 | if (reg_nr < A0_REGNUM) |
392a587b | 322 | return (reg_nr * 2); |
4ce44c66 JM |
323 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
324 | return (A0_REGNUM * 2 | |
325 | + (reg_nr - A0_REGNUM) * 8); | |
326 | else | |
327 | return (A0_REGNUM * 2 | |
328 | + NR_A_REGS * 8 | |
329 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
330 | } |
331 | ||
332 | /* Number of bytes of storage in the actual machine representation for | |
333 | register REG_NR. */ | |
334 | ||
f5e1cf12 | 335 | static int |
fba45db2 | 336 | d10v_register_raw_size (int reg_nr) |
392a587b | 337 | { |
4ce44c66 JM |
338 | if (reg_nr < A0_REGNUM) |
339 | return 2; | |
340 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
341 | return 8; |
342 | else | |
343 | return 2; | |
344 | } | |
345 | ||
346 | /* Number of bytes of storage in the program's representation | |
347 | for register N. */ | |
348 | ||
f5e1cf12 | 349 | static int |
fba45db2 | 350 | d10v_register_virtual_size (int reg_nr) |
392a587b | 351 | { |
4ce44c66 | 352 | return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr)); |
392a587b JM |
353 | } |
354 | ||
355 | /* Return the GDB type object for the "standard" data type | |
356 | of data in register N. */ | |
357 | ||
f5e1cf12 | 358 | static struct type * |
fba45db2 | 359 | d10v_register_virtual_type (int reg_nr) |
392a587b | 360 | { |
75af7f68 JB |
361 | if (reg_nr == PC_REGNUM) |
362 | return builtin_type_void_func_ptr; | |
363 | else if (reg_nr >= A0_REGNUM | |
4ce44c66 JM |
364 | && reg_nr < (A0_REGNUM + NR_A_REGS)) |
365 | return builtin_type_int64; | |
392a587b | 366 | else |
4ce44c66 | 367 | return builtin_type_int16; |
392a587b JM |
368 | } |
369 | ||
f5e1cf12 | 370 | static CORE_ADDR |
fba45db2 | 371 | d10v_make_daddr (CORE_ADDR x) |
392a587b JM |
372 | { |
373 | return ((x) | DMEM_START); | |
374 | } | |
375 | ||
f5e1cf12 | 376 | static CORE_ADDR |
fba45db2 | 377 | d10v_make_iaddr (CORE_ADDR x) |
392a587b JM |
378 | { |
379 | return (((x) << 2) | IMEM_START); | |
380 | } | |
381 | ||
f5e1cf12 | 382 | static int |
fba45db2 | 383 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
384 | { |
385 | return (((x) & 0x3000000) == DMEM_START); | |
386 | } | |
387 | ||
f5e1cf12 | 388 | static int |
fba45db2 | 389 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
390 | { |
391 | return (((x) & 0x3000000) == IMEM_START); | |
392 | } | |
393 | ||
394 | ||
f5e1cf12 | 395 | static CORE_ADDR |
fba45db2 | 396 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
397 | { |
398 | return (((x) >> 2) & 0xffff); | |
399 | } | |
400 | ||
f5e1cf12 | 401 | static CORE_ADDR |
fba45db2 | 402 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
403 | { |
404 | return ((x) & 0xffff); | |
405 | } | |
406 | ||
75af7f68 JB |
407 | static void |
408 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
409 | { | |
410 | /* Is it a code address? */ | |
411 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
412 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
413 | { | |
414 | #if 0 | |
415 | if (! d10v_iaddr_p (addr)) | |
416 | { | |
417 | warning_begin (); | |
418 | fprintf_unfiltered (gdb_stderr, "address `"); | |
419 | print_address_numeric (addr, 1, gdb_stderr); | |
420 | fprintf_unfiltered (gdb_stderr, "' is not a code address\n"); | |
421 | } | |
422 | #endif | |
423 | ||
424 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
425 | d10v_convert_iaddr_to_raw (addr)); | |
426 | } | |
427 | else | |
428 | { | |
429 | /* Strip off any upper segment bits. */ | |
430 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
431 | d10v_convert_daddr_to_raw (addr)); | |
432 | } | |
433 | } | |
434 | ||
435 | static CORE_ADDR | |
436 | d10v_pointer_to_address (struct type *type, void *buf) | |
437 | { | |
438 | CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type)); | |
439 | ||
440 | /* Is it a code address? */ | |
441 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
86884b37 MS |
442 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD || |
443 | (TYPE_FLAGS (TYPE_TARGET_TYPE (type)) & TYPE_FLAG_CODE_SPACE) != 0) | |
75af7f68 JB |
444 | return d10v_make_iaddr (addr); |
445 | else | |
446 | return d10v_make_daddr (addr); | |
447 | } | |
448 | ||
fc0c74b1 AC |
449 | static CORE_ADDR |
450 | d10v_integer_to_address (struct type *type, void *buf) | |
451 | { | |
452 | LONGEST val; | |
453 | val = unpack_long (type, buf); | |
454 | if (TYPE_CODE (type) == TYPE_CODE_INT | |
455 | && TYPE_LENGTH (type) <= TYPE_LENGTH (builtin_type_void_data_ptr)) | |
456 | /* Convert small integers that would would be directly copied into | |
457 | a pointer variable into an address pointing into data space. */ | |
458 | return d10v_make_daddr (val & 0xffff); | |
459 | else | |
460 | /* The value is too large to fit in a pointer. Assume this was | |
461 | intentional and that the user in fact specified a raw address. */ | |
462 | return val; | |
463 | } | |
75af7f68 | 464 | |
392a587b JM |
465 | /* Store the address of the place in which to copy the structure the |
466 | subroutine will return. This is called from call_function. | |
467 | ||
468 | We store structs through a pointer passed in the first Argument | |
469 | register. */ | |
470 | ||
f5e1cf12 | 471 | static void |
fba45db2 | 472 | d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
392a587b JM |
473 | { |
474 | write_register (ARG1_REGNUM, (addr)); | |
475 | } | |
476 | ||
477 | /* Write into appropriate registers a function return value | |
478 | of type TYPE, given in virtual format. | |
479 | ||
480 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
481 | ||
f5e1cf12 | 482 | static void |
fba45db2 | 483 | d10v_store_return_value (struct type *type, char *valbuf) |
392a587b JM |
484 | { |
485 | write_register_bytes (REGISTER_BYTE (RET1_REGNUM), | |
486 | valbuf, | |
487 | TYPE_LENGTH (type)); | |
488 | } | |
489 | ||
490 | /* Extract from an array REGBUF containing the (raw) register state | |
491 | the address in which a function should return its structure value, | |
492 | as a CORE_ADDR (or an expression that can be used as one). */ | |
493 | ||
f5e1cf12 | 494 | static CORE_ADDR |
fba45db2 | 495 | d10v_extract_struct_value_address (char *regbuf) |
392a587b JM |
496 | { |
497 | return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM), | |
498 | REGISTER_RAW_SIZE (ARG1_REGNUM)) | |
499 | | DMEM_START); | |
500 | } | |
501 | ||
f5e1cf12 | 502 | static CORE_ADDR |
fba45db2 | 503 | d10v_frame_saved_pc (struct frame_info *frame) |
392a587b | 504 | { |
cce74817 | 505 | return ((frame)->extra_info->return_pc); |
392a587b JM |
506 | } |
507 | ||
392a587b JM |
508 | /* Immediately after a function call, return the saved pc. We can't |
509 | use frame->return_pc beause that is determined by reading R13 off | |
510 | the stack and that may not be written yet. */ | |
511 | ||
f5e1cf12 | 512 | static CORE_ADDR |
fba45db2 | 513 | d10v_saved_pc_after_call (struct frame_info *frame) |
392a587b | 514 | { |
c5aa993b | 515 | return ((read_register (LR_REGNUM) << 2) |
392a587b JM |
516 | | IMEM_START); |
517 | } | |
518 | ||
c906108c SS |
519 | /* Discard from the stack the innermost frame, restoring all saved |
520 | registers. */ | |
521 | ||
f5e1cf12 | 522 | static void |
fba45db2 | 523 | d10v_pop_frame (void) |
cce74817 JM |
524 | { |
525 | generic_pop_current_frame (do_d10v_pop_frame); | |
526 | } | |
527 | ||
528 | static void | |
fba45db2 | 529 | do_d10v_pop_frame (struct frame_info *fi) |
c906108c SS |
530 | { |
531 | CORE_ADDR fp; | |
532 | int regnum; | |
c906108c SS |
533 | char raw_buffer[8]; |
534 | ||
cce74817 | 535 | fp = FRAME_FP (fi); |
c906108c SS |
536 | /* fill out fsr with the address of where each */ |
537 | /* register was stored in the frame */ | |
cce74817 | 538 | d10v_frame_init_saved_regs (fi); |
c5aa993b | 539 | |
c906108c | 540 | /* now update the current registers with the old values */ |
4ce44c66 | 541 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) |
c906108c | 542 | { |
cce74817 | 543 | if (fi->saved_regs[regnum]) |
c906108c | 544 | { |
c5aa993b JM |
545 | read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); |
546 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
547 | } |
548 | } | |
549 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
550 | { | |
cce74817 | 551 | if (fi->saved_regs[regnum]) |
c906108c | 552 | { |
c5aa993b | 553 | write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum))); |
c906108c SS |
554 | } |
555 | } | |
cce74817 | 556 | if (fi->saved_regs[PSW_REGNUM]) |
c906108c | 557 | { |
c5aa993b | 558 | write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); |
c906108c SS |
559 | } |
560 | ||
561 | write_register (PC_REGNUM, read_register (LR_REGNUM)); | |
cce74817 | 562 | write_register (SP_REGNUM, fp + fi->extra_info->size); |
c906108c SS |
563 | target_store_registers (-1); |
564 | flush_cached_frames (); | |
565 | } | |
566 | ||
c5aa993b | 567 | static int |
fba45db2 | 568 | check_prologue (unsigned short op) |
c906108c SS |
569 | { |
570 | /* st rn, @-sp */ | |
571 | if ((op & 0x7E1F) == 0x6C1F) | |
572 | return 1; | |
573 | ||
574 | /* st2w rn, @-sp */ | |
575 | if ((op & 0x7E3F) == 0x6E1F) | |
576 | return 1; | |
577 | ||
578 | /* subi sp, n */ | |
579 | if ((op & 0x7FE1) == 0x01E1) | |
580 | return 1; | |
581 | ||
582 | /* mv r11, sp */ | |
583 | if (op == 0x417E) | |
584 | return 1; | |
585 | ||
586 | /* nop */ | |
587 | if (op == 0x5E00) | |
588 | return 1; | |
589 | ||
590 | /* st rn, @sp */ | |
591 | if ((op & 0x7E1F) == 0x681E) | |
592 | return 1; | |
593 | ||
594 | /* st2w rn, @sp */ | |
c5aa993b JM |
595 | if ((op & 0x7E3F) == 0x3A1E) |
596 | return 1; | |
c906108c SS |
597 | |
598 | return 0; | |
599 | } | |
600 | ||
f5e1cf12 | 601 | static CORE_ADDR |
fba45db2 | 602 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
603 | { |
604 | unsigned long op; | |
605 | unsigned short op1, op2; | |
606 | CORE_ADDR func_addr, func_end; | |
607 | struct symtab_and_line sal; | |
608 | ||
609 | /* If we have line debugging information, then the end of the */ | |
610 | /* prologue should the first assembly instruction of the first source line */ | |
611 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
612 | { | |
613 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 614 | if (sal.end && sal.end < func_end) |
c906108c SS |
615 | return sal.end; |
616 | } | |
c5aa993b JM |
617 | |
618 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
619 | return pc; /* Can't access it -- assume no prologue. */ |
620 | ||
621 | while (1) | |
622 | { | |
c5aa993b | 623 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
624 | if ((op & 0xC0000000) == 0xC0000000) |
625 | { | |
626 | /* long instruction */ | |
c5aa993b JM |
627 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
628 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
629 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
630 | break; |
631 | } | |
632 | else | |
633 | { | |
634 | /* short instructions */ | |
635 | if ((op & 0xC0000000) == 0x80000000) | |
636 | { | |
637 | op2 = (op & 0x3FFF8000) >> 15; | |
638 | op1 = op & 0x7FFF; | |
c5aa993b JM |
639 | } |
640 | else | |
c906108c SS |
641 | { |
642 | op1 = (op & 0x3FFF8000) >> 15; | |
643 | op2 = op & 0x7FFF; | |
644 | } | |
c5aa993b | 645 | if (check_prologue (op1)) |
c906108c | 646 | { |
c5aa993b | 647 | if (!check_prologue (op2)) |
c906108c SS |
648 | { |
649 | /* if the previous opcode was really part of the prologue */ | |
650 | /* and not just a NOP, then we want to break after both instructions */ | |
651 | if (op1 != 0x5E00) | |
652 | pc += 4; | |
653 | break; | |
654 | } | |
655 | } | |
656 | else | |
657 | break; | |
658 | } | |
659 | pc += 4; | |
660 | } | |
661 | return pc; | |
662 | } | |
663 | ||
664 | /* Given a GDB frame, determine the address of the calling function's frame. | |
665 | This will be used to create a new GDB frame struct, and then | |
666 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
c5aa993b | 667 | */ |
c906108c | 668 | |
f5e1cf12 | 669 | static CORE_ADDR |
fba45db2 | 670 | d10v_frame_chain (struct frame_info *fi) |
c906108c | 671 | { |
cce74817 | 672 | d10v_frame_init_saved_regs (fi); |
c906108c | 673 | |
cce74817 JM |
674 | if (fi->extra_info->return_pc == IMEM_START |
675 | || inside_entry_file (fi->extra_info->return_pc)) | |
c5aa993b | 676 | return (CORE_ADDR) 0; |
c906108c | 677 | |
cce74817 | 678 | if (!fi->saved_regs[FP_REGNUM]) |
c906108c | 679 | { |
cce74817 JM |
680 | if (!fi->saved_regs[SP_REGNUM] |
681 | || fi->saved_regs[SP_REGNUM] == STACK_START) | |
c5aa993b JM |
682 | return (CORE_ADDR) 0; |
683 | ||
cce74817 | 684 | return fi->saved_regs[SP_REGNUM]; |
c906108c SS |
685 | } |
686 | ||
c5aa993b JM |
687 | if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
688 | REGISTER_RAW_SIZE (FP_REGNUM))) | |
689 | return (CORE_ADDR) 0; | |
c906108c | 690 | |
7b570125 | 691 | return d10v_make_daddr (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], |
c5aa993b JM |
692 | REGISTER_RAW_SIZE (FP_REGNUM))); |
693 | } | |
c906108c SS |
694 | |
695 | static int next_addr, uses_frame; | |
696 | ||
c5aa993b | 697 | static int |
fba45db2 | 698 | prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr) |
c906108c SS |
699 | { |
700 | int n; | |
701 | ||
702 | /* st rn, @-sp */ | |
703 | if ((op & 0x7E1F) == 0x6C1F) | |
704 | { | |
705 | n = (op & 0x1E0) >> 5; | |
706 | next_addr -= 2; | |
cce74817 | 707 | fi->saved_regs[n] = next_addr; |
c906108c SS |
708 | return 1; |
709 | } | |
710 | ||
711 | /* st2w rn, @-sp */ | |
712 | else if ((op & 0x7E3F) == 0x6E1F) | |
713 | { | |
714 | n = (op & 0x1E0) >> 5; | |
715 | next_addr -= 4; | |
cce74817 | 716 | fi->saved_regs[n] = next_addr; |
c5aa993b | 717 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
718 | return 1; |
719 | } | |
720 | ||
721 | /* subi sp, n */ | |
722 | if ((op & 0x7FE1) == 0x01E1) | |
723 | { | |
724 | n = (op & 0x1E) >> 1; | |
725 | if (n == 0) | |
726 | n = 16; | |
727 | next_addr -= n; | |
728 | return 1; | |
729 | } | |
730 | ||
731 | /* mv r11, sp */ | |
732 | if (op == 0x417E) | |
733 | { | |
734 | uses_frame = 1; | |
735 | return 1; | |
736 | } | |
737 | ||
738 | /* nop */ | |
739 | if (op == 0x5E00) | |
740 | return 1; | |
741 | ||
742 | /* st rn, @sp */ | |
743 | if ((op & 0x7E1F) == 0x681E) | |
744 | { | |
745 | n = (op & 0x1E0) >> 5; | |
cce74817 | 746 | fi->saved_regs[n] = next_addr; |
c906108c SS |
747 | return 1; |
748 | } | |
749 | ||
750 | /* st2w rn, @sp */ | |
751 | if ((op & 0x7E3F) == 0x3A1E) | |
752 | { | |
753 | n = (op & 0x1E0) >> 5; | |
cce74817 | 754 | fi->saved_regs[n] = next_addr; |
c5aa993b | 755 | fi->saved_regs[n + 1] = next_addr + 2; |
c906108c SS |
756 | return 1; |
757 | } | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
cce74817 JM |
762 | /* Put here the code to store, into fi->saved_regs, the addresses of |
763 | the saved registers of frame described by FRAME_INFO. This | |
764 | includes special registers such as pc and fp saved in special ways | |
765 | in the stack frame. sp is even more special: the address we return | |
766 | for it IS the sp for the next frame. */ | |
767 | ||
f5e1cf12 | 768 | static void |
fba45db2 | 769 | d10v_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
770 | { |
771 | CORE_ADDR fp, pc; | |
772 | unsigned long op; | |
773 | unsigned short op1, op2; | |
774 | int i; | |
775 | ||
776 | fp = fi->frame; | |
cce74817 | 777 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
778 | next_addr = 0; |
779 | ||
780 | pc = get_pc_function_start (fi->pc); | |
781 | ||
782 | uses_frame = 0; | |
783 | while (1) | |
784 | { | |
c5aa993b | 785 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
786 | if ((op & 0xC0000000) == 0xC0000000) |
787 | { | |
788 | /* long instruction */ | |
789 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
790 | { | |
791 | /* add3 sp,sp,n */ | |
792 | short n = op & 0xFFFF; | |
793 | next_addr += n; | |
794 | } | |
795 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
796 | { | |
797 | /* st rn, @(offset,sp) */ | |
798 | short offset = op & 0xFFFF; | |
799 | short n = (op >> 20) & 0xF; | |
cce74817 | 800 | fi->saved_regs[n] = next_addr + offset; |
c906108c SS |
801 | } |
802 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
803 | { | |
804 | /* st2w rn, @(offset,sp) */ | |
805 | short offset = op & 0xFFFF; | |
806 | short n = (op >> 20) & 0xF; | |
cce74817 | 807 | fi->saved_regs[n] = next_addr + offset; |
c5aa993b | 808 | fi->saved_regs[n + 1] = next_addr + offset + 2; |
c906108c SS |
809 | } |
810 | else | |
811 | break; | |
812 | } | |
813 | else | |
814 | { | |
815 | /* short instructions */ | |
816 | if ((op & 0xC0000000) == 0x80000000) | |
817 | { | |
818 | op2 = (op & 0x3FFF8000) >> 15; | |
819 | op1 = op & 0x7FFF; | |
c5aa993b JM |
820 | } |
821 | else | |
c906108c SS |
822 | { |
823 | op1 = (op & 0x3FFF8000) >> 15; | |
824 | op2 = op & 0x7FFF; | |
825 | } | |
c5aa993b | 826 | if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc)) |
c906108c SS |
827 | break; |
828 | } | |
829 | pc += 4; | |
830 | } | |
c5aa993b | 831 | |
cce74817 | 832 | fi->extra_info->size = -next_addr; |
c906108c SS |
833 | |
834 | if (!(fp & 0xffff)) | |
7b570125 | 835 | fp = d10v_make_daddr (read_register (SP_REGNUM)); |
c906108c | 836 | |
c5aa993b | 837 | for (i = 0; i < NUM_REGS - 1; i++) |
cce74817 | 838 | if (fi->saved_regs[i]) |
c906108c | 839 | { |
c5aa993b | 840 | fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]); |
c906108c SS |
841 | } |
842 | ||
cce74817 | 843 | if (fi->saved_regs[LR_REGNUM]) |
c906108c | 844 | { |
cce74817 | 845 | CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM)); |
7b570125 | 846 | fi->extra_info->return_pc = d10v_make_iaddr (return_pc); |
c906108c SS |
847 | } |
848 | else | |
849 | { | |
7b570125 | 850 | fi->extra_info->return_pc = d10v_make_iaddr (read_register (LR_REGNUM)); |
c906108c | 851 | } |
c5aa993b | 852 | |
c906108c | 853 | /* th SP is not normally (ever?) saved, but check anyway */ |
cce74817 | 854 | if (!fi->saved_regs[SP_REGNUM]) |
c906108c SS |
855 | { |
856 | /* if the FP was saved, that means the current FP is valid, */ | |
857 | /* otherwise, it isn't being used, so we use the SP instead */ | |
858 | if (uses_frame) | |
c5aa993b | 859 | fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size; |
c906108c SS |
860 | else |
861 | { | |
cce74817 JM |
862 | fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size; |
863 | fi->extra_info->frameless = 1; | |
864 | fi->saved_regs[FP_REGNUM] = 0; | |
c906108c SS |
865 | } |
866 | } | |
867 | } | |
868 | ||
f5e1cf12 | 869 | static void |
fba45db2 | 870 | d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 871 | { |
cce74817 JM |
872 | fi->extra_info = (struct frame_extra_info *) |
873 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
874 | frame_saved_regs_zalloc (fi); | |
875 | ||
876 | fi->extra_info->frameless = 0; | |
877 | fi->extra_info->size = 0; | |
878 | fi->extra_info->return_pc = 0; | |
c906108c SS |
879 | |
880 | /* The call dummy doesn't save any registers on the stack, so we can | |
881 | return now. */ | |
882 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
883 | { | |
884 | return; | |
885 | } | |
886 | else | |
887 | { | |
cce74817 | 888 | d10v_frame_init_saved_regs (fi); |
c906108c SS |
889 | } |
890 | } | |
891 | ||
892 | static void | |
fba45db2 | 893 | show_regs (char *args, int from_tty) |
c906108c SS |
894 | { |
895 | int a; | |
d4f3574e SS |
896 | printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
897 | (long) read_register (PC_REGNUM), | |
7b570125 | 898 | (long) d10v_make_iaddr (read_register (PC_REGNUM)), |
d4f3574e SS |
899 | (long) read_register (PSW_REGNUM), |
900 | (long) read_register (24), | |
901 | (long) read_register (25), | |
902 | (long) read_register (23)); | |
903 | printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
904 | (long) read_register (0), | |
905 | (long) read_register (1), | |
906 | (long) read_register (2), | |
907 | (long) read_register (3), | |
908 | (long) read_register (4), | |
909 | (long) read_register (5), | |
910 | (long) read_register (6), | |
911 | (long) read_register (7)); | |
912 | printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
913 | (long) read_register (8), | |
914 | (long) read_register (9), | |
915 | (long) read_register (10), | |
916 | (long) read_register (11), | |
917 | (long) read_register (12), | |
918 | (long) read_register (13), | |
919 | (long) read_register (14), | |
920 | (long) read_register (15)); | |
4ce44c66 JM |
921 | for (a = 0; a < NR_IMAP_REGS; a++) |
922 | { | |
923 | if (a > 0) | |
924 | printf_filtered (" "); | |
925 | printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); | |
926 | } | |
927 | if (NR_DMAP_REGS == 1) | |
928 | printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); | |
929 | else | |
930 | { | |
931 | for (a = 0; a < NR_DMAP_REGS; a++) | |
932 | { | |
933 | printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); | |
934 | } | |
935 | printf_filtered ("\n"); | |
936 | } | |
937 | printf_filtered ("A0-A%d", NR_A_REGS - 1); | |
938 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) | |
c906108c SS |
939 | { |
940 | char num[MAX_REGISTER_RAW_SIZE]; | |
941 | int i; | |
942 | printf_filtered (" "); | |
c5aa993b | 943 | read_register_gen (a, (char *) &num); |
c906108c SS |
944 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) |
945 | { | |
946 | printf_filtered ("%02x", (num[i] & 0xff)); | |
947 | } | |
948 | } | |
949 | printf_filtered ("\n"); | |
950 | } | |
951 | ||
f5e1cf12 | 952 | static CORE_ADDR |
39f77062 | 953 | d10v_read_pc (ptid_t ptid) |
c906108c | 954 | { |
39f77062 | 955 | ptid_t save_ptid; |
c906108c SS |
956 | CORE_ADDR pc; |
957 | CORE_ADDR retval; | |
958 | ||
39f77062 KB |
959 | save_ptid = inferior_ptid; |
960 | inferior_ptid = ptid; | |
c906108c | 961 | pc = (int) read_register (PC_REGNUM); |
39f77062 | 962 | inferior_ptid = save_ptid; |
7b570125 | 963 | retval = d10v_make_iaddr (pc); |
c906108c SS |
964 | return retval; |
965 | } | |
966 | ||
f5e1cf12 | 967 | static void |
39f77062 | 968 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 969 | { |
39f77062 | 970 | ptid_t save_ptid; |
c906108c | 971 | |
39f77062 KB |
972 | save_ptid = inferior_ptid; |
973 | inferior_ptid = ptid; | |
7b570125 | 974 | write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 975 | inferior_ptid = save_ptid; |
c906108c SS |
976 | } |
977 | ||
f5e1cf12 | 978 | static CORE_ADDR |
fba45db2 | 979 | d10v_read_sp (void) |
c906108c | 980 | { |
7b570125 | 981 | return (d10v_make_daddr (read_register (SP_REGNUM))); |
c906108c SS |
982 | } |
983 | ||
f5e1cf12 | 984 | static void |
fba45db2 | 985 | d10v_write_sp (CORE_ADDR val) |
c906108c | 986 | { |
7b570125 | 987 | write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val)); |
c906108c SS |
988 | } |
989 | ||
f5e1cf12 | 990 | static void |
fba45db2 | 991 | d10v_write_fp (CORE_ADDR val) |
c906108c | 992 | { |
7b570125 | 993 | write_register (FP_REGNUM, d10v_convert_daddr_to_raw (val)); |
c906108c SS |
994 | } |
995 | ||
f5e1cf12 | 996 | static CORE_ADDR |
fba45db2 | 997 | d10v_read_fp (void) |
c906108c | 998 | { |
7b570125 | 999 | return (d10v_make_daddr (read_register (FP_REGNUM))); |
c906108c SS |
1000 | } |
1001 | ||
1002 | /* Function: push_return_address (pc) | |
1003 | Set up the return address for the inferior function call. | |
1004 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
c5aa993b | 1005 | |
f5e1cf12 | 1006 | static CORE_ADDR |
fba45db2 | 1007 | d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 1008 | { |
7b570125 | 1009 | write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ())); |
c906108c SS |
1010 | return sp; |
1011 | } | |
c5aa993b | 1012 | |
c906108c | 1013 | |
7a292a7a SS |
1014 | /* When arguments must be pushed onto the stack, they go on in reverse |
1015 | order. The below implements a FILO (stack) to do this. */ | |
1016 | ||
1017 | struct stack_item | |
1018 | { | |
1019 | int len; | |
1020 | struct stack_item *prev; | |
1021 | void *data; | |
1022 | }; | |
1023 | ||
a14ed312 KB |
1024 | static struct stack_item *push_stack_item (struct stack_item *prev, |
1025 | void *contents, int len); | |
7a292a7a | 1026 | static struct stack_item * |
fba45db2 | 1027 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
1028 | { |
1029 | struct stack_item *si; | |
1030 | si = xmalloc (sizeof (struct stack_item)); | |
1031 | si->data = xmalloc (len); | |
1032 | si->len = len; | |
1033 | si->prev = prev; | |
1034 | memcpy (si->data, contents, len); | |
1035 | return si; | |
1036 | } | |
1037 | ||
a14ed312 | 1038 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 1039 | static struct stack_item * |
fba45db2 | 1040 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
1041 | { |
1042 | struct stack_item *dead = si; | |
1043 | si = si->prev; | |
b8c9b27d KB |
1044 | xfree (dead->data); |
1045 | xfree (dead); | |
7a292a7a SS |
1046 | return si; |
1047 | } | |
1048 | ||
1049 | ||
f5e1cf12 | 1050 | static CORE_ADDR |
ea7c478f | 1051 | d10v_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
fba45db2 | 1052 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
1053 | { |
1054 | int i; | |
1055 | int regnum = ARG1_REGNUM; | |
7a292a7a | 1056 | struct stack_item *si = NULL; |
c5aa993b | 1057 | |
c906108c SS |
1058 | /* Fill in registers and arg lists */ |
1059 | for (i = 0; i < nargs; i++) | |
1060 | { | |
ea7c478f | 1061 | struct value *arg = args[i]; |
c906108c SS |
1062 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
1063 | char *contents = VALUE_CONTENTS (arg); | |
1064 | int len = TYPE_LENGTH (type); | |
1065 | /* printf ("push: type=%d len=%d\n", type->code, len); */ | |
c906108c SS |
1066 | { |
1067 | int aligned_regnum = (regnum + 1) & ~1; | |
1068 | if (len <= 2 && regnum <= ARGN_REGNUM) | |
1069 | /* fits in a single register, do not align */ | |
1070 | { | |
1071 | long val = extract_unsigned_integer (contents, len); | |
1072 | write_register (regnum++, val); | |
1073 | } | |
1074 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1075 | /* value fits in remaining registers, store keeping left | |
c5aa993b | 1076 | aligned */ |
c906108c SS |
1077 | { |
1078 | int b; | |
1079 | regnum = aligned_regnum; | |
1080 | for (b = 0; b < (len & ~1); b += 2) | |
1081 | { | |
1082 | long val = extract_unsigned_integer (&contents[b], 2); | |
1083 | write_register (regnum++, val); | |
1084 | } | |
1085 | if (b < len) | |
1086 | { | |
1087 | long val = extract_unsigned_integer (&contents[b], 1); | |
1088 | write_register (regnum++, (val << 8)); | |
1089 | } | |
1090 | } | |
1091 | else | |
1092 | { | |
7a292a7a | 1093 | /* arg will go onto stack */ |
c5aa993b | 1094 | regnum = ARGN_REGNUM + 1; |
7a292a7a | 1095 | si = push_stack_item (si, contents, len); |
c906108c SS |
1096 | } |
1097 | } | |
1098 | } | |
7a292a7a SS |
1099 | |
1100 | while (si) | |
1101 | { | |
1102 | sp = (sp - si->len) & ~1; | |
1103 | write_memory (sp, si->data, si->len); | |
1104 | si = pop_stack_item (si); | |
1105 | } | |
c5aa993b | 1106 | |
c906108c SS |
1107 | return sp; |
1108 | } | |
1109 | ||
1110 | ||
1111 | /* Given a return value in `regbuf' with a type `valtype', | |
1112 | extract and copy its value into `valbuf'. */ | |
1113 | ||
f5e1cf12 | 1114 | static void |
72623009 KB |
1115 | d10v_extract_return_value (struct type *type, char regbuf[REGISTER_BYTES], |
1116 | char *valbuf) | |
c906108c SS |
1117 | { |
1118 | int len; | |
1119 | /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */ | |
c906108c SS |
1120 | { |
1121 | len = TYPE_LENGTH (type); | |
1122 | if (len == 1) | |
1123 | { | |
1124 | unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); | |
1125 | store_unsigned_integer (valbuf, 1, c); | |
1126 | } | |
1127 | else if ((len & 1) == 0) | |
1128 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len); | |
1129 | else | |
1130 | { | |
1131 | /* For return values of odd size, the first byte is in the | |
c5aa993b JM |
1132 | least significant part of the first register. The |
1133 | remaining bytes in remaining registers. Interestingly, | |
1134 | when such values are passed in, the last byte is in the | |
1135 | most significant byte of that same register - wierd. */ | |
c906108c SS |
1136 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); |
1137 | } | |
1138 | } | |
1139 | } | |
1140 | ||
c2c6d25f JM |
1141 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1142 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1143 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1144 | (segmentation fault). Since the simulator knows all about how the | |
1145 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1146 | |
4ce44c66 | 1147 | static void |
c2c6d25f JM |
1148 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1149 | CORE_ADDR *targ_addr, int *targ_len) | |
1150 | { | |
4ce44c66 JM |
1151 | long out_addr; |
1152 | long out_len; | |
1153 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1154 | &out_addr, | |
1155 | d10v_dmap_register, | |
1156 | d10v_imap_register); | |
1157 | *targ_addr = out_addr; | |
1158 | *targ_len = out_len; | |
c2c6d25f JM |
1159 | } |
1160 | ||
4ce44c66 | 1161 | |
c906108c SS |
1162 | /* The following code implements access to, and display of, the D10V's |
1163 | instruction trace buffer. The buffer consists of 64K or more | |
1164 | 4-byte words of data, of which each words includes an 8-bit count, | |
1165 | an 8-bit segment number, and a 16-bit instruction address. | |
1166 | ||
1167 | In theory, the trace buffer is continuously capturing instruction | |
1168 | data that the CPU presents on its "debug bus", but in practice, the | |
1169 | ROMified GDB stub only enables tracing when it continues or steps | |
1170 | the program, and stops tracing when the program stops; so it | |
1171 | actually works for GDB to read the buffer counter out of memory and | |
1172 | then read each trace word. The counter records where the tracing | |
1173 | stops, but there is no record of where it started, so we remember | |
1174 | the PC when we resumed and then search backwards in the trace | |
1175 | buffer for a word that includes that address. This is not perfect, | |
1176 | because you will miss trace data if the resumption PC is the target | |
1177 | of a branch. (The value of the buffer counter is semi-random, any | |
1178 | trace data from a previous program stop is gone.) */ | |
1179 | ||
1180 | /* The address of the last word recorded in the trace buffer. */ | |
1181 | ||
1182 | #define DBBC_ADDR (0xd80000) | |
1183 | ||
1184 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1185 | ||
1186 | #define TRACE_BUFFER_BASE (0xf40000) | |
1187 | ||
a14ed312 | 1188 | static void trace_command (char *, int); |
c906108c | 1189 | |
a14ed312 | 1190 | static void untrace_command (char *, int); |
c906108c | 1191 | |
a14ed312 | 1192 | static void trace_info (char *, int); |
c906108c | 1193 | |
a14ed312 | 1194 | static void tdisassemble_command (char *, int); |
c906108c | 1195 | |
a14ed312 | 1196 | static void display_trace (int, int); |
c906108c SS |
1197 | |
1198 | /* True when instruction traces are being collected. */ | |
1199 | ||
1200 | static int tracing; | |
1201 | ||
1202 | /* Remembered PC. */ | |
1203 | ||
1204 | static CORE_ADDR last_pc; | |
1205 | ||
1206 | /* True when trace output should be displayed whenever program stops. */ | |
1207 | ||
1208 | static int trace_display; | |
1209 | ||
1210 | /* True when trace listing should include source lines. */ | |
1211 | ||
1212 | static int default_trace_show_source = 1; | |
1213 | ||
c5aa993b JM |
1214 | struct trace_buffer |
1215 | { | |
1216 | int size; | |
1217 | short *counts; | |
1218 | CORE_ADDR *addrs; | |
1219 | } | |
1220 | trace_data; | |
c906108c SS |
1221 | |
1222 | static void | |
fba45db2 | 1223 | trace_command (char *args, int from_tty) |
c906108c SS |
1224 | { |
1225 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1226 | trace_data.size = 0; | |
1227 | if (trace_data.counts == NULL) | |
c5aa993b | 1228 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1229 | if (trace_data.addrs == NULL) |
c5aa993b | 1230 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1231 | |
1232 | tracing = 1; | |
1233 | ||
1234 | printf_filtered ("Tracing is now on.\n"); | |
1235 | } | |
1236 | ||
1237 | static void | |
fba45db2 | 1238 | untrace_command (char *args, int from_tty) |
c906108c SS |
1239 | { |
1240 | tracing = 0; | |
1241 | ||
1242 | printf_filtered ("Tracing is now off.\n"); | |
1243 | } | |
1244 | ||
1245 | static void | |
fba45db2 | 1246 | trace_info (char *args, int from_tty) |
c906108c SS |
1247 | { |
1248 | int i; | |
1249 | ||
1250 | if (trace_data.size) | |
1251 | { | |
1252 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1253 | ||
1254 | for (i = 0; i < trace_data.size; ++i) | |
1255 | { | |
d4f3574e SS |
1256 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1257 | i, | |
1258 | trace_data.counts[i], | |
c906108c | 1259 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1260 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1261 | } |
1262 | } | |
1263 | else | |
1264 | printf_filtered ("No entries in trace buffer.\n"); | |
1265 | ||
1266 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1267 | } | |
1268 | ||
1269 | /* Print the instruction at address MEMADDR in debugged memory, | |
1270 | on STREAM. Returns length of the instruction, in bytes. */ | |
1271 | ||
1272 | static int | |
fba45db2 | 1273 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1274 | { |
1275 | /* If there's no disassembler, something is very wrong. */ | |
1276 | if (tm_print_insn == NULL) | |
8e65ff28 AC |
1277 | internal_error (__FILE__, __LINE__, |
1278 | "print_insn: no disassembler"); | |
c906108c SS |
1279 | |
1280 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1281 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; | |
1282 | else | |
1283 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
2bf0cb65 | 1284 | return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info); |
c906108c SS |
1285 | } |
1286 | ||
392a587b | 1287 | static void |
fba45db2 | 1288 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1289 | { |
1290 | if (!tracing) | |
1291 | return; | |
1292 | ||
1293 | last_pc = read_register (PC_REGNUM); | |
1294 | } | |
1295 | ||
1296 | /* Collect trace data from the target board and format it into a form | |
1297 | more useful for display. */ | |
1298 | ||
392a587b | 1299 | static void |
fba45db2 | 1300 | d10v_eva_get_trace_data (void) |
c906108c SS |
1301 | { |
1302 | int count, i, j, oldsize; | |
1303 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1304 | unsigned int last_trace, trace_word, next_word; | |
1305 | unsigned int *tmpspace; | |
1306 | ||
1307 | if (!tracing) | |
1308 | return; | |
1309 | ||
c5aa993b | 1310 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1311 | |
1312 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1313 | ||
1314 | /* Collect buffer contents from the target, stopping when we reach | |
1315 | the word recorded when execution resumed. */ | |
1316 | ||
1317 | count = 0; | |
1318 | while (last_trace > 0) | |
1319 | { | |
1320 | QUIT; | |
1321 | trace_word = | |
1322 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1323 | trace_addr = trace_word & 0xffff; | |
1324 | last_trace -= 4; | |
1325 | /* Ignore an apparently nonsensical entry. */ | |
1326 | if (trace_addr == 0xffd5) | |
1327 | continue; | |
1328 | tmpspace[count++] = trace_word; | |
1329 | if (trace_addr == last_pc) | |
1330 | break; | |
1331 | if (count > 65535) | |
1332 | break; | |
1333 | } | |
1334 | ||
1335 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1336 | include the last instruction executed and transforming the address | |
1337 | into something that GDB likes. */ | |
1338 | ||
1339 | for (i = 0; i < count; ++i) | |
1340 | { | |
1341 | trace_word = tmpspace[i]; | |
1342 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1343 | trace_addr = trace_word & 0xffff; | |
1344 | next_cnt = (next_word >> 24) & 0xff; | |
1345 | j = trace_data.size + count - i - 1; | |
1346 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1347 | trace_data.counts[j] = next_cnt + 1; | |
1348 | } | |
1349 | ||
1350 | oldsize = trace_data.size; | |
1351 | trace_data.size += count; | |
1352 | ||
b8c9b27d | 1353 | xfree (tmpspace); |
c906108c SS |
1354 | |
1355 | if (trace_display) | |
1356 | display_trace (oldsize, trace_data.size); | |
1357 | } | |
1358 | ||
1359 | static void | |
fba45db2 | 1360 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1361 | { |
1362 | int i, count; | |
1363 | CORE_ADDR low, high; | |
1364 | char *space_index; | |
1365 | ||
1366 | if (!arg) | |
1367 | { | |
1368 | low = 0; | |
1369 | high = trace_data.size; | |
1370 | } | |
1371 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1372 | { | |
1373 | low = parse_and_eval_address (arg); | |
1374 | high = low + 5; | |
1375 | } | |
1376 | else | |
1377 | { | |
1378 | /* Two arguments. */ | |
1379 | *space_index = '\0'; | |
1380 | low = parse_and_eval_address (arg); | |
1381 | high = parse_and_eval_address (space_index + 1); | |
1382 | if (high < low) | |
1383 | high = low; | |
1384 | } | |
1385 | ||
d4f3574e | 1386 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1387 | |
1388 | display_trace (low, high); | |
1389 | ||
1390 | printf_filtered ("End of trace dump.\n"); | |
1391 | gdb_flush (gdb_stdout); | |
1392 | } | |
1393 | ||
1394 | static void | |
fba45db2 | 1395 | display_trace (int low, int high) |
c906108c SS |
1396 | { |
1397 | int i, count, trace_show_source, first, suppress; | |
1398 | CORE_ADDR next_address; | |
1399 | ||
1400 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1401 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1402 | { |
1403 | trace_show_source = 0; | |
1404 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1405 | printf_filtered ("Trace will not display any source.\n"); | |
1406 | } | |
1407 | ||
1408 | first = 1; | |
1409 | suppress = 0; | |
1410 | for (i = low; i < high; ++i) | |
1411 | { | |
1412 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1413 | count = trace_data.counts[i]; |
c906108c SS |
1414 | while (count-- > 0) |
1415 | { | |
1416 | QUIT; | |
1417 | if (trace_show_source) | |
1418 | { | |
1419 | struct symtab_and_line sal, sal_prev; | |
1420 | ||
1421 | sal_prev = find_pc_line (next_address - 4, 0); | |
1422 | sal = find_pc_line (next_address, 0); | |
1423 | ||
1424 | if (sal.symtab) | |
1425 | { | |
1426 | if (first || sal.line != sal_prev.line) | |
1427 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1428 | suppress = 0; | |
1429 | } | |
1430 | else | |
1431 | { | |
1432 | if (!suppress) | |
1433 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1434 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1435 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1436 | suppress = 1; |
1437 | } | |
1438 | } | |
1439 | first = 0; | |
1440 | print_address (next_address, gdb_stdout); | |
1441 | printf_filtered (":"); | |
1442 | printf_filtered ("\t"); | |
1443 | wrap_here (" "); | |
1444 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1445 | printf_filtered ("\n"); | |
1446 | gdb_flush (gdb_stdout); | |
1447 | } | |
1448 | } | |
1449 | } | |
1450 | ||
ac9a91a7 | 1451 | |
0f71a2f6 | 1452 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1453 | |
0f71a2f6 | 1454 | static struct gdbarch * |
fba45db2 | 1455 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1456 | { |
c5aa993b JM |
1457 | static LONGEST d10v_call_dummy_words[] = |
1458 | {0}; | |
0f71a2f6 | 1459 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1460 | int d10v_num_regs; |
1461 | struct gdbarch_tdep *tdep; | |
1462 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1463 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1464 | |
4ce44c66 JM |
1465 | /* Find a candidate among the list of pre-declared architectures. */ |
1466 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1467 | if (arches != NULL) |
1468 | return arches->gdbarch; | |
4ce44c66 JM |
1469 | |
1470 | /* None found, create a new architecture from the information | |
1471 | provided. */ | |
1472 | tdep = XMALLOC (struct gdbarch_tdep); | |
1473 | gdbarch = gdbarch_alloc (&info, tdep); | |
1474 | ||
1475 | switch (info.bfd_arch_info->mach) | |
1476 | { | |
1477 | case bfd_mach_d10v_ts2: | |
1478 | d10v_num_regs = 37; | |
1479 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1480 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1481 | tdep->a0_regnum = TS2_A0_REGNUM; |
1482 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1483 | tdep->dmap_register = d10v_ts2_dmap_register; |
1484 | tdep->imap_register = d10v_ts2_imap_register; | |
1485 | break; | |
1486 | default: | |
1487 | case bfd_mach_d10v_ts3: | |
1488 | d10v_num_regs = 42; | |
1489 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1490 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1491 | tdep->a0_regnum = TS3_A0_REGNUM; |
1492 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1493 | tdep->dmap_register = d10v_ts3_dmap_register; |
1494 | tdep->imap_register = d10v_ts3_imap_register; | |
1495 | break; | |
1496 | } | |
0f71a2f6 JM |
1497 | |
1498 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1499 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1500 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
1501 | set_gdbarch_write_fp (gdbarch, d10v_write_fp); | |
1502 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); | |
1503 | set_gdbarch_write_sp (gdbarch, d10v_write_sp); | |
1504 | ||
1505 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1506 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1507 | set_gdbarch_fp_regnum (gdbarch, 11); | |
1508 | set_gdbarch_pc_regnum (gdbarch, 18); | |
1509 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1510 | set_gdbarch_register_size (gdbarch, 2); | |
1511 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1512 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1513 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
1514 | set_gdbarch_max_register_raw_size (gdbarch, 8); | |
1515 | set_gdbarch_register_virtual_size (gdbarch, d10v_register_virtual_size); | |
1516 | set_gdbarch_max_register_virtual_size (gdbarch, 8); | |
1517 | set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); | |
1518 | ||
75af7f68 JB |
1519 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1520 | set_gdbarch_addr_bit (gdbarch, 32); | |
1521 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1522 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1523 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1524 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1525 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1526 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1527 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e AC |
1528 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1529 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1530 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1531 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1532 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1533 | switch (info.byte_order) |
1534 | { | |
1535 | case BIG_ENDIAN: | |
1536 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
1537 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1538 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1539 | break; | |
1540 | case LITTLE_ENDIAN: | |
1541 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
1542 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1543 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1544 | break; | |
1545 | default: | |
8e65ff28 AC |
1546 | internal_error (__FILE__, __LINE__, |
1547 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1548 | } |
0f71a2f6 JM |
1549 | |
1550 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
1551 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
1552 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
1553 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
1554 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
1555 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
1556 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
1557 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
1558 | set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); | |
1559 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); | |
1560 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
1561 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
1562 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
1563 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
1564 | ||
0f71a2f6 JM |
1565 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); |
1566 | set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); | |
1567 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
1568 | set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); | |
1569 | ||
0f71a2f6 JM |
1570 | set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); |
1571 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); | |
1572 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
1573 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); | |
1574 | ||
1575 | set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs); | |
1576 | set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info); | |
1577 | ||
1578 | set_gdbarch_pop_frame (gdbarch, d10v_pop_frame); | |
1579 | ||
1580 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); | |
1581 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1582 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1583 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1584 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1585 | ||
1586 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1587 | ||
1588 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1589 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
1590 | set_gdbarch_frame_chain (gdbarch, d10v_frame_chain); | |
1591 | set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid); | |
1592 | set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc); | |
c347ee3e MS |
1593 | set_gdbarch_frame_args_address (gdbarch, default_frame_address); |
1594 | set_gdbarch_frame_locals_address (gdbarch, default_frame_address); | |
0f71a2f6 JM |
1595 | set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); |
1596 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
23964bcd | 1597 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1598 | |
7c7651b2 | 1599 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
0a49d05e | 1600 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); |
7c7651b2 | 1601 | |
0f71a2f6 JM |
1602 | return gdbarch; |
1603 | } | |
1604 | ||
1605 | ||
507f3c78 KB |
1606 | extern void (*target_resume_hook) (void); |
1607 | extern void (*target_wait_loop_hook) (void); | |
c906108c SS |
1608 | |
1609 | void | |
fba45db2 | 1610 | _initialize_d10v_tdep (void) |
c906108c | 1611 | { |
0f71a2f6 JM |
1612 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1613 | ||
c906108c SS |
1614 | tm_print_insn = print_insn_d10v; |
1615 | ||
1616 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1617 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1618 | ||
1619 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
1620 | ||
cff3e48b | 1621 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1622 | "Enable tracing of instruction execution."); |
1623 | ||
cff3e48b | 1624 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1625 | "Disable tracing of instruction execution."); |
1626 | ||
cff3e48b | 1627 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1628 | "Disassemble the trace buffer.\n\ |
1629 | Two optional arguments specify a range of trace buffer entries\n\ | |
1630 | as reported by info trace (NOT addresses!)."); | |
1631 | ||
cff3e48b | 1632 | add_info ("itrace", trace_info, |
c906108c SS |
1633 | "Display info about the trace data buffer."); |
1634 | ||
cff3e48b | 1635 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1636 | var_integer, (char *) &trace_display, |
1637 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1638 | &showlist); |
cff3e48b | 1639 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1640 | var_integer, (char *) &default_trace_show_source, |
1641 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1642 | &showlist); |
1643 | ||
c5aa993b | 1644 | } |