Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
349c5d5f | 2 | |
51603483 | 3 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software |
349c5d5f | 4 | Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
7f6104a9 | 27 | #include "frame-unwind.h" |
c906108c SS |
28 | #include "symtab.h" |
29 | #include "gdbtypes.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "gdb_string.h" | |
33 | #include "value.h" | |
34 | #include "inferior.h" | |
c5aa993b | 35 | #include "dis-asm.h" |
c906108c SS |
36 | #include "symfile.h" |
37 | #include "objfiles.h" | |
104c1213 | 38 | #include "language.h" |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
c906108c | 41 | |
f0d4cc9e | 42 | #include "floatformat.h" |
b91b96f4 | 43 | #include "gdb/sim-d10v.h" |
8238d0bf | 44 | #include "sim-regno.h" |
4ce44c66 | 45 | |
fa1fd571 AC |
46 | #include "gdb_assert.h" |
47 | ||
cce74817 | 48 | struct frame_extra_info |
c5aa993b JM |
49 | { |
50 | CORE_ADDR return_pc; | |
51 | int frameless; | |
52 | int size; | |
53 | }; | |
cce74817 | 54 | |
4ce44c66 JM |
55 | struct gdbarch_tdep |
56 | { | |
57 | int a0_regnum; | |
58 | int nr_dmap_regs; | |
59 | unsigned long (*dmap_register) (int nr); | |
60 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
61 | }; |
62 | ||
63 | /* These are the addresses the D10V-EVA board maps data and | |
64 | instruction memory to. */ | |
cce74817 | 65 | |
78eac43e MS |
66 | enum memspace { |
67 | DMEM_START = 0x2000000, | |
68 | IMEM_START = 0x1000000, | |
69 | STACK_START = 0x200bffe | |
70 | }; | |
cce74817 | 71 | |
4ce44c66 JM |
72 | /* d10v register names. */ |
73 | ||
74 | enum | |
75 | { | |
76 | R0_REGNUM = 0, | |
78eac43e MS |
77 | R3_REGNUM = 3, |
78 | _FP_REGNUM = 11, | |
4ce44c66 | 79 | LR_REGNUM = 13, |
78eac43e | 80 | _SP_REGNUM = 15, |
4ce44c66 | 81 | PSW_REGNUM = 16, |
78eac43e | 82 | _PC_REGNUM = 18, |
4ce44c66 | 83 | NR_IMAP_REGS = 2, |
78eac43e MS |
84 | NR_A_REGS = 2, |
85 | TS2_NUM_REGS = 37, | |
86 | TS3_NUM_REGS = 42, | |
87 | /* d10v calling convention. */ | |
88 | ARG1_REGNUM = R0_REGNUM, | |
89 | ARGN_REGNUM = R3_REGNUM, | |
90 | RET1_REGNUM = R0_REGNUM, | |
4ce44c66 | 91 | }; |
78eac43e | 92 | |
4ce44c66 JM |
93 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) |
94 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
95 | ||
392a587b JM |
96 | /* Local functions */ |
97 | ||
a14ed312 | 98 | extern void _initialize_d10v_tdep (void); |
392a587b | 99 | |
095a4c96 EZ |
100 | static CORE_ADDR d10v_read_sp (void); |
101 | ||
102 | static CORE_ADDR d10v_read_fp (void); | |
103 | ||
a14ed312 | 104 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 105 | |
a14ed312 | 106 | static void d10v_eva_get_trace_data (void); |
c906108c | 107 | |
23964bcd | 108 | static CORE_ADDR |
489137c0 AC |
109 | d10v_stack_align (CORE_ADDR len) |
110 | { | |
111 | return (len + 1) & ~1; | |
112 | } | |
c906108c SS |
113 | |
114 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
115 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
116 | and TYPE is the type (which is known to be struct, union or array). | |
117 | ||
118 | The d10v returns anything less than 8 bytes in size in | |
119 | registers. */ | |
120 | ||
f5e1cf12 | 121 | static int |
fba45db2 | 122 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 123 | { |
02da6206 JSC |
124 | long alignment; |
125 | int i; | |
126 | /* The d10v only passes a struct in a register when that structure | |
127 | has an alignment that matches the size of a register. */ | |
128 | /* If the structure doesn't fit in 4 registers, put it on the | |
129 | stack. */ | |
130 | if (TYPE_LENGTH (type) > 8) | |
131 | return 1; | |
132 | /* If the struct contains only one field, don't put it on the stack | |
133 | - gcc can fit it in one or more registers. */ | |
134 | if (TYPE_NFIELDS (type) == 1) | |
135 | return 0; | |
136 | alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); | |
137 | for (i = 1; i < TYPE_NFIELDS (type); i++) | |
138 | { | |
139 | /* If the alignment changes, just assume it goes on the | |
140 | stack. */ | |
141 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) | |
142 | return 1; | |
143 | } | |
144 | /* If the alignment is suitable for the d10v's 16 bit registers, | |
145 | don't put it on the stack. */ | |
146 | if (alignment == 2 || alignment == 4) | |
147 | return 0; | |
148 | return 1; | |
c906108c SS |
149 | } |
150 | ||
151 | ||
f4f9705a | 152 | static const unsigned char * |
fba45db2 | 153 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 154 | { |
c5aa993b JM |
155 | static unsigned char breakpoint[] = |
156 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
157 | *lenptr = sizeof (breakpoint); |
158 | return breakpoint; | |
159 | } | |
160 | ||
4ce44c66 JM |
161 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
162 | when the reg_nr isn't valid. */ | |
163 | ||
164 | enum ts2_regnums | |
165 | { | |
166 | TS2_IMAP0_REGNUM = 32, | |
167 | TS2_DMAP_REGNUM = 34, | |
168 | TS2_NR_DMAP_REGS = 1, | |
169 | TS2_A0_REGNUM = 35 | |
170 | }; | |
171 | ||
fa88f677 | 172 | static const char * |
4ce44c66 | 173 | d10v_ts2_register_name (int reg_nr) |
392a587b | 174 | { |
c5aa993b JM |
175 | static char *register_names[] = |
176 | { | |
177 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
178 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
179 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
180 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
181 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
182 | }; |
183 | if (reg_nr < 0) | |
184 | return NULL; | |
185 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
186 | return NULL; | |
c5aa993b | 187 | return register_names[reg_nr]; |
392a587b JM |
188 | } |
189 | ||
4ce44c66 JM |
190 | enum ts3_regnums |
191 | { | |
192 | TS3_IMAP0_REGNUM = 36, | |
193 | TS3_DMAP0_REGNUM = 38, | |
194 | TS3_NR_DMAP_REGS = 4, | |
195 | TS3_A0_REGNUM = 32 | |
196 | }; | |
197 | ||
fa88f677 | 198 | static const char * |
4ce44c66 JM |
199 | d10v_ts3_register_name (int reg_nr) |
200 | { | |
201 | static char *register_names[] = | |
202 | { | |
203 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
204 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
205 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
206 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
207 | "a0", "a1", | |
208 | "spi", "spu", | |
209 | "imap0", "imap1", | |
210 | "dmap0", "dmap1", "dmap2", "dmap3" | |
211 | }; | |
212 | if (reg_nr < 0) | |
213 | return NULL; | |
214 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
215 | return NULL; | |
216 | return register_names[reg_nr]; | |
217 | } | |
218 | ||
bf93dfed JB |
219 | /* Access the DMAP/IMAP registers in a target independent way. |
220 | ||
221 | Divide the D10V's 64k data space into four 16k segments: | |
222 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
223 | 0xc000 -- 0xffff. | |
224 | ||
225 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
226 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
227 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
228 | unified memory or instruction memory, under the control of the | |
229 | single DMAP register. | |
230 | ||
231 | On the TS3, there are four DMAP registers, each of which controls | |
232 | one of the segments. */ | |
4ce44c66 JM |
233 | |
234 | static unsigned long | |
235 | d10v_ts2_dmap_register (int reg_nr) | |
236 | { | |
237 | switch (reg_nr) | |
238 | { | |
239 | case 0: | |
240 | case 1: | |
241 | return 0x2000; | |
242 | case 2: | |
243 | return read_register (TS2_DMAP_REGNUM); | |
244 | default: | |
245 | return 0; | |
246 | } | |
247 | } | |
248 | ||
249 | static unsigned long | |
250 | d10v_ts3_dmap_register (int reg_nr) | |
251 | { | |
252 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
253 | } | |
254 | ||
255 | static unsigned long | |
256 | d10v_dmap_register (int reg_nr) | |
257 | { | |
258 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
259 | } | |
260 | ||
261 | static unsigned long | |
262 | d10v_ts2_imap_register (int reg_nr) | |
263 | { | |
264 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
265 | } | |
266 | ||
267 | static unsigned long | |
268 | d10v_ts3_imap_register (int reg_nr) | |
269 | { | |
270 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
271 | } | |
272 | ||
273 | static unsigned long | |
274 | d10v_imap_register (int reg_nr) | |
275 | { | |
276 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
277 | } | |
278 | ||
279 | /* MAP GDB's internal register numbering (determined by the layout fo | |
280 | the REGISTER_BYTE array) onto the simulator's register | |
281 | numbering. */ | |
282 | ||
283 | static int | |
284 | d10v_ts2_register_sim_regno (int nr) | |
285 | { | |
8238d0bf AC |
286 | if (legacy_register_sim_regno (nr) < 0) |
287 | return legacy_register_sim_regno (nr); | |
4ce44c66 JM |
288 | if (nr >= TS2_IMAP0_REGNUM |
289 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
290 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
291 | if (nr == TS2_DMAP_REGNUM) | |
292 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
293 | if (nr >= TS2_A0_REGNUM | |
294 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
295 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
296 | return nr; | |
297 | } | |
298 | ||
299 | static int | |
300 | d10v_ts3_register_sim_regno (int nr) | |
301 | { | |
8238d0bf AC |
302 | if (legacy_register_sim_regno (nr) < 0) |
303 | return legacy_register_sim_regno (nr); | |
4ce44c66 JM |
304 | if (nr >= TS3_IMAP0_REGNUM |
305 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
306 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
307 | if (nr >= TS3_DMAP0_REGNUM | |
308 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
309 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
310 | if (nr >= TS3_A0_REGNUM | |
311 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
312 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
313 | return nr; | |
314 | } | |
315 | ||
392a587b JM |
316 | /* Index within `registers' of the first byte of the space for |
317 | register REG_NR. */ | |
318 | ||
f5e1cf12 | 319 | static int |
fba45db2 | 320 | d10v_register_byte (int reg_nr) |
392a587b | 321 | { |
4ce44c66 | 322 | if (reg_nr < A0_REGNUM) |
392a587b | 323 | return (reg_nr * 2); |
4ce44c66 JM |
324 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
325 | return (A0_REGNUM * 2 | |
326 | + (reg_nr - A0_REGNUM) * 8); | |
327 | else | |
328 | return (A0_REGNUM * 2 | |
329 | + NR_A_REGS * 8 | |
330 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
331 | } |
332 | ||
333 | /* Number of bytes of storage in the actual machine representation for | |
334 | register REG_NR. */ | |
335 | ||
f5e1cf12 | 336 | static int |
fba45db2 | 337 | d10v_register_raw_size (int reg_nr) |
392a587b | 338 | { |
4ce44c66 JM |
339 | if (reg_nr < A0_REGNUM) |
340 | return 2; | |
341 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
342 | return 8; |
343 | else | |
344 | return 2; | |
345 | } | |
346 | ||
392a587b JM |
347 | /* Return the GDB type object for the "standard" data type |
348 | of data in register N. */ | |
349 | ||
f5e1cf12 | 350 | static struct type * |
fba45db2 | 351 | d10v_register_virtual_type (int reg_nr) |
392a587b | 352 | { |
75af7f68 JB |
353 | if (reg_nr == PC_REGNUM) |
354 | return builtin_type_void_func_ptr; | |
095a4c96 EZ |
355 | if (reg_nr == _SP_REGNUM || reg_nr == _FP_REGNUM) |
356 | return builtin_type_void_data_ptr; | |
75af7f68 | 357 | else if (reg_nr >= A0_REGNUM |
4ce44c66 JM |
358 | && reg_nr < (A0_REGNUM + NR_A_REGS)) |
359 | return builtin_type_int64; | |
392a587b | 360 | else |
4ce44c66 | 361 | return builtin_type_int16; |
392a587b JM |
362 | } |
363 | ||
f5e1cf12 | 364 | static int |
fba45db2 | 365 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
366 | { |
367 | return (((x) & 0x3000000) == DMEM_START); | |
368 | } | |
369 | ||
f5e1cf12 | 370 | static int |
fba45db2 | 371 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
372 | { |
373 | return (((x) & 0x3000000) == IMEM_START); | |
374 | } | |
375 | ||
169a7369 MS |
376 | static CORE_ADDR |
377 | d10v_make_daddr (CORE_ADDR x) | |
378 | { | |
379 | return ((x) | DMEM_START); | |
380 | } | |
381 | ||
382 | static CORE_ADDR | |
383 | d10v_make_iaddr (CORE_ADDR x) | |
384 | { | |
385 | if (d10v_iaddr_p (x)) | |
386 | return x; /* Idempotency -- x is already in the IMEM space. */ | |
387 | else | |
388 | return (((x) << 2) | IMEM_START); | |
389 | } | |
392a587b | 390 | |
f5e1cf12 | 391 | static CORE_ADDR |
fba45db2 | 392 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
393 | { |
394 | return (((x) >> 2) & 0xffff); | |
395 | } | |
396 | ||
f5e1cf12 | 397 | static CORE_ADDR |
fba45db2 | 398 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
399 | { |
400 | return ((x) & 0xffff); | |
401 | } | |
402 | ||
75af7f68 JB |
403 | static void |
404 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
405 | { | |
406 | /* Is it a code address? */ | |
407 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
408 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
409 | { | |
75af7f68 JB |
410 | store_unsigned_integer (buf, TYPE_LENGTH (type), |
411 | d10v_convert_iaddr_to_raw (addr)); | |
412 | } | |
413 | else | |
414 | { | |
415 | /* Strip off any upper segment bits. */ | |
416 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
417 | d10v_convert_daddr_to_raw (addr)); | |
418 | } | |
419 | } | |
420 | ||
421 | static CORE_ADDR | |
66140c26 | 422 | d10v_pointer_to_address (struct type *type, const void *buf) |
75af7f68 JB |
423 | { |
424 | CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type)); | |
425 | ||
426 | /* Is it a code address? */ | |
427 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
74a9bb82 FF |
428 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
429 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
75af7f68 JB |
430 | return d10v_make_iaddr (addr); |
431 | else | |
432 | return d10v_make_daddr (addr); | |
433 | } | |
434 | ||
095a4c96 EZ |
435 | /* Don't do anything if we have an integer, this way users can type 'x |
436 | <addr>' w/o having gdb outsmart them. The internal gdb conversions | |
437 | to the correct space are taken care of in the pointer_to_address | |
438 | function. If we don't do this, 'x $fp' wouldn't work. */ | |
fc0c74b1 AC |
439 | static CORE_ADDR |
440 | d10v_integer_to_address (struct type *type, void *buf) | |
441 | { | |
442 | LONGEST val; | |
443 | val = unpack_long (type, buf); | |
095a4c96 | 444 | return val; |
fc0c74b1 | 445 | } |
75af7f68 | 446 | |
392a587b JM |
447 | /* Store the address of the place in which to copy the structure the |
448 | subroutine will return. This is called from call_function. | |
449 | ||
450 | We store structs through a pointer passed in the first Argument | |
451 | register. */ | |
452 | ||
f5e1cf12 | 453 | static void |
fba45db2 | 454 | d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
392a587b JM |
455 | { |
456 | write_register (ARG1_REGNUM, (addr)); | |
457 | } | |
458 | ||
459 | /* Write into appropriate registers a function return value | |
460 | of type TYPE, given in virtual format. | |
461 | ||
462 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
463 | ||
f5e1cf12 | 464 | static void |
fa1fd571 AC |
465 | d10v_store_return_value (struct type *type, struct regcache *regcache, |
466 | const void *valbuf) | |
392a587b | 467 | { |
fa1fd571 AC |
468 | /* Only char return values need to be shifted right within the first |
469 | regnum. */ | |
3d79a47c MS |
470 | if (TYPE_LENGTH (type) == 1 |
471 | && TYPE_CODE (type) == TYPE_CODE_INT) | |
472 | { | |
fa1fd571 AC |
473 | bfd_byte tmp[2]; |
474 | tmp[1] = *(bfd_byte *)valbuf; | |
475 | regcache_cooked_write (regcache, RET1_REGNUM, tmp); | |
3d79a47c MS |
476 | } |
477 | else | |
fa1fd571 AC |
478 | { |
479 | int reg; | |
480 | /* A structure is never more than 8 bytes long. See | |
481 | use_struct_convention(). */ | |
482 | gdb_assert (TYPE_LENGTH (type) <= 8); | |
483 | /* Write out most registers, stop loop before trying to write | |
484 | out any dangling byte at the end of the buffer. */ | |
485 | for (reg = 0; (reg * 2) + 1 < TYPE_LENGTH (type); reg++) | |
486 | { | |
487 | regcache_cooked_write (regcache, RET1_REGNUM + reg, | |
488 | (bfd_byte *) valbuf + reg * 2); | |
489 | } | |
490 | /* Write out any dangling byte at the end of the buffer. */ | |
491 | if ((reg * 2) + 1 == TYPE_LENGTH (type)) | |
492 | regcache_cooked_write_part (regcache, reg, 0, 1, | |
493 | (bfd_byte *) valbuf + reg * 2); | |
494 | } | |
392a587b JM |
495 | } |
496 | ||
497 | /* Extract from an array REGBUF containing the (raw) register state | |
498 | the address in which a function should return its structure value, | |
499 | as a CORE_ADDR (or an expression that can be used as one). */ | |
500 | ||
f5e1cf12 | 501 | static CORE_ADDR |
fa1fd571 | 502 | d10v_extract_struct_value_address (struct regcache *regcache) |
392a587b | 503 | { |
fa1fd571 AC |
504 | ULONGEST addr; |
505 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr); | |
506 | return (addr | DMEM_START); | |
392a587b JM |
507 | } |
508 | ||
392a587b JM |
509 | /* Immediately after a function call, return the saved pc. We can't |
510 | use frame->return_pc beause that is determined by reading R13 off | |
511 | the stack and that may not be written yet. */ | |
512 | ||
f5e1cf12 | 513 | static CORE_ADDR |
fba45db2 | 514 | d10v_saved_pc_after_call (struct frame_info *frame) |
392a587b | 515 | { |
c5aa993b | 516 | return ((read_register (LR_REGNUM) << 2) |
392a587b JM |
517 | | IMEM_START); |
518 | } | |
519 | ||
c5aa993b | 520 | static int |
fba45db2 | 521 | check_prologue (unsigned short op) |
c906108c SS |
522 | { |
523 | /* st rn, @-sp */ | |
524 | if ((op & 0x7E1F) == 0x6C1F) | |
525 | return 1; | |
526 | ||
527 | /* st2w rn, @-sp */ | |
528 | if ((op & 0x7E3F) == 0x6E1F) | |
529 | return 1; | |
530 | ||
531 | /* subi sp, n */ | |
532 | if ((op & 0x7FE1) == 0x01E1) | |
533 | return 1; | |
534 | ||
535 | /* mv r11, sp */ | |
536 | if (op == 0x417E) | |
537 | return 1; | |
538 | ||
539 | /* nop */ | |
540 | if (op == 0x5E00) | |
541 | return 1; | |
542 | ||
543 | /* st rn, @sp */ | |
544 | if ((op & 0x7E1F) == 0x681E) | |
545 | return 1; | |
546 | ||
547 | /* st2w rn, @sp */ | |
c5aa993b JM |
548 | if ((op & 0x7E3F) == 0x3A1E) |
549 | return 1; | |
c906108c SS |
550 | |
551 | return 0; | |
552 | } | |
553 | ||
f5e1cf12 | 554 | static CORE_ADDR |
fba45db2 | 555 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
556 | { |
557 | unsigned long op; | |
558 | unsigned short op1, op2; | |
559 | CORE_ADDR func_addr, func_end; | |
560 | struct symtab_and_line sal; | |
561 | ||
562 | /* If we have line debugging information, then the end of the */ | |
563 | /* prologue should the first assembly instruction of the first source line */ | |
564 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
565 | { | |
566 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 567 | if (sal.end && sal.end < func_end) |
c906108c SS |
568 | return sal.end; |
569 | } | |
c5aa993b JM |
570 | |
571 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
572 | return pc; /* Can't access it -- assume no prologue. */ |
573 | ||
574 | while (1) | |
575 | { | |
c5aa993b | 576 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
577 | if ((op & 0xC0000000) == 0xC0000000) |
578 | { | |
579 | /* long instruction */ | |
c5aa993b JM |
580 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
581 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
582 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
583 | break; |
584 | } | |
585 | else | |
586 | { | |
587 | /* short instructions */ | |
588 | if ((op & 0xC0000000) == 0x80000000) | |
589 | { | |
590 | op2 = (op & 0x3FFF8000) >> 15; | |
591 | op1 = op & 0x7FFF; | |
c5aa993b JM |
592 | } |
593 | else | |
c906108c SS |
594 | { |
595 | op1 = (op & 0x3FFF8000) >> 15; | |
596 | op2 = op & 0x7FFF; | |
597 | } | |
c5aa993b | 598 | if (check_prologue (op1)) |
c906108c | 599 | { |
c5aa993b | 600 | if (!check_prologue (op2)) |
c906108c SS |
601 | { |
602 | /* if the previous opcode was really part of the prologue */ | |
603 | /* and not just a NOP, then we want to break after both instructions */ | |
604 | if (op1 != 0x5E00) | |
605 | pc += 4; | |
606 | break; | |
607 | } | |
608 | } | |
609 | else | |
610 | break; | |
611 | } | |
612 | pc += 4; | |
613 | } | |
614 | return pc; | |
615 | } | |
616 | ||
7f6104a9 | 617 | struct d10v_unwind_cache |
c906108c | 618 | { |
7f6104a9 AC |
619 | CORE_ADDR return_pc; |
620 | int frameless; | |
621 | int size; | |
622 | CORE_ADDR *saved_regs; | |
623 | CORE_ADDR next_addr; | |
624 | int uses_frame; | |
625 | void **regs; | |
626 | }; | |
c906108c | 627 | |
c5aa993b | 628 | static int |
7f6104a9 AC |
629 | prologue_find_regs (struct d10v_unwind_cache *info, unsigned short op, |
630 | CORE_ADDR addr) | |
c906108c SS |
631 | { |
632 | int n; | |
633 | ||
634 | /* st rn, @-sp */ | |
635 | if ((op & 0x7E1F) == 0x6C1F) | |
636 | { | |
637 | n = (op & 0x1E0) >> 5; | |
7f6104a9 AC |
638 | info->next_addr -= 2; |
639 | info->saved_regs[n] = info->next_addr; | |
c906108c SS |
640 | return 1; |
641 | } | |
642 | ||
643 | /* st2w rn, @-sp */ | |
644 | else if ((op & 0x7E3F) == 0x6E1F) | |
645 | { | |
646 | n = (op & 0x1E0) >> 5; | |
7f6104a9 AC |
647 | info->next_addr -= 4; |
648 | info->saved_regs[n] = info->next_addr; | |
649 | info->saved_regs[n + 1] = info->next_addr + 2; | |
c906108c SS |
650 | return 1; |
651 | } | |
652 | ||
653 | /* subi sp, n */ | |
654 | if ((op & 0x7FE1) == 0x01E1) | |
655 | { | |
656 | n = (op & 0x1E) >> 1; | |
657 | if (n == 0) | |
658 | n = 16; | |
7f6104a9 | 659 | info->next_addr -= n; |
c906108c SS |
660 | return 1; |
661 | } | |
662 | ||
663 | /* mv r11, sp */ | |
664 | if (op == 0x417E) | |
665 | { | |
7f6104a9 | 666 | info->uses_frame = 1; |
c906108c SS |
667 | return 1; |
668 | } | |
669 | ||
670 | /* nop */ | |
671 | if (op == 0x5E00) | |
672 | return 1; | |
673 | ||
674 | /* st rn, @sp */ | |
675 | if ((op & 0x7E1F) == 0x681E) | |
676 | { | |
677 | n = (op & 0x1E0) >> 5; | |
7f6104a9 | 678 | info->saved_regs[n] = info->next_addr; |
c906108c SS |
679 | return 1; |
680 | } | |
681 | ||
682 | /* st2w rn, @sp */ | |
683 | if ((op & 0x7E3F) == 0x3A1E) | |
684 | { | |
685 | n = (op & 0x1E0) >> 5; | |
7f6104a9 AC |
686 | info->saved_regs[n] = info->next_addr; |
687 | info->saved_regs[n + 1] = info->next_addr + 2; | |
c906108c SS |
688 | return 1; |
689 | } | |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
cce74817 JM |
694 | /* Put here the code to store, into fi->saved_regs, the addresses of |
695 | the saved registers of frame described by FRAME_INFO. This | |
696 | includes special registers such as pc and fp saved in special ways | |
697 | in the stack frame. sp is even more special: the address we return | |
698 | for it IS the sp for the next frame. */ | |
699 | ||
7f6104a9 AC |
700 | struct d10v_unwind_cache * |
701 | d10v_frame_unwind_cache (struct frame_info *fi, | |
702 | void **cache) | |
c906108c SS |
703 | { |
704 | CORE_ADDR fp, pc; | |
705 | unsigned long op; | |
706 | unsigned short op1, op2; | |
707 | int i; | |
7f6104a9 AC |
708 | struct d10v_unwind_cache *info; |
709 | ||
710 | if ((*cache)) | |
711 | return (*cache); | |
712 | ||
713 | info = FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache); | |
714 | (*cache) = info; | |
715 | info->saved_regs = frame_obstack_zalloc (SIZEOF_FRAME_SAVED_REGS); | |
716 | ||
717 | info->frameless = 0; | |
718 | info->size = 0; | |
719 | info->return_pc = 0; | |
c906108c | 720 | |
1e2330ba | 721 | fp = get_frame_base (fi); |
7f6104a9 | 722 | info->next_addr = 0; |
c906108c | 723 | |
50abf9e5 | 724 | pc = get_pc_function_start (get_frame_pc (fi)); |
c906108c | 725 | |
7f6104a9 | 726 | info->uses_frame = 0; |
c906108c SS |
727 | while (1) |
728 | { | |
c5aa993b | 729 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
730 | if ((op & 0xC0000000) == 0xC0000000) |
731 | { | |
732 | /* long instruction */ | |
733 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
734 | { | |
735 | /* add3 sp,sp,n */ | |
736 | short n = op & 0xFFFF; | |
7f6104a9 | 737 | info->next_addr += n; |
c906108c SS |
738 | } |
739 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
740 | { | |
741 | /* st rn, @(offset,sp) */ | |
742 | short offset = op & 0xFFFF; | |
743 | short n = (op >> 20) & 0xF; | |
7f6104a9 | 744 | info->saved_regs[n] = info->next_addr + offset; |
c906108c SS |
745 | } |
746 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
747 | { | |
748 | /* st2w rn, @(offset,sp) */ | |
749 | short offset = op & 0xFFFF; | |
750 | short n = (op >> 20) & 0xF; | |
7f6104a9 AC |
751 | info->saved_regs[n] = info->next_addr + offset; |
752 | info->saved_regs[n + 1] = info->next_addr + offset + 2; | |
c906108c SS |
753 | } |
754 | else | |
755 | break; | |
756 | } | |
757 | else | |
758 | { | |
759 | /* short instructions */ | |
760 | if ((op & 0xC0000000) == 0x80000000) | |
761 | { | |
762 | op2 = (op & 0x3FFF8000) >> 15; | |
763 | op1 = op & 0x7FFF; | |
c5aa993b JM |
764 | } |
765 | else | |
c906108c SS |
766 | { |
767 | op1 = (op & 0x3FFF8000) >> 15; | |
768 | op2 = op & 0x7FFF; | |
769 | } | |
7f6104a9 AC |
770 | if (!prologue_find_regs (info, op1, pc) |
771 | || !prologue_find_regs (info, op2, pc)) | |
c906108c SS |
772 | break; |
773 | } | |
774 | pc += 4; | |
775 | } | |
c5aa993b | 776 | |
7f6104a9 | 777 | info->size = -info->next_addr; |
c906108c SS |
778 | |
779 | if (!(fp & 0xffff)) | |
095a4c96 | 780 | fp = d10v_read_sp (); |
c906108c | 781 | |
c5aa993b | 782 | for (i = 0; i < NUM_REGS - 1; i++) |
7f6104a9 | 783 | if (info->saved_regs[i]) |
c906108c | 784 | { |
7f6104a9 | 785 | info->saved_regs[i] = fp - (info->next_addr - info->saved_regs[i]); |
c906108c SS |
786 | } |
787 | ||
7f6104a9 | 788 | if (info->saved_regs[LR_REGNUM]) |
c906108c | 789 | { |
78eac43e | 790 | CORE_ADDR return_pc |
7f6104a9 | 791 | = read_memory_unsigned_integer (info->saved_regs[LR_REGNUM], |
78eac43e | 792 | REGISTER_RAW_SIZE (LR_REGNUM)); |
7f6104a9 | 793 | info->return_pc = d10v_make_iaddr (return_pc); |
c906108c SS |
794 | } |
795 | else | |
796 | { | |
7f6104a9 AC |
797 | ULONGEST return_pc; |
798 | frame_read_unsigned_register (fi, LR_REGNUM, &return_pc); | |
799 | info->return_pc = d10v_make_iaddr (return_pc); | |
c906108c | 800 | } |
c5aa993b | 801 | |
78eac43e | 802 | /* The SP is not normally (ever?) saved, but check anyway */ |
7f6104a9 | 803 | if (!info->saved_regs[SP_REGNUM]) |
c906108c SS |
804 | { |
805 | /* if the FP was saved, that means the current FP is valid, */ | |
806 | /* otherwise, it isn't being used, so we use the SP instead */ | |
7f6104a9 AC |
807 | if (info->uses_frame) |
808 | info->saved_regs[SP_REGNUM] | |
809 | = d10v_read_fp () + info->size; | |
c906108c SS |
810 | else |
811 | { | |
7f6104a9 AC |
812 | info->saved_regs[SP_REGNUM] = fp + info->size; |
813 | info->frameless = 1; | |
814 | info->saved_regs[FP_REGNUM] = 0; | |
c906108c SS |
815 | } |
816 | } | |
c906108c | 817 | |
7f6104a9 | 818 | return info; |
c906108c SS |
819 | } |
820 | ||
821 | static void | |
fba45db2 | 822 | show_regs (char *args, int from_tty) |
c906108c SS |
823 | { |
824 | int a; | |
d4f3574e SS |
825 | printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
826 | (long) read_register (PC_REGNUM), | |
7b570125 | 827 | (long) d10v_make_iaddr (read_register (PC_REGNUM)), |
d4f3574e SS |
828 | (long) read_register (PSW_REGNUM), |
829 | (long) read_register (24), | |
830 | (long) read_register (25), | |
831 | (long) read_register (23)); | |
832 | printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
833 | (long) read_register (0), | |
834 | (long) read_register (1), | |
835 | (long) read_register (2), | |
836 | (long) read_register (3), | |
837 | (long) read_register (4), | |
838 | (long) read_register (5), | |
839 | (long) read_register (6), | |
840 | (long) read_register (7)); | |
841 | printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
842 | (long) read_register (8), | |
843 | (long) read_register (9), | |
844 | (long) read_register (10), | |
845 | (long) read_register (11), | |
846 | (long) read_register (12), | |
847 | (long) read_register (13), | |
848 | (long) read_register (14), | |
849 | (long) read_register (15)); | |
4ce44c66 JM |
850 | for (a = 0; a < NR_IMAP_REGS; a++) |
851 | { | |
852 | if (a > 0) | |
853 | printf_filtered (" "); | |
854 | printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); | |
855 | } | |
856 | if (NR_DMAP_REGS == 1) | |
857 | printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); | |
858 | else | |
859 | { | |
860 | for (a = 0; a < NR_DMAP_REGS; a++) | |
861 | { | |
862 | printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); | |
863 | } | |
864 | printf_filtered ("\n"); | |
865 | } | |
866 | printf_filtered ("A0-A%d", NR_A_REGS - 1); | |
6789195b AC |
867 | { |
868 | char *num = alloca (max_register_size (current_gdbarch)); | |
869 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) | |
870 | { | |
871 | int i; | |
872 | printf_filtered (" "); | |
873 | deprecated_read_register_gen (a, (char *) &num); | |
874 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) | |
875 | { | |
876 | printf_filtered ("%02x", (num[i] & 0xff)); | |
877 | } | |
878 | } | |
879 | } | |
c906108c SS |
880 | printf_filtered ("\n"); |
881 | } | |
882 | ||
f5e1cf12 | 883 | static CORE_ADDR |
39f77062 | 884 | d10v_read_pc (ptid_t ptid) |
c906108c | 885 | { |
39f77062 | 886 | ptid_t save_ptid; |
c906108c SS |
887 | CORE_ADDR pc; |
888 | CORE_ADDR retval; | |
889 | ||
39f77062 KB |
890 | save_ptid = inferior_ptid; |
891 | inferior_ptid = ptid; | |
c906108c | 892 | pc = (int) read_register (PC_REGNUM); |
39f77062 | 893 | inferior_ptid = save_ptid; |
7b570125 | 894 | retval = d10v_make_iaddr (pc); |
c906108c SS |
895 | return retval; |
896 | } | |
897 | ||
f5e1cf12 | 898 | static void |
39f77062 | 899 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 900 | { |
39f77062 | 901 | ptid_t save_ptid; |
c906108c | 902 | |
39f77062 KB |
903 | save_ptid = inferior_ptid; |
904 | inferior_ptid = ptid; | |
7b570125 | 905 | write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 906 | inferior_ptid = save_ptid; |
c906108c SS |
907 | } |
908 | ||
f5e1cf12 | 909 | static CORE_ADDR |
fba45db2 | 910 | d10v_read_sp (void) |
c906108c | 911 | { |
7b570125 | 912 | return (d10v_make_daddr (read_register (SP_REGNUM))); |
c906108c SS |
913 | } |
914 | ||
f5e1cf12 | 915 | static void |
fba45db2 | 916 | d10v_write_sp (CORE_ADDR val) |
c906108c | 917 | { |
7b570125 | 918 | write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val)); |
c906108c SS |
919 | } |
920 | ||
f5e1cf12 | 921 | static CORE_ADDR |
fba45db2 | 922 | d10v_read_fp (void) |
c906108c | 923 | { |
7b570125 | 924 | return (d10v_make_daddr (read_register (FP_REGNUM))); |
c906108c SS |
925 | } |
926 | ||
927 | /* Function: push_return_address (pc) | |
928 | Set up the return address for the inferior function call. | |
929 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
c5aa993b | 930 | |
f5e1cf12 | 931 | static CORE_ADDR |
fba45db2 | 932 | d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 933 | { |
7b570125 | 934 | write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ())); |
c906108c SS |
935 | return sp; |
936 | } | |
c5aa993b | 937 | |
c906108c | 938 | |
7a292a7a SS |
939 | /* When arguments must be pushed onto the stack, they go on in reverse |
940 | order. The below implements a FILO (stack) to do this. */ | |
941 | ||
942 | struct stack_item | |
943 | { | |
944 | int len; | |
945 | struct stack_item *prev; | |
946 | void *data; | |
947 | }; | |
948 | ||
a14ed312 KB |
949 | static struct stack_item *push_stack_item (struct stack_item *prev, |
950 | void *contents, int len); | |
7a292a7a | 951 | static struct stack_item * |
fba45db2 | 952 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
953 | { |
954 | struct stack_item *si; | |
955 | si = xmalloc (sizeof (struct stack_item)); | |
956 | si->data = xmalloc (len); | |
957 | si->len = len; | |
958 | si->prev = prev; | |
959 | memcpy (si->data, contents, len); | |
960 | return si; | |
961 | } | |
962 | ||
a14ed312 | 963 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 964 | static struct stack_item * |
fba45db2 | 965 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
966 | { |
967 | struct stack_item *dead = si; | |
968 | si = si->prev; | |
b8c9b27d KB |
969 | xfree (dead->data); |
970 | xfree (dead); | |
7a292a7a SS |
971 | return si; |
972 | } | |
973 | ||
974 | ||
f5e1cf12 | 975 | static CORE_ADDR |
ea7c478f | 976 | d10v_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
fba45db2 | 977 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
978 | { |
979 | int i; | |
980 | int regnum = ARG1_REGNUM; | |
7a292a7a | 981 | struct stack_item *si = NULL; |
7bd91a28 MS |
982 | long val; |
983 | ||
984 | /* If struct_return is true, then the struct return address will | |
985 | consume one argument-passing register. No need to actually | |
986 | write the value to the register -- that's done by | |
987 | d10v_store_struct_return(). */ | |
988 | ||
989 | if (struct_return) | |
990 | regnum++; | |
c5aa993b | 991 | |
c906108c SS |
992 | /* Fill in registers and arg lists */ |
993 | for (i = 0; i < nargs; i++) | |
994 | { | |
ea7c478f | 995 | struct value *arg = args[i]; |
c906108c SS |
996 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
997 | char *contents = VALUE_CONTENTS (arg); | |
998 | int len = TYPE_LENGTH (type); | |
7bd91a28 MS |
999 | int aligned_regnum = (regnum + 1) & ~1; |
1000 | ||
8b279e7a | 1001 | /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */ |
7bd91a28 MS |
1002 | if (len <= 2 && regnum <= ARGN_REGNUM) |
1003 | /* fits in a single register, do not align */ | |
1004 | { | |
1005 | val = extract_unsigned_integer (contents, len); | |
1006 | write_register (regnum++, val); | |
1007 | } | |
1008 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1009 | /* value fits in remaining registers, store keeping left | |
1010 | aligned */ | |
c906108c | 1011 | { |
7bd91a28 MS |
1012 | int b; |
1013 | regnum = aligned_regnum; | |
1014 | for (b = 0; b < (len & ~1); b += 2) | |
c906108c | 1015 | { |
7bd91a28 | 1016 | val = extract_unsigned_integer (&contents[b], 2); |
c906108c SS |
1017 | write_register (regnum++, val); |
1018 | } | |
7bd91a28 | 1019 | if (b < len) |
c906108c | 1020 | { |
7bd91a28 MS |
1021 | val = extract_unsigned_integer (&contents[b], 1); |
1022 | write_register (regnum++, (val << 8)); | |
c906108c SS |
1023 | } |
1024 | } | |
7bd91a28 MS |
1025 | else |
1026 | { | |
1027 | /* arg will go onto stack */ | |
1028 | regnum = ARGN_REGNUM + 1; | |
1029 | si = push_stack_item (si, contents, len); | |
1030 | } | |
c906108c | 1031 | } |
7a292a7a SS |
1032 | |
1033 | while (si) | |
1034 | { | |
1035 | sp = (sp - si->len) & ~1; | |
1036 | write_memory (sp, si->data, si->len); | |
1037 | si = pop_stack_item (si); | |
1038 | } | |
c5aa993b | 1039 | |
c906108c SS |
1040 | return sp; |
1041 | } | |
1042 | ||
1043 | ||
1044 | /* Given a return value in `regbuf' with a type `valtype', | |
1045 | extract and copy its value into `valbuf'. */ | |
1046 | ||
f5e1cf12 | 1047 | static void |
fa1fd571 AC |
1048 | d10v_extract_return_value (struct type *type, struct regcache *regcache, |
1049 | void *valbuf) | |
c906108c SS |
1050 | { |
1051 | int len; | |
3d79a47c MS |
1052 | #if 0 |
1053 | printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type), | |
1054 | TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, | |
1055 | (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), | |
1056 | REGISTER_RAW_SIZE (RET1_REGNUM))); | |
1057 | #endif | |
fa1fd571 | 1058 | if (TYPE_LENGTH (type) == 1) |
c906108c | 1059 | { |
fa1fd571 AC |
1060 | ULONGEST c; |
1061 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &c); | |
3d79a47c MS |
1062 | store_unsigned_integer (valbuf, 1, c); |
1063 | } | |
3d79a47c MS |
1064 | else |
1065 | { | |
1066 | /* For return values of odd size, the first byte is in the | |
1067 | least significant part of the first register. The | |
fa1fd571 AC |
1068 | remaining bytes in remaining registers. Interestingly, when |
1069 | such values are passed in, the last byte is in the most | |
1070 | significant byte of that same register - wierd. */ | |
1071 | int reg = RET1_REGNUM; | |
1072 | int off = 0; | |
1073 | if (TYPE_LENGTH (type) & 1) | |
1074 | { | |
1075 | regcache_cooked_read_part (regcache, RET1_REGNUM, 1, 1, | |
1076 | (bfd_byte *)valbuf + off); | |
1077 | off++; | |
1078 | reg++; | |
1079 | } | |
1080 | /* Transfer the remaining registers. */ | |
1081 | for (; off < TYPE_LENGTH (type); reg++, off += 2) | |
1082 | { | |
1083 | regcache_cooked_read (regcache, RET1_REGNUM + reg, | |
1084 | (bfd_byte *) valbuf + off); | |
1085 | } | |
c906108c SS |
1086 | } |
1087 | } | |
1088 | ||
c2c6d25f JM |
1089 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1090 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1091 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1092 | (segmentation fault). Since the simulator knows all about how the | |
1093 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1094 | |
4ce44c66 | 1095 | static void |
c2c6d25f JM |
1096 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1097 | CORE_ADDR *targ_addr, int *targ_len) | |
1098 | { | |
4ce44c66 JM |
1099 | long out_addr; |
1100 | long out_len; | |
1101 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1102 | &out_addr, | |
1103 | d10v_dmap_register, | |
1104 | d10v_imap_register); | |
1105 | *targ_addr = out_addr; | |
1106 | *targ_len = out_len; | |
c2c6d25f JM |
1107 | } |
1108 | ||
4ce44c66 | 1109 | |
c906108c SS |
1110 | /* The following code implements access to, and display of, the D10V's |
1111 | instruction trace buffer. The buffer consists of 64K or more | |
1112 | 4-byte words of data, of which each words includes an 8-bit count, | |
1113 | an 8-bit segment number, and a 16-bit instruction address. | |
1114 | ||
1115 | In theory, the trace buffer is continuously capturing instruction | |
1116 | data that the CPU presents on its "debug bus", but in practice, the | |
1117 | ROMified GDB stub only enables tracing when it continues or steps | |
1118 | the program, and stops tracing when the program stops; so it | |
1119 | actually works for GDB to read the buffer counter out of memory and | |
1120 | then read each trace word. The counter records where the tracing | |
1121 | stops, but there is no record of where it started, so we remember | |
1122 | the PC when we resumed and then search backwards in the trace | |
1123 | buffer for a word that includes that address. This is not perfect, | |
1124 | because you will miss trace data if the resumption PC is the target | |
1125 | of a branch. (The value of the buffer counter is semi-random, any | |
1126 | trace data from a previous program stop is gone.) */ | |
1127 | ||
1128 | /* The address of the last word recorded in the trace buffer. */ | |
1129 | ||
1130 | #define DBBC_ADDR (0xd80000) | |
1131 | ||
1132 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1133 | ||
1134 | #define TRACE_BUFFER_BASE (0xf40000) | |
1135 | ||
a14ed312 | 1136 | static void trace_command (char *, int); |
c906108c | 1137 | |
a14ed312 | 1138 | static void untrace_command (char *, int); |
c906108c | 1139 | |
a14ed312 | 1140 | static void trace_info (char *, int); |
c906108c | 1141 | |
a14ed312 | 1142 | static void tdisassemble_command (char *, int); |
c906108c | 1143 | |
a14ed312 | 1144 | static void display_trace (int, int); |
c906108c SS |
1145 | |
1146 | /* True when instruction traces are being collected. */ | |
1147 | ||
1148 | static int tracing; | |
1149 | ||
1150 | /* Remembered PC. */ | |
1151 | ||
1152 | static CORE_ADDR last_pc; | |
1153 | ||
1154 | /* True when trace output should be displayed whenever program stops. */ | |
1155 | ||
1156 | static int trace_display; | |
1157 | ||
1158 | /* True when trace listing should include source lines. */ | |
1159 | ||
1160 | static int default_trace_show_source = 1; | |
1161 | ||
c5aa993b JM |
1162 | struct trace_buffer |
1163 | { | |
1164 | int size; | |
1165 | short *counts; | |
1166 | CORE_ADDR *addrs; | |
1167 | } | |
1168 | trace_data; | |
c906108c SS |
1169 | |
1170 | static void | |
fba45db2 | 1171 | trace_command (char *args, int from_tty) |
c906108c SS |
1172 | { |
1173 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1174 | trace_data.size = 0; | |
1175 | if (trace_data.counts == NULL) | |
c5aa993b | 1176 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1177 | if (trace_data.addrs == NULL) |
c5aa993b | 1178 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1179 | |
1180 | tracing = 1; | |
1181 | ||
1182 | printf_filtered ("Tracing is now on.\n"); | |
1183 | } | |
1184 | ||
1185 | static void | |
fba45db2 | 1186 | untrace_command (char *args, int from_tty) |
c906108c SS |
1187 | { |
1188 | tracing = 0; | |
1189 | ||
1190 | printf_filtered ("Tracing is now off.\n"); | |
1191 | } | |
1192 | ||
1193 | static void | |
fba45db2 | 1194 | trace_info (char *args, int from_tty) |
c906108c SS |
1195 | { |
1196 | int i; | |
1197 | ||
1198 | if (trace_data.size) | |
1199 | { | |
1200 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1201 | ||
1202 | for (i = 0; i < trace_data.size; ++i) | |
1203 | { | |
d4f3574e SS |
1204 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1205 | i, | |
1206 | trace_data.counts[i], | |
c906108c | 1207 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1208 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1209 | } |
1210 | } | |
1211 | else | |
1212 | printf_filtered ("No entries in trace buffer.\n"); | |
1213 | ||
1214 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1215 | } | |
1216 | ||
1217 | /* Print the instruction at address MEMADDR in debugged memory, | |
1218 | on STREAM. Returns length of the instruction, in bytes. */ | |
1219 | ||
1220 | static int | |
fba45db2 | 1221 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1222 | { |
1223 | /* If there's no disassembler, something is very wrong. */ | |
1224 | if (tm_print_insn == NULL) | |
8e65ff28 AC |
1225 | internal_error (__FILE__, __LINE__, |
1226 | "print_insn: no disassembler"); | |
c906108c | 1227 | |
d7449b42 | 1228 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1229 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; |
1230 | else | |
1231 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
2bf0cb65 | 1232 | return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info); |
c906108c SS |
1233 | } |
1234 | ||
392a587b | 1235 | static void |
fba45db2 | 1236 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1237 | { |
1238 | if (!tracing) | |
1239 | return; | |
1240 | ||
1241 | last_pc = read_register (PC_REGNUM); | |
1242 | } | |
1243 | ||
1244 | /* Collect trace data from the target board and format it into a form | |
1245 | more useful for display. */ | |
1246 | ||
392a587b | 1247 | static void |
fba45db2 | 1248 | d10v_eva_get_trace_data (void) |
c906108c SS |
1249 | { |
1250 | int count, i, j, oldsize; | |
1251 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1252 | unsigned int last_trace, trace_word, next_word; | |
1253 | unsigned int *tmpspace; | |
1254 | ||
1255 | if (!tracing) | |
1256 | return; | |
1257 | ||
c5aa993b | 1258 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1259 | |
1260 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1261 | ||
1262 | /* Collect buffer contents from the target, stopping when we reach | |
1263 | the word recorded when execution resumed. */ | |
1264 | ||
1265 | count = 0; | |
1266 | while (last_trace > 0) | |
1267 | { | |
1268 | QUIT; | |
1269 | trace_word = | |
1270 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1271 | trace_addr = trace_word & 0xffff; | |
1272 | last_trace -= 4; | |
1273 | /* Ignore an apparently nonsensical entry. */ | |
1274 | if (trace_addr == 0xffd5) | |
1275 | continue; | |
1276 | tmpspace[count++] = trace_word; | |
1277 | if (trace_addr == last_pc) | |
1278 | break; | |
1279 | if (count > 65535) | |
1280 | break; | |
1281 | } | |
1282 | ||
1283 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1284 | include the last instruction executed and transforming the address | |
1285 | into something that GDB likes. */ | |
1286 | ||
1287 | for (i = 0; i < count; ++i) | |
1288 | { | |
1289 | trace_word = tmpspace[i]; | |
1290 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1291 | trace_addr = trace_word & 0xffff; | |
1292 | next_cnt = (next_word >> 24) & 0xff; | |
1293 | j = trace_data.size + count - i - 1; | |
1294 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1295 | trace_data.counts[j] = next_cnt + 1; | |
1296 | } | |
1297 | ||
1298 | oldsize = trace_data.size; | |
1299 | trace_data.size += count; | |
1300 | ||
b8c9b27d | 1301 | xfree (tmpspace); |
c906108c SS |
1302 | |
1303 | if (trace_display) | |
1304 | display_trace (oldsize, trace_data.size); | |
1305 | } | |
1306 | ||
1307 | static void | |
fba45db2 | 1308 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1309 | { |
1310 | int i, count; | |
1311 | CORE_ADDR low, high; | |
1312 | char *space_index; | |
1313 | ||
1314 | if (!arg) | |
1315 | { | |
1316 | low = 0; | |
1317 | high = trace_data.size; | |
1318 | } | |
1319 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1320 | { | |
1321 | low = parse_and_eval_address (arg); | |
1322 | high = low + 5; | |
1323 | } | |
1324 | else | |
1325 | { | |
1326 | /* Two arguments. */ | |
1327 | *space_index = '\0'; | |
1328 | low = parse_and_eval_address (arg); | |
1329 | high = parse_and_eval_address (space_index + 1); | |
1330 | if (high < low) | |
1331 | high = low; | |
1332 | } | |
1333 | ||
d4f3574e | 1334 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1335 | |
1336 | display_trace (low, high); | |
1337 | ||
1338 | printf_filtered ("End of trace dump.\n"); | |
1339 | gdb_flush (gdb_stdout); | |
1340 | } | |
1341 | ||
1342 | static void | |
fba45db2 | 1343 | display_trace (int low, int high) |
c906108c SS |
1344 | { |
1345 | int i, count, trace_show_source, first, suppress; | |
1346 | CORE_ADDR next_address; | |
1347 | ||
1348 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1349 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1350 | { |
1351 | trace_show_source = 0; | |
1352 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1353 | printf_filtered ("Trace will not display any source.\n"); | |
1354 | } | |
1355 | ||
1356 | first = 1; | |
1357 | suppress = 0; | |
1358 | for (i = low; i < high; ++i) | |
1359 | { | |
1360 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1361 | count = trace_data.counts[i]; |
c906108c SS |
1362 | while (count-- > 0) |
1363 | { | |
1364 | QUIT; | |
1365 | if (trace_show_source) | |
1366 | { | |
1367 | struct symtab_and_line sal, sal_prev; | |
1368 | ||
1369 | sal_prev = find_pc_line (next_address - 4, 0); | |
1370 | sal = find_pc_line (next_address, 0); | |
1371 | ||
1372 | if (sal.symtab) | |
1373 | { | |
1374 | if (first || sal.line != sal_prev.line) | |
1375 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1376 | suppress = 0; | |
1377 | } | |
1378 | else | |
1379 | { | |
1380 | if (!suppress) | |
1381 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1382 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1383 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1384 | suppress = 1; |
1385 | } | |
1386 | } | |
1387 | first = 0; | |
1388 | print_address (next_address, gdb_stdout); | |
1389 | printf_filtered (":"); | |
1390 | printf_filtered ("\t"); | |
1391 | wrap_here (" "); | |
1392 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1393 | printf_filtered ("\n"); | |
1394 | gdb_flush (gdb_stdout); | |
1395 | } | |
1396 | } | |
1397 | } | |
1398 | ||
ac9a91a7 | 1399 | |
7f6104a9 AC |
1400 | static CORE_ADDR |
1401 | d10v_frame_pc_unwind (struct frame_info *frame, | |
1402 | void **cache) | |
1403 | { | |
1404 | struct d10v_unwind_cache *info = d10v_frame_unwind_cache (frame, cache); | |
1405 | return info->return_pc; | |
1406 | } | |
1407 | ||
1408 | /* Given a GDB frame, determine the address of the calling function's | |
1409 | frame. This will be used to create a new GDB frame struct. */ | |
1410 | ||
1411 | static void | |
1412 | d10v_frame_id_unwind (struct frame_info *frame, | |
1413 | void **cache, | |
1414 | struct frame_id *id) | |
1415 | { | |
1416 | struct d10v_unwind_cache *info = d10v_frame_unwind_cache (frame, cache); | |
1417 | CORE_ADDR addr; | |
1418 | ||
1419 | /* Start with a NULL frame ID. */ | |
1420 | (*id) = null_frame_id; | |
1421 | ||
1422 | if (info->return_pc == IMEM_START | |
1423 | || info->return_pc <= IMEM_START | |
1424 | || inside_entry_file (info->return_pc)) | |
1425 | { | |
1426 | /* This is meant to halt the backtrace at "_start". | |
1427 | Make sure we don't halt it at a generic dummy frame. */ | |
1428 | return; | |
1429 | } | |
1430 | ||
1431 | if (!info->saved_regs[FP_REGNUM]) | |
1432 | { | |
1433 | if (!info->saved_regs[SP_REGNUM] | |
1434 | || info->saved_regs[SP_REGNUM] == STACK_START) | |
1435 | return; | |
1436 | ||
1437 | id->base = info->saved_regs[SP_REGNUM]; | |
1438 | id->pc = info->return_pc; | |
1439 | } | |
1440 | ||
1441 | addr = read_memory_unsigned_integer (info->saved_regs[FP_REGNUM], | |
1442 | REGISTER_RAW_SIZE (FP_REGNUM)); | |
1443 | if (addr == 0) | |
1444 | return; | |
1445 | ||
1446 | id->base = d10v_make_daddr (addr); | |
1447 | id->pc = info->return_pc; | |
1448 | } | |
1449 | ||
1450 | static void | |
1451 | saved_regs_unwinder (struct frame_info *frame, | |
1452 | CORE_ADDR *saved_regs, | |
1453 | int regnum, int *optimizedp, | |
1454 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1455 | int *realnump, void *bufferp) | |
1456 | { | |
1457 | /* If we're using generic dummy frames, we'd better not be in a call | |
1458 | dummy. (generic_call_dummy_register_unwind ought to have been called | |
1459 | instead.) */ | |
1460 | gdb_assert (!(DEPRECATED_USE_GENERIC_DUMMY_FRAMES | |
1461 | && (get_frame_type (frame) == DUMMY_FRAME))); | |
1462 | ||
1463 | if (saved_regs[regnum] != 0) | |
1464 | { | |
1465 | if (regnum == SP_REGNUM) | |
1466 | { | |
1467 | /* SP register treated specially. */ | |
1468 | *optimizedp = 0; | |
1469 | *lvalp = not_lval; | |
1470 | *addrp = 0; | |
1471 | *realnump = -1; | |
1472 | if (bufferp != NULL) | |
1473 | store_address (bufferp, REGISTER_RAW_SIZE (regnum), | |
1474 | saved_regs[regnum]); | |
1475 | } | |
1476 | else | |
1477 | { | |
1478 | /* Any other register is saved in memory, fetch it but cache | |
1479 | a local copy of its value. */ | |
1480 | *optimizedp = 0; | |
1481 | *lvalp = lval_memory; | |
1482 | *addrp = saved_regs[regnum]; | |
1483 | *realnump = -1; | |
1484 | if (bufferp != NULL) | |
1485 | { | |
1486 | /* Read the value in from memory. */ | |
1487 | read_memory (saved_regs[regnum], bufferp, | |
1488 | REGISTER_RAW_SIZE (regnum)); | |
1489 | } | |
1490 | } | |
1491 | return; | |
1492 | } | |
1493 | ||
1494 | /* No luck, assume this and the next frame have the same register | |
1495 | value. If a value is needed, pass the request on down the chain; | |
1496 | otherwise just return an indication that the value is in the same | |
1497 | register as the next frame. */ | |
1498 | frame_register (frame, regnum, optimizedp, lvalp, addrp, | |
1499 | realnump, bufferp); | |
1500 | } | |
1501 | ||
1502 | ||
1503 | static void | |
1504 | d10v_frame_register_unwind (struct frame_info *frame, | |
1505 | void **cache, | |
1506 | int regnum, int *optimizedp, | |
1507 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1508 | int *realnump, void *bufferp) | |
1509 | { | |
1510 | struct d10v_unwind_cache *info = d10v_frame_unwind_cache (frame, cache); | |
1511 | saved_regs_unwinder (frame, info->saved_regs, regnum, optimizedp, | |
1512 | lvalp, addrp, realnump, bufferp); | |
1513 | } | |
1514 | ||
1515 | ||
1516 | static void | |
1517 | d10v_frame_pop (struct frame_info *fi, void **unwind_cache, | |
1518 | struct regcache *regcache) | |
1519 | { | |
1520 | struct d10v_unwind_cache *info = d10v_frame_unwind_cache (fi, unwind_cache); | |
1521 | CORE_ADDR fp; | |
1522 | int regnum; | |
1523 | char raw_buffer[8]; | |
1524 | ||
1525 | fp = get_frame_base (fi); | |
1526 | ||
1527 | /* now update the current registers with the old values */ | |
1528 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) | |
1529 | { | |
1530 | if (info->saved_regs[regnum]) | |
1531 | { | |
1532 | read_memory (info->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
1533 | deprecated_write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, | |
1534 | REGISTER_RAW_SIZE (regnum)); | |
1535 | } | |
1536 | } | |
1537 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
1538 | { | |
1539 | if (info->saved_regs[regnum]) | |
1540 | { | |
1541 | write_register (regnum, read_memory_unsigned_integer (info->saved_regs[regnum], REGISTER_RAW_SIZE (regnum))); | |
1542 | } | |
1543 | } | |
1544 | if (info->saved_regs[PSW_REGNUM]) | |
1545 | { | |
1546 | write_register (PSW_REGNUM, read_memory_unsigned_integer (info->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); | |
1547 | } | |
1548 | ||
1549 | write_register (PC_REGNUM, read_register (LR_REGNUM)); | |
1550 | write_register (SP_REGNUM, fp + info->size); | |
1551 | target_store_registers (-1); | |
1552 | flush_cached_frames (); | |
1553 | } | |
1554 | ||
1555 | static struct frame_unwind d10v_frame_unwind = { | |
1556 | d10v_frame_pop, | |
1557 | d10v_frame_pc_unwind, | |
1558 | d10v_frame_id_unwind, | |
1559 | d10v_frame_register_unwind | |
1560 | }; | |
1561 | ||
1562 | const struct frame_unwind * | |
1563 | d10v_frame_p (CORE_ADDR pc) | |
1564 | { | |
1565 | return &d10v_frame_unwind; | |
1566 | } | |
1567 | ||
0f71a2f6 | 1568 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1569 | |
0f71a2f6 | 1570 | static struct gdbarch * |
fba45db2 | 1571 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1572 | { |
c5aa993b JM |
1573 | static LONGEST d10v_call_dummy_words[] = |
1574 | {0}; | |
0f71a2f6 | 1575 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1576 | int d10v_num_regs; |
1577 | struct gdbarch_tdep *tdep; | |
1578 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1579 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1580 | |
4ce44c66 JM |
1581 | /* Find a candidate among the list of pre-declared architectures. */ |
1582 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1583 | if (arches != NULL) |
1584 | return arches->gdbarch; | |
4ce44c66 JM |
1585 | |
1586 | /* None found, create a new architecture from the information | |
1587 | provided. */ | |
1588 | tdep = XMALLOC (struct gdbarch_tdep); | |
1589 | gdbarch = gdbarch_alloc (&info, tdep); | |
1590 | ||
1591 | switch (info.bfd_arch_info->mach) | |
1592 | { | |
1593 | case bfd_mach_d10v_ts2: | |
1594 | d10v_num_regs = 37; | |
1595 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1596 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1597 | tdep->a0_regnum = TS2_A0_REGNUM; |
1598 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1599 | tdep->dmap_register = d10v_ts2_dmap_register; |
1600 | tdep->imap_register = d10v_ts2_imap_register; | |
1601 | break; | |
1602 | default: | |
1603 | case bfd_mach_d10v_ts3: | |
1604 | d10v_num_regs = 42; | |
1605 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1606 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1607 | tdep->a0_regnum = TS3_A0_REGNUM; |
1608 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1609 | tdep->dmap_register = d10v_ts3_dmap_register; |
1610 | tdep->imap_register = d10v_ts3_imap_register; | |
1611 | break; | |
1612 | } | |
0f71a2f6 JM |
1613 | |
1614 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1615 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1616 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
0f71a2f6 JM |
1617 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); |
1618 | set_gdbarch_write_sp (gdbarch, d10v_write_sp); | |
1619 | ||
1620 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1621 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1622 | set_gdbarch_fp_regnum (gdbarch, 11); | |
1623 | set_gdbarch_pc_regnum (gdbarch, 18); | |
1624 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1625 | set_gdbarch_register_size (gdbarch, 2); | |
1626 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1627 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1628 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
1629 | set_gdbarch_max_register_raw_size (gdbarch, 8); | |
8b279e7a | 1630 | set_gdbarch_register_virtual_size (gdbarch, generic_register_size); |
0f71a2f6 JM |
1631 | set_gdbarch_max_register_virtual_size (gdbarch, 8); |
1632 | set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); | |
1633 | ||
75af7f68 JB |
1634 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1635 | set_gdbarch_addr_bit (gdbarch, 32); | |
1636 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1637 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1638 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1639 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1640 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1641 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1642 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e AC |
1643 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1644 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1645 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1646 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1647 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1648 | switch (info.byte_order) |
1649 | { | |
d7449b42 | 1650 | case BFD_ENDIAN_BIG: |
f0d4cc9e AC |
1651 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
1652 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1653 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1654 | break; | |
778eb05e | 1655 | case BFD_ENDIAN_LITTLE: |
f0d4cc9e AC |
1656 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
1657 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1658 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1659 | break; | |
1660 | default: | |
8e65ff28 AC |
1661 | internal_error (__FILE__, __LINE__, |
1662 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1663 | } |
0f71a2f6 | 1664 | |
0f71a2f6 | 1665 | set_gdbarch_call_dummy_length (gdbarch, 0); |
0f71a2f6 JM |
1666 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
1667 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
1668 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
1669 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
0f71a2f6 JM |
1670 | set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); |
1671 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); | |
1672 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
1673 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
0f71a2f6 JM |
1674 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); |
1675 | ||
fa1fd571 | 1676 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); |
0f71a2f6 JM |
1677 | set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); |
1678 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
1679 | set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); | |
1680 | ||
0f71a2f6 | 1681 | set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); |
fa1fd571 AC |
1682 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); |
1683 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
0f71a2f6 JM |
1684 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); |
1685 | ||
0f71a2f6 JM |
1686 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); |
1687 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1688 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1689 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1690 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1691 | ||
1692 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1693 | ||
1694 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1695 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
f4ded5b1 | 1696 | |
0f71a2f6 JM |
1697 | set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); |
1698 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
23964bcd | 1699 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1700 | |
7c7651b2 | 1701 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
0a49d05e | 1702 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); |
7c7651b2 | 1703 | |
7f6104a9 AC |
1704 | frame_unwind_append_predicate (gdbarch, d10v_frame_p); |
1705 | ||
0f71a2f6 JM |
1706 | return gdbarch; |
1707 | } | |
1708 | ||
1709 | ||
507f3c78 KB |
1710 | extern void (*target_resume_hook) (void); |
1711 | extern void (*target_wait_loop_hook) (void); | |
c906108c SS |
1712 | |
1713 | void | |
fba45db2 | 1714 | _initialize_d10v_tdep (void) |
c906108c | 1715 | { |
0f71a2f6 JM |
1716 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1717 | ||
c906108c SS |
1718 | tm_print_insn = print_insn_d10v; |
1719 | ||
1720 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1721 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1722 | ||
1723 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
1724 | ||
cff3e48b | 1725 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1726 | "Enable tracing of instruction execution."); |
1727 | ||
cff3e48b | 1728 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1729 | "Disable tracing of instruction execution."); |
1730 | ||
cff3e48b | 1731 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1732 | "Disassemble the trace buffer.\n\ |
1733 | Two optional arguments specify a range of trace buffer entries\n\ | |
1734 | as reported by info trace (NOT addresses!)."); | |
1735 | ||
cff3e48b | 1736 | add_info ("itrace", trace_info, |
c906108c SS |
1737 | "Display info about the trace data buffer."); |
1738 | ||
cff3e48b | 1739 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1740 | var_integer, (char *) &trace_display, |
1741 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1742 | &showlist); |
cff3e48b | 1743 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1744 | var_integer, (char *) &default_trace_show_source, |
1745 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1746 | &showlist); |
1747 | ||
c5aa993b | 1748 | } |