Commit | Line | Data |
---|---|---|
4930751a C |
1 | /* Caching code. |
2 | Copyright 1992-1993, 1995, 1998-1999, 2000 Free Software Foundation, Inc. | |
c906108c SS |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
c5aa993b JM |
18 | Foundation, Inc., 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
20 | |
21 | #include "defs.h" | |
22 | #include "dcache.h" | |
23 | #include "gdbcmd.h" | |
24 | #include "gdb_string.h" | |
25 | #include "gdbcore.h" | |
4930751a | 26 | #include "target.h" |
c906108c SS |
27 | |
28 | /* | |
29 | The data cache could lead to incorrect results because it doesn't know | |
30 | about volatile variables, thus making it impossible to debug | |
31 | functions which use memory mapped I/O devices. | |
32 | ||
33 | set remotecache 0 | |
34 | ||
35 | In those cases. | |
36 | ||
37 | In general the dcache speeds up performance, some speed improvement | |
38 | comes from the actual caching mechanism, but the major gain is in | |
39 | the reduction of the remote protocol overhead; instead of reading | |
40 | or writing a large area of memory in 4 byte requests, the cache | |
41 | bundles up the requests into 32 byte (actually LINE_SIZE) chunks. | |
42 | Reducing the overhead to an eighth of what it was. This is very | |
43 | obvious when displaying a large amount of data, | |
44 | ||
45 | eg, x/200x 0 | |
46 | ||
47 | caching | no yes | |
48 | ---------------------------- | |
49 | first time | 4 sec 2 sec improvement due to chunking | |
50 | second time | 4 sec 0 sec improvement due to caching | |
51 | ||
52 | The cache structure is unusual, we keep a number of cache blocks | |
53 | (DCACHE_SIZE) and each one caches a LINE_SIZEed area of memory. | |
54 | Within each line we remember the address of the line (always a | |
55 | multiple of the LINE_SIZE) and a vector of bytes over the range. | |
56 | There's another vector which contains the state of the bytes. | |
57 | ||
58 | ENTRY_BAD means that the byte is just plain wrong, and has no | |
59 | correspondence with anything else (as it would when the cache is | |
60 | turned on, but nothing has been done to it. | |
61 | ||
62 | ENTRY_DIRTY means that the byte has some data in it which should be | |
63 | written out to the remote target one day, but contains correct | |
64 | data. ENTRY_OK means that the data is the same in the cache as it | |
65 | is in remote memory. | |
66 | ||
67 | ||
68 | The ENTRY_DIRTY state is necessary because GDB likes to write large | |
69 | lumps of memory in small bits. If the caching mechanism didn't | |
70 | maintain the DIRTY information, then something like a two byte | |
71 | write would mean that the entire cache line would have to be read, | |
72 | the two bytes modified and then written out again. The alternative | |
73 | would be to not read in the cache line in the first place, and just | |
74 | write the two bytes directly into target memory. The trouble with | |
75 | that is that it really nails performance, because of the remote | |
76 | protocol overhead. This way, all those little writes are bundled | |
77 | up into an entire cache line write in one go, without having to | |
78 | read the cache line in the first place. | |
79 | ||
80 | ||
c5aa993b | 81 | */ |
c906108c SS |
82 | |
83 | ||
84 | /* This value regulates the number of cache blocks stored. | |
85 | Smaller values reduce the time spent searching for a cache | |
86 | line, and reduce memory requirements, but increase the risk | |
87 | of a line not being in memory */ | |
88 | ||
c5aa993b | 89 | #define DCACHE_SIZE 64 |
c906108c SS |
90 | |
91 | /* This value regulates the size of a cache line. Smaller values | |
92 | reduce the time taken to read a single byte, but reduce overall | |
93 | throughput. */ | |
94 | ||
c5aa993b | 95 | #define LINE_SIZE_POWER (5) |
c906108c SS |
96 | #define LINE_SIZE (1 << LINE_SIZE_POWER) |
97 | ||
98 | /* Each cache block holds LINE_SIZE bytes of data | |
99 | starting at a multiple-of-LINE_SIZE address. */ | |
100 | ||
c5aa993b | 101 | #define LINE_SIZE_MASK ((LINE_SIZE - 1)) |
c906108c SS |
102 | #define XFORM(x) ((x) & LINE_SIZE_MASK) |
103 | #define MASK(x) ((x) & ~LINE_SIZE_MASK) | |
104 | ||
105 | ||
c5aa993b JM |
106 | #define ENTRY_BAD 0 /* data at this byte is wrong */ |
107 | #define ENTRY_DIRTY 1 /* data at this byte needs to be written back */ | |
108 | #define ENTRY_OK 2 /* data at this byte is same as in memory */ | |
c906108c SS |
109 | |
110 | ||
111 | struct dcache_block | |
c5aa993b JM |
112 | { |
113 | struct dcache_block *p; /* next in list */ | |
114 | CORE_ADDR addr; /* Address for which data is recorded. */ | |
115 | char data[LINE_SIZE]; /* bytes at given address */ | |
116 | unsigned char state[LINE_SIZE]; /* what state the data is in */ | |
c906108c | 117 | |
c5aa993b JM |
118 | /* whether anything in state is dirty - used to speed up the |
119 | dirty scan. */ | |
120 | int anydirty; | |
c906108c | 121 | |
c5aa993b JM |
122 | int refs; |
123 | }; | |
c906108c SS |
124 | |
125 | ||
c5aa993b JM |
126 | struct dcache_struct |
127 | { | |
c5aa993b JM |
128 | /* free list */ |
129 | struct dcache_block *free_head; | |
130 | struct dcache_block *free_tail; | |
c906108c | 131 | |
c5aa993b JM |
132 | /* in use list */ |
133 | struct dcache_block *valid_head; | |
134 | struct dcache_block *valid_tail; | |
c906108c | 135 | |
c5aa993b JM |
136 | /* The cache itself. */ |
137 | struct dcache_block *the_cache; | |
c906108c | 138 | |
c5aa993b JM |
139 | /* potentially, if the cache was enabled, and then turned off, and |
140 | then turned on again, the stuff in it could be stale, so this is | |
141 | used to mark it */ | |
142 | int cache_has_stuff; | |
143 | }; | |
c906108c | 144 | |
8edbea78 | 145 | static int dcache_poke_byte (DCACHE *dcache, CORE_ADDR addr, char *ptr); |
c906108c | 146 | |
8edbea78 | 147 | static int dcache_peek_byte (DCACHE *dcache, CORE_ADDR addr, char *ptr); |
c906108c | 148 | |
8edbea78 | 149 | static struct dcache_block *dcache_hit (DCACHE *dcache, CORE_ADDR addr); |
c906108c | 150 | |
8edbea78 | 151 | static int dcache_write_line (DCACHE *dcache, struct dcache_block *db); |
c906108c | 152 | |
8edbea78 | 153 | static int dcache_read_line (DCACHE *dcache, struct dcache_block *db); |
c906108c | 154 | |
8edbea78 C |
155 | static struct dcache_block *dcache_alloc (DCACHE *dcache, CORE_ADDR addr); |
156 | ||
157 | static int dcache_writeback (DCACHE *dcache); | |
c906108c | 158 | |
a14ed312 | 159 | static void dcache_info (char *exp, int tty); |
c906108c | 160 | |
a14ed312 | 161 | void _initialize_dcache (void); |
c906108c | 162 | |
917317f4 | 163 | static int dcache_enabled_p = 0; |
c906108c | 164 | |
c5aa993b | 165 | DCACHE *last_cache; /* Used by info dcache */ |
c906108c SS |
166 | |
167 | ||
168 | /* Free all the data cache blocks, thus discarding all cached data. */ | |
169 | ||
170 | void | |
4930751a | 171 | dcache_invalidate (DCACHE *dcache) |
c906108c SS |
172 | { |
173 | int i; | |
174 | dcache->valid_head = 0; | |
175 | dcache->valid_tail = 0; | |
176 | ||
177 | dcache->free_head = 0; | |
178 | dcache->free_tail = 0; | |
179 | ||
180 | for (i = 0; i < DCACHE_SIZE; i++) | |
181 | { | |
182 | struct dcache_block *db = dcache->the_cache + i; | |
183 | ||
184 | if (!dcache->free_head) | |
185 | dcache->free_head = db; | |
186 | else | |
187 | dcache->free_tail->p = db; | |
188 | dcache->free_tail = db; | |
189 | db->p = 0; | |
190 | } | |
191 | ||
192 | dcache->cache_has_stuff = 0; | |
193 | ||
194 | return; | |
195 | } | |
196 | ||
197 | /* If addr is present in the dcache, return the address of the block | |
198 | containing it. */ | |
199 | ||
200 | static struct dcache_block * | |
fba45db2 | 201 | dcache_hit (DCACHE *dcache, CORE_ADDR addr) |
c906108c SS |
202 | { |
203 | register struct dcache_block *db; | |
204 | ||
205 | /* Search all cache blocks for one that is at this address. */ | |
206 | db = dcache->valid_head; | |
207 | ||
208 | while (db) | |
209 | { | |
c5aa993b | 210 | if (MASK (addr) == db->addr) |
c906108c SS |
211 | { |
212 | db->refs++; | |
213 | return db; | |
214 | } | |
215 | db = db->p; | |
216 | } | |
217 | ||
218 | return NULL; | |
219 | } | |
220 | ||
221 | /* Make sure that anything in this line which needs to | |
222 | be written is. */ | |
223 | ||
224 | static int | |
fba45db2 | 225 | dcache_write_line (DCACHE *dcache, register struct dcache_block *db) |
c906108c SS |
226 | { |
227 | int s; | |
228 | int e; | |
8edbea78 | 229 | |
c906108c SS |
230 | if (db->anydirty) |
231 | { | |
232 | for (s = 0; s < LINE_SIZE; s++) | |
233 | { | |
234 | if (db->state[s] == ENTRY_DIRTY) | |
235 | { | |
236 | int len = 0; | |
c5aa993b | 237 | for (e = s; e < LINE_SIZE; e++, len++) |
c906108c SS |
238 | if (db->state[e] != ENTRY_DIRTY) |
239 | break; | |
240 | { | |
241 | /* all bytes from s..s+len-1 need to | |
242 | be written out */ | |
243 | int done = 0; | |
c5aa993b JM |
244 | while (done < len) |
245 | { | |
4930751a C |
246 | int t = do_xfer_memory (db->addr + s + done, |
247 | db->data + s + done, | |
248 | len - done, 1); | |
249 | if (t <= 0) | |
c5aa993b JM |
250 | return 0; |
251 | done += t; | |
252 | } | |
c906108c SS |
253 | memset (db->state + s, ENTRY_OK, len); |
254 | s = e; | |
255 | } | |
256 | } | |
257 | } | |
258 | db->anydirty = 0; | |
259 | } | |
260 | return 1; | |
261 | } | |
262 | ||
8edbea78 C |
263 | /* Read cache line */ |
264 | static int | |
265 | dcache_read_line (DCACHE *dcache, struct dcache_block *db) | |
266 | { | |
267 | CORE_ADDR memaddr; | |
268 | char *myaddr; | |
269 | int len; | |
270 | int res; | |
271 | ||
272 | /* If there are any dirty bytes in the line, it must be written | |
273 | before a new line can be read */ | |
274 | if (db->anydirty) | |
275 | { | |
276 | if (!dcache_write_line (dcache, db)) | |
277 | return 0; | |
278 | } | |
279 | ||
280 | len = LINE_SIZE; | |
281 | memaddr = db->addr; | |
282 | myaddr = db->data; | |
283 | ||
284 | while (len > 0) | |
285 | { | |
4930751a C |
286 | res = do_xfer_memory (memaddr, myaddr, len, 0); |
287 | if (res <= 0) | |
8edbea78 C |
288 | return 0; |
289 | ||
290 | memaddr += res; | |
291 | myaddr += res; | |
292 | len -= res; | |
293 | } | |
294 | ||
295 | memset (db->state, ENTRY_OK, sizeof (db->data)); | |
296 | db->anydirty = 0; | |
297 | ||
298 | return 1; | |
299 | } | |
300 | ||
c906108c | 301 | /* Get a free cache block, put or keep it on the valid list, |
f1d7622b | 302 | and return its address. */ |
c906108c SS |
303 | |
304 | static struct dcache_block * | |
f1d7622b | 305 | dcache_alloc (DCACHE *dcache, CORE_ADDR addr) |
c906108c SS |
306 | { |
307 | register struct dcache_block *db; | |
308 | ||
917317f4 | 309 | if (dcache_enabled_p == 0) |
c906108c SS |
310 | abort (); |
311 | ||
312 | /* Take something from the free list */ | |
313 | db = dcache->free_head; | |
314 | if (db) | |
315 | { | |
316 | dcache->free_head = db->p; | |
317 | } | |
318 | else | |
319 | { | |
320 | /* Nothing left on free list, so grab one from the valid list */ | |
321 | db = dcache->valid_head; | |
c906108c | 322 | |
8edbea78 C |
323 | if (!dcache_write_line (dcache, db)) |
324 | return NULL; | |
325 | ||
326 | dcache->valid_head = db->p; | |
c906108c SS |
327 | } |
328 | ||
f1d7622b C |
329 | db->addr = MASK(addr); |
330 | db->refs = 0; | |
331 | db->anydirty = 0; | |
332 | memset (db->state, ENTRY_BAD, sizeof (db->data)); | |
333 | ||
c906108c SS |
334 | /* append this line to end of valid list */ |
335 | if (!dcache->valid_head) | |
336 | dcache->valid_head = db; | |
337 | else | |
338 | dcache->valid_tail->p = db; | |
339 | dcache->valid_tail = db; | |
340 | db->p = 0; | |
341 | ||
342 | return db; | |
343 | } | |
344 | ||
c906108c SS |
345 | /* Writeback any dirty lines to the remote. */ |
346 | static int | |
fba45db2 | 347 | dcache_writeback (DCACHE *dcache) |
c906108c SS |
348 | { |
349 | struct dcache_block *db; | |
350 | ||
351 | db = dcache->valid_head; | |
352 | ||
353 | while (db) | |
354 | { | |
355 | if (!dcache_write_line (dcache, db)) | |
356 | return 0; | |
357 | db = db->p; | |
358 | } | |
359 | return 1; | |
360 | } | |
361 | ||
362 | ||
8edbea78 C |
363 | /* Using the data cache DCACHE return the contents of the byte at |
364 | address ADDR in the remote machine. | |
365 | ||
366 | Returns 0 on error. */ | |
367 | ||
368 | static int | |
369 | dcache_peek_byte (DCACHE *dcache, CORE_ADDR addr, char *ptr) | |
370 | { | |
371 | register struct dcache_block *db = dcache_hit (dcache, addr); | |
372 | ||
373 | if (!db) | |
374 | { | |
375 | db = dcache_alloc (dcache, addr); | |
376 | if (!db) | |
377 | return 0; | |
378 | } | |
379 | ||
380 | if (db->state[XFORM (addr)] == ENTRY_BAD) | |
381 | { | |
382 | if (!dcache_read_line(dcache, db)) | |
383 | return 0; | |
384 | } | |
385 | ||
386 | *ptr = db->data[XFORM (addr)]; | |
387 | return 1; | |
388 | } | |
389 | ||
390 | ||
c906108c SS |
391 | /* Write the byte at PTR into ADDR in the data cache. |
392 | Return zero on write error. | |
393 | */ | |
394 | ||
395 | static int | |
fba45db2 | 396 | dcache_poke_byte (DCACHE *dcache, CORE_ADDR addr, char *ptr) |
c906108c SS |
397 | { |
398 | register struct dcache_block *db = dcache_hit (dcache, addr); | |
399 | ||
400 | if (!db) | |
401 | { | |
f1d7622b | 402 | db = dcache_alloc (dcache, addr); |
8edbea78 C |
403 | if (!db) |
404 | return 0; | |
c906108c SS |
405 | } |
406 | ||
407 | db->data[XFORM (addr)] = *ptr; | |
408 | db->state[XFORM (addr)] = ENTRY_DIRTY; | |
409 | db->anydirty = 1; | |
410 | return 1; | |
411 | } | |
412 | ||
c906108c SS |
413 | /* Initialize the data cache. */ |
414 | DCACHE * | |
4930751a | 415 | dcache_init (void) |
c906108c SS |
416 | { |
417 | int csize = sizeof (struct dcache_block) * DCACHE_SIZE; | |
418 | DCACHE *dcache; | |
419 | ||
420 | dcache = (DCACHE *) xmalloc (sizeof (*dcache)); | |
c906108c SS |
421 | |
422 | dcache->the_cache = (struct dcache_block *) xmalloc (csize); | |
423 | memset (dcache->the_cache, 0, csize); | |
424 | ||
4930751a | 425 | dcache_invalidate (dcache); |
c906108c SS |
426 | |
427 | last_cache = dcache; | |
428 | return dcache; | |
429 | } | |
430 | ||
e99586d5 C |
431 | /* Free a data cache */ |
432 | void | |
433 | dcache_free (DCACHE *dcache) | |
434 | { | |
435 | if (last_cache == dcache) | |
436 | last_cache = NULL; | |
437 | ||
b8c9b27d KB |
438 | xfree (dcache->the_cache); |
439 | xfree (dcache); | |
e99586d5 C |
440 | } |
441 | ||
c906108c SS |
442 | /* Read or write LEN bytes from inferior memory at MEMADDR, transferring |
443 | to or from debugger address MYADDR. Write to inferior if SHOULD_WRITE is | |
444 | nonzero. | |
445 | ||
446 | Returns length of data written or read; 0 for error. | |
447 | ||
448 | This routine is indended to be called by remote_xfer_ functions. */ | |
449 | ||
450 | int | |
fba45db2 KB |
451 | dcache_xfer_memory (DCACHE *dcache, CORE_ADDR memaddr, char *myaddr, int len, |
452 | int should_write) | |
c906108c SS |
453 | { |
454 | int i; | |
455 | ||
917317f4 | 456 | if (dcache_enabled_p) |
c906108c | 457 | { |
8edbea78 | 458 | int (*xfunc) (DCACHE *dcache, CORE_ADDR addr, char *ptr); |
c906108c SS |
459 | xfunc = should_write ? dcache_poke_byte : dcache_peek_byte; |
460 | ||
461 | for (i = 0; i < len; i++) | |
462 | { | |
463 | if (!xfunc (dcache, memaddr + i, myaddr + i)) | |
464 | return 0; | |
465 | } | |
8edbea78 C |
466 | |
467 | if (should_write) | |
468 | dcache_writeback (dcache); | |
469 | ||
c906108c | 470 | dcache->cache_has_stuff = 1; |
c906108c | 471 | } |
c5aa993b | 472 | else |
c906108c | 473 | { |
c906108c | 474 | if (dcache->cache_has_stuff) |
4930751a | 475 | dcache_invalidate (dcache); |
c906108c | 476 | |
4930751a | 477 | len = do_xfer_memory(memaddr, myaddr, len, should_write); |
c906108c SS |
478 | } |
479 | return len; | |
480 | } | |
481 | ||
c5aa993b | 482 | static void |
fba45db2 | 483 | dcache_info (char *exp, int tty) |
c906108c SS |
484 | { |
485 | struct dcache_block *p; | |
486 | ||
917317f4 | 487 | if (!dcache_enabled_p) |
c906108c SS |
488 | { |
489 | printf_filtered ("Dcache not enabled\n"); | |
490 | return; | |
491 | } | |
492 | printf_filtered ("Dcache enabled, line width %d, depth %d\n", | |
493 | LINE_SIZE, DCACHE_SIZE); | |
494 | ||
5e2039ea | 495 | if (last_cache) |
c906108c | 496 | { |
5e2039ea C |
497 | printf_filtered ("Cache state:\n"); |
498 | ||
499 | for (p = last_cache->valid_head; p; p = p->p) | |
500 | { | |
501 | int j; | |
502 | printf_filtered ("Line at %s, referenced %d times\n", | |
503 | paddr (p->addr), p->refs); | |
c906108c | 504 | |
5e2039ea C |
505 | for (j = 0; j < LINE_SIZE; j++) |
506 | printf_filtered ("%02x", p->data[j] & 0xFF); | |
507 | printf_filtered ("\n"); | |
c906108c | 508 | |
5e2039ea | 509 | for (j = 0; j < LINE_SIZE; j++) |
8edbea78 | 510 | printf_filtered ("%2x", p->state[j]); |
5e2039ea C |
511 | printf_filtered ("\n"); |
512 | } | |
c906108c SS |
513 | } |
514 | } | |
515 | ||
c2d11a7d JM |
516 | /* Turn dcache on or off. */ |
517 | void | |
518 | set_dcache_state (int what) | |
519 | { | |
520 | dcache_enabled_p = !!what; | |
521 | } | |
522 | ||
c906108c | 523 | void |
fba45db2 | 524 | _initialize_dcache (void) |
c906108c SS |
525 | { |
526 | add_show_from_set | |
527 | (add_set_cmd ("remotecache", class_support, var_boolean, | |
917317f4 | 528 | (char *) &dcache_enabled_p, |
c906108c SS |
529 | "\ |
530 | Set cache use for remote targets.\n\ | |
531 | When on, use data caching for remote targets. For many remote targets\n\ | |
532 | this option can offer better throughput for reading target memory.\n\ | |
533 | Unfortunately, gdb does not currently know anything about volatile\n\ | |
534 | registers and thus data caching will produce incorrect results with\n\ | |
917317f4 | 535 | volatile registers are in use. By default, this option is off.", |
c906108c SS |
536 | &setlist), |
537 | &showlist); | |
538 | ||
539 | add_info ("dcache", dcache_info, | |
540 | "Print information on the dcache performance."); | |
541 | ||
542 | } |