sim: allow the assert configure option everywhere
[deliverable/binutils-gdb.git] / gdb / features / arm-with-vfpv3.c
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1/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
2 Original: arm-with-vfpv3.xml */
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3
4#include "defs.h"
8ab03ccb 5#include "osabi.h"
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6#include "target-descriptions.h"
7
8struct target_desc *tdesc_arm_with_vfpv3;
9static void
10initialize_tdesc_arm_with_vfpv3 (void)
11{
12 struct target_desc *result = allocate_target_description ();
13 struct tdesc_feature *feature;
58d6951d 14
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15 set_tdesc_architecture (result, bfd_scan_arch ("arm"));
16
58d6951d 17 feature = tdesc_create_feature (result, "org.gnu.gdb.arm.core");
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18 tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "uint32");
19 tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "uint32");
20 tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "uint32");
21 tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "uint32");
22 tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "uint32");
23 tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "uint32");
24 tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "uint32");
25 tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "uint32");
26 tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "uint32");
27 tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "uint32");
28 tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "uint32");
29 tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "uint32");
30 tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "uint32");
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31 tdesc_create_reg (feature, "sp", 13, 1, NULL, 32, "data_ptr");
32 tdesc_create_reg (feature, "lr", 14, 1, NULL, 32, "int");
33 tdesc_create_reg (feature, "pc", 15, 1, NULL, 32, "code_ptr");
34 tdesc_create_reg (feature, "cpsr", 25, 1, NULL, 32, "int");
35
36 feature = tdesc_create_feature (result, "org.gnu.gdb.arm.vfp");
37 tdesc_create_reg (feature, "d0", 26, 1, NULL, 64, "ieee_double");
38 tdesc_create_reg (feature, "d1", 27, 1, NULL, 64, "ieee_double");
39 tdesc_create_reg (feature, "d2", 28, 1, NULL, 64, "ieee_double");
40 tdesc_create_reg (feature, "d3", 29, 1, NULL, 64, "ieee_double");
41 tdesc_create_reg (feature, "d4", 30, 1, NULL, 64, "ieee_double");
42 tdesc_create_reg (feature, "d5", 31, 1, NULL, 64, "ieee_double");
43 tdesc_create_reg (feature, "d6", 32, 1, NULL, 64, "ieee_double");
44 tdesc_create_reg (feature, "d7", 33, 1, NULL, 64, "ieee_double");
45 tdesc_create_reg (feature, "d8", 34, 1, NULL, 64, "ieee_double");
46 tdesc_create_reg (feature, "d9", 35, 1, NULL, 64, "ieee_double");
47 tdesc_create_reg (feature, "d10", 36, 1, NULL, 64, "ieee_double");
48 tdesc_create_reg (feature, "d11", 37, 1, NULL, 64, "ieee_double");
49 tdesc_create_reg (feature, "d12", 38, 1, NULL, 64, "ieee_double");
50 tdesc_create_reg (feature, "d13", 39, 1, NULL, 64, "ieee_double");
51 tdesc_create_reg (feature, "d14", 40, 1, NULL, 64, "ieee_double");
52 tdesc_create_reg (feature, "d15", 41, 1, NULL, 64, "ieee_double");
53 tdesc_create_reg (feature, "d16", 42, 1, NULL, 64, "ieee_double");
54 tdesc_create_reg (feature, "d17", 43, 1, NULL, 64, "ieee_double");
55 tdesc_create_reg (feature, "d18", 44, 1, NULL, 64, "ieee_double");
56 tdesc_create_reg (feature, "d19", 45, 1, NULL, 64, "ieee_double");
57 tdesc_create_reg (feature, "d20", 46, 1, NULL, 64, "ieee_double");
58 tdesc_create_reg (feature, "d21", 47, 1, NULL, 64, "ieee_double");
59 tdesc_create_reg (feature, "d22", 48, 1, NULL, 64, "ieee_double");
60 tdesc_create_reg (feature, "d23", 49, 1, NULL, 64, "ieee_double");
61 tdesc_create_reg (feature, "d24", 50, 1, NULL, 64, "ieee_double");
62 tdesc_create_reg (feature, "d25", 51, 1, NULL, 64, "ieee_double");
63 tdesc_create_reg (feature, "d26", 52, 1, NULL, 64, "ieee_double");
64 tdesc_create_reg (feature, "d27", 53, 1, NULL, 64, "ieee_double");
65 tdesc_create_reg (feature, "d28", 54, 1, NULL, 64, "ieee_double");
66 tdesc_create_reg (feature, "d29", 55, 1, NULL, 64, "ieee_double");
67 tdesc_create_reg (feature, "d30", 56, 1, NULL, 64, "ieee_double");
68 tdesc_create_reg (feature, "d31", 57, 1, NULL, 64, "ieee_double");
69 tdesc_create_reg (feature, "fpscr", 58, 1, "float", 32, "int");
70
71 tdesc_arm_with_vfpv3 = result;
72}
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