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456f8b9d | 1 | /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger. |
9ab9195f | 2 | Copyright 2002, 2003, 2004 Free Software Foundation, Inc. |
456f8b9d DB |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include "defs.h" | |
8baa6f92 | 22 | #include "gdb_string.h" |
456f8b9d | 23 | #include "inferior.h" |
456f8b9d DB |
24 | #include "gdbcore.h" |
25 | #include "arch-utils.h" | |
26 | #include "regcache.h" | |
8baa6f92 | 27 | #include "frame.h" |
1cb761c7 KB |
28 | #include "frame-unwind.h" |
29 | #include "frame-base.h" | |
8baa6f92 | 30 | #include "trad-frame.h" |
dcc6aaff | 31 | #include "dis-asm.h" |
526eef89 KB |
32 | #include "gdb_assert.h" |
33 | #include "sim-regno.h" | |
34 | #include "gdb/sim-frv.h" | |
35 | #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */ | |
634aa483 | 36 | #include "symtab.h" |
7e295833 KB |
37 | #include "elf-bfd.h" |
38 | #include "elf/frv.h" | |
39 | #include "osabi.h" | |
40 | #include "frv-tdep.h" | |
456f8b9d DB |
41 | |
42 | extern void _initialize_frv_tdep (void); | |
43 | ||
44 | static gdbarch_init_ftype frv_gdbarch_init; | |
45 | ||
46 | static gdbarch_register_name_ftype frv_register_name; | |
456f8b9d | 47 | static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc; |
46a16dba | 48 | static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address; |
456f8b9d | 49 | static gdbarch_skip_prologue_ftype frv_skip_prologue; |
456f8b9d | 50 | |
456f8b9d | 51 | |
1cb761c7 | 52 | struct frv_unwind_cache /* was struct frame_extra_info */ |
456f8b9d | 53 | { |
1cb761c7 KB |
54 | /* The previous frame's inner-most stack address. Used as this |
55 | frame ID's stack_addr. */ | |
56 | CORE_ADDR prev_sp; | |
456f8b9d | 57 | |
1cb761c7 KB |
58 | /* The frame's base, optionally used by the high-level debug info. */ |
59 | CORE_ADDR base; | |
8baa6f92 KB |
60 | |
61 | /* Table indicating the location of each and every register. */ | |
62 | struct trad_frame_saved_reg *saved_regs; | |
456f8b9d DB |
63 | }; |
64 | ||
456f8b9d DB |
65 | /* A structure describing a particular variant of the FRV. |
66 | We allocate and initialize one of these structures when we create | |
67 | the gdbarch object for a variant. | |
68 | ||
69 | At the moment, all the FR variants we support differ only in which | |
70 | registers are present; the portable code of GDB knows that | |
71 | registers whose names are the empty string don't exist, so the | |
72 | `register_names' array captures all the per-variant information we | |
73 | need. | |
74 | ||
75 | in the future, if we need to have per-variant maps for raw size, | |
76 | virtual type, etc., we should replace register_names with an array | |
77 | of structures, each of which gives all the necessary info for one | |
78 | register. Don't stick parallel arrays in here --- that's so | |
79 | Fortran. */ | |
80 | struct gdbarch_tdep | |
81 | { | |
7e295833 KB |
82 | /* Which ABI is in use? */ |
83 | enum frv_abi frv_abi; | |
84 | ||
456f8b9d DB |
85 | /* How many general-purpose registers does this variant have? */ |
86 | int num_gprs; | |
87 | ||
88 | /* How many floating-point registers does this variant have? */ | |
89 | int num_fprs; | |
90 | ||
91 | /* How many hardware watchpoints can it support? */ | |
92 | int num_hw_watchpoints; | |
93 | ||
94 | /* How many hardware breakpoints can it support? */ | |
95 | int num_hw_breakpoints; | |
96 | ||
97 | /* Register names. */ | |
98 | char **register_names; | |
99 | }; | |
100 | ||
101 | #define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch)) | |
102 | ||
7e295833 KB |
103 | /* Return the FR-V ABI associated with GDBARCH. */ |
104 | enum frv_abi | |
105 | frv_abi (struct gdbarch *gdbarch) | |
106 | { | |
107 | return gdbarch_tdep (gdbarch)->frv_abi; | |
108 | } | |
109 | ||
110 | /* Fetch the interpreter and executable loadmap addresses (for shared | |
111 | library support) for the FDPIC ABI. Return 0 if successful, -1 if | |
112 | not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */ | |
113 | int | |
114 | frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr, | |
115 | CORE_ADDR *exec_addr) | |
116 | { | |
117 | if (frv_abi (gdbarch) != FRV_ABI_FDPIC) | |
118 | return -1; | |
119 | else | |
120 | { | |
121 | if (interp_addr != NULL) | |
122 | { | |
123 | ULONGEST val; | |
124 | regcache_cooked_read_unsigned (current_regcache, | |
125 | fdpic_loadmap_interp_regnum, &val); | |
126 | *interp_addr = val; | |
127 | } | |
128 | if (exec_addr != NULL) | |
129 | { | |
130 | ULONGEST val; | |
131 | regcache_cooked_read_unsigned (current_regcache, | |
132 | fdpic_loadmap_exec_regnum, &val); | |
133 | *exec_addr = val; | |
134 | } | |
135 | return 0; | |
136 | } | |
137 | } | |
456f8b9d DB |
138 | |
139 | /* Allocate a new variant structure, and set up default values for all | |
140 | the fields. */ | |
141 | static struct gdbarch_tdep * | |
5ae5f592 | 142 | new_variant (void) |
456f8b9d DB |
143 | { |
144 | struct gdbarch_tdep *var; | |
145 | int r; | |
146 | char buf[20]; | |
147 | ||
148 | var = xmalloc (sizeof (*var)); | |
149 | memset (var, 0, sizeof (*var)); | |
150 | ||
7e295833 | 151 | var->frv_abi = FRV_ABI_EABI; |
456f8b9d DB |
152 | var->num_gprs = 64; |
153 | var->num_fprs = 64; | |
154 | var->num_hw_watchpoints = 0; | |
155 | var->num_hw_breakpoints = 0; | |
156 | ||
157 | /* By default, don't supply any general-purpose or floating-point | |
158 | register names. */ | |
6a748db6 KB |
159 | var->register_names |
160 | = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs) | |
161 | * sizeof (char *)); | |
162 | for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++) | |
456f8b9d DB |
163 | var->register_names[r] = ""; |
164 | ||
526eef89 | 165 | /* Do, however, supply default names for the known special-purpose |
456f8b9d | 166 | registers. */ |
456f8b9d DB |
167 | |
168 | var->register_names[pc_regnum] = "pc"; | |
169 | var->register_names[lr_regnum] = "lr"; | |
170 | var->register_names[lcr_regnum] = "lcr"; | |
171 | ||
172 | var->register_names[psr_regnum] = "psr"; | |
173 | var->register_names[ccr_regnum] = "ccr"; | |
174 | var->register_names[cccr_regnum] = "cccr"; | |
175 | var->register_names[tbr_regnum] = "tbr"; | |
176 | ||
177 | /* Debug registers. */ | |
178 | var->register_names[brr_regnum] = "brr"; | |
179 | var->register_names[dbar0_regnum] = "dbar0"; | |
180 | var->register_names[dbar1_regnum] = "dbar1"; | |
181 | var->register_names[dbar2_regnum] = "dbar2"; | |
182 | var->register_names[dbar3_regnum] = "dbar3"; | |
183 | ||
526eef89 KB |
184 | /* iacc0 (Only found on MB93405.) */ |
185 | var->register_names[iacc0h_regnum] = "iacc0h"; | |
186 | var->register_names[iacc0l_regnum] = "iacc0l"; | |
6a748db6 | 187 | var->register_names[iacc0_regnum] = "iacc0"; |
526eef89 | 188 | |
456f8b9d DB |
189 | return var; |
190 | } | |
191 | ||
192 | ||
193 | /* Indicate that the variant VAR has NUM_GPRS general-purpose | |
194 | registers, and fill in the names array appropriately. */ | |
195 | static void | |
196 | set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs) | |
197 | { | |
198 | int r; | |
199 | ||
200 | var->num_gprs = num_gprs; | |
201 | ||
202 | for (r = 0; r < num_gprs; ++r) | |
203 | { | |
204 | char buf[20]; | |
205 | ||
206 | sprintf (buf, "gr%d", r); | |
207 | var->register_names[first_gpr_regnum + r] = xstrdup (buf); | |
208 | } | |
209 | } | |
210 | ||
211 | ||
212 | /* Indicate that the variant VAR has NUM_FPRS floating-point | |
213 | registers, and fill in the names array appropriately. */ | |
214 | static void | |
215 | set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs) | |
216 | { | |
217 | int r; | |
218 | ||
219 | var->num_fprs = num_fprs; | |
220 | ||
221 | for (r = 0; r < num_fprs; ++r) | |
222 | { | |
223 | char buf[20]; | |
224 | ||
225 | sprintf (buf, "fr%d", r); | |
226 | var->register_names[first_fpr_regnum + r] = xstrdup (buf); | |
227 | } | |
228 | } | |
229 | ||
7e295833 KB |
230 | static void |
231 | set_variant_abi_fdpic (struct gdbarch_tdep *var) | |
232 | { | |
233 | var->frv_abi = FRV_ABI_FDPIC; | |
234 | var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec"); | |
235 | var->register_names[fdpic_loadmap_interp_regnum] = xstrdup ("loadmap_interp"); | |
236 | } | |
456f8b9d | 237 | |
b2d6d697 KB |
238 | static void |
239 | set_variant_scratch_registers (struct gdbarch_tdep *var) | |
240 | { | |
241 | var->register_names[scr0_regnum] = xstrdup ("scr0"); | |
242 | var->register_names[scr1_regnum] = xstrdup ("scr1"); | |
243 | var->register_names[scr2_regnum] = xstrdup ("scr2"); | |
244 | var->register_names[scr3_regnum] = xstrdup ("scr3"); | |
245 | } | |
246 | ||
456f8b9d DB |
247 | static const char * |
248 | frv_register_name (int reg) | |
249 | { | |
250 | if (reg < 0) | |
251 | return "?toosmall?"; | |
6a748db6 | 252 | if (reg >= frv_num_regs + frv_num_pseudo_regs) |
456f8b9d DB |
253 | return "?toolarge?"; |
254 | ||
255 | return CURRENT_VARIANT->register_names[reg]; | |
256 | } | |
257 | ||
526eef89 | 258 | |
456f8b9d | 259 | static struct type * |
7f398216 | 260 | frv_register_type (struct gdbarch *gdbarch, int reg) |
456f8b9d | 261 | { |
526eef89 | 262 | if (reg >= first_fpr_regnum && reg <= last_fpr_regnum) |
456f8b9d | 263 | return builtin_type_float; |
6a748db6 KB |
264 | else if (reg == iacc0_regnum) |
265 | return builtin_type_int64; | |
456f8b9d | 266 | else |
526eef89 | 267 | return builtin_type_int32; |
456f8b9d DB |
268 | } |
269 | ||
6a748db6 KB |
270 | static void |
271 | frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
272 | int reg, void *buffer) | |
273 | { | |
274 | if (reg == iacc0_regnum) | |
275 | { | |
276 | regcache_raw_read (regcache, iacc0h_regnum, buffer); | |
277 | regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); | |
278 | } | |
279 | } | |
280 | ||
281 | static void | |
282 | frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
283 | int reg, const void *buffer) | |
284 | { | |
285 | if (reg == iacc0_regnum) | |
286 | { | |
287 | regcache_raw_write (regcache, iacc0h_regnum, buffer); | |
288 | regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); | |
289 | } | |
290 | } | |
291 | ||
526eef89 KB |
292 | static int |
293 | frv_register_sim_regno (int reg) | |
294 | { | |
295 | static const int spr_map[] = | |
296 | { | |
297 | H_SPR_PSR, /* psr_regnum */ | |
298 | H_SPR_CCR, /* ccr_regnum */ | |
299 | H_SPR_CCCR, /* cccr_regnum */ | |
300 | -1, /* 132 */ | |
301 | -1, /* 133 */ | |
302 | -1, /* 134 */ | |
303 | H_SPR_TBR, /* tbr_regnum */ | |
304 | H_SPR_BRR, /* brr_regnum */ | |
305 | H_SPR_DBAR0, /* dbar0_regnum */ | |
306 | H_SPR_DBAR1, /* dbar1_regnum */ | |
307 | H_SPR_DBAR2, /* dbar2_regnum */ | |
308 | H_SPR_DBAR3, /* dbar3_regnum */ | |
309 | -1, /* 141 */ | |
310 | -1, /* 142 */ | |
311 | -1, /* 143 */ | |
312 | -1, /* 144 */ | |
313 | H_SPR_LR, /* lr_regnum */ | |
314 | H_SPR_LCR, /* lcr_regnum */ | |
315 | H_SPR_IACC0H, /* iacc0h_regnum */ | |
316 | H_SPR_IACC0L /* iacc0l_regnum */ | |
317 | }; | |
318 | ||
319 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
320 | ||
321 | if (first_gpr_regnum <= reg && reg <= last_gpr_regnum) | |
322 | return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM; | |
323 | else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum) | |
324 | return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM; | |
325 | else if (pc_regnum == reg) | |
326 | return SIM_FRV_PC_REGNUM; | |
327 | else if (reg >= first_spr_regnum | |
328 | && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0])) | |
329 | { | |
330 | int spr_reg_offset = spr_map[reg - first_spr_regnum]; | |
331 | ||
332 | if (spr_reg_offset < 0) | |
333 | return SIM_REGNO_DOES_NOT_EXIST; | |
334 | else | |
335 | return SIM_FRV_SPR0_REGNUM + spr_reg_offset; | |
336 | } | |
337 | ||
338 | internal_error (__FILE__, __LINE__, "Bad register number %d", reg); | |
339 | } | |
340 | ||
456f8b9d DB |
341 | static const unsigned char * |
342 | frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp) | |
343 | { | |
344 | static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01}; | |
345 | *lenp = sizeof (breakpoint); | |
346 | return breakpoint; | |
347 | } | |
348 | ||
46a16dba KB |
349 | /* Define the maximum number of instructions which may be packed into a |
350 | bundle (VLIW instruction). */ | |
351 | static const int max_instrs_per_bundle = 8; | |
352 | ||
353 | /* Define the size (in bytes) of an FR-V instruction. */ | |
354 | static const int frv_instr_size = 4; | |
355 | ||
356 | /* Adjust a breakpoint's address to account for the FR-V architecture's | |
357 | constraint that a break instruction must not appear as any but the | |
358 | first instruction in the bundle. */ | |
359 | static CORE_ADDR | |
360 | frv_gdbarch_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
361 | { | |
362 | int count = max_instrs_per_bundle; | |
363 | CORE_ADDR addr = bpaddr - frv_instr_size; | |
364 | CORE_ADDR func_start = get_pc_function_start (bpaddr); | |
365 | ||
366 | /* Find the end of the previous packing sequence. This will be indicated | |
367 | by either attempting to access some inaccessible memory or by finding | |
368 | an instruction word whose packing bit is set to one. */ | |
369 | while (count-- > 0 && addr >= func_start) | |
370 | { | |
371 | char instr[frv_instr_size]; | |
372 | int status; | |
373 | ||
374 | status = read_memory_nobpt (addr, instr, sizeof instr); | |
375 | ||
376 | if (status != 0) | |
377 | break; | |
378 | ||
379 | /* This is a big endian architecture, so byte zero will have most | |
380 | significant byte. The most significant bit of this byte is the | |
381 | packing bit. */ | |
382 | if (instr[0] & 0x80) | |
383 | break; | |
384 | ||
385 | addr -= frv_instr_size; | |
386 | } | |
387 | ||
388 | if (count > 0) | |
389 | bpaddr = addr + frv_instr_size; | |
390 | ||
391 | return bpaddr; | |
392 | } | |
393 | ||
456f8b9d DB |
394 | |
395 | /* Return true if REG is a caller-saves ("scratch") register, | |
396 | false otherwise. */ | |
397 | static int | |
398 | is_caller_saves_reg (int reg) | |
399 | { | |
400 | return ((4 <= reg && reg <= 7) | |
401 | || (14 <= reg && reg <= 15) | |
402 | || (32 <= reg && reg <= 47)); | |
403 | } | |
404 | ||
405 | ||
406 | /* Return true if REG is a callee-saves register, false otherwise. */ | |
407 | static int | |
408 | is_callee_saves_reg (int reg) | |
409 | { | |
410 | return ((16 <= reg && reg <= 31) | |
411 | || (48 <= reg && reg <= 63)); | |
412 | } | |
413 | ||
414 | ||
415 | /* Return true if REG is an argument register, false otherwise. */ | |
416 | static int | |
417 | is_argument_reg (int reg) | |
418 | { | |
419 | return (8 <= reg && reg <= 13); | |
420 | } | |
421 | ||
456f8b9d DB |
422 | /* Scan an FR-V prologue, starting at PC, until frame->PC. |
423 | If FRAME is non-zero, fill in its saved_regs with appropriate addresses. | |
424 | We assume FRAME's saved_regs array has already been allocated and cleared. | |
425 | Return the first PC value after the prologue. | |
426 | ||
427 | Note that, for unoptimized code, we almost don't need this function | |
428 | at all; all arguments and locals live on the stack, so we just need | |
429 | the FP to find everything. The catch: structures passed by value | |
430 | have their addresses living in registers; they're never spilled to | |
431 | the stack. So if you ever want to be able to get to these | |
432 | arguments in any frame but the top, you'll need to do this serious | |
433 | prologue analysis. */ | |
434 | static CORE_ADDR | |
1cb761c7 KB |
435 | frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
436 | struct frv_unwind_cache *info) | |
456f8b9d DB |
437 | { |
438 | /* When writing out instruction bitpatterns, we use the following | |
439 | letters to label instruction fields: | |
440 | P - The parallel bit. We don't use this. | |
441 | J - The register number of GRj in the instruction description. | |
442 | K - The register number of GRk in the instruction description. | |
443 | I - The register number of GRi. | |
444 | S - a signed imediate offset. | |
445 | U - an unsigned immediate offset. | |
446 | ||
447 | The dots below the numbers indicate where hex digit boundaries | |
448 | fall, to make it easier to check the numbers. */ | |
449 | ||
450 | /* Non-zero iff we've seen the instruction that initializes the | |
451 | frame pointer for this function's frame. */ | |
452 | int fp_set = 0; | |
453 | ||
454 | /* If fp_set is non_zero, then this is the distance from | |
455 | the stack pointer to frame pointer: fp = sp + fp_offset. */ | |
456 | int fp_offset = 0; | |
457 | ||
458 | /* Total size of frame prior to any alloca operations. */ | |
459 | int framesize = 0; | |
460 | ||
1cb761c7 KB |
461 | /* Flag indicating if lr has been saved on the stack. */ |
462 | int lr_saved_on_stack = 0; | |
463 | ||
456f8b9d DB |
464 | /* The number of the general-purpose register we saved the return |
465 | address ("link register") in, or -1 if we haven't moved it yet. */ | |
466 | int lr_save_reg = -1; | |
467 | ||
1cb761c7 KB |
468 | /* Offset (from sp) at which lr has been saved on the stack. */ |
469 | ||
470 | int lr_sp_offset = 0; | |
456f8b9d DB |
471 | |
472 | /* If gr_saved[i] is non-zero, then we've noticed that general | |
473 | register i has been saved at gr_sp_offset[i] from the stack | |
474 | pointer. */ | |
475 | char gr_saved[64]; | |
476 | int gr_sp_offset[64]; | |
477 | ||
d40fcd7b KB |
478 | /* The address of the most recently scanned prologue instruction. */ |
479 | CORE_ADDR last_prologue_pc; | |
480 | ||
481 | /* The address of the next instruction. */ | |
482 | CORE_ADDR next_pc; | |
483 | ||
484 | /* The upper bound to of the pc values to scan. */ | |
485 | CORE_ADDR lim_pc; | |
486 | ||
456f8b9d DB |
487 | memset (gr_saved, 0, sizeof (gr_saved)); |
488 | ||
d40fcd7b KB |
489 | last_prologue_pc = pc; |
490 | ||
491 | /* Try to compute an upper limit (on how far to scan) based on the | |
492 | line number info. */ | |
493 | lim_pc = skip_prologue_using_sal (pc); | |
494 | /* If there's no line number info, lim_pc will be 0. In that case, | |
495 | set the limit to be 100 instructions away from pc. Hopefully, this | |
496 | will be far enough away to account for the entire prologue. Don't | |
497 | worry about overshooting the end of the function. The scan loop | |
498 | below contains some checks to avoid scanning unreasonably far. */ | |
499 | if (lim_pc == 0) | |
500 | lim_pc = pc + 400; | |
501 | ||
502 | /* If we have a frame, we don't want to scan past the frame's pc. This | |
503 | will catch those cases where the pc is in the prologue. */ | |
504 | if (next_frame) | |
505 | { | |
506 | CORE_ADDR frame_pc = frame_pc_unwind (next_frame); | |
507 | if (frame_pc < lim_pc) | |
508 | lim_pc = frame_pc; | |
509 | } | |
510 | ||
511 | /* Scan the prologue. */ | |
512 | while (pc < lim_pc) | |
456f8b9d | 513 | { |
1ccda5e9 KB |
514 | char buf[frv_instr_size]; |
515 | LONGEST op; | |
516 | ||
517 | if (target_read_memory (pc, buf, sizeof buf) != 0) | |
518 | break; | |
519 | op = extract_signed_integer (buf, sizeof buf); | |
520 | ||
d40fcd7b | 521 | next_pc = pc + 4; |
456f8b9d DB |
522 | |
523 | /* The tests in this chain of ifs should be in order of | |
524 | decreasing selectivity, so that more particular patterns get | |
525 | to fire before less particular patterns. */ | |
526 | ||
d40fcd7b KB |
527 | /* Some sort of control transfer instruction: stop scanning prologue. |
528 | Integer Conditional Branch: | |
529 | X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX | |
530 | Floating-point / media Conditional Branch: | |
531 | X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX | |
532 | LCR Conditional Branch to LR | |
533 | X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX | |
534 | Integer conditional Branches to LR | |
535 | X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX | |
536 | X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX | |
537 | Floating-point/Media Branches to LR | |
538 | X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX | |
539 | X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX | |
540 | Jump and Link | |
541 | X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX | |
542 | X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX | |
543 | Call | |
544 | X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX | |
545 | Return from Trap | |
546 | X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX | |
547 | Integer Conditional Trap | |
548 | X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX | |
549 | X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX | |
550 | Floating-point /media Conditional Trap | |
551 | X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX | |
552 | X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX | |
553 | Break | |
554 | X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX | |
555 | Media Trap | |
556 | X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */ | |
557 | if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */ | |
558 | || (op & 0x01f80000) == 0x00300000 /* Jump and Link */ | |
559 | || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */ | |
560 | || (op & 0x01f80000) == 0x00700000) /* Trap immediate */ | |
561 | { | |
562 | /* Stop scanning; not in prologue any longer. */ | |
563 | break; | |
564 | } | |
565 | ||
566 | /* Loading something from memory into fp probably means that | |
567 | we're in the epilogue. Stop scanning the prologue. | |
568 | ld @(GRi, GRk), fp | |
569 | X 000010 0000010 XXXXXX 000100 XXXXXX | |
570 | ldi @(GRi, d12), fp | |
571 | X 000010 0110010 XXXXXX XXXXXXXXXXXX */ | |
572 | else if ((op & 0x7ffc0fc0) == 0x04080100 | |
573 | || (op & 0x7ffc0000) == 0x04c80000) | |
574 | { | |
575 | break; | |
576 | } | |
577 | ||
456f8b9d DB |
578 | /* Setting the FP from the SP: |
579 | ori sp, 0, fp | |
580 | P 000010 0100010 000001 000000000000 = 0x04881000 | |
581 | 0 111111 1111111 111111 111111111111 = 0x7fffffff | |
582 | . . . . . . . . | |
583 | We treat this as part of the prologue. */ | |
d40fcd7b | 584 | else if ((op & 0x7fffffff) == 0x04881000) |
456f8b9d DB |
585 | { |
586 | fp_set = 1; | |
587 | fp_offset = 0; | |
d40fcd7b | 588 | last_prologue_pc = next_pc; |
456f8b9d DB |
589 | } |
590 | ||
591 | /* Move the link register to the scratch register grJ, before saving: | |
592 | movsg lr, grJ | |
593 | P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0 | |
594 | 0 111111 1111111 111111 111111 000000 = 0x7fffffc0 | |
595 | . . . . . . . . | |
596 | We treat this as part of the prologue. */ | |
597 | else if ((op & 0x7fffffc0) == 0x080d01c0) | |
598 | { | |
599 | int gr_j = op & 0x3f; | |
600 | ||
601 | /* If we're moving it to a scratch register, that's fine. */ | |
602 | if (is_caller_saves_reg (gr_j)) | |
d40fcd7b KB |
603 | { |
604 | lr_save_reg = gr_j; | |
605 | last_prologue_pc = next_pc; | |
606 | } | |
456f8b9d DB |
607 | } |
608 | ||
609 | /* To save multiple callee-saves registers on the stack, at | |
610 | offset zero: | |
611 | ||
612 | std grK,@(sp,gr0) | |
613 | P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0 | |
614 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
615 | ||
616 | stq grK,@(sp,gr0) | |
617 | P KKKKKK 0000011 000001 000100 000000 = 0x000c1100 | |
618 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
619 | . . . . . . . . | |
620 | We treat this as part of the prologue, and record the register's | |
621 | saved address in the frame structure. */ | |
622 | else if ((op & 0x01ffffff) == 0x000c10c0 | |
623 | || (op & 0x01ffffff) == 0x000c1100) | |
624 | { | |
625 | int gr_k = ((op >> 25) & 0x3f); | |
626 | int ope = ((op >> 6) & 0x3f); | |
627 | int count; | |
628 | int i; | |
629 | ||
630 | /* Is it an std or an stq? */ | |
631 | if (ope == 0x03) | |
632 | count = 2; | |
633 | else | |
634 | count = 4; | |
635 | ||
636 | /* Is it really a callee-saves register? */ | |
637 | if (is_callee_saves_reg (gr_k)) | |
638 | { | |
639 | for (i = 0; i < count; i++) | |
640 | { | |
641 | gr_saved[gr_k + i] = 1; | |
642 | gr_sp_offset[gr_k + i] = 4 * i; | |
643 | } | |
d40fcd7b | 644 | last_prologue_pc = next_pc; |
456f8b9d | 645 | } |
456f8b9d DB |
646 | } |
647 | ||
648 | /* Adjusting the stack pointer. (The stack pointer is GR1.) | |
649 | addi sp, S, sp | |
650 | P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000 | |
651 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
652 | . . . . . . . . | |
653 | We treat this as part of the prologue. */ | |
654 | else if ((op & 0x7ffff000) == 0x02401000) | |
655 | { | |
d40fcd7b KB |
656 | if (framesize == 0) |
657 | { | |
658 | /* Sign-extend the twelve-bit field. | |
659 | (Isn't there a better way to do this?) */ | |
660 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
456f8b9d | 661 | |
d40fcd7b KB |
662 | framesize -= s; |
663 | last_prologue_pc = pc; | |
664 | } | |
665 | else | |
666 | { | |
667 | /* If the prologue is being adjusted again, we've | |
668 | likely gone too far; i.e. we're probably in the | |
669 | epilogue. */ | |
670 | break; | |
671 | } | |
456f8b9d DB |
672 | } |
673 | ||
674 | /* Setting the FP to a constant distance from the SP: | |
675 | addi sp, S, fp | |
676 | P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000 | |
677 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
678 | . . . . . . . . | |
679 | We treat this as part of the prologue. */ | |
680 | else if ((op & 0x7ffff000) == 0x04401000) | |
681 | { | |
682 | /* Sign-extend the twelve-bit field. | |
683 | (Isn't there a better way to do this?) */ | |
684 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
685 | fp_set = 1; | |
686 | fp_offset = s; | |
d40fcd7b | 687 | last_prologue_pc = pc; |
456f8b9d DB |
688 | } |
689 | ||
690 | /* To spill an argument register to a scratch register: | |
691 | ori GRi, 0, GRk | |
692 | P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000 | |
693 | 0 000000 1111111 000000 111111111111 = 0x01fc0fff | |
694 | . . . . . . . . | |
695 | For the time being, we treat this as a prologue instruction, | |
696 | assuming that GRi is an argument register. This one's kind | |
697 | of suspicious, because it seems like it could be part of a | |
698 | legitimate body instruction. But we only come here when the | |
699 | source info wasn't helpful, so we have to do the best we can. | |
700 | Hopefully once GCC and GDB agree on how to emit line number | |
701 | info for prologues, then this code will never come into play. */ | |
702 | else if ((op & 0x01fc0fff) == 0x00880000) | |
703 | { | |
704 | int gr_i = ((op >> 12) & 0x3f); | |
705 | ||
d40fcd7b KB |
706 | /* Make sure that the source is an arg register; if it is, we'll |
707 | treat it as a prologue instruction. */ | |
708 | if (is_argument_reg (gr_i)) | |
709 | last_prologue_pc = next_pc; | |
456f8b9d DB |
710 | } |
711 | ||
712 | /* To spill 16-bit values to the stack: | |
713 | sthi GRk, @(fp, s) | |
714 | P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000 | |
715 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
716 | . . . . . . . . | |
717 | And for 8-bit values, we use STB instructions. | |
718 | stbi GRk, @(fp, s) | |
719 | P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000 | |
720 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
721 | . . . . . . . . | |
722 | We check that GRk is really an argument register, and treat | |
723 | all such as part of the prologue. */ | |
724 | else if ( (op & 0x01fff000) == 0x01442000 | |
725 | || (op & 0x01fff000) == 0x01402000) | |
726 | { | |
727 | int gr_k = ((op >> 25) & 0x3f); | |
728 | ||
d40fcd7b KB |
729 | /* Make sure that GRk is really an argument register; treat |
730 | it as a prologue instruction if so. */ | |
731 | if (is_argument_reg (gr_k)) | |
732 | last_prologue_pc = next_pc; | |
456f8b9d DB |
733 | } |
734 | ||
735 | /* To save multiple callee-saves register on the stack, at a | |
736 | non-zero offset: | |
737 | ||
738 | stdi GRk, @(sp, s) | |
739 | P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000 | |
740 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
741 | . . . . . . . . | |
742 | stqi GRk, @(sp, s) | |
743 | P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000 | |
744 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
745 | . . . . . . . . | |
746 | We treat this as part of the prologue, and record the register's | |
747 | saved address in the frame structure. */ | |
748 | else if ((op & 0x01fff000) == 0x014c1000 | |
749 | || (op & 0x01fff000) == 0x01501000) | |
750 | { | |
751 | int gr_k = ((op >> 25) & 0x3f); | |
752 | int count; | |
753 | int i; | |
754 | ||
755 | /* Is it a stdi or a stqi? */ | |
756 | if ((op & 0x01fff000) == 0x014c1000) | |
757 | count = 2; | |
758 | else | |
759 | count = 4; | |
760 | ||
761 | /* Is it really a callee-saves register? */ | |
762 | if (is_callee_saves_reg (gr_k)) | |
763 | { | |
764 | /* Sign-extend the twelve-bit field. | |
765 | (Isn't there a better way to do this?) */ | |
766 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
767 | ||
768 | for (i = 0; i < count; i++) | |
769 | { | |
770 | gr_saved[gr_k + i] = 1; | |
771 | gr_sp_offset[gr_k + i] = s + (4 * i); | |
772 | } | |
d40fcd7b | 773 | last_prologue_pc = next_pc; |
456f8b9d | 774 | } |
456f8b9d DB |
775 | } |
776 | ||
777 | /* Storing any kind of integer register at any constant offset | |
778 | from any other register. | |
779 | ||
780 | st GRk, @(GRi, gr0) | |
781 | P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080 | |
782 | 0 000000 1111111 000000 111111 111111 = 0x01fc0fff | |
783 | . . . . . . . . | |
784 | sti GRk, @(GRi, d12) | |
785 | P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000 | |
786 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 | |
787 | . . . . . . . . | |
788 | These could be almost anything, but a lot of prologue | |
789 | instructions fall into this pattern, so let's decode the | |
790 | instruction once, and then work at a higher level. */ | |
791 | else if (((op & 0x01fc0fff) == 0x000c0080) | |
792 | || ((op & 0x01fc0000) == 0x01480000)) | |
793 | { | |
794 | int gr_k = ((op >> 25) & 0x3f); | |
795 | int gr_i = ((op >> 12) & 0x3f); | |
796 | int offset; | |
797 | ||
798 | /* Are we storing with gr0 as an offset, or using an | |
799 | immediate value? */ | |
800 | if ((op & 0x01fc0fff) == 0x000c0080) | |
801 | offset = 0; | |
802 | else | |
803 | offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
804 | ||
805 | /* If the address isn't relative to the SP or FP, it's not a | |
806 | prologue instruction. */ | |
807 | if (gr_i != sp_regnum && gr_i != fp_regnum) | |
d40fcd7b KB |
808 | { |
809 | /* Do nothing; not a prologue instruction. */ | |
810 | } | |
456f8b9d DB |
811 | |
812 | /* Saving the old FP in the new frame (relative to the SP). */ | |
d40fcd7b | 813 | else if (gr_k == fp_regnum && gr_i == sp_regnum) |
1cb761c7 KB |
814 | { |
815 | gr_saved[fp_regnum] = 1; | |
816 | gr_sp_offset[fp_regnum] = offset; | |
d40fcd7b | 817 | last_prologue_pc = next_pc; |
1cb761c7 | 818 | } |
456f8b9d DB |
819 | |
820 | /* Saving callee-saves register(s) on the stack, relative to | |
821 | the SP. */ | |
822 | else if (gr_i == sp_regnum | |
823 | && is_callee_saves_reg (gr_k)) | |
824 | { | |
825 | gr_saved[gr_k] = 1; | |
1cb761c7 KB |
826 | if (gr_i == sp_regnum) |
827 | gr_sp_offset[gr_k] = offset; | |
828 | else | |
829 | gr_sp_offset[gr_k] = offset + fp_offset; | |
d40fcd7b | 830 | last_prologue_pc = next_pc; |
456f8b9d DB |
831 | } |
832 | ||
833 | /* Saving the scratch register holding the return address. */ | |
834 | else if (lr_save_reg != -1 | |
835 | && gr_k == lr_save_reg) | |
1cb761c7 KB |
836 | { |
837 | lr_saved_on_stack = 1; | |
838 | if (gr_i == sp_regnum) | |
839 | lr_sp_offset = offset; | |
840 | else | |
841 | lr_sp_offset = offset + fp_offset; | |
d40fcd7b | 842 | last_prologue_pc = next_pc; |
1cb761c7 | 843 | } |
456f8b9d DB |
844 | |
845 | /* Spilling int-sized arguments to the stack. */ | |
846 | else if (is_argument_reg (gr_k)) | |
d40fcd7b | 847 | last_prologue_pc = next_pc; |
456f8b9d | 848 | } |
d40fcd7b | 849 | pc = next_pc; |
456f8b9d DB |
850 | } |
851 | ||
1cb761c7 | 852 | if (next_frame && info) |
456f8b9d | 853 | { |
1cb761c7 KB |
854 | int i; |
855 | ULONGEST this_base; | |
456f8b9d DB |
856 | |
857 | /* If we know the relationship between the stack and frame | |
858 | pointers, record the addresses of the registers we noticed. | |
859 | Note that we have to do this as a separate step at the end, | |
860 | because instructions may save relative to the SP, but we need | |
861 | their addresses relative to the FP. */ | |
862 | if (fp_set) | |
1cb761c7 KB |
863 | frame_unwind_unsigned_register (next_frame, fp_regnum, &this_base); |
864 | else | |
865 | frame_unwind_unsigned_register (next_frame, sp_regnum, &this_base); | |
456f8b9d | 866 | |
1cb761c7 KB |
867 | for (i = 0; i < 64; i++) |
868 | if (gr_saved[i]) | |
869 | info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i]; | |
456f8b9d | 870 | |
1cb761c7 KB |
871 | info->prev_sp = this_base - fp_offset + framesize; |
872 | info->base = this_base; | |
873 | ||
874 | /* If LR was saved on the stack, record its location. */ | |
875 | if (lr_saved_on_stack) | |
876 | info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset; | |
877 | ||
878 | /* The call instruction moves the caller's PC in the callee's LR. | |
879 | Since this is an unwind, do the reverse. Copy the location of LR | |
880 | into PC (the address / regnum) so that a request for PC will be | |
881 | converted into a request for the LR. */ | |
882 | info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum]; | |
883 | ||
884 | /* Save the previous frame's computed SP value. */ | |
885 | trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp); | |
456f8b9d DB |
886 | } |
887 | ||
d40fcd7b | 888 | return last_prologue_pc; |
456f8b9d DB |
889 | } |
890 | ||
891 | ||
892 | static CORE_ADDR | |
893 | frv_skip_prologue (CORE_ADDR pc) | |
894 | { | |
895 | CORE_ADDR func_addr, func_end, new_pc; | |
896 | ||
897 | new_pc = pc; | |
898 | ||
899 | /* If the line table has entry for a line *within* the function | |
900 | (i.e., not in the prologue, and not past the end), then that's | |
901 | our location. */ | |
902 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
903 | { | |
904 | struct symtab_and_line sal; | |
905 | ||
906 | sal = find_pc_line (func_addr, 0); | |
907 | ||
908 | if (sal.line != 0 && sal.end < func_end) | |
909 | { | |
910 | new_pc = sal.end; | |
911 | } | |
912 | } | |
913 | ||
914 | /* The FR-V prologue is at least five instructions long (twenty bytes). | |
915 | If we didn't find a real source location past that, then | |
916 | do a full analysis of the prologue. */ | |
917 | if (new_pc < pc + 20) | |
1cb761c7 | 918 | new_pc = frv_analyze_prologue (pc, 0, 0); |
456f8b9d DB |
919 | |
920 | return new_pc; | |
921 | } | |
922 | ||
1cb761c7 KB |
923 | |
924 | static struct frv_unwind_cache * | |
925 | frv_frame_unwind_cache (struct frame_info *next_frame, | |
926 | void **this_prologue_cache) | |
456f8b9d | 927 | { |
1cb761c7 KB |
928 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
929 | CORE_ADDR pc; | |
1cb761c7 KB |
930 | ULONGEST this_base; |
931 | struct frv_unwind_cache *info; | |
8baa6f92 | 932 | |
1cb761c7 KB |
933 | if ((*this_prologue_cache)) |
934 | return (*this_prologue_cache); | |
456f8b9d | 935 | |
1cb761c7 KB |
936 | info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache); |
937 | (*this_prologue_cache) = info; | |
938 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
456f8b9d | 939 | |
1cb761c7 KB |
940 | /* Prologue analysis does the rest... */ |
941 | frv_analyze_prologue (frame_func_unwind (next_frame), next_frame, info); | |
456f8b9d | 942 | |
1cb761c7 | 943 | return info; |
456f8b9d DB |
944 | } |
945 | ||
456f8b9d | 946 | static void |
cd31fb03 KB |
947 | frv_extract_return_value (struct type *type, struct regcache *regcache, |
948 | void *valbuf) | |
456f8b9d | 949 | { |
cd31fb03 KB |
950 | int len = TYPE_LENGTH (type); |
951 | ||
952 | if (len <= 4) | |
953 | { | |
954 | ULONGEST gpr8_val; | |
955 | regcache_cooked_read_unsigned (regcache, 8, &gpr8_val); | |
956 | store_unsigned_integer (valbuf, len, gpr8_val); | |
957 | } | |
958 | else if (len == 8) | |
959 | { | |
960 | ULONGEST regval; | |
961 | regcache_cooked_read_unsigned (regcache, 8, ®val); | |
962 | store_unsigned_integer (valbuf, 4, regval); | |
963 | regcache_cooked_read_unsigned (regcache, 9, ®val); | |
964 | store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval); | |
965 | } | |
966 | else | |
967 | internal_error (__FILE__, __LINE__, "Illegal return value length: %d", len); | |
456f8b9d DB |
968 | } |
969 | ||
970 | static CORE_ADDR | |
cd31fb03 | 971 | frv_extract_struct_value_address (struct regcache *regcache) |
456f8b9d | 972 | { |
cd31fb03 KB |
973 | ULONGEST addr; |
974 | regcache_cooked_read_unsigned (regcache, struct_return_regnum, &addr); | |
975 | return addr; | |
456f8b9d DB |
976 | } |
977 | ||
978 | static void | |
979 | frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
980 | { | |
981 | write_register (struct_return_regnum, addr); | |
982 | } | |
983 | ||
984 | static int | |
985 | frv_frameless_function_invocation (struct frame_info *frame) | |
986 | { | |
19772a2c | 987 | return legacy_frameless_look_for_prologue (frame); |
456f8b9d DB |
988 | } |
989 | ||
1cb761c7 KB |
990 | static CORE_ADDR |
991 | frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
456f8b9d | 992 | { |
1cb761c7 | 993 | /* Require dword alignment. */ |
5b03f266 | 994 | return align_down (sp, 8); |
456f8b9d DB |
995 | } |
996 | ||
c4d10515 KB |
997 | static CORE_ADDR |
998 | find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point) | |
999 | { | |
1000 | CORE_ADDR descr; | |
1001 | char valbuf[4]; | |
1002 | ||
1003 | descr = frv_fdpic_find_canonical_descriptor (entry_point); | |
1004 | ||
1005 | if (descr != 0) | |
1006 | return descr; | |
1007 | ||
1008 | /* Construct a non-canonical descriptor from space allocated on | |
1009 | the stack. */ | |
1010 | ||
1011 | descr = value_as_long (value_allocate_space_in_inferior (8)); | |
1012 | store_unsigned_integer (valbuf, 4, entry_point); | |
1013 | write_memory (descr, valbuf, 4); | |
1014 | store_unsigned_integer (valbuf, 4, | |
1015 | frv_fdpic_find_global_pointer (entry_point)); | |
1016 | write_memory (descr + 4, valbuf, 4); | |
1017 | return descr; | |
1018 | } | |
1019 | ||
1020 | static CORE_ADDR | |
1021 | frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr, | |
1022 | struct target_ops *targ) | |
1023 | { | |
1024 | CORE_ADDR entry_point; | |
1025 | CORE_ADDR got_address; | |
1026 | ||
1027 | entry_point = get_target_memory_unsigned (targ, addr, 4); | |
1028 | got_address = get_target_memory_unsigned (targ, addr + 4, 4); | |
1029 | ||
1030 | if (got_address == frv_fdpic_find_global_pointer (entry_point)) | |
1031 | return entry_point; | |
1032 | else | |
1033 | return addr; | |
1034 | } | |
1035 | ||
456f8b9d | 1036 | static CORE_ADDR |
1cb761c7 KB |
1037 | frv_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1038 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1039 | int nargs, struct value **args, CORE_ADDR sp, | |
1040 | int struct_return, CORE_ADDR struct_addr) | |
456f8b9d DB |
1041 | { |
1042 | int argreg; | |
1043 | int argnum; | |
1044 | char *val; | |
1045 | char valbuf[4]; | |
1046 | struct value *arg; | |
1047 | struct type *arg_type; | |
1048 | int len; | |
1049 | enum type_code typecode; | |
1050 | CORE_ADDR regval; | |
1051 | int stack_space; | |
1052 | int stack_offset; | |
c4d10515 | 1053 | enum frv_abi abi = frv_abi (gdbarch); |
456f8b9d DB |
1054 | |
1055 | #if 0 | |
1056 | printf("Push %d args at sp = %x, struct_return=%d (%x)\n", | |
1057 | nargs, (int) sp, struct_return, struct_addr); | |
1058 | #endif | |
1059 | ||
1060 | stack_space = 0; | |
1061 | for (argnum = 0; argnum < nargs; ++argnum) | |
5b03f266 | 1062 | stack_space += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4); |
456f8b9d DB |
1063 | |
1064 | stack_space -= (6 * 4); | |
1065 | if (stack_space > 0) | |
1066 | sp -= stack_space; | |
1067 | ||
1068 | /* Make sure stack is dword aligned. */ | |
5b03f266 | 1069 | sp = align_down (sp, 8); |
456f8b9d DB |
1070 | |
1071 | stack_offset = 0; | |
1072 | ||
1073 | argreg = 8; | |
1074 | ||
1075 | if (struct_return) | |
1cb761c7 KB |
1076 | regcache_cooked_write_unsigned (regcache, struct_return_regnum, |
1077 | struct_addr); | |
456f8b9d DB |
1078 | |
1079 | for (argnum = 0; argnum < nargs; ++argnum) | |
1080 | { | |
1081 | arg = args[argnum]; | |
1082 | arg_type = check_typedef (VALUE_TYPE (arg)); | |
1083 | len = TYPE_LENGTH (arg_type); | |
1084 | typecode = TYPE_CODE (arg_type); | |
1085 | ||
1086 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
1087 | { | |
fbd9dcd3 | 1088 | store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg)); |
456f8b9d DB |
1089 | typecode = TYPE_CODE_PTR; |
1090 | len = 4; | |
1091 | val = valbuf; | |
1092 | } | |
c4d10515 KB |
1093 | else if (abi == FRV_ABI_FDPIC |
1094 | && len == 4 | |
1095 | && typecode == TYPE_CODE_PTR | |
1096 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
1097 | { | |
1098 | /* The FDPIC ABI requires function descriptors to be passed instead | |
1099 | of entry points. */ | |
1100 | store_unsigned_integer | |
1101 | (valbuf, 4, | |
1102 | find_func_descr (gdbarch, | |
1103 | extract_unsigned_integer (VALUE_CONTENTS (arg), | |
1104 | 4))); | |
1105 | typecode = TYPE_CODE_PTR; | |
1106 | len = 4; | |
1107 | val = valbuf; | |
1108 | } | |
456f8b9d DB |
1109 | else |
1110 | { | |
1111 | val = (char *) VALUE_CONTENTS (arg); | |
1112 | } | |
1113 | ||
1114 | while (len > 0) | |
1115 | { | |
1116 | int partial_len = (len < 4 ? len : 4); | |
1117 | ||
1118 | if (argreg < 14) | |
1119 | { | |
7c0b4a20 | 1120 | regval = extract_unsigned_integer (val, partial_len); |
456f8b9d DB |
1121 | #if 0 |
1122 | printf(" Argnum %d data %x -> reg %d\n", | |
1123 | argnum, (int) regval, argreg); | |
1124 | #endif | |
1cb761c7 | 1125 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
456f8b9d DB |
1126 | ++argreg; |
1127 | } | |
1128 | else | |
1129 | { | |
1130 | #if 0 | |
1131 | printf(" Argnum %d data %x -> offset %d (%x)\n", | |
1132 | argnum, *((int *)val), stack_offset, (int) (sp + stack_offset)); | |
1133 | #endif | |
1134 | write_memory (sp + stack_offset, val, partial_len); | |
5b03f266 | 1135 | stack_offset += align_up (partial_len, 4); |
456f8b9d DB |
1136 | } |
1137 | len -= partial_len; | |
1138 | val += partial_len; | |
1139 | } | |
1140 | } | |
456f8b9d | 1141 | |
1cb761c7 KB |
1142 | /* Set the return address. For the frv, the return breakpoint is |
1143 | always at BP_ADDR. */ | |
1144 | regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr); | |
1145 | ||
c4d10515 KB |
1146 | if (abi == FRV_ABI_FDPIC) |
1147 | { | |
1148 | /* Set the GOT register for the FDPIC ABI. */ | |
1149 | regcache_cooked_write_unsigned | |
1150 | (regcache, first_gpr_regnum + 15, | |
1151 | frv_fdpic_find_global_pointer (func_addr)); | |
1152 | } | |
1153 | ||
1cb761c7 KB |
1154 | /* Finally, update the SP register. */ |
1155 | regcache_cooked_write_unsigned (regcache, sp_regnum, sp); | |
1156 | ||
456f8b9d DB |
1157 | return sp; |
1158 | } | |
1159 | ||
1160 | static void | |
cd31fb03 KB |
1161 | frv_store_return_value (struct type *type, struct regcache *regcache, |
1162 | const void *valbuf) | |
456f8b9d | 1163 | { |
cd31fb03 KB |
1164 | int len = TYPE_LENGTH (type); |
1165 | ||
1166 | if (len <= 4) | |
1167 | { | |
1168 | bfd_byte val[4]; | |
1169 | memset (val, 0, sizeof (val)); | |
1170 | memcpy (val + (4 - len), valbuf, len); | |
1171 | regcache_cooked_write (regcache, 8, val); | |
1172 | } | |
1173 | else if (len == 8) | |
1174 | { | |
1175 | regcache_cooked_write (regcache, 8, valbuf); | |
1176 | regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4); | |
1177 | } | |
456f8b9d DB |
1178 | else |
1179 | internal_error (__FILE__, __LINE__, | |
cd31fb03 | 1180 | "Don't know how to return a %d-byte value.", len); |
456f8b9d DB |
1181 | } |
1182 | ||
456f8b9d | 1183 | |
456f8b9d DB |
1184 | /* Hardware watchpoint / breakpoint support for the FR500 |
1185 | and FR400. */ | |
1186 | ||
1187 | int | |
1188 | frv_check_watch_resources (int type, int cnt, int ot) | |
1189 | { | |
1190 | struct gdbarch_tdep *var = CURRENT_VARIANT; | |
1191 | ||
1192 | /* Watchpoints not supported on simulator. */ | |
1193 | if (strcmp (target_shortname, "sim") == 0) | |
1194 | return 0; | |
1195 | ||
1196 | if (type == bp_hardware_breakpoint) | |
1197 | { | |
1198 | if (var->num_hw_breakpoints == 0) | |
1199 | return 0; | |
1200 | else if (cnt <= var->num_hw_breakpoints) | |
1201 | return 1; | |
1202 | } | |
1203 | else | |
1204 | { | |
1205 | if (var->num_hw_watchpoints == 0) | |
1206 | return 0; | |
1207 | else if (ot) | |
1208 | return -1; | |
1209 | else if (cnt <= var->num_hw_watchpoints) | |
1210 | return 1; | |
1211 | } | |
1212 | return -1; | |
1213 | } | |
1214 | ||
1215 | ||
1216 | CORE_ADDR | |
5ae5f592 | 1217 | frv_stopped_data_address (void) |
456f8b9d DB |
1218 | { |
1219 | CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3; | |
1220 | ||
1221 | brr = read_register (brr_regnum); | |
1222 | dbar0 = read_register (dbar0_regnum); | |
1223 | dbar1 = read_register (dbar1_regnum); | |
1224 | dbar2 = read_register (dbar2_regnum); | |
1225 | dbar3 = read_register (dbar3_regnum); | |
1226 | ||
1227 | if (brr & (1<<11)) | |
1228 | return dbar0; | |
1229 | else if (brr & (1<<10)) | |
1230 | return dbar1; | |
1231 | else if (brr & (1<<9)) | |
1232 | return dbar2; | |
1233 | else if (brr & (1<<8)) | |
1234 | return dbar3; | |
1235 | else | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1cb761c7 KB |
1239 | static CORE_ADDR |
1240 | frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1241 | { | |
1242 | return frame_unwind_register_unsigned (next_frame, pc_regnum); | |
1243 | } | |
1244 | ||
1245 | /* Given a GDB frame, determine the address of the calling function's | |
1246 | frame. This will be used to create a new GDB frame struct. */ | |
1247 | ||
1248 | static void | |
1249 | frv_frame_this_id (struct frame_info *next_frame, | |
1250 | void **this_prologue_cache, struct frame_id *this_id) | |
1251 | { | |
1252 | struct frv_unwind_cache *info | |
1253 | = frv_frame_unwind_cache (next_frame, this_prologue_cache); | |
1254 | CORE_ADDR base; | |
1255 | CORE_ADDR func; | |
1256 | struct minimal_symbol *msym_stack; | |
1257 | struct frame_id id; | |
1258 | ||
1259 | /* The FUNC is easy. */ | |
1260 | func = frame_func_unwind (next_frame); | |
1261 | ||
1cb761c7 KB |
1262 | /* Check if the stack is empty. */ |
1263 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
1264 | if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) | |
1265 | return; | |
1266 | ||
1267 | /* Hopefully the prologue analysis either correctly determined the | |
1268 | frame's base (which is the SP from the previous frame), or set | |
1269 | that base to "NULL". */ | |
1270 | base = info->prev_sp; | |
1271 | if (base == 0) | |
1272 | return; | |
1273 | ||
1274 | id = frame_id_build (base, func); | |
1275 | ||
1276 | /* Check that we're not going round in circles with the same frame | |
1277 | ID (but avoid applying the test to sentinel frames which do go | |
1278 | round in circles). Can't use frame_id_eq() as that doesn't yet | |
1279 | compare the frame's PC value. */ | |
1280 | if (frame_relative_level (next_frame) >= 0 | |
1281 | && get_frame_type (next_frame) != DUMMY_FRAME | |
1282 | && frame_id_eq (get_frame_id (next_frame), id)) | |
1283 | return; | |
1284 | ||
1285 | (*this_id) = id; | |
1286 | } | |
1287 | ||
1288 | static void | |
1289 | frv_frame_prev_register (struct frame_info *next_frame, | |
1290 | void **this_prologue_cache, | |
1291 | int regnum, int *optimizedp, | |
1292 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1293 | int *realnump, void *bufferp) | |
1294 | { | |
1295 | struct frv_unwind_cache *info | |
1296 | = frv_frame_unwind_cache (next_frame, this_prologue_cache); | |
1297 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
1298 | optimizedp, lvalp, addrp, realnump, bufferp); | |
1299 | } | |
1300 | ||
1301 | static const struct frame_unwind frv_frame_unwind = { | |
1302 | NORMAL_FRAME, | |
1303 | frv_frame_this_id, | |
1304 | frv_frame_prev_register | |
1305 | }; | |
1306 | ||
1307 | static const struct frame_unwind * | |
1308 | frv_frame_sniffer (struct frame_info *next_frame) | |
1309 | { | |
1310 | return &frv_frame_unwind; | |
1311 | } | |
1312 | ||
1313 | static CORE_ADDR | |
1314 | frv_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1315 | { | |
1316 | struct frv_unwind_cache *info | |
1317 | = frv_frame_unwind_cache (next_frame, this_cache); | |
1318 | return info->base; | |
1319 | } | |
1320 | ||
1321 | static const struct frame_base frv_frame_base = { | |
1322 | &frv_frame_unwind, | |
1323 | frv_frame_base_address, | |
1324 | frv_frame_base_address, | |
1325 | frv_frame_base_address | |
1326 | }; | |
1327 | ||
1328 | static CORE_ADDR | |
1329 | frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1330 | { | |
1331 | return frame_unwind_register_unsigned (next_frame, sp_regnum); | |
1332 | } | |
1333 | ||
1334 | ||
1335 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
1336 | dummy frame. The frame ID's base needs to match the TOS value | |
1337 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1338 | breakpoint. */ | |
1339 | ||
1340 | static struct frame_id | |
1341 | frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1342 | { | |
1343 | return frame_id_build (frv_unwind_sp (gdbarch, next_frame), | |
1344 | frame_pc_unwind (next_frame)); | |
1345 | } | |
1346 | ||
1347 | ||
456f8b9d DB |
1348 | static struct gdbarch * |
1349 | frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1350 | { | |
1351 | struct gdbarch *gdbarch; | |
1352 | struct gdbarch_tdep *var; | |
7e295833 | 1353 | int elf_flags = 0; |
456f8b9d DB |
1354 | |
1355 | /* Check to see if we've already built an appropriate architecture | |
1356 | object for this executable. */ | |
1357 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1358 | if (arches) | |
1359 | return arches->gdbarch; | |
1360 | ||
1361 | /* Select the right tdep structure for this variant. */ | |
1362 | var = new_variant (); | |
1363 | switch (info.bfd_arch_info->mach) | |
1364 | { | |
1365 | case bfd_mach_frv: | |
1366 | case bfd_mach_frvsimple: | |
1367 | case bfd_mach_fr500: | |
1368 | case bfd_mach_frvtomcat: | |
251a3ae3 | 1369 | case bfd_mach_fr550: |
456f8b9d DB |
1370 | set_variant_num_gprs (var, 64); |
1371 | set_variant_num_fprs (var, 64); | |
1372 | break; | |
1373 | ||
1374 | case bfd_mach_fr400: | |
b2d6d697 | 1375 | case bfd_mach_fr450: |
456f8b9d DB |
1376 | set_variant_num_gprs (var, 32); |
1377 | set_variant_num_fprs (var, 32); | |
1378 | break; | |
1379 | ||
1380 | default: | |
1381 | /* Never heard of this variant. */ | |
1382 | return 0; | |
1383 | } | |
7e295833 KB |
1384 | |
1385 | /* Extract the ELF flags, if available. */ | |
1386 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1387 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1388 | ||
1389 | if (elf_flags & EF_FRV_FDPIC) | |
1390 | set_variant_abi_fdpic (var); | |
1391 | ||
b2d6d697 KB |
1392 | if (elf_flags & EF_FRV_CPU_FR450) |
1393 | set_variant_scratch_registers (var); | |
1394 | ||
456f8b9d DB |
1395 | gdbarch = gdbarch_alloc (&info, var); |
1396 | ||
1397 | set_gdbarch_short_bit (gdbarch, 16); | |
1398 | set_gdbarch_int_bit (gdbarch, 32); | |
1399 | set_gdbarch_long_bit (gdbarch, 32); | |
1400 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1401 | set_gdbarch_float_bit (gdbarch, 32); | |
1402 | set_gdbarch_double_bit (gdbarch, 64); | |
1403 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1404 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1405 | ||
1406 | set_gdbarch_num_regs (gdbarch, frv_num_regs); | |
6a748db6 KB |
1407 | set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs); |
1408 | ||
456f8b9d | 1409 | set_gdbarch_sp_regnum (gdbarch, sp_regnum); |
0ba6dca9 | 1410 | set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum); |
456f8b9d DB |
1411 | set_gdbarch_pc_regnum (gdbarch, pc_regnum); |
1412 | ||
1413 | set_gdbarch_register_name (gdbarch, frv_register_name); | |
7f398216 | 1414 | set_gdbarch_register_type (gdbarch, frv_register_type); |
526eef89 | 1415 | set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno); |
456f8b9d | 1416 | |
6a748db6 KB |
1417 | set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read); |
1418 | set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write); | |
1419 | ||
456f8b9d DB |
1420 | set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue); |
1421 | set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc); | |
46a16dba | 1422 | set_gdbarch_adjust_breakpoint_address (gdbarch, frv_gdbarch_adjust_breakpoint_address); |
456f8b9d | 1423 | |
19772a2c | 1424 | set_gdbarch_deprecated_frameless_function_invocation (gdbarch, frv_frameless_function_invocation); |
456f8b9d | 1425 | |
1fd35568 | 1426 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
cd31fb03 | 1427 | set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value); |
456f8b9d | 1428 | |
4183d812 | 1429 | set_gdbarch_deprecated_store_struct_return (gdbarch, frv_store_struct_return); |
cd31fb03 | 1430 | set_gdbarch_store_return_value (gdbarch, frv_store_return_value); |
74055713 | 1431 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, frv_extract_struct_value_address); |
456f8b9d | 1432 | |
1cb761c7 KB |
1433 | /* Frame stuff. */ |
1434 | set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc); | |
1435 | set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp); | |
1436 | set_gdbarch_frame_align (gdbarch, frv_frame_align); | |
1437 | frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer); | |
1438 | frame_base_set_default (gdbarch, &frv_frame_base); | |
456f8b9d | 1439 | |
1cb761c7 KB |
1440 | /* Settings for calling functions in the inferior. */ |
1441 | set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call); | |
1442 | set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id); | |
456f8b9d DB |
1443 | |
1444 | /* Settings that should be unnecessary. */ | |
1445 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1446 | ||
456f8b9d | 1447 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
456f8b9d | 1448 | |
456f8b9d | 1449 | set_gdbarch_remote_translate_xfer_address |
aed7f26a | 1450 | (gdbarch, generic_remote_translate_xfer_address); |
456f8b9d DB |
1451 | |
1452 | /* Hardware watchpoint / breakpoint support. */ | |
1453 | switch (info.bfd_arch_info->mach) | |
1454 | { | |
1455 | case bfd_mach_frv: | |
1456 | case bfd_mach_frvsimple: | |
1457 | case bfd_mach_fr500: | |
1458 | case bfd_mach_frvtomcat: | |
1459 | /* fr500-style hardware debugging support. */ | |
1460 | var->num_hw_watchpoints = 4; | |
1461 | var->num_hw_breakpoints = 4; | |
1462 | break; | |
1463 | ||
1464 | case bfd_mach_fr400: | |
b2d6d697 | 1465 | case bfd_mach_fr450: |
456f8b9d DB |
1466 | /* fr400-style hardware debugging support. */ |
1467 | var->num_hw_watchpoints = 2; | |
1468 | var->num_hw_breakpoints = 4; | |
1469 | break; | |
1470 | ||
1471 | default: | |
1472 | /* Otherwise, assume we don't have hardware debugging support. */ | |
1473 | var->num_hw_watchpoints = 0; | |
1474 | var->num_hw_breakpoints = 0; | |
1475 | break; | |
1476 | } | |
1477 | ||
36482093 | 1478 | set_gdbarch_print_insn (gdbarch, print_insn_frv); |
c4d10515 KB |
1479 | if (frv_abi (gdbarch) == FRV_ABI_FDPIC) |
1480 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, | |
1481 | frv_convert_from_func_ptr_addr); | |
36482093 | 1482 | |
456f8b9d DB |
1483 | return gdbarch; |
1484 | } | |
1485 | ||
1486 | void | |
1487 | _initialize_frv_tdep (void) | |
1488 | { | |
1489 | register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init); | |
456f8b9d | 1490 | } |