2004-02-16 Andrew Cagney <cagney@redhat.com>
[deliverable/binutils-gdb.git] / gdb / frv-tdep.c
CommitLineData
456f8b9d 1/* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
9ab9195f 2 Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
456f8b9d
DB
3
4 This file is part of GDB.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21#include "defs.h"
8baa6f92 22#include "gdb_string.h"
456f8b9d 23#include "inferior.h"
456f8b9d
DB
24#include "gdbcore.h"
25#include "arch-utils.h"
26#include "regcache.h"
8baa6f92 27#include "frame.h"
1cb761c7
KB
28#include "frame-unwind.h"
29#include "frame-base.h"
8baa6f92 30#include "trad-frame.h"
dcc6aaff 31#include "dis-asm.h"
526eef89
KB
32#include "gdb_assert.h"
33#include "sim-regno.h"
34#include "gdb/sim-frv.h"
35#include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
456f8b9d
DB
36
37extern void _initialize_frv_tdep (void);
38
39static gdbarch_init_ftype frv_gdbarch_init;
40
41static gdbarch_register_name_ftype frv_register_name;
456f8b9d 42static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc;
46a16dba 43static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address;
456f8b9d 44static gdbarch_skip_prologue_ftype frv_skip_prologue;
456f8b9d 45static gdbarch_frameless_function_invocation_ftype frv_frameless_function_invocation;
456f8b9d 46
526eef89
KB
47/* Register numbers. The order in which these appear define the
48 remote protocol, so take care in changing them. */
456f8b9d 49enum {
456f8b9d
DB
50 /* Register numbers 0 -- 63 are always reserved for general-purpose
51 registers. The chip at hand may have less. */
52 first_gpr_regnum = 0,
53 sp_regnum = 1,
54 fp_regnum = 2,
55 struct_return_regnum = 3,
56 last_gpr_regnum = 63,
57
58 /* Register numbers 64 -- 127 are always reserved for floating-point
59 registers. The chip at hand may have less. */
60 first_fpr_regnum = 64,
61 last_fpr_regnum = 127,
62
526eef89 63 /* The PC register. */
456f8b9d 64 pc_regnum = 128,
526eef89
KB
65
66 /* Register numbers 129 on up are always reserved for special-purpose
67 registers. */
68 first_spr_regnum = 129,
456f8b9d
DB
69 psr_regnum = 129,
70 ccr_regnum = 130,
71 cccr_regnum = 131,
72 tbr_regnum = 135,
73 brr_regnum = 136,
74 dbar0_regnum = 137,
75 dbar1_regnum = 138,
76 dbar2_regnum = 139,
77 dbar3_regnum = 140,
78 lr_regnum = 145,
79 lcr_regnum = 146,
526eef89
KB
80 iacc0h_regnum = 147,
81 iacc0l_regnum = 148,
82 last_spr_regnum = 148,
83
84 /* The total number of registers we know exist. */
6a748db6
KB
85 frv_num_regs = last_spr_regnum + 1,
86
87 /* Pseudo registers */
88 first_pseudo_regnum = frv_num_regs,
89
90 /* iacc0 - the 64-bit concatenation of iacc0h and iacc0l. */
91 iacc0_regnum = first_pseudo_regnum + 0,
92
93 last_pseudo_regnum = iacc0_regnum,
65ed7f0a 94 frv_num_pseudo_regs = last_pseudo_regnum - first_pseudo_regnum + 1,
456f8b9d
DB
95};
96
97static LONGEST frv_call_dummy_words[] =
98{0};
99
100
1cb761c7 101struct frv_unwind_cache /* was struct frame_extra_info */
456f8b9d 102 {
1cb761c7
KB
103 /* The previous frame's inner-most stack address. Used as this
104 frame ID's stack_addr. */
105 CORE_ADDR prev_sp;
456f8b9d 106
1cb761c7
KB
107 /* The frame's base, optionally used by the high-level debug info. */
108 CORE_ADDR base;
8baa6f92
KB
109
110 /* Table indicating the location of each and every register. */
111 struct trad_frame_saved_reg *saved_regs;
456f8b9d
DB
112 };
113
114
115/* A structure describing a particular variant of the FRV.
116 We allocate and initialize one of these structures when we create
117 the gdbarch object for a variant.
118
119 At the moment, all the FR variants we support differ only in which
120 registers are present; the portable code of GDB knows that
121 registers whose names are the empty string don't exist, so the
122 `register_names' array captures all the per-variant information we
123 need.
124
125 in the future, if we need to have per-variant maps for raw size,
126 virtual type, etc., we should replace register_names with an array
127 of structures, each of which gives all the necessary info for one
128 register. Don't stick parallel arrays in here --- that's so
129 Fortran. */
130struct gdbarch_tdep
131{
132 /* How many general-purpose registers does this variant have? */
133 int num_gprs;
134
135 /* How many floating-point registers does this variant have? */
136 int num_fprs;
137
138 /* How many hardware watchpoints can it support? */
139 int num_hw_watchpoints;
140
141 /* How many hardware breakpoints can it support? */
142 int num_hw_breakpoints;
143
144 /* Register names. */
145 char **register_names;
146};
147
148#define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch))
149
150
151/* Allocate a new variant structure, and set up default values for all
152 the fields. */
153static struct gdbarch_tdep *
5ae5f592 154new_variant (void)
456f8b9d
DB
155{
156 struct gdbarch_tdep *var;
157 int r;
158 char buf[20];
159
160 var = xmalloc (sizeof (*var));
161 memset (var, 0, sizeof (*var));
162
163 var->num_gprs = 64;
164 var->num_fprs = 64;
165 var->num_hw_watchpoints = 0;
166 var->num_hw_breakpoints = 0;
167
168 /* By default, don't supply any general-purpose or floating-point
169 register names. */
6a748db6
KB
170 var->register_names
171 = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs)
172 * sizeof (char *));
173 for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++)
456f8b9d
DB
174 var->register_names[r] = "";
175
526eef89 176 /* Do, however, supply default names for the known special-purpose
456f8b9d 177 registers. */
456f8b9d
DB
178
179 var->register_names[pc_regnum] = "pc";
180 var->register_names[lr_regnum] = "lr";
181 var->register_names[lcr_regnum] = "lcr";
182
183 var->register_names[psr_regnum] = "psr";
184 var->register_names[ccr_regnum] = "ccr";
185 var->register_names[cccr_regnum] = "cccr";
186 var->register_names[tbr_regnum] = "tbr";
187
188 /* Debug registers. */
189 var->register_names[brr_regnum] = "brr";
190 var->register_names[dbar0_regnum] = "dbar0";
191 var->register_names[dbar1_regnum] = "dbar1";
192 var->register_names[dbar2_regnum] = "dbar2";
193 var->register_names[dbar3_regnum] = "dbar3";
194
526eef89
KB
195 /* iacc0 (Only found on MB93405.) */
196 var->register_names[iacc0h_regnum] = "iacc0h";
197 var->register_names[iacc0l_regnum] = "iacc0l";
6a748db6 198 var->register_names[iacc0_regnum] = "iacc0";
526eef89 199
456f8b9d
DB
200 return var;
201}
202
203
204/* Indicate that the variant VAR has NUM_GPRS general-purpose
205 registers, and fill in the names array appropriately. */
206static void
207set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)
208{
209 int r;
210
211 var->num_gprs = num_gprs;
212
213 for (r = 0; r < num_gprs; ++r)
214 {
215 char buf[20];
216
217 sprintf (buf, "gr%d", r);
218 var->register_names[first_gpr_regnum + r] = xstrdup (buf);
219 }
220}
221
222
223/* Indicate that the variant VAR has NUM_FPRS floating-point
224 registers, and fill in the names array appropriately. */
225static void
226set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)
227{
228 int r;
229
230 var->num_fprs = num_fprs;
231
232 for (r = 0; r < num_fprs; ++r)
233 {
234 char buf[20];
235
236 sprintf (buf, "fr%d", r);
237 var->register_names[first_fpr_regnum + r] = xstrdup (buf);
238 }
239}
240
241
242static const char *
243frv_register_name (int reg)
244{
245 if (reg < 0)
246 return "?toosmall?";
6a748db6 247 if (reg >= frv_num_regs + frv_num_pseudo_regs)
456f8b9d
DB
248 return "?toolarge?";
249
250 return CURRENT_VARIANT->register_names[reg];
251}
252
526eef89 253
456f8b9d 254static struct type *
7f398216 255frv_register_type (struct gdbarch *gdbarch, int reg)
456f8b9d 256{
526eef89 257 if (reg >= first_fpr_regnum && reg <= last_fpr_regnum)
456f8b9d 258 return builtin_type_float;
6a748db6
KB
259 else if (reg == iacc0_regnum)
260 return builtin_type_int64;
456f8b9d 261 else
526eef89 262 return builtin_type_int32;
456f8b9d
DB
263}
264
6a748db6
KB
265static void
266frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
267 int reg, void *buffer)
268{
269 if (reg == iacc0_regnum)
270 {
271 regcache_raw_read (regcache, iacc0h_regnum, buffer);
272 regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
273 }
274}
275
276static void
277frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
278 int reg, const void *buffer)
279{
280 if (reg == iacc0_regnum)
281 {
282 regcache_raw_write (regcache, iacc0h_regnum, buffer);
283 regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
284 }
285}
286
526eef89
KB
287static int
288frv_register_sim_regno (int reg)
289{
290 static const int spr_map[] =
291 {
292 H_SPR_PSR, /* psr_regnum */
293 H_SPR_CCR, /* ccr_regnum */
294 H_SPR_CCCR, /* cccr_regnum */
295 -1, /* 132 */
296 -1, /* 133 */
297 -1, /* 134 */
298 H_SPR_TBR, /* tbr_regnum */
299 H_SPR_BRR, /* brr_regnum */
300 H_SPR_DBAR0, /* dbar0_regnum */
301 H_SPR_DBAR1, /* dbar1_regnum */
302 H_SPR_DBAR2, /* dbar2_regnum */
303 H_SPR_DBAR3, /* dbar3_regnum */
304 -1, /* 141 */
305 -1, /* 142 */
306 -1, /* 143 */
307 -1, /* 144 */
308 H_SPR_LR, /* lr_regnum */
309 H_SPR_LCR, /* lcr_regnum */
310 H_SPR_IACC0H, /* iacc0h_regnum */
311 H_SPR_IACC0L /* iacc0l_regnum */
312 };
313
314 gdb_assert (reg >= 0 && reg < NUM_REGS);
315
316 if (first_gpr_regnum <= reg && reg <= last_gpr_regnum)
317 return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM;
318 else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum)
319 return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM;
320 else if (pc_regnum == reg)
321 return SIM_FRV_PC_REGNUM;
322 else if (reg >= first_spr_regnum
323 && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0]))
324 {
325 int spr_reg_offset = spr_map[reg - first_spr_regnum];
326
327 if (spr_reg_offset < 0)
328 return SIM_REGNO_DOES_NOT_EXIST;
329 else
330 return SIM_FRV_SPR0_REGNUM + spr_reg_offset;
331 }
332
333 internal_error (__FILE__, __LINE__, "Bad register number %d", reg);
334}
335
456f8b9d
DB
336static const unsigned char *
337frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp)
338{
339 static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};
340 *lenp = sizeof (breakpoint);
341 return breakpoint;
342}
343
46a16dba
KB
344/* Define the maximum number of instructions which may be packed into a
345 bundle (VLIW instruction). */
346static const int max_instrs_per_bundle = 8;
347
348/* Define the size (in bytes) of an FR-V instruction. */
349static const int frv_instr_size = 4;
350
351/* Adjust a breakpoint's address to account for the FR-V architecture's
352 constraint that a break instruction must not appear as any but the
353 first instruction in the bundle. */
354static CORE_ADDR
355frv_gdbarch_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
356{
357 int count = max_instrs_per_bundle;
358 CORE_ADDR addr = bpaddr - frv_instr_size;
359 CORE_ADDR func_start = get_pc_function_start (bpaddr);
360
361 /* Find the end of the previous packing sequence. This will be indicated
362 by either attempting to access some inaccessible memory or by finding
363 an instruction word whose packing bit is set to one. */
364 while (count-- > 0 && addr >= func_start)
365 {
366 char instr[frv_instr_size];
367 int status;
368
369 status = read_memory_nobpt (addr, instr, sizeof instr);
370
371 if (status != 0)
372 break;
373
374 /* This is a big endian architecture, so byte zero will have most
375 significant byte. The most significant bit of this byte is the
376 packing bit. */
377 if (instr[0] & 0x80)
378 break;
379
380 addr -= frv_instr_size;
381 }
382
383 if (count > 0)
384 bpaddr = addr + frv_instr_size;
385
386 return bpaddr;
387}
388
456f8b9d
DB
389
390/* Return true if REG is a caller-saves ("scratch") register,
391 false otherwise. */
392static int
393is_caller_saves_reg (int reg)
394{
395 return ((4 <= reg && reg <= 7)
396 || (14 <= reg && reg <= 15)
397 || (32 <= reg && reg <= 47));
398}
399
400
401/* Return true if REG is a callee-saves register, false otherwise. */
402static int
403is_callee_saves_reg (int reg)
404{
405 return ((16 <= reg && reg <= 31)
406 || (48 <= reg && reg <= 63));
407}
408
409
410/* Return true if REG is an argument register, false otherwise. */
411static int
412is_argument_reg (int reg)
413{
414 return (8 <= reg && reg <= 13);
415}
416
d40fcd7b
KB
417/* Given PC at the function's start address, attempt to find the
418 prologue end using SAL information. Return zero if the skip fails.
419
420 A non-optimized prologue traditionally has one SAL for the function
421 and a second for the function body. A single line function has
422 them both pointing at the same line.
423
424 An optimized prologue is similar but the prologue may contain
425 instructions (SALs) from the instruction body. Need to skip those
426 while not getting into the function body.
427
428 The functions end point and an increasing SAL line are used as
429 indicators of the prologue's endpoint.
430
431 This code is based on the function refine_prologue_limit (versions
432 found in both ia64 and ppc). */
433
434static CORE_ADDR
435skip_prologue_using_sal (CORE_ADDR func_addr)
436{
437 struct symtab_and_line prologue_sal;
438 CORE_ADDR start_pc;
439 CORE_ADDR end_pc;
440
441 /* Get an initial range for the function. */
442 find_pc_partial_function (func_addr, NULL, &start_pc, &end_pc);
443 start_pc += FUNCTION_START_OFFSET;
444
445 prologue_sal = find_pc_line (start_pc, 0);
446 if (prologue_sal.line != 0)
447 {
448 while (prologue_sal.end < end_pc)
449 {
450 struct symtab_and_line sal;
451
452 sal = find_pc_line (prologue_sal.end, 0);
453 if (sal.line == 0)
454 break;
455 /* Assume that a consecutive SAL for the same (or larger)
456 line mark the prologue -> body transition. */
457 if (sal.line >= prologue_sal.line)
458 break;
459 /* The case in which compiler's optimizer/scheduler has
460 moved instructions into the prologue. We look ahead in
461 the function looking for address ranges whose
462 corresponding line number is less the first one that we
463 found for the function. This is more conservative then
464 refine_prologue_limit which scans a large number of SALs
465 looking for any in the prologue */
466 prologue_sal = sal;
467 }
468 }
469 return prologue_sal.end;
470}
471
456f8b9d
DB
472
473/* Scan an FR-V prologue, starting at PC, until frame->PC.
474 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
475 We assume FRAME's saved_regs array has already been allocated and cleared.
476 Return the first PC value after the prologue.
477
478 Note that, for unoptimized code, we almost don't need this function
479 at all; all arguments and locals live on the stack, so we just need
480 the FP to find everything. The catch: structures passed by value
481 have their addresses living in registers; they're never spilled to
482 the stack. So if you ever want to be able to get to these
483 arguments in any frame but the top, you'll need to do this serious
484 prologue analysis. */
485static CORE_ADDR
1cb761c7
KB
486frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame,
487 struct frv_unwind_cache *info)
456f8b9d
DB
488{
489 /* When writing out instruction bitpatterns, we use the following
490 letters to label instruction fields:
491 P - The parallel bit. We don't use this.
492 J - The register number of GRj in the instruction description.
493 K - The register number of GRk in the instruction description.
494 I - The register number of GRi.
495 S - a signed imediate offset.
496 U - an unsigned immediate offset.
497
498 The dots below the numbers indicate where hex digit boundaries
499 fall, to make it easier to check the numbers. */
500
501 /* Non-zero iff we've seen the instruction that initializes the
502 frame pointer for this function's frame. */
503 int fp_set = 0;
504
505 /* If fp_set is non_zero, then this is the distance from
506 the stack pointer to frame pointer: fp = sp + fp_offset. */
507 int fp_offset = 0;
508
509 /* Total size of frame prior to any alloca operations. */
510 int framesize = 0;
511
1cb761c7
KB
512 /* Flag indicating if lr has been saved on the stack. */
513 int lr_saved_on_stack = 0;
514
456f8b9d
DB
515 /* The number of the general-purpose register we saved the return
516 address ("link register") in, or -1 if we haven't moved it yet. */
517 int lr_save_reg = -1;
518
1cb761c7
KB
519 /* Offset (from sp) at which lr has been saved on the stack. */
520
521 int lr_sp_offset = 0;
456f8b9d
DB
522
523 /* If gr_saved[i] is non-zero, then we've noticed that general
524 register i has been saved at gr_sp_offset[i] from the stack
525 pointer. */
526 char gr_saved[64];
527 int gr_sp_offset[64];
528
d40fcd7b
KB
529 /* The address of the most recently scanned prologue instruction. */
530 CORE_ADDR last_prologue_pc;
531
532 /* The address of the next instruction. */
533 CORE_ADDR next_pc;
534
535 /* The upper bound to of the pc values to scan. */
536 CORE_ADDR lim_pc;
537
456f8b9d
DB
538 memset (gr_saved, 0, sizeof (gr_saved));
539
d40fcd7b
KB
540 last_prologue_pc = pc;
541
542 /* Try to compute an upper limit (on how far to scan) based on the
543 line number info. */
544 lim_pc = skip_prologue_using_sal (pc);
545 /* If there's no line number info, lim_pc will be 0. In that case,
546 set the limit to be 100 instructions away from pc. Hopefully, this
547 will be far enough away to account for the entire prologue. Don't
548 worry about overshooting the end of the function. The scan loop
549 below contains some checks to avoid scanning unreasonably far. */
550 if (lim_pc == 0)
551 lim_pc = pc + 400;
552
553 /* If we have a frame, we don't want to scan past the frame's pc. This
554 will catch those cases where the pc is in the prologue. */
555 if (next_frame)
556 {
557 CORE_ADDR frame_pc = frame_pc_unwind (next_frame);
558 if (frame_pc < lim_pc)
559 lim_pc = frame_pc;
560 }
561
562 /* Scan the prologue. */
563 while (pc < lim_pc)
456f8b9d
DB
564 {
565 LONGEST op = read_memory_integer (pc, 4);
d40fcd7b 566 next_pc = pc + 4;
456f8b9d
DB
567
568 /* The tests in this chain of ifs should be in order of
569 decreasing selectivity, so that more particular patterns get
570 to fire before less particular patterns. */
571
d40fcd7b
KB
572 /* Some sort of control transfer instruction: stop scanning prologue.
573 Integer Conditional Branch:
574 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
575 Floating-point / media Conditional Branch:
576 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
577 LCR Conditional Branch to LR
578 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
579 Integer conditional Branches to LR
580 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
581 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
582 Floating-point/Media Branches to LR
583 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
584 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
585 Jump and Link
586 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
587 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
588 Call
589 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
590 Return from Trap
591 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
592 Integer Conditional Trap
593 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
594 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
595 Floating-point /media Conditional Trap
596 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
597 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
598 Break
599 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
600 Media Trap
601 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
602 if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */
603 || (op & 0x01f80000) == 0x00300000 /* Jump and Link */
604 || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
605 || (op & 0x01f80000) == 0x00700000) /* Trap immediate */
606 {
607 /* Stop scanning; not in prologue any longer. */
608 break;
609 }
610
611 /* Loading something from memory into fp probably means that
612 we're in the epilogue. Stop scanning the prologue.
613 ld @(GRi, GRk), fp
614 X 000010 0000010 XXXXXX 000100 XXXXXX
615 ldi @(GRi, d12), fp
616 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
617 else if ((op & 0x7ffc0fc0) == 0x04080100
618 || (op & 0x7ffc0000) == 0x04c80000)
619 {
620 break;
621 }
622
456f8b9d
DB
623 /* Setting the FP from the SP:
624 ori sp, 0, fp
625 P 000010 0100010 000001 000000000000 = 0x04881000
626 0 111111 1111111 111111 111111111111 = 0x7fffffff
627 . . . . . . . .
628 We treat this as part of the prologue. */
d40fcd7b 629 else if ((op & 0x7fffffff) == 0x04881000)
456f8b9d
DB
630 {
631 fp_set = 1;
632 fp_offset = 0;
d40fcd7b 633 last_prologue_pc = next_pc;
456f8b9d
DB
634 }
635
636 /* Move the link register to the scratch register grJ, before saving:
637 movsg lr, grJ
638 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
639 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
640 . . . . . . . .
641 We treat this as part of the prologue. */
642 else if ((op & 0x7fffffc0) == 0x080d01c0)
643 {
644 int gr_j = op & 0x3f;
645
646 /* If we're moving it to a scratch register, that's fine. */
647 if (is_caller_saves_reg (gr_j))
d40fcd7b
KB
648 {
649 lr_save_reg = gr_j;
650 last_prologue_pc = next_pc;
651 }
456f8b9d
DB
652 }
653
654 /* To save multiple callee-saves registers on the stack, at
655 offset zero:
656
657 std grK,@(sp,gr0)
658 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
659 0 000000 1111111 111111 111111 111111 = 0x01ffffff
660
661 stq grK,@(sp,gr0)
662 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
663 0 000000 1111111 111111 111111 111111 = 0x01ffffff
664 . . . . . . . .
665 We treat this as part of the prologue, and record the register's
666 saved address in the frame structure. */
667 else if ((op & 0x01ffffff) == 0x000c10c0
668 || (op & 0x01ffffff) == 0x000c1100)
669 {
670 int gr_k = ((op >> 25) & 0x3f);
671 int ope = ((op >> 6) & 0x3f);
672 int count;
673 int i;
674
675 /* Is it an std or an stq? */
676 if (ope == 0x03)
677 count = 2;
678 else
679 count = 4;
680
681 /* Is it really a callee-saves register? */
682 if (is_callee_saves_reg (gr_k))
683 {
684 for (i = 0; i < count; i++)
685 {
686 gr_saved[gr_k + i] = 1;
687 gr_sp_offset[gr_k + i] = 4 * i;
688 }
d40fcd7b 689 last_prologue_pc = next_pc;
456f8b9d 690 }
456f8b9d
DB
691 }
692
693 /* Adjusting the stack pointer. (The stack pointer is GR1.)
694 addi sp, S, sp
695 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
696 0 111111 1111111 111111 000000000000 = 0x7ffff000
697 . . . . . . . .
698 We treat this as part of the prologue. */
699 else if ((op & 0x7ffff000) == 0x02401000)
700 {
d40fcd7b
KB
701 if (framesize == 0)
702 {
703 /* Sign-extend the twelve-bit field.
704 (Isn't there a better way to do this?) */
705 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
456f8b9d 706
d40fcd7b
KB
707 framesize -= s;
708 last_prologue_pc = pc;
709 }
710 else
711 {
712 /* If the prologue is being adjusted again, we've
713 likely gone too far; i.e. we're probably in the
714 epilogue. */
715 break;
716 }
456f8b9d
DB
717 }
718
719 /* Setting the FP to a constant distance from the SP:
720 addi sp, S, fp
721 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
722 0 111111 1111111 111111 000000000000 = 0x7ffff000
723 . . . . . . . .
724 We treat this as part of the prologue. */
725 else if ((op & 0x7ffff000) == 0x04401000)
726 {
727 /* Sign-extend the twelve-bit field.
728 (Isn't there a better way to do this?) */
729 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
730 fp_set = 1;
731 fp_offset = s;
d40fcd7b 732 last_prologue_pc = pc;
456f8b9d
DB
733 }
734
735 /* To spill an argument register to a scratch register:
736 ori GRi, 0, GRk
737 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
738 0 000000 1111111 000000 111111111111 = 0x01fc0fff
739 . . . . . . . .
740 For the time being, we treat this as a prologue instruction,
741 assuming that GRi is an argument register. This one's kind
742 of suspicious, because it seems like it could be part of a
743 legitimate body instruction. But we only come here when the
744 source info wasn't helpful, so we have to do the best we can.
745 Hopefully once GCC and GDB agree on how to emit line number
746 info for prologues, then this code will never come into play. */
747 else if ((op & 0x01fc0fff) == 0x00880000)
748 {
749 int gr_i = ((op >> 12) & 0x3f);
750
d40fcd7b
KB
751 /* Make sure that the source is an arg register; if it is, we'll
752 treat it as a prologue instruction. */
753 if (is_argument_reg (gr_i))
754 last_prologue_pc = next_pc;
456f8b9d
DB
755 }
756
757 /* To spill 16-bit values to the stack:
758 sthi GRk, @(fp, s)
759 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
760 0 000000 1111111 111111 000000000000 = 0x01fff000
761 . . . . . . . .
762 And for 8-bit values, we use STB instructions.
763 stbi GRk, @(fp, s)
764 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
765 0 000000 1111111 111111 000000000000 = 0x01fff000
766 . . . . . . . .
767 We check that GRk is really an argument register, and treat
768 all such as part of the prologue. */
769 else if ( (op & 0x01fff000) == 0x01442000
770 || (op & 0x01fff000) == 0x01402000)
771 {
772 int gr_k = ((op >> 25) & 0x3f);
773
d40fcd7b
KB
774 /* Make sure that GRk is really an argument register; treat
775 it as a prologue instruction if so. */
776 if (is_argument_reg (gr_k))
777 last_prologue_pc = next_pc;
456f8b9d
DB
778 }
779
780 /* To save multiple callee-saves register on the stack, at a
781 non-zero offset:
782
783 stdi GRk, @(sp, s)
784 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
785 0 000000 1111111 111111 000000000000 = 0x01fff000
786 . . . . . . . .
787 stqi GRk, @(sp, s)
788 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
789 0 000000 1111111 111111 000000000000 = 0x01fff000
790 . . . . . . . .
791 We treat this as part of the prologue, and record the register's
792 saved address in the frame structure. */
793 else if ((op & 0x01fff000) == 0x014c1000
794 || (op & 0x01fff000) == 0x01501000)
795 {
796 int gr_k = ((op >> 25) & 0x3f);
797 int count;
798 int i;
799
800 /* Is it a stdi or a stqi? */
801 if ((op & 0x01fff000) == 0x014c1000)
802 count = 2;
803 else
804 count = 4;
805
806 /* Is it really a callee-saves register? */
807 if (is_callee_saves_reg (gr_k))
808 {
809 /* Sign-extend the twelve-bit field.
810 (Isn't there a better way to do this?) */
811 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
812
813 for (i = 0; i < count; i++)
814 {
815 gr_saved[gr_k + i] = 1;
816 gr_sp_offset[gr_k + i] = s + (4 * i);
817 }
d40fcd7b 818 last_prologue_pc = next_pc;
456f8b9d 819 }
456f8b9d
DB
820 }
821
822 /* Storing any kind of integer register at any constant offset
823 from any other register.
824
825 st GRk, @(GRi, gr0)
826 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
827 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
828 . . . . . . . .
829 sti GRk, @(GRi, d12)
830 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
831 0 000000 1111111 000000 000000000000 = 0x01fc0000
832 . . . . . . . .
833 These could be almost anything, but a lot of prologue
834 instructions fall into this pattern, so let's decode the
835 instruction once, and then work at a higher level. */
836 else if (((op & 0x01fc0fff) == 0x000c0080)
837 || ((op & 0x01fc0000) == 0x01480000))
838 {
839 int gr_k = ((op >> 25) & 0x3f);
840 int gr_i = ((op >> 12) & 0x3f);
841 int offset;
842
843 /* Are we storing with gr0 as an offset, or using an
844 immediate value? */
845 if ((op & 0x01fc0fff) == 0x000c0080)
846 offset = 0;
847 else
848 offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
849
850 /* If the address isn't relative to the SP or FP, it's not a
851 prologue instruction. */
852 if (gr_i != sp_regnum && gr_i != fp_regnum)
d40fcd7b
KB
853 {
854 /* Do nothing; not a prologue instruction. */
855 }
456f8b9d
DB
856
857 /* Saving the old FP in the new frame (relative to the SP). */
d40fcd7b 858 else if (gr_k == fp_regnum && gr_i == sp_regnum)
1cb761c7
KB
859 {
860 gr_saved[fp_regnum] = 1;
861 gr_sp_offset[fp_regnum] = offset;
d40fcd7b 862 last_prologue_pc = next_pc;
1cb761c7 863 }
456f8b9d
DB
864
865 /* Saving callee-saves register(s) on the stack, relative to
866 the SP. */
867 else if (gr_i == sp_regnum
868 && is_callee_saves_reg (gr_k))
869 {
870 gr_saved[gr_k] = 1;
1cb761c7
KB
871 if (gr_i == sp_regnum)
872 gr_sp_offset[gr_k] = offset;
873 else
874 gr_sp_offset[gr_k] = offset + fp_offset;
d40fcd7b 875 last_prologue_pc = next_pc;
456f8b9d
DB
876 }
877
878 /* Saving the scratch register holding the return address. */
879 else if (lr_save_reg != -1
880 && gr_k == lr_save_reg)
1cb761c7
KB
881 {
882 lr_saved_on_stack = 1;
883 if (gr_i == sp_regnum)
884 lr_sp_offset = offset;
885 else
886 lr_sp_offset = offset + fp_offset;
d40fcd7b 887 last_prologue_pc = next_pc;
1cb761c7 888 }
456f8b9d
DB
889
890 /* Spilling int-sized arguments to the stack. */
891 else if (is_argument_reg (gr_k))
d40fcd7b 892 last_prologue_pc = next_pc;
456f8b9d 893 }
d40fcd7b 894 pc = next_pc;
456f8b9d
DB
895 }
896
1cb761c7 897 if (next_frame && info)
456f8b9d 898 {
1cb761c7
KB
899 int i;
900 ULONGEST this_base;
456f8b9d
DB
901
902 /* If we know the relationship between the stack and frame
903 pointers, record the addresses of the registers we noticed.
904 Note that we have to do this as a separate step at the end,
905 because instructions may save relative to the SP, but we need
906 their addresses relative to the FP. */
907 if (fp_set)
1cb761c7
KB
908 frame_unwind_unsigned_register (next_frame, fp_regnum, &this_base);
909 else
910 frame_unwind_unsigned_register (next_frame, sp_regnum, &this_base);
456f8b9d 911
1cb761c7
KB
912 for (i = 0; i < 64; i++)
913 if (gr_saved[i])
914 info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i];
456f8b9d 915
1cb761c7
KB
916 info->prev_sp = this_base - fp_offset + framesize;
917 info->base = this_base;
918
919 /* If LR was saved on the stack, record its location. */
920 if (lr_saved_on_stack)
921 info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset;
922
923 /* The call instruction moves the caller's PC in the callee's LR.
924 Since this is an unwind, do the reverse. Copy the location of LR
925 into PC (the address / regnum) so that a request for PC will be
926 converted into a request for the LR. */
927 info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum];
928
929 /* Save the previous frame's computed SP value. */
930 trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp);
456f8b9d
DB
931 }
932
d40fcd7b 933 return last_prologue_pc;
456f8b9d
DB
934}
935
936
937static CORE_ADDR
938frv_skip_prologue (CORE_ADDR pc)
939{
940 CORE_ADDR func_addr, func_end, new_pc;
941
942 new_pc = pc;
943
944 /* If the line table has entry for a line *within* the function
945 (i.e., not in the prologue, and not past the end), then that's
946 our location. */
947 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
948 {
949 struct symtab_and_line sal;
950
951 sal = find_pc_line (func_addr, 0);
952
953 if (sal.line != 0 && sal.end < func_end)
954 {
955 new_pc = sal.end;
956 }
957 }
958
959 /* The FR-V prologue is at least five instructions long (twenty bytes).
960 If we didn't find a real source location past that, then
961 do a full analysis of the prologue. */
962 if (new_pc < pc + 20)
1cb761c7 963 new_pc = frv_analyze_prologue (pc, 0, 0);
456f8b9d
DB
964
965 return new_pc;
966}
967
1cb761c7
KB
968
969static struct frv_unwind_cache *
970frv_frame_unwind_cache (struct frame_info *next_frame,
971 void **this_prologue_cache)
456f8b9d 972{
1cb761c7
KB
973 struct gdbarch *gdbarch = get_frame_arch (next_frame);
974 CORE_ADDR pc;
975 ULONGEST prev_sp;
976 ULONGEST this_base;
977 struct frv_unwind_cache *info;
8baa6f92 978
1cb761c7
KB
979 if ((*this_prologue_cache))
980 return (*this_prologue_cache);
456f8b9d 981
1cb761c7
KB
982 info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache);
983 (*this_prologue_cache) = info;
984 info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
456f8b9d 985
1cb761c7
KB
986 /* Prologue analysis does the rest... */
987 frv_analyze_prologue (frame_func_unwind (next_frame), next_frame, info);
456f8b9d 988
1cb761c7 989 return info;
456f8b9d
DB
990}
991
456f8b9d 992static void
cd31fb03
KB
993frv_extract_return_value (struct type *type, struct regcache *regcache,
994 void *valbuf)
456f8b9d 995{
cd31fb03
KB
996 int len = TYPE_LENGTH (type);
997
998 if (len <= 4)
999 {
1000 ULONGEST gpr8_val;
1001 regcache_cooked_read_unsigned (regcache, 8, &gpr8_val);
1002 store_unsigned_integer (valbuf, len, gpr8_val);
1003 }
1004 else if (len == 8)
1005 {
1006 ULONGEST regval;
1007 regcache_cooked_read_unsigned (regcache, 8, &regval);
1008 store_unsigned_integer (valbuf, 4, regval);
1009 regcache_cooked_read_unsigned (regcache, 9, &regval);
1010 store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval);
1011 }
1012 else
1013 internal_error (__FILE__, __LINE__, "Illegal return value length: %d", len);
456f8b9d
DB
1014}
1015
1016static CORE_ADDR
cd31fb03 1017frv_extract_struct_value_address (struct regcache *regcache)
456f8b9d 1018{
cd31fb03
KB
1019 ULONGEST addr;
1020 regcache_cooked_read_unsigned (regcache, struct_return_regnum, &addr);
1021 return addr;
456f8b9d
DB
1022}
1023
1024static void
1025frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
1026{
1027 write_register (struct_return_regnum, addr);
1028}
1029
1030static int
1031frv_frameless_function_invocation (struct frame_info *frame)
1032{
1033 return frameless_look_for_prologue (frame);
1034}
1035
1cb761c7
KB
1036static CORE_ADDR
1037frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
456f8b9d 1038{
1cb761c7 1039 /* Require dword alignment. */
5b03f266 1040 return align_down (sp, 8);
456f8b9d
DB
1041}
1042
456f8b9d 1043static CORE_ADDR
1cb761c7
KB
1044frv_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1045 struct regcache *regcache, CORE_ADDR bp_addr,
1046 int nargs, struct value **args, CORE_ADDR sp,
1047 int struct_return, CORE_ADDR struct_addr)
456f8b9d
DB
1048{
1049 int argreg;
1050 int argnum;
1051 char *val;
1052 char valbuf[4];
1053 struct value *arg;
1054 struct type *arg_type;
1055 int len;
1056 enum type_code typecode;
1057 CORE_ADDR regval;
1058 int stack_space;
1059 int stack_offset;
1060
1061#if 0
1062 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1063 nargs, (int) sp, struct_return, struct_addr);
1064#endif
1065
1066 stack_space = 0;
1067 for (argnum = 0; argnum < nargs; ++argnum)
5b03f266 1068 stack_space += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4);
456f8b9d
DB
1069
1070 stack_space -= (6 * 4);
1071 if (stack_space > 0)
1072 sp -= stack_space;
1073
1074 /* Make sure stack is dword aligned. */
5b03f266 1075 sp = align_down (sp, 8);
456f8b9d
DB
1076
1077 stack_offset = 0;
1078
1079 argreg = 8;
1080
1081 if (struct_return)
1cb761c7
KB
1082 regcache_cooked_write_unsigned (regcache, struct_return_regnum,
1083 struct_addr);
456f8b9d
DB
1084
1085 for (argnum = 0; argnum < nargs; ++argnum)
1086 {
1087 arg = args[argnum];
1088 arg_type = check_typedef (VALUE_TYPE (arg));
1089 len = TYPE_LENGTH (arg_type);
1090 typecode = TYPE_CODE (arg_type);
1091
1092 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
1093 {
fbd9dcd3 1094 store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg));
456f8b9d
DB
1095 typecode = TYPE_CODE_PTR;
1096 len = 4;
1097 val = valbuf;
1098 }
1099 else
1100 {
1101 val = (char *) VALUE_CONTENTS (arg);
1102 }
1103
1104 while (len > 0)
1105 {
1106 int partial_len = (len < 4 ? len : 4);
1107
1108 if (argreg < 14)
1109 {
7c0b4a20 1110 regval = extract_unsigned_integer (val, partial_len);
456f8b9d
DB
1111#if 0
1112 printf(" Argnum %d data %x -> reg %d\n",
1113 argnum, (int) regval, argreg);
1114#endif
1cb761c7 1115 regcache_cooked_write_unsigned (regcache, argreg, regval);
456f8b9d
DB
1116 ++argreg;
1117 }
1118 else
1119 {
1120#if 0
1121 printf(" Argnum %d data %x -> offset %d (%x)\n",
1122 argnum, *((int *)val), stack_offset, (int) (sp + stack_offset));
1123#endif
1124 write_memory (sp + stack_offset, val, partial_len);
5b03f266 1125 stack_offset += align_up (partial_len, 4);
456f8b9d
DB
1126 }
1127 len -= partial_len;
1128 val += partial_len;
1129 }
1130 }
456f8b9d 1131
1cb761c7
KB
1132 /* Set the return address. For the frv, the return breakpoint is
1133 always at BP_ADDR. */
1134 regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr);
1135
1136 /* Finally, update the SP register. */
1137 regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
1138
456f8b9d
DB
1139 return sp;
1140}
1141
1142static void
cd31fb03
KB
1143frv_store_return_value (struct type *type, struct regcache *regcache,
1144 const void *valbuf)
456f8b9d 1145{
cd31fb03
KB
1146 int len = TYPE_LENGTH (type);
1147
1148 if (len <= 4)
1149 {
1150 bfd_byte val[4];
1151 memset (val, 0, sizeof (val));
1152 memcpy (val + (4 - len), valbuf, len);
1153 regcache_cooked_write (regcache, 8, val);
1154 }
1155 else if (len == 8)
1156 {
1157 regcache_cooked_write (regcache, 8, valbuf);
1158 regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4);
1159 }
456f8b9d
DB
1160 else
1161 internal_error (__FILE__, __LINE__,
cd31fb03 1162 "Don't know how to return a %d-byte value.", len);
456f8b9d
DB
1163}
1164
456f8b9d 1165
456f8b9d
DB
1166/* Hardware watchpoint / breakpoint support for the FR500
1167 and FR400. */
1168
1169int
1170frv_check_watch_resources (int type, int cnt, int ot)
1171{
1172 struct gdbarch_tdep *var = CURRENT_VARIANT;
1173
1174 /* Watchpoints not supported on simulator. */
1175 if (strcmp (target_shortname, "sim") == 0)
1176 return 0;
1177
1178 if (type == bp_hardware_breakpoint)
1179 {
1180 if (var->num_hw_breakpoints == 0)
1181 return 0;
1182 else if (cnt <= var->num_hw_breakpoints)
1183 return 1;
1184 }
1185 else
1186 {
1187 if (var->num_hw_watchpoints == 0)
1188 return 0;
1189 else if (ot)
1190 return -1;
1191 else if (cnt <= var->num_hw_watchpoints)
1192 return 1;
1193 }
1194 return -1;
1195}
1196
1197
1198CORE_ADDR
5ae5f592 1199frv_stopped_data_address (void)
456f8b9d
DB
1200{
1201 CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3;
1202
1203 brr = read_register (brr_regnum);
1204 dbar0 = read_register (dbar0_regnum);
1205 dbar1 = read_register (dbar1_regnum);
1206 dbar2 = read_register (dbar2_regnum);
1207 dbar3 = read_register (dbar3_regnum);
1208
1209 if (brr & (1<<11))
1210 return dbar0;
1211 else if (brr & (1<<10))
1212 return dbar1;
1213 else if (brr & (1<<9))
1214 return dbar2;
1215 else if (brr & (1<<8))
1216 return dbar3;
1217 else
1218 return 0;
1219}
1220
1cb761c7
KB
1221static CORE_ADDR
1222frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1223{
1224 return frame_unwind_register_unsigned (next_frame, pc_regnum);
1225}
1226
1227/* Given a GDB frame, determine the address of the calling function's
1228 frame. This will be used to create a new GDB frame struct. */
1229
1230static void
1231frv_frame_this_id (struct frame_info *next_frame,
1232 void **this_prologue_cache, struct frame_id *this_id)
1233{
1234 struct frv_unwind_cache *info
1235 = frv_frame_unwind_cache (next_frame, this_prologue_cache);
1236 CORE_ADDR base;
1237 CORE_ADDR func;
1238 struct minimal_symbol *msym_stack;
1239 struct frame_id id;
1240
1241 /* The FUNC is easy. */
1242 func = frame_func_unwind (next_frame);
1243
1cb761c7
KB
1244 /* Check if the stack is empty. */
1245 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
1246 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
1247 return;
1248
1249 /* Hopefully the prologue analysis either correctly determined the
1250 frame's base (which is the SP from the previous frame), or set
1251 that base to "NULL". */
1252 base = info->prev_sp;
1253 if (base == 0)
1254 return;
1255
1256 id = frame_id_build (base, func);
1257
1258 /* Check that we're not going round in circles with the same frame
1259 ID (but avoid applying the test to sentinel frames which do go
1260 round in circles). Can't use frame_id_eq() as that doesn't yet
1261 compare the frame's PC value. */
1262 if (frame_relative_level (next_frame) >= 0
1263 && get_frame_type (next_frame) != DUMMY_FRAME
1264 && frame_id_eq (get_frame_id (next_frame), id))
1265 return;
1266
1267 (*this_id) = id;
1268}
1269
1270static void
1271frv_frame_prev_register (struct frame_info *next_frame,
1272 void **this_prologue_cache,
1273 int regnum, int *optimizedp,
1274 enum lval_type *lvalp, CORE_ADDR *addrp,
1275 int *realnump, void *bufferp)
1276{
1277 struct frv_unwind_cache *info
1278 = frv_frame_unwind_cache (next_frame, this_prologue_cache);
1279 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
1280 optimizedp, lvalp, addrp, realnump, bufferp);
1281}
1282
1283static const struct frame_unwind frv_frame_unwind = {
1284 NORMAL_FRAME,
1285 frv_frame_this_id,
1286 frv_frame_prev_register
1287};
1288
1289static const struct frame_unwind *
1290frv_frame_sniffer (struct frame_info *next_frame)
1291{
1292 return &frv_frame_unwind;
1293}
1294
1295static CORE_ADDR
1296frv_frame_base_address (struct frame_info *next_frame, void **this_cache)
1297{
1298 struct frv_unwind_cache *info
1299 = frv_frame_unwind_cache (next_frame, this_cache);
1300 return info->base;
1301}
1302
1303static const struct frame_base frv_frame_base = {
1304 &frv_frame_unwind,
1305 frv_frame_base_address,
1306 frv_frame_base_address,
1307 frv_frame_base_address
1308};
1309
1310static CORE_ADDR
1311frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1312{
1313 return frame_unwind_register_unsigned (next_frame, sp_regnum);
1314}
1315
1316
1317/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1318 dummy frame. The frame ID's base needs to match the TOS value
1319 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1320 breakpoint. */
1321
1322static struct frame_id
1323frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1324{
1325 return frame_id_build (frv_unwind_sp (gdbarch, next_frame),
1326 frame_pc_unwind (next_frame));
1327}
1328
1329
456f8b9d
DB
1330static struct gdbarch *
1331frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1332{
1333 struct gdbarch *gdbarch;
1334 struct gdbarch_tdep *var;
1335
1336 /* Check to see if we've already built an appropriate architecture
1337 object for this executable. */
1338 arches = gdbarch_list_lookup_by_info (arches, &info);
1339 if (arches)
1340 return arches->gdbarch;
1341
1342 /* Select the right tdep structure for this variant. */
1343 var = new_variant ();
1344 switch (info.bfd_arch_info->mach)
1345 {
1346 case bfd_mach_frv:
1347 case bfd_mach_frvsimple:
1348 case bfd_mach_fr500:
1349 case bfd_mach_frvtomcat:
251a3ae3 1350 case bfd_mach_fr550:
456f8b9d
DB
1351 set_variant_num_gprs (var, 64);
1352 set_variant_num_fprs (var, 64);
1353 break;
1354
1355 case bfd_mach_fr400:
1356 set_variant_num_gprs (var, 32);
1357 set_variant_num_fprs (var, 32);
1358 break;
1359
1360 default:
1361 /* Never heard of this variant. */
1362 return 0;
1363 }
1364
1365 gdbarch = gdbarch_alloc (&info, var);
1366
1367 set_gdbarch_short_bit (gdbarch, 16);
1368 set_gdbarch_int_bit (gdbarch, 32);
1369 set_gdbarch_long_bit (gdbarch, 32);
1370 set_gdbarch_long_long_bit (gdbarch, 64);
1371 set_gdbarch_float_bit (gdbarch, 32);
1372 set_gdbarch_double_bit (gdbarch, 64);
1373 set_gdbarch_long_double_bit (gdbarch, 64);
1374 set_gdbarch_ptr_bit (gdbarch, 32);
1375
1376 set_gdbarch_num_regs (gdbarch, frv_num_regs);
6a748db6
KB
1377 set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs);
1378
456f8b9d 1379 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
0ba6dca9 1380 set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum);
456f8b9d
DB
1381 set_gdbarch_pc_regnum (gdbarch, pc_regnum);
1382
1383 set_gdbarch_register_name (gdbarch, frv_register_name);
7f398216 1384 set_gdbarch_register_type (gdbarch, frv_register_type);
526eef89 1385 set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno);
456f8b9d 1386
6a748db6
KB
1387 set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read);
1388 set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write);
1389
456f8b9d
DB
1390 set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue);
1391 set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc);
46a16dba 1392 set_gdbarch_adjust_breakpoint_address (gdbarch, frv_gdbarch_adjust_breakpoint_address);
456f8b9d 1393
456f8b9d
DB
1394 set_gdbarch_frameless_function_invocation (gdbarch, frv_frameless_function_invocation);
1395
1fd35568 1396 set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention);
cd31fb03 1397 set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value);
456f8b9d 1398
4183d812 1399 set_gdbarch_deprecated_store_struct_return (gdbarch, frv_store_struct_return);
cd31fb03 1400 set_gdbarch_store_return_value (gdbarch, frv_store_return_value);
74055713 1401 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, frv_extract_struct_value_address);
456f8b9d 1402
1cb761c7
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1403 /* Frame stuff. */
1404 set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc);
1405 set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp);
1406 set_gdbarch_frame_align (gdbarch, frv_frame_align);
1407 frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer);
1408 frame_base_set_default (gdbarch, &frv_frame_base);
456f8b9d 1409
1cb761c7
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1410 /* Settings for calling functions in the inferior. */
1411 set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call);
1412 set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id);
456f8b9d
DB
1413
1414 /* Settings that should be unnecessary. */
1415 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1416
456f8b9d 1417 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
456f8b9d 1418
456f8b9d 1419 set_gdbarch_remote_translate_xfer_address
aed7f26a 1420 (gdbarch, generic_remote_translate_xfer_address);
456f8b9d
DB
1421
1422 /* Hardware watchpoint / breakpoint support. */
1423 switch (info.bfd_arch_info->mach)
1424 {
1425 case bfd_mach_frv:
1426 case bfd_mach_frvsimple:
1427 case bfd_mach_fr500:
1428 case bfd_mach_frvtomcat:
1429 /* fr500-style hardware debugging support. */
1430 var->num_hw_watchpoints = 4;
1431 var->num_hw_breakpoints = 4;
1432 break;
1433
1434 case bfd_mach_fr400:
1435 /* fr400-style hardware debugging support. */
1436 var->num_hw_watchpoints = 2;
1437 var->num_hw_breakpoints = 4;
1438 break;
1439
1440 default:
1441 /* Otherwise, assume we don't have hardware debugging support. */
1442 var->num_hw_watchpoints = 0;
1443 var->num_hw_breakpoints = 0;
1444 break;
1445 }
1446
36482093
AC
1447 set_gdbarch_print_insn (gdbarch, print_insn_frv);
1448
456f8b9d
DB
1449 return gdbarch;
1450}
1451
1452void
1453_initialize_frv_tdep (void)
1454{
1455 register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init);
456f8b9d 1456}
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