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456f8b9d | 1 | /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger. |
1e698235 | 2 | Copyright 2002, 2003 Free Software Foundation, Inc. |
456f8b9d DB |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include "defs.h" | |
8baa6f92 | 22 | #include "gdb_string.h" |
456f8b9d DB |
23 | #include "inferior.h" |
24 | #include "symfile.h" /* for entry_point_address */ | |
25 | #include "gdbcore.h" | |
26 | #include "arch-utils.h" | |
27 | #include "regcache.h" | |
8baa6f92 | 28 | #include "frame.h" |
1cb761c7 KB |
29 | #include "frame-unwind.h" |
30 | #include "frame-base.h" | |
8baa6f92 | 31 | #include "trad-frame.h" |
dcc6aaff | 32 | #include "dis-asm.h" |
526eef89 KB |
33 | #include "gdb_assert.h" |
34 | #include "sim-regno.h" | |
35 | #include "gdb/sim-frv.h" | |
36 | #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */ | |
456f8b9d DB |
37 | |
38 | extern void _initialize_frv_tdep (void); | |
39 | ||
40 | static gdbarch_init_ftype frv_gdbarch_init; | |
41 | ||
42 | static gdbarch_register_name_ftype frv_register_name; | |
456f8b9d | 43 | static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc; |
46a16dba | 44 | static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address; |
456f8b9d | 45 | static gdbarch_skip_prologue_ftype frv_skip_prologue; |
456f8b9d | 46 | static gdbarch_frameless_function_invocation_ftype frv_frameless_function_invocation; |
456f8b9d | 47 | |
526eef89 KB |
48 | /* Register numbers. The order in which these appear define the |
49 | remote protocol, so take care in changing them. */ | |
456f8b9d | 50 | enum { |
456f8b9d DB |
51 | /* Register numbers 0 -- 63 are always reserved for general-purpose |
52 | registers. The chip at hand may have less. */ | |
53 | first_gpr_regnum = 0, | |
54 | sp_regnum = 1, | |
55 | fp_regnum = 2, | |
56 | struct_return_regnum = 3, | |
57 | last_gpr_regnum = 63, | |
58 | ||
59 | /* Register numbers 64 -- 127 are always reserved for floating-point | |
60 | registers. The chip at hand may have less. */ | |
61 | first_fpr_regnum = 64, | |
62 | last_fpr_regnum = 127, | |
63 | ||
526eef89 | 64 | /* The PC register. */ |
456f8b9d | 65 | pc_regnum = 128, |
526eef89 KB |
66 | |
67 | /* Register numbers 129 on up are always reserved for special-purpose | |
68 | registers. */ | |
69 | first_spr_regnum = 129, | |
456f8b9d DB |
70 | psr_regnum = 129, |
71 | ccr_regnum = 130, | |
72 | cccr_regnum = 131, | |
73 | tbr_regnum = 135, | |
74 | brr_regnum = 136, | |
75 | dbar0_regnum = 137, | |
76 | dbar1_regnum = 138, | |
77 | dbar2_regnum = 139, | |
78 | dbar3_regnum = 140, | |
79 | lr_regnum = 145, | |
80 | lcr_regnum = 146, | |
526eef89 KB |
81 | iacc0h_regnum = 147, |
82 | iacc0l_regnum = 148, | |
83 | last_spr_regnum = 148, | |
84 | ||
85 | /* The total number of registers we know exist. */ | |
6a748db6 KB |
86 | frv_num_regs = last_spr_regnum + 1, |
87 | ||
88 | /* Pseudo registers */ | |
89 | first_pseudo_regnum = frv_num_regs, | |
90 | ||
91 | /* iacc0 - the 64-bit concatenation of iacc0h and iacc0l. */ | |
92 | iacc0_regnum = first_pseudo_regnum + 0, | |
93 | ||
94 | last_pseudo_regnum = iacc0_regnum, | |
65ed7f0a | 95 | frv_num_pseudo_regs = last_pseudo_regnum - first_pseudo_regnum + 1, |
456f8b9d DB |
96 | }; |
97 | ||
98 | static LONGEST frv_call_dummy_words[] = | |
99 | {0}; | |
100 | ||
101 | ||
1cb761c7 | 102 | struct frv_unwind_cache /* was struct frame_extra_info */ |
456f8b9d | 103 | { |
1cb761c7 KB |
104 | /* The previous frame's inner-most stack address. Used as this |
105 | frame ID's stack_addr. */ | |
106 | CORE_ADDR prev_sp; | |
456f8b9d | 107 | |
1cb761c7 KB |
108 | /* The frame's base, optionally used by the high-level debug info. */ |
109 | CORE_ADDR base; | |
8baa6f92 KB |
110 | |
111 | /* Table indicating the location of each and every register. */ | |
112 | struct trad_frame_saved_reg *saved_regs; | |
456f8b9d DB |
113 | }; |
114 | ||
115 | ||
116 | /* A structure describing a particular variant of the FRV. | |
117 | We allocate and initialize one of these structures when we create | |
118 | the gdbarch object for a variant. | |
119 | ||
120 | At the moment, all the FR variants we support differ only in which | |
121 | registers are present; the portable code of GDB knows that | |
122 | registers whose names are the empty string don't exist, so the | |
123 | `register_names' array captures all the per-variant information we | |
124 | need. | |
125 | ||
126 | in the future, if we need to have per-variant maps for raw size, | |
127 | virtual type, etc., we should replace register_names with an array | |
128 | of structures, each of which gives all the necessary info for one | |
129 | register. Don't stick parallel arrays in here --- that's so | |
130 | Fortran. */ | |
131 | struct gdbarch_tdep | |
132 | { | |
133 | /* How many general-purpose registers does this variant have? */ | |
134 | int num_gprs; | |
135 | ||
136 | /* How many floating-point registers does this variant have? */ | |
137 | int num_fprs; | |
138 | ||
139 | /* How many hardware watchpoints can it support? */ | |
140 | int num_hw_watchpoints; | |
141 | ||
142 | /* How many hardware breakpoints can it support? */ | |
143 | int num_hw_breakpoints; | |
144 | ||
145 | /* Register names. */ | |
146 | char **register_names; | |
147 | }; | |
148 | ||
149 | #define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch)) | |
150 | ||
151 | ||
152 | /* Allocate a new variant structure, and set up default values for all | |
153 | the fields. */ | |
154 | static struct gdbarch_tdep * | |
5ae5f592 | 155 | new_variant (void) |
456f8b9d DB |
156 | { |
157 | struct gdbarch_tdep *var; | |
158 | int r; | |
159 | char buf[20]; | |
160 | ||
161 | var = xmalloc (sizeof (*var)); | |
162 | memset (var, 0, sizeof (*var)); | |
163 | ||
164 | var->num_gprs = 64; | |
165 | var->num_fprs = 64; | |
166 | var->num_hw_watchpoints = 0; | |
167 | var->num_hw_breakpoints = 0; | |
168 | ||
169 | /* By default, don't supply any general-purpose or floating-point | |
170 | register names. */ | |
6a748db6 KB |
171 | var->register_names |
172 | = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs) | |
173 | * sizeof (char *)); | |
174 | for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++) | |
456f8b9d DB |
175 | var->register_names[r] = ""; |
176 | ||
526eef89 | 177 | /* Do, however, supply default names for the known special-purpose |
456f8b9d | 178 | registers. */ |
456f8b9d DB |
179 | |
180 | var->register_names[pc_regnum] = "pc"; | |
181 | var->register_names[lr_regnum] = "lr"; | |
182 | var->register_names[lcr_regnum] = "lcr"; | |
183 | ||
184 | var->register_names[psr_regnum] = "psr"; | |
185 | var->register_names[ccr_regnum] = "ccr"; | |
186 | var->register_names[cccr_regnum] = "cccr"; | |
187 | var->register_names[tbr_regnum] = "tbr"; | |
188 | ||
189 | /* Debug registers. */ | |
190 | var->register_names[brr_regnum] = "brr"; | |
191 | var->register_names[dbar0_regnum] = "dbar0"; | |
192 | var->register_names[dbar1_regnum] = "dbar1"; | |
193 | var->register_names[dbar2_regnum] = "dbar2"; | |
194 | var->register_names[dbar3_regnum] = "dbar3"; | |
195 | ||
526eef89 KB |
196 | /* iacc0 (Only found on MB93405.) */ |
197 | var->register_names[iacc0h_regnum] = "iacc0h"; | |
198 | var->register_names[iacc0l_regnum] = "iacc0l"; | |
6a748db6 | 199 | var->register_names[iacc0_regnum] = "iacc0"; |
526eef89 | 200 | |
456f8b9d DB |
201 | return var; |
202 | } | |
203 | ||
204 | ||
205 | /* Indicate that the variant VAR has NUM_GPRS general-purpose | |
206 | registers, and fill in the names array appropriately. */ | |
207 | static void | |
208 | set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs) | |
209 | { | |
210 | int r; | |
211 | ||
212 | var->num_gprs = num_gprs; | |
213 | ||
214 | for (r = 0; r < num_gprs; ++r) | |
215 | { | |
216 | char buf[20]; | |
217 | ||
218 | sprintf (buf, "gr%d", r); | |
219 | var->register_names[first_gpr_regnum + r] = xstrdup (buf); | |
220 | } | |
221 | } | |
222 | ||
223 | ||
224 | /* Indicate that the variant VAR has NUM_FPRS floating-point | |
225 | registers, and fill in the names array appropriately. */ | |
226 | static void | |
227 | set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs) | |
228 | { | |
229 | int r; | |
230 | ||
231 | var->num_fprs = num_fprs; | |
232 | ||
233 | for (r = 0; r < num_fprs; ++r) | |
234 | { | |
235 | char buf[20]; | |
236 | ||
237 | sprintf (buf, "fr%d", r); | |
238 | var->register_names[first_fpr_regnum + r] = xstrdup (buf); | |
239 | } | |
240 | } | |
241 | ||
242 | ||
243 | static const char * | |
244 | frv_register_name (int reg) | |
245 | { | |
246 | if (reg < 0) | |
247 | return "?toosmall?"; | |
6a748db6 | 248 | if (reg >= frv_num_regs + frv_num_pseudo_regs) |
456f8b9d DB |
249 | return "?toolarge?"; |
250 | ||
251 | return CURRENT_VARIANT->register_names[reg]; | |
252 | } | |
253 | ||
526eef89 | 254 | |
456f8b9d | 255 | static struct type * |
7f398216 | 256 | frv_register_type (struct gdbarch *gdbarch, int reg) |
456f8b9d | 257 | { |
526eef89 | 258 | if (reg >= first_fpr_regnum && reg <= last_fpr_regnum) |
456f8b9d | 259 | return builtin_type_float; |
6a748db6 KB |
260 | else if (reg == iacc0_regnum) |
261 | return builtin_type_int64; | |
456f8b9d | 262 | else |
526eef89 | 263 | return builtin_type_int32; |
456f8b9d DB |
264 | } |
265 | ||
6a748db6 KB |
266 | static void |
267 | frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
268 | int reg, void *buffer) | |
269 | { | |
270 | if (reg == iacc0_regnum) | |
271 | { | |
272 | regcache_raw_read (regcache, iacc0h_regnum, buffer); | |
273 | regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); | |
274 | } | |
275 | } | |
276 | ||
277 | static void | |
278 | frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
279 | int reg, const void *buffer) | |
280 | { | |
281 | if (reg == iacc0_regnum) | |
282 | { | |
283 | regcache_raw_write (regcache, iacc0h_regnum, buffer); | |
284 | regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); | |
285 | } | |
286 | } | |
287 | ||
526eef89 KB |
288 | static int |
289 | frv_register_sim_regno (int reg) | |
290 | { | |
291 | static const int spr_map[] = | |
292 | { | |
293 | H_SPR_PSR, /* psr_regnum */ | |
294 | H_SPR_CCR, /* ccr_regnum */ | |
295 | H_SPR_CCCR, /* cccr_regnum */ | |
296 | -1, /* 132 */ | |
297 | -1, /* 133 */ | |
298 | -1, /* 134 */ | |
299 | H_SPR_TBR, /* tbr_regnum */ | |
300 | H_SPR_BRR, /* brr_regnum */ | |
301 | H_SPR_DBAR0, /* dbar0_regnum */ | |
302 | H_SPR_DBAR1, /* dbar1_regnum */ | |
303 | H_SPR_DBAR2, /* dbar2_regnum */ | |
304 | H_SPR_DBAR3, /* dbar3_regnum */ | |
305 | -1, /* 141 */ | |
306 | -1, /* 142 */ | |
307 | -1, /* 143 */ | |
308 | -1, /* 144 */ | |
309 | H_SPR_LR, /* lr_regnum */ | |
310 | H_SPR_LCR, /* lcr_regnum */ | |
311 | H_SPR_IACC0H, /* iacc0h_regnum */ | |
312 | H_SPR_IACC0L /* iacc0l_regnum */ | |
313 | }; | |
314 | ||
315 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
316 | ||
317 | if (first_gpr_regnum <= reg && reg <= last_gpr_regnum) | |
318 | return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM; | |
319 | else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum) | |
320 | return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM; | |
321 | else if (pc_regnum == reg) | |
322 | return SIM_FRV_PC_REGNUM; | |
323 | else if (reg >= first_spr_regnum | |
324 | && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0])) | |
325 | { | |
326 | int spr_reg_offset = spr_map[reg - first_spr_regnum]; | |
327 | ||
328 | if (spr_reg_offset < 0) | |
329 | return SIM_REGNO_DOES_NOT_EXIST; | |
330 | else | |
331 | return SIM_FRV_SPR0_REGNUM + spr_reg_offset; | |
332 | } | |
333 | ||
334 | internal_error (__FILE__, __LINE__, "Bad register number %d", reg); | |
335 | } | |
336 | ||
456f8b9d DB |
337 | static const unsigned char * |
338 | frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp) | |
339 | { | |
340 | static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01}; | |
341 | *lenp = sizeof (breakpoint); | |
342 | return breakpoint; | |
343 | } | |
344 | ||
46a16dba KB |
345 | /* Define the maximum number of instructions which may be packed into a |
346 | bundle (VLIW instruction). */ | |
347 | static const int max_instrs_per_bundle = 8; | |
348 | ||
349 | /* Define the size (in bytes) of an FR-V instruction. */ | |
350 | static const int frv_instr_size = 4; | |
351 | ||
352 | /* Adjust a breakpoint's address to account for the FR-V architecture's | |
353 | constraint that a break instruction must not appear as any but the | |
354 | first instruction in the bundle. */ | |
355 | static CORE_ADDR | |
356 | frv_gdbarch_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
357 | { | |
358 | int count = max_instrs_per_bundle; | |
359 | CORE_ADDR addr = bpaddr - frv_instr_size; | |
360 | CORE_ADDR func_start = get_pc_function_start (bpaddr); | |
361 | ||
362 | /* Find the end of the previous packing sequence. This will be indicated | |
363 | by either attempting to access some inaccessible memory or by finding | |
364 | an instruction word whose packing bit is set to one. */ | |
365 | while (count-- > 0 && addr >= func_start) | |
366 | { | |
367 | char instr[frv_instr_size]; | |
368 | int status; | |
369 | ||
370 | status = read_memory_nobpt (addr, instr, sizeof instr); | |
371 | ||
372 | if (status != 0) | |
373 | break; | |
374 | ||
375 | /* This is a big endian architecture, so byte zero will have most | |
376 | significant byte. The most significant bit of this byte is the | |
377 | packing bit. */ | |
378 | if (instr[0] & 0x80) | |
379 | break; | |
380 | ||
381 | addr -= frv_instr_size; | |
382 | } | |
383 | ||
384 | if (count > 0) | |
385 | bpaddr = addr + frv_instr_size; | |
386 | ||
387 | return bpaddr; | |
388 | } | |
389 | ||
456f8b9d DB |
390 | |
391 | /* Return true if REG is a caller-saves ("scratch") register, | |
392 | false otherwise. */ | |
393 | static int | |
394 | is_caller_saves_reg (int reg) | |
395 | { | |
396 | return ((4 <= reg && reg <= 7) | |
397 | || (14 <= reg && reg <= 15) | |
398 | || (32 <= reg && reg <= 47)); | |
399 | } | |
400 | ||
401 | ||
402 | /* Return true if REG is a callee-saves register, false otherwise. */ | |
403 | static int | |
404 | is_callee_saves_reg (int reg) | |
405 | { | |
406 | return ((16 <= reg && reg <= 31) | |
407 | || (48 <= reg && reg <= 63)); | |
408 | } | |
409 | ||
410 | ||
411 | /* Return true if REG is an argument register, false otherwise. */ | |
412 | static int | |
413 | is_argument_reg (int reg) | |
414 | { | |
415 | return (8 <= reg && reg <= 13); | |
416 | } | |
417 | ||
d40fcd7b KB |
418 | /* Given PC at the function's start address, attempt to find the |
419 | prologue end using SAL information. Return zero if the skip fails. | |
420 | ||
421 | A non-optimized prologue traditionally has one SAL for the function | |
422 | and a second for the function body. A single line function has | |
423 | them both pointing at the same line. | |
424 | ||
425 | An optimized prologue is similar but the prologue may contain | |
426 | instructions (SALs) from the instruction body. Need to skip those | |
427 | while not getting into the function body. | |
428 | ||
429 | The functions end point and an increasing SAL line are used as | |
430 | indicators of the prologue's endpoint. | |
431 | ||
432 | This code is based on the function refine_prologue_limit (versions | |
433 | found in both ia64 and ppc). */ | |
434 | ||
435 | static CORE_ADDR | |
436 | skip_prologue_using_sal (CORE_ADDR func_addr) | |
437 | { | |
438 | struct symtab_and_line prologue_sal; | |
439 | CORE_ADDR start_pc; | |
440 | CORE_ADDR end_pc; | |
441 | ||
442 | /* Get an initial range for the function. */ | |
443 | find_pc_partial_function (func_addr, NULL, &start_pc, &end_pc); | |
444 | start_pc += FUNCTION_START_OFFSET; | |
445 | ||
446 | prologue_sal = find_pc_line (start_pc, 0); | |
447 | if (prologue_sal.line != 0) | |
448 | { | |
449 | while (prologue_sal.end < end_pc) | |
450 | { | |
451 | struct symtab_and_line sal; | |
452 | ||
453 | sal = find_pc_line (prologue_sal.end, 0); | |
454 | if (sal.line == 0) | |
455 | break; | |
456 | /* Assume that a consecutive SAL for the same (or larger) | |
457 | line mark the prologue -> body transition. */ | |
458 | if (sal.line >= prologue_sal.line) | |
459 | break; | |
460 | /* The case in which compiler's optimizer/scheduler has | |
461 | moved instructions into the prologue. We look ahead in | |
462 | the function looking for address ranges whose | |
463 | corresponding line number is less the first one that we | |
464 | found for the function. This is more conservative then | |
465 | refine_prologue_limit which scans a large number of SALs | |
466 | looking for any in the prologue */ | |
467 | prologue_sal = sal; | |
468 | } | |
469 | } | |
470 | return prologue_sal.end; | |
471 | } | |
472 | ||
456f8b9d DB |
473 | |
474 | /* Scan an FR-V prologue, starting at PC, until frame->PC. | |
475 | If FRAME is non-zero, fill in its saved_regs with appropriate addresses. | |
476 | We assume FRAME's saved_regs array has already been allocated and cleared. | |
477 | Return the first PC value after the prologue. | |
478 | ||
479 | Note that, for unoptimized code, we almost don't need this function | |
480 | at all; all arguments and locals live on the stack, so we just need | |
481 | the FP to find everything. The catch: structures passed by value | |
482 | have their addresses living in registers; they're never spilled to | |
483 | the stack. So if you ever want to be able to get to these | |
484 | arguments in any frame but the top, you'll need to do this serious | |
485 | prologue analysis. */ | |
486 | static CORE_ADDR | |
1cb761c7 KB |
487 | frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
488 | struct frv_unwind_cache *info) | |
456f8b9d DB |
489 | { |
490 | /* When writing out instruction bitpatterns, we use the following | |
491 | letters to label instruction fields: | |
492 | P - The parallel bit. We don't use this. | |
493 | J - The register number of GRj in the instruction description. | |
494 | K - The register number of GRk in the instruction description. | |
495 | I - The register number of GRi. | |
496 | S - a signed imediate offset. | |
497 | U - an unsigned immediate offset. | |
498 | ||
499 | The dots below the numbers indicate where hex digit boundaries | |
500 | fall, to make it easier to check the numbers. */ | |
501 | ||
502 | /* Non-zero iff we've seen the instruction that initializes the | |
503 | frame pointer for this function's frame. */ | |
504 | int fp_set = 0; | |
505 | ||
506 | /* If fp_set is non_zero, then this is the distance from | |
507 | the stack pointer to frame pointer: fp = sp + fp_offset. */ | |
508 | int fp_offset = 0; | |
509 | ||
510 | /* Total size of frame prior to any alloca operations. */ | |
511 | int framesize = 0; | |
512 | ||
1cb761c7 KB |
513 | /* Flag indicating if lr has been saved on the stack. */ |
514 | int lr_saved_on_stack = 0; | |
515 | ||
456f8b9d DB |
516 | /* The number of the general-purpose register we saved the return |
517 | address ("link register") in, or -1 if we haven't moved it yet. */ | |
518 | int lr_save_reg = -1; | |
519 | ||
1cb761c7 KB |
520 | /* Offset (from sp) at which lr has been saved on the stack. */ |
521 | ||
522 | int lr_sp_offset = 0; | |
456f8b9d DB |
523 | |
524 | /* If gr_saved[i] is non-zero, then we've noticed that general | |
525 | register i has been saved at gr_sp_offset[i] from the stack | |
526 | pointer. */ | |
527 | char gr_saved[64]; | |
528 | int gr_sp_offset[64]; | |
529 | ||
d40fcd7b KB |
530 | /* The address of the most recently scanned prologue instruction. */ |
531 | CORE_ADDR last_prologue_pc; | |
532 | ||
533 | /* The address of the next instruction. */ | |
534 | CORE_ADDR next_pc; | |
535 | ||
536 | /* The upper bound to of the pc values to scan. */ | |
537 | CORE_ADDR lim_pc; | |
538 | ||
456f8b9d DB |
539 | memset (gr_saved, 0, sizeof (gr_saved)); |
540 | ||
d40fcd7b KB |
541 | last_prologue_pc = pc; |
542 | ||
543 | /* Try to compute an upper limit (on how far to scan) based on the | |
544 | line number info. */ | |
545 | lim_pc = skip_prologue_using_sal (pc); | |
546 | /* If there's no line number info, lim_pc will be 0. In that case, | |
547 | set the limit to be 100 instructions away from pc. Hopefully, this | |
548 | will be far enough away to account for the entire prologue. Don't | |
549 | worry about overshooting the end of the function. The scan loop | |
550 | below contains some checks to avoid scanning unreasonably far. */ | |
551 | if (lim_pc == 0) | |
552 | lim_pc = pc + 400; | |
553 | ||
554 | /* If we have a frame, we don't want to scan past the frame's pc. This | |
555 | will catch those cases where the pc is in the prologue. */ | |
556 | if (next_frame) | |
557 | { | |
558 | CORE_ADDR frame_pc = frame_pc_unwind (next_frame); | |
559 | if (frame_pc < lim_pc) | |
560 | lim_pc = frame_pc; | |
561 | } | |
562 | ||
563 | /* Scan the prologue. */ | |
564 | while (pc < lim_pc) | |
456f8b9d DB |
565 | { |
566 | LONGEST op = read_memory_integer (pc, 4); | |
d40fcd7b | 567 | next_pc = pc + 4; |
456f8b9d DB |
568 | |
569 | /* The tests in this chain of ifs should be in order of | |
570 | decreasing selectivity, so that more particular patterns get | |
571 | to fire before less particular patterns. */ | |
572 | ||
d40fcd7b KB |
573 | /* Some sort of control transfer instruction: stop scanning prologue. |
574 | Integer Conditional Branch: | |
575 | X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX | |
576 | Floating-point / media Conditional Branch: | |
577 | X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX | |
578 | LCR Conditional Branch to LR | |
579 | X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX | |
580 | Integer conditional Branches to LR | |
581 | X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX | |
582 | X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX | |
583 | Floating-point/Media Branches to LR | |
584 | X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX | |
585 | X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX | |
586 | Jump and Link | |
587 | X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX | |
588 | X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX | |
589 | Call | |
590 | X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX | |
591 | Return from Trap | |
592 | X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX | |
593 | Integer Conditional Trap | |
594 | X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX | |
595 | X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX | |
596 | Floating-point /media Conditional Trap | |
597 | X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX | |
598 | X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX | |
599 | Break | |
600 | X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX | |
601 | Media Trap | |
602 | X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */ | |
603 | if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */ | |
604 | || (op & 0x01f80000) == 0x00300000 /* Jump and Link */ | |
605 | || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */ | |
606 | || (op & 0x01f80000) == 0x00700000) /* Trap immediate */ | |
607 | { | |
608 | /* Stop scanning; not in prologue any longer. */ | |
609 | break; | |
610 | } | |
611 | ||
612 | /* Loading something from memory into fp probably means that | |
613 | we're in the epilogue. Stop scanning the prologue. | |
614 | ld @(GRi, GRk), fp | |
615 | X 000010 0000010 XXXXXX 000100 XXXXXX | |
616 | ldi @(GRi, d12), fp | |
617 | X 000010 0110010 XXXXXX XXXXXXXXXXXX */ | |
618 | else if ((op & 0x7ffc0fc0) == 0x04080100 | |
619 | || (op & 0x7ffc0000) == 0x04c80000) | |
620 | { | |
621 | break; | |
622 | } | |
623 | ||
456f8b9d DB |
624 | /* Setting the FP from the SP: |
625 | ori sp, 0, fp | |
626 | P 000010 0100010 000001 000000000000 = 0x04881000 | |
627 | 0 111111 1111111 111111 111111111111 = 0x7fffffff | |
628 | . . . . . . . . | |
629 | We treat this as part of the prologue. */ | |
d40fcd7b | 630 | else if ((op & 0x7fffffff) == 0x04881000) |
456f8b9d DB |
631 | { |
632 | fp_set = 1; | |
633 | fp_offset = 0; | |
d40fcd7b | 634 | last_prologue_pc = next_pc; |
456f8b9d DB |
635 | } |
636 | ||
637 | /* Move the link register to the scratch register grJ, before saving: | |
638 | movsg lr, grJ | |
639 | P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0 | |
640 | 0 111111 1111111 111111 111111 000000 = 0x7fffffc0 | |
641 | . . . . . . . . | |
642 | We treat this as part of the prologue. */ | |
643 | else if ((op & 0x7fffffc0) == 0x080d01c0) | |
644 | { | |
645 | int gr_j = op & 0x3f; | |
646 | ||
647 | /* If we're moving it to a scratch register, that's fine. */ | |
648 | if (is_caller_saves_reg (gr_j)) | |
d40fcd7b KB |
649 | { |
650 | lr_save_reg = gr_j; | |
651 | last_prologue_pc = next_pc; | |
652 | } | |
456f8b9d DB |
653 | } |
654 | ||
655 | /* To save multiple callee-saves registers on the stack, at | |
656 | offset zero: | |
657 | ||
658 | std grK,@(sp,gr0) | |
659 | P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0 | |
660 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
661 | ||
662 | stq grK,@(sp,gr0) | |
663 | P KKKKKK 0000011 000001 000100 000000 = 0x000c1100 | |
664 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
665 | . . . . . . . . | |
666 | We treat this as part of the prologue, and record the register's | |
667 | saved address in the frame structure. */ | |
668 | else if ((op & 0x01ffffff) == 0x000c10c0 | |
669 | || (op & 0x01ffffff) == 0x000c1100) | |
670 | { | |
671 | int gr_k = ((op >> 25) & 0x3f); | |
672 | int ope = ((op >> 6) & 0x3f); | |
673 | int count; | |
674 | int i; | |
675 | ||
676 | /* Is it an std or an stq? */ | |
677 | if (ope == 0x03) | |
678 | count = 2; | |
679 | else | |
680 | count = 4; | |
681 | ||
682 | /* Is it really a callee-saves register? */ | |
683 | if (is_callee_saves_reg (gr_k)) | |
684 | { | |
685 | for (i = 0; i < count; i++) | |
686 | { | |
687 | gr_saved[gr_k + i] = 1; | |
688 | gr_sp_offset[gr_k + i] = 4 * i; | |
689 | } | |
d40fcd7b | 690 | last_prologue_pc = next_pc; |
456f8b9d | 691 | } |
456f8b9d DB |
692 | } |
693 | ||
694 | /* Adjusting the stack pointer. (The stack pointer is GR1.) | |
695 | addi sp, S, sp | |
696 | P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000 | |
697 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
698 | . . . . . . . . | |
699 | We treat this as part of the prologue. */ | |
700 | else if ((op & 0x7ffff000) == 0x02401000) | |
701 | { | |
d40fcd7b KB |
702 | if (framesize == 0) |
703 | { | |
704 | /* Sign-extend the twelve-bit field. | |
705 | (Isn't there a better way to do this?) */ | |
706 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
456f8b9d | 707 | |
d40fcd7b KB |
708 | framesize -= s; |
709 | last_prologue_pc = pc; | |
710 | } | |
711 | else | |
712 | { | |
713 | /* If the prologue is being adjusted again, we've | |
714 | likely gone too far; i.e. we're probably in the | |
715 | epilogue. */ | |
716 | break; | |
717 | } | |
456f8b9d DB |
718 | } |
719 | ||
720 | /* Setting the FP to a constant distance from the SP: | |
721 | addi sp, S, fp | |
722 | P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000 | |
723 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
724 | . . . . . . . . | |
725 | We treat this as part of the prologue. */ | |
726 | else if ((op & 0x7ffff000) == 0x04401000) | |
727 | { | |
728 | /* Sign-extend the twelve-bit field. | |
729 | (Isn't there a better way to do this?) */ | |
730 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
731 | fp_set = 1; | |
732 | fp_offset = s; | |
d40fcd7b | 733 | last_prologue_pc = pc; |
456f8b9d DB |
734 | } |
735 | ||
736 | /* To spill an argument register to a scratch register: | |
737 | ori GRi, 0, GRk | |
738 | P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000 | |
739 | 0 000000 1111111 000000 111111111111 = 0x01fc0fff | |
740 | . . . . . . . . | |
741 | For the time being, we treat this as a prologue instruction, | |
742 | assuming that GRi is an argument register. This one's kind | |
743 | of suspicious, because it seems like it could be part of a | |
744 | legitimate body instruction. But we only come here when the | |
745 | source info wasn't helpful, so we have to do the best we can. | |
746 | Hopefully once GCC and GDB agree on how to emit line number | |
747 | info for prologues, then this code will never come into play. */ | |
748 | else if ((op & 0x01fc0fff) == 0x00880000) | |
749 | { | |
750 | int gr_i = ((op >> 12) & 0x3f); | |
751 | ||
d40fcd7b KB |
752 | /* Make sure that the source is an arg register; if it is, we'll |
753 | treat it as a prologue instruction. */ | |
754 | if (is_argument_reg (gr_i)) | |
755 | last_prologue_pc = next_pc; | |
456f8b9d DB |
756 | } |
757 | ||
758 | /* To spill 16-bit values to the stack: | |
759 | sthi GRk, @(fp, s) | |
760 | P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000 | |
761 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
762 | . . . . . . . . | |
763 | And for 8-bit values, we use STB instructions. | |
764 | stbi GRk, @(fp, s) | |
765 | P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000 | |
766 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
767 | . . . . . . . . | |
768 | We check that GRk is really an argument register, and treat | |
769 | all such as part of the prologue. */ | |
770 | else if ( (op & 0x01fff000) == 0x01442000 | |
771 | || (op & 0x01fff000) == 0x01402000) | |
772 | { | |
773 | int gr_k = ((op >> 25) & 0x3f); | |
774 | ||
d40fcd7b KB |
775 | /* Make sure that GRk is really an argument register; treat |
776 | it as a prologue instruction if so. */ | |
777 | if (is_argument_reg (gr_k)) | |
778 | last_prologue_pc = next_pc; | |
456f8b9d DB |
779 | } |
780 | ||
781 | /* To save multiple callee-saves register on the stack, at a | |
782 | non-zero offset: | |
783 | ||
784 | stdi GRk, @(sp, s) | |
785 | P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000 | |
786 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
787 | . . . . . . . . | |
788 | stqi GRk, @(sp, s) | |
789 | P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000 | |
790 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
791 | . . . . . . . . | |
792 | We treat this as part of the prologue, and record the register's | |
793 | saved address in the frame structure. */ | |
794 | else if ((op & 0x01fff000) == 0x014c1000 | |
795 | || (op & 0x01fff000) == 0x01501000) | |
796 | { | |
797 | int gr_k = ((op >> 25) & 0x3f); | |
798 | int count; | |
799 | int i; | |
800 | ||
801 | /* Is it a stdi or a stqi? */ | |
802 | if ((op & 0x01fff000) == 0x014c1000) | |
803 | count = 2; | |
804 | else | |
805 | count = 4; | |
806 | ||
807 | /* Is it really a callee-saves register? */ | |
808 | if (is_callee_saves_reg (gr_k)) | |
809 | { | |
810 | /* Sign-extend the twelve-bit field. | |
811 | (Isn't there a better way to do this?) */ | |
812 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
813 | ||
814 | for (i = 0; i < count; i++) | |
815 | { | |
816 | gr_saved[gr_k + i] = 1; | |
817 | gr_sp_offset[gr_k + i] = s + (4 * i); | |
818 | } | |
d40fcd7b | 819 | last_prologue_pc = next_pc; |
456f8b9d | 820 | } |
456f8b9d DB |
821 | } |
822 | ||
823 | /* Storing any kind of integer register at any constant offset | |
824 | from any other register. | |
825 | ||
826 | st GRk, @(GRi, gr0) | |
827 | P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080 | |
828 | 0 000000 1111111 000000 111111 111111 = 0x01fc0fff | |
829 | . . . . . . . . | |
830 | sti GRk, @(GRi, d12) | |
831 | P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000 | |
832 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 | |
833 | . . . . . . . . | |
834 | These could be almost anything, but a lot of prologue | |
835 | instructions fall into this pattern, so let's decode the | |
836 | instruction once, and then work at a higher level. */ | |
837 | else if (((op & 0x01fc0fff) == 0x000c0080) | |
838 | || ((op & 0x01fc0000) == 0x01480000)) | |
839 | { | |
840 | int gr_k = ((op >> 25) & 0x3f); | |
841 | int gr_i = ((op >> 12) & 0x3f); | |
842 | int offset; | |
843 | ||
844 | /* Are we storing with gr0 as an offset, or using an | |
845 | immediate value? */ | |
846 | if ((op & 0x01fc0fff) == 0x000c0080) | |
847 | offset = 0; | |
848 | else | |
849 | offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
850 | ||
851 | /* If the address isn't relative to the SP or FP, it's not a | |
852 | prologue instruction. */ | |
853 | if (gr_i != sp_regnum && gr_i != fp_regnum) | |
d40fcd7b KB |
854 | { |
855 | /* Do nothing; not a prologue instruction. */ | |
856 | } | |
456f8b9d DB |
857 | |
858 | /* Saving the old FP in the new frame (relative to the SP). */ | |
d40fcd7b | 859 | else if (gr_k == fp_regnum && gr_i == sp_regnum) |
1cb761c7 KB |
860 | { |
861 | gr_saved[fp_regnum] = 1; | |
862 | gr_sp_offset[fp_regnum] = offset; | |
d40fcd7b | 863 | last_prologue_pc = next_pc; |
1cb761c7 | 864 | } |
456f8b9d DB |
865 | |
866 | /* Saving callee-saves register(s) on the stack, relative to | |
867 | the SP. */ | |
868 | else if (gr_i == sp_regnum | |
869 | && is_callee_saves_reg (gr_k)) | |
870 | { | |
871 | gr_saved[gr_k] = 1; | |
1cb761c7 KB |
872 | if (gr_i == sp_regnum) |
873 | gr_sp_offset[gr_k] = offset; | |
874 | else | |
875 | gr_sp_offset[gr_k] = offset + fp_offset; | |
d40fcd7b | 876 | last_prologue_pc = next_pc; |
456f8b9d DB |
877 | } |
878 | ||
879 | /* Saving the scratch register holding the return address. */ | |
880 | else if (lr_save_reg != -1 | |
881 | && gr_k == lr_save_reg) | |
1cb761c7 KB |
882 | { |
883 | lr_saved_on_stack = 1; | |
884 | if (gr_i == sp_regnum) | |
885 | lr_sp_offset = offset; | |
886 | else | |
887 | lr_sp_offset = offset + fp_offset; | |
d40fcd7b | 888 | last_prologue_pc = next_pc; |
1cb761c7 | 889 | } |
456f8b9d DB |
890 | |
891 | /* Spilling int-sized arguments to the stack. */ | |
892 | else if (is_argument_reg (gr_k)) | |
d40fcd7b | 893 | last_prologue_pc = next_pc; |
456f8b9d | 894 | } |
d40fcd7b | 895 | pc = next_pc; |
456f8b9d DB |
896 | } |
897 | ||
1cb761c7 | 898 | if (next_frame && info) |
456f8b9d | 899 | { |
1cb761c7 KB |
900 | int i; |
901 | ULONGEST this_base; | |
456f8b9d DB |
902 | |
903 | /* If we know the relationship between the stack and frame | |
904 | pointers, record the addresses of the registers we noticed. | |
905 | Note that we have to do this as a separate step at the end, | |
906 | because instructions may save relative to the SP, but we need | |
907 | their addresses relative to the FP. */ | |
908 | if (fp_set) | |
1cb761c7 KB |
909 | frame_unwind_unsigned_register (next_frame, fp_regnum, &this_base); |
910 | else | |
911 | frame_unwind_unsigned_register (next_frame, sp_regnum, &this_base); | |
456f8b9d | 912 | |
1cb761c7 KB |
913 | for (i = 0; i < 64; i++) |
914 | if (gr_saved[i]) | |
915 | info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i]; | |
456f8b9d | 916 | |
1cb761c7 KB |
917 | info->prev_sp = this_base - fp_offset + framesize; |
918 | info->base = this_base; | |
919 | ||
920 | /* If LR was saved on the stack, record its location. */ | |
921 | if (lr_saved_on_stack) | |
922 | info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset; | |
923 | ||
924 | /* The call instruction moves the caller's PC in the callee's LR. | |
925 | Since this is an unwind, do the reverse. Copy the location of LR | |
926 | into PC (the address / regnum) so that a request for PC will be | |
927 | converted into a request for the LR. */ | |
928 | info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum]; | |
929 | ||
930 | /* Save the previous frame's computed SP value. */ | |
931 | trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp); | |
456f8b9d DB |
932 | } |
933 | ||
d40fcd7b | 934 | return last_prologue_pc; |
456f8b9d DB |
935 | } |
936 | ||
937 | ||
938 | static CORE_ADDR | |
939 | frv_skip_prologue (CORE_ADDR pc) | |
940 | { | |
941 | CORE_ADDR func_addr, func_end, new_pc; | |
942 | ||
943 | new_pc = pc; | |
944 | ||
945 | /* If the line table has entry for a line *within* the function | |
946 | (i.e., not in the prologue, and not past the end), then that's | |
947 | our location. */ | |
948 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
949 | { | |
950 | struct symtab_and_line sal; | |
951 | ||
952 | sal = find_pc_line (func_addr, 0); | |
953 | ||
954 | if (sal.line != 0 && sal.end < func_end) | |
955 | { | |
956 | new_pc = sal.end; | |
957 | } | |
958 | } | |
959 | ||
960 | /* The FR-V prologue is at least five instructions long (twenty bytes). | |
961 | If we didn't find a real source location past that, then | |
962 | do a full analysis of the prologue. */ | |
963 | if (new_pc < pc + 20) | |
1cb761c7 | 964 | new_pc = frv_analyze_prologue (pc, 0, 0); |
456f8b9d DB |
965 | |
966 | return new_pc; | |
967 | } | |
968 | ||
1cb761c7 KB |
969 | |
970 | static struct frv_unwind_cache * | |
971 | frv_frame_unwind_cache (struct frame_info *next_frame, | |
972 | void **this_prologue_cache) | |
456f8b9d | 973 | { |
1cb761c7 KB |
974 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
975 | CORE_ADDR pc; | |
976 | ULONGEST prev_sp; | |
977 | ULONGEST this_base; | |
978 | struct frv_unwind_cache *info; | |
8baa6f92 | 979 | |
1cb761c7 KB |
980 | if ((*this_prologue_cache)) |
981 | return (*this_prologue_cache); | |
456f8b9d | 982 | |
1cb761c7 KB |
983 | info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache); |
984 | (*this_prologue_cache) = info; | |
985 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
456f8b9d | 986 | |
1cb761c7 KB |
987 | /* Prologue analysis does the rest... */ |
988 | frv_analyze_prologue (frame_func_unwind (next_frame), next_frame, info); | |
456f8b9d | 989 | |
1cb761c7 | 990 | return info; |
456f8b9d DB |
991 | } |
992 | ||
456f8b9d | 993 | static void |
cd31fb03 KB |
994 | frv_extract_return_value (struct type *type, struct regcache *regcache, |
995 | void *valbuf) | |
456f8b9d | 996 | { |
cd31fb03 KB |
997 | int len = TYPE_LENGTH (type); |
998 | ||
999 | if (len <= 4) | |
1000 | { | |
1001 | ULONGEST gpr8_val; | |
1002 | regcache_cooked_read_unsigned (regcache, 8, &gpr8_val); | |
1003 | store_unsigned_integer (valbuf, len, gpr8_val); | |
1004 | } | |
1005 | else if (len == 8) | |
1006 | { | |
1007 | ULONGEST regval; | |
1008 | regcache_cooked_read_unsigned (regcache, 8, ®val); | |
1009 | store_unsigned_integer (valbuf, 4, regval); | |
1010 | regcache_cooked_read_unsigned (regcache, 9, ®val); | |
1011 | store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval); | |
1012 | } | |
1013 | else | |
1014 | internal_error (__FILE__, __LINE__, "Illegal return value length: %d", len); | |
456f8b9d DB |
1015 | } |
1016 | ||
1017 | static CORE_ADDR | |
cd31fb03 | 1018 | frv_extract_struct_value_address (struct regcache *regcache) |
456f8b9d | 1019 | { |
cd31fb03 KB |
1020 | ULONGEST addr; |
1021 | regcache_cooked_read_unsigned (regcache, struct_return_regnum, &addr); | |
1022 | return addr; | |
456f8b9d DB |
1023 | } |
1024 | ||
1025 | static void | |
1026 | frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
1027 | { | |
1028 | write_register (struct_return_regnum, addr); | |
1029 | } | |
1030 | ||
1031 | static int | |
1032 | frv_frameless_function_invocation (struct frame_info *frame) | |
1033 | { | |
1034 | return frameless_look_for_prologue (frame); | |
1035 | } | |
1036 | ||
1cb761c7 KB |
1037 | static CORE_ADDR |
1038 | frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
456f8b9d | 1039 | { |
1cb761c7 | 1040 | /* Require dword alignment. */ |
5b03f266 | 1041 | return align_down (sp, 8); |
456f8b9d DB |
1042 | } |
1043 | ||
456f8b9d | 1044 | static CORE_ADDR |
1cb761c7 KB |
1045 | frv_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1046 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1047 | int nargs, struct value **args, CORE_ADDR sp, | |
1048 | int struct_return, CORE_ADDR struct_addr) | |
456f8b9d DB |
1049 | { |
1050 | int argreg; | |
1051 | int argnum; | |
1052 | char *val; | |
1053 | char valbuf[4]; | |
1054 | struct value *arg; | |
1055 | struct type *arg_type; | |
1056 | int len; | |
1057 | enum type_code typecode; | |
1058 | CORE_ADDR regval; | |
1059 | int stack_space; | |
1060 | int stack_offset; | |
1061 | ||
1062 | #if 0 | |
1063 | printf("Push %d args at sp = %x, struct_return=%d (%x)\n", | |
1064 | nargs, (int) sp, struct_return, struct_addr); | |
1065 | #endif | |
1066 | ||
1067 | stack_space = 0; | |
1068 | for (argnum = 0; argnum < nargs; ++argnum) | |
5b03f266 | 1069 | stack_space += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4); |
456f8b9d DB |
1070 | |
1071 | stack_space -= (6 * 4); | |
1072 | if (stack_space > 0) | |
1073 | sp -= stack_space; | |
1074 | ||
1075 | /* Make sure stack is dword aligned. */ | |
5b03f266 | 1076 | sp = align_down (sp, 8); |
456f8b9d DB |
1077 | |
1078 | stack_offset = 0; | |
1079 | ||
1080 | argreg = 8; | |
1081 | ||
1082 | if (struct_return) | |
1cb761c7 KB |
1083 | regcache_cooked_write_unsigned (regcache, struct_return_regnum, |
1084 | struct_addr); | |
456f8b9d DB |
1085 | |
1086 | for (argnum = 0; argnum < nargs; ++argnum) | |
1087 | { | |
1088 | arg = args[argnum]; | |
1089 | arg_type = check_typedef (VALUE_TYPE (arg)); | |
1090 | len = TYPE_LENGTH (arg_type); | |
1091 | typecode = TYPE_CODE (arg_type); | |
1092 | ||
1093 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
1094 | { | |
fbd9dcd3 | 1095 | store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg)); |
456f8b9d DB |
1096 | typecode = TYPE_CODE_PTR; |
1097 | len = 4; | |
1098 | val = valbuf; | |
1099 | } | |
1100 | else | |
1101 | { | |
1102 | val = (char *) VALUE_CONTENTS (arg); | |
1103 | } | |
1104 | ||
1105 | while (len > 0) | |
1106 | { | |
1107 | int partial_len = (len < 4 ? len : 4); | |
1108 | ||
1109 | if (argreg < 14) | |
1110 | { | |
7c0b4a20 | 1111 | regval = extract_unsigned_integer (val, partial_len); |
456f8b9d DB |
1112 | #if 0 |
1113 | printf(" Argnum %d data %x -> reg %d\n", | |
1114 | argnum, (int) regval, argreg); | |
1115 | #endif | |
1cb761c7 | 1116 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
456f8b9d DB |
1117 | ++argreg; |
1118 | } | |
1119 | else | |
1120 | { | |
1121 | #if 0 | |
1122 | printf(" Argnum %d data %x -> offset %d (%x)\n", | |
1123 | argnum, *((int *)val), stack_offset, (int) (sp + stack_offset)); | |
1124 | #endif | |
1125 | write_memory (sp + stack_offset, val, partial_len); | |
5b03f266 | 1126 | stack_offset += align_up (partial_len, 4); |
456f8b9d DB |
1127 | } |
1128 | len -= partial_len; | |
1129 | val += partial_len; | |
1130 | } | |
1131 | } | |
456f8b9d | 1132 | |
1cb761c7 KB |
1133 | /* Set the return address. For the frv, the return breakpoint is |
1134 | always at BP_ADDR. */ | |
1135 | regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr); | |
1136 | ||
1137 | /* Finally, update the SP register. */ | |
1138 | regcache_cooked_write_unsigned (regcache, sp_regnum, sp); | |
1139 | ||
456f8b9d DB |
1140 | return sp; |
1141 | } | |
1142 | ||
1143 | static void | |
cd31fb03 KB |
1144 | frv_store_return_value (struct type *type, struct regcache *regcache, |
1145 | const void *valbuf) | |
456f8b9d | 1146 | { |
cd31fb03 KB |
1147 | int len = TYPE_LENGTH (type); |
1148 | ||
1149 | if (len <= 4) | |
1150 | { | |
1151 | bfd_byte val[4]; | |
1152 | memset (val, 0, sizeof (val)); | |
1153 | memcpy (val + (4 - len), valbuf, len); | |
1154 | regcache_cooked_write (regcache, 8, val); | |
1155 | } | |
1156 | else if (len == 8) | |
1157 | { | |
1158 | regcache_cooked_write (regcache, 8, valbuf); | |
1159 | regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4); | |
1160 | } | |
456f8b9d DB |
1161 | else |
1162 | internal_error (__FILE__, __LINE__, | |
cd31fb03 | 1163 | "Don't know how to return a %d-byte value.", len); |
456f8b9d DB |
1164 | } |
1165 | ||
456f8b9d | 1166 | |
456f8b9d DB |
1167 | /* Hardware watchpoint / breakpoint support for the FR500 |
1168 | and FR400. */ | |
1169 | ||
1170 | int | |
1171 | frv_check_watch_resources (int type, int cnt, int ot) | |
1172 | { | |
1173 | struct gdbarch_tdep *var = CURRENT_VARIANT; | |
1174 | ||
1175 | /* Watchpoints not supported on simulator. */ | |
1176 | if (strcmp (target_shortname, "sim") == 0) | |
1177 | return 0; | |
1178 | ||
1179 | if (type == bp_hardware_breakpoint) | |
1180 | { | |
1181 | if (var->num_hw_breakpoints == 0) | |
1182 | return 0; | |
1183 | else if (cnt <= var->num_hw_breakpoints) | |
1184 | return 1; | |
1185 | } | |
1186 | else | |
1187 | { | |
1188 | if (var->num_hw_watchpoints == 0) | |
1189 | return 0; | |
1190 | else if (ot) | |
1191 | return -1; | |
1192 | else if (cnt <= var->num_hw_watchpoints) | |
1193 | return 1; | |
1194 | } | |
1195 | return -1; | |
1196 | } | |
1197 | ||
1198 | ||
1199 | CORE_ADDR | |
5ae5f592 | 1200 | frv_stopped_data_address (void) |
456f8b9d DB |
1201 | { |
1202 | CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3; | |
1203 | ||
1204 | brr = read_register (brr_regnum); | |
1205 | dbar0 = read_register (dbar0_regnum); | |
1206 | dbar1 = read_register (dbar1_regnum); | |
1207 | dbar2 = read_register (dbar2_regnum); | |
1208 | dbar3 = read_register (dbar3_regnum); | |
1209 | ||
1210 | if (brr & (1<<11)) | |
1211 | return dbar0; | |
1212 | else if (brr & (1<<10)) | |
1213 | return dbar1; | |
1214 | else if (brr & (1<<9)) | |
1215 | return dbar2; | |
1216 | else if (brr & (1<<8)) | |
1217 | return dbar3; | |
1218 | else | |
1219 | return 0; | |
1220 | } | |
1221 | ||
1cb761c7 KB |
1222 | static CORE_ADDR |
1223 | frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1224 | { | |
1225 | return frame_unwind_register_unsigned (next_frame, pc_regnum); | |
1226 | } | |
1227 | ||
1228 | /* Given a GDB frame, determine the address of the calling function's | |
1229 | frame. This will be used to create a new GDB frame struct. */ | |
1230 | ||
1231 | static void | |
1232 | frv_frame_this_id (struct frame_info *next_frame, | |
1233 | void **this_prologue_cache, struct frame_id *this_id) | |
1234 | { | |
1235 | struct frv_unwind_cache *info | |
1236 | = frv_frame_unwind_cache (next_frame, this_prologue_cache); | |
1237 | CORE_ADDR base; | |
1238 | CORE_ADDR func; | |
1239 | struct minimal_symbol *msym_stack; | |
1240 | struct frame_id id; | |
1241 | ||
1242 | /* The FUNC is easy. */ | |
1243 | func = frame_func_unwind (next_frame); | |
1244 | ||
1cb761c7 KB |
1245 | /* Check if the stack is empty. */ |
1246 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
1247 | if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) | |
1248 | return; | |
1249 | ||
1250 | /* Hopefully the prologue analysis either correctly determined the | |
1251 | frame's base (which is the SP from the previous frame), or set | |
1252 | that base to "NULL". */ | |
1253 | base = info->prev_sp; | |
1254 | if (base == 0) | |
1255 | return; | |
1256 | ||
1257 | id = frame_id_build (base, func); | |
1258 | ||
1259 | /* Check that we're not going round in circles with the same frame | |
1260 | ID (but avoid applying the test to sentinel frames which do go | |
1261 | round in circles). Can't use frame_id_eq() as that doesn't yet | |
1262 | compare the frame's PC value. */ | |
1263 | if (frame_relative_level (next_frame) >= 0 | |
1264 | && get_frame_type (next_frame) != DUMMY_FRAME | |
1265 | && frame_id_eq (get_frame_id (next_frame), id)) | |
1266 | return; | |
1267 | ||
1268 | (*this_id) = id; | |
1269 | } | |
1270 | ||
1271 | static void | |
1272 | frv_frame_prev_register (struct frame_info *next_frame, | |
1273 | void **this_prologue_cache, | |
1274 | int regnum, int *optimizedp, | |
1275 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1276 | int *realnump, void *bufferp) | |
1277 | { | |
1278 | struct frv_unwind_cache *info | |
1279 | = frv_frame_unwind_cache (next_frame, this_prologue_cache); | |
1280 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
1281 | optimizedp, lvalp, addrp, realnump, bufferp); | |
1282 | } | |
1283 | ||
1284 | static const struct frame_unwind frv_frame_unwind = { | |
1285 | NORMAL_FRAME, | |
1286 | frv_frame_this_id, | |
1287 | frv_frame_prev_register | |
1288 | }; | |
1289 | ||
1290 | static const struct frame_unwind * | |
1291 | frv_frame_sniffer (struct frame_info *next_frame) | |
1292 | { | |
1293 | return &frv_frame_unwind; | |
1294 | } | |
1295 | ||
1296 | static CORE_ADDR | |
1297 | frv_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1298 | { | |
1299 | struct frv_unwind_cache *info | |
1300 | = frv_frame_unwind_cache (next_frame, this_cache); | |
1301 | return info->base; | |
1302 | } | |
1303 | ||
1304 | static const struct frame_base frv_frame_base = { | |
1305 | &frv_frame_unwind, | |
1306 | frv_frame_base_address, | |
1307 | frv_frame_base_address, | |
1308 | frv_frame_base_address | |
1309 | }; | |
1310 | ||
1311 | static CORE_ADDR | |
1312 | frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1313 | { | |
1314 | return frame_unwind_register_unsigned (next_frame, sp_regnum); | |
1315 | } | |
1316 | ||
1317 | ||
1318 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
1319 | dummy frame. The frame ID's base needs to match the TOS value | |
1320 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1321 | breakpoint. */ | |
1322 | ||
1323 | static struct frame_id | |
1324 | frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1325 | { | |
1326 | return frame_id_build (frv_unwind_sp (gdbarch, next_frame), | |
1327 | frame_pc_unwind (next_frame)); | |
1328 | } | |
1329 | ||
1330 | ||
456f8b9d DB |
1331 | static struct gdbarch * |
1332 | frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1333 | { | |
1334 | struct gdbarch *gdbarch; | |
1335 | struct gdbarch_tdep *var; | |
1336 | ||
1337 | /* Check to see if we've already built an appropriate architecture | |
1338 | object for this executable. */ | |
1339 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1340 | if (arches) | |
1341 | return arches->gdbarch; | |
1342 | ||
1343 | /* Select the right tdep structure for this variant. */ | |
1344 | var = new_variant (); | |
1345 | switch (info.bfd_arch_info->mach) | |
1346 | { | |
1347 | case bfd_mach_frv: | |
1348 | case bfd_mach_frvsimple: | |
1349 | case bfd_mach_fr500: | |
1350 | case bfd_mach_frvtomcat: | |
251a3ae3 | 1351 | case bfd_mach_fr550: |
456f8b9d DB |
1352 | set_variant_num_gprs (var, 64); |
1353 | set_variant_num_fprs (var, 64); | |
1354 | break; | |
1355 | ||
1356 | case bfd_mach_fr400: | |
1357 | set_variant_num_gprs (var, 32); | |
1358 | set_variant_num_fprs (var, 32); | |
1359 | break; | |
1360 | ||
1361 | default: | |
1362 | /* Never heard of this variant. */ | |
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | gdbarch = gdbarch_alloc (&info, var); | |
1367 | ||
1368 | set_gdbarch_short_bit (gdbarch, 16); | |
1369 | set_gdbarch_int_bit (gdbarch, 32); | |
1370 | set_gdbarch_long_bit (gdbarch, 32); | |
1371 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1372 | set_gdbarch_float_bit (gdbarch, 32); | |
1373 | set_gdbarch_double_bit (gdbarch, 64); | |
1374 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1375 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1376 | ||
1377 | set_gdbarch_num_regs (gdbarch, frv_num_regs); | |
6a748db6 KB |
1378 | set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs); |
1379 | ||
456f8b9d | 1380 | set_gdbarch_sp_regnum (gdbarch, sp_regnum); |
0ba6dca9 | 1381 | set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum); |
456f8b9d DB |
1382 | set_gdbarch_pc_regnum (gdbarch, pc_regnum); |
1383 | ||
1384 | set_gdbarch_register_name (gdbarch, frv_register_name); | |
7f398216 | 1385 | set_gdbarch_register_type (gdbarch, frv_register_type); |
526eef89 | 1386 | set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno); |
456f8b9d | 1387 | |
6a748db6 KB |
1388 | set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read); |
1389 | set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write); | |
1390 | ||
456f8b9d DB |
1391 | set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue); |
1392 | set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc); | |
46a16dba | 1393 | set_gdbarch_adjust_breakpoint_address (gdbarch, frv_gdbarch_adjust_breakpoint_address); |
456f8b9d | 1394 | |
456f8b9d DB |
1395 | set_gdbarch_frame_args_skip (gdbarch, 0); |
1396 | set_gdbarch_frameless_function_invocation (gdbarch, frv_frameless_function_invocation); | |
1397 | ||
1fd35568 | 1398 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
cd31fb03 | 1399 | set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value); |
456f8b9d | 1400 | |
4183d812 | 1401 | set_gdbarch_deprecated_store_struct_return (gdbarch, frv_store_struct_return); |
cd31fb03 KB |
1402 | set_gdbarch_store_return_value (gdbarch, frv_store_return_value); |
1403 | set_gdbarch_extract_struct_value_address (gdbarch, frv_extract_struct_value_address); | |
456f8b9d | 1404 | |
1cb761c7 KB |
1405 | /* Frame stuff. */ |
1406 | set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc); | |
1407 | set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp); | |
1408 | set_gdbarch_frame_align (gdbarch, frv_frame_align); | |
1409 | frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer); | |
1410 | frame_base_set_default (gdbarch, &frv_frame_base); | |
456f8b9d | 1411 | |
1cb761c7 KB |
1412 | /* Settings for calling functions in the inferior. */ |
1413 | set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call); | |
1414 | set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id); | |
456f8b9d DB |
1415 | |
1416 | /* Settings that should be unnecessary. */ | |
1417 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1418 | ||
456f8b9d | 1419 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
456f8b9d | 1420 | |
456f8b9d | 1421 | set_gdbarch_remote_translate_xfer_address |
aed7f26a | 1422 | (gdbarch, generic_remote_translate_xfer_address); |
456f8b9d DB |
1423 | |
1424 | /* Hardware watchpoint / breakpoint support. */ | |
1425 | switch (info.bfd_arch_info->mach) | |
1426 | { | |
1427 | case bfd_mach_frv: | |
1428 | case bfd_mach_frvsimple: | |
1429 | case bfd_mach_fr500: | |
1430 | case bfd_mach_frvtomcat: | |
1431 | /* fr500-style hardware debugging support. */ | |
1432 | var->num_hw_watchpoints = 4; | |
1433 | var->num_hw_breakpoints = 4; | |
1434 | break; | |
1435 | ||
1436 | case bfd_mach_fr400: | |
1437 | /* fr400-style hardware debugging support. */ | |
1438 | var->num_hw_watchpoints = 2; | |
1439 | var->num_hw_breakpoints = 4; | |
1440 | break; | |
1441 | ||
1442 | default: | |
1443 | /* Otherwise, assume we don't have hardware debugging support. */ | |
1444 | var->num_hw_watchpoints = 0; | |
1445 | var->num_hw_breakpoints = 0; | |
1446 | break; | |
1447 | } | |
1448 | ||
36482093 AC |
1449 | set_gdbarch_print_insn (gdbarch, print_insn_frv); |
1450 | ||
456f8b9d DB |
1451 | return gdbarch; |
1452 | } | |
1453 | ||
1454 | void | |
1455 | _initialize_frv_tdep (void) | |
1456 | { | |
1457 | register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init); | |
456f8b9d | 1458 | } |