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e6f9de87 DE |
1 | /* Debug register code for the i386. |
2 | ||
ecd75fc8 | 3 | Copyright (C) 2009-2014 Free Software Foundation, Inc. |
e6f9de87 DE |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "server.h" | |
21 | #include "target.h" | |
22 | #include "i386-low.h" | |
23 | ||
6e62758f GB |
24 | /* Support for hardware watchpoints and breakpoints using the i386 |
25 | debug registers. | |
26 | ||
27 | This provides several functions for inserting and removing | |
28 | hardware-assisted breakpoints and watchpoints, testing if one or | |
29 | more of the watchpoints triggered and at what address, checking | |
30 | whether a given region can be watched, etc. | |
31 | ||
32 | The functions below implement debug registers sharing by reference | |
33 | counts, and allow to watch regions up to 16 bytes long. */ | |
34 | ||
1b6d4134 GB |
35 | /* Support for 8-byte wide hw watchpoints. */ |
36 | #define TARGET_HAS_DR_LEN_8 (i386_get_debug_register_length () == 8) | |
e6f9de87 | 37 | |
e6f9de87 DE |
38 | /* DR7 Debug Control register fields. */ |
39 | ||
40 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
41 | #define DR_CONTROL_SHIFT 16 | |
42 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
43 | #define DR_CONTROL_SIZE 4 | |
44 | ||
45 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
46 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ | |
47 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
48 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
49 | ||
50 | /* This is here for completeness. No platform supports this | |
51 | functionality yet (as of March 2001). Note that the DE flag in the | |
52 | CR4 register needs to be set to support this. */ | |
53 | #ifndef DR_RW_IORW | |
54 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ | |
55 | #endif | |
56 | ||
57 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
58 | is so we could OR this with the read/write field defined above. */ | |
59 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ | |
60 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
61 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
62 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
63 | ||
64 | /* Local and Global Enable flags in DR7. | |
65 | ||
66 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
67 | enabled only for the current task; the processor automatically | |
68 | clears this flag on every task switch. When the Global Enable flag | |
69 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
70 | processor never clears this flag. | |
71 | ||
72 | Currently, all watchpoint are locally enabled. If you need to | |
73 | enable them globally, read the comment which pertains to this in | |
4be83cc2 | 74 | i386_dr_insert_aligned_watchpoint below. */ |
e6f9de87 DE |
75 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
76 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
77 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
78 | ||
79 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
80 | flags). These are only required on i386, to allow detection of the | |
81 | exact instruction which caused a watchpoint to break; i486 and | |
82 | later processors do that automatically. We set these flags for | |
83 | backwards compatibility. */ | |
84 | #define DR_LOCAL_SLOWDOWN (0x100) | |
85 | #define DR_GLOBAL_SLOWDOWN (0x200) | |
86 | ||
87 | /* Fields reserved by Intel. This includes the GD (General Detect | |
88 | Enable) flag, which causes a debug exception to be generated when a | |
89 | MOV instruction accesses one of the debug registers. | |
90 | ||
91 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
92 | #define DR_CONTROL_RESERVED (0xFC00) | |
93 | ||
94 | /* Auxiliary helper macros. */ | |
95 | ||
96 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
97 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) | |
98 | ||
99 | /* The I'th debug register is vacant if its Local and Global Enable | |
100 | bits are reset in the Debug Control register. */ | |
101 | #define I386_DR_VACANT(state, i) \ | |
102 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
103 | ||
104 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
105 | #define I386_DR_LOCAL_ENABLE(state, i) \ | |
106 | do { \ | |
107 | (state)->dr_control_mirror |= \ | |
108 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
109 | } while (0) | |
110 | ||
111 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
112 | #define I386_DR_GLOBAL_ENABLE(state, i) \ | |
113 | do { \ | |
114 | (state)->dr_control_mirror |= \ | |
115 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
116 | } while (0) | |
117 | ||
118 | /* Disable the break/watchpoint in the I'th debug register. */ | |
119 | #define I386_DR_DISABLE(state, i) \ | |
120 | do { \ | |
121 | (state)->dr_control_mirror &= \ | |
122 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
123 | } while (0) | |
124 | ||
125 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
fc6e2f03 | 126 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ |
e6f9de87 DE |
127 | do { \ |
128 | (state)->dr_control_mirror &= \ | |
129 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
130 | (state)->dr_control_mirror |= \ | |
131 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
132 | } while (0) | |
133 | ||
134 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
964e4306 PA |
135 | #define I386_DR_GET_RW_LEN(dr7, i) \ |
136 | (((dr7) \ | |
e6f9de87 DE |
137 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) |
138 | ||
139 | /* Did the watchpoint whose address is in the I'th register break? */ | |
964e4306 | 140 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
e6f9de87 | 141 | |
e6f9de87 DE |
142 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ |
143 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
fc6e2f03 | 144 | |
e6f9de87 DE |
145 | /* Implementation. */ |
146 | ||
147 | /* Clear the reference counts and forget everything we knew about the | |
148 | debug registers. */ | |
149 | ||
150 | void | |
151 | i386_low_init_dregs (struct i386_debug_reg_state *state) | |
152 | { | |
153 | int i; | |
154 | ||
155 | ALL_DEBUG_REGISTERS (i) | |
156 | { | |
157 | state->dr_mirror[i] = 0; | |
158 | state->dr_ref_count[i] = 0; | |
159 | } | |
160 | state->dr_control_mirror = 0; | |
161 | state->dr_status_mirror = 0; | |
162 | } | |
163 | ||
6e62758f | 164 | /* Print the values of the mirrored debug registers. */ |
e6f9de87 | 165 | |
4be83cc2 GB |
166 | void |
167 | i386_dr_show (struct i386_debug_reg_state *state, | |
e6f9de87 DE |
168 | const char *func, CORE_ADDR addr, |
169 | int len, enum target_hw_bp_type type) | |
170 | { | |
171 | int i; | |
172 | ||
1b6d4134 | 173 | debug_printf ("%s", func); |
e6f9de87 | 174 | if (addr || len) |
1b6d4134 GB |
175 | debug_printf (" (addr=%s, len=%d, type=%s)", |
176 | phex (addr, 8), len, | |
177 | type == hw_write ? "data-write" | |
178 | : (type == hw_read ? "data-read" | |
179 | : (type == hw_access ? "data-read/write" | |
180 | : (type == hw_execute ? "instruction-execute" | |
181 | /* FIXME: if/when I/O read/write | |
182 | watchpoints are supported, add them | |
183 | here. */ | |
184 | : "??unknown??")))); | |
185 | debug_printf (":\n"); | |
186 | debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", | |
187 | phex (state->dr_control_mirror, 8), | |
188 | phex (state->dr_status_mirror, 8)); | |
e6f9de87 DE |
189 | ALL_DEBUG_REGISTERS (i) |
190 | { | |
1b6d4134 | 191 | debug_printf ("\ |
e6f9de87 | 192 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", |
1b6d4134 GB |
193 | i, phex (state->dr_mirror[i], |
194 | i386_get_debug_register_length ()), | |
195 | state->dr_ref_count[i], | |
196 | i + 1, phex (state->dr_mirror[i + 1], | |
197 | i386_get_debug_register_length ()), | |
198 | state->dr_ref_count[i + 1]); | |
e6f9de87 DE |
199 | i++; |
200 | } | |
201 | } | |
202 | ||
203 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
204 | region of LEN bytes for accesses of type TYPE. LEN is assumed to | |
205 | have the value of 1, 2, or 4. */ | |
206 | ||
4be83cc2 GB |
207 | unsigned |
208 | i386_dr_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
e6f9de87 DE |
209 | { |
210 | unsigned rw; | |
211 | ||
212 | switch (type) | |
213 | { | |
214 | case hw_execute: | |
215 | rw = DR_RW_EXECUTE; | |
216 | break; | |
217 | case hw_write: | |
218 | rw = DR_RW_WRITE; | |
219 | break; | |
220 | case hw_read: | |
e927c9fc GB |
221 | internal_error (__FILE__, __LINE__, |
222 | _("The i386 doesn't support " | |
223 | "data-read watchpoints.\n")); | |
e6f9de87 DE |
224 | case hw_access: |
225 | rw = DR_RW_READ; | |
226 | break; | |
227 | #if 0 | |
228 | /* Not yet supported. */ | |
229 | case hw_io_access: | |
230 | rw = DR_RW_IORW; | |
231 | break; | |
232 | #endif | |
233 | default: | |
e927c9fc | 234 | internal_error (__FILE__, __LINE__, _("\ |
4be83cc2 | 235 | Invalid hardware breakpoint type %d in i386_dr_length_and_rw_bits.\n"), |
e6f9de87 DE |
236 | (int) type); |
237 | } | |
238 | ||
239 | switch (len) | |
240 | { | |
241 | case 1: | |
242 | return (DR_LEN_1 | rw); | |
243 | case 2: | |
244 | return (DR_LEN_2 | rw); | |
245 | case 4: | |
246 | return (DR_LEN_4 | rw); | |
247 | case 8: | |
248 | if (TARGET_HAS_DR_LEN_8) | |
249 | return (DR_LEN_8 | rw); | |
96f7a20f | 250 | /* ELSE FALL THROUGH */ |
e6f9de87 | 251 | default: |
e927c9fc | 252 | internal_error (__FILE__, __LINE__, _("\ |
4be83cc2 | 253 | Invalid hardware breakpoint length %d in i386_dr_length_and_rw_bits.\n"), len); |
e6f9de87 DE |
254 | } |
255 | } | |
256 | ||
257 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
258 | according to the length of the region to watch. LEN_RW_BITS is the | |
259 | value of the bits from DR7 which describes the length and access | |
260 | type of the region to be watched by this watchpoint. Return 0 on | |
261 | success, -1 on failure. */ | |
262 | ||
4be83cc2 GB |
263 | int |
264 | i386_dr_insert_aligned_watchpoint (struct i386_debug_reg_state *state, | |
265 | CORE_ADDR addr, unsigned len_rw_bits) | |
e6f9de87 DE |
266 | { |
267 | int i; | |
268 | ||
131aa0d4 GB |
269 | if (!i386_dr_low_can_set_addr () || !i386_dr_low_can_set_control ()) |
270 | return -1; | |
271 | ||
e6f9de87 DE |
272 | /* First, look for an occupied debug register with the same address |
273 | and the same RW and LEN definitions. If we find one, we can | |
274 | reuse it for this watchpoint as well (and save a register). */ | |
275 | ALL_DEBUG_REGISTERS (i) | |
276 | { | |
277 | if (!I386_DR_VACANT (state, i) | |
278 | && state->dr_mirror[i] == addr | |
964e4306 | 279 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) |
e6f9de87 DE |
280 | { |
281 | state->dr_ref_count[i]++; | |
282 | return 0; | |
283 | } | |
284 | } | |
285 | ||
286 | /* Next, look for a vacant debug register. */ | |
287 | ALL_DEBUG_REGISTERS (i) | |
288 | { | |
289 | if (I386_DR_VACANT (state, i)) | |
290 | break; | |
291 | } | |
292 | ||
293 | /* No more debug registers! */ | |
294 | if (i >= DR_NADDR) | |
295 | return -1; | |
296 | ||
297 | /* Now set up the register I to watch our region. */ | |
298 | ||
299 | /* Record the info in our local mirrored array. */ | |
300 | state->dr_mirror[i] = addr; | |
301 | state->dr_ref_count[i] = 1; | |
302 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
303 | /* Note: we only enable the watchpoint locally, i.e. in the current | |
304 | task. Currently, no i386 target allows or supports global | |
305 | watchpoints; however, if any target would want that in the | |
306 | future, GDB should probably provide a command to control whether | |
307 | to enable watchpoints globally or locally, and the code below | |
308 | should use global or local enable and slow-down flags as | |
309 | appropriate. */ | |
310 | I386_DR_LOCAL_ENABLE (state, i); | |
311 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
312 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
313 | ||
e6f9de87 DE |
314 | return 0; |
315 | } | |
316 | ||
317 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
318 | according to the length of the region to watch. LEN_RW_BITS is the | |
319 | value of the bits from DR7 which describes the length and access | |
320 | type of the region watched by this watchpoint. Return 0 on | |
321 | success, -1 on failure. */ | |
322 | ||
4be83cc2 GB |
323 | int |
324 | i386_dr_remove_aligned_watchpoint (struct i386_debug_reg_state *state, | |
325 | CORE_ADDR addr, unsigned len_rw_bits) | |
e6f9de87 DE |
326 | { |
327 | int i, retval = -1; | |
328 | ||
329 | ALL_DEBUG_REGISTERS (i) | |
330 | { | |
331 | if (!I386_DR_VACANT (state, i) | |
332 | && state->dr_mirror[i] == addr | |
964e4306 | 333 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) |
e6f9de87 DE |
334 | { |
335 | if (--state->dr_ref_count[i] == 0) /* No longer in use? */ | |
336 | { | |
337 | /* Reset our mirror. */ | |
338 | state->dr_mirror[i] = 0; | |
339 | I386_DR_DISABLE (state, i); | |
e6f9de87 DE |
340 | } |
341 | retval = 0; | |
342 | } | |
343 | } | |
344 | ||
345 | return retval; | |
346 | } | |
347 | ||
348 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
349 | number of debug registers required to watch a region at address | |
350 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
351 | successful insertion or removal, a positive number when queried | |
352 | about the number of registers, or -1 on failure. If WHAT is not a | |
353 | valid value, bombs through internal_error. */ | |
354 | ||
355 | static int | |
356 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, | |
357 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
358 | enum target_hw_bp_type type) | |
359 | { | |
1ced966e | 360 | int retval = 0; |
e6f9de87 DE |
361 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
362 | ||
363 | static const int size_try_array[8][8] = | |
364 | { | |
365 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ | |
366 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
367 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
368 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
369 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
370 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
371 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
372 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
373 | }; | |
374 | ||
375 | while (len > 0) | |
376 | { | |
377 | int align = addr % max_wp_len; | |
378 | /* Four (eight on AMD64) is the maximum length a debug register | |
379 | can watch. */ | |
380 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); | |
381 | int size = size_try_array[try][align]; | |
382 | ||
383 | if (what == WP_COUNT) | |
384 | { | |
385 | /* size_try_array[] is defined such that each iteration | |
386 | through the loop is guaranteed to produce an address and a | |
387 | size that can be watched with a single debug register. | |
388 | Thus, for counting the registers required to watch a | |
389 | region, we simply need to increment the count on each | |
390 | iteration. */ | |
391 | retval++; | |
392 | } | |
393 | else | |
394 | { | |
4be83cc2 | 395 | unsigned len_rw = i386_dr_length_and_rw_bits (size, type); |
e6f9de87 DE |
396 | |
397 | if (what == WP_INSERT) | |
4be83cc2 | 398 | retval = i386_dr_insert_aligned_watchpoint (state, addr, len_rw); |
e6f9de87 | 399 | else if (what == WP_REMOVE) |
4be83cc2 | 400 | retval = i386_dr_remove_aligned_watchpoint (state, addr, len_rw); |
e6f9de87 | 401 | else |
e927c9fc GB |
402 | internal_error (__FILE__, __LINE__, _("\ |
403 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
404 | (int) what); | |
1ced966e PA |
405 | if (retval) |
406 | break; | |
e6f9de87 DE |
407 | } |
408 | ||
409 | addr += size; | |
410 | len -= size; | |
411 | } | |
412 | ||
413 | return retval; | |
414 | } | |
415 | ||
d9305f7f | 416 | /* Update the inferior debug registers state, in STATE, with the |
1ced966e PA |
417 | new debug registers state, in NEW_STATE. */ |
418 | ||
4be83cc2 GB |
419 | void |
420 | i386_dr_update_inferior_debug_regs (struct i386_debug_reg_state *state, | |
421 | struct i386_debug_reg_state *new_state) | |
1ced966e PA |
422 | { |
423 | int i; | |
424 | ||
425 | ALL_DEBUG_REGISTERS (i) | |
426 | { | |
d9305f7f | 427 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (state, i)) |
1ced966e PA |
428 | i386_dr_low_set_addr (new_state, i); |
429 | else | |
d9305f7f | 430 | gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); |
1ced966e PA |
431 | } |
432 | ||
d9305f7f | 433 | if (new_state->dr_control_mirror != state->dr_control_mirror) |
1ced966e PA |
434 | i386_dr_low_set_control (new_state); |
435 | ||
d9305f7f | 436 | *state = *new_state; |
1ced966e PA |
437 | } |
438 | ||
e6f9de87 DE |
439 | /* Insert a watchpoint to watch a memory region which starts at |
440 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
6e62758f | 441 | of the type TYPE. Return 0 on success, -1 on failure. */ |
e6f9de87 DE |
442 | |
443 | int | |
4be83cc2 GB |
444 | i386_dr_insert_watchpoint (struct i386_debug_reg_state *state, |
445 | enum target_hw_bp_type type, | |
446 | CORE_ADDR addr, int len) | |
e6f9de87 DE |
447 | { |
448 | int retval; | |
1ced966e PA |
449 | /* Work on a local copy of the debug registers, and on success, |
450 | commit the change back to the inferior. */ | |
451 | struct i386_debug_reg_state local_state = *state; | |
e6f9de87 | 452 | |
85d721b8 PA |
453 | if (type == hw_read) |
454 | return 1; /* unsupported */ | |
455 | ||
e6f9de87 DE |
456 | if (((len != 1 && len != 2 && len != 4) |
457 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
458 | || addr % len != 0) | |
459 | { | |
fc6e2f03 GB |
460 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
461 | WP_INSERT, | |
e6f9de87 DE |
462 | addr, len, type); |
463 | } | |
464 | else | |
465 | { | |
4be83cc2 | 466 | unsigned len_rw = i386_dr_length_and_rw_bits (len, type); |
e6f9de87 | 467 | |
4be83cc2 | 468 | retval = i386_dr_insert_aligned_watchpoint (&local_state, |
fc6e2f03 | 469 | addr, len_rw); |
e6f9de87 DE |
470 | } |
471 | ||
1ced966e | 472 | if (retval == 0) |
4be83cc2 | 473 | i386_dr_update_inferior_debug_regs (state, &local_state); |
1ced966e | 474 | |
e6f9de87 | 475 | if (debug_hw_points) |
4be83cc2 | 476 | i386_dr_show (state, "insert_watchpoint", addr, len, type); |
e6f9de87 DE |
477 | |
478 | return retval; | |
479 | } | |
480 | ||
481 | /* Remove a watchpoint that watched the memory region which starts at | |
482 | address ADDR, whose length is LEN bytes, and for accesses of the | |
a4165e94 | 483 | type TYPE. Return 0 on success, -1 on failure. */ |
e6f9de87 DE |
484 | |
485 | int | |
4be83cc2 GB |
486 | i386_dr_remove_watchpoint (struct i386_debug_reg_state *state, |
487 | enum target_hw_bp_type type, | |
488 | CORE_ADDR addr, int len) | |
e6f9de87 DE |
489 | { |
490 | int retval; | |
1ced966e PA |
491 | /* Work on a local copy of the debug registers, and on success, |
492 | commit the change back to the inferior. */ | |
493 | struct i386_debug_reg_state local_state = *state; | |
e6f9de87 DE |
494 | |
495 | if (((len != 1 && len != 2 && len != 4) | |
496 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
497 | || addr % len != 0) | |
498 | { | |
fc6e2f03 GB |
499 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
500 | WP_REMOVE, | |
e6f9de87 DE |
501 | addr, len, type); |
502 | } | |
503 | else | |
504 | { | |
4be83cc2 | 505 | unsigned len_rw = i386_dr_length_and_rw_bits (len, type); |
e6f9de87 | 506 | |
4be83cc2 | 507 | retval = i386_dr_remove_aligned_watchpoint (&local_state, |
fc6e2f03 | 508 | addr, len_rw); |
e6f9de87 DE |
509 | } |
510 | ||
1ced966e | 511 | if (retval == 0) |
4be83cc2 | 512 | i386_dr_update_inferior_debug_regs (state, &local_state); |
1ced966e | 513 | |
e6f9de87 | 514 | if (debug_hw_points) |
4be83cc2 | 515 | i386_dr_show (state, "remove_watchpoint", addr, len, type); |
e6f9de87 DE |
516 | |
517 | return retval; | |
518 | } | |
519 | ||
520 | /* Return non-zero if we can watch a memory region that starts at | |
521 | address ADDR and whose length is LEN bytes. */ | |
522 | ||
523 | int | |
4be83cc2 GB |
524 | i386_dr_region_ok_for_watchpoint (struct i386_debug_reg_state *state, |
525 | CORE_ADDR addr, int len) | |
e6f9de87 DE |
526 | { |
527 | int nregs; | |
528 | ||
529 | /* Compute how many aligned watchpoints we would need to cover this | |
530 | region. */ | |
531 | nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT, | |
532 | addr, len, hw_write); | |
533 | return nregs <= DR_NADDR ? 1 : 0; | |
534 | } | |
535 | ||
536 | /* If the inferior has some break/watchpoint that triggered, set the | |
6e62758f GB |
537 | address associated with that break/watchpoint and return non-zero. |
538 | Otherwise, return zero. */ | |
e6f9de87 DE |
539 | |
540 | int | |
4be83cc2 GB |
541 | i386_dr_stopped_data_address (struct i386_debug_reg_state *state, |
542 | CORE_ADDR *addr_p) | |
e6f9de87 DE |
543 | { |
544 | CORE_ADDR addr = 0; | |
545 | int i; | |
546 | int rc = 0; | |
6210a125 PA |
547 | /* The current thread's DR_STATUS. We always need to read this to |
548 | check whether some watchpoint caused the trap. */ | |
964e4306 | 549 | unsigned status; |
6210a125 PA |
550 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a |
551 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
552 | unnecessary extra syscall when no watchpoint triggered. */ | |
553 | int control_p = 0; | |
d54d1edf | 554 | unsigned control = 0; |
e6f9de87 | 555 | |
6210a125 PA |
556 | /* In non-stop/async, threads can be running while we change the |
557 | global dr_mirror (and friends). Say, we set a watchpoint, and | |
558 | let threads resume. Now, say you delete the watchpoint, or | |
559 | add/remove watchpoints such that dr_mirror changes while threads | |
560 | are running. On targets that support non-stop, | |
561 | inserting/deleting watchpoints updates the global dr_mirror only. | |
562 | It does not update the real thread's debug registers; that's only | |
563 | done prior to resume. Instead, if threads are running when the | |
564 | mirror changes, a temporary and transparent stop on all threads | |
565 | is forced so they can get their copy of the debug registers | |
566 | updated on re-resume. Now, say, a thread hit a watchpoint before | |
567 | having been updated with the new dr_mirror contents, and we | |
568 | haven't yet handled the corresponding SIGTRAP. If we trusted | |
569 | dr_mirror below, we'd mistake the real trapped address (from the | |
570 | last time we had updated debug registers in the thread) with | |
571 | whatever was currently in dr_mirror. So to fix this, dr_mirror | |
572 | always represents intention, what we _want_ threads to have in | |
573 | debug registers. To get at the address and cause of the trap, we | |
574 | need to read the state the thread still has in its debug | |
575 | registers. | |
576 | ||
577 | In sum, always get the current debug register values the current | |
578 | thread has, instead of trusting the global mirror. If the thread | |
579 | was running when we last changed watchpoints, the mirror no | |
580 | longer represents what was set in this thread's debug | |
581 | registers. */ | |
964e4306 | 582 | status = i386_dr_low_get_status (); |
e6f9de87 DE |
583 | |
584 | ALL_DEBUG_REGISTERS (i) | |
585 | { | |
6210a125 PA |
586 | if (!I386_DR_WATCH_HIT (status, i)) |
587 | continue; | |
588 | ||
589 | if (!control_p) | |
590 | { | |
591 | control = i386_dr_low_get_control (); | |
592 | control_p = 1; | |
593 | } | |
594 | ||
595 | /* This second condition makes sure DRi is set up for a data | |
596 | watchpoint, not a hardware breakpoint. The reason is that | |
597 | GDB doesn't call the target_stopped_data_address method | |
598 | except for data watchpoints. In other words, I'm being | |
599 | paranoiac. */ | |
600 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
e6f9de87 | 601 | { |
964e4306 | 602 | addr = i386_dr_low_get_addr (i); |
e6f9de87 DE |
603 | rc = 1; |
604 | if (debug_hw_points) | |
4be83cc2 | 605 | i386_dr_show (state, "watchpoint_hit", addr, -1, hw_write); |
e6f9de87 DE |
606 | } |
607 | } | |
608 | ||
609 | if (debug_hw_points && addr == 0) | |
4be83cc2 | 610 | i386_dr_show (state, "stopped_data_addr", 0, 0, hw_write); |
e6f9de87 DE |
611 | |
612 | if (rc) | |
613 | *addr_p = addr; | |
614 | return rc; | |
615 | } | |
616 | ||
6e62758f GB |
617 | /* Return non-zero if the inferior has some watchpoint that triggered. |
618 | Otherwise return zero. */ | |
e6f9de87 DE |
619 | |
620 | int | |
4be83cc2 | 621 | i386_dr_stopped_by_watchpoint (struct i386_debug_reg_state *state) |
e6f9de87 DE |
622 | { |
623 | CORE_ADDR addr = 0; | |
4be83cc2 | 624 | return i386_dr_stopped_data_address (state, &addr); |
e6f9de87 | 625 | } |