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e6f9de87 DE |
1 | /* Debug register code for the i386. |
2 | ||
ecd75fc8 | 3 | Copyright (C) 2009-2014 Free Software Foundation, Inc. |
e6f9de87 DE |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "server.h" | |
21 | #include "target.h" | |
22 | #include "i386-low.h" | |
23 | ||
24 | /* Support for 8-byte wide hw watchpoints. */ | |
25 | #ifndef TARGET_HAS_DR_LEN_8 | |
26 | /* NOTE: sizeof (long) == 4 on win64. */ | |
27 | #define TARGET_HAS_DR_LEN_8 (sizeof (void *) == 8) | |
28 | #endif | |
29 | ||
e6f9de87 DE |
30 | /* DR7 Debug Control register fields. */ |
31 | ||
32 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
33 | #define DR_CONTROL_SHIFT 16 | |
34 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
35 | #define DR_CONTROL_SIZE 4 | |
36 | ||
37 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
38 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ | |
39 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
40 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
41 | ||
42 | /* This is here for completeness. No platform supports this | |
43 | functionality yet (as of March 2001). Note that the DE flag in the | |
44 | CR4 register needs to be set to support this. */ | |
45 | #ifndef DR_RW_IORW | |
46 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ | |
47 | #endif | |
48 | ||
49 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
50 | is so we could OR this with the read/write field defined above. */ | |
51 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ | |
52 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
53 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
54 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
55 | ||
56 | /* Local and Global Enable flags in DR7. | |
57 | ||
58 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
59 | enabled only for the current task; the processor automatically | |
60 | clears this flag on every task switch. When the Global Enable flag | |
61 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
62 | processor never clears this flag. | |
63 | ||
64 | Currently, all watchpoint are locally enabled. If you need to | |
65 | enable them globally, read the comment which pertains to this in | |
66 | i386_insert_aligned_watchpoint below. */ | |
67 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ | |
68 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
69 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
70 | ||
71 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
72 | flags). These are only required on i386, to allow detection of the | |
73 | exact instruction which caused a watchpoint to break; i486 and | |
74 | later processors do that automatically. We set these flags for | |
75 | backwards compatibility. */ | |
76 | #define DR_LOCAL_SLOWDOWN (0x100) | |
77 | #define DR_GLOBAL_SLOWDOWN (0x200) | |
78 | ||
79 | /* Fields reserved by Intel. This includes the GD (General Detect | |
80 | Enable) flag, which causes a debug exception to be generated when a | |
81 | MOV instruction accesses one of the debug registers. | |
82 | ||
83 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
84 | #define DR_CONTROL_RESERVED (0xFC00) | |
85 | ||
86 | /* Auxiliary helper macros. */ | |
87 | ||
88 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
89 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) | |
90 | ||
91 | /* The I'th debug register is vacant if its Local and Global Enable | |
92 | bits are reset in the Debug Control register. */ | |
93 | #define I386_DR_VACANT(state, i) \ | |
94 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
95 | ||
96 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
97 | #define I386_DR_LOCAL_ENABLE(state, i) \ | |
98 | do { \ | |
99 | (state)->dr_control_mirror |= \ | |
100 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
101 | } while (0) | |
102 | ||
103 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
104 | #define I386_DR_GLOBAL_ENABLE(state, i) \ | |
105 | do { \ | |
106 | (state)->dr_control_mirror |= \ | |
107 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
108 | } while (0) | |
109 | ||
110 | /* Disable the break/watchpoint in the I'th debug register. */ | |
111 | #define I386_DR_DISABLE(state, i) \ | |
112 | do { \ | |
113 | (state)->dr_control_mirror &= \ | |
114 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
115 | } while (0) | |
116 | ||
117 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
118 | #define I386_DR_SET_RW_LEN(state, i,rwlen) \ | |
119 | do { \ | |
120 | (state)->dr_control_mirror &= \ | |
121 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
122 | (state)->dr_control_mirror |= \ | |
123 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
124 | } while (0) | |
125 | ||
126 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
964e4306 PA |
127 | #define I386_DR_GET_RW_LEN(dr7, i) \ |
128 | (((dr7) \ | |
e6f9de87 DE |
129 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) |
130 | ||
131 | /* Did the watchpoint whose address is in the I'th register break? */ | |
964e4306 | 132 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
e6f9de87 DE |
133 | |
134 | /* A macro to loop over all debug registers. */ | |
135 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) | |
136 | ||
137 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
138 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
139 | \f | |
140 | /* Implementation. */ | |
141 | ||
142 | /* Clear the reference counts and forget everything we knew about the | |
143 | debug registers. */ | |
144 | ||
145 | void | |
146 | i386_low_init_dregs (struct i386_debug_reg_state *state) | |
147 | { | |
148 | int i; | |
149 | ||
150 | ALL_DEBUG_REGISTERS (i) | |
151 | { | |
152 | state->dr_mirror[i] = 0; | |
153 | state->dr_ref_count[i] = 0; | |
154 | } | |
155 | state->dr_control_mirror = 0; | |
156 | state->dr_status_mirror = 0; | |
157 | } | |
158 | ||
159 | /* Print the values of the mirrored debug registers. This is enabled via | |
160 | the "set debug-hw-points 1" monitor command. */ | |
161 | ||
162 | static void | |
163 | i386_show_dr (struct i386_debug_reg_state *state, | |
164 | const char *func, CORE_ADDR addr, | |
165 | int len, enum target_hw_bp_type type) | |
166 | { | |
167 | int i; | |
168 | ||
169 | fprintf (stderr, "%s", func); | |
170 | if (addr || len) | |
171 | fprintf (stderr, " (addr=%lx, len=%d, type=%s)", | |
172 | (unsigned long) addr, len, | |
173 | type == hw_write ? "data-write" | |
174 | : (type == hw_read ? "data-read" | |
175 | : (type == hw_access ? "data-read/write" | |
176 | : (type == hw_execute ? "instruction-execute" | |
177 | /* FIXME: if/when I/O read/write | |
178 | watchpoints are supported, add them | |
179 | here. */ | |
180 | : "??unknown??")))); | |
181 | fprintf (stderr, ":\n"); | |
182 | fprintf (stderr, "\tCONTROL (DR7): %08x STATUS (DR6): %08x\n", | |
183 | state->dr_control_mirror, state->dr_status_mirror); | |
184 | ALL_DEBUG_REGISTERS (i) | |
185 | { | |
186 | fprintf (stderr, "\ | |
187 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
188 | i, paddress (state->dr_mirror[i]), | |
189 | state->dr_ref_count[i], | |
190 | i + 1, paddress (state->dr_mirror[i + 1]), | |
191 | state->dr_ref_count[i + 1]); | |
192 | i++; | |
193 | } | |
194 | } | |
195 | ||
196 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
197 | region of LEN bytes for accesses of type TYPE. LEN is assumed to | |
198 | have the value of 1, 2, or 4. */ | |
199 | ||
200 | static unsigned | |
201 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
202 | { | |
203 | unsigned rw; | |
204 | ||
205 | switch (type) | |
206 | { | |
207 | case hw_execute: | |
208 | rw = DR_RW_EXECUTE; | |
209 | break; | |
210 | case hw_write: | |
211 | rw = DR_RW_WRITE; | |
212 | break; | |
213 | case hw_read: | |
85d721b8 | 214 | fatal ("The i386 doesn't support data-read watchpoints.\n"); |
e6f9de87 DE |
215 | case hw_access: |
216 | rw = DR_RW_READ; | |
217 | break; | |
218 | #if 0 | |
219 | /* Not yet supported. */ | |
220 | case hw_io_access: | |
221 | rw = DR_RW_IORW; | |
222 | break; | |
223 | #endif | |
224 | default: | |
225 | error ("\ | |
226 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n", | |
227 | (int) type); | |
228 | } | |
229 | ||
230 | switch (len) | |
231 | { | |
232 | case 1: | |
233 | return (DR_LEN_1 | rw); | |
234 | case 2: | |
235 | return (DR_LEN_2 | rw); | |
236 | case 4: | |
237 | return (DR_LEN_4 | rw); | |
238 | case 8: | |
239 | if (TARGET_HAS_DR_LEN_8) | |
240 | return (DR_LEN_8 | rw); | |
96f7a20f | 241 | /* ELSE FALL THROUGH */ |
e6f9de87 DE |
242 | default: |
243 | error ("\ | |
244 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n", len); | |
245 | } | |
246 | } | |
247 | ||
248 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
249 | according to the length of the region to watch. LEN_RW_BITS is the | |
250 | value of the bits from DR7 which describes the length and access | |
251 | type of the region to be watched by this watchpoint. Return 0 on | |
252 | success, -1 on failure. */ | |
253 | ||
254 | static int | |
255 | i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, | |
256 | CORE_ADDR addr, unsigned len_rw_bits) | |
257 | { | |
258 | int i; | |
259 | ||
260 | /* First, look for an occupied debug register with the same address | |
261 | and the same RW and LEN definitions. If we find one, we can | |
262 | reuse it for this watchpoint as well (and save a register). */ | |
263 | ALL_DEBUG_REGISTERS (i) | |
264 | { | |
265 | if (!I386_DR_VACANT (state, i) | |
266 | && state->dr_mirror[i] == addr | |
964e4306 | 267 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) |
e6f9de87 DE |
268 | { |
269 | state->dr_ref_count[i]++; | |
270 | return 0; | |
271 | } | |
272 | } | |
273 | ||
274 | /* Next, look for a vacant debug register. */ | |
275 | ALL_DEBUG_REGISTERS (i) | |
276 | { | |
277 | if (I386_DR_VACANT (state, i)) | |
278 | break; | |
279 | } | |
280 | ||
281 | /* No more debug registers! */ | |
282 | if (i >= DR_NADDR) | |
283 | return -1; | |
284 | ||
285 | /* Now set up the register I to watch our region. */ | |
286 | ||
287 | /* Record the info in our local mirrored array. */ | |
288 | state->dr_mirror[i] = addr; | |
289 | state->dr_ref_count[i] = 1; | |
290 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
291 | /* Note: we only enable the watchpoint locally, i.e. in the current | |
292 | task. Currently, no i386 target allows or supports global | |
293 | watchpoints; however, if any target would want that in the | |
294 | future, GDB should probably provide a command to control whether | |
295 | to enable watchpoints globally or locally, and the code below | |
296 | should use global or local enable and slow-down flags as | |
297 | appropriate. */ | |
298 | I386_DR_LOCAL_ENABLE (state, i); | |
299 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
300 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
301 | ||
e6f9de87 DE |
302 | return 0; |
303 | } | |
304 | ||
305 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
306 | according to the length of the region to watch. LEN_RW_BITS is the | |
307 | value of the bits from DR7 which describes the length and access | |
308 | type of the region watched by this watchpoint. Return 0 on | |
309 | success, -1 on failure. */ | |
310 | ||
311 | static int | |
312 | i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, | |
313 | CORE_ADDR addr, unsigned len_rw_bits) | |
314 | { | |
315 | int i, retval = -1; | |
316 | ||
317 | ALL_DEBUG_REGISTERS (i) | |
318 | { | |
319 | if (!I386_DR_VACANT (state, i) | |
320 | && state->dr_mirror[i] == addr | |
964e4306 | 321 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) |
e6f9de87 DE |
322 | { |
323 | if (--state->dr_ref_count[i] == 0) /* No longer in use? */ | |
324 | { | |
325 | /* Reset our mirror. */ | |
326 | state->dr_mirror[i] = 0; | |
327 | I386_DR_DISABLE (state, i); | |
e6f9de87 DE |
328 | } |
329 | retval = 0; | |
330 | } | |
331 | } | |
332 | ||
333 | return retval; | |
334 | } | |
335 | ||
336 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
337 | number of debug registers required to watch a region at address | |
338 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
339 | successful insertion or removal, a positive number when queried | |
340 | about the number of registers, or -1 on failure. If WHAT is not a | |
341 | valid value, bombs through internal_error. */ | |
342 | ||
343 | static int | |
344 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, | |
345 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
346 | enum target_hw_bp_type type) | |
347 | { | |
1ced966e | 348 | int retval = 0; |
e6f9de87 DE |
349 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
350 | ||
351 | static const int size_try_array[8][8] = | |
352 | { | |
353 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ | |
354 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
355 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
356 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
357 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
358 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
359 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
360 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
361 | }; | |
362 | ||
363 | while (len > 0) | |
364 | { | |
365 | int align = addr % max_wp_len; | |
366 | /* Four (eight on AMD64) is the maximum length a debug register | |
367 | can watch. */ | |
368 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); | |
369 | int size = size_try_array[try][align]; | |
370 | ||
371 | if (what == WP_COUNT) | |
372 | { | |
373 | /* size_try_array[] is defined such that each iteration | |
374 | through the loop is guaranteed to produce an address and a | |
375 | size that can be watched with a single debug register. | |
376 | Thus, for counting the registers required to watch a | |
377 | region, we simply need to increment the count on each | |
378 | iteration. */ | |
379 | retval++; | |
380 | } | |
381 | else | |
382 | { | |
383 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
384 | ||
385 | if (what == WP_INSERT) | |
1ced966e | 386 | retval = i386_insert_aligned_watchpoint (state, addr, len_rw); |
e6f9de87 | 387 | else if (what == WP_REMOVE) |
1ced966e | 388 | retval = i386_remove_aligned_watchpoint (state, addr, len_rw); |
e6f9de87 DE |
389 | else |
390 | fatal ("\ | |
391 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n", | |
392 | (int) what); | |
393 | ||
1ced966e PA |
394 | if (retval) |
395 | break; | |
e6f9de87 DE |
396 | } |
397 | ||
398 | addr += size; | |
399 | len -= size; | |
400 | } | |
401 | ||
402 | return retval; | |
403 | } | |
404 | ||
961bd387 | 405 | #define Z_PACKET_HW_BP '1' |
e6f9de87 DE |
406 | #define Z_PACKET_WRITE_WP '2' |
407 | #define Z_PACKET_READ_WP '3' | |
408 | #define Z_PACKET_ACCESS_WP '4' | |
409 | ||
a4165e94 | 410 | enum target_hw_bp_type |
e6f9de87 DE |
411 | Z_packet_to_hw_type (char type) |
412 | { | |
413 | switch (type) | |
414 | { | |
961bd387 ME |
415 | case Z_PACKET_HW_BP: |
416 | return hw_execute; | |
e6f9de87 DE |
417 | case Z_PACKET_WRITE_WP: |
418 | return hw_write; | |
419 | case Z_PACKET_READ_WP: | |
420 | return hw_read; | |
421 | case Z_PACKET_ACCESS_WP: | |
422 | return hw_access; | |
423 | default: | |
424 | fatal ("Z_packet_to_hw_type: bad watchpoint type %c", type); | |
425 | } | |
426 | } | |
427 | ||
1ced966e PA |
428 | /* Update the inferior debug registers state, in INF_STATE, with the |
429 | new debug registers state, in NEW_STATE. */ | |
430 | ||
431 | static void | |
432 | i386_update_inferior_debug_regs (struct i386_debug_reg_state *inf_state, | |
433 | struct i386_debug_reg_state *new_state) | |
434 | { | |
435 | int i; | |
436 | ||
437 | ALL_DEBUG_REGISTERS (i) | |
438 | { | |
439 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (inf_state, i)) | |
440 | i386_dr_low_set_addr (new_state, i); | |
441 | else | |
442 | gdb_assert (new_state->dr_mirror[i] == inf_state->dr_mirror[i]); | |
443 | } | |
444 | ||
445 | if (new_state->dr_control_mirror != inf_state->dr_control_mirror) | |
446 | i386_dr_low_set_control (new_state); | |
447 | ||
448 | *inf_state = *new_state; | |
449 | } | |
450 | ||
e6f9de87 DE |
451 | /* Insert a watchpoint to watch a memory region which starts at |
452 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
453 | of the type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */ | |
454 | ||
455 | int | |
456 | i386_low_insert_watchpoint (struct i386_debug_reg_state *state, | |
a4165e94 PA |
457 | enum target_hw_bp_type type, |
458 | CORE_ADDR addr, int len) | |
e6f9de87 DE |
459 | { |
460 | int retval; | |
1ced966e PA |
461 | /* Work on a local copy of the debug registers, and on success, |
462 | commit the change back to the inferior. */ | |
463 | struct i386_debug_reg_state local_state = *state; | |
e6f9de87 | 464 | |
85d721b8 PA |
465 | if (type == hw_read) |
466 | return 1; /* unsupported */ | |
467 | ||
e6f9de87 DE |
468 | if (((len != 1 && len != 2 && len != 4) |
469 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
470 | || addr % len != 0) | |
471 | { | |
1ced966e | 472 | retval = i386_handle_nonaligned_watchpoint (&local_state, WP_INSERT, |
e6f9de87 DE |
473 | addr, len, type); |
474 | } | |
475 | else | |
476 | { | |
477 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
478 | ||
1ced966e | 479 | retval = i386_insert_aligned_watchpoint (&local_state, addr, len_rw); |
e6f9de87 DE |
480 | } |
481 | ||
1ced966e PA |
482 | if (retval == 0) |
483 | i386_update_inferior_debug_regs (state, &local_state); | |
484 | ||
e6f9de87 DE |
485 | if (debug_hw_points) |
486 | i386_show_dr (state, "insert_watchpoint", addr, len, type); | |
487 | ||
488 | return retval; | |
489 | } | |
490 | ||
491 | /* Remove a watchpoint that watched the memory region which starts at | |
492 | address ADDR, whose length is LEN bytes, and for accesses of the | |
a4165e94 | 493 | type TYPE. Return 0 on success, -1 on failure. */ |
e6f9de87 DE |
494 | |
495 | int | |
496 | i386_low_remove_watchpoint (struct i386_debug_reg_state *state, | |
a4165e94 PA |
497 | enum target_hw_bp_type type, |
498 | CORE_ADDR addr, int len) | |
e6f9de87 DE |
499 | { |
500 | int retval; | |
1ced966e PA |
501 | /* Work on a local copy of the debug registers, and on success, |
502 | commit the change back to the inferior. */ | |
503 | struct i386_debug_reg_state local_state = *state; | |
e6f9de87 DE |
504 | |
505 | if (((len != 1 && len != 2 && len != 4) | |
506 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
507 | || addr % len != 0) | |
508 | { | |
1ced966e | 509 | retval = i386_handle_nonaligned_watchpoint (&local_state, WP_REMOVE, |
e6f9de87 DE |
510 | addr, len, type); |
511 | } | |
512 | else | |
513 | { | |
514 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
515 | ||
1ced966e | 516 | retval = i386_remove_aligned_watchpoint (&local_state, addr, len_rw); |
e6f9de87 DE |
517 | } |
518 | ||
1ced966e PA |
519 | if (retval == 0) |
520 | i386_update_inferior_debug_regs (state, &local_state); | |
521 | ||
e6f9de87 DE |
522 | if (debug_hw_points) |
523 | i386_show_dr (state, "remove_watchpoint", addr, len, type); | |
524 | ||
525 | return retval; | |
526 | } | |
527 | ||
528 | /* Return non-zero if we can watch a memory region that starts at | |
529 | address ADDR and whose length is LEN bytes. */ | |
530 | ||
531 | int | |
532 | i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state *state, | |
533 | CORE_ADDR addr, int len) | |
534 | { | |
535 | int nregs; | |
536 | ||
537 | /* Compute how many aligned watchpoints we would need to cover this | |
538 | region. */ | |
539 | nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT, | |
540 | addr, len, hw_write); | |
541 | return nregs <= DR_NADDR ? 1 : 0; | |
542 | } | |
543 | ||
544 | /* If the inferior has some break/watchpoint that triggered, set the | |
545 | address associated with that break/watchpoint and return true. | |
546 | Otherwise, return false. */ | |
547 | ||
548 | int | |
549 | i386_low_stopped_data_address (struct i386_debug_reg_state *state, | |
550 | CORE_ADDR *addr_p) | |
551 | { | |
552 | CORE_ADDR addr = 0; | |
553 | int i; | |
554 | int rc = 0; | |
6210a125 PA |
555 | /* The current thread's DR_STATUS. We always need to read this to |
556 | check whether some watchpoint caused the trap. */ | |
964e4306 | 557 | unsigned status; |
6210a125 PA |
558 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a |
559 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
560 | unnecessary extra syscall when no watchpoint triggered. */ | |
561 | int control_p = 0; | |
d54d1edf | 562 | unsigned control = 0; |
e6f9de87 | 563 | |
6210a125 PA |
564 | /* In non-stop/async, threads can be running while we change the |
565 | global dr_mirror (and friends). Say, we set a watchpoint, and | |
566 | let threads resume. Now, say you delete the watchpoint, or | |
567 | add/remove watchpoints such that dr_mirror changes while threads | |
568 | are running. On targets that support non-stop, | |
569 | inserting/deleting watchpoints updates the global dr_mirror only. | |
570 | It does not update the real thread's debug registers; that's only | |
571 | done prior to resume. Instead, if threads are running when the | |
572 | mirror changes, a temporary and transparent stop on all threads | |
573 | is forced so they can get their copy of the debug registers | |
574 | updated on re-resume. Now, say, a thread hit a watchpoint before | |
575 | having been updated with the new dr_mirror contents, and we | |
576 | haven't yet handled the corresponding SIGTRAP. If we trusted | |
577 | dr_mirror below, we'd mistake the real trapped address (from the | |
578 | last time we had updated debug registers in the thread) with | |
579 | whatever was currently in dr_mirror. So to fix this, dr_mirror | |
580 | always represents intention, what we _want_ threads to have in | |
581 | debug registers. To get at the address and cause of the trap, we | |
582 | need to read the state the thread still has in its debug | |
583 | registers. | |
584 | ||
585 | In sum, always get the current debug register values the current | |
586 | thread has, instead of trusting the global mirror. If the thread | |
587 | was running when we last changed watchpoints, the mirror no | |
588 | longer represents what was set in this thread's debug | |
589 | registers. */ | |
964e4306 | 590 | status = i386_dr_low_get_status (); |
e6f9de87 DE |
591 | |
592 | ALL_DEBUG_REGISTERS (i) | |
593 | { | |
6210a125 PA |
594 | if (!I386_DR_WATCH_HIT (status, i)) |
595 | continue; | |
596 | ||
597 | if (!control_p) | |
598 | { | |
599 | control = i386_dr_low_get_control (); | |
600 | control_p = 1; | |
601 | } | |
602 | ||
603 | /* This second condition makes sure DRi is set up for a data | |
604 | watchpoint, not a hardware breakpoint. The reason is that | |
605 | GDB doesn't call the target_stopped_data_address method | |
606 | except for data watchpoints. In other words, I'm being | |
607 | paranoiac. */ | |
608 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
e6f9de87 | 609 | { |
964e4306 | 610 | addr = i386_dr_low_get_addr (i); |
e6f9de87 DE |
611 | rc = 1; |
612 | if (debug_hw_points) | |
613 | i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write); | |
614 | } | |
615 | } | |
616 | ||
617 | if (debug_hw_points && addr == 0) | |
618 | i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write); | |
619 | ||
620 | if (rc) | |
621 | *addr_p = addr; | |
622 | return rc; | |
623 | } | |
624 | ||
625 | /* Return true if the inferior has some watchpoint that triggered. | |
626 | Otherwise return false. */ | |
627 | ||
628 | int | |
629 | i386_low_stopped_by_watchpoint (struct i386_debug_reg_state *state) | |
630 | { | |
631 | CORE_ADDR addr = 0; | |
632 | return i386_low_stopped_data_address (state, &addr); | |
633 | } |