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e6f9de87 DE |
1 | /* Debug register code for the i386. |
2 | ||
ecd75fc8 | 3 | Copyright (C) 2009-2014 Free Software Foundation, Inc. |
e6f9de87 DE |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "server.h" | |
21 | #include "target.h" | |
22 | #include "i386-low.h" | |
23 | ||
6e62758f GB |
24 | /* Support for hardware watchpoints and breakpoints using the i386 |
25 | debug registers. | |
26 | ||
27 | This provides several functions for inserting and removing | |
28 | hardware-assisted breakpoints and watchpoints, testing if one or | |
29 | more of the watchpoints triggered and at what address, checking | |
30 | whether a given region can be watched, etc. | |
31 | ||
32 | The functions below implement debug registers sharing by reference | |
33 | counts, and allow to watch regions up to 16 bytes long. */ | |
34 | ||
1b6d4134 | 35 | /* Debug register size, in bytes. */ |
e6f9de87 | 36 | /* NOTE: sizeof (long) == 4 on win64. */ |
1b6d4134 GB |
37 | #define i386_get_debug_register_length() (sizeof (void *)) |
38 | ||
39 | /* Support for 8-byte wide hw watchpoints. */ | |
40 | #define TARGET_HAS_DR_LEN_8 (i386_get_debug_register_length () == 8) | |
e6f9de87 | 41 | |
e6f9de87 DE |
42 | /* DR7 Debug Control register fields. */ |
43 | ||
44 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
45 | #define DR_CONTROL_SHIFT 16 | |
46 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
47 | #define DR_CONTROL_SIZE 4 | |
48 | ||
49 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
50 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ | |
51 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
52 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
53 | ||
54 | /* This is here for completeness. No platform supports this | |
55 | functionality yet (as of March 2001). Note that the DE flag in the | |
56 | CR4 register needs to be set to support this. */ | |
57 | #ifndef DR_RW_IORW | |
58 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ | |
59 | #endif | |
60 | ||
61 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
62 | is so we could OR this with the read/write field defined above. */ | |
63 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ | |
64 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
65 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
66 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
67 | ||
68 | /* Local and Global Enable flags in DR7. | |
69 | ||
70 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
71 | enabled only for the current task; the processor automatically | |
72 | clears this flag on every task switch. When the Global Enable flag | |
73 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
74 | processor never clears this flag. | |
75 | ||
76 | Currently, all watchpoint are locally enabled. If you need to | |
77 | enable them globally, read the comment which pertains to this in | |
78 | i386_insert_aligned_watchpoint below. */ | |
79 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ | |
80 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
81 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
82 | ||
83 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
84 | flags). These are only required on i386, to allow detection of the | |
85 | exact instruction which caused a watchpoint to break; i486 and | |
86 | later processors do that automatically. We set these flags for | |
87 | backwards compatibility. */ | |
88 | #define DR_LOCAL_SLOWDOWN (0x100) | |
89 | #define DR_GLOBAL_SLOWDOWN (0x200) | |
90 | ||
91 | /* Fields reserved by Intel. This includes the GD (General Detect | |
92 | Enable) flag, which causes a debug exception to be generated when a | |
93 | MOV instruction accesses one of the debug registers. | |
94 | ||
95 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
96 | #define DR_CONTROL_RESERVED (0xFC00) | |
97 | ||
98 | /* Auxiliary helper macros. */ | |
99 | ||
100 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
101 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) | |
102 | ||
103 | /* The I'th debug register is vacant if its Local and Global Enable | |
104 | bits are reset in the Debug Control register. */ | |
105 | #define I386_DR_VACANT(state, i) \ | |
106 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
107 | ||
108 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
109 | #define I386_DR_LOCAL_ENABLE(state, i) \ | |
110 | do { \ | |
111 | (state)->dr_control_mirror |= \ | |
112 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
113 | } while (0) | |
114 | ||
115 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
116 | #define I386_DR_GLOBAL_ENABLE(state, i) \ | |
117 | do { \ | |
118 | (state)->dr_control_mirror |= \ | |
119 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
120 | } while (0) | |
121 | ||
122 | /* Disable the break/watchpoint in the I'th debug register. */ | |
123 | #define I386_DR_DISABLE(state, i) \ | |
124 | do { \ | |
125 | (state)->dr_control_mirror &= \ | |
126 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
127 | } while (0) | |
128 | ||
129 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
fc6e2f03 | 130 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ |
e6f9de87 DE |
131 | do { \ |
132 | (state)->dr_control_mirror &= \ | |
133 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
134 | (state)->dr_control_mirror |= \ | |
135 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
136 | } while (0) | |
137 | ||
138 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
964e4306 PA |
139 | #define I386_DR_GET_RW_LEN(dr7, i) \ |
140 | (((dr7) \ | |
e6f9de87 DE |
141 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) |
142 | ||
143 | /* Did the watchpoint whose address is in the I'th register break? */ | |
964e4306 | 144 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
e6f9de87 DE |
145 | |
146 | /* A macro to loop over all debug registers. */ | |
147 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) | |
148 | ||
149 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
150 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
fc6e2f03 | 151 | |
e6f9de87 DE |
152 | /* Implementation. */ |
153 | ||
154 | /* Clear the reference counts and forget everything we knew about the | |
155 | debug registers. */ | |
156 | ||
157 | void | |
158 | i386_low_init_dregs (struct i386_debug_reg_state *state) | |
159 | { | |
160 | int i; | |
161 | ||
162 | ALL_DEBUG_REGISTERS (i) | |
163 | { | |
164 | state->dr_mirror[i] = 0; | |
165 | state->dr_ref_count[i] = 0; | |
166 | } | |
167 | state->dr_control_mirror = 0; | |
168 | state->dr_status_mirror = 0; | |
169 | } | |
170 | ||
6e62758f | 171 | /* Print the values of the mirrored debug registers. */ |
e6f9de87 DE |
172 | |
173 | static void | |
174 | i386_show_dr (struct i386_debug_reg_state *state, | |
175 | const char *func, CORE_ADDR addr, | |
176 | int len, enum target_hw_bp_type type) | |
177 | { | |
178 | int i; | |
179 | ||
1b6d4134 | 180 | debug_printf ("%s", func); |
e6f9de87 | 181 | if (addr || len) |
1b6d4134 GB |
182 | debug_printf (" (addr=%s, len=%d, type=%s)", |
183 | phex (addr, 8), len, | |
184 | type == hw_write ? "data-write" | |
185 | : (type == hw_read ? "data-read" | |
186 | : (type == hw_access ? "data-read/write" | |
187 | : (type == hw_execute ? "instruction-execute" | |
188 | /* FIXME: if/when I/O read/write | |
189 | watchpoints are supported, add them | |
190 | here. */ | |
191 | : "??unknown??")))); | |
192 | debug_printf (":\n"); | |
193 | debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", | |
194 | phex (state->dr_control_mirror, 8), | |
195 | phex (state->dr_status_mirror, 8)); | |
e6f9de87 DE |
196 | ALL_DEBUG_REGISTERS (i) |
197 | { | |
1b6d4134 | 198 | debug_printf ("\ |
e6f9de87 | 199 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", |
1b6d4134 GB |
200 | i, phex (state->dr_mirror[i], |
201 | i386_get_debug_register_length ()), | |
202 | state->dr_ref_count[i], | |
203 | i + 1, phex (state->dr_mirror[i + 1], | |
204 | i386_get_debug_register_length ()), | |
205 | state->dr_ref_count[i + 1]); | |
e6f9de87 DE |
206 | i++; |
207 | } | |
208 | } | |
209 | ||
210 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
211 | region of LEN bytes for accesses of type TYPE. LEN is assumed to | |
212 | have the value of 1, 2, or 4. */ | |
213 | ||
214 | static unsigned | |
215 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
216 | { | |
217 | unsigned rw; | |
218 | ||
219 | switch (type) | |
220 | { | |
221 | case hw_execute: | |
222 | rw = DR_RW_EXECUTE; | |
223 | break; | |
224 | case hw_write: | |
225 | rw = DR_RW_WRITE; | |
226 | break; | |
227 | case hw_read: | |
e927c9fc GB |
228 | internal_error (__FILE__, __LINE__, |
229 | _("The i386 doesn't support " | |
230 | "data-read watchpoints.\n")); | |
e6f9de87 DE |
231 | case hw_access: |
232 | rw = DR_RW_READ; | |
233 | break; | |
234 | #if 0 | |
235 | /* Not yet supported. */ | |
236 | case hw_io_access: | |
237 | rw = DR_RW_IORW; | |
238 | break; | |
239 | #endif | |
240 | default: | |
e927c9fc GB |
241 | internal_error (__FILE__, __LINE__, _("\ |
242 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
e6f9de87 DE |
243 | (int) type); |
244 | } | |
245 | ||
246 | switch (len) | |
247 | { | |
248 | case 1: | |
249 | return (DR_LEN_1 | rw); | |
250 | case 2: | |
251 | return (DR_LEN_2 | rw); | |
252 | case 4: | |
253 | return (DR_LEN_4 | rw); | |
254 | case 8: | |
255 | if (TARGET_HAS_DR_LEN_8) | |
256 | return (DR_LEN_8 | rw); | |
96f7a20f | 257 | /* ELSE FALL THROUGH */ |
e6f9de87 | 258 | default: |
e927c9fc GB |
259 | internal_error (__FILE__, __LINE__, _("\ |
260 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
e6f9de87 DE |
261 | } |
262 | } | |
263 | ||
264 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
265 | according to the length of the region to watch. LEN_RW_BITS is the | |
266 | value of the bits from DR7 which describes the length and access | |
267 | type of the region to be watched by this watchpoint. Return 0 on | |
268 | success, -1 on failure. */ | |
269 | ||
270 | static int | |
271 | i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, | |
272 | CORE_ADDR addr, unsigned len_rw_bits) | |
273 | { | |
274 | int i; | |
275 | ||
276 | /* First, look for an occupied debug register with the same address | |
277 | and the same RW and LEN definitions. If we find one, we can | |
278 | reuse it for this watchpoint as well (and save a register). */ | |
279 | ALL_DEBUG_REGISTERS (i) | |
280 | { | |
281 | if (!I386_DR_VACANT (state, i) | |
282 | && state->dr_mirror[i] == addr | |
964e4306 | 283 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) |
e6f9de87 DE |
284 | { |
285 | state->dr_ref_count[i]++; | |
286 | return 0; | |
287 | } | |
288 | } | |
289 | ||
290 | /* Next, look for a vacant debug register. */ | |
291 | ALL_DEBUG_REGISTERS (i) | |
292 | { | |
293 | if (I386_DR_VACANT (state, i)) | |
294 | break; | |
295 | } | |
296 | ||
297 | /* No more debug registers! */ | |
298 | if (i >= DR_NADDR) | |
299 | return -1; | |
300 | ||
301 | /* Now set up the register I to watch our region. */ | |
302 | ||
303 | /* Record the info in our local mirrored array. */ | |
304 | state->dr_mirror[i] = addr; | |
305 | state->dr_ref_count[i] = 1; | |
306 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
307 | /* Note: we only enable the watchpoint locally, i.e. in the current | |
308 | task. Currently, no i386 target allows or supports global | |
309 | watchpoints; however, if any target would want that in the | |
310 | future, GDB should probably provide a command to control whether | |
311 | to enable watchpoints globally or locally, and the code below | |
312 | should use global or local enable and slow-down flags as | |
313 | appropriate. */ | |
314 | I386_DR_LOCAL_ENABLE (state, i); | |
315 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
316 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
317 | ||
e6f9de87 DE |
318 | return 0; |
319 | } | |
320 | ||
321 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
322 | according to the length of the region to watch. LEN_RW_BITS is the | |
323 | value of the bits from DR7 which describes the length and access | |
324 | type of the region watched by this watchpoint. Return 0 on | |
325 | success, -1 on failure. */ | |
326 | ||
327 | static int | |
328 | i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, | |
329 | CORE_ADDR addr, unsigned len_rw_bits) | |
330 | { | |
331 | int i, retval = -1; | |
332 | ||
333 | ALL_DEBUG_REGISTERS (i) | |
334 | { | |
335 | if (!I386_DR_VACANT (state, i) | |
336 | && state->dr_mirror[i] == addr | |
964e4306 | 337 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) |
e6f9de87 DE |
338 | { |
339 | if (--state->dr_ref_count[i] == 0) /* No longer in use? */ | |
340 | { | |
341 | /* Reset our mirror. */ | |
342 | state->dr_mirror[i] = 0; | |
343 | I386_DR_DISABLE (state, i); | |
e6f9de87 DE |
344 | } |
345 | retval = 0; | |
346 | } | |
347 | } | |
348 | ||
349 | return retval; | |
350 | } | |
351 | ||
352 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
353 | number of debug registers required to watch a region at address | |
354 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
355 | successful insertion or removal, a positive number when queried | |
356 | about the number of registers, or -1 on failure. If WHAT is not a | |
357 | valid value, bombs through internal_error. */ | |
358 | ||
359 | static int | |
360 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, | |
361 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
362 | enum target_hw_bp_type type) | |
363 | { | |
1ced966e | 364 | int retval = 0; |
e6f9de87 DE |
365 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
366 | ||
367 | static const int size_try_array[8][8] = | |
368 | { | |
369 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ | |
370 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
371 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
372 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
373 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
374 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
375 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
376 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
377 | }; | |
378 | ||
379 | while (len > 0) | |
380 | { | |
381 | int align = addr % max_wp_len; | |
382 | /* Four (eight on AMD64) is the maximum length a debug register | |
383 | can watch. */ | |
384 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); | |
385 | int size = size_try_array[try][align]; | |
386 | ||
387 | if (what == WP_COUNT) | |
388 | { | |
389 | /* size_try_array[] is defined such that each iteration | |
390 | through the loop is guaranteed to produce an address and a | |
391 | size that can be watched with a single debug register. | |
392 | Thus, for counting the registers required to watch a | |
393 | region, we simply need to increment the count on each | |
394 | iteration. */ | |
395 | retval++; | |
396 | } | |
397 | else | |
398 | { | |
399 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
400 | ||
401 | if (what == WP_INSERT) | |
1ced966e | 402 | retval = i386_insert_aligned_watchpoint (state, addr, len_rw); |
e6f9de87 | 403 | else if (what == WP_REMOVE) |
1ced966e | 404 | retval = i386_remove_aligned_watchpoint (state, addr, len_rw); |
e6f9de87 | 405 | else |
e927c9fc GB |
406 | internal_error (__FILE__, __LINE__, _("\ |
407 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
408 | (int) what); | |
1ced966e PA |
409 | if (retval) |
410 | break; | |
e6f9de87 DE |
411 | } |
412 | ||
413 | addr += size; | |
414 | len -= size; | |
415 | } | |
416 | ||
417 | return retval; | |
418 | } | |
419 | ||
1ced966e PA |
420 | /* Update the inferior debug registers state, in INF_STATE, with the |
421 | new debug registers state, in NEW_STATE. */ | |
422 | ||
423 | static void | |
424 | i386_update_inferior_debug_regs (struct i386_debug_reg_state *inf_state, | |
425 | struct i386_debug_reg_state *new_state) | |
426 | { | |
427 | int i; | |
428 | ||
429 | ALL_DEBUG_REGISTERS (i) | |
430 | { | |
431 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (inf_state, i)) | |
432 | i386_dr_low_set_addr (new_state, i); | |
433 | else | |
434 | gdb_assert (new_state->dr_mirror[i] == inf_state->dr_mirror[i]); | |
435 | } | |
436 | ||
437 | if (new_state->dr_control_mirror != inf_state->dr_control_mirror) | |
438 | i386_dr_low_set_control (new_state); | |
439 | ||
440 | *inf_state = *new_state; | |
441 | } | |
442 | ||
e6f9de87 DE |
443 | /* Insert a watchpoint to watch a memory region which starts at |
444 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
6e62758f | 445 | of the type TYPE. Return 0 on success, -1 on failure. */ |
e6f9de87 DE |
446 | |
447 | int | |
448 | i386_low_insert_watchpoint (struct i386_debug_reg_state *state, | |
a4165e94 PA |
449 | enum target_hw_bp_type type, |
450 | CORE_ADDR addr, int len) | |
e6f9de87 DE |
451 | { |
452 | int retval; | |
1ced966e PA |
453 | /* Work on a local copy of the debug registers, and on success, |
454 | commit the change back to the inferior. */ | |
455 | struct i386_debug_reg_state local_state = *state; | |
e6f9de87 | 456 | |
85d721b8 PA |
457 | if (type == hw_read) |
458 | return 1; /* unsupported */ | |
459 | ||
e6f9de87 DE |
460 | if (((len != 1 && len != 2 && len != 4) |
461 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
462 | || addr % len != 0) | |
463 | { | |
fc6e2f03 GB |
464 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
465 | WP_INSERT, | |
e6f9de87 DE |
466 | addr, len, type); |
467 | } | |
468 | else | |
469 | { | |
470 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
471 | ||
fc6e2f03 GB |
472 | retval = i386_insert_aligned_watchpoint (&local_state, |
473 | addr, len_rw); | |
e6f9de87 DE |
474 | } |
475 | ||
1ced966e PA |
476 | if (retval == 0) |
477 | i386_update_inferior_debug_regs (state, &local_state); | |
478 | ||
e6f9de87 DE |
479 | if (debug_hw_points) |
480 | i386_show_dr (state, "insert_watchpoint", addr, len, type); | |
481 | ||
482 | return retval; | |
483 | } | |
484 | ||
485 | /* Remove a watchpoint that watched the memory region which starts at | |
486 | address ADDR, whose length is LEN bytes, and for accesses of the | |
a4165e94 | 487 | type TYPE. Return 0 on success, -1 on failure. */ |
e6f9de87 DE |
488 | |
489 | int | |
490 | i386_low_remove_watchpoint (struct i386_debug_reg_state *state, | |
a4165e94 PA |
491 | enum target_hw_bp_type type, |
492 | CORE_ADDR addr, int len) | |
e6f9de87 DE |
493 | { |
494 | int retval; | |
1ced966e PA |
495 | /* Work on a local copy of the debug registers, and on success, |
496 | commit the change back to the inferior. */ | |
497 | struct i386_debug_reg_state local_state = *state; | |
e6f9de87 DE |
498 | |
499 | if (((len != 1 && len != 2 && len != 4) | |
500 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
501 | || addr % len != 0) | |
502 | { | |
fc6e2f03 GB |
503 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
504 | WP_REMOVE, | |
e6f9de87 DE |
505 | addr, len, type); |
506 | } | |
507 | else | |
508 | { | |
509 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
510 | ||
fc6e2f03 GB |
511 | retval = i386_remove_aligned_watchpoint (&local_state, |
512 | addr, len_rw); | |
e6f9de87 DE |
513 | } |
514 | ||
1ced966e PA |
515 | if (retval == 0) |
516 | i386_update_inferior_debug_regs (state, &local_state); | |
517 | ||
e6f9de87 DE |
518 | if (debug_hw_points) |
519 | i386_show_dr (state, "remove_watchpoint", addr, len, type); | |
520 | ||
521 | return retval; | |
522 | } | |
523 | ||
524 | /* Return non-zero if we can watch a memory region that starts at | |
525 | address ADDR and whose length is LEN bytes. */ | |
526 | ||
527 | int | |
528 | i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state *state, | |
529 | CORE_ADDR addr, int len) | |
530 | { | |
531 | int nregs; | |
532 | ||
533 | /* Compute how many aligned watchpoints we would need to cover this | |
534 | region. */ | |
535 | nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT, | |
536 | addr, len, hw_write); | |
537 | return nregs <= DR_NADDR ? 1 : 0; | |
538 | } | |
539 | ||
540 | /* If the inferior has some break/watchpoint that triggered, set the | |
6e62758f GB |
541 | address associated with that break/watchpoint and return non-zero. |
542 | Otherwise, return zero. */ | |
e6f9de87 DE |
543 | |
544 | int | |
545 | i386_low_stopped_data_address (struct i386_debug_reg_state *state, | |
546 | CORE_ADDR *addr_p) | |
547 | { | |
548 | CORE_ADDR addr = 0; | |
549 | int i; | |
550 | int rc = 0; | |
6210a125 PA |
551 | /* The current thread's DR_STATUS. We always need to read this to |
552 | check whether some watchpoint caused the trap. */ | |
964e4306 | 553 | unsigned status; |
6210a125 PA |
554 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a |
555 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
556 | unnecessary extra syscall when no watchpoint triggered. */ | |
557 | int control_p = 0; | |
d54d1edf | 558 | unsigned control = 0; |
e6f9de87 | 559 | |
6210a125 PA |
560 | /* In non-stop/async, threads can be running while we change the |
561 | global dr_mirror (and friends). Say, we set a watchpoint, and | |
562 | let threads resume. Now, say you delete the watchpoint, or | |
563 | add/remove watchpoints such that dr_mirror changes while threads | |
564 | are running. On targets that support non-stop, | |
565 | inserting/deleting watchpoints updates the global dr_mirror only. | |
566 | It does not update the real thread's debug registers; that's only | |
567 | done prior to resume. Instead, if threads are running when the | |
568 | mirror changes, a temporary and transparent stop on all threads | |
569 | is forced so they can get their copy of the debug registers | |
570 | updated on re-resume. Now, say, a thread hit a watchpoint before | |
571 | having been updated with the new dr_mirror contents, and we | |
572 | haven't yet handled the corresponding SIGTRAP. If we trusted | |
573 | dr_mirror below, we'd mistake the real trapped address (from the | |
574 | last time we had updated debug registers in the thread) with | |
575 | whatever was currently in dr_mirror. So to fix this, dr_mirror | |
576 | always represents intention, what we _want_ threads to have in | |
577 | debug registers. To get at the address and cause of the trap, we | |
578 | need to read the state the thread still has in its debug | |
579 | registers. | |
580 | ||
581 | In sum, always get the current debug register values the current | |
582 | thread has, instead of trusting the global mirror. If the thread | |
583 | was running when we last changed watchpoints, the mirror no | |
584 | longer represents what was set in this thread's debug | |
585 | registers. */ | |
964e4306 | 586 | status = i386_dr_low_get_status (); |
e6f9de87 DE |
587 | |
588 | ALL_DEBUG_REGISTERS (i) | |
589 | { | |
6210a125 PA |
590 | if (!I386_DR_WATCH_HIT (status, i)) |
591 | continue; | |
592 | ||
593 | if (!control_p) | |
594 | { | |
595 | control = i386_dr_low_get_control (); | |
596 | control_p = 1; | |
597 | } | |
598 | ||
599 | /* This second condition makes sure DRi is set up for a data | |
600 | watchpoint, not a hardware breakpoint. The reason is that | |
601 | GDB doesn't call the target_stopped_data_address method | |
602 | except for data watchpoints. In other words, I'm being | |
603 | paranoiac. */ | |
604 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
e6f9de87 | 605 | { |
964e4306 | 606 | addr = i386_dr_low_get_addr (i); |
e6f9de87 DE |
607 | rc = 1; |
608 | if (debug_hw_points) | |
609 | i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write); | |
610 | } | |
611 | } | |
612 | ||
613 | if (debug_hw_points && addr == 0) | |
614 | i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write); | |
615 | ||
616 | if (rc) | |
617 | *addr_p = addr; | |
618 | return rc; | |
619 | } | |
620 | ||
6e62758f GB |
621 | /* Return non-zero if the inferior has some watchpoint that triggered. |
622 | Otherwise return zero. */ | |
e6f9de87 DE |
623 | |
624 | int | |
625 | i386_low_stopped_by_watchpoint (struct i386_debug_reg_state *state) | |
626 | { | |
627 | CORE_ADDR addr = 0; | |
628 | return i386_low_stopped_data_address (state, &addr); | |
629 | } |