Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
42a4f53d | 2 | Copyright (C) 1995-2019 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
d9311bfa AT |
22 | #include "arch/arm-linux.h" |
23 | #include "arch/arm-get-next-pcs.h" | |
bd9e6534 | 24 | #include "linux-aarch32-low.h" |
0a30fbc4 | 25 | |
bd9e6534 | 26 | #include <sys/uio.h> |
3743bb4f DE |
27 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
28 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
29 | #ifndef ELFMAG0 | |
58d6951d | 30 | #include <elf.h> |
3743bb4f | 31 | #endif |
5826e159 | 32 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 33 | #include <signal.h> |
d9311bfa | 34 | #include <sys/syscall.h> |
9308fc88 | 35 | |
58d6951d | 36 | /* Defined in auto-generated files. */ |
d05b4ac3 | 37 | void init_registers_arm (void); |
3aee8918 PA |
38 | extern const struct target_desc *tdesc_arm; |
39 | ||
d05b4ac3 | 40 | void init_registers_arm_with_iwmmxt (void); |
3aee8918 PA |
41 | extern const struct target_desc *tdesc_arm_with_iwmmxt; |
42 | ||
58d6951d | 43 | void init_registers_arm_with_vfpv2 (void); |
3aee8918 PA |
44 | extern const struct target_desc *tdesc_arm_with_vfpv2; |
45 | ||
58d6951d | 46 | void init_registers_arm_with_vfpv3 (void); |
3aee8918 PA |
47 | extern const struct target_desc *tdesc_arm_with_vfpv3; |
48 | ||
9308fc88 DJ |
49 | #ifndef PTRACE_GET_THREAD_AREA |
50 | #define PTRACE_GET_THREAD_AREA 22 | |
51 | #endif | |
52 | ||
fb1e4ffc DJ |
53 | #ifndef PTRACE_GETWMMXREGS |
54 | # define PTRACE_GETWMMXREGS 18 | |
55 | # define PTRACE_SETWMMXREGS 19 | |
56 | #endif | |
57 | ||
58d6951d DJ |
58 | #ifndef PTRACE_GETVFPREGS |
59 | # define PTRACE_GETVFPREGS 27 | |
60 | # define PTRACE_SETVFPREGS 28 | |
61 | #endif | |
62 | ||
09b4ad9f UW |
63 | #ifndef PTRACE_GETHBPREGS |
64 | #define PTRACE_GETHBPREGS 29 | |
65 | #define PTRACE_SETHBPREGS 30 | |
66 | #endif | |
67 | ||
68 | /* Information describing the hardware breakpoint capabilities. */ | |
71487fd7 | 69 | static struct |
09b4ad9f UW |
70 | { |
71 | unsigned char arch; | |
72 | unsigned char max_wp_length; | |
73 | unsigned char wp_count; | |
74 | unsigned char bp_count; | |
71487fd7 | 75 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
76 | |
77 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
78 | typedef enum | |
79 | { | |
80 | arm_hwbp_break = 0, | |
81 | arm_hwbp_load = 1, | |
82 | arm_hwbp_store = 2, | |
83 | arm_hwbp_access = 3 | |
84 | } arm_hwbp_type; | |
85 | ||
86 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
87 | typedef unsigned int arm_hwbp_control_t; | |
88 | ||
89 | /* Structure used to keep track of hardware break-/watch-points. */ | |
90 | struct arm_linux_hw_breakpoint | |
91 | { | |
92 | /* Address to break on, or being watched. */ | |
93 | unsigned int address; | |
94 | /* Control register for break-/watch- point. */ | |
95 | arm_hwbp_control_t control; | |
96 | }; | |
97 | ||
98 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
99 | assume a maximum number of supported break-/watchpoints. */ | |
100 | #define MAX_BPTS 32 | |
101 | #define MAX_WPTS 32 | |
102 | ||
103 | /* Per-process arch-specific data we want to keep. */ | |
104 | struct arch_process_info | |
105 | { | |
106 | /* Hardware breakpoints for this process. */ | |
107 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
108 | /* Hardware watchpoints for this process. */ | |
109 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
110 | }; | |
111 | ||
112 | /* Per-thread arch-specific data we want to keep. */ | |
113 | struct arch_lwp_info | |
114 | { | |
115 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
116 | char bpts_changed[MAX_BPTS]; | |
117 | char wpts_changed[MAX_WPTS]; | |
118 | /* Cached stopped data address. */ | |
119 | CORE_ADDR stopped_data_address; | |
120 | }; | |
121 | ||
58d6951d DJ |
122 | /* These are in <asm/elf.h> in current kernels. */ |
123 | #define HWCAP_VFP 64 | |
124 | #define HWCAP_IWMMXT 512 | |
125 | #define HWCAP_NEON 4096 | |
126 | #define HWCAP_VFPv3 8192 | |
127 | #define HWCAP_VFPv3D16 16384 | |
128 | ||
0a30fbc4 DJ |
129 | #ifdef HAVE_SYS_REG_H |
130 | #include <sys/reg.h> | |
131 | #endif | |
132 | ||
23ce3b1c | 133 | #define arm_num_regs 26 |
0a30fbc4 | 134 | |
2ec06d2e | 135 | static int arm_regmap[] = { |
0a30fbc4 DJ |
136 | 0, 4, 8, 12, 16, 20, 24, 28, |
137 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
138 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
139 | 64 | |
0a30fbc4 DJ |
140 | }; |
141 | ||
d9311bfa AT |
142 | /* Forward declarations needed for get_next_pcs ops. */ |
143 | static ULONGEST get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
144 | int len, | |
145 | int byte_order); | |
146 | ||
147 | static CORE_ADDR get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
148 | CORE_ADDR val); | |
149 | ||
553cb527 | 150 | static CORE_ADDR get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
d9311bfa AT |
151 | |
152 | static int get_next_pcs_is_thumb (struct arm_get_next_pcs *self); | |
153 | ||
154 | /* get_next_pcs operations. */ | |
155 | static struct arm_get_next_pcs_ops get_next_pcs_ops = { | |
156 | get_next_pcs_read_memory_unsigned_integer, | |
157 | get_next_pcs_syscall_next_pc, | |
158 | get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
159 | get_next_pcs_is_thumb, |
160 | arm_linux_get_next_pcs_fixup, | |
d9311bfa AT |
161 | }; |
162 | ||
2ec06d2e DJ |
163 | static int |
164 | arm_cannot_store_register (int regno) | |
0a30fbc4 | 165 | { |
2ec06d2e | 166 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
167 | } |
168 | ||
2ec06d2e DJ |
169 | static int |
170 | arm_cannot_fetch_register (int regno) | |
0a30fbc4 | 171 | { |
2ec06d2e | 172 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
173 | } |
174 | ||
fb1e4ffc | 175 | static void |
442ea881 | 176 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc | 177 | { |
89abb039 | 178 | if (regcache->tdesc != tdesc_arm_with_iwmmxt) |
58d6951d DJ |
179 | return; |
180 | ||
166a82be | 181 | for (int i = 0; i < 16; i++) |
442ea881 | 182 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
183 | |
184 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 185 | for (int i = 0; i < 6; i++) |
442ea881 PA |
186 | collect_register (regcache, arm_num_regs + i + 16, |
187 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
188 | } |
189 | ||
190 | static void | |
442ea881 | 191 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc | 192 | { |
89abb039 | 193 | if (regcache->tdesc != tdesc_arm_with_iwmmxt) |
58d6951d DJ |
194 | return; |
195 | ||
166a82be | 196 | for (int i = 0; i < 16; i++) |
442ea881 | 197 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
198 | |
199 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 200 | for (int i = 0; i < 6; i++) |
442ea881 PA |
201 | supply_register (regcache, arm_num_regs + i + 16, |
202 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
203 | } |
204 | ||
58d6951d | 205 | static void |
442ea881 | 206 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 207 | { |
bd9e6534 | 208 | int num; |
58d6951d | 209 | |
89abb039 YQ |
210 | if (regcache->tdesc == tdesc_arm_with_neon |
211 | || regcache->tdesc == tdesc_arm_with_vfpv3) | |
58d6951d | 212 | num = 32; |
89abb039 | 213 | else if (regcache->tdesc == tdesc_arm_with_vfpv2) |
58d6951d | 214 | num = 16; |
89abb039 YQ |
215 | else |
216 | return; | |
58d6951d | 217 | |
bd9e6534 | 218 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
219 | } |
220 | ||
d9311bfa AT |
221 | /* Wrapper of UNMAKE_THUMB_ADDR for get_next_pcs. */ |
222 | static CORE_ADDR | |
223 | get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, CORE_ADDR val) | |
224 | { | |
225 | return UNMAKE_THUMB_ADDR (val); | |
226 | } | |
227 | ||
58d6951d | 228 | static void |
442ea881 | 229 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 230 | { |
bd9e6534 | 231 | int num; |
58d6951d | 232 | |
89abb039 YQ |
233 | if (regcache->tdesc == tdesc_arm_with_neon |
234 | || regcache->tdesc == tdesc_arm_with_vfpv3) | |
58d6951d | 235 | num = 32; |
89abb039 | 236 | else if (regcache->tdesc == tdesc_arm_with_vfpv2) |
58d6951d | 237 | num = 16; |
89abb039 YQ |
238 | else |
239 | return; | |
58d6951d | 240 | |
bd9e6534 | 241 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 242 | } |
fb1e4ffc | 243 | |
d9311bfa AT |
244 | /* Wrapper of arm_is_thumb_mode for get_next_pcs. */ |
245 | static int | |
246 | get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
247 | { | |
248 | return arm_is_thumb_mode (); | |
249 | } | |
250 | ||
251 | /* Read memory from the inferiror. | |
252 | BYTE_ORDER is ignored and there to keep compatiblity with GDB's | |
253 | read_memory_unsigned_integer. */ | |
254 | static ULONGEST | |
255 | get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
256 | int len, | |
257 | int byte_order) | |
258 | { | |
259 | ULONGEST res; | |
260 | ||
9e784964 | 261 | res = 0; |
694b382c AT |
262 | target_read_memory (memaddr, (unsigned char *) &res, len); |
263 | ||
d9311bfa AT |
264 | return res; |
265 | } | |
266 | ||
9308fc88 DJ |
267 | /* Fetch the thread-local storage pointer for libthread_db. */ |
268 | ||
269 | ps_err_e | |
754653a7 | 270 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 271 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
272 | { |
273 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
274 | return PS_ERR; | |
275 | ||
276 | /* IDX is the bias from the thread pointer to the beginning of the | |
277 | thread descriptor. It has to be subtracted due to implementation | |
278 | quirks in libthread_db. */ | |
279 | *base = (void *) ((char *)*base - idx); | |
280 | ||
281 | return PS_OK; | |
282 | } | |
283 | ||
09b4ad9f | 284 | |
71487fd7 UW |
285 | /* Query Hardware Breakpoint information for the target we are attached to |
286 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
287 | static void | |
288 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 289 | { |
71487fd7 | 290 | unsigned int val; |
09b4ad9f | 291 | |
71487fd7 UW |
292 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
293 | return; | |
09b4ad9f | 294 | |
71487fd7 UW |
295 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
296 | if (arm_linux_hwbp_cap.arch == 0) | |
297 | return; | |
09b4ad9f | 298 | |
71487fd7 UW |
299 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
300 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
301 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 302 | |
71487fd7 UW |
303 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
304 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
305 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
306 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
307 | } |
308 | ||
309 | /* How many hardware breakpoints are available? */ | |
310 | static int | |
311 | arm_linux_get_hw_breakpoint_count (void) | |
312 | { | |
71487fd7 | 313 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
314 | } |
315 | ||
316 | /* How many hardware watchpoints are available? */ | |
317 | static int | |
318 | arm_linux_get_hw_watchpoint_count (void) | |
319 | { | |
71487fd7 | 320 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
321 | } |
322 | ||
323 | /* Maximum length of area watched by hardware watchpoint. */ | |
324 | static int | |
325 | arm_linux_get_hw_watchpoint_max_length (void) | |
326 | { | |
71487fd7 | 327 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
328 | } |
329 | ||
330 | /* Initialize an ARM hardware break-/watch-point control register value. | |
331 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
332 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
333 | */ | |
334 | static arm_hwbp_control_t | |
335 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
336 | arm_hwbp_type hwbp_type, | |
337 | int enable) | |
338 | { | |
339 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
340 | gdb_assert (hwbp_type != arm_hwbp_break | |
341 | || ((byte_address_select & 0xfU) != 0)); | |
342 | ||
343 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
344 | } | |
345 | ||
346 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
347 | static int | |
348 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
349 | { | |
350 | return control & 0x1; | |
351 | } | |
352 | ||
353 | /* Is the breakpoint control value CONTROL initialized? */ | |
354 | static int | |
355 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
356 | { | |
357 | return control != 0; | |
358 | } | |
359 | ||
360 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
361 | static arm_hwbp_control_t | |
362 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
363 | { | |
364 | return control & ~0x1; | |
365 | } | |
366 | ||
367 | /* Are two break-/watch-points equal? */ | |
368 | static int | |
369 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
370 | const struct arm_linux_hw_breakpoint *p2) | |
371 | { | |
372 | return p1->address == p2->address && p1->control == p2->control; | |
373 | } | |
374 | ||
802e8e6d PA |
375 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
376 | ||
171de4b8 | 377 | static arm_hwbp_type |
802e8e6d PA |
378 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) |
379 | { | |
380 | switch (raw_type) | |
381 | { | |
382 | case raw_bkpt_type_hw: | |
383 | return arm_hwbp_break; | |
384 | case raw_bkpt_type_write_wp: | |
385 | return arm_hwbp_store; | |
386 | case raw_bkpt_type_read_wp: | |
387 | return arm_hwbp_load; | |
388 | case raw_bkpt_type_access_wp: | |
389 | return arm_hwbp_access; | |
390 | default: | |
391 | gdb_assert_not_reached ("unhandled raw type"); | |
392 | } | |
393 | } | |
394 | ||
09b4ad9f UW |
395 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
396 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
397 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
398 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
399 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 400 | static int |
802e8e6d PA |
401 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
402 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
403 | { |
404 | arm_hwbp_type hwbp_type; | |
405 | unsigned mask; | |
406 | ||
802e8e6d | 407 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
408 | |
409 | if (hwbp_type == arm_hwbp_break) | |
410 | { | |
411 | /* For breakpoints, the length field encodes the mode. */ | |
412 | switch (len) | |
413 | { | |
414 | case 2: /* 16-bit Thumb mode breakpoint */ | |
415 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
416 | mask = 0x3; |
417 | addr &= ~1; | |
09b4ad9f UW |
418 | break; |
419 | case 4: /* 32-bit ARM mode breakpoint */ | |
420 | mask = 0xf; | |
fcf303ab | 421 | addr &= ~3; |
09b4ad9f UW |
422 | break; |
423 | default: | |
424 | /* Unsupported. */ | |
b62e2b27 | 425 | return -2; |
09b4ad9f | 426 | } |
09b4ad9f UW |
427 | } |
428 | else | |
429 | { | |
430 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
431 | CORE_ADDR aligned_addr; | |
432 | ||
433 | /* Can not set watchpoints for zero or negative lengths. */ | |
434 | if (len <= 0) | |
b62e2b27 | 435 | return -2; |
09b4ad9f UW |
436 | /* The current ptrace interface can only handle watchpoints that are a |
437 | power of 2. */ | |
438 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 439 | return -2; |
09b4ad9f UW |
440 | |
441 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
442 | range covered by a watchpoint. */ | |
443 | aligned_addr = addr & ~(max_wp_length - 1); | |
444 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 445 | return -2; |
09b4ad9f UW |
446 | |
447 | mask = (1 << len) - 1; | |
448 | } | |
449 | ||
450 | p->address = (unsigned int) addr; | |
451 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
452 | ||
453 | return hwbp_type != arm_hwbp_break; | |
454 | } | |
455 | ||
456 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
457 | the current process. */ | |
458 | ||
00192f77 SM |
459 | static void |
460 | update_registers_callback (thread_info *thread, int watch, int i) | |
09b4ad9f | 461 | { |
d86d4aaf | 462 | struct lwp_info *lwp = get_thread_lwp (thread); |
09b4ad9f | 463 | |
00192f77 SM |
464 | /* The actual update is done later just before resuming the lwp, |
465 | we just mark that the registers need updating. */ | |
466 | if (watch) | |
467 | lwp->arch_private->wpts_changed[i] = 1; | |
468 | else | |
469 | lwp->arch_private->bpts_changed[i] = 1; | |
09b4ad9f | 470 | |
00192f77 SM |
471 | /* If the lwp isn't stopped, force it to momentarily pause, so |
472 | we can update its breakpoint registers. */ | |
473 | if (!lwp->stopped) | |
474 | linux_stop_lwp (lwp); | |
09b4ad9f UW |
475 | } |
476 | ||
802e8e6d PA |
477 | static int |
478 | arm_supports_z_point_type (char z_type) | |
479 | { | |
480 | switch (z_type) | |
481 | { | |
abeead09 | 482 | case Z_PACKET_SW_BP: |
802e8e6d PA |
483 | case Z_PACKET_HW_BP: |
484 | case Z_PACKET_WRITE_WP: | |
485 | case Z_PACKET_READ_WP: | |
486 | case Z_PACKET_ACCESS_WP: | |
487 | return 1; | |
488 | default: | |
489 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
490 | return 0; | |
491 | } | |
492 | } | |
493 | ||
09b4ad9f UW |
494 | /* Insert hardware break-/watchpoint. */ |
495 | static int | |
802e8e6d PA |
496 | arm_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
497 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
498 | { |
499 | struct process_info *proc = current_process (); | |
500 | struct arm_linux_hw_breakpoint p, *pts; | |
501 | int watch, i, count; | |
502 | ||
503 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
504 | if (watch < 0) | |
505 | { | |
506 | /* Unsupported. */ | |
b62e2b27 | 507 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
508 | } |
509 | ||
510 | if (watch) | |
511 | { | |
512 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 513 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
514 | } |
515 | else | |
516 | { | |
517 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 518 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
519 | } |
520 | ||
521 | for (i = 0; i < count; i++) | |
522 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
523 | { | |
09b4ad9f | 524 | pts[i] = p; |
00192f77 SM |
525 | |
526 | /* Only update the threads of the current process. */ | |
527 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
528 | { | |
529 | update_registers_callback (thread, watch, i); | |
530 | }); | |
531 | ||
09b4ad9f UW |
532 | return 0; |
533 | } | |
534 | ||
535 | /* We're out of watchpoints. */ | |
536 | return -1; | |
537 | } | |
538 | ||
539 | /* Remove hardware break-/watchpoint. */ | |
540 | static int | |
802e8e6d PA |
541 | arm_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
542 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
543 | { |
544 | struct process_info *proc = current_process (); | |
545 | struct arm_linux_hw_breakpoint p, *pts; | |
546 | int watch, i, count; | |
547 | ||
548 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
549 | if (watch < 0) | |
550 | { | |
551 | /* Unsupported. */ | |
552 | return -1; | |
553 | } | |
554 | ||
555 | if (watch) | |
556 | { | |
557 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 558 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
559 | } |
560 | else | |
561 | { | |
562 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 563 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
564 | } |
565 | ||
566 | for (i = 0; i < count; i++) | |
567 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
568 | { | |
09b4ad9f | 569 | pts[i].control = arm_hwbp_control_disable (pts[i].control); |
00192f77 SM |
570 | |
571 | /* Only update the threads of the current process. */ | |
572 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
573 | { | |
574 | update_registers_callback (thread, watch, i); | |
575 | }); | |
576 | ||
09b4ad9f UW |
577 | return 0; |
578 | } | |
579 | ||
580 | /* No watchpoint matched. */ | |
581 | return -1; | |
582 | } | |
583 | ||
584 | /* Return whether current thread is stopped due to a watchpoint. */ | |
585 | static int | |
586 | arm_stopped_by_watchpoint (void) | |
587 | { | |
0bfdf32f | 588 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 589 | siginfo_t siginfo; |
09b4ad9f UW |
590 | |
591 | /* We must be able to set hardware watchpoints. */ | |
592 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
593 | return 0; | |
594 | ||
595 | /* Retrieve siginfo. */ | |
596 | errno = 0; | |
0bfdf32f | 597 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f UW |
598 | if (errno != 0) |
599 | return 0; | |
600 | ||
601 | /* This must be a hardware breakpoint. */ | |
602 | if (siginfo.si_signo != SIGTRAP | |
603 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
604 | return 0; | |
605 | ||
606 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
607 | a watchpoint. */ | |
608 | if (siginfo.si_errno >= 0) | |
609 | return 0; | |
610 | ||
611 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
612 | lwp->arch_private->stopped_data_address | |
613 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
614 | ||
615 | return 1; | |
616 | } | |
617 | ||
618 | /* Return data address that triggered watchpoint. Called only if | |
619 | arm_stopped_by_watchpoint returned true. */ | |
620 | static CORE_ADDR | |
621 | arm_stopped_data_address (void) | |
622 | { | |
0bfdf32f | 623 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
624 | return lwp->arch_private->stopped_data_address; |
625 | } | |
626 | ||
627 | /* Called when a new process is created. */ | |
628 | static struct arch_process_info * | |
629 | arm_new_process (void) | |
630 | { | |
8d749320 | 631 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
09b4ad9f UW |
632 | return info; |
633 | } | |
634 | ||
04ec7890 SM |
635 | /* Called when a process is being deleted. */ |
636 | ||
637 | static void | |
638 | arm_delete_process (struct arch_process_info *info) | |
639 | { | |
640 | xfree (info); | |
641 | } | |
642 | ||
09b4ad9f | 643 | /* Called when a new thread is detected. */ |
34c703da GB |
644 | static void |
645 | arm_new_thread (struct lwp_info *lwp) | |
09b4ad9f | 646 | { |
8d749320 | 647 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
09b4ad9f UW |
648 | int i; |
649 | ||
650 | for (i = 0; i < MAX_BPTS; i++) | |
651 | info->bpts_changed[i] = 1; | |
652 | for (i = 0; i < MAX_WPTS; i++) | |
653 | info->wpts_changed[i] = 1; | |
654 | ||
34c703da | 655 | lwp->arch_private = info; |
09b4ad9f UW |
656 | } |
657 | ||
466eecee SM |
658 | /* Function to call when a thread is being deleted. */ |
659 | ||
660 | static void | |
661 | arm_delete_thread (struct arch_lwp_info *arch_lwp) | |
662 | { | |
663 | xfree (arch_lwp); | |
664 | } | |
665 | ||
3a8a0396 DB |
666 | static void |
667 | arm_new_fork (struct process_info *parent, struct process_info *child) | |
668 | { | |
69291610 HW |
669 | struct arch_process_info *parent_proc_info; |
670 | struct arch_process_info *child_proc_info; | |
3a8a0396 DB |
671 | struct lwp_info *child_lwp; |
672 | struct arch_lwp_info *child_lwp_info; | |
673 | int i; | |
674 | ||
675 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
676 | gdb_assert (parent->priv != NULL |
677 | && parent->priv->arch_private != NULL); | |
678 | gdb_assert (child->priv != NULL | |
679 | && child->priv->arch_private != NULL); | |
3a8a0396 | 680 | |
69291610 HW |
681 | parent_proc_info = parent->priv->arch_private; |
682 | child_proc_info = child->priv->arch_private; | |
683 | ||
3a8a0396 DB |
684 | /* Linux kernel before 2.6.33 commit |
685 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
686 | will inherit hardware debug registers from parent | |
687 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
688 | zeroed debug registers. | |
689 | ||
690 | GDB core assumes the child inherits the watchpoints/hw | |
691 | breakpoints of the parent, and will remove them all from the | |
692 | forked off process. Copy the debug registers mirrors into the | |
693 | new process so that all breakpoints and watchpoints can be | |
694 | removed together. The debug registers mirror will become zeroed | |
695 | in the end before detaching the forked off process, thus making | |
696 | this compatible with older Linux kernels too. */ | |
697 | ||
698 | *child_proc_info = *parent_proc_info; | |
699 | ||
700 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
701 | make sure that the registers will be updated. */ | |
9179355e | 702 | child_lwp = find_lwp_pid (ptid_t (child->pid)); |
3a8a0396 DB |
703 | child_lwp_info = child_lwp->arch_private; |
704 | for (i = 0; i < MAX_BPTS; i++) | |
705 | child_lwp_info->bpts_changed[i] = 1; | |
706 | for (i = 0; i < MAX_WPTS; i++) | |
707 | child_lwp_info->wpts_changed[i] = 1; | |
708 | } | |
709 | ||
09b4ad9f UW |
710 | /* Called when resuming a thread. |
711 | If the debug regs have changed, update the thread's copies. */ | |
712 | static void | |
713 | arm_prepare_to_resume (struct lwp_info *lwp) | |
714 | { | |
d86d4aaf DE |
715 | struct thread_info *thread = get_lwp_thread (lwp); |
716 | int pid = lwpid_of (thread); | |
717 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 718 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
719 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
720 | int i; | |
721 | ||
722 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
723 | if (lwp_info->bpts_changed[i]) | |
724 | { | |
725 | errno = 0; | |
726 | ||
727 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 728 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 729 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 730 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 731 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
732 | |
733 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 734 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 735 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 736 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 737 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
738 | |
739 | lwp_info->bpts_changed[i] = 0; | |
740 | } | |
741 | ||
742 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
743 | if (lwp_info->wpts_changed[i]) | |
744 | { | |
745 | errno = 0; | |
746 | ||
747 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 748 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 749 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 750 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 751 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
752 | |
753 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 754 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 755 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 756 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 757 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
758 | |
759 | lwp_info->wpts_changed[i] = 0; | |
760 | } | |
761 | } | |
762 | ||
f7a6a40d YQ |
763 | /* Find the next pc for a sigreturn or rt_sigreturn syscall. In |
764 | addition, set IS_THUMB depending on whether we will return to ARM | |
765 | or Thumb code. | |
d9311bfa AT |
766 | See arm-linux.h for stack layout details. */ |
767 | static CORE_ADDR | |
f7a6a40d YQ |
768 | arm_sigreturn_next_pc (struct regcache *regcache, int svc_number, |
769 | int *is_thumb) | |
d9311bfa AT |
770 | { |
771 | unsigned long sp; | |
772 | unsigned long sp_data; | |
773 | /* Offset of PC register. */ | |
774 | int pc_offset = 0; | |
775 | CORE_ADDR next_pc = 0; | |
cf2ebb6e | 776 | uint32_t cpsr; |
d9311bfa AT |
777 | |
778 | gdb_assert (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn); | |
779 | ||
780 | collect_register_by_name (regcache, "sp", &sp); | |
781 | (*the_target->read_memory) (sp, (unsigned char *) &sp_data, 4); | |
782 | ||
783 | pc_offset = arm_linux_sigreturn_next_pc_offset | |
784 | (sp, sp_data, svc_number, __NR_sigreturn == svc_number ? 1 : 0); | |
785 | ||
786 | (*the_target->read_memory) (sp + pc_offset, (unsigned char *) &next_pc, 4); | |
787 | ||
f7a6a40d YQ |
788 | /* Set IS_THUMB according the CPSR saved on the stack. */ |
789 | (*the_target->read_memory) (sp + pc_offset + 4, (unsigned char *) &cpsr, 4); | |
790 | *is_thumb = ((cpsr & CPSR_T) != 0); | |
791 | ||
d9311bfa AT |
792 | return next_pc; |
793 | } | |
794 | ||
795 | /* When PC is at a syscall instruction, return the PC of the next | |
796 | instruction to be executed. */ | |
797 | static CORE_ADDR | |
553cb527 | 798 | get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa AT |
799 | { |
800 | CORE_ADDR next_pc = 0; | |
553cb527 | 801 | CORE_ADDR pc = regcache_read_pc (self->regcache); |
d9311bfa AT |
802 | int is_thumb = arm_is_thumb_mode (); |
803 | ULONGEST svc_number = 0; | |
804 | struct regcache *regcache = self->regcache; | |
805 | ||
806 | if (is_thumb) | |
807 | { | |
808 | collect_register (regcache, 7, &svc_number); | |
809 | next_pc = pc + 2; | |
810 | } | |
811 | else | |
812 | { | |
813 | unsigned long this_instr; | |
814 | unsigned long svc_operand; | |
815 | ||
694b382c | 816 | target_read_memory (pc, (unsigned char *) &this_instr, 4); |
d9311bfa AT |
817 | svc_operand = (0x00ffffff & this_instr); |
818 | ||
819 | if (svc_operand) /* OABI. */ | |
820 | { | |
821 | svc_number = svc_operand - 0x900000; | |
822 | } | |
823 | else /* EABI. */ | |
824 | { | |
825 | collect_register (regcache, 7, &svc_number); | |
826 | } | |
827 | ||
828 | next_pc = pc + 4; | |
829 | } | |
830 | ||
831 | /* This is a sigreturn or sigreturn_rt syscall. */ | |
832 | if (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn) | |
833 | { | |
f7a6a40d YQ |
834 | /* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so |
835 | update IS_THUMB. */ | |
836 | next_pc = arm_sigreturn_next_pc (regcache, svc_number, &is_thumb); | |
d9311bfa AT |
837 | } |
838 | ||
839 | /* Addresses for calling Thumb functions have the bit 0 set. */ | |
840 | if (is_thumb) | |
841 | next_pc = MAKE_THUMB_ADDR (next_pc); | |
842 | ||
843 | return next_pc; | |
844 | } | |
09b4ad9f | 845 | |
3aee8918 PA |
846 | static const struct target_desc * |
847 | arm_read_description (void) | |
58d6951d | 848 | { |
974c89e0 | 849 | unsigned long arm_hwcap = linux_get_hwcap (4); |
71487fd7 | 850 | |
58d6951d | 851 | if (arm_hwcap & HWCAP_IWMMXT) |
3aee8918 | 852 | return tdesc_arm_with_iwmmxt; |
58d6951d DJ |
853 | |
854 | if (arm_hwcap & HWCAP_VFP) | |
855 | { | |
166a82be AH |
856 | /* Make sure that the kernel supports reading VFP registers. Support was |
857 | added in 2.6.30. */ | |
858 | int pid = lwpid_of (current_thread); | |
859 | errno = 0; | |
860 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
861 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
862 | return tdesc_arm; | |
58d6951d DJ |
863 | |
864 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
865 | it with VFP. */ | |
866 | if (arm_hwcap & HWCAP_NEON) | |
166a82be | 867 | return tdesc_arm_with_neon; |
58d6951d | 868 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
166a82be | 869 | return tdesc_arm_with_vfpv3; |
58d6951d | 870 | else |
166a82be | 871 | return tdesc_arm_with_vfpv2; |
58d6951d DJ |
872 | } |
873 | ||
874 | /* The default configuration uses legacy FPA registers, probably | |
875 | simulated. */ | |
3aee8918 | 876 | return tdesc_arm; |
58d6951d DJ |
877 | } |
878 | ||
3aee8918 PA |
879 | static void |
880 | arm_arch_setup (void) | |
881 | { | |
bd9e6534 YQ |
882 | int tid = lwpid_of (current_thread); |
883 | int gpregs[18]; | |
884 | struct iovec iov; | |
885 | ||
166a82be AH |
886 | /* Query hardware watchpoint/breakpoint capabilities. */ |
887 | arm_linux_init_hwbp_cap (tid); | |
888 | ||
3aee8918 | 889 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
890 | |
891 | iov.iov_base = gpregs; | |
892 | iov.iov_len = sizeof (gpregs); | |
893 | ||
894 | /* Check if PTRACE_GETREGSET works. */ | |
895 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
896 | have_ptrace_getregset = 1; | |
897 | else | |
898 | have_ptrace_getregset = 0; | |
3aee8918 PA |
899 | } |
900 | ||
d9311bfa AT |
901 | /* Fetch the next possible PCs after the current instruction executes. */ |
902 | ||
a0ff9e1a | 903 | static std::vector<CORE_ADDR> |
4d18591b | 904 | arm_gdbserver_get_next_pcs (struct regcache *regcache) |
d9311bfa AT |
905 | { |
906 | struct arm_get_next_pcs next_pcs_ctx; | |
d9311bfa AT |
907 | |
908 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
909 | &get_next_pcs_ops, | |
910 | /* Byte order is ignored assumed as host. */ | |
911 | 0, | |
912 | 0, | |
1b451dda | 913 | 1, |
d9311bfa AT |
914 | regcache); |
915 | ||
a0ff9e1a | 916 | return arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa AT |
917 | } |
918 | ||
7d00775e AT |
919 | /* Support for hardware single step. */ |
920 | ||
921 | static int | |
922 | arm_supports_hardware_single_step (void) | |
923 | { | |
924 | return 0; | |
925 | } | |
926 | ||
79e7fd4f YQ |
927 | /* Implementation of linux_target_ops method "get_syscall_trapinfo". */ |
928 | ||
929 | static void | |
930 | arm_get_syscall_trapinfo (struct regcache *regcache, int *sysno) | |
931 | { | |
932 | if (arm_is_thumb_mode ()) | |
933 | collect_register_by_name (regcache, "r7", sysno); | |
934 | else | |
935 | { | |
936 | unsigned long pc; | |
937 | unsigned long insn; | |
938 | ||
939 | collect_register_by_name (regcache, "pc", &pc); | |
940 | ||
941 | if ((*the_target->read_memory) (pc - 4, (unsigned char *) &insn, 4)) | |
942 | *sysno = UNKNOWN_SYSCALL; | |
943 | else | |
944 | { | |
945 | unsigned long svc_operand = (0x00ffffff & insn); | |
946 | ||
947 | if (svc_operand) | |
948 | { | |
949 | /* OABI */ | |
950 | *sysno = svc_operand - 0x900000; | |
951 | } | |
952 | else | |
953 | { | |
954 | /* EABI */ | |
955 | collect_register_by_name (regcache, "r7", sysno); | |
956 | } | |
957 | } | |
958 | } | |
959 | } | |
960 | ||
bd9e6534 YQ |
961 | /* Register sets without using PTRACE_GETREGSET. */ |
962 | ||
3aee8918 | 963 | static struct regset_info arm_regsets[] = { |
350fab54 AH |
964 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, |
965 | ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS, | |
fb1e4ffc | 966 | arm_fill_gregset, arm_store_gregset }, |
350fab54 | 967 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS, |
fb1e4ffc | 968 | arm_fill_wmmxregset, arm_store_wmmxregset }, |
350fab54 | 969 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS, |
58d6951d | 970 | arm_fill_vfpregset, arm_store_vfpregset }, |
50bc912a | 971 | NULL_REGSET |
fb1e4ffc DJ |
972 | }; |
973 | ||
3aee8918 PA |
974 | static struct regsets_info arm_regsets_info = |
975 | { | |
976 | arm_regsets, /* regsets */ | |
977 | 0, /* num_regsets */ | |
978 | NULL, /* disabled_regsets */ | |
979 | }; | |
980 | ||
981 | static struct usrregs_info arm_usrregs_info = | |
982 | { | |
983 | arm_num_regs, | |
984 | arm_regmap, | |
985 | }; | |
986 | ||
bd9e6534 | 987 | static struct regs_info regs_info_arm = |
3aee8918 PA |
988 | { |
989 | NULL, /* regset_bitmap */ | |
990 | &arm_usrregs_info, | |
991 | &arm_regsets_info | |
992 | }; | |
993 | ||
994 | static const struct regs_info * | |
995 | arm_regs_info (void) | |
996 | { | |
bd9e6534 YQ |
997 | const struct target_desc *tdesc = current_process ()->tdesc; |
998 | ||
999 | if (have_ptrace_getregset == 1 | |
1000 | && (tdesc == tdesc_arm_with_neon || tdesc == tdesc_arm_with_vfpv3)) | |
1001 | return ®s_info_aarch32; | |
1002 | else | |
1003 | return ®s_info_arm; | |
3aee8918 PA |
1004 | } |
1005 | ||
dd373349 AT |
1006 | struct linux_target_ops the_low_target = { |
1007 | arm_arch_setup, | |
1008 | arm_regs_info, | |
1009 | arm_cannot_fetch_register, | |
1010 | arm_cannot_store_register, | |
1011 | NULL, /* fetch_register */ | |
276d4552 YQ |
1012 | linux_get_pc_32bit, |
1013 | linux_set_pc_32bit, | |
8689682c | 1014 | arm_breakpoint_kind_from_pc, |
dd373349 | 1015 | arm_sw_breakpoint_from_kind, |
d9311bfa | 1016 | arm_gdbserver_get_next_pcs, |
0d62e5e8 DJ |
1017 | 0, |
1018 | arm_breakpoint_at, | |
802e8e6d | 1019 | arm_supports_z_point_type, |
09b4ad9f UW |
1020 | arm_insert_point, |
1021 | arm_remove_point, | |
1022 | arm_stopped_by_watchpoint, | |
1023 | arm_stopped_data_address, | |
1024 | NULL, /* collect_ptrace_register */ | |
1025 | NULL, /* supply_ptrace_register */ | |
1026 | NULL, /* siginfo_fixup */ | |
1027 | arm_new_process, | |
04ec7890 | 1028 | arm_delete_process, |
09b4ad9f | 1029 | arm_new_thread, |
466eecee | 1030 | arm_delete_thread, |
3a8a0396 | 1031 | arm_new_fork, |
09b4ad9f | 1032 | arm_prepare_to_resume, |
769ef81f AT |
1033 | NULL, /* process_qsupported */ |
1034 | NULL, /* supports_tracepoints */ | |
1035 | NULL, /* get_thread_area */ | |
1036 | NULL, /* install_fast_tracepoint_jump_pad */ | |
1037 | NULL, /* emit_ops */ | |
1038 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
1039 | NULL, /* supports_range_stepping */ | |
7d00775e | 1040 | arm_breakpoint_kind_from_current_state, |
79e7fd4f YQ |
1041 | arm_supports_hardware_single_step, |
1042 | arm_get_syscall_trapinfo, | |
2ec06d2e | 1043 | }; |
3aee8918 PA |
1044 | |
1045 | void | |
1046 | initialize_low_arch (void) | |
1047 | { | |
1048 | /* Initialize the Linux target descriptions. */ | |
1049 | init_registers_arm (); | |
1050 | init_registers_arm_with_iwmmxt (); | |
1051 | init_registers_arm_with_vfpv2 (); | |
1052 | init_registers_arm_with_vfpv3 (); | |
bd9e6534 YQ |
1053 | |
1054 | initialize_low_arch_aarch32 (); | |
3aee8918 PA |
1055 | |
1056 | initialize_regsets_info (&arm_regsets_info); | |
1057 | } |