Share regcache function regcache_raw_read_unsigned
[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-arm-low.c
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0a30fbc4 1/* GNU/Linux/ARM specific low level interface, for the remote server for GDB.
32d0add0 2 Copyright (C) 1995-2015 Free Software Foundation, Inc.
0a30fbc4
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3
4 This file is part of GDB.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
a9762ec7 8 the Free Software Foundation; either version 3 of the License, or
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9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
a9762ec7 17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
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18
19#include "server.h"
58caa3dc 20#include "linux-low.h"
deca266c 21#include "arch/arm.h"
bd9e6534 22#include "linux-aarch32-low.h"
0a30fbc4 23
bd9e6534 24#include <sys/uio.h>
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25/* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h.
26 On Bionic elf.h and linux/elf.h have conflicting definitions. */
27#ifndef ELFMAG0
58d6951d 28#include <elf.h>
3743bb4f 29#endif
5826e159 30#include "nat/gdb_ptrace.h"
09b4ad9f 31#include <signal.h>
9308fc88 32
58d6951d 33/* Defined in auto-generated files. */
d05b4ac3 34void init_registers_arm (void);
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35extern const struct target_desc *tdesc_arm;
36
d05b4ac3 37void init_registers_arm_with_iwmmxt (void);
3aee8918
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38extern const struct target_desc *tdesc_arm_with_iwmmxt;
39
58d6951d 40void init_registers_arm_with_vfpv2 (void);
3aee8918
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41extern const struct target_desc *tdesc_arm_with_vfpv2;
42
58d6951d 43void init_registers_arm_with_vfpv3 (void);
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44extern const struct target_desc *tdesc_arm_with_vfpv3;
45
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46#ifndef PTRACE_GET_THREAD_AREA
47#define PTRACE_GET_THREAD_AREA 22
48#endif
49
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50#ifndef PTRACE_GETWMMXREGS
51# define PTRACE_GETWMMXREGS 18
52# define PTRACE_SETWMMXREGS 19
53#endif
54
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55#ifndef PTRACE_GETVFPREGS
56# define PTRACE_GETVFPREGS 27
57# define PTRACE_SETVFPREGS 28
58#endif
59
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60#ifndef PTRACE_GETHBPREGS
61#define PTRACE_GETHBPREGS 29
62#define PTRACE_SETHBPREGS 30
63#endif
64
65/* Information describing the hardware breakpoint capabilities. */
71487fd7 66static struct
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67{
68 unsigned char arch;
69 unsigned char max_wp_length;
70 unsigned char wp_count;
71 unsigned char bp_count;
71487fd7 72} arm_linux_hwbp_cap;
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73
74/* Enum describing the different types of ARM hardware break-/watch-points. */
75typedef enum
76{
77 arm_hwbp_break = 0,
78 arm_hwbp_load = 1,
79 arm_hwbp_store = 2,
80 arm_hwbp_access = 3
81} arm_hwbp_type;
82
83/* Type describing an ARM Hardware Breakpoint Control register value. */
84typedef unsigned int arm_hwbp_control_t;
85
86/* Structure used to keep track of hardware break-/watch-points. */
87struct arm_linux_hw_breakpoint
88{
89 /* Address to break on, or being watched. */
90 unsigned int address;
91 /* Control register for break-/watch- point. */
92 arm_hwbp_control_t control;
93};
94
95/* Since we cannot dynamically allocate subfields of arch_process_info,
96 assume a maximum number of supported break-/watchpoints. */
97#define MAX_BPTS 32
98#define MAX_WPTS 32
99
100/* Per-process arch-specific data we want to keep. */
101struct arch_process_info
102{
103 /* Hardware breakpoints for this process. */
104 struct arm_linux_hw_breakpoint bpts[MAX_BPTS];
105 /* Hardware watchpoints for this process. */
106 struct arm_linux_hw_breakpoint wpts[MAX_WPTS];
107};
108
109/* Per-thread arch-specific data we want to keep. */
110struct arch_lwp_info
111{
112 /* Non-zero if our copy differs from what's recorded in the thread. */
113 char bpts_changed[MAX_BPTS];
114 char wpts_changed[MAX_WPTS];
115 /* Cached stopped data address. */
116 CORE_ADDR stopped_data_address;
117};
118
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119/* These are in <asm/elf.h> in current kernels. */
120#define HWCAP_VFP 64
121#define HWCAP_IWMMXT 512
122#define HWCAP_NEON 4096
123#define HWCAP_VFPv3 8192
124#define HWCAP_VFPv3D16 16384
125
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126#ifdef HAVE_SYS_REG_H
127#include <sys/reg.h>
128#endif
129
23ce3b1c 130#define arm_num_regs 26
0a30fbc4 131
2ec06d2e 132static int arm_regmap[] = {
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133 0, 4, 8, 12, 16, 20, 24, 28,
134 32, 36, 40, 44, 48, 52, 56, 60,
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135 -1, -1, -1, -1, -1, -1, -1, -1, -1,
136 64
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137};
138
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139static int
140arm_cannot_store_register (int regno)
0a30fbc4 141{
2ec06d2e 142 return (regno >= arm_num_regs);
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143}
144
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145static int
146arm_cannot_fetch_register (int regno)
0a30fbc4 147{
2ec06d2e 148 return (regno >= arm_num_regs);
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149}
150
fb1e4ffc 151static void
442ea881 152arm_fill_wmmxregset (struct regcache *regcache, void *buf)
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153{
154 int i;
155
89abb039 156 if (regcache->tdesc != tdesc_arm_with_iwmmxt)
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157 return;
158
fb1e4ffc 159 for (i = 0; i < 16; i++)
442ea881 160 collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8);
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161
162 /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */
163 for (i = 0; i < 6; i++)
442ea881
PA
164 collect_register (regcache, arm_num_regs + i + 16,
165 (char *) buf + 16 * 8 + i * 4);
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166}
167
168static void
442ea881 169arm_store_wmmxregset (struct regcache *regcache, const void *buf)
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170{
171 int i;
172
89abb039 173 if (regcache->tdesc != tdesc_arm_with_iwmmxt)
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174 return;
175
fb1e4ffc 176 for (i = 0; i < 16; i++)
442ea881 177 supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8);
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178
179 /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */
180 for (i = 0; i < 6; i++)
442ea881
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181 supply_register (regcache, arm_num_regs + i + 16,
182 (char *) buf + 16 * 8 + i * 4);
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183}
184
58d6951d 185static void
442ea881 186arm_fill_vfpregset (struct regcache *regcache, void *buf)
58d6951d 187{
bd9e6534 188 int num;
58d6951d 189
89abb039
YQ
190 if (regcache->tdesc == tdesc_arm_with_neon
191 || regcache->tdesc == tdesc_arm_with_vfpv3)
58d6951d 192 num = 32;
89abb039 193 else if (regcache->tdesc == tdesc_arm_with_vfpv2)
58d6951d 194 num = 16;
89abb039
YQ
195 else
196 return;
58d6951d 197
bd9e6534 198 arm_fill_vfpregset_num (regcache, buf, num);
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199}
200
201static void
442ea881 202arm_store_vfpregset (struct regcache *regcache, const void *buf)
58d6951d 203{
bd9e6534 204 int num;
58d6951d 205
89abb039
YQ
206 if (regcache->tdesc == tdesc_arm_with_neon
207 || regcache->tdesc == tdesc_arm_with_vfpv3)
58d6951d 208 num = 32;
89abb039 209 else if (regcache->tdesc == tdesc_arm_with_vfpv2)
58d6951d 210 num = 16;
89abb039
YQ
211 else
212 return;
58d6951d 213
bd9e6534 214 arm_store_vfpregset_num (regcache, buf, num);
58d6951d 215}
fb1e4ffc 216
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217extern int debug_threads;
218
0d62e5e8 219static CORE_ADDR
442ea881 220arm_get_pc (struct regcache *regcache)
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221{
222 unsigned long pc;
442ea881 223 collect_register_by_name (regcache, "pc", &pc);
d677d77d 224 if (debug_threads)
87ce2a04 225 debug_printf ("stop pc is %08lx\n", pc);
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226 return pc;
227}
228
229static void
442ea881 230arm_set_pc (struct regcache *regcache, CORE_ADDR pc)
0d62e5e8
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231{
232 unsigned long newpc = pc;
442ea881 233 supply_register_by_name (regcache, "pc", &newpc);
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234}
235
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236/* Fetch the thread-local storage pointer for libthread_db. */
237
238ps_err_e
239ps_get_thread_area (const struct ps_prochandle *ph,
1b3f6016 240 lwpid_t lwpid, int idx, void **base)
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241{
242 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
243 return PS_ERR;
244
245 /* IDX is the bias from the thread pointer to the beginning of the
246 thread descriptor. It has to be subtracted due to implementation
247 quirks in libthread_db. */
248 *base = (void *) ((char *)*base - idx);
249
250 return PS_OK;
251}
252
09b4ad9f 253
71487fd7
UW
254/* Query Hardware Breakpoint information for the target we are attached to
255 (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */
256static void
257arm_linux_init_hwbp_cap (int pid)
09b4ad9f 258{
71487fd7 259 unsigned int val;
09b4ad9f 260
71487fd7
UW
261 if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0)
262 return;
09b4ad9f 263
71487fd7
UW
264 arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff);
265 if (arm_linux_hwbp_cap.arch == 0)
266 return;
09b4ad9f 267
71487fd7
UW
268 arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff);
269 arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff);
270 arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff);
09b4ad9f 271
71487fd7
UW
272 if (arm_linux_hwbp_cap.wp_count > MAX_WPTS)
273 internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints");
274 if (arm_linux_hwbp_cap.bp_count > MAX_BPTS)
275 internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints");
09b4ad9f
UW
276}
277
278/* How many hardware breakpoints are available? */
279static int
280arm_linux_get_hw_breakpoint_count (void)
281{
71487fd7 282 return arm_linux_hwbp_cap.bp_count;
09b4ad9f
UW
283}
284
285/* How many hardware watchpoints are available? */
286static int
287arm_linux_get_hw_watchpoint_count (void)
288{
71487fd7 289 return arm_linux_hwbp_cap.wp_count;
09b4ad9f
UW
290}
291
292/* Maximum length of area watched by hardware watchpoint. */
293static int
294arm_linux_get_hw_watchpoint_max_length (void)
295{
71487fd7 296 return arm_linux_hwbp_cap.max_wp_length;
09b4ad9f
UW
297}
298
299/* Initialize an ARM hardware break-/watch-point control register value.
300 BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the
301 type of break-/watch-point; ENABLE indicates whether the point is enabled.
302 */
303static arm_hwbp_control_t
304arm_hwbp_control_initialize (unsigned byte_address_select,
305 arm_hwbp_type hwbp_type,
306 int enable)
307{
308 gdb_assert ((byte_address_select & ~0xffU) == 0);
309 gdb_assert (hwbp_type != arm_hwbp_break
310 || ((byte_address_select & 0xfU) != 0));
311
312 return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable;
313}
314
315/* Does the breakpoint control value CONTROL have the enable bit set? */
316static int
317arm_hwbp_control_is_enabled (arm_hwbp_control_t control)
318{
319 return control & 0x1;
320}
321
322/* Is the breakpoint control value CONTROL initialized? */
323static int
324arm_hwbp_control_is_initialized (arm_hwbp_control_t control)
325{
326 return control != 0;
327}
328
329/* Change a breakpoint control word so that it is in the disabled state. */
330static arm_hwbp_control_t
331arm_hwbp_control_disable (arm_hwbp_control_t control)
332{
333 return control & ~0x1;
334}
335
336/* Are two break-/watch-points equal? */
337static int
338arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1,
339 const struct arm_linux_hw_breakpoint *p2)
340{
341 return p1->address == p2->address && p1->control == p2->control;
342}
343
802e8e6d
PA
344/* Convert a raw breakpoint type to an enum arm_hwbp_type. */
345
171de4b8 346static arm_hwbp_type
802e8e6d
PA
347raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type)
348{
349 switch (raw_type)
350 {
351 case raw_bkpt_type_hw:
352 return arm_hwbp_break;
353 case raw_bkpt_type_write_wp:
354 return arm_hwbp_store;
355 case raw_bkpt_type_read_wp:
356 return arm_hwbp_load;
357 case raw_bkpt_type_access_wp:
358 return arm_hwbp_access;
359 default:
360 gdb_assert_not_reached ("unhandled raw type");
361 }
362}
363
09b4ad9f
UW
364/* Initialize the hardware breakpoint structure P for a breakpoint or
365 watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE.
b62e2b27
UW
366 Returns -1 if TYPE is unsupported, or -2 if the particular combination
367 of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE
368 represents a breakpoint and 1 if type represents a watchpoint. */
09b4ad9f 369static int
802e8e6d
PA
370arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr,
371 int len, struct arm_linux_hw_breakpoint *p)
09b4ad9f
UW
372{
373 arm_hwbp_type hwbp_type;
374 unsigned mask;
375
802e8e6d 376 hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type);
09b4ad9f
UW
377
378 if (hwbp_type == arm_hwbp_break)
379 {
380 /* For breakpoints, the length field encodes the mode. */
381 switch (len)
382 {
383 case 2: /* 16-bit Thumb mode breakpoint */
384 case 3: /* 32-bit Thumb mode breakpoint */
fcf303ab
UW
385 mask = 0x3;
386 addr &= ~1;
09b4ad9f
UW
387 break;
388 case 4: /* 32-bit ARM mode breakpoint */
389 mask = 0xf;
fcf303ab 390 addr &= ~3;
09b4ad9f
UW
391 break;
392 default:
393 /* Unsupported. */
b62e2b27 394 return -2;
09b4ad9f 395 }
09b4ad9f
UW
396 }
397 else
398 {
399 CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length ();
400 CORE_ADDR aligned_addr;
401
402 /* Can not set watchpoints for zero or negative lengths. */
403 if (len <= 0)
b62e2b27 404 return -2;
09b4ad9f
UW
405 /* The current ptrace interface can only handle watchpoints that are a
406 power of 2. */
407 if ((len & (len - 1)) != 0)
b62e2b27 408 return -2;
09b4ad9f
UW
409
410 /* Test that the range [ADDR, ADDR + LEN) fits into the largest address
411 range covered by a watchpoint. */
412 aligned_addr = addr & ~(max_wp_length - 1);
413 if (aligned_addr + max_wp_length < addr + len)
b62e2b27 414 return -2;
09b4ad9f
UW
415
416 mask = (1 << len) - 1;
417 }
418
419 p->address = (unsigned int) addr;
420 p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1);
421
422 return hwbp_type != arm_hwbp_break;
423}
424
425/* Callback to mark a watch-/breakpoint to be updated in all threads of
426 the current process. */
427
428struct update_registers_data
429{
430 int watch;
431 int i;
432};
433
434static int
435update_registers_callback (struct inferior_list_entry *entry, void *arg)
436{
d86d4aaf
DE
437 struct thread_info *thread = (struct thread_info *) entry;
438 struct lwp_info *lwp = get_thread_lwp (thread);
09b4ad9f
UW
439 struct update_registers_data *data = (struct update_registers_data *) arg;
440
441 /* Only update the threads of the current process. */
0bfdf32f 442 if (pid_of (thread) == pid_of (current_thread))
09b4ad9f
UW
443 {
444 /* The actual update is done later just before resuming the lwp,
445 we just mark that the registers need updating. */
446 if (data->watch)
447 lwp->arch_private->wpts_changed[data->i] = 1;
448 else
449 lwp->arch_private->bpts_changed[data->i] = 1;
450
451 /* If the lwp isn't stopped, force it to momentarily pause, so
452 we can update its breakpoint registers. */
453 if (!lwp->stopped)
454 linux_stop_lwp (lwp);
455 }
456
457 return 0;
458}
459
802e8e6d
PA
460static int
461arm_supports_z_point_type (char z_type)
462{
463 switch (z_type)
464 {
abeead09 465 case Z_PACKET_SW_BP:
802e8e6d
PA
466 case Z_PACKET_HW_BP:
467 case Z_PACKET_WRITE_WP:
468 case Z_PACKET_READ_WP:
469 case Z_PACKET_ACCESS_WP:
470 return 1;
471 default:
472 /* Leave the handling of sw breakpoints with the gdb client. */
473 return 0;
474 }
475}
476
09b4ad9f
UW
477/* Insert hardware break-/watchpoint. */
478static int
802e8e6d
PA
479arm_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
480 int len, struct raw_breakpoint *bp)
09b4ad9f
UW
481{
482 struct process_info *proc = current_process ();
483 struct arm_linux_hw_breakpoint p, *pts;
484 int watch, i, count;
485
486 watch = arm_linux_hw_point_initialize (type, addr, len, &p);
487 if (watch < 0)
488 {
489 /* Unsupported. */
b62e2b27 490 return watch == -1 ? 1 : -1;
09b4ad9f
UW
491 }
492
493 if (watch)
494 {
495 count = arm_linux_get_hw_watchpoint_count ();
fe978cb0 496 pts = proc->priv->arch_private->wpts;
09b4ad9f
UW
497 }
498 else
499 {
500 count = arm_linux_get_hw_breakpoint_count ();
fe978cb0 501 pts = proc->priv->arch_private->bpts;
09b4ad9f
UW
502 }
503
504 for (i = 0; i < count; i++)
505 if (!arm_hwbp_control_is_enabled (pts[i].control))
506 {
507 struct update_registers_data data = { watch, i };
508 pts[i] = p;
d86d4aaf 509 find_inferior (&all_threads, update_registers_callback, &data);
09b4ad9f
UW
510 return 0;
511 }
512
513 /* We're out of watchpoints. */
514 return -1;
515}
516
517/* Remove hardware break-/watchpoint. */
518static int
802e8e6d
PA
519arm_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
520 int len, struct raw_breakpoint *bp)
09b4ad9f
UW
521{
522 struct process_info *proc = current_process ();
523 struct arm_linux_hw_breakpoint p, *pts;
524 int watch, i, count;
525
526 watch = arm_linux_hw_point_initialize (type, addr, len, &p);
527 if (watch < 0)
528 {
529 /* Unsupported. */
530 return -1;
531 }
532
533 if (watch)
534 {
535 count = arm_linux_get_hw_watchpoint_count ();
fe978cb0 536 pts = proc->priv->arch_private->wpts;
09b4ad9f
UW
537 }
538 else
539 {
540 count = arm_linux_get_hw_breakpoint_count ();
fe978cb0 541 pts = proc->priv->arch_private->bpts;
09b4ad9f
UW
542 }
543
544 for (i = 0; i < count; i++)
545 if (arm_linux_hw_breakpoint_equal (&p, pts + i))
546 {
547 struct update_registers_data data = { watch, i };
548 pts[i].control = arm_hwbp_control_disable (pts[i].control);
d86d4aaf 549 find_inferior (&all_threads, update_registers_callback, &data);
09b4ad9f
UW
550 return 0;
551 }
552
553 /* No watchpoint matched. */
554 return -1;
555}
556
557/* Return whether current thread is stopped due to a watchpoint. */
558static int
559arm_stopped_by_watchpoint (void)
560{
0bfdf32f 561 struct lwp_info *lwp = get_thread_lwp (current_thread);
a5362b9a 562 siginfo_t siginfo;
09b4ad9f
UW
563
564 /* We must be able to set hardware watchpoints. */
565 if (arm_linux_get_hw_watchpoint_count () == 0)
566 return 0;
567
568 /* Retrieve siginfo. */
569 errno = 0;
0bfdf32f 570 ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo);
09b4ad9f
UW
571 if (errno != 0)
572 return 0;
573
574 /* This must be a hardware breakpoint. */
575 if (siginfo.si_signo != SIGTRAP
576 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
577 return 0;
578
579 /* If we are in a positive slot then we're looking at a breakpoint and not
580 a watchpoint. */
581 if (siginfo.si_errno >= 0)
582 return 0;
583
584 /* Cache stopped data address for use by arm_stopped_data_address. */
585 lwp->arch_private->stopped_data_address
586 = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
587
588 return 1;
589}
590
591/* Return data address that triggered watchpoint. Called only if
592 arm_stopped_by_watchpoint returned true. */
593static CORE_ADDR
594arm_stopped_data_address (void)
595{
0bfdf32f 596 struct lwp_info *lwp = get_thread_lwp (current_thread);
09b4ad9f
UW
597 return lwp->arch_private->stopped_data_address;
598}
599
600/* Called when a new process is created. */
601static struct arch_process_info *
602arm_new_process (void)
603{
8d749320 604 struct arch_process_info *info = XCNEW (struct arch_process_info);
09b4ad9f
UW
605 return info;
606}
607
608/* Called when a new thread is detected. */
34c703da
GB
609static void
610arm_new_thread (struct lwp_info *lwp)
09b4ad9f 611{
8d749320 612 struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
09b4ad9f
UW
613 int i;
614
615 for (i = 0; i < MAX_BPTS; i++)
616 info->bpts_changed[i] = 1;
617 for (i = 0; i < MAX_WPTS; i++)
618 info->wpts_changed[i] = 1;
619
34c703da 620 lwp->arch_private = info;
09b4ad9f
UW
621}
622
3a8a0396
DB
623static void
624arm_new_fork (struct process_info *parent, struct process_info *child)
625{
69291610
HW
626 struct arch_process_info *parent_proc_info;
627 struct arch_process_info *child_proc_info;
3a8a0396
DB
628 struct lwp_info *child_lwp;
629 struct arch_lwp_info *child_lwp_info;
630 int i;
631
632 /* These are allocated by linux_add_process. */
61a7418c
DB
633 gdb_assert (parent->priv != NULL
634 && parent->priv->arch_private != NULL);
635 gdb_assert (child->priv != NULL
636 && child->priv->arch_private != NULL);
3a8a0396 637
69291610
HW
638 parent_proc_info = parent->priv->arch_private;
639 child_proc_info = child->priv->arch_private;
640
3a8a0396
DB
641 /* Linux kernel before 2.6.33 commit
642 72f674d203cd230426437cdcf7dd6f681dad8b0d
643 will inherit hardware debug registers from parent
644 on fork/vfork/clone. Newer Linux kernels create such tasks with
645 zeroed debug registers.
646
647 GDB core assumes the child inherits the watchpoints/hw
648 breakpoints of the parent, and will remove them all from the
649 forked off process. Copy the debug registers mirrors into the
650 new process so that all breakpoints and watchpoints can be
651 removed together. The debug registers mirror will become zeroed
652 in the end before detaching the forked off process, thus making
653 this compatible with older Linux kernels too. */
654
655 *child_proc_info = *parent_proc_info;
656
657 /* Mark all the hardware breakpoints and watchpoints as changed to
658 make sure that the registers will be updated. */
659 child_lwp = find_lwp_pid (ptid_of (child));
660 child_lwp_info = child_lwp->arch_private;
661 for (i = 0; i < MAX_BPTS; i++)
662 child_lwp_info->bpts_changed[i] = 1;
663 for (i = 0; i < MAX_WPTS; i++)
664 child_lwp_info->wpts_changed[i] = 1;
665}
666
09b4ad9f
UW
667/* Called when resuming a thread.
668 If the debug regs have changed, update the thread's copies. */
669static void
670arm_prepare_to_resume (struct lwp_info *lwp)
671{
d86d4aaf
DE
672 struct thread_info *thread = get_lwp_thread (lwp);
673 int pid = lwpid_of (thread);
674 struct process_info *proc = find_process_pid (pid_of (thread));
fe978cb0 675 struct arch_process_info *proc_info = proc->priv->arch_private;
09b4ad9f
UW
676 struct arch_lwp_info *lwp_info = lwp->arch_private;
677 int i;
678
679 for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++)
680 if (lwp_info->bpts_changed[i])
681 {
682 errno = 0;
683
684 if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control))
f15f9948 685 if (ptrace (PTRACE_SETHBPREGS, pid,
b8e1b30e 686 (PTRACE_TYPE_ARG3) ((i << 1) + 1),
f15f9948 687 &proc_info->bpts[i].address) < 0)
71487fd7 688 perror_with_name ("Unexpected error setting breakpoint address");
09b4ad9f
UW
689
690 if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control))
f15f9948 691 if (ptrace (PTRACE_SETHBPREGS, pid,
b8e1b30e 692 (PTRACE_TYPE_ARG3) ((i << 1) + 2),
f15f9948 693 &proc_info->bpts[i].control) < 0)
71487fd7 694 perror_with_name ("Unexpected error setting breakpoint");
09b4ad9f
UW
695
696 lwp_info->bpts_changed[i] = 0;
697 }
698
699 for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++)
700 if (lwp_info->wpts_changed[i])
701 {
702 errno = 0;
703
704 if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control))
f15f9948 705 if (ptrace (PTRACE_SETHBPREGS, pid,
b8e1b30e 706 (PTRACE_TYPE_ARG3) -((i << 1) + 1),
f15f9948 707 &proc_info->wpts[i].address) < 0)
71487fd7 708 perror_with_name ("Unexpected error setting watchpoint address");
09b4ad9f
UW
709
710 if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control))
f15f9948 711 if (ptrace (PTRACE_SETHBPREGS, pid,
b8e1b30e 712 (PTRACE_TYPE_ARG3) -((i << 1) + 2),
f15f9948 713 &proc_info->wpts[i].control) < 0)
71487fd7 714 perror_with_name ("Unexpected error setting watchpoint");
09b4ad9f
UW
715
716 lwp_info->wpts_changed[i] = 0;
717 }
718}
719
720
58d6951d
DJ
721static int
722arm_get_hwcap (unsigned long *valp)
723{
04248ead 724 unsigned char *data = (unsigned char *) alloca (8);
58d6951d
DJ
725 int offset = 0;
726
727 while ((*the_target->read_auxv) (offset, data, 8) == 8)
728 {
729 unsigned int *data_p = (unsigned int *)data;
730 if (data_p[0] == AT_HWCAP)
731 {
732 *valp = data_p[1];
733 return 1;
734 }
735
736 offset += 8;
737 }
738
739 *valp = 0;
740 return 0;
741}
742
3aee8918
PA
743static const struct target_desc *
744arm_read_description (void)
58d6951d 745{
0bfdf32f 746 int pid = lwpid_of (current_thread);
e8b41681 747 unsigned long arm_hwcap = 0;
71487fd7
UW
748
749 /* Query hardware watchpoint/breakpoint capabilities. */
750 arm_linux_init_hwbp_cap (pid);
751
58d6951d 752 if (arm_get_hwcap (&arm_hwcap) == 0)
3aee8918 753 return tdesc_arm;
58d6951d
DJ
754
755 if (arm_hwcap & HWCAP_IWMMXT)
3aee8918 756 return tdesc_arm_with_iwmmxt;
58d6951d
DJ
757
758 if (arm_hwcap & HWCAP_VFP)
759 {
3aee8918 760 const struct target_desc *result;
58d6951d
DJ
761 char *buf;
762
763 /* NEON implies either no VFP, or VFPv3-D32. We only support
764 it with VFP. */
765 if (arm_hwcap & HWCAP_NEON)
3aee8918 766 result = tdesc_arm_with_neon;
58d6951d 767 else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3)
3aee8918 768 result = tdesc_arm_with_vfpv3;
58d6951d 769 else
3aee8918 770 result = tdesc_arm_with_vfpv2;
58d6951d
DJ
771
772 /* Now make sure that the kernel supports reading these
773 registers. Support was added in 2.6.30. */
58d6951d 774 errno = 0;
04248ead 775 buf = (char *) xmalloc (32 * 8 + 4);
58d6951d
DJ
776 if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0
777 && errno == EIO)
e8b41681
YQ
778 result = tdesc_arm;
779
58d6951d
DJ
780 free (buf);
781
3aee8918 782 return result;
58d6951d
DJ
783 }
784
785 /* The default configuration uses legacy FPA registers, probably
786 simulated. */
3aee8918 787 return tdesc_arm;
58d6951d
DJ
788}
789
3aee8918
PA
790static void
791arm_arch_setup (void)
792{
bd9e6534
YQ
793 int tid = lwpid_of (current_thread);
794 int gpregs[18];
795 struct iovec iov;
796
3aee8918 797 current_process ()->tdesc = arm_read_description ();
bd9e6534
YQ
798
799 iov.iov_base = gpregs;
800 iov.iov_len = sizeof (gpregs);
801
802 /* Check if PTRACE_GETREGSET works. */
803 if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0)
804 have_ptrace_getregset = 1;
805 else
806 have_ptrace_getregset = 0;
3aee8918
PA
807}
808
7d00775e
AT
809/* Support for hardware single step. */
810
811static int
812arm_supports_hardware_single_step (void)
813{
814 return 0;
815}
816
bd9e6534
YQ
817/* Register sets without using PTRACE_GETREGSET. */
818
3aee8918 819static struct regset_info arm_regsets[] = {
1570b33e 820 { PTRACE_GETREGS, PTRACE_SETREGS, 0, 18 * 4,
fb1e4ffc
DJ
821 GENERAL_REGS,
822 arm_fill_gregset, arm_store_gregset },
1570b33e 823 { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, 16 * 8 + 6 * 4,
fb1e4ffc
DJ
824 EXTENDED_REGS,
825 arm_fill_wmmxregset, arm_store_wmmxregset },
1570b33e 826 { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, 32 * 8 + 4,
58d6951d
DJ
827 EXTENDED_REGS,
828 arm_fill_vfpregset, arm_store_vfpregset },
50bc912a 829 NULL_REGSET
fb1e4ffc
DJ
830};
831
3aee8918
PA
832static struct regsets_info arm_regsets_info =
833 {
834 arm_regsets, /* regsets */
835 0, /* num_regsets */
836 NULL, /* disabled_regsets */
837 };
838
839static struct usrregs_info arm_usrregs_info =
840 {
841 arm_num_regs,
842 arm_regmap,
843 };
844
bd9e6534 845static struct regs_info regs_info_arm =
3aee8918
PA
846 {
847 NULL, /* regset_bitmap */
848 &arm_usrregs_info,
849 &arm_regsets_info
850 };
851
852static const struct regs_info *
853arm_regs_info (void)
854{
bd9e6534
YQ
855 const struct target_desc *tdesc = current_process ()->tdesc;
856
857 if (have_ptrace_getregset == 1
858 && (tdesc == tdesc_arm_with_neon || tdesc == tdesc_arm_with_vfpv3))
859 return &regs_info_aarch32;
860 else
861 return &regs_info_arm;
3aee8918
PA
862}
863
dd373349
AT
864struct linux_target_ops the_low_target = {
865 arm_arch_setup,
866 arm_regs_info,
867 arm_cannot_fetch_register,
868 arm_cannot_store_register,
869 NULL, /* fetch_register */
870 arm_get_pc,
871 arm_set_pc,
8689682c 872 arm_breakpoint_kind_from_pc,
dd373349 873 arm_sw_breakpoint_from_kind,
fa5308bd 874 NULL, /* get_next_pcs */
0d62e5e8
DJ
875 0,
876 arm_breakpoint_at,
802e8e6d 877 arm_supports_z_point_type,
09b4ad9f
UW
878 arm_insert_point,
879 arm_remove_point,
880 arm_stopped_by_watchpoint,
881 arm_stopped_data_address,
882 NULL, /* collect_ptrace_register */
883 NULL, /* supply_ptrace_register */
884 NULL, /* siginfo_fixup */
885 arm_new_process,
886 arm_new_thread,
3a8a0396 887 arm_new_fork,
09b4ad9f 888 arm_prepare_to_resume,
769ef81f
AT
889 NULL, /* process_qsupported */
890 NULL, /* supports_tracepoints */
891 NULL, /* get_thread_area */
892 NULL, /* install_fast_tracepoint_jump_pad */
893 NULL, /* emit_ops */
894 NULL, /* get_min_fast_tracepoint_insn_len */
895 NULL, /* supports_range_stepping */
7d00775e
AT
896 arm_breakpoint_kind_from_current_state,
897 arm_supports_hardware_single_step
2ec06d2e 898};
3aee8918
PA
899
900void
901initialize_low_arch (void)
902{
903 /* Initialize the Linux target descriptions. */
904 init_registers_arm ();
905 init_registers_arm_with_iwmmxt ();
906 init_registers_arm_with_vfpv2 ();
907 init_registers_arm_with_vfpv3 ();
bd9e6534
YQ
908
909 initialize_low_arch_aarch32 ();
3aee8918
PA
910
911 initialize_regsets_info (&arm_regsets_info);
912}
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