[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-crisv32-low.c

/* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
   Copyright 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#include "server.h"
#include "linux-low.h"
#include <sys/ptrace.h>

/* CRISv32 */
#define cris_num_regs 49

/* Note: Ignoring USP (having the stack pointer in two locations causes trouble
   without any significant gain).  */

/* Locations need to match <include/asm/arch/ptrace.h>.  */
static int cris_regmap[] = {
  1*4, 2*4, 3*4, 4*4,
  5*4, 6*4, 7*4, 8*4,
  9*4, 10*4, 11*4, 12*4,
  13*4, 14*4, 24*4, 15*4,

  -1, -1, -1, 16*4,
  -1, 22*4, 23*4, 17*4,
  -1, -1, 21*4, 20*4,
  -1, 19*4, -1, 18*4,

  25*4,

  26*4, -1,   -1,   29*4, 
  30*4, 31*4, 32*4, 33*4,
  34*4, 35*4, 36*4, 37*4,
  38*4, 39*4, 40*4, -1
  
};

extern int debug_threads;

static CORE_ADDR
cris_get_pc (void)
{
  unsigned long pc;
  collect_register_by_name ("pc", &pc);
  if (debug_threads)
    fprintf (stderr, "stop pc is %08lx\n", pc);
  return pc;
}

static void
cris_set_pc (CORE_ADDR pc)
{
  unsigned long newpc = pc;
  supply_register_by_name ("pc", &newpc);
}

static const unsigned short cris_breakpoint = 0xe938;
#define cris_breakpoint_len 2

static int
cris_breakpoint_at (CORE_ADDR where)
{
  unsigned short insn;

  (*the_target->read_memory) (where, (char *) &insn, cris_breakpoint_len);
  if (insn == cris_breakpoint)
    return 1;

  /* If necessary, recognize more trap instructions here.  GDB only uses the
     one.  */
  return 0;
}

/* We only place breakpoints in empty marker functions, and thread locking
   is outside of the function.  So rather than importing software single-step,
   we can just run until exit.  */

/* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP
   for CRISv32.  Without it, td_ta_event_getmsg in thread_db_create_event
   will fail when debugging multi-threaded applications.  */

static CORE_ADDR
cris_reinsert_addr (void)
{
  unsigned long pc;
  collect_register_by_name ("srp", &pc);
  return pc;
}

static void
cris_write_data_breakpoint (int bp, unsigned long start, unsigned long end)
{
  switch (bp)
    {
    case 0:
      supply_register_by_name ("s3", &start);
      supply_register_by_name ("s4", &end);
      break;
    case 1:
      supply_register_by_name ("s5", &start);
      supply_register_by_name ("s6", &end);
      break;
    case 2:
      supply_register_by_name ("s7", &start);
      supply_register_by_name ("s8", &end);
      break;
    case 3:
      supply_register_by_name ("s9", &start);
      supply_register_by_name ("s10", &end);
      break;
    case 4:
      supply_register_by_name ("s11", &start);
      supply_register_by_name ("s12", &end);
      break;
    case 5:
      supply_register_by_name ("s13", &start);
      supply_register_by_name ("s14", &end);
      break;
    }
}

static int
cris_insert_watchpoint (char type, CORE_ADDR addr, int len)
{
  int bp;
  unsigned long bp_ctrl;
  unsigned long start, end;
  unsigned long ccs;
  
  /* Breakpoint/watchpoint types (GDB terminology):
     0 = memory breakpoint for instructions
     (not supported; done via memory write instead)
     1 = hardware breakpoint for instructions (not supported)
     2 = write watchpoint (supported)
     3 = read watchpoint (supported)
     4 = access watchpoint (supported).  */
  
  if (type < '2' || type > '4') 
    {
      /* Unsupported.  */
      return 1;
    }

  /* Read watchpoints are set as access watchpoints, because of GDB's
     inability to deal with pure read watchpoints.  */
  if (type == '3')
    type = '4';

  /* Get the configuration register.  */
  collect_register_by_name ("s0", &bp_ctrl);

  /* The watchpoint allocation scheme is the simplest possible.
     For example, if a region is watched for read and
     a write watch is requested, a new watchpoint will
     be used.  Also, if a watch for a region that is already
     covered by one or more existing watchpoints, a new
     watchpoint will be used.  */
    
  /* First, find a free data watchpoint.  */
  for (bp = 0; bp < 6; bp++)
    {
      /* Each data watchpoint's control registers occupy 2 bits
	 (hence the 3), starting at bit 2 for D0 (hence the 2)
	 with 4 bits between for each watchpoint (yes, the 4).  */
      if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) 
	break;
    }
    
  if (bp > 5)
    {
      /* We're out of watchpoints.  */
      return -1;
    }

  /* Configure the control register first.  */
  if (type == '3' || type == '4')
    {
      /* Trigger on read.  */
      bp_ctrl |= (1 << (2 + bp * 4));
    }
  if (type == '2' || type == '4') 
    {
      /* Trigger on write.  */
      bp_ctrl |= (2 << (2 + bp * 4));
    }
  
  /* Setup the configuration register.  */
  supply_register_by_name ("s0", &bp_ctrl);
  
  /* Setup the range.  */
  start = addr;
  end = addr + len - 1;

  /* Configure the watchpoint register.  */
  cris_write_data_breakpoint (bp, start, end);

  collect_register_by_name ("ccs", &ccs);
  /* Set the S1 flag to enable watchpoints.  */
  ccs |= (1 << 19);
  supply_register_by_name ("ccs", &ccs);

  return 0;
}

static int
cris_remove_watchpoint (char type, CORE_ADDR addr, int len)
{
  int bp;
  unsigned long bp_ctrl;
  unsigned long start, end;
  
  /* Breakpoint/watchpoint types:
     0 = memory breakpoint for instructions
     (not supported; done via memory write instead)
     1 = hardware breakpoint for instructions (not supported)
     2 = write watchpoint (supported)
     3 = read watchpoint (supported)
     4 = access watchpoint (supported).  */
  if (type < '2' || type > '4')
    return -1;
  
  /* Read watchpoints are set as access watchpoints, because of GDB's
     inability to deal with pure read watchpoints.  */
  if (type == '3')
    type = '4';
  
  /* Get the configuration register.  */
  collect_register_by_name ("s0", &bp_ctrl);

  /* Try to find a watchpoint that is configured for the
     specified range, then check that read/write also matches.  */
  
  /* Ugly pointer arithmetic, since I cannot rely on a
     single switch (addr) as there may be several watchpoints with
     the same start address for example.  */

  unsigned long bp_d_regs[12];

  /* Get all range registers to simplify search.  */
  collect_register_by_name ("s3", &bp_d_regs[0]);
  collect_register_by_name ("s4", &bp_d_regs[1]);
  collect_register_by_name ("s5", &bp_d_regs[2]);
  collect_register_by_name ("s6", &bp_d_regs[3]);
  collect_register_by_name ("s7", &bp_d_regs[4]);
  collect_register_by_name ("s8", &bp_d_regs[5]);
  collect_register_by_name ("s9", &bp_d_regs[6]);
  collect_register_by_name ("s10", &bp_d_regs[7]);
  collect_register_by_name ("s11", &bp_d_regs[8]);
  collect_register_by_name ("s12", &bp_d_regs[9]);
  collect_register_by_name ("s13", &bp_d_regs[10]);
  collect_register_by_name ("s14", &bp_d_regs[11]);

  for (bp = 0; bp < 6; bp++) 
    {
      if (bp_d_regs[bp * 2] == addr 
	  && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
	/* Matching range.  */
	int bitpos = 2 + bp * 4;
	int rw_bits;
      
	/* Read/write bits for this BP.  */
	rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
      
	if ((type == '3' && rw_bits == 0x1)
	    || (type == '2' && rw_bits == 0x2) 
	    || (type == '4' && rw_bits == 0x3))
	  {
	    /* Read/write matched.  */
	    break;
	  }
      }
    }
    
  if (bp > 5)
    {
      /* No watchpoint matched.  */
      return -1;
    }
    
  /* Found a matching watchpoint.  Now, deconfigure it by
     both disabling read/write in bp_ctrl and zeroing its
     start/end addresses.  */
  bp_ctrl &= ~(3 << (2 + (bp * 4)));
  /* Setup the configuration register.  */
  supply_register_by_name ("s0", &bp_ctrl);

  start = end = 0;
  /* Configure the watchpoint register.  */
  cris_write_data_breakpoint (bp, start, end);

  /* Note that we don't clear the S1 flag here.  It's done when continuing.  */
  return 0;
}

static int
cris_stopped_by_watchpoint (void)
{
  unsigned long exs;

  collect_register_by_name ("exs", &exs);

  return (((exs & 0xff00) >> 8) == 0xc);
}

static CORE_ADDR
cris_stopped_data_address (void)
{
  unsigned long eda;

  collect_register_by_name ("eda", &eda);

  /* FIXME: Possibly adjust to match watched range.  */
  return eda;
}

static void
cris_fill_gregset (void *buf)
{
  int i;

  for (i = 0; i < cris_num_regs; i++)
    {
      if (cris_regmap[i] != -1)
	collect_register (i, ((char *) buf) + cris_regmap[i]);
    }
}

static void
cris_store_gregset (const void *buf)
{
  int i;

  for (i = 0; i < cris_num_regs; i++)
    {
      if (cris_regmap[i] != -1)
	supply_register (i, ((char *) buf) + cris_regmap[i]);
    }
}

typedef unsigned long elf_gregset_t[cris_num_regs];

struct regset_info target_regsets[] = {
  { PTRACE_GETREGS, PTRACE_SETREGS, sizeof (elf_gregset_t),
    GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
  { 0, 0, -1, -1, NULL, NULL }
};

struct linux_target_ops the_low_target = {
  -1,
  NULL,
  NULL,
  NULL,
  cris_get_pc,
  cris_set_pc,
  (const char *) &cris_breakpoint,
  cris_breakpoint_len,
  cris_reinsert_addr,
  0,
  cris_breakpoint_at,
  cris_insert_watchpoint,
  cris_remove_watchpoint,
  cris_stopped_by_watchpoint,
  cris_stopped_data_address,
};
Commit	Line	Data
45b134e5 OF	1	/* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
	2	Copyright 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
	3	Free Software Foundation, Inc.
	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 59 Temple Place - Suite 330,
	20	Boston, MA 02111-1307, USA. */
	21
	22	#include "server.h"
	23	#include "linux-low.h"
	24	#include <sys/ptrace.h>
	25
	26	/* CRISv32 */
	27	#define cris_num_regs 49
	28
	29	/* Note: Ignoring USP (having the stack pointer in two locations causes trouble
	30	without any significant gain). */
	31
	32	/* Locations need to match <include/asm/arch/ptrace.h>. */
	33	static int cris_regmap[] = {
	34	14, 24, 34, 44,
	35	54, 64, 74, 84,
	36	94, 104, 114, 124,
	37	134, 144, 244, 154,
	38
	39	-1, -1, -1, 16*4,
	40	-1, 224, 234, 17*4,
	41	-1, -1, 214, 204,
	42	-1, 194, -1, 184,
	43
	44	25*4,
	45
	46	264, -1, -1, 294,
	47	304, 314, 324, 334,
	48	344, 354, 364, 374,
	49	384, 394, 40*4, -1
	50
	51	};
	52
	53	extern int debug_threads;
	54
	55	static CORE_ADDR
	56	cris_get_pc (void)
	57	{
	58	unsigned long pc;
	59	collect_register_by_name ("pc", &pc);
	60	if (debug_threads)
	61	fprintf (stderr, "stop pc is %08lx\n", pc);
	62	return pc;
	63	}
	64
65	static void
66	cris_set_pc (CORE_ADDR pc)
67	{
68	unsigned long newpc = pc;
69	supply_register_by_name ("pc", &newpc);
70	}
71
72	static const unsigned short cris_breakpoint = 0xe938;
73	#define cris_breakpoint_len 2
74
75	static int
76	cris_breakpoint_at (CORE_ADDR where)
77	{
78	unsigned short insn;
79
80	(the_target->read_memory) (where, (char ) &insn, cris_breakpoint_len);
81	if (insn == cris_breakpoint)
82	return 1;
83
84	/* If necessary, recognize more trap instructions here. GDB only uses the
85	one. */
86	return 0;
87	}
88
89	/* We only place breakpoints in empty marker functions, and thread locking
90	is outside of the function. So rather than importing software single-step,
91	we can just run until exit. */
92
93	/* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP
94	for CRISv32. Without it, td_ta_event_getmsg in thread_db_create_event
95	will fail when debugging multi-threaded applications. */
96
97	static CORE_ADDR
98	cris_reinsert_addr (void)
99	{
100	unsigned long pc;
101	collect_register_by_name ("srp", &pc);
102	return pc;
103	}
104
105	static void
106	cris_write_data_breakpoint (int bp, unsigned long start, unsigned long end)
107	{
108	switch (bp)
109	{
110	case 0:
111	supply_register_by_name ("s3", &start);
112	supply_register_by_name ("s4", &end);
113	break;
114	case 1:
115	supply_register_by_name ("s5", &start);
116	supply_register_by_name ("s6", &end);
117	break;
118	case 2:
119	supply_register_by_name ("s7", &start);
120	supply_register_by_name ("s8", &end);
121	break;
122	case 3:
123	supply_register_by_name ("s9", &start);
124	supply_register_by_name ("s10", &end);
125	break;
126	case 4:
127	supply_register_by_name ("s11", &start);
128	supply_register_by_name ("s12", &end);
129	break;
130	case 5:
131	supply_register_by_name ("s13", &start);
132	supply_register_by_name ("s14", &end);
133	break;
134	}
135	}
136
137	static int
138	cris_insert_watchpoint (char type, CORE_ADDR addr, int len)
139	{
140	int bp;
141	unsigned long bp_ctrl;
142	unsigned long start, end;
143	unsigned long ccs;
144
145	/* Breakpoint/watchpoint types (GDB terminology):
146	0 = memory breakpoint for instructions
147	(not supported; done via memory write instead)
148	1 = hardware breakpoint for instructions (not supported)
149	2 = write watchpoint (supported)
150	3 = read watchpoint (supported)
151	4 = access watchpoint (supported). */
152
153	if (type < '2' \|\| type > '4')
154	{
155	/* Unsupported. */
156	return 1;
157	}
158
159	/* Read watchpoints are set as access watchpoints, because of GDB's
160	inability to deal with pure read watchpoints. */
161	if (type == '3')
162	type = '4';
163
164	/* Get the configuration register. */
165	collect_register_by_name ("s0", &bp_ctrl);
166
167	/* The watchpoint allocation scheme is the simplest possible.
168	For example, if a region is watched for read and
169	a write watch is requested, a new watchpoint will
170	be used. Also, if a watch for a region that is already
171	covered by one or more existing watchpoints, a new
172	watchpoint will be used. */
173
174	/* First, find a free data watchpoint. */
175	for (bp = 0; bp < 6; bp++)
176	{
177	/* Each data watchpoint's control registers occupy 2 bits
178	(hence the 3), starting at bit 2 for D0 (hence the 2)
179	with 4 bits between for each watchpoint (yes, the 4). */
180	if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
181	break;
182	}
183
184	if (bp > 5)
185	{
186	/* We're out of watchpoints. */
187	return -1;
188	}
189
190	/* Configure the control register first. */
191	if (type == '3' \|\| type == '4')
192	{
193	/* Trigger on read. */
194	bp_ctrl \|= (1 << (2 + bp * 4));
195	}
196	if (type == '2' \|\| type == '4')
197	{
198	/* Trigger on write. */
199	bp_ctrl \|= (2 << (2 + bp * 4));
200	}
201
202	/* Setup the configuration register. */
203	supply_register_by_name ("s0", &bp_ctrl);
204
205	/* Setup the range. */
206	start = addr;
207	end = addr + len - 1;
208
209	/* Configure the watchpoint register. */
210	cris_write_data_breakpoint (bp, start, end);
211
212	collect_register_by_name ("ccs", &ccs);
213	/* Set the S1 flag to enable watchpoints. */
214	ccs \|= (1 << 19);
215	supply_register_by_name ("ccs", &ccs);
216
217	return 0;
218	}
219
220	static int
221	cris_remove_watchpoint (char type, CORE_ADDR addr, int len)
222	{
223	int bp;
224	unsigned long bp_ctrl;
225	unsigned long start, end;
226
227	/* Breakpoint/watchpoint types:
228	0 = memory breakpoint for instructions
229	(not supported; done via memory write instead)
230	1 = hardware breakpoint for instructions (not supported)
231	2 = write watchpoint (supported)
232	3 = read watchpoint (supported)
233	4 = access watchpoint (supported). */
234	if (type < '2' \|\| type > '4')
235	return -1;
236
237	/* Read watchpoints are set as access watchpoints, because of GDB's
238	inability to deal with pure read watchpoints. */
239	if (type == '3')
240	type = '4';
241
242	/* Get the configuration register. */
243	collect_register_by_name ("s0", &bp_ctrl);
244
245	/* Try to find a watchpoint that is configured for the
246	specified range, then check that read/write also matches. */
247
248	/* Ugly pointer arithmetic, since I cannot rely on a
249	single switch (addr) as there may be several watchpoints with
250	the same start address for example. */
251
252	unsigned long bp_d_regs[12];
253
254	/* Get all range registers to simplify search. */
255	collect_register_by_name ("s3", &bp_d_regs[0]);
256	collect_register_by_name ("s4", &bp_d_regs[1]);
257	collect_register_by_name ("s5", &bp_d_regs[2]);
258	collect_register_by_name ("s6", &bp_d_regs[3]);
259	collect_register_by_name ("s7", &bp_d_regs[4]);
260	collect_register_by_name ("s8", &bp_d_regs[5]);
261	collect_register_by_name ("s9", &bp_d_regs[6]);
262	collect_register_by_name ("s10", &bp_d_regs[7]);
263	collect_register_by_name ("s11", &bp_d_regs[8]);
264	collect_register_by_name ("s12", &bp_d_regs[9]);
265	collect_register_by_name ("s13", &bp_d_regs[10]);
266	collect_register_by_name ("s14", &bp_d_regs[11]);
267
268	for (bp = 0; bp < 6; bp++)
269	{
270	if (bp_d_regs[bp * 2] == addr
271	&& bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
272	/* Matching range. */
273	int bitpos = 2 + bp * 4;
274	int rw_bits;
275
276	/* Read/write bits for this BP. */
277	rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
278
279	if ((type == '3' && rw_bits == 0x1)
280	\|\| (type == '2' && rw_bits == 0x2)
281	\|\| (type == '4' && rw_bits == 0x3))
282	{
283	/* Read/write matched. */
284	break;
285	}
286	}
287	}
288
289	if (bp > 5)
290	{
291	/* No watchpoint matched. */
292	return -1;
293	}
294
295	/* Found a matching watchpoint. Now, deconfigure it by
296	both disabling read/write in bp_ctrl and zeroing its
297	start/end addresses. */
298	bp_ctrl &= ~(3 << (2 + (bp * 4)));
299	/* Setup the configuration register. */
300	supply_register_by_name ("s0", &bp_ctrl);
301
302	start = end = 0;
303	/* Configure the watchpoint register. */
304	cris_write_data_breakpoint (bp, start, end);
305
306	/* Note that we don't clear the S1 flag here. It's done when continuing. */
307	return 0;
308	}
309
310	static int
311	cris_stopped_by_watchpoint (void)
312	{
313	unsigned long exs;
314
315	collect_register_by_name ("exs", &exs);
316
317	return (((exs & 0xff00) >> 8) == 0xc);
318	}
319
320	static CORE_ADDR
321	cris_stopped_data_address (void)
322	{
323	unsigned long eda;
324
325	collect_register_by_name ("eda", &eda);
326
327	/* FIXME: Possibly adjust to match watched range. */
328	return eda;
329	}
330
331	static void
332	cris_fill_gregset (void *buf)
333	{
334	int i;
335
336	for (i = 0; i < cris_num_regs; i++)
337	{
338	if (cris_regmap[i] != -1)
339	collect_register (i, ((char *) buf) + cris_regmap[i]);
340	}
341	}
342
343	static void
344	cris_store_gregset (const void *buf)
345	{
346	int i;
347
348	for (i = 0; i < cris_num_regs; i++)
349	{
350	if (cris_regmap[i] != -1)
351	supply_register (i, ((char *) buf) + cris_regmap[i]);
352	}
353	}
354
355	typedef unsigned long elf_gregset_t[cris_num_regs];
356
357	struct regset_info target_regsets[] = {
358	{ PTRACE_GETREGS, PTRACE_SETREGS, sizeof (elf_gregset_t),
359	GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
360	{ 0, 0, -1, -1, NULL, NULL }
361	};
362
363	struct linux_target_ops the_low_target = {
364	-1,
365	NULL,
366	NULL,
367	NULL,
368	cris_get_pc,
369	cris_set_pc,
370	(const char *) &cris_breakpoint,
371	cris_breakpoint_len,
372	cris_reinsert_addr,
373	0,
374	cris_breakpoint_at,
375	cris_insert_watchpoint,
376	cris_remove_watchpoint,
377	cris_stopped_by_watchpoint,
378	cris_stopped_data_address,
379	};