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[PowerPC] Add support for EBB and PMU registers
[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-ppc-low.c
CommitLineData
0a30fbc4
DJ		 1/* GNU/Linux/PowerPC specific low level interface, for the remote server for
2 GDB.
e2882c85 3 Copyright (C) 1995-2018 Free Software Foundation, Inc.
0a30fbc4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ		 19
20#include "server.h"
58caa3dc 21#include "linux-low.h"
0a30fbc4 22
7ca18ed6
EBM		 23#include "elf/common.h"
24#include <sys/uio.h>
b6430ec3 25#include <elf.h>
0a30fbc4
DJ		 26#include <asm/ptrace.h>
27
bd64614e
PFC		 28#include "arch/ppc-linux-common.h"
29#include "arch/ppc-linux-tdesc.h"
514c5338 30#include "nat/ppc-linux.h"
bd64614e 31#include "linux-ppc-tdesc-init.h"
a2174ba4
MK		 32#include "ax.h"
33#include "tracepoint.h"
34
35#define PPC_FIELD(value, from, len) \
36 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
37#define PPC_SEXT(v, bs) \
38 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
39 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
40 - ((CORE_ADDR) 1 << ((bs) - 1)))
41#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
42#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
43#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
44#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
b6430ec3 45
7ca18ed6
EBM		 46/* Holds the AT_HWCAP auxv entry. */
47
b6430ec3
UW		 48static unsigned long ppc_hwcap;
49
7ca18ed6
EBM		 50/* Holds the AT_HWCAP2 auxv entry. */
51
52static unsigned long ppc_hwcap2;
53
b6430ec3 54
7284e1be
UW		 55#define ppc_num_regs 73
56
5b0a002e
UW		 57#ifdef __powerpc64__
58/* We use a constant for FPSCR instead of PT_FPSCR, because
59 many shipped PPC64 kernels had the wrong value in ptrace.h. */
60static int ppc_regmap[] =
61 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
62 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
63 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
64 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
65 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
66 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
67 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
68 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
69 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
70 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
71 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
72 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
73 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
74 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
75 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
76 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
77 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
7284e1be
UW		 78 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
79 PT_ORIG_R3 * 8, PT_TRAP * 8 };
5b0a002e 80#else
0a30fbc4 81/* Currently, don't check/send MQ. */
2ec06d2e 82static int ppc_regmap[] =
0a30fbc4
DJ		 83 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
84 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
85 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
86 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
87 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
88 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
89 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
90 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
91 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
92 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
93 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
94 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
95 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
96 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
97 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
98 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
99 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 100 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
101 PT_ORIG_R3 * 4, PT_TRAP * 4
b6430ec3
UW		 102 };
103
104static int ppc_regmap_e500[] =
105 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
106 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
107 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
108 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
109 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
110 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
111 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
112 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
113 -1, -1, -1, -1,
114 -1, -1, -1, -1,
115 -1, -1, -1, -1,
116 -1, -1, -1, -1,
117 -1, -1, -1, -1,
118 -1, -1, -1, -1,
119 -1, -1, -1, -1,
120 -1, -1, -1, -1,
121 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 122 PT_CTR * 4, PT_XER * 4, -1,
123 PT_ORIG_R3 * 4, PT_TRAP * 4
30ed0a8f 124 };
5b0a002e 125#endif
0a30fbc4 126
7ca18ed6
EBM		 127/* Check whether the kernel provides a register set with number
128 REGSET_ID of size REGSETSIZE for process/thread TID. */
129
130static int
131ppc_check_regset (int tid, int regset_id, int regsetsize)
132{
133 void *buf = alloca (regsetsize);
134 struct iovec iov;
135
136 iov.iov_base = buf;
137 iov.iov_len = regsetsize;
138
139 if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
140 || errno == ENODATA)
141 return 1;
142 return 0;
143}
144
2ec06d2e
DJ		 145static int
146ppc_cannot_store_register (int regno)
0a30fbc4 147{
3aee8918
PA		 148 const struct target_desc *tdesc = current_process ()->tdesc;
149
b6430ec3 150#ifndef __powerpc64__
bc1e36ca 151 /* Some kernels do not allow us to store fpscr. */
3aee8918
PA		 152 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
153 && regno == find_regno (tdesc, "fpscr"))
bc1e36ca 154 return 2;
30ed0a8f 155#endif
bc1e36ca 156
7284e1be 157 /* Some kernels do not allow us to store orig_r3 or trap. */
3aee8918
PA		 158 if (regno == find_regno (tdesc, "orig_r3")
159 || regno == find_regno (tdesc, "trap"))
7284e1be
UW		 160 return 2;
161
0a30fbc4
DJ		 162 return 0;
163}
164
2ec06d2e
DJ		 165static int
166ppc_cannot_fetch_register (int regno)
0a30fbc4
DJ		 167{
168 return 0;
169}
170
5b0a002e 171static void
442ea881 172ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
5b0a002e 173{
76b233dd
UW		 174 memset (buf, 0, sizeof (long));
175
2e4bb98a
EBM		 176 if (__BYTE_ORDER == __LITTLE_ENDIAN)
177 {
178 /* Little-endian values always sit at the left end of the buffer. */
179 collect_register (regcache, regno, buf);
180 }
181 else if (__BYTE_ORDER == __BIG_ENDIAN)
182 {
183 /* Big-endian values sit at the right end of the buffer. In case of
184 registers whose sizes are smaller than sizeof (long), we must use a
185 padding to access them correctly. */
186 int size = register_size (regcache->tdesc, regno);
187
188 if (size < sizeof (long))
189 collect_register (regcache, regno, buf + sizeof (long) - size);
190 else
191 collect_register (regcache, regno, buf);
192 }
5b0a002e 193 else
2e4bb98a 194 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 195}
196
197static void
442ea881
PA		 198ppc_supply_ptrace_register (struct regcache *regcache,
199 int regno, const char *buf)
5b0a002e 200{
2e4bb98a
EBM		 201 if (__BYTE_ORDER == __LITTLE_ENDIAN)
202 {
203 /* Little-endian values always sit at the left end of the buffer. */
204 supply_register (regcache, regno, buf);
205 }
206 else if (__BYTE_ORDER == __BIG_ENDIAN)
207 {
208 /* Big-endian values sit at the right end of the buffer. In case of
209 registers whose sizes are smaller than sizeof (long), we must use a
210 padding to access them correctly. */
211 int size = register_size (regcache->tdesc, regno);
212
213 if (size < sizeof (long))
214 supply_register (regcache, regno, buf + sizeof (long) - size);
215 else
216 supply_register (regcache, regno, buf);
217 }
5b0a002e 218 else
2e4bb98a 219 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 220}
221
0b9ff2c0
UW		 222
223#define INSTR_SC 0x44000002
224#define NR_spu_run 0x0116
225
226/* If the PPU thread is currently stopped on a spu_run system call,
227 return to FD and ADDR the file handle and NPC parameter address
228 used with the system call. Return non-zero if successful. */
229static int
442ea881 230parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr)
0b9ff2c0
UW		 231{
232 CORE_ADDR curr_pc;
233 int curr_insn;
234 int curr_r0;
235
3aee8918 236 if (register_size (regcache->tdesc, 0) == 4)
0b9ff2c0
UW		 237 {
238 unsigned int pc, r0, r3, r4;
442ea881
PA		 239 collect_register_by_name (regcache, "pc", &pc);
240 collect_register_by_name (regcache, "r0", &r0);
241 collect_register_by_name (regcache, "orig_r3", &r3);
242 collect_register_by_name (regcache, "r4", &r4);
0b9ff2c0
UW		 243 curr_pc = (CORE_ADDR) pc;
244 curr_r0 = (int) r0;
245 *fd = (int) r3;
246 *addr = (CORE_ADDR) r4;
247 }
248 else
249 {
250 unsigned long pc, r0, r3, r4;
442ea881
PA		 251 collect_register_by_name (regcache, "pc", &pc);
252 collect_register_by_name (regcache, "r0", &r0);
253 collect_register_by_name (regcache, "orig_r3", &r3);
254 collect_register_by_name (regcache, "r4", &r4);
0b9ff2c0
UW		 255 curr_pc = (CORE_ADDR) pc;
256 curr_r0 = (int) r0;
257 *fd = (int) r3;
258 *addr = (CORE_ADDR) r4;
259 }
260
261 /* Fetch instruction preceding current NIP. */
262 if ((*the_target->read_memory) (curr_pc - 4,
263 (unsigned char *) &curr_insn, 4) != 0)
264 return 0;
265 /* It should be a "sc" instruction. */
266 if (curr_insn != INSTR_SC)
267 return 0;
268 /* System call number should be NR_spu_run. */
269 if (curr_r0 != NR_spu_run)
270 return 0;
271
272 return 1;
273}
274
0d62e5e8 275static CORE_ADDR
442ea881 276ppc_get_pc (struct regcache *regcache)
0d62e5e8 277{
0b9ff2c0
UW		 278 CORE_ADDR addr;
279 int fd;
280
442ea881 281 if (parse_spufs_run (regcache, &fd, &addr))
0b9ff2c0
UW		 282 {
283 unsigned int pc;
284 (*the_target->read_memory) (addr, (unsigned char *) &pc, 4);
493e2a69
MS		 285 return ((CORE_ADDR)1 << 63)
286 | ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4);
0b9ff2c0 287 }
3aee8918 288 else if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 289 {
290 unsigned int pc;
442ea881 291 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 292 return (CORE_ADDR) pc;
293 }
294 else
295 {
296 unsigned long pc;
442ea881 297 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 298 return (CORE_ADDR) pc;
299 }
0d62e5e8
DJ		 300}
301
302static void
442ea881 303ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
0d62e5e8 304{
0b9ff2c0
UW		 305 CORE_ADDR addr;
306 int fd;
307
442ea881 308 if (parse_spufs_run (regcache, &fd, &addr))
0b9ff2c0
UW		 309 {
310 unsigned int newpc = pc;
311 (*the_target->write_memory) (addr, (unsigned char *) &newpc, 4);
312 }
3aee8918 313 else if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 314 {
315 unsigned int newpc = pc;
442ea881 316 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 317 }
318 else
319 {
320 unsigned long newpc = pc;
442ea881 321 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 322 }
323}
324
b6430ec3
UW		 325
326static int
a2174ba4 327ppc_get_auxv (unsigned long type, unsigned long *valp)
b6430ec3 328{
3aee8918
PA		 329 const struct target_desc *tdesc = current_process ()->tdesc;
330 int wordsize = register_size (tdesc, 0);
2bc84e8a 331 unsigned char *data = (unsigned char *) alloca (2 * wordsize);
b6430ec3
UW		 332 int offset = 0;
333
334 while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize)
335 {
336 if (wordsize == 4)
337 {
338 unsigned int *data_p = (unsigned int *)data;
a2174ba4 339 if (data_p[0] == type)
b6430ec3
UW		 340 {
341 *valp = data_p[1];
342 return 1;
343 }
344 }
345 else
346 {
347 unsigned long *data_p = (unsigned long *)data;
a2174ba4 348 if (data_p[0] == type)
b6430ec3
UW		 349 {
350 *valp = data_p[1];
351 return 1;
352 }
353 }
354
355 offset += 2 * wordsize;
356 }
357
358 *valp = 0;
359 return 0;
360}
361
3aee8918
PA		 362#ifndef __powerpc64__
363static int ppc_regmap_adjusted;
364#endif
365
0d62e5e8 366
5b0a002e 367/* Correct in either endianness.
0d62e5e8
DJ		 368 This instruction is "twge r2, r2", which GDB uses as a software
369 breakpoint. */
5b0a002e 370static const unsigned int ppc_breakpoint = 0x7d821008;
0d62e5e8
DJ		 371#define ppc_breakpoint_len 4
372
dd373349
AT		 373/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
374
375static const gdb_byte *
376ppc_sw_breakpoint_from_kind (int kind, int *size)
377{
378 *size = ppc_breakpoint_len;
379 return (const gdb_byte *) &ppc_breakpoint;
380}
381
0d62e5e8
DJ		 382static int
383ppc_breakpoint_at (CORE_ADDR where)
384{
5b0a002e 385 unsigned int insn;
0d62e5e8 386
0b9ff2c0
UW		 387 if (where & ((CORE_ADDR)1 << 63))
388 {
389 char mem_annex[32];
390 sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff));
391 (*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn,
392 NULL, where & 0xffffffff, 4);
393 if (insn == 0x3fff)
394 return 1;
395 }
396 else
397 {
398 (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
399 if (insn == ppc_breakpoint)
400 return 1;
401 /* If necessary, recognize more trap instructions here. GDB only uses
402 the one. */
403 }
404
0d62e5e8
DJ		 405 return 0;
406}
407
657f9cde
WW		 408/* Implement supports_z_point_type target-ops.
409 Returns true if type Z_TYPE breakpoint is supported.
410
411 Handling software breakpoint at server side, so tracepoints
412 and breakpoints can be inserted at the same location. */
413
414static int
415ppc_supports_z_point_type (char z_type)
416{
417 switch (z_type)
418 {
419 case Z_PACKET_SW_BP:
420 return 1;
421 case Z_PACKET_HW_BP:
422 case Z_PACKET_WRITE_WP:
423 case Z_PACKET_ACCESS_WP:
424 default:
425 return 0;
426 }
427}
428
429/* Implement insert_point target-ops.
430 Returns 0 on success, -1 on failure and 1 on unsupported. */
431
432static int
433ppc_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
434 int size, struct raw_breakpoint *bp)
435{
436 switch (type)
437 {
438 case raw_bkpt_type_sw:
439 return insert_memory_breakpoint (bp);
440
441 case raw_bkpt_type_hw:
442 case raw_bkpt_type_write_wp:
443 case raw_bkpt_type_access_wp:
444 default:
445 /* Unsupported. */
446 return 1;
447 }
448}
449
450/* Implement remove_point target-ops.
451 Returns 0 on success, -1 on failure and 1 on unsupported. */
452
453static int
454ppc_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
455 int size, struct raw_breakpoint *bp)
456{
457 switch (type)
458 {
459 case raw_bkpt_type_sw:
460 return remove_memory_breakpoint (bp);
461
462 case raw_bkpt_type_hw:
463 case raw_bkpt_type_write_wp:
464 case raw_bkpt_type_access_wp:
465 default:
466 /* Unsupported. */
467 return 1;
468 }
469}
470
e9d25b98
DJ		 471/* Provide only a fill function for the general register set. ps_lgetregs
472 will use this for NPTL support. */
473
442ea881 474static void ppc_fill_gregset (struct regcache *regcache, void *buf)
e9d25b98
DJ		 475{
476 int i;
477
478 for (i = 0; i < 32; i++)
442ea881 479 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 480
481 for (i = 64; i < 70; i++)
442ea881 482 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
7284e1be
UW		 483
484 for (i = 71; i < 73; i++)
442ea881 485 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 486}
487
7ca18ed6
EBM		 488/* Program Priority Register regset fill function. */
489
490static void
491ppc_fill_pprregset (struct regcache *regcache, void *buf)
492{
493 char *ppr = (char *) buf;
494
495 collect_register_by_name (regcache, "ppr", ppr);
496}
497
498/* Program Priority Register regset store function. */
499
500static void
501ppc_store_pprregset (struct regcache *regcache, const void *buf)
502{
503 const char *ppr = (const char *) buf;
504
505 supply_register_by_name (regcache, "ppr", ppr);
506}
507
508/* Data Stream Control Register regset fill function. */
509
510static void
511ppc_fill_dscrregset (struct regcache *regcache, void *buf)
512{
513 char *dscr = (char *) buf;
514
515 collect_register_by_name (regcache, "dscr", dscr);
516}
517
518/* Data Stream Control Register regset store function. */
519
520static void
521ppc_store_dscrregset (struct regcache *regcache, const void *buf)
522{
523 const char *dscr = (const char *) buf;
524
525 supply_register_by_name (regcache, "dscr", dscr);
526}
527
f2cf6173
EBM		 528/* Target Address Register regset fill function. */
529
530static void
531ppc_fill_tarregset (struct regcache *regcache, void *buf)
532{
533 char *tar = (char *) buf;
534
535 collect_register_by_name (regcache, "tar", tar);
536}
537
538/* Target Address Register regset store function. */
539
540static void
541ppc_store_tarregset (struct regcache *regcache, const void *buf)
542{
543 const char *tar = (const char *) buf;
544
545 supply_register_by_name (regcache, "tar", tar);
546}
547
232bfb86
EBM		 548/* Event-Based Branching regset store function. Unless the inferior
549 has a perf event open, ptrace can return in error when reading and
550 writing to the regset, with ENODATA. For reading, the registers
551 will correctly show as unavailable. For writing, gdbserver
552 currently only caches any register writes from P and G packets and
553 the stub always tries to write all the regsets when resuming the
554 inferior, which would result in frequent warnings. For this
555 reason, we don't define a fill function. This also means that the
556 client-side regcache will be dirty if the user tries to write to
557 the EBB registers. G packets that the client sends to write to
558 unrelated registers will also include data for EBB registers, even
559 if they are unavailable. */
560
561static void
562ppc_store_ebbregset (struct regcache *regcache, const void *buf)
563{
564 const char *regset = (const char *) buf;
565
566 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
567 .dat file is BESCR, EBBHR, EBBRR. */
568 supply_register_by_name (regcache, "ebbrr", &regset[0]);
569 supply_register_by_name (regcache, "ebbhr", &regset[8]);
570 supply_register_by_name (regcache, "bescr", &regset[16]);
571}
572
573/* Performance Monitoring Unit regset fill function. */
574
575static void
576ppc_fill_pmuregset (struct regcache *regcache, void *buf)
577{
578 char *regset = (char *) buf;
579
580 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
581 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
582 collect_register_by_name (regcache, "siar", &regset[0]);
583 collect_register_by_name (regcache, "sdar", &regset[8]);
584 collect_register_by_name (regcache, "sier", &regset[16]);
585 collect_register_by_name (regcache, "mmcr2", &regset[24]);
586 collect_register_by_name (regcache, "mmcr0", &regset[32]);
587}
588
589/* Performance Monitoring Unit regset store function. */
590
591static void
592ppc_store_pmuregset (struct regcache *regcache, const void *buf)
593{
594 const char *regset = (const char *) buf;
595
596 supply_register_by_name (regcache, "siar", &regset[0]);
597 supply_register_by_name (regcache, "sdar", &regset[8]);
598 supply_register_by_name (regcache, "sier", &regset[16]);
599 supply_register_by_name (regcache, "mmcr2", &regset[24]);
600 supply_register_by_name (regcache, "mmcr0", &regset[32]);
601}
602
677c5bb1 603static void
442ea881 604ppc_fill_vsxregset (struct regcache *regcache, void *buf)
677c5bb1
LM		 605{
606 int i, base;
2bc84e8a 607 char *regset = (char *) buf;
677c5bb1 608
3aee8918 609 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 610 for (i = 0; i < 32; i++)
442ea881 611 collect_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 612}
613
614static void
442ea881 615ppc_store_vsxregset (struct regcache *regcache, const void *buf)
677c5bb1
LM		 616{
617 int i, base;
2bc84e8a 618 const char *regset = (const char *) buf;
677c5bb1 619
3aee8918 620 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 621 for (i = 0; i < 32; i++)
442ea881 622 supply_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 623}
624
30ed0a8f 625static void
442ea881 626ppc_fill_vrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 627{
628 int i, base;
2bc84e8a 629 char *regset = (char *) buf;
1d75a658 630 int vscr_offset = 0;
30ed0a8f 631
3aee8918 632 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 633 for (i = 0; i < 32; i++)
442ea881 634 collect_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 635
1d75a658
PFC		 636 if (__BYTE_ORDER == __BIG_ENDIAN)
637 vscr_offset = 12;
638
1d75a658
PFC		 639 collect_register_by_name (regcache, "vscr",
640 &regset[32 * 16 + vscr_offset]);
641
442ea881 642 collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 643}
644
645static void
442ea881 646ppc_store_vrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 647{
648 int i, base;
2bc84e8a 649 const char *regset = (const char *) buf;
1d75a658 650 int vscr_offset = 0;
30ed0a8f 651
3aee8918 652 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 653 for (i = 0; i < 32; i++)
442ea881 654 supply_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 655
1d75a658
PFC		 656 if (__BYTE_ORDER == __BIG_ENDIAN)
657 vscr_offset = 12;
658
659 supply_register_by_name (regcache, "vscr",
660 &regset[32 * 16 + vscr_offset]);
442ea881 661 supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 662}
663
30ed0a8f
DJ		 664struct gdb_evrregset_t
665{
666 unsigned long evr[32];
667 unsigned long long acc;
668 unsigned long spefscr;
669};
670
671static void
442ea881 672ppc_fill_evrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 673{
674 int i, ev0;
2bc84e8a 675 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf;
30ed0a8f 676
3aee8918 677 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 678 for (i = 0; i < 32; i++)
442ea881 679 collect_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 680
442ea881
PA		 681 collect_register_by_name (regcache, "acc", &regset->acc);
682 collect_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f
DJ		 683}
684
685static void
442ea881 686ppc_store_evrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 687{
688 int i, ev0;
2bc84e8a 689 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf;
30ed0a8f 690
3aee8918 691 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 692 for (i = 0; i < 32; i++)
442ea881 693 supply_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 694
442ea881
PA		 695 supply_register_by_name (regcache, "acc", &regset->acc);
696 supply_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f 697}
30ed0a8f 698
7d00775e
AT		 699/* Support for hardware single step. */
700
701static int
702ppc_supports_hardware_single_step (void)
703{
704 return 1;
705}
706
3aee8918 707static struct regset_info ppc_regsets[] = {
30ed0a8f
DJ		 708 /* List the extra register sets before GENERAL_REGS. That way we will
709 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
710 general registers. Some kernels support these, but not the newer
711 PPC_PTRACE_GETREGS. */
232bfb86
EBM		 712 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS,
713 NULL, ppc_store_ebbregset },
714 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS,
715 ppc_fill_pmuregset, ppc_store_pmuregset },
f2cf6173
EBM		 716 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
717 ppc_fill_tarregset, ppc_store_tarregset },
7ca18ed6
EBM		 718 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
719 ppc_fill_pprregset, ppc_store_pprregset },
720 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
721 ppc_fill_dscrregset, ppc_store_dscrregset },
7273b5fc 722 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
677c5bb1 723 ppc_fill_vsxregset, ppc_store_vsxregset },
7273b5fc 724 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 725 ppc_fill_vrregset, ppc_store_vrregset },
7273b5fc 726 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 727 ppc_fill_evrregset, ppc_store_evrregset },
1570b33e 728 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
50bc912a 729 NULL_REGSET
e9d25b98
DJ		 730};
731
3aee8918
PA		 732static struct usrregs_info ppc_usrregs_info =
733 {
734 ppc_num_regs,
735 ppc_regmap,
736 };
737
738static struct regsets_info ppc_regsets_info =
739 {
740 ppc_regsets, /* regsets */
741 0, /* num_regsets */
742 NULL, /* disabled_regsets */
743 };
744
745static struct regs_info regs_info =
746 {
747 NULL, /* regset_bitmap */
748 &ppc_usrregs_info,
749 &ppc_regsets_info
750 };
751
752static const struct regs_info *
753ppc_regs_info (void)
754{
755 return &regs_info;
756}
757
e6c5bb05
SM		 758static void
759ppc_arch_setup (void)
760{
761 const struct target_desc *tdesc;
7273b5fc 762 struct regset_info *regset;
bd64614e 763 struct ppc_linux_features features = ppc_linux_no_features;
7273b5fc 764
2e077f5e 765 int tid = lwpid_of (current_thread);
bd64614e 766
2e077f5e 767 features.wordsize = ppc_linux_target_wordsize (tid);
e6c5bb05 768
bd64614e 769 if (features.wordsize == 4)
bd64614e 770 tdesc = tdesc_powerpc_32l;
2e077f5e
PFC		 771 else
772 tdesc = tdesc_powerpc_64l;
773
774 current_process ()->tdesc = tdesc;
e6c5bb05 775
bd64614e
PFC		 776 /* The value of current_process ()->tdesc needs to be set for this
777 call. */
a2174ba4 778 ppc_get_auxv (AT_HWCAP, &ppc_hwcap);
7ca18ed6 779 ppc_get_auxv (AT_HWCAP2, &ppc_hwcap2);
bd64614e
PFC		 780
781 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
782
783 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
784 features.vsx = true;
785
786 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
787 features.altivec = true;
788
7ca18ed6
EBM		 789 if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
790 && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
791 && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
f2cf6173
EBM		 792 {
793 features.ppr_dscr = true;
794 if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
795 && (ppc_hwcap2 & PPC_FEATURE2_TAR)
232bfb86 796 && (ppc_hwcap2 & PPC_FEATURE2_EBB)
f2cf6173 797 && ppc_check_regset (tid, NT_PPC_TAR,
232bfb86
EBM		 798 PPC_LINUX_SIZEOF_TARREGSET)
799 && ppc_check_regset (tid, NT_PPC_EBB,
800 PPC_LINUX_SIZEOF_EBBREGSET)
801 && ppc_check_regset (tid, NT_PPC_PMU,
802 PPC_LINUX_SIZEOF_PMUREGSET))
f2cf6173
EBM		 803 features.isa207 = true;
804 }
7ca18ed6 805
e6c5bb05 806 if (ppc_hwcap & PPC_FEATURE_CELL)
bd64614e
PFC		 807 features.cell = true;
808
809 tdesc = ppc_linux_match_description (features);
e6c5bb05
SM		 810
811 /* On 32-bit machines, check for SPE registers.
812 Set the low target's regmap field as appropriately. */
813#ifndef __powerpc64__
814 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
815 tdesc = tdesc_powerpc_e500l;
816
817 if (!ppc_regmap_adjusted)
818 {
819 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
820 ppc_usrregs_info.regmap = ppc_regmap_e500;
821
822 /* If the FPSCR is 64-bit wide, we need to fetch the whole
823 64-bit slot and not just its second word. The PT_FPSCR
824 supplied in a 32-bit GDB compilation doesn't reflect
825 this. */
826 if (register_size (tdesc, 70) == 8)
827 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
828
829 ppc_regmap_adjusted = 1;
830 }
831#endif
bd64614e 832
e6c5bb05 833 current_process ()->tdesc = tdesc;
7273b5fc
PFC		 834
835 for (regset = ppc_regsets; regset->size >= 0; regset++)
836 switch (regset->get_request)
837 {
838 case PTRACE_GETVRREGS:
d078308a 839 regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0;
7273b5fc
PFC		 840 break;
841 case PTRACE_GETVSXREGS:
d078308a 842 regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0;
7273b5fc
PFC		 843 break;
844 case PTRACE_GETEVRREGS:
845 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
846 regset->size = 32 * 4 + 8 + 4;
847 else
848 regset->size = 0;
849 break;
7ca18ed6
EBM		 850 case PTRACE_GETREGSET:
851 switch (regset->nt_type)
852 {
853 case NT_PPC_PPR:
854 regset->size = (features.ppr_dscr ?
855 PPC_LINUX_SIZEOF_PPRREGSET : 0);
856 break;
857 case NT_PPC_DSCR:
858 regset->size = (features.ppr_dscr ?
859 PPC_LINUX_SIZEOF_DSCRREGSET : 0);
860 break;
f2cf6173
EBM		 861 case NT_PPC_TAR:
862 regset->size = (features.isa207 ?
863 PPC_LINUX_SIZEOF_TARREGSET : 0);
864 break;
232bfb86
EBM		 865 case NT_PPC_EBB:
866 regset->size = (features.isa207 ?
867 PPC_LINUX_SIZEOF_EBBREGSET : 0);
868 break;
869 case NT_PPC_PMU:
870 regset->size = (features.isa207 ?
871 PPC_LINUX_SIZEOF_PMUREGSET : 0);
872 break;
7ca18ed6
EBM		 873 default:
874 break;
875 }
876 break;
7273b5fc
PFC		 877 default:
878 break;
879 }
e6c5bb05
SM		 880}
881
a2174ba4
MK		 882/* Implementation of linux_target_ops method "supports_tracepoints". */
883
b04fd3be
MK		 884static int
885ppc_supports_tracepoints (void)
886{
887 return 1;
888}
889
a2174ba4
MK		 890/* Get the thread area address. This is used to recognize which
891 thread is which when tracing with the in-process agent library. We
892 don't read anything from the address, and treat it as opaque; it's
893 the address itself that we assume is unique per-thread. */
894
895static int
896ppc_get_thread_area (int lwpid, CORE_ADDR *addr)
897{
f2907e49 898 struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid));
a2174ba4
MK		 899 struct thread_info *thr = get_lwp_thread (lwp);
900 struct regcache *regcache = get_thread_regcache (thr, 1);
901 ULONGEST tp = 0;
902
903#ifdef __powerpc64__
904 if (register_size (regcache->tdesc, 0) == 8)
905 collect_register_by_name (regcache, "r13", &tp);
906 else
907#endif
908 collect_register_by_name (regcache, "r2", &tp);
909
910 *addr = tp;
911
912 return 0;
913}
914
915#ifdef __powerpc64__
916
917/* Older glibc doesn't provide this. */
918
919#ifndef EF_PPC64_ABI
920#define EF_PPC64_ABI 3
921#endif
922
923/* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
924 inferiors. */
925
926static int
927is_elfv2_inferior (void)
928{
929 /* To be used as fallback if we're unable to determine the right result -
930 assume inferior uses the same ABI as gdbserver. */
931#if _CALL_ELF == 2
932 const int def_res = 1;
933#else
934 const int def_res = 0;
935#endif
936 unsigned long phdr;
937 Elf64_Ehdr ehdr;
938
939 if (!ppc_get_auxv (AT_PHDR, &phdr))
940 return def_res;
941
942 /* Assume ELF header is at the beginning of the page where program headers
943 are located. If it doesn't look like one, bail. */
944
945 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr);
946 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG))
947 return def_res;
948
949 return (ehdr.e_flags & EF_PPC64_ABI) == 2;
950}
951
952#endif
953
954/* Generate a ds-form instruction in BUF and return the number of bytes written
955
956 0 6 11 16 30 32
957 | OPCD | RST | RA | DS |XO| */
958
959__attribute__((unused)) /* Maybe unused due to conditional compilation. */
960static int
961gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo)
962{
963 uint32_t insn;
964
965 gdb_assert ((opcd & ~0x3f) == 0);
966 gdb_assert ((rst & ~0x1f) == 0);
967 gdb_assert ((ra & ~0x1f) == 0);
968 gdb_assert ((xo & ~0x3) == 0);
969
970 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3);
971 *buf = (opcd << 26) | insn;
972 return 1;
973}
974
975/* Followings are frequently used ds-form instructions. */
976
977#define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
978#define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
979#define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
980#define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
981
982/* Generate a d-form instruction in BUF.
983
984 0 6 11 16 32
985 | OPCD | RST | RA | D | */
986
987static int
988gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si)
989{
990 uint32_t insn;
991
992 gdb_assert ((opcd & ~0x3f) == 0);
993 gdb_assert ((rst & ~0x1f) == 0);
994 gdb_assert ((ra & ~0x1f) == 0);
995
996 insn = (rst << 21) | (ra << 16) | (si & 0xffff);
997 *buf = (opcd << 26) | insn;
998 return 1;
999}
1000
1001/* Followings are frequently used d-form instructions. */
1002
1003#define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1004#define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1005#define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1006#define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1007#define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1008#define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1009#define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1010#define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1011#define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1012
1013/* Generate a xfx-form instruction in BUF and return the number of bytes
1014 written.
1015
1016 0 6 11 21 31 32
1017 | OPCD | RST | RI | XO |/| */
1018
1019static int
1020gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo)
1021{
1022 uint32_t insn;
1023 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f);
1024
1025 gdb_assert ((opcd & ~0x3f) == 0);
1026 gdb_assert ((rst & ~0x1f) == 0);
1027 gdb_assert ((xo & ~0x3ff) == 0);
1028
1029 insn = (rst << 21) | (n << 11) | (xo << 1);
1030 *buf = (opcd << 26) | insn;
1031 return 1;
1032}
1033
1034/* Followings are frequently used xfx-form instructions. */
1035
1036#define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1037#define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1038#define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1039#define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1040#define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1041 E & 0xf, 598)
1042#define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1043
1044
1045/* Generate a x-form instruction in BUF and return the number of bytes written.
1046
1047 0 6 11 16 21 31 32
1048 | OPCD | RST | RA | RB | XO |RC| */
1049
1050static int
1051gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc)
1052{
1053 uint32_t insn;
1054
1055 gdb_assert ((opcd & ~0x3f) == 0);
1056 gdb_assert ((rst & ~0x1f) == 0);
1057 gdb_assert ((ra & ~0x1f) == 0);
1058 gdb_assert ((rb & ~0x1f) == 0);
1059 gdb_assert ((xo & ~0x3ff) == 0);
1060 gdb_assert ((rc & ~1) == 0);
1061
1062 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc;
1063 *buf = (opcd << 26) | insn;
1064 return 1;
1065}
1066
1067/* Followings are frequently used x-form instructions. */
1068
1069#define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1070#define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1071#define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1072#define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1073/* Assume bf = cr7. */
1074#define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1075
1076
1077/* Generate a md-form instruction in BUF and return the number of bytes written.
1078
1079 0 6 11 16 21 27 30 31 32
1080 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1081
1082static int
1083gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb,
1084 int xo, int rc)
1085{
1086 uint32_t insn;
1087 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1);
1088 unsigned int sh0_4 = sh & 0x1f;
1089 unsigned int sh5 = (sh >> 5) & 1;
1090
1091 gdb_assert ((opcd & ~0x3f) == 0);
1092 gdb_assert ((rs & ~0x1f) == 0);
1093 gdb_assert ((ra & ~0x1f) == 0);
1094 gdb_assert ((sh & ~0x3f) == 0);
1095 gdb_assert ((mb & ~0x3f) == 0);
1096 gdb_assert ((xo & ~0x7) == 0);
1097 gdb_assert ((rc & ~0x1) == 0);
1098
1099 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5)
1100 | (sh5 << 1) | (xo << 2) | (rc & 1);
1101 *buf = (opcd << 26) | insn;
1102 return 1;
1103}
1104
1105/* The following are frequently used md-form instructions. */
1106
1107#define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1108 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1109#define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1110 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1111
1112/* Generate a i-form instruction in BUF and return the number of bytes written.
1113
1114 0 6 30 31 32
1115 | OPCD | LI |AA|LK| */
1116
1117static int
1118gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk)
1119{
1120 uint32_t insn;
1121
1122 gdb_assert ((opcd & ~0x3f) == 0);
1123
1124 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1);
1125 *buf = (opcd << 26) | insn;
1126 return 1;
1127}
1128
1129/* The following are frequently used i-form instructions. */
1130
1131#define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1132#define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1133
1134/* Generate a b-form instruction in BUF and return the number of bytes written.
1135
1136 0 6 11 16 30 31 32
1137 | OPCD | BO | BI | BD |AA|LK| */
1138
1139static int
1140gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd,
1141 int aa, int lk)
1142{
1143 uint32_t insn;
1144
1145 gdb_assert ((opcd & ~0x3f) == 0);
1146 gdb_assert ((bo & ~0x1f) == 0);
1147 gdb_assert ((bi & ~0x1f) == 0);
1148
1149 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1);
1150 *buf = (opcd << 26) | insn;
1151 return 1;
1152}
1153
1154/* The following are frequently used b-form instructions. */
1155/* Assume bi = cr7. */
1156#define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1157
1158/* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1159 respectively. They are primary used for save/restore GPRs in jump-pad,
1160 not used for bytecode compiling. */
1161
1162#ifdef __powerpc64__
1163#define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1164 GEN_LD (buf, rt, ra, si) : \
1165 GEN_LWZ (buf, rt, ra, si))
1166#define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1167 GEN_STD (buf, rt, ra, si) : \
1168 GEN_STW (buf, rt, ra, si))
1169#else
1170#define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1171#define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1172#endif
1173
1174/* Generate a sequence of instructions to load IMM in the register REG.
1175 Write the instructions in BUF and return the number of bytes written. */
1176
1177static int
1178gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64)
1179{
1180 uint32_t *p = buf;
1181
1182 if ((imm + 32768) < 65536)
1183 {
1184 /* li reg, imm[15:0] */
1185 p += GEN_LI (p, reg, imm);
1186 }
1187 else if ((imm >> 32) == 0)
1188 {
1189 /* lis reg, imm[31:16]
1190 ori reg, reg, imm[15:0]
1191 rldicl reg, reg, 0, 32 */
1192 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff);
1193 if ((imm & 0xffff) != 0)
1194 p += GEN_ORI (p, reg, reg, imm & 0xffff);
1195 /* Clear upper 32-bit if sign-bit is set. */
1196 if (imm & (1u << 31) && is_64)
1197 p += GEN_RLDICL (p, reg, reg, 0, 32);
1198 }
1199 else
1200 {
1201 gdb_assert (is_64);
1202 /* lis reg, <imm[63:48]>
1203 ori reg, reg, <imm[48:32]>
1204 rldicr reg, reg, 32, 31
1205 oris reg, reg, <imm[31:16]>
1206 ori reg, reg, <imm[15:0]> */
1207 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff));
1208 if (((imm >> 32) & 0xffff) != 0)
1209 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff));
1210 p += GEN_RLDICR (p, reg, reg, 32, 31);
1211 if (((imm >> 16) & 0xffff) != 0)
1212 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff));
1213 if ((imm & 0xffff) != 0)
1214 p += GEN_ORI (p, reg, reg, (imm & 0xffff));
1215 }
1216
1217 return p - buf;
1218}
1219
1220/* Generate a sequence for atomically exchange at location LOCK.
1221 This code sequence clobbers r6, r7, r8. LOCK is the location for
1222 the atomic-xchg, OLD_VALUE is expected old value stored in the
1223 location, and R_NEW is a register for the new value. */
1224
1225static int
1226gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new,
1227 int is_64)
1228{
1229 const int r_lock = 6;
1230 const int r_old = 7;
1231 const int r_tmp = 8;
1232 uint32_t *p = buf;
1233
1234 /*
1235 1: lwarx TMP, 0, LOCK
1236 cmpwi TMP, OLD
1237 bne 1b
1238 stwcx. NEW, 0, LOCK
1239 bne 1b */
1240
1241 p += gen_limm (p, r_lock, lock, is_64);
1242 p += gen_limm (p, r_old, old_value, is_64);
1243
1244 p += GEN_LWARX (p, r_tmp, 0, r_lock);
1245 p += GEN_CMPW (p, r_tmp, r_old);
1246 p += GEN_BNE (p, -8);
1247 p += GEN_STWCX (p, r_new, 0, r_lock);
1248 p += GEN_BNE (p, -16);
1249
1250 return p - buf;
1251}
1252
1253/* Generate a sequence of instructions for calling a function
1254 at address of FN. Return the number of bytes are written in BUF. */
1255
1256static int
1257gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd)
1258{
1259 uint32_t *p = buf;
1260
1261 /* Must be called by r12 for caller to calculate TOC address. */
1262 p += gen_limm (p, 12, fn, is_64);
1263 if (is_opd)
1264 {
1265 p += GEN_LOAD (p, 11, 12, 16, is_64);
1266 p += GEN_LOAD (p, 2, 12, 8, is_64);
1267 p += GEN_LOAD (p, 12, 12, 0, is_64);
1268 }
1269 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */
1270 *p++ = 0x4e800421; /* bctrl */
1271
1272 return p - buf;
1273}
1274
1275/* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1276 of instruction. This function is used to adjust pc-relative instructions
1277 when copying. */
1278
1279static void
1280ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
1281{
1282 uint32_t insn, op6;
1283 long rel, newrel;
1284
1285 read_inferior_memory (oldloc, (unsigned char *) &insn, 4);
1286 op6 = PPC_OP6 (insn);
1287
1288 if (op6 == 18 && (insn & 2) == 0)
1289 {
1290 /* branch && AA = 0 */
1291 rel = PPC_LI (insn);
1292 newrel = (oldloc - *to) + rel;
1293
1294 /* Out of range. Cannot relocate instruction. */
1295 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1296 return;
1297
1298 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc);
1299 }
1300 else if (op6 == 16 && (insn & 2) == 0)
1301 {
1302 /* conditional branch && AA = 0 */
1303
1304 /* If the new relocation is too big for even a 26-bit unconditional
1305 branch, there is nothing we can do. Just abort.
1306
1307 Otherwise, if it can be fit in 16-bit conditional branch, just
1308 copy the instruction and relocate the address.
1309
1310 If the it's big for conditional-branch (16-bit), try to invert the
1311 condition and jump with 26-bit branch. For example,
1312
1313 beq .Lgoto
1314 INSN1
1315
1316 =>
1317
1318 bne 1f (+8)
1319 b .Lgoto
1320 1:INSN1
1321
1322 After this transform, we are actually jump from *TO+4 instead of *TO,
1323 so check the relocation again because it will be 1-insn farther then
1324 before if *TO is after OLDLOC.
1325
1326
1327 For BDNZT (or so) is transformed from
1328
1329 bdnzt eq, .Lgoto
1330 INSN1
1331
1332 =>
1333
1334 bdz 1f (+12)
1335 bf eq, 1f (+8)
1336 b .Lgoto
1337 1:INSN1
1338
1339 See also "BO field encodings". */
1340
1341 rel = PPC_BD (insn);
1342 newrel = (oldloc - *to) + rel;
1343
1344 if (newrel < (1 << 15) && newrel >= -(1 << 15))
1345 insn = (insn & ~0xfffc) | (newrel & 0xfffc);
1346 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10)
1347 {
1348 newrel -= 4;
1349
1350 /* Out of range. Cannot relocate instruction. */
1351 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1352 return;
1353
1354 if ((PPC_BO (insn) & 0x14) == 0x4)
1355 insn ^= (1 << 24);
1356 else if ((PPC_BO (insn) & 0x14) == 0x10)
1357 insn ^= (1 << 22);
1358
1359 /* Jump over the unconditional branch. */
1360 insn = (insn & ~0xfffc) | 0x8;
1361 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1362 *to += 4;
1363
1364 /* Build a unconditional branch and copy LK bit. */
1365 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1366 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1367 *to += 4;
1368
1369 return;
1370 }
1371 else if ((PPC_BO (insn) & 0x14) == 0)
1372 {
1373 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12;
1374 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8;
1375
1376 newrel -= 8;
1377
1378 /* Out of range. Cannot relocate instruction. */
1379 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1380 return;
1381
1382 /* Copy BI field. */
1383 bf_insn |= (insn & 0x1f0000);
1384
1385 /* Invert condition. */
1386 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
1387 bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
1388
1389 write_inferior_memory (*to, (unsigned char *) &bdnz_insn, 4);
1390 *to += 4;
1391 write_inferior_memory (*to, (unsigned char *) &bf_insn, 4);
1392 *to += 4;
1393
1394 /* Build a unconditional branch and copy LK bit. */
1395 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1396 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1397 *to += 4;
1398
1399 return;
1400 }
1401 else /* (BO & 0x14) == 0x14, branch always. */
1402 {
1403 /* Out of range. Cannot relocate instruction. */
1404 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1405 return;
1406
1407 /* Build a unconditional branch and copy LK bit. */
1408 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1409 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1410 *to += 4;
1411
1412 return;
1413 }
1414 }
1415
1416 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1417 *to += 4;
1418}
1419
1420/* Implement install_fast_tracepoint_jump_pad of target_ops.
1421 See target.h for details. */
1422
1423static int
1424ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1425 CORE_ADDR collector,
1426 CORE_ADDR lockaddr,
1427 ULONGEST orig_size,
1428 CORE_ADDR *jump_entry,
1429 CORE_ADDR *trampoline,
1430 ULONGEST *trampoline_size,
1431 unsigned char *jjump_pad_insn,
1432 ULONGEST *jjump_pad_insn_size,
1433 CORE_ADDR *adjusted_insn_addr,
1434 CORE_ADDR *adjusted_insn_addr_end,
1435 char *err)
1436{
1437 uint32_t buf[256];
1438 uint32_t *p = buf;
1439 int j, offset;
1440 CORE_ADDR buildaddr = *jump_entry;
1441 const CORE_ADDR entryaddr = *jump_entry;
1442 int rsz, min_frame, frame_size, tp_reg;
1443#ifdef __powerpc64__
1444 struct regcache *regcache = get_thread_regcache (current_thread, 0);
1445 int is_64 = register_size (regcache->tdesc, 0) == 8;
1446 int is_opd = is_64 && !is_elfv2_inferior ();
1447#else
1448 int is_64 = 0, is_opd = 0;
1449#endif
1450
1451#ifdef __powerpc64__
1452 if (is_64)
1453 {
1454 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1455 rsz = 8;
1456 min_frame = 112;
1457 frame_size = (40 * rsz) + min_frame;
1458 tp_reg = 13;
1459 }
1460 else
1461 {
1462#endif
1463 rsz = 4;
1464 min_frame = 16;
1465 frame_size = (40 * rsz) + min_frame;
1466 tp_reg = 2;
1467#ifdef __powerpc64__
1468 }
1469#endif
1470
1471 /* Stack frame layout for this jump pad,
1472
1473 High thread_area (r13/r2) |
1474 tpoint - collecting_t obj
1475 PC/<tpaddr> | +36
1476 CTR | +35
1477 LR | +34
1478 XER | +33
1479 CR | +32
1480 R31 |
1481 R29 |
1482 ... |
1483 R1 | +1
1484 R0 - collected registers
1485 ... |
1486 ... |
1487 Low Back-chain -
1488
1489
1490 The code flow of this jump pad,
1491
1492 1. Adjust SP
1493 2. Save GPR and SPR
1494 3. Prepare argument
1495 4. Call gdb_collector
1496 5. Restore GPR and SPR
1497 6. Restore SP
1498 7. Build a jump for back to the program
1499 8. Copy/relocate original instruction
1500 9. Build a jump for replacing orignal instruction. */
1501
1502 /* Adjust stack pointer. */
1503 if (is_64)
1504 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */
1505 else
1506 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */
1507
1508 /* Store GPRs. Save R1 later, because it had just been modified, but
1509 we want the original value. */
1510 for (j = 2; j < 32; j++)
1511 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64);
1512 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64);
1513 /* Set r0 to the original value of r1 before adjusting stack frame,
1514 and then save it. */
1515 p += GEN_ADDI (p, 0, 1, frame_size);
1516 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64);
1517
1518 /* Save CR, XER, LR, and CTR. */
1519 p += GEN_MFCR (p, 3); /* mfcr r3 */
1520 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */
1521 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */
1522 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */
1523 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */
1524 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */
1525 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */
1526 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */
1527
1528 /* Save PC<tpaddr> */
1529 p += gen_limm (p, 3, tpaddr, is_64);
1530 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64);
1531
1532
1533 /* Setup arguments to collector. */
1534 /* Set r4 to collected registers. */
1535 p += GEN_ADDI (p, 4, 1, min_frame);
1536 /* Set r3 to TPOINT. */
1537 p += gen_limm (p, 3, tpoint, is_64);
1538
1539 /* Prepare collecting_t object for lock. */
1540 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64);
1541 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64);
1542 /* Set R5 to collecting object. */
1543 p += GEN_ADDI (p, 5, 1, 37 * rsz);
1544
1545 p += GEN_LWSYNC (p);
1546 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64);
1547 p += GEN_LWSYNC (p);
1548
1549 /* Call to collector. */
1550 p += gen_call (p, collector, is_64, is_opd);
1551
1552 /* Simply write 0 to release the lock. */
1553 p += gen_limm (p, 3, lockaddr, is_64);
1554 p += gen_limm (p, 4, 0, is_64);
1555 p += GEN_LWSYNC (p);
1556 p += GEN_STORE (p, 4, 3, 0, is_64);
1557
1558 /* Restore stack and registers. */
1559 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */
1560 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */
1561 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */
1562 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */
1563 p += GEN_MTCR (p, 3); /* mtcr r3 */
1564 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */
1565 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */
1566 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */
1567
1568 /* Restore GPRs. */
1569 for (j = 2; j < 32; j++)
1570 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64);
1571 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64);
1572 /* Restore SP. */
1573 p += GEN_ADDI (p, 1, 1, frame_size);
1574
1575 /* Flush instructions to inferior memory. */
1576 write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
1577
1578 /* Now, insert the original instruction to execute in the jump pad. */
1579 *adjusted_insn_addr = buildaddr + (p - buf) * 4;
1580 *adjusted_insn_addr_end = *adjusted_insn_addr;
1581 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr);
1582
1583 /* Verify the relocation size. If should be 4 for normal copy,
1584 8 or 12 for some conditional branch. */
1585 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0)
1586 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12))
1587 {
1588 sprintf (err, "E.Unexpected instruction length = %d"
1589 "when relocate instruction.",
1590 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr));
1591 return 1;
1592 }
1593
1594 buildaddr = *adjusted_insn_addr_end;
1595 p = buf;
1596 /* Finally, write a jump back to the program. */
1597 offset = (tpaddr + 4) - buildaddr;
1598 if (offset >= (1 << 25) || offset < -(1 << 25))
1599 {
1600 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1601 "(offset 0x%x > 26-bit).", offset);
1602 return 1;
1603 }
1604 /* b <tpaddr+4> */
1605 p += GEN_B (p, offset);
1606 write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
1607 *jump_entry = buildaddr + (p - buf) * 4;
1608
1609 /* The jump pad is now built. Wire in a jump to our jump pad. This
1610 is always done last (by our caller actually), so that we can
1611 install fast tracepoints with threads running. This relies on
1612 the agent's atomic write support. */
1613 offset = entryaddr - tpaddr;
1614 if (offset >= (1 << 25) || offset < -(1 << 25))
1615 {
1616 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1617 "(offset 0x%x > 26-bit).", offset);
1618 return 1;
1619 }
1620 /* b <jentry> */
1621 GEN_B ((uint32_t *) jjump_pad_insn, offset);
1622 *jjump_pad_insn_size = 4;
1623
1624 return 0;
1625}
1626
1627/* Returns the minimum instruction length for installing a tracepoint. */
1628
1629static int
1630ppc_get_min_fast_tracepoint_insn_len (void)
1631{
1632 return 4;
1633}
1634
14e2b6d9
MK		 1635/* Emits a given buffer into the target at current_insn_ptr. Length
1636 is in units of 32-bit words. */
1637
1638static void
1639emit_insns (uint32_t *buf, int n)
1640{
1641 n = n * sizeof (uint32_t);
1642 write_inferior_memory (current_insn_ptr, (unsigned char *) buf, n);
1643 current_insn_ptr += n;
1644}
1645
1646#define __EMIT_ASM(NAME, INSNS) \
1647 do \
1648 { \
1649 extern uint32_t start_bcax_ ## NAME []; \
1650 extern uint32_t end_bcax_ ## NAME []; \
1651 emit_insns (start_bcax_ ## NAME, \
1652 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1653 __asm__ (".section .text.__ppcbcax\n\t" \
1654 "start_bcax_" #NAME ":\n\t" \
1655 INSNS "\n\t" \
1656 "end_bcax_" #NAME ":\n\t" \
1657 ".previous\n\t"); \
1658 } while (0)
1659
1660#define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1661#define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1662
1663/*
1664
1665 Bytecode execution stack frame - 32-bit
1666
1667 | LR save area (SP + 4)
1668 SP' -> +- Back chain (SP + 0)
1669 | Save r31 for access saved arguments
1670 | Save r30 for bytecode stack pointer
1671 | Save r4 for incoming argument *value
1672 | Save r3 for incoming argument regs
1673 r30 -> +- Bytecode execution stack
1674 |
1675 | 64-byte (8 doublewords) at initial.
1676 | Expand stack as needed.
1677 |
1678 +-
1679 | Some padding for minimum stack frame and 16-byte alignment.
1680 | 16 bytes.
1681 SP +- Back-chain (SP')
1682
1683 initial frame size
1684 = 16 + (4 * 4) + 64
1685 = 96
1686
1687 r30 is the stack-pointer for bytecode machine.
1688 It should point to next-empty, so we can use LDU for pop.
1689 r3 is used for cache of the high part of TOP value.
1690 It was the first argument, pointer to regs.
1691 r4 is used for cache of the low part of TOP value.
1692 It was the second argument, pointer to the result.
1693 We should set *result = TOP after leaving this function.
1694
1695 Note:
1696 * To restore stack at epilogue
1697 => sp = r31
1698 * To check stack is big enough for bytecode execution.
1699 => r30 - 8 > SP + 8
1700 * To return execution result.
1701 => 0(r4) = TOP
1702
1703 */
1704
1705/* Regardless of endian, register 3 is always high part, 4 is low part.
1706 These defines are used when the register pair is stored/loaded.
1707 Likewise, to simplify code, have a similiar define for 5:6. */
1708
1709#if __BYTE_ORDER == __LITTLE_ENDIAN
1710#define TOP_FIRST "4"
1711#define TOP_SECOND "3"
1712#define TMP_FIRST "6"
1713#define TMP_SECOND "5"
1714#else
1715#define TOP_FIRST "3"
1716#define TOP_SECOND "4"
1717#define TMP_FIRST "5"
1718#define TMP_SECOND "6"
1719#endif
1720
1721/* Emit prologue in inferior memory. See above comments. */
1722
1723static void
1724ppc_emit_prologue (void)
1725{
1726 EMIT_ASM (/* Save return address. */
1727 "mflr 0 \n"
1728 "stw 0, 4(1) \n"
1729 /* Adjust SP. 96 is the initial frame size. */
1730 "stwu 1, -96(1) \n"
1731 /* Save r30 and incoming arguments. */
1732 "stw 31, 96-4(1) \n"
1733 "stw 30, 96-8(1) \n"
1734 "stw 4, 96-12(1) \n"
1735 "stw 3, 96-16(1) \n"
1736 /* Point r31 to original r1 for access arguments. */
1737 "addi 31, 1, 96 \n"
1738 /* Set r30 to pointing stack-top. */
1739 "addi 30, 1, 64 \n"
1740 /* Initial r3/TOP to 0. */
1741 "li 3, 0 \n"
1742 "li 4, 0 \n");
1743}
1744
1745/* Emit epilogue in inferior memory. See above comments. */
1746
1747static void
1748ppc_emit_epilogue (void)
1749{
1750 EMIT_ASM (/* *result = TOP */
1751 "lwz 5, -12(31) \n"
1752 "stw " TOP_FIRST ", 0(5) \n"
1753 "stw " TOP_SECOND ", 4(5) \n"
1754 /* Restore registers. */
1755 "lwz 31, -4(31) \n"
1756 "lwz 30, -8(31) \n"
1757 /* Restore SP. */
1758 "lwz 1, 0(1) \n"
1759 /* Restore LR. */
1760 "lwz 0, 4(1) \n"
1761 /* Return 0 for no-error. */
1762 "li 3, 0 \n"
1763 "mtlr 0 \n"
1764 "blr \n");
1765}
1766
1767/* TOP = stack[--sp] + TOP */
1768
1769static void
1770ppc_emit_add (void)
1771{
1772 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1773 "lwz " TMP_SECOND ", 4(30)\n"
1774 "addc 4, 6, 4 \n"
1775 "adde 3, 5, 3 \n");
1776}
1777
1778/* TOP = stack[--sp] - TOP */
1779
1780static void
1781ppc_emit_sub (void)
1782{
1783 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1784 "lwz " TMP_SECOND ", 4(30) \n"
1785 "subfc 4, 4, 6 \n"
1786 "subfe 3, 3, 5 \n");
1787}
1788
1789/* TOP = stack[--sp] * TOP */
1790
1791static void
1792ppc_emit_mul (void)
1793{
1794 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1795 "lwz " TMP_SECOND ", 4(30) \n"
1796 "mulhwu 7, 6, 4 \n"
1797 "mullw 3, 6, 3 \n"
1798 "mullw 5, 4, 5 \n"
1799 "mullw 4, 6, 4 \n"
1800 "add 3, 5, 3 \n"
1801 "add 3, 7, 3 \n");
1802}
1803
1804/* TOP = stack[--sp] << TOP */
1805
1806static void
1807ppc_emit_lsh (void)
1808{
1809 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1810 "lwz " TMP_SECOND ", 4(30) \n"
1811 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1812 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1813 "slw 5, 5, 4\n" /* Shift high part left */
1814 "slw 4, 6, 4\n" /* Shift low part left */
1815 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1816 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1817 "or 3, 5, 3\n"
1818 "or 3, 7, 3\n"); /* Assemble high part */
1819}
1820
1821/* Top = stack[--sp] >> TOP
1822 (Arithmetic shift right) */
1823
1824static void
1825ppc_emit_rsh_signed (void)
1826{
1827 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1828 "lwz " TMP_SECOND ", 4(30) \n"
1829 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1830 "sraw 3, 5, 4\n" /* Shift high part right */
1831 "cmpwi 7, 1\n"
1832 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1833 "sraw 4, 5, 7\n" /* Shift high to low */
1834 "b 2f\n"
1835 "1:\n"
1836 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1837 "srw 4, 6, 4\n" /* Shift low part right */
1838 "slw 5, 5, 7\n" /* Shift high to low */
1839 "or 4, 4, 5\n" /* Assemble low part */
1840 "2:\n");
1841}
1842
1843/* Top = stack[--sp] >> TOP
1844 (Logical shift right) */
1845
1846static void
1847ppc_emit_rsh_unsigned (void)
1848{
1849 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1850 "lwz " TMP_SECOND ", 4(30) \n"
1851 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1852 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1853 "srw 6, 6, 4\n" /* Shift low part right */
1854 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1855 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1856 "or 6, 6, 3\n"
1857 "srw 3, 5, 4\n" /* Shift high part right */
1858 "or 4, 6, 7\n"); /* Assemble low part */
1859}
1860
1861/* Emit code for signed-extension specified by ARG. */
1862
1863static void
1864ppc_emit_ext (int arg)
1865{
1866 switch (arg)
1867 {
1868 case 8:
1869 EMIT_ASM ("extsb 4, 4\n"
1870 "srawi 3, 4, 31");
1871 break;
1872 case 16:
1873 EMIT_ASM ("extsh 4, 4\n"
1874 "srawi 3, 4, 31");
1875 break;
1876 case 32:
1877 EMIT_ASM ("srawi 3, 4, 31");
1878 break;
1879 default:
1880 emit_error = 1;
1881 }
1882}
1883
1884/* Emit code for zero-extension specified by ARG. */
1885
1886static void
1887ppc_emit_zero_ext (int arg)
1888{
1889 switch (arg)
1890 {
1891 case 8:
1892 EMIT_ASM ("clrlwi 4,4,24\n"
1893 "li 3, 0\n");
1894 break;
1895 case 16:
1896 EMIT_ASM ("clrlwi 4,4,16\n"
1897 "li 3, 0\n");
1898 break;
1899 case 32:
1900 EMIT_ASM ("li 3, 0");
1901 break;
1902 default:
1903 emit_error = 1;
1904 }
1905}
1906
1907/* TOP = !TOP
1908 i.e., TOP = (TOP == 0) ? 1 : 0; */
1909
1910static void
1911ppc_emit_log_not (void)
1912{
1913 EMIT_ASM ("or 4, 3, 4 \n"
1914 "cntlzw 4, 4 \n"
1915 "srwi 4, 4, 5 \n"
1916 "li 3, 0 \n");
1917}
1918
1919/* TOP = stack[--sp] & TOP */
1920
1921static void
1922ppc_emit_bit_and (void)
1923{
1924 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1925 "lwz " TMP_SECOND ", 4(30) \n"
1926 "and 4, 6, 4 \n"
1927 "and 3, 5, 3 \n");
1928}
1929
1930/* TOP = stack[--sp] | TOP */
1931
1932static void
1933ppc_emit_bit_or (void)
1934{
1935 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1936 "lwz " TMP_SECOND ", 4(30) \n"
1937 "or 4, 6, 4 \n"
1938 "or 3, 5, 3 \n");
1939}
1940
1941/* TOP = stack[--sp] ^ TOP */
1942
1943static void
1944ppc_emit_bit_xor (void)
1945{
1946 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1947 "lwz " TMP_SECOND ", 4(30) \n"
1948 "xor 4, 6, 4 \n"
1949 "xor 3, 5, 3 \n");
1950}
1951
1952/* TOP = ~TOP
1953 i.e., TOP = ~(TOP | TOP) */
1954
1955static void
1956ppc_emit_bit_not (void)
1957{
1958 EMIT_ASM ("nor 3, 3, 3 \n"
1959 "nor 4, 4, 4 \n");
1960}
1961
1962/* TOP = stack[--sp] == TOP */
1963
1964static void
1965ppc_emit_equal (void)
1966{
1967 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1968 "lwz " TMP_SECOND ", 4(30) \n"
1969 "xor 4, 6, 4 \n"
1970 "xor 3, 5, 3 \n"
1971 "or 4, 3, 4 \n"
1972 "cntlzw 4, 4 \n"
1973 "srwi 4, 4, 5 \n"
1974 "li 3, 0 \n");
1975}
1976
1977/* TOP = stack[--sp] < TOP
1978 (Signed comparison) */
1979
1980static void
1981ppc_emit_less_signed (void)
1982{
1983 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1984 "lwz " TMP_SECOND ", 4(30) \n"
1985 "cmplw 6, 6, 4 \n"
1986 "cmpw 7, 5, 3 \n"
1987 /* CR6 bit 0 = low less and high equal */
1988 "crand 6*4+0, 6*4+0, 7*4+2\n"
1989 /* CR7 bit 0 = (low less and high equal) or high less */
1990 "cror 7*4+0, 7*4+0, 6*4+0\n"
1991 "mfcr 4 \n"
1992 "rlwinm 4, 4, 29, 31, 31 \n"
1993 "li 3, 0 \n");
1994}
1995
1996/* TOP = stack[--sp] < TOP
1997 (Unsigned comparison) */
1998
1999static void
2000ppc_emit_less_unsigned (void)
2001{
2002 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2003 "lwz " TMP_SECOND ", 4(30) \n"
2004 "cmplw 6, 6, 4 \n"
2005 "cmplw 7, 5, 3 \n"
2006 /* CR6 bit 0 = low less and high equal */
2007 "crand 6*4+0, 6*4+0, 7*4+2\n"
2008 /* CR7 bit 0 = (low less and high equal) or high less */
2009 "cror 7*4+0, 7*4+0, 6*4+0\n"
2010 "mfcr 4 \n"
2011 "rlwinm 4, 4, 29, 31, 31 \n"
2012 "li 3, 0 \n");
2013}
2014
2015/* Access the memory address in TOP in size of SIZE.
2016 Zero-extend the read value. */
2017
2018static void
2019ppc_emit_ref (int size)
2020{
2021 switch (size)
2022 {
2023 case 1:
2024 EMIT_ASM ("lbz 4, 0(4)\n"
2025 "li 3, 0");
2026 break;
2027 case 2:
2028 EMIT_ASM ("lhz 4, 0(4)\n"
2029 "li 3, 0");
2030 break;
2031 case 4:
2032 EMIT_ASM ("lwz 4, 0(4)\n"
2033 "li 3, 0");
2034 break;
2035 case 8:
2036 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2037 EMIT_ASM ("lwz 3, 4(4)\n"
2038 "lwz 4, 0(4)");
2039 else
2040 EMIT_ASM ("lwz 3, 0(4)\n"
2041 "lwz 4, 4(4)");
2042 break;
2043 }
2044}
2045
2046/* TOP = NUM */
2047
2048static void
2049ppc_emit_const (LONGEST num)
2050{
2051 uint32_t buf[10];
2052 uint32_t *p = buf;
2053
2054 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0);
2055 p += gen_limm (p, 4, num & 0xffffffff, 0);
2056
2057 emit_insns (buf, p - buf);
2058 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2059}
2060
2061/* Set TOP to the value of register REG by calling get_raw_reg function
2062 with two argument, collected buffer and register number. */
2063
2064static void
2065ppc_emit_reg (int reg)
2066{
2067 uint32_t buf[13];
2068 uint32_t *p = buf;
2069
2070 /* fctx->regs is passed in r3 and then saved in -16(31). */
2071 p += GEN_LWZ (p, 3, 31, -16);
2072 p += GEN_LI (p, 4, reg); /* li r4, reg */
2073 p += gen_call (p, get_raw_reg_func_addr (), 0, 0);
2074
2075 emit_insns (buf, p - buf);
2076 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2077
2078 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2079 {
2080 EMIT_ASM ("mr 5, 4\n"
2081 "mr 4, 3\n"
2082 "mr 3, 5\n");
2083 }
2084}
2085
2086/* TOP = stack[--sp] */
2087
2088static void
2089ppc_emit_pop (void)
2090{
2091 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n"
2092 "lwz " TOP_SECOND ", 4(30) \n");
2093}
2094
2095/* stack[sp++] = TOP
2096
2097 Because we may use up bytecode stack, expand 8 doublewords more
2098 if needed. */
2099
2100static void
2101ppc_emit_stack_flush (void)
2102{
2103 /* Make sure bytecode stack is big enough before push.
2104 Otherwise, expand 64-byte more. */
2105
2106 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n"
2107 " stw " TOP_SECOND ", 4(30)\n"
2108 " addi 5, 30, -(8 + 8) \n"
2109 " cmpw 7, 5, 1 \n"
2110 " bgt 7, 1f \n"
2111 " stwu 31, -64(1) \n"
2112 "1:addi 30, 30, -8 \n");
2113}
2114
2115/* Swap TOP and stack[sp-1] */
2116
2117static void
2118ppc_emit_swap (void)
2119{
2120 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n"
2121 "lwz " TMP_SECOND ", 12(30) \n"
2122 "stw " TOP_FIRST ", 8(30) \n"
2123 "stw " TOP_SECOND ", 12(30) \n"
2124 "mr 3, 5 \n"
2125 "mr 4, 6 \n");
2126}
2127
2128/* Discard N elements in the stack. Also used for ppc64. */
2129
2130static void
2131ppc_emit_stack_adjust (int n)
2132{
2133 uint32_t buf[6];
2134 uint32_t *p = buf;
2135
2136 n = n << 3;
2137 if ((n >> 15) != 0)
2138 {
2139 emit_error = 1;
2140 return;
2141 }
2142
2143 p += GEN_ADDI (p, 30, 30, n);
2144
2145 emit_insns (buf, p - buf);
2146 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2147}
2148
2149/* Call function FN. */
2150
2151static void
2152ppc_emit_call (CORE_ADDR fn)
2153{
2154 uint32_t buf[11];
2155 uint32_t *p = buf;
2156
2157 p += gen_call (p, fn, 0, 0);
2158
2159 emit_insns (buf, p - buf);
2160 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2161}
2162
2163/* FN's prototype is `LONGEST(*fn)(int)'.
2164 TOP = fn (arg1)
2165 */
2166
2167static void
2168ppc_emit_int_call_1 (CORE_ADDR fn, int arg1)
2169{
2170 uint32_t buf[15];
2171 uint32_t *p = buf;
2172
2173 /* Setup argument. arg1 is a 16-bit value. */
2174 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2175 p += gen_call (p, fn, 0, 0);
2176
2177 emit_insns (buf, p - buf);
2178 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2179
2180 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2181 {
2182 EMIT_ASM ("mr 5, 4\n"
2183 "mr 4, 3\n"
2184 "mr 3, 5\n");
2185 }
2186}
2187
2188/* FN's prototype is `void(*fn)(int,LONGEST)'.
2189 fn (arg1, TOP)
2190
2191 TOP should be preserved/restored before/after the call. */
2192
2193static void
2194ppc_emit_void_call_2 (CORE_ADDR fn, int arg1)
2195{
2196 uint32_t buf[21];
2197 uint32_t *p = buf;
2198
2199 /* Save TOP. 0(30) is next-empty. */
2200 p += GEN_STW (p, 3, 30, 0);
2201 p += GEN_STW (p, 4, 30, 4);
2202
2203 /* Setup argument. arg1 is a 16-bit value. */
2204 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2205 {
2206 p += GEN_MR (p, 5, 4);
2207 p += GEN_MR (p, 6, 3);
2208 }
2209 else
2210 {
2211 p += GEN_MR (p, 5, 3);
2212 p += GEN_MR (p, 6, 4);
2213 }
2214 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2215 p += gen_call (p, fn, 0, 0);
2216
2217 /* Restore TOP */
2218 p += GEN_LWZ (p, 3, 30, 0);
2219 p += GEN_LWZ (p, 4, 30, 4);
2220
2221 emit_insns (buf, p - buf);
2222 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2223}
2224
2225/* Note in the following goto ops:
2226
2227 When emitting goto, the target address is later relocated by
2228 write_goto_address. OFFSET_P is the offset of the branch instruction
2229 in the code sequence, and SIZE_P is how to relocate the instruction,
2230 recognized by ppc_write_goto_address. In current implementation,
2231 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2232 */
2233
2234/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2235
2236static void
2237ppc_emit_if_goto (int *offset_p, int *size_p)
2238{
2239 EMIT_ASM ("or. 3, 3, 4 \n"
2240 "lwzu " TOP_FIRST ", 8(30) \n"
2241 "lwz " TOP_SECOND ", 4(30) \n"
2242 "1:bne 0, 1b \n");
2243
2244 if (offset_p)
2245 *offset_p = 12;
2246 if (size_p)
2247 *size_p = 14;
2248}
2249
2250/* Unconditional goto. Also used for ppc64. */
2251
2252static void
2253ppc_emit_goto (int *offset_p, int *size_p)
2254{
2255 EMIT_ASM ("1:b 1b");
2256
2257 if (offset_p)
2258 *offset_p = 0;
2259 if (size_p)
2260 *size_p = 24;
2261}
2262
2263/* Goto if stack[--sp] == TOP */
2264
2265static void
2266ppc_emit_eq_goto (int *offset_p, int *size_p)
2267{
2268 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2269 "lwz " TMP_SECOND ", 4(30) \n"
2270 "xor 4, 6, 4 \n"
2271 "xor 3, 5, 3 \n"
2272 "or. 3, 3, 4 \n"
2273 "lwzu " TOP_FIRST ", 8(30) \n"
2274 "lwz " TOP_SECOND ", 4(30) \n"
2275 "1:beq 0, 1b \n");
2276
2277 if (offset_p)
2278 *offset_p = 28;
2279 if (size_p)
2280 *size_p = 14;
2281}
2282
2283/* Goto if stack[--sp] != TOP */
2284
2285static void
2286ppc_emit_ne_goto (int *offset_p, int *size_p)
2287{
2288 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2289 "lwz " TMP_SECOND ", 4(30) \n"
2290 "xor 4, 6, 4 \n"
2291 "xor 3, 5, 3 \n"
2292 "or. 3, 3, 4 \n"
2293 "lwzu " TOP_FIRST ", 8(30) \n"
2294 "lwz " TOP_SECOND ", 4(30) \n"
2295 "1:bne 0, 1b \n");
2296
2297 if (offset_p)
2298 *offset_p = 28;
2299 if (size_p)
2300 *size_p = 14;
2301}
2302
2303/* Goto if stack[--sp] < TOP */
2304
2305static void
2306ppc_emit_lt_goto (int *offset_p, int *size_p)
2307{
2308 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2309 "lwz " TMP_SECOND ", 4(30) \n"
2310 "cmplw 6, 6, 4 \n"
2311 "cmpw 7, 5, 3 \n"
2312 /* CR6 bit 0 = low less and high equal */
2313 "crand 6*4+0, 6*4+0, 7*4+2\n"
2314 /* CR7 bit 0 = (low less and high equal) or high less */
2315 "cror 7*4+0, 7*4+0, 6*4+0\n"
2316 "lwzu " TOP_FIRST ", 8(30) \n"
2317 "lwz " TOP_SECOND ", 4(30)\n"
2318 "1:blt 7, 1b \n");
2319
2320 if (offset_p)
2321 *offset_p = 32;
2322 if (size_p)
2323 *size_p = 14;
2324}
2325
2326/* Goto if stack[--sp] <= TOP */
2327
2328static void
2329ppc_emit_le_goto (int *offset_p, int *size_p)
2330{
2331 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2332 "lwz " TMP_SECOND ", 4(30) \n"
2333 "cmplw 6, 6, 4 \n"
2334 "cmpw 7, 5, 3 \n"
2335 /* CR6 bit 0 = low less/equal and high equal */
2336 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2337 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2338 "cror 7*4+0, 7*4+0, 6*4+0\n"
2339 "lwzu " TOP_FIRST ", 8(30) \n"
2340 "lwz " TOP_SECOND ", 4(30)\n"
2341 "1:blt 7, 1b \n");
2342
2343 if (offset_p)
2344 *offset_p = 32;
2345 if (size_p)
2346 *size_p = 14;
2347}
2348
2349/* Goto if stack[--sp] > TOP */
2350
2351static void
2352ppc_emit_gt_goto (int *offset_p, int *size_p)
2353{
2354 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2355 "lwz " TMP_SECOND ", 4(30) \n"
2356 "cmplw 6, 6, 4 \n"
2357 "cmpw 7, 5, 3 \n"
2358 /* CR6 bit 0 = low greater and high equal */
2359 "crand 6*4+0, 6*4+1, 7*4+2\n"
2360 /* CR7 bit 0 = (low greater and high equal) or high greater */
2361 "cror 7*4+0, 7*4+1, 6*4+0\n"
2362 "lwzu " TOP_FIRST ", 8(30) \n"
2363 "lwz " TOP_SECOND ", 4(30)\n"
2364 "1:blt 7, 1b \n");
2365
2366 if (offset_p)
2367 *offset_p = 32;
2368 if (size_p)
2369 *size_p = 14;
2370}
2371
2372/* Goto if stack[--sp] >= TOP */
2373
2374static void
2375ppc_emit_ge_goto (int *offset_p, int *size_p)
2376{
2377 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2378 "lwz " TMP_SECOND ", 4(30) \n"
2379 "cmplw 6, 6, 4 \n"
2380 "cmpw 7, 5, 3 \n"
2381 /* CR6 bit 0 = low ge and high equal */
2382 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2383 /* CR7 bit 0 = (low ge and high equal) or high greater */
2384 "cror 7*4+0, 7*4+1, 6*4+0\n"
2385 "lwzu " TOP_FIRST ", 8(30)\n"
2386 "lwz " TOP_SECOND ", 4(30)\n"
2387 "1:blt 7, 1b \n");
2388
2389 if (offset_p)
2390 *offset_p = 32;
2391 if (size_p)
2392 *size_p = 14;
2393}
2394
2395/* Relocate previous emitted branch instruction. FROM is the address
2396 of the branch instruction, TO is the goto target address, and SIZE
2397 if the value we set by *SIZE_P before. Currently, it is either
2398 24 or 14 of branch and conditional-branch instruction.
2399 Also used for ppc64. */
2400
2401static void
2402ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2403{
2404 long rel = to - from;
2405 uint32_t insn;
2406 int opcd;
2407
2408 read_inferior_memory (from, (unsigned char *) &insn, 4);
2409 opcd = (insn >> 26) & 0x3f;
2410
2411 switch (size)
2412 {
2413 case 14:
2414 if (opcd != 16
2415 || (rel >= (1 << 15) || rel < -(1 << 15)))
2416 emit_error = 1;
2417 insn = (insn & ~0xfffc) | (rel & 0xfffc);
2418 break;
2419 case 24:
2420 if (opcd != 18
2421 || (rel >= (1 << 25) || rel < -(1 << 25)))
2422 emit_error = 1;
2423 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc);
2424 break;
2425 default:
2426 emit_error = 1;
2427 }
2428
2429 if (!emit_error)
2430 write_inferior_memory (from, (unsigned char *) &insn, 4);
2431}
2432
2433/* Table of emit ops for 32-bit. */
2434
2435static struct emit_ops ppc_emit_ops_impl =
2436{
2437 ppc_emit_prologue,
2438 ppc_emit_epilogue,
2439 ppc_emit_add,
2440 ppc_emit_sub,
2441 ppc_emit_mul,
2442 ppc_emit_lsh,
2443 ppc_emit_rsh_signed,
2444 ppc_emit_rsh_unsigned,
2445 ppc_emit_ext,
2446 ppc_emit_log_not,
2447 ppc_emit_bit_and,
2448 ppc_emit_bit_or,
2449 ppc_emit_bit_xor,
2450 ppc_emit_bit_not,
2451 ppc_emit_equal,
2452 ppc_emit_less_signed,
2453 ppc_emit_less_unsigned,
2454 ppc_emit_ref,
2455 ppc_emit_if_goto,
2456 ppc_emit_goto,
2457 ppc_write_goto_address,
2458 ppc_emit_const,
2459 ppc_emit_call,
2460 ppc_emit_reg,
2461 ppc_emit_pop,
2462 ppc_emit_stack_flush,
2463 ppc_emit_zero_ext,
2464 ppc_emit_swap,
2465 ppc_emit_stack_adjust,
2466 ppc_emit_int_call_1,
2467 ppc_emit_void_call_2,
2468 ppc_emit_eq_goto,
2469 ppc_emit_ne_goto,
2470 ppc_emit_lt_goto,
2471 ppc_emit_le_goto,
2472 ppc_emit_gt_goto,
2473 ppc_emit_ge_goto
2474};
2475
2476#ifdef __powerpc64__
2477
2478/*
2479
2480 Bytecode execution stack frame - 64-bit
2481
2482 | LR save area (SP + 16)
2483 | CR save area (SP + 8)
2484 SP' -> +- Back chain (SP + 0)
2485 | Save r31 for access saved arguments
2486 | Save r30 for bytecode stack pointer
2487 | Save r4 for incoming argument *value
2488 | Save r3 for incoming argument regs
2489 r30 -> +- Bytecode execution stack
2490 |
2491 | 64-byte (8 doublewords) at initial.
2492 | Expand stack as needed.
2493 |
2494 +-
2495 | Some padding for minimum stack frame.
2496 | 112 for ELFv1.
2497 SP +- Back-chain (SP')
2498
2499 initial frame size
2500 = 112 + (4 * 8) + 64
2501 = 208
2502
2503 r30 is the stack-pointer for bytecode machine.
2504 It should point to next-empty, so we can use LDU for pop.
2505 r3 is used for cache of TOP value.
2506 It was the first argument, pointer to regs.
2507 r4 is the second argument, pointer to the result.
2508 We should set *result = TOP after leaving this function.
2509
2510 Note:
2511 * To restore stack at epilogue
2512 => sp = r31
2513 * To check stack is big enough for bytecode execution.
2514 => r30 - 8 > SP + 112
2515 * To return execution result.
2516 => 0(r4) = TOP
2517
2518 */
2519
2520/* Emit prologue in inferior memory. See above comments. */
2521
2522static void
2523ppc64v1_emit_prologue (void)
2524{
2525 /* On ELFv1, function pointers really point to function descriptor,
2526 so emit one here. We don't care about contents of words 1 and 2,
2527 so let them just overlap out code. */
2528 uint64_t opd = current_insn_ptr + 8;
2529 uint32_t buf[2];
2530
2531 /* Mind the strict aliasing rules. */
2532 memcpy (buf, &opd, sizeof buf);
2533 emit_insns(buf, 2);
2534 EMIT_ASM (/* Save return address. */
2535 "mflr 0 \n"
2536 "std 0, 16(1) \n"
2537 /* Save r30 and incoming arguments. */
2538 "std 31, -8(1) \n"
2539 "std 30, -16(1) \n"
2540 "std 4, -24(1) \n"
2541 "std 3, -32(1) \n"
2542 /* Point r31 to current r1 for access arguments. */
2543 "mr 31, 1 \n"
2544 /* Adjust SP. 208 is the initial frame size. */
2545 "stdu 1, -208(1) \n"
2546 /* Set r30 to pointing stack-top. */
2547 "addi 30, 1, 168 \n"
2548 /* Initial r3/TOP to 0. */
2549 "li 3, 0 \n");
2550}
2551
2552/* Emit prologue in inferior memory. See above comments. */
2553
2554static void
2555ppc64v2_emit_prologue (void)
2556{
2557 EMIT_ASM (/* Save return address. */
2558 "mflr 0 \n"
2559 "std 0, 16(1) \n"
2560 /* Save r30 and incoming arguments. */
2561 "std 31, -8(1) \n"
2562 "std 30, -16(1) \n"
2563 "std 4, -24(1) \n"
2564 "std 3, -32(1) \n"
2565 /* Point r31 to current r1 for access arguments. */
2566 "mr 31, 1 \n"
2567 /* Adjust SP. 208 is the initial frame size. */
2568 "stdu 1, -208(1) \n"
2569 /* Set r30 to pointing stack-top. */
2570 "addi 30, 1, 168 \n"
2571 /* Initial r3/TOP to 0. */
2572 "li 3, 0 \n");
2573}
2574
2575/* Emit epilogue in inferior memory. See above comments. */
2576
2577static void
2578ppc64_emit_epilogue (void)
2579{
2580 EMIT_ASM (/* Restore SP. */
2581 "ld 1, 0(1) \n"
2582 /* *result = TOP */
2583 "ld 4, -24(1) \n"
2584 "std 3, 0(4) \n"
2585 /* Restore registers. */
2586 "ld 31, -8(1) \n"
2587 "ld 30, -16(1) \n"
2588 /* Restore LR. */
2589 "ld 0, 16(1) \n"
2590 /* Return 0 for no-error. */
2591 "li 3, 0 \n"
2592 "mtlr 0 \n"
2593 "blr \n");
2594}
2595
2596/* TOP = stack[--sp] + TOP */
2597
2598static void
2599ppc64_emit_add (void)
2600{
2601 EMIT_ASM ("ldu 4, 8(30) \n"
2602 "add 3, 4, 3 \n");
2603}
2604
2605/* TOP = stack[--sp] - TOP */
2606
2607static void
2608ppc64_emit_sub (void)
2609{
2610 EMIT_ASM ("ldu 4, 8(30) \n"
2611 "sub 3, 4, 3 \n");
2612}
2613
2614/* TOP = stack[--sp] * TOP */
2615
2616static void
2617ppc64_emit_mul (void)
2618{
2619 EMIT_ASM ("ldu 4, 8(30) \n"
2620 "mulld 3, 4, 3 \n");
2621}
2622
2623/* TOP = stack[--sp] << TOP */
2624
2625static void
2626ppc64_emit_lsh (void)
2627{
2628 EMIT_ASM ("ldu 4, 8(30) \n"
2629 "sld 3, 4, 3 \n");
2630}
2631
2632/* Top = stack[--sp] >> TOP
2633 (Arithmetic shift right) */
2634
2635static void
2636ppc64_emit_rsh_signed (void)
2637{
2638 EMIT_ASM ("ldu 4, 8(30) \n"
2639 "srad 3, 4, 3 \n");
2640}
2641
2642/* Top = stack[--sp] >> TOP
2643 (Logical shift right) */
2644
2645static void
2646ppc64_emit_rsh_unsigned (void)
2647{
2648 EMIT_ASM ("ldu 4, 8(30) \n"
2649 "srd 3, 4, 3 \n");
2650}
2651
2652/* Emit code for signed-extension specified by ARG. */
2653
2654static void
2655ppc64_emit_ext (int arg)
2656{
2657 switch (arg)
2658 {
2659 case 8:
2660 EMIT_ASM ("extsb 3, 3");
2661 break;
2662 case 16:
2663 EMIT_ASM ("extsh 3, 3");
2664 break;
2665 case 32:
2666 EMIT_ASM ("extsw 3, 3");
2667 break;
2668 default:
2669 emit_error = 1;
2670 }
2671}
2672
2673/* Emit code for zero-extension specified by ARG. */
2674
2675static void
2676ppc64_emit_zero_ext (int arg)
2677{
2678 switch (arg)
2679 {
2680 case 8:
2681 EMIT_ASM ("rldicl 3,3,0,56");
2682 break;
2683 case 16:
2684 EMIT_ASM ("rldicl 3,3,0,48");
2685 break;
2686 case 32:
2687 EMIT_ASM ("rldicl 3,3,0,32");
2688 break;
2689 default:
2690 emit_error = 1;
2691 }
2692}
2693
2694/* TOP = !TOP
2695 i.e., TOP = (TOP == 0) ? 1 : 0; */
2696
2697static void
2698ppc64_emit_log_not (void)
2699{
2700 EMIT_ASM ("cntlzd 3, 3 \n"
2701 "srdi 3, 3, 6 \n");
2702}
2703
2704/* TOP = stack[--sp] & TOP */
2705
2706static void
2707ppc64_emit_bit_and (void)
2708{
2709 EMIT_ASM ("ldu 4, 8(30) \n"
2710 "and 3, 4, 3 \n");
2711}
2712
2713/* TOP = stack[--sp] | TOP */
2714
2715static void
2716ppc64_emit_bit_or (void)
2717{
2718 EMIT_ASM ("ldu 4, 8(30) \n"
2719 "or 3, 4, 3 \n");
2720}
2721
2722/* TOP = stack[--sp] ^ TOP */
2723
2724static void
2725ppc64_emit_bit_xor (void)
2726{
2727 EMIT_ASM ("ldu 4, 8(30) \n"
2728 "xor 3, 4, 3 \n");
2729}
2730
2731/* TOP = ~TOP
2732 i.e., TOP = ~(TOP | TOP) */
2733
2734static void
2735ppc64_emit_bit_not (void)
2736{
2737 EMIT_ASM ("nor 3, 3, 3 \n");
2738}
2739
2740/* TOP = stack[--sp] == TOP */
2741
2742static void
2743ppc64_emit_equal (void)
2744{
2745 EMIT_ASM ("ldu 4, 8(30) \n"
2746 "xor 3, 3, 4 \n"
2747 "cntlzd 3, 3 \n"
2748 "srdi 3, 3, 6 \n");
2749}
2750
2751/* TOP = stack[--sp] < TOP
2752 (Signed comparison) */
2753
2754static void
2755ppc64_emit_less_signed (void)
2756{
2757 EMIT_ASM ("ldu 4, 8(30) \n"
2758 "cmpd 7, 4, 3 \n"
2759 "mfcr 3 \n"
2760 "rlwinm 3, 3, 29, 31, 31 \n");
2761}
2762
2763/* TOP = stack[--sp] < TOP
2764 (Unsigned comparison) */
2765
2766static void
2767ppc64_emit_less_unsigned (void)
2768{
2769 EMIT_ASM ("ldu 4, 8(30) \n"
2770 "cmpld 7, 4, 3 \n"
2771 "mfcr 3 \n"
2772 "rlwinm 3, 3, 29, 31, 31 \n");
2773}
2774
2775/* Access the memory address in TOP in size of SIZE.
2776 Zero-extend the read value. */
2777
2778static void
2779ppc64_emit_ref (int size)
2780{
2781 switch (size)
2782 {
2783 case 1:
2784 EMIT_ASM ("lbz 3, 0(3)");
2785 break;
2786 case 2:
2787 EMIT_ASM ("lhz 3, 0(3)");
2788 break;
2789 case 4:
2790 EMIT_ASM ("lwz 3, 0(3)");
2791 break;
2792 case 8:
2793 EMIT_ASM ("ld 3, 0(3)");
2794 break;
2795 }
2796}
2797
2798/* TOP = NUM */
2799
2800static void
2801ppc64_emit_const (LONGEST num)
2802{
2803 uint32_t buf[5];
2804 uint32_t *p = buf;
2805
2806 p += gen_limm (p, 3, num, 1);
2807
2808 emit_insns (buf, p - buf);
2809 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2810}
2811
2812/* Set TOP to the value of register REG by calling get_raw_reg function
2813 with two argument, collected buffer and register number. */
2814
2815static void
2816ppc64v1_emit_reg (int reg)
2817{
2818 uint32_t buf[15];
2819 uint32_t *p = buf;
2820
2821 /* fctx->regs is passed in r3 and then saved in 176(1). */
2822 p += GEN_LD (p, 3, 31, -32);
2823 p += GEN_LI (p, 4, reg);
2824 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2825 p += gen_call (p, get_raw_reg_func_addr (), 1, 1);
2826 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2827
2828 emit_insns (buf, p - buf);
2829 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2830}
2831
2832/* Likewise, for ELFv2. */
2833
2834static void
2835ppc64v2_emit_reg (int reg)
2836{
2837 uint32_t buf[12];
2838 uint32_t *p = buf;
2839
2840 /* fctx->regs is passed in r3 and then saved in 176(1). */
2841 p += GEN_LD (p, 3, 31, -32);
2842 p += GEN_LI (p, 4, reg);
2843 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2844 p += gen_call (p, get_raw_reg_func_addr (), 1, 0);
2845 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2846
2847 emit_insns (buf, p - buf);
2848 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2849}
2850
2851/* TOP = stack[--sp] */
2852
2853static void
2854ppc64_emit_pop (void)
2855{
2856 EMIT_ASM ("ldu 3, 8(30)");
2857}
2858
2859/* stack[sp++] = TOP
2860
2861 Because we may use up bytecode stack, expand 8 doublewords more
2862 if needed. */
2863
2864static void
2865ppc64_emit_stack_flush (void)
2866{
2867 /* Make sure bytecode stack is big enough before push.
2868 Otherwise, expand 64-byte more. */
2869
2870 EMIT_ASM (" std 3, 0(30) \n"
2871 " addi 4, 30, -(112 + 8) \n"
2872 " cmpd 7, 4, 1 \n"
2873 " bgt 7, 1f \n"
2874 " stdu 31, -64(1) \n"
2875 "1:addi 30, 30, -8 \n");
2876}
2877
2878/* Swap TOP and stack[sp-1] */
2879
2880static void
2881ppc64_emit_swap (void)
2882{
2883 EMIT_ASM ("ld 4, 8(30) \n"
2884 "std 3, 8(30) \n"
2885 "mr 3, 4 \n");
2886}
2887
2888/* Call function FN - ELFv1. */
2889
2890static void
2891ppc64v1_emit_call (CORE_ADDR fn)
2892{
2893 uint32_t buf[13];
2894 uint32_t *p = buf;
2895
2896 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2897 p += gen_call (p, fn, 1, 1);
2898 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2899
2900 emit_insns (buf, p - buf);
2901 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2902}
2903
2904/* Call function FN - ELFv2. */
2905
2906static void
2907ppc64v2_emit_call (CORE_ADDR fn)
2908{
2909 uint32_t buf[10];
2910 uint32_t *p = buf;
2911
2912 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2913 p += gen_call (p, fn, 1, 0);
2914 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2915
2916 emit_insns (buf, p - buf);
2917 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2918}
2919
2920/* FN's prototype is `LONGEST(*fn)(int)'.
2921 TOP = fn (arg1)
2922 */
2923
2924static void
2925ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1)
2926{
2927 uint32_t buf[13];
2928 uint32_t *p = buf;
2929
2930 /* Setup argument. arg1 is a 16-bit value. */
2931 p += gen_limm (p, 3, arg1, 1);
2932 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2933 p += gen_call (p, fn, 1, 1);
2934 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2935
2936 emit_insns (buf, p - buf);
2937 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2938}
2939
2940/* Likewise for ELFv2. */
2941
2942static void
2943ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1)
2944{
2945 uint32_t buf[10];
2946 uint32_t *p = buf;
2947
2948 /* Setup argument. arg1 is a 16-bit value. */
2949 p += gen_limm (p, 3, arg1, 1);
2950 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2951 p += gen_call (p, fn, 1, 0);
2952 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2953
2954 emit_insns (buf, p - buf);
2955 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2956}
2957
2958/* FN's prototype is `void(*fn)(int,LONGEST)'.
2959 fn (arg1, TOP)
2960
2961 TOP should be preserved/restored before/after the call. */
2962
2963static void
2964ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1)
2965{
2966 uint32_t buf[17];
2967 uint32_t *p = buf;
2968
2969 /* Save TOP. 0(30) is next-empty. */
2970 p += GEN_STD (p, 3, 30, 0);
2971
2972 /* Setup argument. arg1 is a 16-bit value. */
2973 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
2974 p += gen_limm (p, 3, arg1, 1);
2975 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2976 p += gen_call (p, fn, 1, 1);
2977 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2978
2979 /* Restore TOP */
2980 p += GEN_LD (p, 3, 30, 0);
2981
2982 emit_insns (buf, p - buf);
2983 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2984}
2985
2986/* Likewise for ELFv2. */
2987
2988static void
2989ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1)
2990{
2991 uint32_t buf[14];
2992 uint32_t *p = buf;
2993
2994 /* Save TOP. 0(30) is next-empty. */
2995 p += GEN_STD (p, 3, 30, 0);
2996
2997 /* Setup argument. arg1 is a 16-bit value. */
2998 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
2999 p += gen_limm (p, 3, arg1, 1);
3000 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3001 p += gen_call (p, fn, 1, 0);
3002 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3003
3004 /* Restore TOP */
3005 p += GEN_LD (p, 3, 30, 0);
3006
3007 emit_insns (buf, p - buf);
3008 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3009}
3010
3011/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3012
3013static void
3014ppc64_emit_if_goto (int *offset_p, int *size_p)
3015{
3016 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3017 "ldu 3, 8(30) \n"
3018 "1:bne 7, 1b \n");
3019
3020 if (offset_p)
3021 *offset_p = 8;
3022 if (size_p)
3023 *size_p = 14;
3024}
3025
3026/* Goto if stack[--sp] == TOP */
3027
3028static void
3029ppc64_emit_eq_goto (int *offset_p, int *size_p)
3030{
3031 EMIT_ASM ("ldu 4, 8(30) \n"
3032 "cmpd 7, 4, 3 \n"
3033 "ldu 3, 8(30) \n"
3034 "1:beq 7, 1b \n");
3035
3036 if (offset_p)
3037 *offset_p = 12;
3038 if (size_p)
3039 *size_p = 14;
3040}
3041
3042/* Goto if stack[--sp] != TOP */
3043
3044static void
3045ppc64_emit_ne_goto (int *offset_p, int *size_p)
3046{
3047 EMIT_ASM ("ldu 4, 8(30) \n"
3048 "cmpd 7, 4, 3 \n"
3049 "ldu 3, 8(30) \n"
3050 "1:bne 7, 1b \n");
3051
3052 if (offset_p)
3053 *offset_p = 12;
3054 if (size_p)
3055 *size_p = 14;
3056}
3057
3058/* Goto if stack[--sp] < TOP */
3059
3060static void
3061ppc64_emit_lt_goto (int *offset_p, int *size_p)
3062{
3063 EMIT_ASM ("ldu 4, 8(30) \n"
3064 "cmpd 7, 4, 3 \n"
3065 "ldu 3, 8(30) \n"
3066 "1:blt 7, 1b \n");
3067
3068 if (offset_p)
3069 *offset_p = 12;
3070 if (size_p)
3071 *size_p = 14;
3072}
3073
3074/* Goto if stack[--sp] <= TOP */
3075
3076static void
3077ppc64_emit_le_goto (int *offset_p, int *size_p)
3078{
3079 EMIT_ASM ("ldu 4, 8(30) \n"
3080 "cmpd 7, 4, 3 \n"
3081 "ldu 3, 8(30) \n"
3082 "1:ble 7, 1b \n");
3083
3084 if (offset_p)
3085 *offset_p = 12;
3086 if (size_p)
3087 *size_p = 14;
3088}
3089
3090/* Goto if stack[--sp] > TOP */
3091
3092static void
3093ppc64_emit_gt_goto (int *offset_p, int *size_p)
3094{
3095 EMIT_ASM ("ldu 4, 8(30) \n"
3096 "cmpd 7, 4, 3 \n"
3097 "ldu 3, 8(30) \n"
3098 "1:bgt 7, 1b \n");
3099
3100 if (offset_p)
3101 *offset_p = 12;
3102 if (size_p)
3103 *size_p = 14;
3104}
3105
3106/* Goto if stack[--sp] >= TOP */
3107
3108static void
3109ppc64_emit_ge_goto (int *offset_p, int *size_p)
3110{
3111 EMIT_ASM ("ldu 4, 8(30) \n"
3112 "cmpd 7, 4, 3 \n"
3113 "ldu 3, 8(30) \n"
3114 "1:bge 7, 1b \n");
3115
3116 if (offset_p)
3117 *offset_p = 12;
3118 if (size_p)
3119 *size_p = 14;
3120}
3121
3122/* Table of emit ops for 64-bit ELFv1. */
3123
3124static struct emit_ops ppc64v1_emit_ops_impl =
3125{
3126 ppc64v1_emit_prologue,
3127 ppc64_emit_epilogue,
3128 ppc64_emit_add,
3129 ppc64_emit_sub,
3130 ppc64_emit_mul,
3131 ppc64_emit_lsh,
3132 ppc64_emit_rsh_signed,
3133 ppc64_emit_rsh_unsigned,
3134 ppc64_emit_ext,
3135 ppc64_emit_log_not,
3136 ppc64_emit_bit_and,
3137 ppc64_emit_bit_or,
3138 ppc64_emit_bit_xor,
3139 ppc64_emit_bit_not,
3140 ppc64_emit_equal,
3141 ppc64_emit_less_signed,
3142 ppc64_emit_less_unsigned,
3143 ppc64_emit_ref,
3144 ppc64_emit_if_goto,
3145 ppc_emit_goto,
3146 ppc_write_goto_address,
3147 ppc64_emit_const,
3148 ppc64v1_emit_call,
3149 ppc64v1_emit_reg,
3150 ppc64_emit_pop,
3151 ppc64_emit_stack_flush,
3152 ppc64_emit_zero_ext,
3153 ppc64_emit_swap,
3154 ppc_emit_stack_adjust,
3155 ppc64v1_emit_int_call_1,
3156 ppc64v1_emit_void_call_2,
3157 ppc64_emit_eq_goto,
3158 ppc64_emit_ne_goto,
3159 ppc64_emit_lt_goto,
3160 ppc64_emit_le_goto,
3161 ppc64_emit_gt_goto,
3162 ppc64_emit_ge_goto
3163};
3164
3165/* Table of emit ops for 64-bit ELFv2. */
3166
3167static struct emit_ops ppc64v2_emit_ops_impl =
3168{
3169 ppc64v2_emit_prologue,
3170 ppc64_emit_epilogue,
3171 ppc64_emit_add,
3172 ppc64_emit_sub,
3173 ppc64_emit_mul,
3174 ppc64_emit_lsh,
3175 ppc64_emit_rsh_signed,
3176 ppc64_emit_rsh_unsigned,
3177 ppc64_emit_ext,
3178 ppc64_emit_log_not,
3179 ppc64_emit_bit_and,
3180 ppc64_emit_bit_or,
3181 ppc64_emit_bit_xor,
3182 ppc64_emit_bit_not,
3183 ppc64_emit_equal,
3184 ppc64_emit_less_signed,
3185 ppc64_emit_less_unsigned,
3186 ppc64_emit_ref,
3187 ppc64_emit_if_goto,
3188 ppc_emit_goto,
3189 ppc_write_goto_address,
3190 ppc64_emit_const,
3191 ppc64v2_emit_call,
3192 ppc64v2_emit_reg,
3193 ppc64_emit_pop,
3194 ppc64_emit_stack_flush,
3195 ppc64_emit_zero_ext,
3196 ppc64_emit_swap,
3197 ppc_emit_stack_adjust,
3198 ppc64v2_emit_int_call_1,
3199 ppc64v2_emit_void_call_2,
3200 ppc64_emit_eq_goto,
3201 ppc64_emit_ne_goto,
3202 ppc64_emit_lt_goto,
3203 ppc64_emit_le_goto,
3204 ppc64_emit_gt_goto,
3205 ppc64_emit_ge_goto
3206};
3207
3208#endif
3209
3210/* Implementation of linux_target_ops method "emit_ops". */
3211
3212static struct emit_ops *
3213ppc_emit_ops (void)
3214{
3215#ifdef __powerpc64__
3216 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3217
3218 if (register_size (regcache->tdesc, 0) == 8)
3219 {
3220 if (is_elfv2_inferior ())
3221 return &ppc64v2_emit_ops_impl;
3222 else
3223 return &ppc64v1_emit_ops_impl;
3224 }
3225#endif
3226 return &ppc_emit_ops_impl;
3227}
3228
a2174ba4
MK		 3229/* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3230
3231static int
3232ppc_get_ipa_tdesc_idx (void)
3233{
3234 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3235 const struct target_desc *tdesc = regcache->tdesc;
3236
3237#ifdef __powerpc64__
3238 if (tdesc == tdesc_powerpc_64l)
3239 return PPC_TDESC_BASE;
3240 if (tdesc == tdesc_powerpc_altivec64l)
3241 return PPC_TDESC_ALTIVEC;
3242 if (tdesc == tdesc_powerpc_cell64l)
3243 return PPC_TDESC_CELL;
3244 if (tdesc == tdesc_powerpc_vsx64l)
3245 return PPC_TDESC_VSX;
3246 if (tdesc == tdesc_powerpc_isa205_64l)
3247 return PPC_TDESC_ISA205;
3248 if (tdesc == tdesc_powerpc_isa205_altivec64l)
3249 return PPC_TDESC_ISA205_ALTIVEC;
3250 if (tdesc == tdesc_powerpc_isa205_vsx64l)
3251 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3252 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
3253 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3254 if (tdesc == tdesc_powerpc_isa207_vsx64l)
3255 return PPC_TDESC_ISA207_VSX;
a2174ba4
MK		 3256#endif
3257
3258 if (tdesc == tdesc_powerpc_32l)
3259 return PPC_TDESC_BASE;
3260 if (tdesc == tdesc_powerpc_altivec32l)
3261 return PPC_TDESC_ALTIVEC;
3262 if (tdesc == tdesc_powerpc_cell32l)
3263 return PPC_TDESC_CELL;
3264 if (tdesc == tdesc_powerpc_vsx32l)
3265 return PPC_TDESC_VSX;
3266 if (tdesc == tdesc_powerpc_isa205_32l)
3267 return PPC_TDESC_ISA205;
3268 if (tdesc == tdesc_powerpc_isa205_altivec32l)
3269 return PPC_TDESC_ISA205_ALTIVEC;
3270 if (tdesc == tdesc_powerpc_isa205_vsx32l)
3271 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3272 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
3273 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3274 if (tdesc == tdesc_powerpc_isa207_vsx32l)
3275 return PPC_TDESC_ISA207_VSX;
a2174ba4
MK		 3276 if (tdesc == tdesc_powerpc_e500l)
3277 return PPC_TDESC_E500;
3278
3279 return 0;
3280}
3281
2ec06d2e 3282struct linux_target_ops the_low_target = {
6fe305f7 3283 ppc_arch_setup,
3aee8918 3284 ppc_regs_info,
2ec06d2e
DJ		 3285 ppc_cannot_fetch_register,
3286 ppc_cannot_store_register,
c14dfd32 3287 NULL, /* fetch_register */
0d62e5e8
DJ		 3288 ppc_get_pc,
3289 ppc_set_pc,
dd373349
AT		 3290 NULL, /* breakpoint_kind_from_pc */
3291 ppc_sw_breakpoint_from_kind,
0d62e5e8
DJ		 3292 NULL,
3293 0,
3294 ppc_breakpoint_at,
657f9cde
WW		 3295 ppc_supports_z_point_type,
3296 ppc_insert_point,
3297 ppc_remove_point,
5b0a002e
UW		 3298 NULL,
3299 NULL,
3300 ppc_collect_ptrace_register,
3301 ppc_supply_ptrace_register,
7d00775e
AT		 3302 NULL, /* siginfo_fixup */
3303 NULL, /* new_process */
04ec7890 3304 NULL, /* delete_process */
7d00775e 3305 NULL, /* new_thread */
466eecee 3306 NULL, /* delete_thread */
7d00775e
AT		 3307 NULL, /* new_fork */
3308 NULL, /* prepare_to_resume */
3309 NULL, /* process_qsupported */
b04fd3be 3310 ppc_supports_tracepoints,
a2174ba4
MK		 3311 ppc_get_thread_area,
3312 ppc_install_fast_tracepoint_jump_pad,
14e2b6d9 3313 ppc_emit_ops,
a2174ba4 3314 ppc_get_min_fast_tracepoint_insn_len,
7d00775e
AT		 3315 NULL, /* supports_range_stepping */
3316 NULL, /* breakpoint_kind_from_current_state */
3317 ppc_supports_hardware_single_step,
a2174ba4
MK		 3318 NULL, /* get_syscall_trapinfo */
3319 ppc_get_ipa_tdesc_idx,
2ec06d2e 3320};
3aee8918
PA		 3321
3322void
3323initialize_low_arch (void)
3324{
3325 /* Initialize the Linux target descriptions. */
3326
3327 init_registers_powerpc_32l ();
3328 init_registers_powerpc_altivec32l ();
3329 init_registers_powerpc_cell32l ();
3330 init_registers_powerpc_vsx32l ();
3331 init_registers_powerpc_isa205_32l ();
3332 init_registers_powerpc_isa205_altivec32l ();
3333 init_registers_powerpc_isa205_vsx32l ();
7ca18ed6 3334 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
f2cf6173 3335 init_registers_powerpc_isa207_vsx32l ();
3aee8918 3336 init_registers_powerpc_e500l ();
a2174ba4 3337#if __powerpc64__
3aee8918
PA		 3338 init_registers_powerpc_64l ();
3339 init_registers_powerpc_altivec64l ();
3340 init_registers_powerpc_cell64l ();
3341 init_registers_powerpc_vsx64l ();
3342 init_registers_powerpc_isa205_64l ();
3343 init_registers_powerpc_isa205_altivec64l ();
3344 init_registers_powerpc_isa205_vsx64l ();
7ca18ed6 3345 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
f2cf6173 3346 init_registers_powerpc_isa207_vsx64l ();
a2174ba4 3347#endif
3aee8918
PA		 3348
3349 initialize_regsets_info (&ppc_regsets_info);
3350}
GDB Binutils - Deliverables
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