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0a30fbc4 DJ |
1 | /* GNU/Linux/PowerPC specific low level interface, for the remote server for |
2 | GDB. | |
618f726f | 3 | Copyright (C) 1995-2016 Free Software Foundation, Inc. |
0a30fbc4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
19 | |
20 | #include "server.h" | |
58caa3dc | 21 | #include "linux-low.h" |
0a30fbc4 | 22 | |
b6430ec3 | 23 | #include <elf.h> |
0a30fbc4 DJ |
24 | #include <asm/ptrace.h> |
25 | ||
514c5338 | 26 | #include "nat/ppc-linux.h" |
b6430ec3 UW |
27 | |
28 | static unsigned long ppc_hwcap; | |
29 | ||
30 | ||
7284e1be UW |
31 | /* Defined in auto-generated file powerpc-32l.c. */ |
32 | void init_registers_powerpc_32l (void); | |
3aee8918 PA |
33 | extern const struct target_desc *tdesc_powerpc_32l; |
34 | ||
7284e1be UW |
35 | /* Defined in auto-generated file powerpc-altivec32l.c. */ |
36 | void init_registers_powerpc_altivec32l (void); | |
3aee8918 PA |
37 | extern const struct target_desc *tdesc_powerpc_altivec32l; |
38 | ||
f4d9bade UW |
39 | /* Defined in auto-generated file powerpc-cell32l.c. */ |
40 | void init_registers_powerpc_cell32l (void); | |
3aee8918 PA |
41 | extern const struct target_desc *tdesc_powerpc_cell32l; |
42 | ||
677c5bb1 LM |
43 | /* Defined in auto-generated file powerpc-vsx32l.c. */ |
44 | void init_registers_powerpc_vsx32l (void); | |
3aee8918 PA |
45 | extern const struct target_desc *tdesc_powerpc_vsx32l; |
46 | ||
2c4ad781 TJB |
47 | /* Defined in auto-generated file powerpc-isa205-32l.c. */ |
48 | void init_registers_powerpc_isa205_32l (void); | |
3aee8918 PA |
49 | extern const struct target_desc *tdesc_powerpc_isa205_32l; |
50 | ||
2c4ad781 TJB |
51 | /* Defined in auto-generated file powerpc-isa205-altivec32l.c. */ |
52 | void init_registers_powerpc_isa205_altivec32l (void); | |
3aee8918 PA |
53 | extern const struct target_desc *tdesc_powerpc_isa205_altivec32l; |
54 | ||
2c4ad781 TJB |
55 | /* Defined in auto-generated file powerpc-isa205-vsx32l.c. */ |
56 | void init_registers_powerpc_isa205_vsx32l (void); | |
3aee8918 PA |
57 | extern const struct target_desc *tdesc_powerpc_isa205_vsx32l; |
58 | ||
7284e1be UW |
59 | /* Defined in auto-generated file powerpc-e500l.c. */ |
60 | void init_registers_powerpc_e500l (void); | |
3aee8918 PA |
61 | extern const struct target_desc *tdesc_powerpc_e500l; |
62 | ||
7284e1be UW |
63 | /* Defined in auto-generated file powerpc-64l.c. */ |
64 | void init_registers_powerpc_64l (void); | |
3aee8918 PA |
65 | extern const struct target_desc *tdesc_powerpc_64l; |
66 | ||
7284e1be UW |
67 | /* Defined in auto-generated file powerpc-altivec64l.c. */ |
68 | void init_registers_powerpc_altivec64l (void); | |
3aee8918 PA |
69 | extern const struct target_desc *tdesc_powerpc_altivec64l; |
70 | ||
f4d9bade UW |
71 | /* Defined in auto-generated file powerpc-cell64l.c. */ |
72 | void init_registers_powerpc_cell64l (void); | |
3aee8918 PA |
73 | extern const struct target_desc *tdesc_powerpc_cell64l; |
74 | ||
677c5bb1 LM |
75 | /* Defined in auto-generated file powerpc-vsx64l.c. */ |
76 | void init_registers_powerpc_vsx64l (void); | |
3aee8918 PA |
77 | extern const struct target_desc *tdesc_powerpc_vsx64l; |
78 | ||
2c4ad781 TJB |
79 | /* Defined in auto-generated file powerpc-isa205-64l.c. */ |
80 | void init_registers_powerpc_isa205_64l (void); | |
3aee8918 PA |
81 | extern const struct target_desc *tdesc_powerpc_isa205_64l; |
82 | ||
2c4ad781 TJB |
83 | /* Defined in auto-generated file powerpc-isa205-altivec64l.c. */ |
84 | void init_registers_powerpc_isa205_altivec64l (void); | |
3aee8918 PA |
85 | extern const struct target_desc *tdesc_powerpc_isa205_altivec64l; |
86 | ||
2c4ad781 TJB |
87 | /* Defined in auto-generated file powerpc-isa205-vsx64l.c. */ |
88 | void init_registers_powerpc_isa205_vsx64l (void); | |
3aee8918 | 89 | extern const struct target_desc *tdesc_powerpc_isa205_vsx64l; |
7284e1be UW |
90 | |
91 | #define ppc_num_regs 73 | |
92 | ||
5b0a002e UW |
93 | #ifdef __powerpc64__ |
94 | /* We use a constant for FPSCR instead of PT_FPSCR, because | |
95 | many shipped PPC64 kernels had the wrong value in ptrace.h. */ | |
96 | static int ppc_regmap[] = | |
97 | {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8, | |
98 | PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8, | |
99 | PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8, | |
100 | PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8, | |
101 | PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8, | |
102 | PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8, | |
103 | PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8, | |
104 | PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8, | |
105 | PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24, | |
106 | PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56, | |
107 | PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88, | |
108 | PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120, | |
109 | PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152, | |
110 | PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184, | |
111 | PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216, | |
112 | PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248, | |
113 | PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8, | |
7284e1be UW |
114 | PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256, |
115 | PT_ORIG_R3 * 8, PT_TRAP * 8 }; | |
5b0a002e | 116 | #else |
0a30fbc4 | 117 | /* Currently, don't check/send MQ. */ |
2ec06d2e | 118 | static int ppc_regmap[] = |
0a30fbc4 DJ |
119 | {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4, |
120 | PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4, | |
121 | PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4, | |
122 | PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4, | |
123 | PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4, | |
124 | PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4, | |
125 | PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4, | |
126 | PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4, | |
127 | PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24, | |
128 | PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56, | |
129 | PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88, | |
130 | PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120, | |
131 | PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152, | |
132 | PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184, | |
133 | PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216, | |
134 | PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248, | |
135 | PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4, | |
7284e1be UW |
136 | PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4, |
137 | PT_ORIG_R3 * 4, PT_TRAP * 4 | |
b6430ec3 UW |
138 | }; |
139 | ||
140 | static int ppc_regmap_e500[] = | |
141 | {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4, | |
142 | PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4, | |
143 | PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4, | |
144 | PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4, | |
145 | PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4, | |
146 | PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4, | |
147 | PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4, | |
148 | PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4, | |
149 | -1, -1, -1, -1, | |
150 | -1, -1, -1, -1, | |
151 | -1, -1, -1, -1, | |
152 | -1, -1, -1, -1, | |
153 | -1, -1, -1, -1, | |
154 | -1, -1, -1, -1, | |
155 | -1, -1, -1, -1, | |
156 | -1, -1, -1, -1, | |
157 | PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4, | |
7284e1be UW |
158 | PT_CTR * 4, PT_XER * 4, -1, |
159 | PT_ORIG_R3 * 4, PT_TRAP * 4 | |
30ed0a8f | 160 | }; |
5b0a002e | 161 | #endif |
0a30fbc4 | 162 | |
2ec06d2e DJ |
163 | static int |
164 | ppc_cannot_store_register (int regno) | |
0a30fbc4 | 165 | { |
3aee8918 PA |
166 | const struct target_desc *tdesc = current_process ()->tdesc; |
167 | ||
b6430ec3 | 168 | #ifndef __powerpc64__ |
bc1e36ca | 169 | /* Some kernels do not allow us to store fpscr. */ |
3aee8918 PA |
170 | if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE) |
171 | && regno == find_regno (tdesc, "fpscr")) | |
bc1e36ca | 172 | return 2; |
30ed0a8f | 173 | #endif |
bc1e36ca | 174 | |
7284e1be | 175 | /* Some kernels do not allow us to store orig_r3 or trap. */ |
3aee8918 PA |
176 | if (regno == find_regno (tdesc, "orig_r3") |
177 | || regno == find_regno (tdesc, "trap")) | |
7284e1be UW |
178 | return 2; |
179 | ||
0a30fbc4 DJ |
180 | return 0; |
181 | } | |
182 | ||
2ec06d2e DJ |
183 | static int |
184 | ppc_cannot_fetch_register (int regno) | |
0a30fbc4 DJ |
185 | { |
186 | return 0; | |
187 | } | |
188 | ||
5b0a002e | 189 | static void |
442ea881 | 190 | ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) |
5b0a002e | 191 | { |
76b233dd UW |
192 | memset (buf, 0, sizeof (long)); |
193 | ||
2e4bb98a EBM |
194 | if (__BYTE_ORDER == __LITTLE_ENDIAN) |
195 | { | |
196 | /* Little-endian values always sit at the left end of the buffer. */ | |
197 | collect_register (regcache, regno, buf); | |
198 | } | |
199 | else if (__BYTE_ORDER == __BIG_ENDIAN) | |
200 | { | |
201 | /* Big-endian values sit at the right end of the buffer. In case of | |
202 | registers whose sizes are smaller than sizeof (long), we must use a | |
203 | padding to access them correctly. */ | |
204 | int size = register_size (regcache->tdesc, regno); | |
205 | ||
206 | if (size < sizeof (long)) | |
207 | collect_register (regcache, regno, buf + sizeof (long) - size); | |
208 | else | |
209 | collect_register (regcache, regno, buf); | |
210 | } | |
5b0a002e | 211 | else |
2e4bb98a | 212 | perror_with_name ("Unexpected byte order"); |
5b0a002e UW |
213 | } |
214 | ||
215 | static void | |
442ea881 PA |
216 | ppc_supply_ptrace_register (struct regcache *regcache, |
217 | int regno, const char *buf) | |
5b0a002e | 218 | { |
2e4bb98a EBM |
219 | if (__BYTE_ORDER == __LITTLE_ENDIAN) |
220 | { | |
221 | /* Little-endian values always sit at the left end of the buffer. */ | |
222 | supply_register (regcache, regno, buf); | |
223 | } | |
224 | else if (__BYTE_ORDER == __BIG_ENDIAN) | |
225 | { | |
226 | /* Big-endian values sit at the right end of the buffer. In case of | |
227 | registers whose sizes are smaller than sizeof (long), we must use a | |
228 | padding to access them correctly. */ | |
229 | int size = register_size (regcache->tdesc, regno); | |
230 | ||
231 | if (size < sizeof (long)) | |
232 | supply_register (regcache, regno, buf + sizeof (long) - size); | |
233 | else | |
234 | supply_register (regcache, regno, buf); | |
235 | } | |
5b0a002e | 236 | else |
2e4bb98a | 237 | perror_with_name ("Unexpected byte order"); |
5b0a002e UW |
238 | } |
239 | ||
0b9ff2c0 UW |
240 | |
241 | #define INSTR_SC 0x44000002 | |
242 | #define NR_spu_run 0x0116 | |
243 | ||
244 | /* If the PPU thread is currently stopped on a spu_run system call, | |
245 | return to FD and ADDR the file handle and NPC parameter address | |
246 | used with the system call. Return non-zero if successful. */ | |
247 | static int | |
442ea881 | 248 | parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr) |
0b9ff2c0 UW |
249 | { |
250 | CORE_ADDR curr_pc; | |
251 | int curr_insn; | |
252 | int curr_r0; | |
253 | ||
3aee8918 | 254 | if (register_size (regcache->tdesc, 0) == 4) |
0b9ff2c0 UW |
255 | { |
256 | unsigned int pc, r0, r3, r4; | |
442ea881 PA |
257 | collect_register_by_name (regcache, "pc", &pc); |
258 | collect_register_by_name (regcache, "r0", &r0); | |
259 | collect_register_by_name (regcache, "orig_r3", &r3); | |
260 | collect_register_by_name (regcache, "r4", &r4); | |
0b9ff2c0 UW |
261 | curr_pc = (CORE_ADDR) pc; |
262 | curr_r0 = (int) r0; | |
263 | *fd = (int) r3; | |
264 | *addr = (CORE_ADDR) r4; | |
265 | } | |
266 | else | |
267 | { | |
268 | unsigned long pc, r0, r3, r4; | |
442ea881 PA |
269 | collect_register_by_name (regcache, "pc", &pc); |
270 | collect_register_by_name (regcache, "r0", &r0); | |
271 | collect_register_by_name (regcache, "orig_r3", &r3); | |
272 | collect_register_by_name (regcache, "r4", &r4); | |
0b9ff2c0 UW |
273 | curr_pc = (CORE_ADDR) pc; |
274 | curr_r0 = (int) r0; | |
275 | *fd = (int) r3; | |
276 | *addr = (CORE_ADDR) r4; | |
277 | } | |
278 | ||
279 | /* Fetch instruction preceding current NIP. */ | |
280 | if ((*the_target->read_memory) (curr_pc - 4, | |
281 | (unsigned char *) &curr_insn, 4) != 0) | |
282 | return 0; | |
283 | /* It should be a "sc" instruction. */ | |
284 | if (curr_insn != INSTR_SC) | |
285 | return 0; | |
286 | /* System call number should be NR_spu_run. */ | |
287 | if (curr_r0 != NR_spu_run) | |
288 | return 0; | |
289 | ||
290 | return 1; | |
291 | } | |
292 | ||
0d62e5e8 | 293 | static CORE_ADDR |
442ea881 | 294 | ppc_get_pc (struct regcache *regcache) |
0d62e5e8 | 295 | { |
0b9ff2c0 UW |
296 | CORE_ADDR addr; |
297 | int fd; | |
298 | ||
442ea881 | 299 | if (parse_spufs_run (regcache, &fd, &addr)) |
0b9ff2c0 UW |
300 | { |
301 | unsigned int pc; | |
302 | (*the_target->read_memory) (addr, (unsigned char *) &pc, 4); | |
493e2a69 MS |
303 | return ((CORE_ADDR)1 << 63) |
304 | | ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4); | |
0b9ff2c0 | 305 | } |
3aee8918 | 306 | else if (register_size (regcache->tdesc, 0) == 4) |
6fe305f7 UW |
307 | { |
308 | unsigned int pc; | |
442ea881 | 309 | collect_register_by_name (regcache, "pc", &pc); |
6fe305f7 UW |
310 | return (CORE_ADDR) pc; |
311 | } | |
312 | else | |
313 | { | |
314 | unsigned long pc; | |
442ea881 | 315 | collect_register_by_name (regcache, "pc", &pc); |
6fe305f7 UW |
316 | return (CORE_ADDR) pc; |
317 | } | |
0d62e5e8 DJ |
318 | } |
319 | ||
320 | static void | |
442ea881 | 321 | ppc_set_pc (struct regcache *regcache, CORE_ADDR pc) |
0d62e5e8 | 322 | { |
0b9ff2c0 UW |
323 | CORE_ADDR addr; |
324 | int fd; | |
325 | ||
442ea881 | 326 | if (parse_spufs_run (regcache, &fd, &addr)) |
0b9ff2c0 UW |
327 | { |
328 | unsigned int newpc = pc; | |
329 | (*the_target->write_memory) (addr, (unsigned char *) &newpc, 4); | |
330 | } | |
3aee8918 | 331 | else if (register_size (regcache->tdesc, 0) == 4) |
6fe305f7 UW |
332 | { |
333 | unsigned int newpc = pc; | |
442ea881 | 334 | supply_register_by_name (regcache, "pc", &newpc); |
6fe305f7 UW |
335 | } |
336 | else | |
337 | { | |
338 | unsigned long newpc = pc; | |
442ea881 | 339 | supply_register_by_name (regcache, "pc", &newpc); |
6fe305f7 UW |
340 | } |
341 | } | |
342 | ||
b6430ec3 UW |
343 | |
344 | static int | |
345 | ppc_get_hwcap (unsigned long *valp) | |
346 | { | |
3aee8918 PA |
347 | const struct target_desc *tdesc = current_process ()->tdesc; |
348 | int wordsize = register_size (tdesc, 0); | |
2bc84e8a | 349 | unsigned char *data = (unsigned char *) alloca (2 * wordsize); |
b6430ec3 UW |
350 | int offset = 0; |
351 | ||
352 | while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize) | |
353 | { | |
354 | if (wordsize == 4) | |
355 | { | |
356 | unsigned int *data_p = (unsigned int *)data; | |
357 | if (data_p[0] == AT_HWCAP) | |
358 | { | |
359 | *valp = data_p[1]; | |
360 | return 1; | |
361 | } | |
362 | } | |
363 | else | |
364 | { | |
365 | unsigned long *data_p = (unsigned long *)data; | |
366 | if (data_p[0] == AT_HWCAP) | |
367 | { | |
368 | *valp = data_p[1]; | |
369 | return 1; | |
370 | } | |
371 | } | |
372 | ||
373 | offset += 2 * wordsize; | |
374 | } | |
375 | ||
376 | *valp = 0; | |
377 | return 0; | |
378 | } | |
379 | ||
3aee8918 PA |
380 | #ifndef __powerpc64__ |
381 | static int ppc_regmap_adjusted; | |
382 | #endif | |
383 | ||
0d62e5e8 | 384 | |
5b0a002e | 385 | /* Correct in either endianness. |
0d62e5e8 DJ |
386 | This instruction is "twge r2, r2", which GDB uses as a software |
387 | breakpoint. */ | |
5b0a002e | 388 | static const unsigned int ppc_breakpoint = 0x7d821008; |
0d62e5e8 DJ |
389 | #define ppc_breakpoint_len 4 |
390 | ||
dd373349 AT |
391 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
392 | ||
393 | static const gdb_byte * | |
394 | ppc_sw_breakpoint_from_kind (int kind, int *size) | |
395 | { | |
396 | *size = ppc_breakpoint_len; | |
397 | return (const gdb_byte *) &ppc_breakpoint; | |
398 | } | |
399 | ||
0d62e5e8 DJ |
400 | static int |
401 | ppc_breakpoint_at (CORE_ADDR where) | |
402 | { | |
5b0a002e | 403 | unsigned int insn; |
0d62e5e8 | 404 | |
0b9ff2c0 UW |
405 | if (where & ((CORE_ADDR)1 << 63)) |
406 | { | |
407 | char mem_annex[32]; | |
408 | sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff)); | |
409 | (*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn, | |
410 | NULL, where & 0xffffffff, 4); | |
411 | if (insn == 0x3fff) | |
412 | return 1; | |
413 | } | |
414 | else | |
415 | { | |
416 | (*the_target->read_memory) (where, (unsigned char *) &insn, 4); | |
417 | if (insn == ppc_breakpoint) | |
418 | return 1; | |
419 | /* If necessary, recognize more trap instructions here. GDB only uses | |
420 | the one. */ | |
421 | } | |
422 | ||
0d62e5e8 DJ |
423 | return 0; |
424 | } | |
425 | ||
657f9cde WW |
426 | /* Implement supports_z_point_type target-ops. |
427 | Returns true if type Z_TYPE breakpoint is supported. | |
428 | ||
429 | Handling software breakpoint at server side, so tracepoints | |
430 | and breakpoints can be inserted at the same location. */ | |
431 | ||
432 | static int | |
433 | ppc_supports_z_point_type (char z_type) | |
434 | { | |
435 | switch (z_type) | |
436 | { | |
437 | case Z_PACKET_SW_BP: | |
438 | return 1; | |
439 | case Z_PACKET_HW_BP: | |
440 | case Z_PACKET_WRITE_WP: | |
441 | case Z_PACKET_ACCESS_WP: | |
442 | default: | |
443 | return 0; | |
444 | } | |
445 | } | |
446 | ||
447 | /* Implement insert_point target-ops. | |
448 | Returns 0 on success, -1 on failure and 1 on unsupported. */ | |
449 | ||
450 | static int | |
451 | ppc_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, | |
452 | int size, struct raw_breakpoint *bp) | |
453 | { | |
454 | switch (type) | |
455 | { | |
456 | case raw_bkpt_type_sw: | |
457 | return insert_memory_breakpoint (bp); | |
458 | ||
459 | case raw_bkpt_type_hw: | |
460 | case raw_bkpt_type_write_wp: | |
461 | case raw_bkpt_type_access_wp: | |
462 | default: | |
463 | /* Unsupported. */ | |
464 | return 1; | |
465 | } | |
466 | } | |
467 | ||
468 | /* Implement remove_point target-ops. | |
469 | Returns 0 on success, -1 on failure and 1 on unsupported. */ | |
470 | ||
471 | static int | |
472 | ppc_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, | |
473 | int size, struct raw_breakpoint *bp) | |
474 | { | |
475 | switch (type) | |
476 | { | |
477 | case raw_bkpt_type_sw: | |
478 | return remove_memory_breakpoint (bp); | |
479 | ||
480 | case raw_bkpt_type_hw: | |
481 | case raw_bkpt_type_write_wp: | |
482 | case raw_bkpt_type_access_wp: | |
483 | default: | |
484 | /* Unsupported. */ | |
485 | return 1; | |
486 | } | |
487 | } | |
488 | ||
e9d25b98 DJ |
489 | /* Provide only a fill function for the general register set. ps_lgetregs |
490 | will use this for NPTL support. */ | |
491 | ||
442ea881 | 492 | static void ppc_fill_gregset (struct regcache *regcache, void *buf) |
e9d25b98 DJ |
493 | { |
494 | int i; | |
495 | ||
496 | for (i = 0; i < 32; i++) | |
442ea881 | 497 | ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]); |
e9d25b98 DJ |
498 | |
499 | for (i = 64; i < 70; i++) | |
442ea881 | 500 | ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]); |
7284e1be UW |
501 | |
502 | for (i = 71; i < 73; i++) | |
442ea881 | 503 | ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]); |
e9d25b98 DJ |
504 | } |
505 | ||
677c5bb1 LM |
506 | #define SIZEOF_VSXREGS 32*8 |
507 | ||
508 | static void | |
442ea881 | 509 | ppc_fill_vsxregset (struct regcache *regcache, void *buf) |
677c5bb1 LM |
510 | { |
511 | int i, base; | |
2bc84e8a | 512 | char *regset = (char *) buf; |
677c5bb1 LM |
513 | |
514 | if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX)) | |
515 | return; | |
516 | ||
3aee8918 | 517 | base = find_regno (regcache->tdesc, "vs0h"); |
677c5bb1 | 518 | for (i = 0; i < 32; i++) |
442ea881 | 519 | collect_register (regcache, base + i, ®set[i * 8]); |
677c5bb1 LM |
520 | } |
521 | ||
522 | static void | |
442ea881 | 523 | ppc_store_vsxregset (struct regcache *regcache, const void *buf) |
677c5bb1 LM |
524 | { |
525 | int i, base; | |
2bc84e8a | 526 | const char *regset = (const char *) buf; |
677c5bb1 LM |
527 | |
528 | if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX)) | |
529 | return; | |
530 | ||
3aee8918 | 531 | base = find_regno (regcache->tdesc, "vs0h"); |
677c5bb1 | 532 | for (i = 0; i < 32; i++) |
442ea881 | 533 | supply_register (regcache, base + i, ®set[i * 8]); |
677c5bb1 LM |
534 | } |
535 | ||
30ed0a8f DJ |
536 | #define SIZEOF_VRREGS 33*16+4 |
537 | ||
538 | static void | |
442ea881 | 539 | ppc_fill_vrregset (struct regcache *regcache, void *buf) |
30ed0a8f DJ |
540 | { |
541 | int i, base; | |
2bc84e8a | 542 | char *regset = (char *) buf; |
30ed0a8f | 543 | |
b6430ec3 UW |
544 | if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)) |
545 | return; | |
546 | ||
3aee8918 | 547 | base = find_regno (regcache->tdesc, "vr0"); |
30ed0a8f | 548 | for (i = 0; i < 32; i++) |
442ea881 | 549 | collect_register (regcache, base + i, ®set[i * 16]); |
30ed0a8f | 550 | |
442ea881 PA |
551 | collect_register_by_name (regcache, "vscr", ®set[32 * 16 + 12]); |
552 | collect_register_by_name (regcache, "vrsave", ®set[33 * 16]); | |
30ed0a8f DJ |
553 | } |
554 | ||
555 | static void | |
442ea881 | 556 | ppc_store_vrregset (struct regcache *regcache, const void *buf) |
30ed0a8f DJ |
557 | { |
558 | int i, base; | |
2bc84e8a | 559 | const char *regset = (const char *) buf; |
30ed0a8f | 560 | |
b6430ec3 UW |
561 | if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)) |
562 | return; | |
563 | ||
3aee8918 | 564 | base = find_regno (regcache->tdesc, "vr0"); |
30ed0a8f | 565 | for (i = 0; i < 32; i++) |
442ea881 | 566 | supply_register (regcache, base + i, ®set[i * 16]); |
30ed0a8f | 567 | |
442ea881 PA |
568 | supply_register_by_name (regcache, "vscr", ®set[32 * 16 + 12]); |
569 | supply_register_by_name (regcache, "vrsave", ®set[33 * 16]); | |
30ed0a8f DJ |
570 | } |
571 | ||
30ed0a8f DJ |
572 | struct gdb_evrregset_t |
573 | { | |
574 | unsigned long evr[32]; | |
575 | unsigned long long acc; | |
576 | unsigned long spefscr; | |
577 | }; | |
578 | ||
579 | static void | |
442ea881 | 580 | ppc_fill_evrregset (struct regcache *regcache, void *buf) |
30ed0a8f DJ |
581 | { |
582 | int i, ev0; | |
2bc84e8a | 583 | struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf; |
30ed0a8f | 584 | |
b6430ec3 UW |
585 | if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)) |
586 | return; | |
587 | ||
3aee8918 | 588 | ev0 = find_regno (regcache->tdesc, "ev0h"); |
30ed0a8f | 589 | for (i = 0; i < 32; i++) |
442ea881 | 590 | collect_register (regcache, ev0 + i, ®set->evr[i]); |
30ed0a8f | 591 | |
442ea881 PA |
592 | collect_register_by_name (regcache, "acc", ®set->acc); |
593 | collect_register_by_name (regcache, "spefscr", ®set->spefscr); | |
30ed0a8f DJ |
594 | } |
595 | ||
596 | static void | |
442ea881 | 597 | ppc_store_evrregset (struct regcache *regcache, const void *buf) |
30ed0a8f DJ |
598 | { |
599 | int i, ev0; | |
2bc84e8a | 600 | const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf; |
30ed0a8f | 601 | |
b6430ec3 UW |
602 | if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)) |
603 | return; | |
604 | ||
3aee8918 | 605 | ev0 = find_regno (regcache->tdesc, "ev0h"); |
30ed0a8f | 606 | for (i = 0; i < 32; i++) |
442ea881 | 607 | supply_register (regcache, ev0 + i, ®set->evr[i]); |
30ed0a8f | 608 | |
442ea881 PA |
609 | supply_register_by_name (regcache, "acc", ®set->acc); |
610 | supply_register_by_name (regcache, "spefscr", ®set->spefscr); | |
30ed0a8f | 611 | } |
30ed0a8f | 612 | |
7d00775e AT |
613 | /* Support for hardware single step. */ |
614 | ||
615 | static int | |
616 | ppc_supports_hardware_single_step (void) | |
617 | { | |
618 | return 1; | |
619 | } | |
620 | ||
3aee8918 | 621 | static struct regset_info ppc_regsets[] = { |
30ed0a8f DJ |
622 | /* List the extra register sets before GENERAL_REGS. That way we will |
623 | fetch them every time, but still fall back to PTRACE_PEEKUSER for the | |
624 | general registers. Some kernels support these, but not the newer | |
625 | PPC_PTRACE_GETREGS. */ | |
1570b33e | 626 | { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, SIZEOF_VSXREGS, EXTENDED_REGS, |
677c5bb1 | 627 | ppc_fill_vsxregset, ppc_store_vsxregset }, |
1570b33e | 628 | { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, SIZEOF_VRREGS, EXTENDED_REGS, |
30ed0a8f | 629 | ppc_fill_vrregset, ppc_store_vrregset }, |
1570b33e | 630 | { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 32 * 4 + 8 + 4, EXTENDED_REGS, |
30ed0a8f | 631 | ppc_fill_evrregset, ppc_store_evrregset }, |
1570b33e | 632 | { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL }, |
50bc912a | 633 | NULL_REGSET |
e9d25b98 DJ |
634 | }; |
635 | ||
3aee8918 PA |
636 | static struct usrregs_info ppc_usrregs_info = |
637 | { | |
638 | ppc_num_regs, | |
639 | ppc_regmap, | |
640 | }; | |
641 | ||
642 | static struct regsets_info ppc_regsets_info = | |
643 | { | |
644 | ppc_regsets, /* regsets */ | |
645 | 0, /* num_regsets */ | |
646 | NULL, /* disabled_regsets */ | |
647 | }; | |
648 | ||
649 | static struct regs_info regs_info = | |
650 | { | |
651 | NULL, /* regset_bitmap */ | |
652 | &ppc_usrregs_info, | |
653 | &ppc_regsets_info | |
654 | }; | |
655 | ||
656 | static const struct regs_info * | |
657 | ppc_regs_info (void) | |
658 | { | |
659 | return ®s_info; | |
660 | } | |
661 | ||
e6c5bb05 SM |
662 | static void |
663 | ppc_arch_setup (void) | |
664 | { | |
665 | const struct target_desc *tdesc; | |
666 | #ifdef __powerpc64__ | |
667 | long msr; | |
668 | struct regcache *regcache; | |
669 | ||
670 | /* On a 64-bit host, assume 64-bit inferior process with no | |
671 | AltiVec registers. Reset ppc_hwcap to ensure that the | |
672 | collect_register call below does not fail. */ | |
673 | tdesc = tdesc_powerpc_64l; | |
674 | current_process ()->tdesc = tdesc; | |
675 | ppc_hwcap = 0; | |
676 | ||
677 | regcache = new_register_cache (tdesc); | |
678 | fetch_inferior_registers (regcache, find_regno (tdesc, "msr")); | |
679 | collect_register_by_name (regcache, "msr", &msr); | |
680 | free_register_cache (regcache); | |
681 | if (ppc64_64bit_inferior_p (msr)) | |
682 | { | |
683 | ppc_get_hwcap (&ppc_hwcap); | |
684 | if (ppc_hwcap & PPC_FEATURE_CELL) | |
685 | tdesc = tdesc_powerpc_cell64l; | |
686 | else if (ppc_hwcap & PPC_FEATURE_HAS_VSX) | |
687 | { | |
688 | /* Power ISA 2.05 (implemented by Power 6 and newer processors) | |
689 | increases the FPSCR from 32 bits to 64 bits. Even though Power 7 | |
690 | supports this ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 | |
691 | set, only PPC_FEATURE_ARCH_2_06. Since for now the only bits | |
692 | used in the higher half of the register are for Decimal Floating | |
693 | Point, we check if that feature is available to decide the size | |
694 | of the FPSCR. */ | |
695 | if (ppc_hwcap & PPC_FEATURE_HAS_DFP) | |
696 | tdesc = tdesc_powerpc_isa205_vsx64l; | |
697 | else | |
698 | tdesc = tdesc_powerpc_vsx64l; | |
699 | } | |
700 | else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC) | |
701 | { | |
702 | if (ppc_hwcap & PPC_FEATURE_HAS_DFP) | |
703 | tdesc = tdesc_powerpc_isa205_altivec64l; | |
704 | else | |
705 | tdesc = tdesc_powerpc_altivec64l; | |
706 | } | |
707 | ||
708 | current_process ()->tdesc = tdesc; | |
709 | return; | |
710 | } | |
711 | #endif | |
712 | ||
713 | /* OK, we have a 32-bit inferior. */ | |
714 | tdesc = tdesc_powerpc_32l; | |
715 | current_process ()->tdesc = tdesc; | |
716 | ||
717 | ppc_get_hwcap (&ppc_hwcap); | |
718 | if (ppc_hwcap & PPC_FEATURE_CELL) | |
719 | tdesc = tdesc_powerpc_cell32l; | |
720 | else if (ppc_hwcap & PPC_FEATURE_HAS_VSX) | |
721 | { | |
722 | if (ppc_hwcap & PPC_FEATURE_HAS_DFP) | |
723 | tdesc = tdesc_powerpc_isa205_vsx32l; | |
724 | else | |
725 | tdesc = tdesc_powerpc_vsx32l; | |
726 | } | |
727 | else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC) | |
728 | { | |
729 | if (ppc_hwcap & PPC_FEATURE_HAS_DFP) | |
730 | tdesc = tdesc_powerpc_isa205_altivec32l; | |
731 | else | |
732 | tdesc = tdesc_powerpc_altivec32l; | |
733 | } | |
734 | ||
735 | /* On 32-bit machines, check for SPE registers. | |
736 | Set the low target's regmap field as appropriately. */ | |
737 | #ifndef __powerpc64__ | |
738 | if (ppc_hwcap & PPC_FEATURE_HAS_SPE) | |
739 | tdesc = tdesc_powerpc_e500l; | |
740 | ||
741 | if (!ppc_regmap_adjusted) | |
742 | { | |
743 | if (ppc_hwcap & PPC_FEATURE_HAS_SPE) | |
744 | ppc_usrregs_info.regmap = ppc_regmap_e500; | |
745 | ||
746 | /* If the FPSCR is 64-bit wide, we need to fetch the whole | |
747 | 64-bit slot and not just its second word. The PT_FPSCR | |
748 | supplied in a 32-bit GDB compilation doesn't reflect | |
749 | this. */ | |
750 | if (register_size (tdesc, 70) == 8) | |
751 | ppc_regmap[70] = (48 + 2*32) * sizeof (long); | |
752 | ||
753 | ppc_regmap_adjusted = 1; | |
754 | } | |
755 | #endif | |
756 | current_process ()->tdesc = tdesc; | |
757 | } | |
758 | ||
2ec06d2e | 759 | struct linux_target_ops the_low_target = { |
6fe305f7 | 760 | ppc_arch_setup, |
3aee8918 | 761 | ppc_regs_info, |
2ec06d2e DJ |
762 | ppc_cannot_fetch_register, |
763 | ppc_cannot_store_register, | |
c14dfd32 | 764 | NULL, /* fetch_register */ |
0d62e5e8 DJ |
765 | ppc_get_pc, |
766 | ppc_set_pc, | |
dd373349 AT |
767 | NULL, /* breakpoint_kind_from_pc */ |
768 | ppc_sw_breakpoint_from_kind, | |
0d62e5e8 DJ |
769 | NULL, |
770 | 0, | |
771 | ppc_breakpoint_at, | |
657f9cde WW |
772 | ppc_supports_z_point_type, |
773 | ppc_insert_point, | |
774 | ppc_remove_point, | |
5b0a002e UW |
775 | NULL, |
776 | NULL, | |
777 | ppc_collect_ptrace_register, | |
778 | ppc_supply_ptrace_register, | |
7d00775e AT |
779 | NULL, /* siginfo_fixup */ |
780 | NULL, /* new_process */ | |
781 | NULL, /* new_thread */ | |
782 | NULL, /* new_fork */ | |
783 | NULL, /* prepare_to_resume */ | |
784 | NULL, /* process_qsupported */ | |
785 | NULL, /* supports_tracepoints */ | |
786 | NULL, /* get_thread_area */ | |
787 | NULL, /* install_fast_tracepoint_jump_pad */ | |
788 | NULL, /* emit_ops */ | |
789 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
790 | NULL, /* supports_range_stepping */ | |
791 | NULL, /* breakpoint_kind_from_current_state */ | |
792 | ppc_supports_hardware_single_step, | |
2ec06d2e | 793 | }; |
3aee8918 PA |
794 | |
795 | void | |
796 | initialize_low_arch (void) | |
797 | { | |
798 | /* Initialize the Linux target descriptions. */ | |
799 | ||
800 | init_registers_powerpc_32l (); | |
801 | init_registers_powerpc_altivec32l (); | |
802 | init_registers_powerpc_cell32l (); | |
803 | init_registers_powerpc_vsx32l (); | |
804 | init_registers_powerpc_isa205_32l (); | |
805 | init_registers_powerpc_isa205_altivec32l (); | |
806 | init_registers_powerpc_isa205_vsx32l (); | |
807 | init_registers_powerpc_e500l (); | |
808 | init_registers_powerpc_64l (); | |
809 | init_registers_powerpc_altivec64l (); | |
810 | init_registers_powerpc_cell64l (); | |
811 | init_registers_powerpc_vsx64l (); | |
812 | init_registers_powerpc_isa205_64l (); | |
813 | init_registers_powerpc_isa205_altivec64l (); | |
814 | init_registers_powerpc_isa205_vsx64l (); | |
815 | ||
816 | initialize_regsets_info (&ppc_regsets_info); | |
817 | } |