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[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-x86-low.c
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d0722149
DE		 1/* GNU/Linux/x86-64 specific low level interface, for the remote server
2 for GDB.
618f726f 3 Copyright (C) 2002-2016 Free Software Foundation, Inc.
d0722149
DE		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
d41f6d8e 20#include "server.h"
d0722149 21#include <signal.h>
6a271cae 22#include <limits.h>
f4647387 23#include <inttypes.h>
d0722149
DE		 24#include "linux-low.h"
25#include "i387-fp.h"
df7e5265
GB		 26#include "x86-low.h"
27#include "x86-xstate.h"
5826e159 28#include "nat/gdb_ptrace.h"
d0722149
DE		 29
30#include "gdb_proc_service.h"
b5737fa9
PA		 31/* Don't include elf/common.h if linux/elf.h got included by
32 gdb_proc_service.h. */
33#ifndef ELFMAG0
34#include "elf/common.h"
35#endif
36
58b4daa5 37#include "agent.h"
3aee8918 38#include "tdesc.h"
c144c7a0 39#include "tracepoint.h"
f699aaba 40#include "ax.h"
7b669087 41#include "nat/linux-nat.h"
4b134ca1 42#include "nat/x86-linux.h"
8e5d4070 43#include "nat/x86-linux-dregs.h"
d0722149 44
3aee8918 45#ifdef __x86_64__
90884b2b
L		 46/* Defined in auto-generated file amd64-linux.c. */
47void init_registers_amd64_linux (void);
3aee8918
PA		 48extern const struct target_desc *tdesc_amd64_linux;
49
1570b33e
L		 50/* Defined in auto-generated file amd64-avx-linux.c. */
51void init_registers_amd64_avx_linux (void);
3aee8918
PA		 52extern const struct target_desc *tdesc_amd64_avx_linux;
53
01f9f808
MS		 54/* Defined in auto-generated file amd64-avx512-linux.c. */
55void init_registers_amd64_avx512_linux (void);
56extern const struct target_desc *tdesc_amd64_avx512_linux;
57
a196ebeb
WT		 58/* Defined in auto-generated file amd64-mpx-linux.c. */
59void init_registers_amd64_mpx_linux (void);
60extern const struct target_desc *tdesc_amd64_mpx_linux;
61
4d47af5c
L		 62/* Defined in auto-generated file x32-linux.c. */
63void init_registers_x32_linux (void);
3aee8918
PA		 64extern const struct target_desc *tdesc_x32_linux;
65
4d47af5c
L		 66/* Defined in auto-generated file x32-avx-linux.c. */
67void init_registers_x32_avx_linux (void);
3aee8918 68extern const struct target_desc *tdesc_x32_avx_linux;
a196ebeb 69
01f9f808
MS		 70/* Defined in auto-generated file x32-avx512-linux.c. */
71void init_registers_x32_avx512_linux (void);
72extern const struct target_desc *tdesc_x32_avx512_linux;
73
3aee8918
PA		 74#endif
75
76/* Defined in auto-generated file i386-linux.c. */
77void init_registers_i386_linux (void);
78extern const struct target_desc *tdesc_i386_linux;
79
80/* Defined in auto-generated file i386-mmx-linux.c. */
81void init_registers_i386_mmx_linux (void);
82extern const struct target_desc *tdesc_i386_mmx_linux;
83
84/* Defined in auto-generated file i386-avx-linux.c. */
85void init_registers_i386_avx_linux (void);
86extern const struct target_desc *tdesc_i386_avx_linux;
87
01f9f808
MS		 88/* Defined in auto-generated file i386-avx512-linux.c. */
89void init_registers_i386_avx512_linux (void);
90extern const struct target_desc *tdesc_i386_avx512_linux;
91
a196ebeb
WT		 92/* Defined in auto-generated file i386-mpx-linux.c. */
93void init_registers_i386_mpx_linux (void);
94extern const struct target_desc *tdesc_i386_mpx_linux;
95
3aee8918
PA		 96#ifdef __x86_64__
97static struct target_desc *tdesc_amd64_linux_no_xml;
98#endif
99static struct target_desc *tdesc_i386_linux_no_xml;
100
1570b33e 101
fa593d66 102static unsigned char jump_insn[] = { 0xe9, 0, 0, 0, 0 };
405f8e94 103static unsigned char small_jump_insn[] = { 0x66, 0xe9, 0, 0 };
fa593d66 104
1570b33e
L		 105/* Backward compatibility for gdb without XML support. */
106
107static const char *xmltarget_i386_linux_no_xml = "@<target>\
108<architecture>i386</architecture>\
109<osabi>GNU/Linux</osabi>\
110</target>";
f6d1620c
L		 111
112#ifdef __x86_64__
1570b33e
L		 113static const char *xmltarget_amd64_linux_no_xml = "@<target>\
114<architecture>i386:x86-64</architecture>\
115<osabi>GNU/Linux</osabi>\
116</target>";
f6d1620c 117#endif
d0722149
DE		 118
119#include <sys/reg.h>
120#include <sys/procfs.h>
5826e159 121#include "nat/gdb_ptrace.h"
1570b33e
L		 122#include <sys/uio.h>
123
d0722149
DE		 124#ifndef PTRACE_GET_THREAD_AREA
125#define PTRACE_GET_THREAD_AREA 25
126#endif
127
128/* This definition comes from prctl.h, but some kernels may not have it. */
129#ifndef PTRACE_ARCH_PRCTL
130#define PTRACE_ARCH_PRCTL 30
131#endif
132
133/* The following definitions come from prctl.h, but may be absent
134 for certain configurations. */
135#ifndef ARCH_GET_FS
136#define ARCH_SET_GS 0x1001
137#define ARCH_SET_FS 0x1002
138#define ARCH_GET_FS 0x1003
139#define ARCH_GET_GS 0x1004
140#endif
141
aa5ca48f
DE		 142/* Per-process arch-specific data we want to keep. */
143
144struct arch_process_info
145{
df7e5265 146 struct x86_debug_reg_state debug_reg_state;
aa5ca48f
DE		 147};
148
d0722149
DE		 149#ifdef __x86_64__
150
151/* Mapping between the general-purpose registers in `struct user'
152 format and GDB's register array layout.
153 Note that the transfer layout uses 64-bit regs. */
154static /*const*/ int i386_regmap[] =
155{
156 RAX * 8, RCX * 8, RDX * 8, RBX * 8,
157 RSP * 8, RBP * 8, RSI * 8, RDI * 8,
158 RIP * 8, EFLAGS * 8, CS * 8, SS * 8,
159 DS * 8, ES * 8, FS * 8, GS * 8
160};
161
162#define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
163
164/* So code below doesn't have to care, i386 or amd64. */
165#define ORIG_EAX ORIG_RAX
bc9540e8 166#define REGSIZE 8
d0722149
DE		 167
168static const int x86_64_regmap[] =
169{
170 RAX * 8, RBX * 8, RCX * 8, RDX * 8,
171 RSI * 8, RDI * 8, RBP * 8, RSP * 8,
172 R8 * 8, R9 * 8, R10 * 8, R11 * 8,
173 R12 * 8, R13 * 8, R14 * 8, R15 * 8,
174 RIP * 8, EFLAGS * 8, CS * 8, SS * 8,
175 DS * 8, ES * 8, FS * 8, GS * 8,
176 -1, -1, -1, -1, -1, -1, -1, -1,
177 -1, -1, -1, -1, -1, -1, -1, -1,
178 -1, -1, -1, -1, -1, -1, -1, -1,
a196ebeb
WT		 179 -1,
180 -1, -1, -1, -1, -1, -1, -1, -1,
181 ORIG_RAX * 8,
182 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
01f9f808
MS		 183 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
184 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
185 -1, -1, -1, -1, -1, -1, -1, -1,
186 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
187 -1, -1, -1, -1, -1, -1, -1, -1,
188 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
189 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
190 -1, -1, -1, -1, -1, -1, -1, -1,
191 -1, -1, -1, -1, -1, -1, -1, -1,
192 -1, -1, -1, -1, -1, -1, -1, -1
d0722149
DE		 193};
194
195#define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
9e0aa64f 196#define X86_64_USER_REGS (GS + 1)
d0722149
DE		 197
198#else /* ! __x86_64__ */
199
200/* Mapping between the general-purpose registers in `struct user'
201 format and GDB's register array layout. */
202static /*const*/ int i386_regmap[] =
203{
204 EAX * 4, ECX * 4, EDX * 4, EBX * 4,
205 UESP * 4, EBP * 4, ESI * 4, EDI * 4,
206 EIP * 4, EFL * 4, CS * 4, SS * 4,
207 DS * 4, ES * 4, FS * 4, GS * 4
208};
209
210#define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
211
bc9540e8
PA		 212#define REGSIZE 4
213
d0722149 214#endif
3aee8918
PA		 215
216#ifdef __x86_64__
217
218/* Returns true if the current inferior belongs to a x86-64 process,
219 per the tdesc. */
220
221static int
222is_64bit_tdesc (void)
223{
0bfdf32f 224 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3aee8918
PA		 225
226 return register_size (regcache->tdesc, 0) == 8;
227}
228
229#endif
230
d0722149
DE		 231\f
232/* Called by libthread_db. */
233
234ps_err_e
235ps_get_thread_area (const struct ps_prochandle *ph,
236 lwpid_t lwpid, int idx, void **base)
237{
238#ifdef __x86_64__
3aee8918 239 int use_64bit = is_64bit_tdesc ();
d0722149
DE		 240
241 if (use_64bit)
242 {
243 switch (idx)
244 {
245 case FS:
246 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_FS) == 0)
247 return PS_OK;
248 break;
249 case GS:
250 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_GS) == 0)
251 return PS_OK;
252 break;
253 default:
254 return PS_BADADDR;
255 }
256 return PS_ERR;
257 }
258#endif
259
260 {
261 unsigned int desc[4];
262
263 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid,
264 (void *) (intptr_t) idx, (unsigned long) &desc) < 0)
265 return PS_ERR;
266
d1ec4ce7
DE		 267 /* Ensure we properly extend the value to 64-bits for x86_64. */
268 *base = (void *) (uintptr_t) desc[1];
d0722149
DE		 269 return PS_OK;
270 }
271}
fa593d66
PA		 272
273/* Get the thread area address. This is used to recognize which
274 thread is which when tracing with the in-process agent library. We
275 don't read anything from the address, and treat it as opaque; it's
276 the address itself that we assume is unique per-thread. */
277
278static int
279x86_get_thread_area (int lwpid, CORE_ADDR *addr)
280{
281#ifdef __x86_64__
3aee8918 282 int use_64bit = is_64bit_tdesc ();
fa593d66
PA		 283
284 if (use_64bit)
285 {
286 void *base;
287 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_FS) == 0)
288 {
289 *addr = (CORE_ADDR) (uintptr_t) base;
290 return 0;
291 }
292
293 return -1;
294 }
295#endif
296
297 {
298 struct lwp_info *lwp = find_lwp_pid (pid_to_ptid (lwpid));
d86d4aaf
DE		 299 struct thread_info *thr = get_lwp_thread (lwp);
300 struct regcache *regcache = get_thread_regcache (thr, 1);
fa593d66
PA		 301 unsigned int desc[4];
302 ULONGEST gs = 0;
303 const int reg_thread_area = 3; /* bits to scale down register value. */
304 int idx;
305
306 collect_register_by_name (regcache, "gs", &gs);
307
308 idx = gs >> reg_thread_area;
309
310 if (ptrace (PTRACE_GET_THREAD_AREA,
d86d4aaf 311 lwpid_of (thr),
493e2a69 312 (void *) (long) idx, (unsigned long) &desc) < 0)
fa593d66
PA		 313 return -1;
314
315 *addr = desc[1];
316 return 0;
317 }
318}
319
320
d0722149
DE		 321\f
322static int
3aee8918 323x86_cannot_store_register (int regno)
d0722149 324{
3aee8918
PA		 325#ifdef __x86_64__
326 if (is_64bit_tdesc ())
327 return 0;
328#endif
329
d0722149
DE		 330 return regno >= I386_NUM_REGS;
331}
332
333static int
3aee8918 334x86_cannot_fetch_register (int regno)
d0722149 335{
3aee8918
PA		 336#ifdef __x86_64__
337 if (is_64bit_tdesc ())
338 return 0;
339#endif
340
d0722149
DE		 341 return regno >= I386_NUM_REGS;
342}
343
344static void
442ea881 345x86_fill_gregset (struct regcache *regcache, void *buf)
d0722149
DE		 346{
347 int i;
348
349#ifdef __x86_64__
3aee8918 350 if (register_size (regcache->tdesc, 0) == 8)
d0722149
DE		 351 {
352 for (i = 0; i < X86_64_NUM_REGS; i++)
353 if (x86_64_regmap[i] != -1)
442ea881 354 collect_register (regcache, i, ((char *) buf) + x86_64_regmap[i]);
d0722149
DE		 355 return;
356 }
9e0aa64f
JK		 357
358 /* 32-bit inferior registers need to be zero-extended.
359 Callers would read uninitialized memory otherwise. */
360 memset (buf, 0x00, X86_64_USER_REGS * 8);
d0722149
DE		 361#endif
362
363 for (i = 0; i < I386_NUM_REGS; i++)
442ea881 364 collect_register (regcache, i, ((char *) buf) + i386_regmap[i]);
d0722149 365
442ea881 366 collect_register_by_name (regcache, "orig_eax",
bc9540e8 367 ((char *) buf) + ORIG_EAX * REGSIZE);
d0722149
DE		 368}
369
370static void
442ea881 371x86_store_gregset (struct regcache *regcache, const void *buf)
d0722149
DE		 372{
373 int i;
374
375#ifdef __x86_64__
3aee8918 376 if (register_size (regcache->tdesc, 0) == 8)
d0722149
DE		 377 {
378 for (i = 0; i < X86_64_NUM_REGS; i++)
379 if (x86_64_regmap[i] != -1)
442ea881 380 supply_register (regcache, i, ((char *) buf) + x86_64_regmap[i]);
d0722149
DE		 381 return;
382 }
383#endif
384
385 for (i = 0; i < I386_NUM_REGS; i++)
442ea881 386 supply_register (regcache, i, ((char *) buf) + i386_regmap[i]);
d0722149 387
442ea881 388 supply_register_by_name (regcache, "orig_eax",
bc9540e8 389 ((char *) buf) + ORIG_EAX * REGSIZE);
d0722149
DE		 390}
391
392static void
442ea881 393x86_fill_fpregset (struct regcache *regcache, void *buf)
d0722149
DE		 394{
395#ifdef __x86_64__
442ea881 396 i387_cache_to_fxsave (regcache, buf);
d0722149 397#else
442ea881 398 i387_cache_to_fsave (regcache, buf);
d0722149
DE		 399#endif
400}
401
402static void
442ea881 403x86_store_fpregset (struct regcache *regcache, const void *buf)
d0722149
DE		 404{
405#ifdef __x86_64__
442ea881 406 i387_fxsave_to_cache (regcache, buf);
d0722149 407#else
442ea881 408 i387_fsave_to_cache (regcache, buf);
d0722149
DE		 409#endif
410}
411
412#ifndef __x86_64__
413
414static void
442ea881 415x86_fill_fpxregset (struct regcache *regcache, void *buf)
d0722149 416{
442ea881 417 i387_cache_to_fxsave (regcache, buf);
d0722149
DE		 418}
419
420static void
442ea881 421x86_store_fpxregset (struct regcache *regcache, const void *buf)
d0722149 422{
442ea881 423 i387_fxsave_to_cache (regcache, buf);
d0722149
DE		 424}
425
426#endif
427
1570b33e
L		 428static void
429x86_fill_xstateregset (struct regcache *regcache, void *buf)
430{
431 i387_cache_to_xsave (regcache, buf);
432}
433
434static void
435x86_store_xstateregset (struct regcache *regcache, const void *buf)
436{
437 i387_xsave_to_cache (regcache, buf);
438}
439
d0722149
DE		 440/* ??? The non-biarch i386 case stores all the i387 regs twice.
441 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
442 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
443 doesn't work. IWBN to avoid the duplication in the case where it
444 does work. Maybe the arch_setup routine could check whether it works
3aee8918 445 and update the supported regsets accordingly. */
d0722149 446
3aee8918 447static struct regset_info x86_regsets[] =
d0722149
DE		 448{
449#ifdef HAVE_PTRACE_GETREGS
1570b33e 450 { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t),
d0722149
DE		 451 GENERAL_REGS,
452 x86_fill_gregset, x86_store_gregset },
1570b33e
L		 453 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_X86_XSTATE, 0,
454 EXTENDED_REGS, x86_fill_xstateregset, x86_store_xstateregset },
d0722149
DE		 455# ifndef __x86_64__
456# ifdef HAVE_PTRACE_GETFPXREGS
1570b33e 457 { PTRACE_GETFPXREGS, PTRACE_SETFPXREGS, 0, sizeof (elf_fpxregset_t),
d0722149
DE		 458 EXTENDED_REGS,
459 x86_fill_fpxregset, x86_store_fpxregset },
460# endif
461# endif
1570b33e 462 { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, sizeof (elf_fpregset_t),
d0722149
DE		 463 FP_REGS,
464 x86_fill_fpregset, x86_store_fpregset },
465#endif /* HAVE_PTRACE_GETREGS */
50bc912a 466 NULL_REGSET
d0722149
DE		 467};
468
469static CORE_ADDR
442ea881 470x86_get_pc (struct regcache *regcache)
d0722149 471{
3aee8918 472 int use_64bit = register_size (regcache->tdesc, 0) == 8;
d0722149
DE		 473
474 if (use_64bit)
475 {
476 unsigned long pc;
442ea881 477 collect_register_by_name (regcache, "rip", &pc);
d0722149
DE		 478 return (CORE_ADDR) pc;
479 }
480 else
481 {
482 unsigned int pc;
442ea881 483 collect_register_by_name (regcache, "eip", &pc);
d0722149
DE		 484 return (CORE_ADDR) pc;
485 }
486}
487
488static void
442ea881 489x86_set_pc (struct regcache *regcache, CORE_ADDR pc)
d0722149 490{
3aee8918 491 int use_64bit = register_size (regcache->tdesc, 0) == 8;
d0722149
DE		 492
493 if (use_64bit)
494 {
495 unsigned long newpc = pc;
442ea881 496 supply_register_by_name (regcache, "rip", &newpc);
d0722149
DE		 497 }
498 else
499 {
500 unsigned int newpc = pc;
442ea881 501 supply_register_by_name (regcache, "eip", &newpc);
d0722149
DE		 502 }
503}
504\f
dd373349 505static const gdb_byte x86_breakpoint[] = { 0xCC };
d0722149
DE		 506#define x86_breakpoint_len 1
507
508static int
509x86_breakpoint_at (CORE_ADDR pc)
510{
511 unsigned char c;
512
fc7238bb 513 (*the_target->read_memory) (pc, &c, 1);
d0722149
DE		 514 if (c == 0xCC)
515 return 1;
516
517 return 0;
518}
519\f
42995dbd 520/* Low-level function vector. */
df7e5265 521struct x86_dr_low_type x86_dr_low =
42995dbd 522 {
d33472ad
GB		 523 x86_linux_dr_set_control,
524 x86_linux_dr_set_addr,
525 x86_linux_dr_get_addr,
526 x86_linux_dr_get_status,
527 x86_linux_dr_get_control,
42995dbd
GB		 528 sizeof (void *),
529 };
aa5ca48f 530\f
90d74c30 531/* Breakpoint/Watchpoint support. */
aa5ca48f
DE		 532
533static int
802e8e6d
PA		 534x86_supports_z_point_type (char z_type)
535{
536 switch (z_type)
537 {
538 case Z_PACKET_SW_BP:
539 case Z_PACKET_HW_BP:
540 case Z_PACKET_WRITE_WP:
541 case Z_PACKET_ACCESS_WP:
542 return 1;
543 default:
544 return 0;
545 }
546}
547
548static int
549x86_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
550 int size, struct raw_breakpoint *bp)
aa5ca48f
DE		 551{
552 struct process_info *proc = current_process ();
802e8e6d 553
aa5ca48f
DE		 554 switch (type)
555 {
802e8e6d
PA		 556 case raw_bkpt_type_hw:
557 case raw_bkpt_type_write_wp:
558 case raw_bkpt_type_access_wp:
a4165e94 559 {
802e8e6d
PA		 560 enum target_hw_bp_type hw_type
561 = raw_bkpt_type_to_target_hw_bp_type (type);
df7e5265 562 struct x86_debug_reg_state *state
fe978cb0 563 = &proc->priv->arch_private->debug_reg_state;
a4165e94 564
df7e5265 565 return x86_dr_insert_watchpoint (state, hw_type, addr, size);
a4165e94 566 }
961bd387 567
aa5ca48f
DE		 568 default:
569 /* Unsupported. */
570 return 1;
571 }
572}
573
574static int
802e8e6d
PA		 575x86_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
576 int size, struct raw_breakpoint *bp)
aa5ca48f
DE		 577{
578 struct process_info *proc = current_process ();
802e8e6d 579
aa5ca48f
DE		 580 switch (type)
581 {
802e8e6d
PA		 582 case raw_bkpt_type_hw:
583 case raw_bkpt_type_write_wp:
584 case raw_bkpt_type_access_wp:
a4165e94 585 {
802e8e6d
PA		 586 enum target_hw_bp_type hw_type
587 = raw_bkpt_type_to_target_hw_bp_type (type);
df7e5265 588 struct x86_debug_reg_state *state
fe978cb0 589 = &proc->priv->arch_private->debug_reg_state;
a4165e94 590
df7e5265 591 return x86_dr_remove_watchpoint (state, hw_type, addr, size);
a4165e94 592 }
aa5ca48f
DE		 593 default:
594 /* Unsupported. */
595 return 1;
596 }
597}
598
599static int
600x86_stopped_by_watchpoint (void)
601{
602 struct process_info *proc = current_process ();
fe978cb0 603 return x86_dr_stopped_by_watchpoint (&proc->priv->arch_private->debug_reg_state);
aa5ca48f
DE		 604}
605
606static CORE_ADDR
607x86_stopped_data_address (void)
608{
609 struct process_info *proc = current_process ();
610 CORE_ADDR addr;
fe978cb0 611 if (x86_dr_stopped_data_address (&proc->priv->arch_private->debug_reg_state,
df7e5265 612 &addr))
aa5ca48f
DE		 613 return addr;
614 return 0;
615}
616\f
617/* Called when a new process is created. */
618
619static struct arch_process_info *
620x86_linux_new_process (void)
621{
ed859da7 622 struct arch_process_info *info = XCNEW (struct arch_process_info);
aa5ca48f 623
df7e5265 624 x86_low_init_dregs (&info->debug_reg_state);
aa5ca48f
DE		 625
626 return info;
627}
628
3a8a0396
DB		 629/* Target routine for linux_new_fork. */
630
631static void
632x86_linux_new_fork (struct process_info *parent, struct process_info *child)
633{
634 /* These are allocated by linux_add_process. */
635 gdb_assert (parent->priv != NULL
636 && parent->priv->arch_private != NULL);
637 gdb_assert (child->priv != NULL
638 && child->priv->arch_private != NULL);
639
640 /* Linux kernel before 2.6.33 commit
641 72f674d203cd230426437cdcf7dd6f681dad8b0d
642 will inherit hardware debug registers from parent
643 on fork/vfork/clone. Newer Linux kernels create such tasks with
644 zeroed debug registers.
645
646 GDB core assumes the child inherits the watchpoints/hw
647 breakpoints of the parent, and will remove them all from the
648 forked off process. Copy the debug registers mirrors into the
649 new process so that all breakpoints and watchpoints can be
650 removed together. The debug registers mirror will become zeroed
651 in the end before detaching the forked off process, thus making
652 this compatible with older Linux kernels too. */
653
654 *child->priv->arch_private = *parent->priv->arch_private;
655}
656
70a0bb6b
GB		 657/* See nat/x86-dregs.h. */
658
659struct x86_debug_reg_state *
660x86_debug_reg_state (pid_t pid)
661{
662 struct process_info *proc = find_process_pid (pid);
663
664 return &proc->priv->arch_private->debug_reg_state;
665}
aa5ca48f 666\f
d0722149
DE		 667/* When GDBSERVER is built as a 64-bit application on linux, the
668 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
669 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
670 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
671 conversion in-place ourselves. */
672
673/* These types below (compat_*) define a siginfo type that is layout
674 compatible with the siginfo type exported by the 32-bit userspace
675 support. */
676
677#ifdef __x86_64__
678
679typedef int compat_int_t;
680typedef unsigned int compat_uptr_t;
681
682typedef int compat_time_t;
683typedef int compat_timer_t;
684typedef int compat_clock_t;
685
686struct compat_timeval
687{
688 compat_time_t tv_sec;
689 int tv_usec;
690};
691
692typedef union compat_sigval
693{
694 compat_int_t sival_int;
695 compat_uptr_t sival_ptr;
696} compat_sigval_t;
697
698typedef struct compat_siginfo
699{
700 int si_signo;
701 int si_errno;
702 int si_code;
703
704 union
705 {
706 int _pad[((128 / sizeof (int)) - 3)];
707
708 /* kill() */
709 struct
710 {
711 unsigned int _pid;
712 unsigned int _uid;
713 } _kill;
714
715 /* POSIX.1b timers */
716 struct
717 {
718 compat_timer_t _tid;
719 int _overrun;
720 compat_sigval_t _sigval;
721 } _timer;
722
723 /* POSIX.1b signals */
724 struct
725 {
726 unsigned int _pid;
727 unsigned int _uid;
728 compat_sigval_t _sigval;
729 } _rt;
730
731 /* SIGCHLD */
732 struct
733 {
734 unsigned int _pid;
735 unsigned int _uid;
736 int _status;
737 compat_clock_t _utime;
738 compat_clock_t _stime;
739 } _sigchld;
740
741 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
742 struct
743 {
744 unsigned int _addr;
745 } _sigfault;
746
747 /* SIGPOLL */
748 struct
749 {
750 int _band;
751 int _fd;
752 } _sigpoll;
753 } _sifields;
754} compat_siginfo_t;
755
c92b5177
L		 756/* For x32, clock_t in _sigchld is 64bit aligned at 4 bytes. */
757typedef long __attribute__ ((__aligned__ (4))) compat_x32_clock_t;
758
759typedef struct compat_x32_siginfo
760{
761 int si_signo;
762 int si_errno;
763 int si_code;
764
765 union
766 {
767 int _pad[((128 / sizeof (int)) - 3)];
768
769 /* kill() */
770 struct
771 {
772 unsigned int _pid;
773 unsigned int _uid;
774 } _kill;
775
776 /* POSIX.1b timers */
777 struct
778 {
779 compat_timer_t _tid;
780 int _overrun;
781 compat_sigval_t _sigval;
782 } _timer;
783
784 /* POSIX.1b signals */
785 struct
786 {
787 unsigned int _pid;
788 unsigned int _uid;
789 compat_sigval_t _sigval;
790 } _rt;
791
792 /* SIGCHLD */
793 struct
794 {
795 unsigned int _pid;
796 unsigned int _uid;
797 int _status;
798 compat_x32_clock_t _utime;
799 compat_x32_clock_t _stime;
800 } _sigchld;
801
802 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
803 struct
804 {
805 unsigned int _addr;
806 } _sigfault;
807
808 /* SIGPOLL */
809 struct
810 {
811 int _band;
812 int _fd;
813 } _sigpoll;
814 } _sifields;
815} compat_x32_siginfo_t __attribute__ ((__aligned__ (8)));
816
d0722149
DE		 817#define cpt_si_pid _sifields._kill._pid
818#define cpt_si_uid _sifields._kill._uid
819#define cpt_si_timerid _sifields._timer._tid
820#define cpt_si_overrun _sifields._timer._overrun
821#define cpt_si_status _sifields._sigchld._status
822#define cpt_si_utime _sifields._sigchld._utime
823#define cpt_si_stime _sifields._sigchld._stime
824#define cpt_si_ptr _sifields._rt._sigval.sival_ptr
825#define cpt_si_addr _sifields._sigfault._addr
826#define cpt_si_band _sifields._sigpoll._band
827#define cpt_si_fd _sifields._sigpoll._fd
828
829/* glibc at least up to 2.3.2 doesn't have si_timerid, si_overrun.
830 In their place is si_timer1,si_timer2. */
831#ifndef si_timerid
832#define si_timerid si_timer1
833#endif
834#ifndef si_overrun
835#define si_overrun si_timer2
836#endif
837
838static void
839compat_siginfo_from_siginfo (compat_siginfo_t *to, siginfo_t *from)
840{
841 memset (to, 0, sizeof (*to));
842
843 to->si_signo = from->si_signo;
844 to->si_errno = from->si_errno;
845 to->si_code = from->si_code;
846
b53a1623 847 if (to->si_code == SI_TIMER)
d0722149 848 {
b53a1623
PA		 849 to->cpt_si_timerid = from->si_timerid;
850 to->cpt_si_overrun = from->si_overrun;
d0722149
DE		 851 to->cpt_si_ptr = (intptr_t) from->si_ptr;
852 }
853 else if (to->si_code == SI_USER)
854 {
855 to->cpt_si_pid = from->si_pid;
856 to->cpt_si_uid = from->si_uid;
857 }
b53a1623 858 else if (to->si_code < 0)
d0722149 859 {
b53a1623
PA		 860 to->cpt_si_pid = from->si_pid;
861 to->cpt_si_uid = from->si_uid;
d0722149
DE		 862 to->cpt_si_ptr = (intptr_t) from->si_ptr;
863 }
864 else
865 {
866 switch (to->si_signo)
867 {
868 case SIGCHLD:
869 to->cpt_si_pid = from->si_pid;
870 to->cpt_si_uid = from->si_uid;
871 to->cpt_si_status = from->si_status;
872 to->cpt_si_utime = from->si_utime;
873 to->cpt_si_stime = from->si_stime;
874 break;
875 case SIGILL:
876 case SIGFPE:
877 case SIGSEGV:
878 case SIGBUS:
879 to->cpt_si_addr = (intptr_t) from->si_addr;
880 break;
881 case SIGPOLL:
882 to->cpt_si_band = from->si_band;
883 to->cpt_si_fd = from->si_fd;
884 break;
885 default:
886 to->cpt_si_pid = from->si_pid;
887 to->cpt_si_uid = from->si_uid;
888 to->cpt_si_ptr = (intptr_t) from->si_ptr;
889 break;
890 }
891 }
892}
893
894static void
895siginfo_from_compat_siginfo (siginfo_t *to, compat_siginfo_t *from)
896{
897 memset (to, 0, sizeof (*to));
898
899 to->si_signo = from->si_signo;
900 to->si_errno = from->si_errno;
901 to->si_code = from->si_code;
902
b53a1623 903 if (to->si_code == SI_TIMER)
d0722149 904 {
b53a1623
PA		 905 to->si_timerid = from->cpt_si_timerid;
906 to->si_overrun = from->cpt_si_overrun;
d0722149
DE		 907 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
908 }
909 else if (to->si_code == SI_USER)
910 {
911 to->si_pid = from->cpt_si_pid;
912 to->si_uid = from->cpt_si_uid;
913 }
b53a1623 914 else if (to->si_code < 0)
d0722149 915 {
b53a1623
PA		 916 to->si_pid = from->cpt_si_pid;
917 to->si_uid = from->cpt_si_uid;
d0722149
DE		 918 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
919 }
920 else
921 {
922 switch (to->si_signo)
923 {
924 case SIGCHLD:
925 to->si_pid = from->cpt_si_pid;
926 to->si_uid = from->cpt_si_uid;
927 to->si_status = from->cpt_si_status;
928 to->si_utime = from->cpt_si_utime;
929 to->si_stime = from->cpt_si_stime;
930 break;
931 case SIGILL:
932 case SIGFPE:
933 case SIGSEGV:
934 case SIGBUS:
935 to->si_addr = (void *) (intptr_t) from->cpt_si_addr;
936 break;
937 case SIGPOLL:
938 to->si_band = from->cpt_si_band;
939 to->si_fd = from->cpt_si_fd;
940 break;
941 default:
942 to->si_pid = from->cpt_si_pid;
943 to->si_uid = from->cpt_si_uid;
944 to->si_ptr = (void* ) (intptr_t) from->cpt_si_ptr;
945 break;
946 }
947 }
948}
949
c92b5177
L		 950static void
951compat_x32_siginfo_from_siginfo (compat_x32_siginfo_t *to,
952 siginfo_t *from)
953{
954 memset (to, 0, sizeof (*to));
955
956 to->si_signo = from->si_signo;
957 to->si_errno = from->si_errno;
958 to->si_code = from->si_code;
959
960 if (to->si_code == SI_TIMER)
961 {
962 to->cpt_si_timerid = from->si_timerid;
963 to->cpt_si_overrun = from->si_overrun;
964 to->cpt_si_ptr = (intptr_t) from->si_ptr;
965 }
966 else if (to->si_code == SI_USER)
967 {
968 to->cpt_si_pid = from->si_pid;
969 to->cpt_si_uid = from->si_uid;
970 }
971 else if (to->si_code < 0)
972 {
973 to->cpt_si_pid = from->si_pid;
974 to->cpt_si_uid = from->si_uid;
975 to->cpt_si_ptr = (intptr_t) from->si_ptr;
976 }
977 else
978 {
979 switch (to->si_signo)
980 {
981 case SIGCHLD:
982 to->cpt_si_pid = from->si_pid;
983 to->cpt_si_uid = from->si_uid;
984 to->cpt_si_status = from->si_status;
985 to->cpt_si_utime = from->si_utime;
986 to->cpt_si_stime = from->si_stime;
987 break;
988 case SIGILL:
989 case SIGFPE:
990 case SIGSEGV:
991 case SIGBUS:
992 to->cpt_si_addr = (intptr_t) from->si_addr;
993 break;
994 case SIGPOLL:
995 to->cpt_si_band = from->si_band;
996 to->cpt_si_fd = from->si_fd;
997 break;
998 default:
999 to->cpt_si_pid = from->si_pid;
1000 to->cpt_si_uid = from->si_uid;
1001 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1002 break;
1003 }
1004 }
1005}
1006
1007static void
1008siginfo_from_compat_x32_siginfo (siginfo_t *to,
1009 compat_x32_siginfo_t *from)
1010{
1011 memset (to, 0, sizeof (*to));
1012
1013 to->si_signo = from->si_signo;
1014 to->si_errno = from->si_errno;
1015 to->si_code = from->si_code;
1016
1017 if (to->si_code == SI_TIMER)
1018 {
1019 to->si_timerid = from->cpt_si_timerid;
1020 to->si_overrun = from->cpt_si_overrun;
1021 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1022 }
1023 else if (to->si_code == SI_USER)
1024 {
1025 to->si_pid = from->cpt_si_pid;
1026 to->si_uid = from->cpt_si_uid;
1027 }
1028 else if (to->si_code < 0)
1029 {
1030 to->si_pid = from->cpt_si_pid;
1031 to->si_uid = from->cpt_si_uid;
1032 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1033 }
1034 else
1035 {
1036 switch (to->si_signo)
1037 {
1038 case SIGCHLD:
1039 to->si_pid = from->cpt_si_pid;
1040 to->si_uid = from->cpt_si_uid;
1041 to->si_status = from->cpt_si_status;
1042 to->si_utime = from->cpt_si_utime;
1043 to->si_stime = from->cpt_si_stime;
1044 break;
1045 case SIGILL:
1046 case SIGFPE:
1047 case SIGSEGV:
1048 case SIGBUS:
1049 to->si_addr = (void *) (intptr_t) from->cpt_si_addr;
1050 break;
1051 case SIGPOLL:
1052 to->si_band = from->cpt_si_band;
1053 to->si_fd = from->cpt_si_fd;
1054 break;
1055 default:
1056 to->si_pid = from->cpt_si_pid;
1057 to->si_uid = from->cpt_si_uid;
1058 to->si_ptr = (void* ) (intptr_t) from->cpt_si_ptr;
1059 break;
1060 }
1061 }
1062}
1063
d0722149
DE		 1064#endif /* __x86_64__ */
1065
1066/* Convert a native/host siginfo object, into/from the siginfo in the
1067 layout of the inferiors' architecture. Returns true if any
1068 conversion was done; false otherwise. If DIRECTION is 1, then copy
1069 from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to
1070 INF. */
1071
1072static int
a5362b9a 1073x86_siginfo_fixup (siginfo_t *native, void *inf, int direction)
d0722149
DE		 1074{
1075#ifdef __x86_64__
760256f9 1076 unsigned int machine;
0bfdf32f 1077 int tid = lwpid_of (current_thread);
760256f9
PA		 1078 int is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
1079
d0722149 1080 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
3aee8918 1081 if (!is_64bit_tdesc ())
d0722149 1082 {
38e08fca 1083 gdb_assert (sizeof (siginfo_t) == sizeof (compat_siginfo_t));
d0722149
DE		 1084
1085 if (direction == 0)
1086 compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, native);
1087 else
1088 siginfo_from_compat_siginfo (native, (struct compat_siginfo *) inf);
1089
c92b5177
L		 1090 return 1;
1091 }
1092 /* No fixup for native x32 GDB. */
760256f9 1093 else if (!is_elf64 && sizeof (void *) == 8)
c92b5177 1094 {
38e08fca 1095 gdb_assert (sizeof (siginfo_t) == sizeof (compat_x32_siginfo_t));
c92b5177
L		 1096
1097 if (direction == 0)
1098 compat_x32_siginfo_from_siginfo ((struct compat_x32_siginfo *) inf,
1099 native);
1100 else
1101 siginfo_from_compat_x32_siginfo (native,
1102 (struct compat_x32_siginfo *) inf);
1103
d0722149
DE		 1104 return 1;
1105 }
1106#endif
1107
1108 return 0;
1109}
1110\f
1570b33e
L		 1111static int use_xml;
1112
3aee8918
PA		 1113/* Format of XSAVE extended state is:
1114 struct
1115 {
1116 fxsave_bytes[0..463]
1117 sw_usable_bytes[464..511]
1118 xstate_hdr_bytes[512..575]
1119 avx_bytes[576..831]
1120 future_state etc
1121 };
1122
1123 Same memory layout will be used for the coredump NT_X86_XSTATE
1124 representing the XSAVE extended state registers.
1125
1126 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
1127 extended state mask, which is the same as the extended control register
1128 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
1129 together with the mask saved in the xstate_hdr_bytes to determine what
1130 states the processor/OS supports and what state, used or initialized,
1131 the process/thread is in. */
1132#define I386_LINUX_XSAVE_XCR0_OFFSET 464
1133
1134/* Does the current host support the GETFPXREGS request? The header
1135 file may or may not define it, and even if it is defined, the
1136 kernel will return EIO if it's running on a pre-SSE processor. */
1137int have_ptrace_getfpxregs =
1138#ifdef HAVE_PTRACE_GETFPXREGS
1139 -1
1140#else
1141 0
1142#endif
1143;
1570b33e 1144
3aee8918
PA		 1145/* Get Linux/x86 target description from running target. */
1146
1147static const struct target_desc *
1148x86_linux_read_description (void)
1570b33e 1149{
3aee8918
PA		 1150 unsigned int machine;
1151 int is_elf64;
a196ebeb 1152 int xcr0_features;
3aee8918
PA		 1153 int tid;
1154 static uint64_t xcr0;
3a13a53b 1155 struct regset_info *regset;
1570b33e 1156
0bfdf32f 1157 tid = lwpid_of (current_thread);
1570b33e 1158
3aee8918 1159 is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
45ba0d02 1160
3aee8918 1161 if (sizeof (void *) == 4)
3a13a53b 1162 {
3aee8918
PA		 1163 if (is_elf64 > 0)
1164 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
1165#ifndef __x86_64__
1166 else if (machine == EM_X86_64)
1167 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
1168#endif
1169 }
3a13a53b 1170
3aee8918
PA		 1171#if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
1172 if (machine == EM_386 && have_ptrace_getfpxregs == -1)
1173 {
1174 elf_fpxregset_t fpxregs;
3a13a53b 1175
3aee8918 1176 if (ptrace (PTRACE_GETFPXREGS, tid, 0, (long) &fpxregs) < 0)
3a13a53b 1177 {
3aee8918
PA		 1178 have_ptrace_getfpxregs = 0;
1179 have_ptrace_getregset = 0;
1180 return tdesc_i386_mmx_linux;
3a13a53b 1181 }
3aee8918
PA		 1182 else
1183 have_ptrace_getfpxregs = 1;
3a13a53b 1184 }
1570b33e
L		 1185#endif
1186
1187 if (!use_xml)
1188 {
df7e5265 1189 x86_xcr0 = X86_XSTATE_SSE_MASK;
3aee8918 1190
1570b33e
L		 1191 /* Don't use XML. */
1192#ifdef __x86_64__
3aee8918
PA		 1193 if (machine == EM_X86_64)
1194 return tdesc_amd64_linux_no_xml;
1570b33e 1195 else
1570b33e 1196#endif
3aee8918 1197 return tdesc_i386_linux_no_xml;
1570b33e
L		 1198 }
1199
1570b33e
L		 1200 if (have_ptrace_getregset == -1)
1201 {
df7e5265 1202 uint64_t xstateregs[(X86_XSTATE_SSE_SIZE / sizeof (uint64_t))];
1570b33e 1203 struct iovec iov;
1570b33e
L		 1204
1205 iov.iov_base = xstateregs;
1206 iov.iov_len = sizeof (xstateregs);
1207
1208 /* Check if PTRACE_GETREGSET works. */
3aee8918
PA		 1209 if (ptrace (PTRACE_GETREGSET, tid,
1210 (unsigned int) NT_X86_XSTATE, (long) &iov) < 0)
1211 have_ptrace_getregset = 0;
1212 else
1570b33e 1213 {
3aee8918
PA		 1214 have_ptrace_getregset = 1;
1215
1216 /* Get XCR0 from XSAVE extended state. */
1217 xcr0 = xstateregs[(I386_LINUX_XSAVE_XCR0_OFFSET
1218 / sizeof (uint64_t))];
1219
1220 /* Use PTRACE_GETREGSET if it is available. */
1221 for (regset = x86_regsets;
1222 regset->fill_function != NULL; regset++)
1223 if (regset->get_request == PTRACE_GETREGSET)
df7e5265 1224 regset->size = X86_XSTATE_SIZE (xcr0);
3aee8918
PA		 1225 else if (regset->type != GENERAL_REGS)
1226 regset->size = 0;
1570b33e 1227 }
1570b33e
L		 1228 }
1229
3aee8918 1230 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
a196ebeb 1231 xcr0_features = (have_ptrace_getregset
df7e5265 1232 && (xcr0 & X86_XSTATE_ALL_MASK));
3aee8918 1233
a196ebeb 1234 if (xcr0_features)
3aee8918 1235 x86_xcr0 = xcr0;
1570b33e 1236
3aee8918
PA		 1237 if (machine == EM_X86_64)
1238 {
1570b33e 1239#ifdef __x86_64__
a196ebeb 1240 if (is_elf64)
3aee8918 1241 {
a196ebeb
WT		 1242 if (xcr0_features)
1243 {
df7e5265 1244 switch (xcr0 & X86_XSTATE_ALL_MASK)
a196ebeb 1245 {
df7e5265 1246 case X86_XSTATE_AVX512_MASK:
01f9f808
MS		 1247 return tdesc_amd64_avx512_linux;
1248
df7e5265 1249 case X86_XSTATE_MPX_MASK:
a196ebeb
WT		 1250 return tdesc_amd64_mpx_linux;
1251
df7e5265 1252 case X86_XSTATE_AVX_MASK:
a196ebeb
WT		 1253 return tdesc_amd64_avx_linux;
1254
1255 default:
1256 return tdesc_amd64_linux;
1257 }
1258 }
4d47af5c 1259 else
a196ebeb 1260 return tdesc_amd64_linux;
3aee8918
PA		 1261 }
1262 else
1263 {
a196ebeb
WT		 1264 if (xcr0_features)
1265 {
df7e5265 1266 switch (xcr0 & X86_XSTATE_ALL_MASK)
a196ebeb 1267 {
df7e5265 1268 case X86_XSTATE_AVX512_MASK:
01f9f808
MS		 1269 return tdesc_x32_avx512_linux;
1270
df7e5265
GB		 1271 case X86_XSTATE_MPX_MASK: /* No MPX on x32. */
1272 case X86_XSTATE_AVX_MASK:
a196ebeb
WT		 1273 return tdesc_x32_avx_linux;
1274
1275 default:
1276 return tdesc_x32_linux;
1277 }
1278 }
3aee8918 1279 else
a196ebeb 1280 return tdesc_x32_linux;
1570b33e 1281 }
3aee8918 1282#endif
1570b33e 1283 }
3aee8918
PA		 1284 else
1285 {
a196ebeb
WT		 1286 if (xcr0_features)
1287 {
df7e5265 1288 switch (xcr0 & X86_XSTATE_ALL_MASK)
a196ebeb 1289 {
df7e5265 1290 case (X86_XSTATE_AVX512_MASK):
01f9f808
MS		 1291 return tdesc_i386_avx512_linux;
1292
df7e5265 1293 case (X86_XSTATE_MPX_MASK):
a196ebeb
WT		 1294 return tdesc_i386_mpx_linux;
1295
df7e5265 1296 case (X86_XSTATE_AVX_MASK):
a196ebeb
WT		 1297 return tdesc_i386_avx_linux;
1298
1299 default:
1300 return tdesc_i386_linux;
1301 }
1302 }
3aee8918
PA		 1303 else
1304 return tdesc_i386_linux;
1305 }
1306
1307 gdb_assert_not_reached ("failed to return tdesc");
1308}
1309
1310/* Callback for find_inferior. Stops iteration when a thread with a
1311 given PID is found. */
1312
1313static int
1314same_process_callback (struct inferior_list_entry *entry, void *data)
1315{
1316 int pid = *(int *) data;
1317
1318 return (ptid_get_pid (entry->id) == pid);
1319}
1320
1321/* Callback for for_each_inferior. Calls the arch_setup routine for
1322 each process. */
1323
1324static void
1325x86_arch_setup_process_callback (struct inferior_list_entry *entry)
1326{
1327 int pid = ptid_get_pid (entry->id);
1328
1329 /* Look up any thread of this processes. */
0bfdf32f 1330 current_thread
3aee8918
PA		 1331 = (struct thread_info *) find_inferior (&all_threads,
1332 same_process_callback, &pid);
1333
1334 the_low_target.arch_setup ();
1335}
1336
1337/* Update all the target description of all processes; a new GDB
1338 connected, and it may or not support xml target descriptions. */
1339
1340static void
1341x86_linux_update_xmltarget (void)
1342{
0bfdf32f 1343 struct thread_info *saved_thread = current_thread;
3aee8918
PA		 1344
1345 /* Before changing the register cache's internal layout, flush the
1346 contents of the current valid caches back to the threads, and
1347 release the current regcache objects. */
1348 regcache_release ();
1349
1350 for_each_inferior (&all_processes, x86_arch_setup_process_callback);
1351
0bfdf32f 1352 current_thread = saved_thread;
1570b33e
L		 1353}
1354
1355/* Process qSupported query, "xmlRegisters=". Update the buffer size for
1356 PTRACE_GETREGSET. */
1357
1358static void
06e03fff 1359x86_linux_process_qsupported (char **features, int count)
1570b33e 1360{
06e03fff
PA		 1361 int i;
1362
1570b33e
L		 1363 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
1364 with "i386" in qSupported query, it supports x86 XML target
1365 descriptions. */
1366 use_xml = 0;
06e03fff 1367 for (i = 0; i < count; i++)
1570b33e 1368 {
06e03fff 1369 const char *feature = features[i];
1570b33e 1370
06e03fff 1371 if (startswith (feature, "xmlRegisters="))
1570b33e 1372 {
06e03fff
PA		 1373 char *copy = xstrdup (feature + 13);
1374 char *p;
1375
1376 for (p = strtok (copy, ","); p != NULL; p = strtok (NULL, ","))
1570b33e 1377 {
06e03fff
PA		 1378 if (strcmp (p, "i386") == 0)
1379 {
1380 use_xml = 1;
1381 break;
1382 }
1570b33e 1383 }
1570b33e 1384
06e03fff
PA		 1385 free (copy);
1386 }
1570b33e 1387 }
1570b33e
L		 1388 x86_linux_update_xmltarget ();
1389}
1390
3aee8918 1391/* Common for x86/x86-64. */
d0722149 1392
3aee8918
PA		 1393static struct regsets_info x86_regsets_info =
1394 {
1395 x86_regsets, /* regsets */
1396 0, /* num_regsets */
1397 NULL, /* disabled_regsets */
1398 };
214d508e
L		 1399
1400#ifdef __x86_64__
3aee8918
PA		 1401static struct regs_info amd64_linux_regs_info =
1402 {
1403 NULL, /* regset_bitmap */
1404 NULL, /* usrregs_info */
1405 &x86_regsets_info
1406 };
d0722149 1407#endif
3aee8918
PA		 1408static struct usrregs_info i386_linux_usrregs_info =
1409 {
1410 I386_NUM_REGS,
1411 i386_regmap,
1412 };
d0722149 1413
3aee8918
PA		 1414static struct regs_info i386_linux_regs_info =
1415 {
1416 NULL, /* regset_bitmap */
1417 &i386_linux_usrregs_info,
1418 &x86_regsets_info
1419 };
d0722149 1420
3aee8918
PA		 1421const struct regs_info *
1422x86_linux_regs_info (void)
1423{
1424#ifdef __x86_64__
1425 if (is_64bit_tdesc ())
1426 return &amd64_linux_regs_info;
1427 else
1428#endif
1429 return &i386_linux_regs_info;
1430}
d0722149 1431
3aee8918
PA		 1432/* Initialize the target description for the architecture of the
1433 inferior. */
1570b33e 1434
3aee8918
PA		 1435static void
1436x86_arch_setup (void)
1437{
1438 current_process ()->tdesc = x86_linux_read_description ();
d0722149
DE		 1439}
1440
82075af2
JS		 1441/* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1442 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1443
1444static void
1445x86_get_syscall_trapinfo (struct regcache *regcache, int *sysno, int *sysret)
1446{
1447 int use_64bit = register_size (regcache->tdesc, 0) == 8;
1448
1449 if (use_64bit)
1450 {
1451 long l_sysno;
1452 long l_sysret;
1453
1454 collect_register_by_name (regcache, "orig_rax", &l_sysno);
1455 collect_register_by_name (regcache, "rax", &l_sysret);
1456 *sysno = (int) l_sysno;
1457 *sysret = (int) l_sysret;
1458 }
1459 else
1460 {
1461 collect_register_by_name (regcache, "orig_eax", sysno);
1462 collect_register_by_name (regcache, "eax", sysret);
1463 }
1464}
1465
219f2f23
PA		 1466static int
1467x86_supports_tracepoints (void)
1468{
1469 return 1;
1470}
1471
fa593d66
PA		 1472static void
1473append_insns (CORE_ADDR *to, size_t len, const unsigned char *buf)
1474{
1475 write_inferior_memory (*to, buf, len);
1476 *to += len;
1477}
1478
1479static int
1480push_opcode (unsigned char *buf, char *op)
1481{
1482 unsigned char *buf_org = buf;
1483
1484 while (1)
1485 {
1486 char *endptr;
1487 unsigned long ul = strtoul (op, &endptr, 16);
1488
1489 if (endptr == op)
1490 break;
1491
1492 *buf++ = ul;
1493 op = endptr;
1494 }
1495
1496 return buf - buf_org;
1497}
1498
1499#ifdef __x86_64__
1500
1501/* Build a jump pad that saves registers and calls a collection
1502 function. Writes a jump instruction to the jump pad to
1503 JJUMPAD_INSN. The caller is responsible to write it in at the
1504 tracepoint address. */
1505
1506static int
1507amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1508 CORE_ADDR collector,
1509 CORE_ADDR lockaddr,
1510 ULONGEST orig_size,
1511 CORE_ADDR *jump_entry,
405f8e94
SS		 1512 CORE_ADDR *trampoline,
1513 ULONGEST *trampoline_size,
fa593d66
PA		 1514 unsigned char *jjump_pad_insn,
1515 ULONGEST *jjump_pad_insn_size,
1516 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1517 CORE_ADDR *adjusted_insn_addr_end,
1518 char *err)
fa593d66
PA		 1519{
1520 unsigned char buf[40];
1521 int i, offset;
f4647387
YQ		 1522 int64_t loffset;
1523
fa593d66
PA		 1524 CORE_ADDR buildaddr = *jump_entry;
1525
1526 /* Build the jump pad. */
1527
1528 /* First, do tracepoint data collection. Save registers. */
1529 i = 0;
1530 /* Need to ensure stack pointer saved first. */
1531 buf[i++] = 0x54; /* push %rsp */
1532 buf[i++] = 0x55; /* push %rbp */
1533 buf[i++] = 0x57; /* push %rdi */
1534 buf[i++] = 0x56; /* push %rsi */
1535 buf[i++] = 0x52; /* push %rdx */
1536 buf[i++] = 0x51; /* push %rcx */
1537 buf[i++] = 0x53; /* push %rbx */
1538 buf[i++] = 0x50; /* push %rax */
1539 buf[i++] = 0x41; buf[i++] = 0x57; /* push %r15 */
1540 buf[i++] = 0x41; buf[i++] = 0x56; /* push %r14 */
1541 buf[i++] = 0x41; buf[i++] = 0x55; /* push %r13 */
1542 buf[i++] = 0x41; buf[i++] = 0x54; /* push %r12 */
1543 buf[i++] = 0x41; buf[i++] = 0x53; /* push %r11 */
1544 buf[i++] = 0x41; buf[i++] = 0x52; /* push %r10 */
1545 buf[i++] = 0x41; buf[i++] = 0x51; /* push %r9 */
1546 buf[i++] = 0x41; buf[i++] = 0x50; /* push %r8 */
1547 buf[i++] = 0x9c; /* pushfq */
1548 buf[i++] = 0x48; /* movl <addr>,%rdi */
1549 buf[i++] = 0xbf;
1550 *((unsigned long *)(buf + i)) = (unsigned long) tpaddr;
1551 i += sizeof (unsigned long);
1552 buf[i++] = 0x57; /* push %rdi */
1553 append_insns (&buildaddr, i, buf);
1554
1555 /* Stack space for the collecting_t object. */
1556 i = 0;
1557 i += push_opcode (&buf[i], "48 83 ec 18"); /* sub $0x18,%rsp */
1558 i += push_opcode (&buf[i], "48 b8"); /* mov <tpoint>,%rax */
1559 memcpy (buf + i, &tpoint, 8);
1560 i += 8;
1561 i += push_opcode (&buf[i], "48 89 04 24"); /* mov %rax,(%rsp) */
1562 i += push_opcode (&buf[i],
1563 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1564 i += push_opcode (&buf[i], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1565 append_insns (&buildaddr, i, buf);
1566
1567 /* spin-lock. */
1568 i = 0;
1569 i += push_opcode (&buf[i], "48 be"); /* movl <lockaddr>,%rsi */
1570 memcpy (&buf[i], (void *) &lockaddr, 8);
1571 i += 8;
1572 i += push_opcode (&buf[i], "48 89 e1"); /* mov %rsp,%rcx */
1573 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1574 i += push_opcode (&buf[i], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1575 i += push_opcode (&buf[i], "48 85 c0"); /* test %rax,%rax */
1576 i += push_opcode (&buf[i], "75 f4"); /* jne <again> */
1577 append_insns (&buildaddr, i, buf);
1578
1579 /* Set up the gdb_collect call. */
1580 /* At this point, (stack pointer + 0x18) is the base of our saved
1581 register block. */
1582
1583 i = 0;
1584 i += push_opcode (&buf[i], "48 89 e6"); /* mov %rsp,%rsi */
1585 i += push_opcode (&buf[i], "48 83 c6 18"); /* add $0x18,%rsi */
1586
1587 /* tpoint address may be 64-bit wide. */
1588 i += push_opcode (&buf[i], "48 bf"); /* movl <addr>,%rdi */
1589 memcpy (buf + i, &tpoint, 8);
1590 i += 8;
1591 append_insns (&buildaddr, i, buf);
1592
1593 /* The collector function being in the shared library, may be
1594 >31-bits away off the jump pad. */
1595 i = 0;
1596 i += push_opcode (&buf[i], "48 b8"); /* mov $collector,%rax */
1597 memcpy (buf + i, &collector, 8);
1598 i += 8;
1599 i += push_opcode (&buf[i], "ff d0"); /* callq *%rax */
1600 append_insns (&buildaddr, i, buf);
1601
1602 /* Clear the spin-lock. */
1603 i = 0;
1604 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1605 i += push_opcode (&buf[i], "48 a3"); /* mov %rax, lockaddr */
1606 memcpy (buf + i, &lockaddr, 8);
1607 i += 8;
1608 append_insns (&buildaddr, i, buf);
1609
1610 /* Remove stack that had been used for the collect_t object. */
1611 i = 0;
1612 i += push_opcode (&buf[i], "48 83 c4 18"); /* add $0x18,%rsp */
1613 append_insns (&buildaddr, i, buf);
1614
1615 /* Restore register state. */
1616 i = 0;
1617 buf[i++] = 0x48; /* add $0x8,%rsp */
1618 buf[i++] = 0x83;
1619 buf[i++] = 0xc4;
1620 buf[i++] = 0x08;
1621 buf[i++] = 0x9d; /* popfq */
1622 buf[i++] = 0x41; buf[i++] = 0x58; /* pop %r8 */
1623 buf[i++] = 0x41; buf[i++] = 0x59; /* pop %r9 */
1624 buf[i++] = 0x41; buf[i++] = 0x5a; /* pop %r10 */
1625 buf[i++] = 0x41; buf[i++] = 0x5b; /* pop %r11 */
1626 buf[i++] = 0x41; buf[i++] = 0x5c; /* pop %r12 */
1627 buf[i++] = 0x41; buf[i++] = 0x5d; /* pop %r13 */
1628 buf[i++] = 0x41; buf[i++] = 0x5e; /* pop %r14 */
1629 buf[i++] = 0x41; buf[i++] = 0x5f; /* pop %r15 */
1630 buf[i++] = 0x58; /* pop %rax */
1631 buf[i++] = 0x5b; /* pop %rbx */
1632 buf[i++] = 0x59; /* pop %rcx */
1633 buf[i++] = 0x5a; /* pop %rdx */
1634 buf[i++] = 0x5e; /* pop %rsi */
1635 buf[i++] = 0x5f; /* pop %rdi */
1636 buf[i++] = 0x5d; /* pop %rbp */
1637 buf[i++] = 0x5c; /* pop %rsp */
1638 append_insns (&buildaddr, i, buf);
1639
1640 /* Now, adjust the original instruction to execute in the jump
1641 pad. */
1642 *adjusted_insn_addr = buildaddr;
1643 relocate_instruction (&buildaddr, tpaddr);
1644 *adjusted_insn_addr_end = buildaddr;
1645
1646 /* Finally, write a jump back to the program. */
f4647387
YQ		 1647
1648 loffset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn));
1649 if (loffset > INT_MAX || loffset < INT_MIN)
1650 {
1651 sprintf (err,
1652 "E.Jump back from jump pad too far from tracepoint "
1653 "(offset 0x%" PRIx64 " > int32).", loffset);
1654 return 1;
1655 }
1656
1657 offset = (int) loffset;
fa593d66
PA		 1658 memcpy (buf, jump_insn, sizeof (jump_insn));
1659 memcpy (buf + 1, &offset, 4);
1660 append_insns (&buildaddr, sizeof (jump_insn), buf);
1661
1662 /* The jump pad is now built. Wire in a jump to our jump pad. This
1663 is always done last (by our caller actually), so that we can
1664 install fast tracepoints with threads running. This relies on
1665 the agent's atomic write support. */
f4647387
YQ		 1666 loffset = *jump_entry - (tpaddr + sizeof (jump_insn));
1667 if (loffset > INT_MAX || loffset < INT_MIN)
1668 {
1669 sprintf (err,
1670 "E.Jump pad too far from tracepoint "
1671 "(offset 0x%" PRIx64 " > int32).", loffset);
1672 return 1;
1673 }
1674
1675 offset = (int) loffset;
1676
fa593d66
PA		 1677 memcpy (buf, jump_insn, sizeof (jump_insn));
1678 memcpy (buf + 1, &offset, 4);
1679 memcpy (jjump_pad_insn, buf, sizeof (jump_insn));
1680 *jjump_pad_insn_size = sizeof (jump_insn);
1681
1682 /* Return the end address of our pad. */
1683 *jump_entry = buildaddr;
1684
1685 return 0;
1686}
1687
1688#endif /* __x86_64__ */
1689
1690/* Build a jump pad that saves registers and calls a collection
1691 function. Writes a jump instruction to the jump pad to
1692 JJUMPAD_INSN. The caller is responsible to write it in at the
1693 tracepoint address. */
1694
1695static int
1696i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1697 CORE_ADDR collector,
1698 CORE_ADDR lockaddr,
1699 ULONGEST orig_size,
1700 CORE_ADDR *jump_entry,
405f8e94
SS		 1701 CORE_ADDR *trampoline,
1702 ULONGEST *trampoline_size,
fa593d66
PA		 1703 unsigned char *jjump_pad_insn,
1704 ULONGEST *jjump_pad_insn_size,
1705 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1706 CORE_ADDR *adjusted_insn_addr_end,
1707 char *err)
fa593d66
PA		 1708{
1709 unsigned char buf[0x100];
1710 int i, offset;
1711 CORE_ADDR buildaddr = *jump_entry;
1712
1713 /* Build the jump pad. */
1714
1715 /* First, do tracepoint data collection. Save registers. */
1716 i = 0;
1717 buf[i++] = 0x60; /* pushad */
1718 buf[i++] = 0x68; /* push tpaddr aka $pc */
1719 *((int *)(buf + i)) = (int) tpaddr;
1720 i += 4;
1721 buf[i++] = 0x9c; /* pushf */
1722 buf[i++] = 0x1e; /* push %ds */
1723 buf[i++] = 0x06; /* push %es */
1724 buf[i++] = 0x0f; /* push %fs */
1725 buf[i++] = 0xa0;
1726 buf[i++] = 0x0f; /* push %gs */
1727 buf[i++] = 0xa8;
1728 buf[i++] = 0x16; /* push %ss */
1729 buf[i++] = 0x0e; /* push %cs */
1730 append_insns (&buildaddr, i, buf);
1731
1732 /* Stack space for the collecting_t object. */
1733 i = 0;
1734 i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */
1735
1736 /* Build the object. */
1737 i += push_opcode (&buf[i], "b8"); /* mov <tpoint>,%eax */
1738 memcpy (buf + i, &tpoint, 4);
1739 i += 4;
1740 i += push_opcode (&buf[i], "89 04 24"); /* mov %eax,(%esp) */
1741
1742 i += push_opcode (&buf[i], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1743 i += push_opcode (&buf[i], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1744 append_insns (&buildaddr, i, buf);
1745
1746 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1747 If we cared for it, this could be using xchg alternatively. */
1748
1749 i = 0;
1750 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1751 i += push_opcode (&buf[i], "f0 0f b1 25"); /* lock cmpxchg
1752 %esp,<lockaddr> */
1753 memcpy (&buf[i], (void *) &lockaddr, 4);
1754 i += 4;
1755 i += push_opcode (&buf[i], "85 c0"); /* test %eax,%eax */
1756 i += push_opcode (&buf[i], "75 f2"); /* jne <again> */
1757 append_insns (&buildaddr, i, buf);
1758
1759
1760 /* Set up arguments to the gdb_collect call. */
1761 i = 0;
1762 i += push_opcode (&buf[i], "89 e0"); /* mov %esp,%eax */
1763 i += push_opcode (&buf[i], "83 c0 08"); /* add $0x08,%eax */
1764 i += push_opcode (&buf[i], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1765 append_insns (&buildaddr, i, buf);
1766
1767 i = 0;
1768 i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */
1769 append_insns (&buildaddr, i, buf);
1770
1771 i = 0;
1772 i += push_opcode (&buf[i], "c7 04 24"); /* movl <addr>,(%esp) */
1773 memcpy (&buf[i], (void *) &tpoint, 4);
1774 i += 4;
1775 append_insns (&buildaddr, i, buf);
1776
1777 buf[0] = 0xe8; /* call <reladdr> */
1778 offset = collector - (buildaddr + sizeof (jump_insn));
1779 memcpy (buf + 1, &offset, 4);
1780 append_insns (&buildaddr, 5, buf);
1781 /* Clean up after the call. */
1782 buf[0] = 0x83; /* add $0x8,%esp */
1783 buf[1] = 0xc4;
1784 buf[2] = 0x08;
1785 append_insns (&buildaddr, 3, buf);
1786
1787
1788 /* Clear the spin-lock. This would need the LOCK prefix on older
1789 broken archs. */
1790 i = 0;
1791 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1792 i += push_opcode (&buf[i], "a3"); /* mov %eax, lockaddr */
1793 memcpy (buf + i, &lockaddr, 4);
1794 i += 4;
1795 append_insns (&buildaddr, i, buf);
1796
1797
1798 /* Remove stack that had been used for the collect_t object. */
1799 i = 0;
1800 i += push_opcode (&buf[i], "83 c4 08"); /* add $0x08,%esp */
1801 append_insns (&buildaddr, i, buf);
1802
1803 i = 0;
1804 buf[i++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1805 buf[i++] = 0xc4;
1806 buf[i++] = 0x04;
1807 buf[i++] = 0x17; /* pop %ss */
1808 buf[i++] = 0x0f; /* pop %gs */
1809 buf[i++] = 0xa9;
1810 buf[i++] = 0x0f; /* pop %fs */
1811 buf[i++] = 0xa1;
1812 buf[i++] = 0x07; /* pop %es */
405f8e94 1813 buf[i++] = 0x1f; /* pop %ds */
fa593d66
PA		 1814 buf[i++] = 0x9d; /* popf */
1815 buf[i++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1816 buf[i++] = 0xc4;
1817 buf[i++] = 0x04;
1818 buf[i++] = 0x61; /* popad */
1819 append_insns (&buildaddr, i, buf);
1820
1821 /* Now, adjust the original instruction to execute in the jump
1822 pad. */
1823 *adjusted_insn_addr = buildaddr;
1824 relocate_instruction (&buildaddr, tpaddr);
1825 *adjusted_insn_addr_end = buildaddr;
1826
1827 /* Write the jump back to the program. */
1828 offset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn));
1829 memcpy (buf, jump_insn, sizeof (jump_insn));
1830 memcpy (buf + 1, &offset, 4);
1831 append_insns (&buildaddr, sizeof (jump_insn), buf);
1832
1833 /* The jump pad is now built. Wire in a jump to our jump pad. This
1834 is always done last (by our caller actually), so that we can
1835 install fast tracepoints with threads running. This relies on
1836 the agent's atomic write support. */
405f8e94
SS		 1837 if (orig_size == 4)
1838 {
1839 /* Create a trampoline. */
1840 *trampoline_size = sizeof (jump_insn);
1841 if (!claim_trampoline_space (*trampoline_size, trampoline))
1842 {
1843 /* No trampoline space available. */
1844 strcpy (err,
1845 "E.Cannot allocate trampoline space needed for fast "
1846 "tracepoints on 4-byte instructions.");
1847 return 1;
1848 }
1849
1850 offset = *jump_entry - (*trampoline + sizeof (jump_insn));
1851 memcpy (buf, jump_insn, sizeof (jump_insn));
1852 memcpy (buf + 1, &offset, 4);
1853 write_inferior_memory (*trampoline, buf, sizeof (jump_insn));
1854
1855 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1856 offset = (*trampoline - (tpaddr + sizeof (small_jump_insn))) & 0xffff;
1857 memcpy (buf, small_jump_insn, sizeof (small_jump_insn));
1858 memcpy (buf + 2, &offset, 2);
1859 memcpy (jjump_pad_insn, buf, sizeof (small_jump_insn));
1860 *jjump_pad_insn_size = sizeof (small_jump_insn);
1861 }
1862 else
1863 {
1864 /* Else use a 32-bit relative jump instruction. */
1865 offset = *jump_entry - (tpaddr + sizeof (jump_insn));
1866 memcpy (buf, jump_insn, sizeof (jump_insn));
1867 memcpy (buf + 1, &offset, 4);
1868 memcpy (jjump_pad_insn, buf, sizeof (jump_insn));
1869 *jjump_pad_insn_size = sizeof (jump_insn);
1870 }
fa593d66
PA		 1871
1872 /* Return the end address of our pad. */
1873 *jump_entry = buildaddr;
1874
1875 return 0;
1876}
1877
1878static int
1879x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1880 CORE_ADDR collector,
1881 CORE_ADDR lockaddr,
1882 ULONGEST orig_size,
1883 CORE_ADDR *jump_entry,
405f8e94
SS		 1884 CORE_ADDR *trampoline,
1885 ULONGEST *trampoline_size,
fa593d66
PA		 1886 unsigned char *jjump_pad_insn,
1887 ULONGEST *jjump_pad_insn_size,
1888 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1889 CORE_ADDR *adjusted_insn_addr_end,
1890 char *err)
fa593d66
PA		 1891{
1892#ifdef __x86_64__
3aee8918 1893 if (is_64bit_tdesc ())
fa593d66
PA		 1894 return amd64_install_fast_tracepoint_jump_pad (tpoint, tpaddr,
1895 collector, lockaddr,
1896 orig_size, jump_entry,
405f8e94 1897 trampoline, trampoline_size,
fa593d66
PA		 1898 jjump_pad_insn,
1899 jjump_pad_insn_size,
1900 adjusted_insn_addr,
405f8e94
SS		 1901 adjusted_insn_addr_end,
1902 err);
fa593d66
PA		 1903#endif
1904
1905 return i386_install_fast_tracepoint_jump_pad (tpoint, tpaddr,
1906 collector, lockaddr,
1907 orig_size, jump_entry,
405f8e94 1908 trampoline, trampoline_size,
fa593d66
PA		 1909 jjump_pad_insn,
1910 jjump_pad_insn_size,
1911 adjusted_insn_addr,
405f8e94
SS		 1912 adjusted_insn_addr_end,
1913 err);
1914}
1915
1916/* Return the minimum instruction length for fast tracepoints on x86/x86-64
1917 architectures. */
1918
1919static int
1920x86_get_min_fast_tracepoint_insn_len (void)
1921{
1922 static int warned_about_fast_tracepoints = 0;
1923
1924#ifdef __x86_64__
1925 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1926 used for fast tracepoints. */
3aee8918 1927 if (is_64bit_tdesc ())
405f8e94
SS		 1928 return 5;
1929#endif
1930
58b4daa5 1931 if (agent_loaded_p ())
405f8e94
SS		 1932 {
1933 char errbuf[IPA_BUFSIZ];
1934
1935 errbuf[0] = '\0';
1936
1937 /* On x86, if trampolines are available, then 4-byte jump instructions
1938 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1939 with a 4-byte offset are used instead. */
1940 if (have_fast_tracepoint_trampoline_buffer (errbuf))
1941 return 4;
1942 else
1943 {
1944 /* GDB has no channel to explain to user why a shorter fast
1945 tracepoint is not possible, but at least make GDBserver
1946 mention that something has gone awry. */
1947 if (!warned_about_fast_tracepoints)
1948 {
1949 warning ("4-byte fast tracepoints not available; %s\n", errbuf);
1950 warned_about_fast_tracepoints = 1;
1951 }
1952 return 5;
1953 }
1954 }
1955 else
1956 {
1957 /* Indicate that the minimum length is currently unknown since the IPA
1958 has not loaded yet. */
1959 return 0;
1960 }
fa593d66
PA		 1961}
1962
6a271cae
PA		 1963static void
1964add_insns (unsigned char *start, int len)
1965{
1966 CORE_ADDR buildaddr = current_insn_ptr;
1967
1968 if (debug_threads)
87ce2a04
DE		 1969 debug_printf ("Adding %d bytes of insn at %s\n",
1970 len, paddress (buildaddr));
6a271cae
PA		 1971
1972 append_insns (&buildaddr, len, start);
1973 current_insn_ptr = buildaddr;
1974}
1975
6a271cae
PA		 1976/* Our general strategy for emitting code is to avoid specifying raw
1977 bytes whenever possible, and instead copy a block of inline asm
1978 that is embedded in the function. This is a little messy, because
1979 we need to keep the compiler from discarding what looks like dead
1980 code, plus suppress various warnings. */
1981
9e4344e5
PA		 1982#define EMIT_ASM(NAME, INSNS) \
1983 do \
1984 { \
1985 extern unsigned char start_ ## NAME, end_ ## NAME; \
1986 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
493e2a69 1987 __asm__ ("jmp end_" #NAME "\n" \
9e4344e5
PA		 1988 "\t" "start_" #NAME ":" \
1989 "\t" INSNS "\n" \
1990 "\t" "end_" #NAME ":"); \
1991 } while (0)
6a271cae
PA		 1992
1993#ifdef __x86_64__
1994
1995#define EMIT_ASM32(NAME,INSNS) \
9e4344e5
PA		 1996 do \
1997 { \
1998 extern unsigned char start_ ## NAME, end_ ## NAME; \
1999 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
2000 __asm__ (".code32\n" \
2001 "\t" "jmp end_" #NAME "\n" \
2002 "\t" "start_" #NAME ":\n" \
2003 "\t" INSNS "\n" \
2004 "\t" "end_" #NAME ":\n" \
2005 ".code64\n"); \
2006 } while (0)
6a271cae
PA		 2007
2008#else
2009
2010#define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
2011
2012#endif
2013
2014#ifdef __x86_64__
2015
2016static void
2017amd64_emit_prologue (void)
2018{
2019 EMIT_ASM (amd64_prologue,
2020 "pushq %rbp\n\t"
2021 "movq %rsp,%rbp\n\t"
2022 "sub $0x20,%rsp\n\t"
2023 "movq %rdi,-8(%rbp)\n\t"
2024 "movq %rsi,-16(%rbp)");
2025}
2026
2027
2028static void
2029amd64_emit_epilogue (void)
2030{
2031 EMIT_ASM (amd64_epilogue,
2032 "movq -16(%rbp),%rdi\n\t"
2033 "movq %rax,(%rdi)\n\t"
2034 "xor %rax,%rax\n\t"
2035 "leave\n\t"
2036 "ret");
2037}
2038
2039static void
2040amd64_emit_add (void)
2041{
2042 EMIT_ASM (amd64_add,
2043 "add (%rsp),%rax\n\t"
2044 "lea 0x8(%rsp),%rsp");
2045}
2046
2047static void
2048amd64_emit_sub (void)
2049{
2050 EMIT_ASM (amd64_sub,
2051 "sub %rax,(%rsp)\n\t"
2052 "pop %rax");
2053}
2054
2055static void
2056amd64_emit_mul (void)
2057{
2058 emit_error = 1;
2059}
2060
2061static void
2062amd64_emit_lsh (void)
2063{
2064 emit_error = 1;
2065}
2066
2067static void
2068amd64_emit_rsh_signed (void)
2069{
2070 emit_error = 1;
2071}
2072
2073static void
2074amd64_emit_rsh_unsigned (void)
2075{
2076 emit_error = 1;
2077}
2078
2079static void
2080amd64_emit_ext (int arg)
2081{
2082 switch (arg)
2083 {
2084 case 8:
2085 EMIT_ASM (amd64_ext_8,
2086 "cbtw\n\t"
2087 "cwtl\n\t"
2088 "cltq");
2089 break;
2090 case 16:
2091 EMIT_ASM (amd64_ext_16,
2092 "cwtl\n\t"
2093 "cltq");
2094 break;
2095 case 32:
2096 EMIT_ASM (amd64_ext_32,
2097 "cltq");
2098 break;
2099 default:
2100 emit_error = 1;
2101 }
2102}
2103
2104static void
2105amd64_emit_log_not (void)
2106{
2107 EMIT_ASM (amd64_log_not,
2108 "test %rax,%rax\n\t"
2109 "sete %cl\n\t"
2110 "movzbq %cl,%rax");
2111}
2112
2113static void
2114amd64_emit_bit_and (void)
2115{
2116 EMIT_ASM (amd64_and,
2117 "and (%rsp),%rax\n\t"
2118 "lea 0x8(%rsp),%rsp");
2119}
2120
2121static void
2122amd64_emit_bit_or (void)
2123{
2124 EMIT_ASM (amd64_or,
2125 "or (%rsp),%rax\n\t"
2126 "lea 0x8(%rsp),%rsp");
2127}
2128
2129static void
2130amd64_emit_bit_xor (void)
2131{
2132 EMIT_ASM (amd64_xor,
2133 "xor (%rsp),%rax\n\t"
2134 "lea 0x8(%rsp),%rsp");
2135}
2136
2137static void
2138amd64_emit_bit_not (void)
2139{
2140 EMIT_ASM (amd64_bit_not,
2141 "xorq $0xffffffffffffffff,%rax");
2142}
2143
2144static void
2145amd64_emit_equal (void)
2146{
2147 EMIT_ASM (amd64_equal,
2148 "cmp %rax,(%rsp)\n\t"
2149 "je .Lamd64_equal_true\n\t"
2150 "xor %rax,%rax\n\t"
2151 "jmp .Lamd64_equal_end\n\t"
2152 ".Lamd64_equal_true:\n\t"
2153 "mov $0x1,%rax\n\t"
2154 ".Lamd64_equal_end:\n\t"
2155 "lea 0x8(%rsp),%rsp");
2156}
2157
2158static void
2159amd64_emit_less_signed (void)
2160{
2161 EMIT_ASM (amd64_less_signed,
2162 "cmp %rax,(%rsp)\n\t"
2163 "jl .Lamd64_less_signed_true\n\t"
2164 "xor %rax,%rax\n\t"
2165 "jmp .Lamd64_less_signed_end\n\t"
2166 ".Lamd64_less_signed_true:\n\t"
2167 "mov $1,%rax\n\t"
2168 ".Lamd64_less_signed_end:\n\t"
2169 "lea 0x8(%rsp),%rsp");
2170}
2171
2172static void
2173amd64_emit_less_unsigned (void)
2174{
2175 EMIT_ASM (amd64_less_unsigned,
2176 "cmp %rax,(%rsp)\n\t"
2177 "jb .Lamd64_less_unsigned_true\n\t"
2178 "xor %rax,%rax\n\t"
2179 "jmp .Lamd64_less_unsigned_end\n\t"
2180 ".Lamd64_less_unsigned_true:\n\t"
2181 "mov $1,%rax\n\t"
2182 ".Lamd64_less_unsigned_end:\n\t"
2183 "lea 0x8(%rsp),%rsp");
2184}
2185
2186static void
2187amd64_emit_ref (int size)
2188{
2189 switch (size)
2190 {
2191 case 1:
2192 EMIT_ASM (amd64_ref1,
2193 "movb (%rax),%al");
2194 break;
2195 case 2:
2196 EMIT_ASM (amd64_ref2,
2197 "movw (%rax),%ax");
2198 break;
2199 case 4:
2200 EMIT_ASM (amd64_ref4,
2201 "movl (%rax),%eax");
2202 break;
2203 case 8:
2204 EMIT_ASM (amd64_ref8,
2205 "movq (%rax),%rax");
2206 break;
2207 }
2208}
2209
2210static void
2211amd64_emit_if_goto (int *offset_p, int *size_p)
2212{
2213 EMIT_ASM (amd64_if_goto,
2214 "mov %rax,%rcx\n\t"
2215 "pop %rax\n\t"
2216 "cmp $0,%rcx\n\t"
2217 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2218 if (offset_p)
2219 *offset_p = 10;
2220 if (size_p)
2221 *size_p = 4;
2222}
2223
2224static void
2225amd64_emit_goto (int *offset_p, int *size_p)
2226{
2227 EMIT_ASM (amd64_goto,
2228 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2229 if (offset_p)
2230 *offset_p = 1;
2231 if (size_p)
2232 *size_p = 4;
2233}
2234
2235static void
2236amd64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2237{
2238 int diff = (to - (from + size));
2239 unsigned char buf[sizeof (int)];
2240
2241 if (size != 4)
2242 {
2243 emit_error = 1;
2244 return;
2245 }
2246
2247 memcpy (buf, &diff, sizeof (int));
2248 write_inferior_memory (from, buf, sizeof (int));
2249}
2250
2251static void
4e29fb54 2252amd64_emit_const (LONGEST num)
6a271cae
PA		 2253{
2254 unsigned char buf[16];
2255 int i;
2256 CORE_ADDR buildaddr = current_insn_ptr;
2257
2258 i = 0;
2259 buf[i++] = 0x48; buf[i++] = 0xb8; /* mov $<n>,%rax */
b00ad6ff 2260 memcpy (&buf[i], &num, sizeof (num));
6a271cae
PA		 2261 i += 8;
2262 append_insns (&buildaddr, i, buf);
2263 current_insn_ptr = buildaddr;
2264}
2265
2266static void
2267amd64_emit_call (CORE_ADDR fn)
2268{
2269 unsigned char buf[16];
2270 int i;
2271 CORE_ADDR buildaddr;
4e29fb54 2272 LONGEST offset64;
6a271cae
PA		 2273
2274 /* The destination function being in the shared library, may be
2275 >31-bits away off the compiled code pad. */
2276
2277 buildaddr = current_insn_ptr;
2278
2279 offset64 = fn - (buildaddr + 1 /* call op */ + 4 /* 32-bit offset */);
2280
2281 i = 0;
2282
2283 if (offset64 > INT_MAX || offset64 < INT_MIN)
2284 {
2285 /* Offset is too large for a call. Use callq, but that requires
2286 a register, so avoid it if possible. Use r10, since it is
2287 call-clobbered, we don't have to push/pop it. */
2288 buf[i++] = 0x48; /* mov $fn,%r10 */
2289 buf[i++] = 0xba;
2290 memcpy (buf + i, &fn, 8);
2291 i += 8;
2292 buf[i++] = 0xff; /* callq *%r10 */
2293 buf[i++] = 0xd2;
2294 }
2295 else
2296 {
2297 int offset32 = offset64; /* we know we can't overflow here. */
2298 memcpy (buf + i, &offset32, 4);
2299 i += 4;
2300 }
2301
2302 append_insns (&buildaddr, i, buf);
2303 current_insn_ptr = buildaddr;
2304}
2305
2306static void
2307amd64_emit_reg (int reg)
2308{
2309 unsigned char buf[16];
2310 int i;
2311 CORE_ADDR buildaddr;
2312
2313 /* Assume raw_regs is still in %rdi. */
2314 buildaddr = current_insn_ptr;
2315 i = 0;
2316 buf[i++] = 0xbe; /* mov $<n>,%esi */
b00ad6ff 2317 memcpy (&buf[i], &reg, sizeof (reg));
6a271cae
PA		 2318 i += 4;
2319 append_insns (&buildaddr, i, buf);
2320 current_insn_ptr = buildaddr;
2321 amd64_emit_call (get_raw_reg_func_addr ());
2322}
2323
2324static void
2325amd64_emit_pop (void)
2326{
2327 EMIT_ASM (amd64_pop,
2328 "pop %rax");
2329}
2330
2331static void
2332amd64_emit_stack_flush (void)
2333{
2334 EMIT_ASM (amd64_stack_flush,
2335 "push %rax");
2336}
2337
2338static void
2339amd64_emit_zero_ext (int arg)
2340{
2341 switch (arg)
2342 {
2343 case 8:
2344 EMIT_ASM (amd64_zero_ext_8,
2345 "and $0xff,%rax");
2346 break;
2347 case 16:
2348 EMIT_ASM (amd64_zero_ext_16,
2349 "and $0xffff,%rax");
2350 break;
2351 case 32:
2352 EMIT_ASM (amd64_zero_ext_32,
2353 "mov $0xffffffff,%rcx\n\t"
2354 "and %rcx,%rax");
2355 break;
2356 default:
2357 emit_error = 1;
2358 }
2359}
2360
2361static void
2362amd64_emit_swap (void)
2363{
2364 EMIT_ASM (amd64_swap,
2365 "mov %rax,%rcx\n\t"
2366 "pop %rax\n\t"
2367 "push %rcx");
2368}
2369
2370static void
2371amd64_emit_stack_adjust (int n)
2372{
2373 unsigned char buf[16];
2374 int i;
2375 CORE_ADDR buildaddr = current_insn_ptr;
2376
2377 i = 0;
2378 buf[i++] = 0x48; /* lea $<n>(%rsp),%rsp */
2379 buf[i++] = 0x8d;
2380 buf[i++] = 0x64;
2381 buf[i++] = 0x24;
2382 /* This only handles adjustments up to 16, but we don't expect any more. */
2383 buf[i++] = n * 8;
2384 append_insns (&buildaddr, i, buf);
2385 current_insn_ptr = buildaddr;
2386}
2387
2388/* FN's prototype is `LONGEST(*fn)(int)'. */
2389
2390static void
2391amd64_emit_int_call_1 (CORE_ADDR fn, int arg1)
2392{
2393 unsigned char buf[16];
2394 int i;
2395 CORE_ADDR buildaddr;
2396
2397 buildaddr = current_insn_ptr;
2398 i = 0;
2399 buf[i++] = 0xbf; /* movl $<n>,%edi */
b00ad6ff 2400 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 2401 i += 4;
2402 append_insns (&buildaddr, i, buf);
2403 current_insn_ptr = buildaddr;
2404 amd64_emit_call (fn);
2405}
2406
4e29fb54 2407/* FN's prototype is `void(*fn)(int,LONGEST)'. */
6a271cae
PA		 2408
2409static void
2410amd64_emit_void_call_2 (CORE_ADDR fn, int arg1)
2411{
2412 unsigned char buf[16];
2413 int i;
2414 CORE_ADDR buildaddr;
2415
2416 buildaddr = current_insn_ptr;
2417 i = 0;
2418 buf[i++] = 0xbf; /* movl $<n>,%edi */
b00ad6ff 2419 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 2420 i += 4;
2421 append_insns (&buildaddr, i, buf);
2422 current_insn_ptr = buildaddr;
2423 EMIT_ASM (amd64_void_call_2_a,
2424 /* Save away a copy of the stack top. */
2425 "push %rax\n\t"
2426 /* Also pass top as the second argument. */
2427 "mov %rax,%rsi");
2428 amd64_emit_call (fn);
2429 EMIT_ASM (amd64_void_call_2_b,
2430 /* Restore the stack top, %rax may have been trashed. */
2431 "pop %rax");
2432}
2433
6b9801d4
SS		 2434void
2435amd64_emit_eq_goto (int *offset_p, int *size_p)
2436{
2437 EMIT_ASM (amd64_eq,
2438 "cmp %rax,(%rsp)\n\t"
2439 "jne .Lamd64_eq_fallthru\n\t"
2440 "lea 0x8(%rsp),%rsp\n\t"
2441 "pop %rax\n\t"
2442 /* jmp, but don't trust the assembler to choose the right jump */
2443 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2444 ".Lamd64_eq_fallthru:\n\t"
2445 "lea 0x8(%rsp),%rsp\n\t"
2446 "pop %rax");
2447
2448 if (offset_p)
2449 *offset_p = 13;
2450 if (size_p)
2451 *size_p = 4;
2452}
2453
2454void
2455amd64_emit_ne_goto (int *offset_p, int *size_p)
2456{
2457 EMIT_ASM (amd64_ne,
2458 "cmp %rax,(%rsp)\n\t"
2459 "je .Lamd64_ne_fallthru\n\t"
2460 "lea 0x8(%rsp),%rsp\n\t"
2461 "pop %rax\n\t"
2462 /* jmp, but don't trust the assembler to choose the right jump */
2463 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2464 ".Lamd64_ne_fallthru:\n\t"
2465 "lea 0x8(%rsp),%rsp\n\t"
2466 "pop %rax");
2467
2468 if (offset_p)
2469 *offset_p = 13;
2470 if (size_p)
2471 *size_p = 4;
2472}
2473
2474void
2475amd64_emit_lt_goto (int *offset_p, int *size_p)
2476{
2477 EMIT_ASM (amd64_lt,
2478 "cmp %rax,(%rsp)\n\t"
2479 "jnl .Lamd64_lt_fallthru\n\t"
2480 "lea 0x8(%rsp),%rsp\n\t"
2481 "pop %rax\n\t"
2482 /* jmp, but don't trust the assembler to choose the right jump */
2483 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2484 ".Lamd64_lt_fallthru:\n\t"
2485 "lea 0x8(%rsp),%rsp\n\t"
2486 "pop %rax");
2487
2488 if (offset_p)
2489 *offset_p = 13;
2490 if (size_p)
2491 *size_p = 4;
2492}
2493
2494void
2495amd64_emit_le_goto (int *offset_p, int *size_p)
2496{
2497 EMIT_ASM (amd64_le,
2498 "cmp %rax,(%rsp)\n\t"
2499 "jnle .Lamd64_le_fallthru\n\t"
2500 "lea 0x8(%rsp),%rsp\n\t"
2501 "pop %rax\n\t"
2502 /* jmp, but don't trust the assembler to choose the right jump */
2503 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2504 ".Lamd64_le_fallthru:\n\t"
2505 "lea 0x8(%rsp),%rsp\n\t"
2506 "pop %rax");
2507
2508 if (offset_p)
2509 *offset_p = 13;
2510 if (size_p)
2511 *size_p = 4;
2512}
2513
2514void
2515amd64_emit_gt_goto (int *offset_p, int *size_p)
2516{
2517 EMIT_ASM (amd64_gt,
2518 "cmp %rax,(%rsp)\n\t"
2519 "jng .Lamd64_gt_fallthru\n\t"
2520 "lea 0x8(%rsp),%rsp\n\t"
2521 "pop %rax\n\t"
2522 /* jmp, but don't trust the assembler to choose the right jump */
2523 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2524 ".Lamd64_gt_fallthru:\n\t"
2525 "lea 0x8(%rsp),%rsp\n\t"
2526 "pop %rax");
2527
2528 if (offset_p)
2529 *offset_p = 13;
2530 if (size_p)
2531 *size_p = 4;
2532}
2533
2534void
2535amd64_emit_ge_goto (int *offset_p, int *size_p)
2536{
2537 EMIT_ASM (amd64_ge,
2538 "cmp %rax,(%rsp)\n\t"
2539 "jnge .Lamd64_ge_fallthru\n\t"
2540 ".Lamd64_ge_jump:\n\t"
2541 "lea 0x8(%rsp),%rsp\n\t"
2542 "pop %rax\n\t"
2543 /* jmp, but don't trust the assembler to choose the right jump */
2544 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2545 ".Lamd64_ge_fallthru:\n\t"
2546 "lea 0x8(%rsp),%rsp\n\t"
2547 "pop %rax");
2548
2549 if (offset_p)
2550 *offset_p = 13;
2551 if (size_p)
2552 *size_p = 4;
2553}
2554
6a271cae
PA		 2555struct emit_ops amd64_emit_ops =
2556 {
2557 amd64_emit_prologue,
2558 amd64_emit_epilogue,
2559 amd64_emit_add,
2560 amd64_emit_sub,
2561 amd64_emit_mul,
2562 amd64_emit_lsh,
2563 amd64_emit_rsh_signed,
2564 amd64_emit_rsh_unsigned,
2565 amd64_emit_ext,
2566 amd64_emit_log_not,
2567 amd64_emit_bit_and,
2568 amd64_emit_bit_or,
2569 amd64_emit_bit_xor,
2570 amd64_emit_bit_not,
2571 amd64_emit_equal,
2572 amd64_emit_less_signed,
2573 amd64_emit_less_unsigned,
2574 amd64_emit_ref,
2575 amd64_emit_if_goto,
2576 amd64_emit_goto,
2577 amd64_write_goto_address,
2578 amd64_emit_const,
2579 amd64_emit_call,
2580 amd64_emit_reg,
2581 amd64_emit_pop,
2582 amd64_emit_stack_flush,
2583 amd64_emit_zero_ext,
2584 amd64_emit_swap,
2585 amd64_emit_stack_adjust,
2586 amd64_emit_int_call_1,
6b9801d4
SS		 2587 amd64_emit_void_call_2,
2588 amd64_emit_eq_goto,
2589 amd64_emit_ne_goto,
2590 amd64_emit_lt_goto,
2591 amd64_emit_le_goto,
2592 amd64_emit_gt_goto,
2593 amd64_emit_ge_goto
6a271cae
PA		 2594 };
2595
2596#endif /* __x86_64__ */
2597
2598static void
2599i386_emit_prologue (void)
2600{
2601 EMIT_ASM32 (i386_prologue,
2602 "push %ebp\n\t"
bf15cbda
SS		 2603 "mov %esp,%ebp\n\t"
2604 "push %ebx");
6a271cae
PA		 2605 /* At this point, the raw regs base address is at 8(%ebp), and the
2606 value pointer is at 12(%ebp). */
2607}
2608
2609static void
2610i386_emit_epilogue (void)
2611{
2612 EMIT_ASM32 (i386_epilogue,
2613 "mov 12(%ebp),%ecx\n\t"
2614 "mov %eax,(%ecx)\n\t"
2615 "mov %ebx,0x4(%ecx)\n\t"
2616 "xor %eax,%eax\n\t"
bf15cbda 2617 "pop %ebx\n\t"
6a271cae
PA		 2618 "pop %ebp\n\t"
2619 "ret");
2620}
2621
2622static void
2623i386_emit_add (void)
2624{
2625 EMIT_ASM32 (i386_add,
2626 "add (%esp),%eax\n\t"
2627 "adc 0x4(%esp),%ebx\n\t"
2628 "lea 0x8(%esp),%esp");
2629}
2630
2631static void
2632i386_emit_sub (void)
2633{
2634 EMIT_ASM32 (i386_sub,
2635 "subl %eax,(%esp)\n\t"
2636 "sbbl %ebx,4(%esp)\n\t"
2637 "pop %eax\n\t"
2638 "pop %ebx\n\t");
2639}
2640
2641static void
2642i386_emit_mul (void)
2643{
2644 emit_error = 1;
2645}
2646
2647static void
2648i386_emit_lsh (void)
2649{
2650 emit_error = 1;
2651}
2652
2653static void
2654i386_emit_rsh_signed (void)
2655{
2656 emit_error = 1;
2657}
2658
2659static void
2660i386_emit_rsh_unsigned (void)
2661{
2662 emit_error = 1;
2663}
2664
2665static void
2666i386_emit_ext (int arg)
2667{
2668 switch (arg)
2669 {
2670 case 8:
2671 EMIT_ASM32 (i386_ext_8,
2672 "cbtw\n\t"
2673 "cwtl\n\t"
2674 "movl %eax,%ebx\n\t"
2675 "sarl $31,%ebx");
2676 break;
2677 case 16:
2678 EMIT_ASM32 (i386_ext_16,
2679 "cwtl\n\t"
2680 "movl %eax,%ebx\n\t"
2681 "sarl $31,%ebx");
2682 break;
2683 case 32:
2684 EMIT_ASM32 (i386_ext_32,
2685 "movl %eax,%ebx\n\t"
2686 "sarl $31,%ebx");
2687 break;
2688 default:
2689 emit_error = 1;
2690 }
2691}
2692
2693static void
2694i386_emit_log_not (void)
2695{
2696 EMIT_ASM32 (i386_log_not,
2697 "or %ebx,%eax\n\t"
2698 "test %eax,%eax\n\t"
2699 "sete %cl\n\t"
2700 "xor %ebx,%ebx\n\t"
2701 "movzbl %cl,%eax");
2702}
2703
2704static void
2705i386_emit_bit_and (void)
2706{
2707 EMIT_ASM32 (i386_and,
2708 "and (%esp),%eax\n\t"
2709 "and 0x4(%esp),%ebx\n\t"
2710 "lea 0x8(%esp),%esp");
2711}
2712
2713static void
2714i386_emit_bit_or (void)
2715{
2716 EMIT_ASM32 (i386_or,
2717 "or (%esp),%eax\n\t"
2718 "or 0x4(%esp),%ebx\n\t"
2719 "lea 0x8(%esp),%esp");
2720}
2721
2722static void
2723i386_emit_bit_xor (void)
2724{
2725 EMIT_ASM32 (i386_xor,
2726 "xor (%esp),%eax\n\t"
2727 "xor 0x4(%esp),%ebx\n\t"
2728 "lea 0x8(%esp),%esp");
2729}
2730
2731static void
2732i386_emit_bit_not (void)
2733{
2734 EMIT_ASM32 (i386_bit_not,
2735 "xor $0xffffffff,%eax\n\t"
2736 "xor $0xffffffff,%ebx\n\t");
2737}
2738
2739static void
2740i386_emit_equal (void)
2741{
2742 EMIT_ASM32 (i386_equal,
2743 "cmpl %ebx,4(%esp)\n\t"
2744 "jne .Li386_equal_false\n\t"
2745 "cmpl %eax,(%esp)\n\t"
2746 "je .Li386_equal_true\n\t"
2747 ".Li386_equal_false:\n\t"
2748 "xor %eax,%eax\n\t"
2749 "jmp .Li386_equal_end\n\t"
2750 ".Li386_equal_true:\n\t"
2751 "mov $1,%eax\n\t"
2752 ".Li386_equal_end:\n\t"
2753 "xor %ebx,%ebx\n\t"
2754 "lea 0x8(%esp),%esp");
2755}
2756
2757static void
2758i386_emit_less_signed (void)
2759{
2760 EMIT_ASM32 (i386_less_signed,
2761 "cmpl %ebx,4(%esp)\n\t"
2762 "jl .Li386_less_signed_true\n\t"
2763 "jne .Li386_less_signed_false\n\t"
2764 "cmpl %eax,(%esp)\n\t"
2765 "jl .Li386_less_signed_true\n\t"
2766 ".Li386_less_signed_false:\n\t"
2767 "xor %eax,%eax\n\t"
2768 "jmp .Li386_less_signed_end\n\t"
2769 ".Li386_less_signed_true:\n\t"
2770 "mov $1,%eax\n\t"
2771 ".Li386_less_signed_end:\n\t"
2772 "xor %ebx,%ebx\n\t"
2773 "lea 0x8(%esp),%esp");
2774}
2775
2776static void
2777i386_emit_less_unsigned (void)
2778{
2779 EMIT_ASM32 (i386_less_unsigned,
2780 "cmpl %ebx,4(%esp)\n\t"
2781 "jb .Li386_less_unsigned_true\n\t"
2782 "jne .Li386_less_unsigned_false\n\t"
2783 "cmpl %eax,(%esp)\n\t"
2784 "jb .Li386_less_unsigned_true\n\t"
2785 ".Li386_less_unsigned_false:\n\t"
2786 "xor %eax,%eax\n\t"
2787 "jmp .Li386_less_unsigned_end\n\t"
2788 ".Li386_less_unsigned_true:\n\t"
2789 "mov $1,%eax\n\t"
2790 ".Li386_less_unsigned_end:\n\t"
2791 "xor %ebx,%ebx\n\t"
2792 "lea 0x8(%esp),%esp");
2793}
2794
2795static void
2796i386_emit_ref (int size)
2797{
2798 switch (size)
2799 {
2800 case 1:
2801 EMIT_ASM32 (i386_ref1,
2802 "movb (%eax),%al");
2803 break;
2804 case 2:
2805 EMIT_ASM32 (i386_ref2,
2806 "movw (%eax),%ax");
2807 break;
2808 case 4:
2809 EMIT_ASM32 (i386_ref4,
2810 "movl (%eax),%eax");
2811 break;
2812 case 8:
2813 EMIT_ASM32 (i386_ref8,
2814 "movl 4(%eax),%ebx\n\t"
2815 "movl (%eax),%eax");
2816 break;
2817 }
2818}
2819
2820static void
2821i386_emit_if_goto (int *offset_p, int *size_p)
2822{
2823 EMIT_ASM32 (i386_if_goto,
2824 "mov %eax,%ecx\n\t"
2825 "or %ebx,%ecx\n\t"
2826 "pop %eax\n\t"
2827 "pop %ebx\n\t"
2828 "cmpl $0,%ecx\n\t"
2829 /* Don't trust the assembler to choose the right jump */
2830 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2831
2832 if (offset_p)
2833 *offset_p = 11; /* be sure that this matches the sequence above */
2834 if (size_p)
2835 *size_p = 4;
2836}
2837
2838static void
2839i386_emit_goto (int *offset_p, int *size_p)
2840{
2841 EMIT_ASM32 (i386_goto,
2842 /* Don't trust the assembler to choose the right jump */
2843 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2844 if (offset_p)
2845 *offset_p = 1;
2846 if (size_p)
2847 *size_p = 4;
2848}
2849
2850static void
2851i386_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2852{
2853 int diff = (to - (from + size));
2854 unsigned char buf[sizeof (int)];
2855
2856 /* We're only doing 4-byte sizes at the moment. */
2857 if (size != 4)
2858 {
2859 emit_error = 1;
2860 return;
2861 }
2862
2863 memcpy (buf, &diff, sizeof (int));
2864 write_inferior_memory (from, buf, sizeof (int));
2865}
2866
2867static void
4e29fb54 2868i386_emit_const (LONGEST num)
6a271cae
PA		 2869{
2870 unsigned char buf[16];
b00ad6ff 2871 int i, hi, lo;
6a271cae
PA		 2872 CORE_ADDR buildaddr = current_insn_ptr;
2873
2874 i = 0;
2875 buf[i++] = 0xb8; /* mov $<n>,%eax */
b00ad6ff
NF		 2876 lo = num & 0xffffffff;
2877 memcpy (&buf[i], &lo, sizeof (lo));
6a271cae
PA		 2878 i += 4;
2879 hi = ((num >> 32) & 0xffffffff);
2880 if (hi)
2881 {
2882 buf[i++] = 0xbb; /* mov $<n>,%ebx */
b00ad6ff 2883 memcpy (&buf[i], &hi, sizeof (hi));
6a271cae
PA		 2884 i += 4;
2885 }
2886 else
2887 {
2888 buf[i++] = 0x31; buf[i++] = 0xdb; /* xor %ebx,%ebx */
2889 }
2890 append_insns (&buildaddr, i, buf);
2891 current_insn_ptr = buildaddr;
2892}
2893
2894static void
2895i386_emit_call (CORE_ADDR fn)
2896{
2897 unsigned char buf[16];
2898 int i, offset;
2899 CORE_ADDR buildaddr;
2900
2901 buildaddr = current_insn_ptr;
2902 i = 0;
2903 buf[i++] = 0xe8; /* call <reladdr> */
2904 offset = ((int) fn) - (buildaddr + 5);
2905 memcpy (buf + 1, &offset, 4);
2906 append_insns (&buildaddr, 5, buf);
2907 current_insn_ptr = buildaddr;
2908}
2909
2910static void
2911i386_emit_reg (int reg)
2912{
2913 unsigned char buf[16];
2914 int i;
2915 CORE_ADDR buildaddr;
2916
2917 EMIT_ASM32 (i386_reg_a,
2918 "sub $0x8,%esp");
2919 buildaddr = current_insn_ptr;
2920 i = 0;
2921 buf[i++] = 0xb8; /* mov $<n>,%eax */
b00ad6ff 2922 memcpy (&buf[i], &reg, sizeof (reg));
6a271cae
PA		 2923 i += 4;
2924 append_insns (&buildaddr, i, buf);
2925 current_insn_ptr = buildaddr;
2926 EMIT_ASM32 (i386_reg_b,
2927 "mov %eax,4(%esp)\n\t"
2928 "mov 8(%ebp),%eax\n\t"
2929 "mov %eax,(%esp)");
2930 i386_emit_call (get_raw_reg_func_addr ());
2931 EMIT_ASM32 (i386_reg_c,
2932 "xor %ebx,%ebx\n\t"
2933 "lea 0x8(%esp),%esp");
2934}
2935
2936static void
2937i386_emit_pop (void)
2938{
2939 EMIT_ASM32 (i386_pop,
2940 "pop %eax\n\t"
2941 "pop %ebx");
2942}
2943
2944static void
2945i386_emit_stack_flush (void)
2946{
2947 EMIT_ASM32 (i386_stack_flush,
2948 "push %ebx\n\t"
2949 "push %eax");
2950}
2951
2952static void
2953i386_emit_zero_ext (int arg)
2954{
2955 switch (arg)
2956 {
2957 case 8:
2958 EMIT_ASM32 (i386_zero_ext_8,
2959 "and $0xff,%eax\n\t"
2960 "xor %ebx,%ebx");
2961 break;
2962 case 16:
2963 EMIT_ASM32 (i386_zero_ext_16,
2964 "and $0xffff,%eax\n\t"
2965 "xor %ebx,%ebx");
2966 break;
2967 case 32:
2968 EMIT_ASM32 (i386_zero_ext_32,
2969 "xor %ebx,%ebx");
2970 break;
2971 default:
2972 emit_error = 1;
2973 }
2974}
2975
2976static void
2977i386_emit_swap (void)
2978{
2979 EMIT_ASM32 (i386_swap,
2980 "mov %eax,%ecx\n\t"
2981 "mov %ebx,%edx\n\t"
2982 "pop %eax\n\t"
2983 "pop %ebx\n\t"
2984 "push %edx\n\t"
2985 "push %ecx");
2986}
2987
2988static void
2989i386_emit_stack_adjust (int n)
2990{
2991 unsigned char buf[16];
2992 int i;
2993 CORE_ADDR buildaddr = current_insn_ptr;
2994
2995 i = 0;
2996 buf[i++] = 0x8d; /* lea $<n>(%esp),%esp */
2997 buf[i++] = 0x64;
2998 buf[i++] = 0x24;
2999 buf[i++] = n * 8;
3000 append_insns (&buildaddr, i, buf);
3001 current_insn_ptr = buildaddr;
3002}
3003
3004/* FN's prototype is `LONGEST(*fn)(int)'. */
3005
3006static void
3007i386_emit_int_call_1 (CORE_ADDR fn, int arg1)
3008{
3009 unsigned char buf[16];
3010 int i;
3011 CORE_ADDR buildaddr;
3012
3013 EMIT_ASM32 (i386_int_call_1_a,
3014 /* Reserve a bit of stack space. */
3015 "sub $0x8,%esp");
3016 /* Put the one argument on the stack. */
3017 buildaddr = current_insn_ptr;
3018 i = 0;
3019 buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */
3020 buf[i++] = 0x04;
3021 buf[i++] = 0x24;
b00ad6ff 3022 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 3023 i += 4;
3024 append_insns (&buildaddr, i, buf);
3025 current_insn_ptr = buildaddr;
3026 i386_emit_call (fn);
3027 EMIT_ASM32 (i386_int_call_1_c,
3028 "mov %edx,%ebx\n\t"
3029 "lea 0x8(%esp),%esp");
3030}
3031
4e29fb54 3032/* FN's prototype is `void(*fn)(int,LONGEST)'. */
6a271cae
PA		 3033
3034static void
3035i386_emit_void_call_2 (CORE_ADDR fn, int arg1)
3036{
3037 unsigned char buf[16];
3038 int i;
3039 CORE_ADDR buildaddr;
3040
3041 EMIT_ASM32 (i386_void_call_2_a,
3042 /* Preserve %eax only; we don't have to worry about %ebx. */
3043 "push %eax\n\t"
3044 /* Reserve a bit of stack space for arguments. */
3045 "sub $0x10,%esp\n\t"
3046 /* Copy "top" to the second argument position. (Note that
3047 we can't assume function won't scribble on its
3048 arguments, so don't try to restore from this.) */
3049 "mov %eax,4(%esp)\n\t"
3050 "mov %ebx,8(%esp)");
3051 /* Put the first argument on the stack. */
3052 buildaddr = current_insn_ptr;
3053 i = 0;
3054 buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */
3055 buf[i++] = 0x04;
3056 buf[i++] = 0x24;
b00ad6ff 3057 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 3058 i += 4;
3059 append_insns (&buildaddr, i, buf);
3060 current_insn_ptr = buildaddr;
3061 i386_emit_call (fn);
3062 EMIT_ASM32 (i386_void_call_2_b,
3063 "lea 0x10(%esp),%esp\n\t"
3064 /* Restore original stack top. */
3065 "pop %eax");
3066}
3067
6b9801d4
SS		 3068
3069void
3070i386_emit_eq_goto (int *offset_p, int *size_p)
3071{
3072 EMIT_ASM32 (eq,
3073 /* Check low half first, more likely to be decider */
3074 "cmpl %eax,(%esp)\n\t"
3075 "jne .Leq_fallthru\n\t"
3076 "cmpl %ebx,4(%esp)\n\t"
3077 "jne .Leq_fallthru\n\t"
3078 "lea 0x8(%esp),%esp\n\t"
3079 "pop %eax\n\t"
3080 "pop %ebx\n\t"
3081 /* jmp, but don't trust the assembler to choose the right jump */
3082 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3083 ".Leq_fallthru:\n\t"
3084 "lea 0x8(%esp),%esp\n\t"
3085 "pop %eax\n\t"
3086 "pop %ebx");
3087
3088 if (offset_p)
3089 *offset_p = 18;
3090 if (size_p)
3091 *size_p = 4;
3092}
3093
3094void
3095i386_emit_ne_goto (int *offset_p, int *size_p)
3096{
3097 EMIT_ASM32 (ne,
3098 /* Check low half first, more likely to be decider */
3099 "cmpl %eax,(%esp)\n\t"
3100 "jne .Lne_jump\n\t"
3101 "cmpl %ebx,4(%esp)\n\t"
3102 "je .Lne_fallthru\n\t"
3103 ".Lne_jump:\n\t"
3104 "lea 0x8(%esp),%esp\n\t"
3105 "pop %eax\n\t"
3106 "pop %ebx\n\t"
3107 /* jmp, but don't trust the assembler to choose the right jump */
3108 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3109 ".Lne_fallthru:\n\t"
3110 "lea 0x8(%esp),%esp\n\t"
3111 "pop %eax\n\t"
3112 "pop %ebx");
3113
3114 if (offset_p)
3115 *offset_p = 18;
3116 if (size_p)
3117 *size_p = 4;
3118}
3119
3120void
3121i386_emit_lt_goto (int *offset_p, int *size_p)
3122{
3123 EMIT_ASM32 (lt,
3124 "cmpl %ebx,4(%esp)\n\t"
3125 "jl .Llt_jump\n\t"
3126 "jne .Llt_fallthru\n\t"
3127 "cmpl %eax,(%esp)\n\t"
3128 "jnl .Llt_fallthru\n\t"
3129 ".Llt_jump:\n\t"
3130 "lea 0x8(%esp),%esp\n\t"
3131 "pop %eax\n\t"
3132 "pop %ebx\n\t"
3133 /* jmp, but don't trust the assembler to choose the right jump */
3134 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3135 ".Llt_fallthru:\n\t"
3136 "lea 0x8(%esp),%esp\n\t"
3137 "pop %eax\n\t"
3138 "pop %ebx");
3139
3140 if (offset_p)
3141 *offset_p = 20;
3142 if (size_p)
3143 *size_p = 4;
3144}
3145
3146void
3147i386_emit_le_goto (int *offset_p, int *size_p)
3148{
3149 EMIT_ASM32 (le,
3150 "cmpl %ebx,4(%esp)\n\t"
3151 "jle .Lle_jump\n\t"
3152 "jne .Lle_fallthru\n\t"
3153 "cmpl %eax,(%esp)\n\t"
3154 "jnle .Lle_fallthru\n\t"
3155 ".Lle_jump:\n\t"
3156 "lea 0x8(%esp),%esp\n\t"
3157 "pop %eax\n\t"
3158 "pop %ebx\n\t"
3159 /* jmp, but don't trust the assembler to choose the right jump */
3160 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3161 ".Lle_fallthru:\n\t"
3162 "lea 0x8(%esp),%esp\n\t"
3163 "pop %eax\n\t"
3164 "pop %ebx");
3165
3166 if (offset_p)
3167 *offset_p = 20;
3168 if (size_p)
3169 *size_p = 4;
3170}
3171
3172void
3173i386_emit_gt_goto (int *offset_p, int *size_p)
3174{
3175 EMIT_ASM32 (gt,
3176 "cmpl %ebx,4(%esp)\n\t"
3177 "jg .Lgt_jump\n\t"
3178 "jne .Lgt_fallthru\n\t"
3179 "cmpl %eax,(%esp)\n\t"
3180 "jng .Lgt_fallthru\n\t"
3181 ".Lgt_jump:\n\t"
3182 "lea 0x8(%esp),%esp\n\t"
3183 "pop %eax\n\t"
3184 "pop %ebx\n\t"
3185 /* jmp, but don't trust the assembler to choose the right jump */
3186 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3187 ".Lgt_fallthru:\n\t"
3188 "lea 0x8(%esp),%esp\n\t"
3189 "pop %eax\n\t"
3190 "pop %ebx");
3191
3192 if (offset_p)
3193 *offset_p = 20;
3194 if (size_p)
3195 *size_p = 4;
3196}
3197
3198void
3199i386_emit_ge_goto (int *offset_p, int *size_p)
3200{
3201 EMIT_ASM32 (ge,
3202 "cmpl %ebx,4(%esp)\n\t"
3203 "jge .Lge_jump\n\t"
3204 "jne .Lge_fallthru\n\t"
3205 "cmpl %eax,(%esp)\n\t"
3206 "jnge .Lge_fallthru\n\t"
3207 ".Lge_jump:\n\t"
3208 "lea 0x8(%esp),%esp\n\t"
3209 "pop %eax\n\t"
3210 "pop %ebx\n\t"
3211 /* jmp, but don't trust the assembler to choose the right jump */
3212 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3213 ".Lge_fallthru:\n\t"
3214 "lea 0x8(%esp),%esp\n\t"
3215 "pop %eax\n\t"
3216 "pop %ebx");
3217
3218 if (offset_p)
3219 *offset_p = 20;
3220 if (size_p)
3221 *size_p = 4;
3222}
3223
6a271cae
PA		 3224struct emit_ops i386_emit_ops =
3225 {
3226 i386_emit_prologue,
3227 i386_emit_epilogue,
3228 i386_emit_add,
3229 i386_emit_sub,
3230 i386_emit_mul,
3231 i386_emit_lsh,
3232 i386_emit_rsh_signed,
3233 i386_emit_rsh_unsigned,
3234 i386_emit_ext,
3235 i386_emit_log_not,
3236 i386_emit_bit_and,
3237 i386_emit_bit_or,
3238 i386_emit_bit_xor,
3239 i386_emit_bit_not,
3240 i386_emit_equal,
3241 i386_emit_less_signed,
3242 i386_emit_less_unsigned,
3243 i386_emit_ref,
3244 i386_emit_if_goto,
3245 i386_emit_goto,
3246 i386_write_goto_address,
3247 i386_emit_const,
3248 i386_emit_call,
3249 i386_emit_reg,
3250 i386_emit_pop,
3251 i386_emit_stack_flush,
3252 i386_emit_zero_ext,
3253 i386_emit_swap,
3254 i386_emit_stack_adjust,
3255 i386_emit_int_call_1,
6b9801d4
SS		 3256 i386_emit_void_call_2,
3257 i386_emit_eq_goto,
3258 i386_emit_ne_goto,
3259 i386_emit_lt_goto,
3260 i386_emit_le_goto,
3261 i386_emit_gt_goto,
3262 i386_emit_ge_goto
6a271cae
PA		 3263 };
3264
3265
3266static struct emit_ops *
3267x86_emit_ops (void)
3268{
3269#ifdef __x86_64__
3aee8918 3270 if (is_64bit_tdesc ())
6a271cae
PA		 3271 return &amd64_emit_ops;
3272 else
3273#endif
3274 return &i386_emit_ops;
3275}
3276
dd373349
AT		 3277/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
3278
3279static const gdb_byte *
3280x86_sw_breakpoint_from_kind (int kind, int *size)
3281{
3282 *size = x86_breakpoint_len;
3283 return x86_breakpoint;
3284}
3285
c2d6af84
PA		 3286static int
3287x86_supports_range_stepping (void)
3288{
3289 return 1;
3290}
3291
7d00775e
AT		 3292/* Implementation of linux_target_ops method "supports_hardware_single_step".
3293 */
3294
3295static int
3296x86_supports_hardware_single_step (void)
3297{
3298 return 1;
3299}
3300
d0722149
DE		 3301/* This is initialized assuming an amd64 target.
3302 x86_arch_setup will correct it for i386 or amd64 targets. */
3303
3304struct linux_target_ops the_low_target =
3305{
3306 x86_arch_setup,
3aee8918
PA		 3307 x86_linux_regs_info,
3308 x86_cannot_fetch_register,
3309 x86_cannot_store_register,
c14dfd32 3310 NULL, /* fetch_register */
d0722149
DE		 3311 x86_get_pc,
3312 x86_set_pc,
dd373349
AT		 3313 NULL, /* breakpoint_kind_from_pc */
3314 x86_sw_breakpoint_from_kind,
d0722149
DE		 3315 NULL,
3316 1,
3317 x86_breakpoint_at,
802e8e6d 3318 x86_supports_z_point_type,
aa5ca48f
DE		 3319 x86_insert_point,
3320 x86_remove_point,
3321 x86_stopped_by_watchpoint,
3322 x86_stopped_data_address,
d0722149
DE		 3323 /* collect_ptrace_register/supply_ptrace_register are not needed in the
3324 native i386 case (no registers smaller than an xfer unit), and are not
3325 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
3326 NULL,
3327 NULL,
3328 /* need to fix up i386 siginfo if host is amd64 */
3329 x86_siginfo_fixup,
aa5ca48f
DE		 3330 x86_linux_new_process,
3331 x86_linux_new_thread,
3a8a0396 3332 x86_linux_new_fork,
1570b33e 3333 x86_linux_prepare_to_resume,
219f2f23 3334 x86_linux_process_qsupported,
fa593d66
PA		 3335 x86_supports_tracepoints,
3336 x86_get_thread_area,
6a271cae 3337 x86_install_fast_tracepoint_jump_pad,
405f8e94
SS		 3338 x86_emit_ops,
3339 x86_get_min_fast_tracepoint_insn_len,
c2d6af84 3340 x86_supports_range_stepping,
7d00775e
AT		 3341 NULL, /* breakpoint_kind_from_current_state */
3342 x86_supports_hardware_single_step,
82075af2 3343 x86_get_syscall_trapinfo,
d0722149 3344};
3aee8918
PA		 3345
3346void
3347initialize_low_arch (void)
3348{
3349 /* Initialize the Linux target descriptions. */
3350#ifdef __x86_64__
3351 init_registers_amd64_linux ();
3352 init_registers_amd64_avx_linux ();
01f9f808 3353 init_registers_amd64_avx512_linux ();
a196ebeb
WT		 3354 init_registers_amd64_mpx_linux ();
3355
3aee8918 3356 init_registers_x32_linux ();
7e5aaa09 3357 init_registers_x32_avx_linux ();
01f9f808 3358 init_registers_x32_avx512_linux ();
3aee8918 3359
8d749320 3360 tdesc_amd64_linux_no_xml = XNEW (struct target_desc);
3aee8918
PA		 3361 copy_target_description (tdesc_amd64_linux_no_xml, tdesc_amd64_linux);
3362 tdesc_amd64_linux_no_xml->xmltarget = xmltarget_amd64_linux_no_xml;
3363#endif
3364 init_registers_i386_linux ();
3365 init_registers_i386_mmx_linux ();
3366 init_registers_i386_avx_linux ();
01f9f808 3367 init_registers_i386_avx512_linux ();
a196ebeb 3368 init_registers_i386_mpx_linux ();
3aee8918 3369
8d749320 3370 tdesc_i386_linux_no_xml = XNEW (struct target_desc);
3aee8918
PA		 3371 copy_target_description (tdesc_i386_linux_no_xml, tdesc_i386_linux);
3372 tdesc_i386_linux_no_xml->xmltarget = xmltarget_i386_linux_no_xml;
3373
3374 initialize_regsets_info (&x86_regsets_info);
3375}
GDB Binutils - Deliverables
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