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Align behavior of xmethod commands with that of pretty-printer commands.
[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-x86-low.c
CommitLineData
d0722149
DE		 1/* GNU/Linux/x86-64 specific low level interface, for the remote server
2 for GDB.
ecd75fc8 3 Copyright (C) 2002-2014 Free Software Foundation, Inc.
d0722149
DE		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
aa5ca48f 20#include <stddef.h>
d0722149 21#include <signal.h>
6a271cae 22#include <limits.h>
f4647387 23#include <inttypes.h>
d0722149
DE		 24#include "server.h"
25#include "linux-low.h"
26#include "i387-fp.h"
aa5ca48f 27#include "i386-low.h"
1570b33e 28#include "i386-xstate.h"
d0722149
DE		 29
30#include "gdb_proc_service.h"
b5737fa9
PA		 31/* Don't include elf/common.h if linux/elf.h got included by
32 gdb_proc_service.h. */
33#ifndef ELFMAG0
34#include "elf/common.h"
35#endif
36
58b4daa5 37#include "agent.h"
3aee8918 38#include "tdesc.h"
c144c7a0 39#include "tracepoint.h"
f699aaba 40#include "ax.h"
d0722149 41
3aee8918 42#ifdef __x86_64__
90884b2b
L		 43/* Defined in auto-generated file amd64-linux.c. */
44void init_registers_amd64_linux (void);
3aee8918
PA		 45extern const struct target_desc *tdesc_amd64_linux;
46
1570b33e
L		 47/* Defined in auto-generated file amd64-avx-linux.c. */
48void init_registers_amd64_avx_linux (void);
3aee8918
PA		 49extern const struct target_desc *tdesc_amd64_avx_linux;
50
01f9f808
MS		 51/* Defined in auto-generated file amd64-avx512-linux.c. */
52void init_registers_amd64_avx512_linux (void);
53extern const struct target_desc *tdesc_amd64_avx512_linux;
54
a196ebeb
WT		 55/* Defined in auto-generated file amd64-mpx-linux.c. */
56void init_registers_amd64_mpx_linux (void);
57extern const struct target_desc *tdesc_amd64_mpx_linux;
58
4d47af5c
L		 59/* Defined in auto-generated file x32-linux.c. */
60void init_registers_x32_linux (void);
3aee8918
PA		 61extern const struct target_desc *tdesc_x32_linux;
62
4d47af5c
L		 63/* Defined in auto-generated file x32-avx-linux.c. */
64void init_registers_x32_avx_linux (void);
3aee8918 65extern const struct target_desc *tdesc_x32_avx_linux;
a196ebeb 66
01f9f808
MS		 67/* Defined in auto-generated file x32-avx512-linux.c. */
68void init_registers_x32_avx512_linux (void);
69extern const struct target_desc *tdesc_x32_avx512_linux;
70
3aee8918
PA		 71#endif
72
73/* Defined in auto-generated file i386-linux.c. */
74void init_registers_i386_linux (void);
75extern const struct target_desc *tdesc_i386_linux;
76
77/* Defined in auto-generated file i386-mmx-linux.c. */
78void init_registers_i386_mmx_linux (void);
79extern const struct target_desc *tdesc_i386_mmx_linux;
80
81/* Defined in auto-generated file i386-avx-linux.c. */
82void init_registers_i386_avx_linux (void);
83extern const struct target_desc *tdesc_i386_avx_linux;
84
01f9f808
MS		 85/* Defined in auto-generated file i386-avx512-linux.c. */
86void init_registers_i386_avx512_linux (void);
87extern const struct target_desc *tdesc_i386_avx512_linux;
88
a196ebeb
WT		 89/* Defined in auto-generated file i386-mpx-linux.c. */
90void init_registers_i386_mpx_linux (void);
91extern const struct target_desc *tdesc_i386_mpx_linux;
92
3aee8918
PA		 93#ifdef __x86_64__
94static struct target_desc *tdesc_amd64_linux_no_xml;
95#endif
96static struct target_desc *tdesc_i386_linux_no_xml;
97
1570b33e 98
fa593d66 99static unsigned char jump_insn[] = { 0xe9, 0, 0, 0, 0 };
405f8e94 100static unsigned char small_jump_insn[] = { 0x66, 0xe9, 0, 0 };
fa593d66 101
1570b33e
L		 102/* Backward compatibility for gdb without XML support. */
103
104static const char *xmltarget_i386_linux_no_xml = "@<target>\
105<architecture>i386</architecture>\
106<osabi>GNU/Linux</osabi>\
107</target>";
f6d1620c
L		 108
109#ifdef __x86_64__
1570b33e
L		 110static const char *xmltarget_amd64_linux_no_xml = "@<target>\
111<architecture>i386:x86-64</architecture>\
112<osabi>GNU/Linux</osabi>\
113</target>";
f6d1620c 114#endif
d0722149
DE		 115
116#include <sys/reg.h>
117#include <sys/procfs.h>
118#include <sys/ptrace.h>
1570b33e
L		 119#include <sys/uio.h>
120
121#ifndef PTRACE_GETREGSET
122#define PTRACE_GETREGSET 0x4204
123#endif
124
125#ifndef PTRACE_SETREGSET
126#define PTRACE_SETREGSET 0x4205
127#endif
128
d0722149
DE		 129
130#ifndef PTRACE_GET_THREAD_AREA
131#define PTRACE_GET_THREAD_AREA 25
132#endif
133
134/* This definition comes from prctl.h, but some kernels may not have it. */
135#ifndef PTRACE_ARCH_PRCTL
136#define PTRACE_ARCH_PRCTL 30
137#endif
138
139/* The following definitions come from prctl.h, but may be absent
140 for certain configurations. */
141#ifndef ARCH_GET_FS
142#define ARCH_SET_GS 0x1001
143#define ARCH_SET_FS 0x1002
144#define ARCH_GET_FS 0x1003
145#define ARCH_GET_GS 0x1004
146#endif
147
aa5ca48f
DE		 148/* Per-process arch-specific data we want to keep. */
149
150struct arch_process_info
151{
152 struct i386_debug_reg_state debug_reg_state;
153};
154
155/* Per-thread arch-specific data we want to keep. */
156
157struct arch_lwp_info
158{
159 /* Non-zero if our copy differs from what's recorded in the thread. */
160 int debug_registers_changed;
161};
162
d0722149
DE		 163#ifdef __x86_64__
164
165/* Mapping between the general-purpose registers in `struct user'
166 format and GDB's register array layout.
167 Note that the transfer layout uses 64-bit regs. */
168static /*const*/ int i386_regmap[] =
169{
170 RAX * 8, RCX * 8, RDX * 8, RBX * 8,
171 RSP * 8, RBP * 8, RSI * 8, RDI * 8,
172 RIP * 8, EFLAGS * 8, CS * 8, SS * 8,
173 DS * 8, ES * 8, FS * 8, GS * 8
174};
175
176#define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
177
178/* So code below doesn't have to care, i386 or amd64. */
179#define ORIG_EAX ORIG_RAX
180
181static const int x86_64_regmap[] =
182{
183 RAX * 8, RBX * 8, RCX * 8, RDX * 8,
184 RSI * 8, RDI * 8, RBP * 8, RSP * 8,
185 R8 * 8, R9 * 8, R10 * 8, R11 * 8,
186 R12 * 8, R13 * 8, R14 * 8, R15 * 8,
187 RIP * 8, EFLAGS * 8, CS * 8, SS * 8,
188 DS * 8, ES * 8, FS * 8, GS * 8,
189 -1, -1, -1, -1, -1, -1, -1, -1,
190 -1, -1, -1, -1, -1, -1, -1, -1,
191 -1, -1, -1, -1, -1, -1, -1, -1,
a196ebeb
WT		 192 -1,
193 -1, -1, -1, -1, -1, -1, -1, -1,
194 ORIG_RAX * 8,
195 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
01f9f808
MS		 196 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
197 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
198 -1, -1, -1, -1, -1, -1, -1, -1,
199 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
200 -1, -1, -1, -1, -1, -1, -1, -1,
201 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
202 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
203 -1, -1, -1, -1, -1, -1, -1, -1,
204 -1, -1, -1, -1, -1, -1, -1, -1,
205 -1, -1, -1, -1, -1, -1, -1, -1
d0722149
DE		 206};
207
208#define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
9e0aa64f 209#define X86_64_USER_REGS (GS + 1)
d0722149
DE		 210
211#else /* ! __x86_64__ */
212
213/* Mapping between the general-purpose registers in `struct user'
214 format and GDB's register array layout. */
215static /*const*/ int i386_regmap[] =
216{
217 EAX * 4, ECX * 4, EDX * 4, EBX * 4,
218 UESP * 4, EBP * 4, ESI * 4, EDI * 4,
219 EIP * 4, EFL * 4, CS * 4, SS * 4,
220 DS * 4, ES * 4, FS * 4, GS * 4
221};
222
223#define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
224
225#endif
3aee8918
PA		 226
227#ifdef __x86_64__
228
229/* Returns true if the current inferior belongs to a x86-64 process,
230 per the tdesc. */
231
232static int
233is_64bit_tdesc (void)
234{
235 struct regcache *regcache = get_thread_regcache (current_inferior, 0);
236
237 return register_size (regcache->tdesc, 0) == 8;
238}
239
240#endif
241
d0722149
DE		 242\f
243/* Called by libthread_db. */
244
245ps_err_e
246ps_get_thread_area (const struct ps_prochandle *ph,
247 lwpid_t lwpid, int idx, void **base)
248{
249#ifdef __x86_64__
3aee8918 250 int use_64bit = is_64bit_tdesc ();
d0722149
DE		 251
252 if (use_64bit)
253 {
254 switch (idx)
255 {
256 case FS:
257 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_FS) == 0)
258 return PS_OK;
259 break;
260 case GS:
261 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_GS) == 0)
262 return PS_OK;
263 break;
264 default:
265 return PS_BADADDR;
266 }
267 return PS_ERR;
268 }
269#endif
270
271 {
272 unsigned int desc[4];
273
274 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid,
275 (void *) (intptr_t) idx, (unsigned long) &desc) < 0)
276 return PS_ERR;
277
d1ec4ce7
DE		 278 /* Ensure we properly extend the value to 64-bits for x86_64. */
279 *base = (void *) (uintptr_t) desc[1];
d0722149
DE		 280 return PS_OK;
281 }
282}
fa593d66
PA		 283
284/* Get the thread area address. This is used to recognize which
285 thread is which when tracing with the in-process agent library. We
286 don't read anything from the address, and treat it as opaque; it's
287 the address itself that we assume is unique per-thread. */
288
289static int
290x86_get_thread_area (int lwpid, CORE_ADDR *addr)
291{
292#ifdef __x86_64__
3aee8918 293 int use_64bit = is_64bit_tdesc ();
fa593d66
PA		 294
295 if (use_64bit)
296 {
297 void *base;
298 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_FS) == 0)
299 {
300 *addr = (CORE_ADDR) (uintptr_t) base;
301 return 0;
302 }
303
304 return -1;
305 }
306#endif
307
308 {
309 struct lwp_info *lwp = find_lwp_pid (pid_to_ptid (lwpid));
d86d4aaf
DE		 310 struct thread_info *thr = get_lwp_thread (lwp);
311 struct regcache *regcache = get_thread_regcache (thr, 1);
fa593d66
PA		 312 unsigned int desc[4];
313 ULONGEST gs = 0;
314 const int reg_thread_area = 3; /* bits to scale down register value. */
315 int idx;
316
317 collect_register_by_name (regcache, "gs", &gs);
318
319 idx = gs >> reg_thread_area;
320
321 if (ptrace (PTRACE_GET_THREAD_AREA,
d86d4aaf 322 lwpid_of (thr),
493e2a69 323 (void *) (long) idx, (unsigned long) &desc) < 0)
fa593d66
PA		 324 return -1;
325
326 *addr = desc[1];
327 return 0;
328 }
329}
330
331
d0722149
DE		 332\f
333static int
3aee8918 334x86_cannot_store_register (int regno)
d0722149 335{
3aee8918
PA		 336#ifdef __x86_64__
337 if (is_64bit_tdesc ())
338 return 0;
339#endif
340
d0722149
DE		 341 return regno >= I386_NUM_REGS;
342}
343
344static int
3aee8918 345x86_cannot_fetch_register (int regno)
d0722149 346{
3aee8918
PA		 347#ifdef __x86_64__
348 if (is_64bit_tdesc ())
349 return 0;
350#endif
351
d0722149
DE		 352 return regno >= I386_NUM_REGS;
353}
354
355static void
442ea881 356x86_fill_gregset (struct regcache *regcache, void *buf)
d0722149
DE		 357{
358 int i;
359
360#ifdef __x86_64__
3aee8918 361 if (register_size (regcache->tdesc, 0) == 8)
d0722149
DE		 362 {
363 for (i = 0; i < X86_64_NUM_REGS; i++)
364 if (x86_64_regmap[i] != -1)
442ea881 365 collect_register (regcache, i, ((char *) buf) + x86_64_regmap[i]);
d0722149
DE		 366 return;
367 }
9e0aa64f
JK		 368
369 /* 32-bit inferior registers need to be zero-extended.
370 Callers would read uninitialized memory otherwise. */
371 memset (buf, 0x00, X86_64_USER_REGS * 8);
d0722149
DE		 372#endif
373
374 for (i = 0; i < I386_NUM_REGS; i++)
442ea881 375 collect_register (regcache, i, ((char *) buf) + i386_regmap[i]);
d0722149 376
442ea881
PA		 377 collect_register_by_name (regcache, "orig_eax",
378 ((char *) buf) + ORIG_EAX * 4);
d0722149
DE		 379}
380
381static void
442ea881 382x86_store_gregset (struct regcache *regcache, const void *buf)
d0722149
DE		 383{
384 int i;
385
386#ifdef __x86_64__
3aee8918 387 if (register_size (regcache->tdesc, 0) == 8)
d0722149
DE		 388 {
389 for (i = 0; i < X86_64_NUM_REGS; i++)
390 if (x86_64_regmap[i] != -1)
442ea881 391 supply_register (regcache, i, ((char *) buf) + x86_64_regmap[i]);
d0722149
DE		 392 return;
393 }
394#endif
395
396 for (i = 0; i < I386_NUM_REGS; i++)
442ea881 397 supply_register (regcache, i, ((char *) buf) + i386_regmap[i]);
d0722149 398
442ea881
PA		 399 supply_register_by_name (regcache, "orig_eax",
400 ((char *) buf) + ORIG_EAX * 4);
d0722149
DE		 401}
402
403static void
442ea881 404x86_fill_fpregset (struct regcache *regcache, void *buf)
d0722149
DE		 405{
406#ifdef __x86_64__
442ea881 407 i387_cache_to_fxsave (regcache, buf);
d0722149 408#else
442ea881 409 i387_cache_to_fsave (regcache, buf);
d0722149
DE		 410#endif
411}
412
413static void
442ea881 414x86_store_fpregset (struct regcache *regcache, const void *buf)
d0722149
DE		 415{
416#ifdef __x86_64__
442ea881 417 i387_fxsave_to_cache (regcache, buf);
d0722149 418#else
442ea881 419 i387_fsave_to_cache (regcache, buf);
d0722149
DE		 420#endif
421}
422
423#ifndef __x86_64__
424
425static void
442ea881 426x86_fill_fpxregset (struct regcache *regcache, void *buf)
d0722149 427{
442ea881 428 i387_cache_to_fxsave (regcache, buf);
d0722149
DE		 429}
430
431static void
442ea881 432x86_store_fpxregset (struct regcache *regcache, const void *buf)
d0722149 433{
442ea881 434 i387_fxsave_to_cache (regcache, buf);
d0722149
DE		 435}
436
437#endif
438
1570b33e
L		 439static void
440x86_fill_xstateregset (struct regcache *regcache, void *buf)
441{
442 i387_cache_to_xsave (regcache, buf);
443}
444
445static void
446x86_store_xstateregset (struct regcache *regcache, const void *buf)
447{
448 i387_xsave_to_cache (regcache, buf);
449}
450
d0722149
DE		 451/* ??? The non-biarch i386 case stores all the i387 regs twice.
452 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
453 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
454 doesn't work. IWBN to avoid the duplication in the case where it
455 does work. Maybe the arch_setup routine could check whether it works
3aee8918 456 and update the supported regsets accordingly. */
d0722149 457
3aee8918 458static struct regset_info x86_regsets[] =
d0722149
DE		 459{
460#ifdef HAVE_PTRACE_GETREGS
1570b33e 461 { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t),
d0722149
DE		 462 GENERAL_REGS,
463 x86_fill_gregset, x86_store_gregset },
1570b33e
L		 464 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_X86_XSTATE, 0,
465 EXTENDED_REGS, x86_fill_xstateregset, x86_store_xstateregset },
d0722149
DE		 466# ifndef __x86_64__
467# ifdef HAVE_PTRACE_GETFPXREGS
1570b33e 468 { PTRACE_GETFPXREGS, PTRACE_SETFPXREGS, 0, sizeof (elf_fpxregset_t),
d0722149
DE		 469 EXTENDED_REGS,
470 x86_fill_fpxregset, x86_store_fpxregset },
471# endif
472# endif
1570b33e 473 { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, sizeof (elf_fpregset_t),
d0722149
DE		 474 FP_REGS,
475 x86_fill_fpregset, x86_store_fpregset },
476#endif /* HAVE_PTRACE_GETREGS */
1570b33e 477 { 0, 0, 0, -1, -1, NULL, NULL }
d0722149
DE		 478};
479
480static CORE_ADDR
442ea881 481x86_get_pc (struct regcache *regcache)
d0722149 482{
3aee8918 483 int use_64bit = register_size (regcache->tdesc, 0) == 8;
d0722149
DE		 484
485 if (use_64bit)
486 {
487 unsigned long pc;
442ea881 488 collect_register_by_name (regcache, "rip", &pc);
d0722149
DE		 489 return (CORE_ADDR) pc;
490 }
491 else
492 {
493 unsigned int pc;
442ea881 494 collect_register_by_name (regcache, "eip", &pc);
d0722149
DE		 495 return (CORE_ADDR) pc;
496 }
497}
498
499static void
442ea881 500x86_set_pc (struct regcache *regcache, CORE_ADDR pc)
d0722149 501{
3aee8918 502 int use_64bit = register_size (regcache->tdesc, 0) == 8;
d0722149
DE		 503
504 if (use_64bit)
505 {
506 unsigned long newpc = pc;
442ea881 507 supply_register_by_name (regcache, "rip", &newpc);
d0722149
DE		 508 }
509 else
510 {
511 unsigned int newpc = pc;
442ea881 512 supply_register_by_name (regcache, "eip", &newpc);
d0722149
DE		 513 }
514}
515\f
516static const unsigned char x86_breakpoint[] = { 0xCC };
517#define x86_breakpoint_len 1
518
519static int
520x86_breakpoint_at (CORE_ADDR pc)
521{
522 unsigned char c;
523
fc7238bb 524 (*the_target->read_memory) (pc, &c, 1);
d0722149
DE		 525 if (c == 0xCC)
526 return 1;
527
528 return 0;
529}
530\f
aa5ca48f
DE		 531/* Support for debug registers. */
532
533static unsigned long
534x86_linux_dr_get (ptid_t ptid, int regnum)
535{
536 int tid;
537 unsigned long value;
538
539 tid = ptid_get_lwp (ptid);
540
541 errno = 0;
542 value = ptrace (PTRACE_PEEKUSER, tid,
543 offsetof (struct user, u_debugreg[regnum]), 0);
544 if (errno != 0)
545 error ("Couldn't read debug register");
546
547 return value;
548}
549
550static void
551x86_linux_dr_set (ptid_t ptid, int regnum, unsigned long value)
552{
553 int tid;
554
555 tid = ptid_get_lwp (ptid);
556
557 errno = 0;
558 ptrace (PTRACE_POKEUSER, tid,
559 offsetof (struct user, u_debugreg[regnum]), value);
560 if (errno != 0)
561 error ("Couldn't write debug register");
562}
563
964e4306
PA		 564static int
565update_debug_registers_callback (struct inferior_list_entry *entry,
566 void *pid_p)
567{
d86d4aaf
DE		 568 struct thread_info *thr = (struct thread_info *) entry;
569 struct lwp_info *lwp = get_thread_lwp (thr);
964e4306
PA		 570 int pid = *(int *) pid_p;
571
572 /* Only update the threads of this process. */
d86d4aaf 573 if (pid_of (thr) == pid)
964e4306
PA		 574 {
575 /* The actual update is done later just before resuming the lwp,
576 we just mark that the registers need updating. */
577 lwp->arch_private->debug_registers_changed = 1;
578
579 /* If the lwp isn't stopped, force it to momentarily pause, so
580 we can update its debug registers. */
581 if (!lwp->stopped)
582 linux_stop_lwp (lwp);
583 }
584
585 return 0;
586}
587
aa5ca48f
DE		 588/* Update the inferior's debug register REGNUM from STATE. */
589
42995dbd
GB		 590static void
591i386_dr_low_set_addr (int regnum, CORE_ADDR addr)
aa5ca48f 592{
964e4306 593 /* Only update the threads of this process. */
d86d4aaf 594 int pid = pid_of (current_inferior);
aa5ca48f
DE		 595
596 if (! (regnum >= 0 && regnum <= DR_LASTADDR - DR_FIRSTADDR))
597 fatal ("Invalid debug register %d", regnum);
598
d86d4aaf 599 find_inferior (&all_threads, update_debug_registers_callback, &pid);
964e4306 600}
aa5ca48f 601
964e4306 602/* Return the inferior's debug register REGNUM. */
aa5ca48f 603
42995dbd 604static CORE_ADDR
964e4306
PA		 605i386_dr_low_get_addr (int regnum)
606{
d86d4aaf 607 ptid_t ptid = ptid_of (current_inferior);
964e4306
PA		 608
609 /* DR6 and DR7 are retrieved with some other way. */
0a5b1e09 610 gdb_assert (DR_FIRSTADDR <= regnum && regnum <= DR_LASTADDR);
964e4306
PA		 611
612 return x86_linux_dr_get (ptid, regnum);
aa5ca48f
DE		 613}
614
615/* Update the inferior's DR7 debug control register from STATE. */
616
42995dbd
GB		 617static void
618i386_dr_low_set_control (unsigned long control)
aa5ca48f 619{
964e4306 620 /* Only update the threads of this process. */
d86d4aaf 621 int pid = pid_of (current_inferior);
aa5ca48f 622
d86d4aaf 623 find_inferior (&all_threads, update_debug_registers_callback, &pid);
964e4306 624}
aa5ca48f 625
964e4306
PA		 626/* Return the inferior's DR7 debug control register. */
627
42995dbd 628static unsigned long
964e4306
PA		 629i386_dr_low_get_control (void)
630{
d86d4aaf 631 ptid_t ptid = ptid_of (current_inferior);
964e4306
PA		 632
633 return x86_linux_dr_get (ptid, DR_CONTROL);
aa5ca48f
DE		 634}
635
636/* Get the value of the DR6 debug status register from the inferior
637 and record it in STATE. */
638
42995dbd 639static unsigned long
964e4306 640i386_dr_low_get_status (void)
aa5ca48f 641{
d86d4aaf 642 ptid_t ptid = ptid_of (current_inferior);
aa5ca48f 643
964e4306 644 return x86_linux_dr_get (ptid, DR_STATUS);
aa5ca48f 645}
42995dbd
GB		 646
647/* Low-level function vector. */
648struct i386_dr_low_type i386_dr_low =
649 {
650 i386_dr_low_set_control,
651 i386_dr_low_set_addr,
652 i386_dr_low_get_addr,
653 i386_dr_low_get_status,
654 i386_dr_low_get_control,
655 sizeof (void *),
656 };
aa5ca48f 657\f
90d74c30 658/* Breakpoint/Watchpoint support. */
aa5ca48f
DE		 659
660static int
802e8e6d
PA		 661x86_supports_z_point_type (char z_type)
662{
663 switch (z_type)
664 {
665 case Z_PACKET_SW_BP:
666 case Z_PACKET_HW_BP:
667 case Z_PACKET_WRITE_WP:
668 case Z_PACKET_ACCESS_WP:
669 return 1;
670 default:
671 return 0;
672 }
673}
674
675static int
676x86_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
677 int size, struct raw_breakpoint *bp)
aa5ca48f
DE		 678{
679 struct process_info *proc = current_process ();
802e8e6d 680
aa5ca48f
DE		 681 switch (type)
682 {
802e8e6d
PA		 683 case raw_bkpt_type_sw:
684 return insert_memory_breakpoint (bp);
685
686 case raw_bkpt_type_hw:
687 case raw_bkpt_type_write_wp:
688 case raw_bkpt_type_access_wp:
a4165e94 689 {
802e8e6d
PA		 690 enum target_hw_bp_type hw_type
691 = raw_bkpt_type_to_target_hw_bp_type (type);
a4165e94
PA		 692 struct i386_debug_reg_state *state
693 = &proc->private->arch_private->debug_reg_state;
694
4be83cc2 695 return i386_dr_insert_watchpoint (state, hw_type, addr, size);
a4165e94 696 }
961bd387 697
aa5ca48f
DE		 698 default:
699 /* Unsupported. */
700 return 1;
701 }
702}
703
704static int
802e8e6d
PA		 705x86_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
706 int size, struct raw_breakpoint *bp)
aa5ca48f
DE		 707{
708 struct process_info *proc = current_process ();
802e8e6d 709
aa5ca48f
DE		 710 switch (type)
711 {
802e8e6d
PA		 712 case raw_bkpt_type_sw:
713 return remove_memory_breakpoint (bp);
714
715 case raw_bkpt_type_hw:
716 case raw_bkpt_type_write_wp:
717 case raw_bkpt_type_access_wp:
a4165e94 718 {
802e8e6d
PA		 719 enum target_hw_bp_type hw_type
720 = raw_bkpt_type_to_target_hw_bp_type (type);
a4165e94
PA		 721 struct i386_debug_reg_state *state
722 = &proc->private->arch_private->debug_reg_state;
723
4be83cc2 724 return i386_dr_remove_watchpoint (state, hw_type, addr, size);
a4165e94 725 }
aa5ca48f
DE		 726 default:
727 /* Unsupported. */
728 return 1;
729 }
730}
731
732static int
733x86_stopped_by_watchpoint (void)
734{
735 struct process_info *proc = current_process ();
4be83cc2 736 return i386_dr_stopped_by_watchpoint (&proc->private->arch_private->debug_reg_state);
aa5ca48f
DE		 737}
738
739static CORE_ADDR
740x86_stopped_data_address (void)
741{
742 struct process_info *proc = current_process ();
743 CORE_ADDR addr;
4be83cc2
GB		 744 if (i386_dr_stopped_data_address (&proc->private->arch_private->debug_reg_state,
745 &addr))
aa5ca48f
DE		 746 return addr;
747 return 0;
748}
749\f
750/* Called when a new process is created. */
751
752static struct arch_process_info *
753x86_linux_new_process (void)
754{
755 struct arch_process_info *info = xcalloc (1, sizeof (*info));
756
757 i386_low_init_dregs (&info->debug_reg_state);
758
759 return info;
760}
761
762/* Called when a new thread is detected. */
763
764static struct arch_lwp_info *
765x86_linux_new_thread (void)
766{
767 struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
768
769 info->debug_registers_changed = 1;
770
771 return info;
772}
773
774/* Called when resuming a thread.
775 If the debug regs have changed, update the thread's copies. */
776
777static void
778x86_linux_prepare_to_resume (struct lwp_info *lwp)
779{
d86d4aaf 780 ptid_t ptid = ptid_of (get_lwp_thread (lwp));
6210a125 781 int clear_status = 0;
b9a881c2 782
aa5ca48f
DE		 783 if (lwp->arch_private->debug_registers_changed)
784 {
785 int i;
aa5ca48f
DE		 786 int pid = ptid_get_pid (ptid);
787 struct process_info *proc = find_process_pid (pid);
493e2a69
MS		 788 struct i386_debug_reg_state *state
789 = &proc->private->arch_private->debug_reg_state;
aa5ca48f
DE		 790
791 for (i = DR_FIRSTADDR; i <= DR_LASTADDR; i++)
6210a125
PA		 792 if (state->dr_ref_count[i] > 0)
793 {
794 x86_linux_dr_set (ptid, i, state->dr_mirror[i]);
795
796 /* If we're setting a watchpoint, any change the inferior
797 had done itself to the debug registers needs to be
4be83cc2 798 discarded, otherwise, i386_dr_stopped_data_address can
6210a125
PA		 799 get confused. */
800 clear_status = 1;
801 }
aa5ca48f
DE		 802
803 x86_linux_dr_set (ptid, DR_CONTROL, state->dr_control_mirror);
804
805 lwp->arch_private->debug_registers_changed = 0;
806 }
b9a881c2 807
6210a125 808 if (clear_status || lwp->stopped_by_watchpoint)
b9a881c2 809 x86_linux_dr_set (ptid, DR_STATUS, 0);
aa5ca48f
DE		 810}
811\f
d0722149
DE		 812/* When GDBSERVER is built as a 64-bit application on linux, the
813 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
814 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
815 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
816 conversion in-place ourselves. */
817
818/* These types below (compat_*) define a siginfo type that is layout
819 compatible with the siginfo type exported by the 32-bit userspace
820 support. */
821
822#ifdef __x86_64__
823
824typedef int compat_int_t;
825typedef unsigned int compat_uptr_t;
826
827typedef int compat_time_t;
828typedef int compat_timer_t;
829typedef int compat_clock_t;
830
831struct compat_timeval
832{
833 compat_time_t tv_sec;
834 int tv_usec;
835};
836
837typedef union compat_sigval
838{
839 compat_int_t sival_int;
840 compat_uptr_t sival_ptr;
841} compat_sigval_t;
842
843typedef struct compat_siginfo
844{
845 int si_signo;
846 int si_errno;
847 int si_code;
848
849 union
850 {
851 int _pad[((128 / sizeof (int)) - 3)];
852
853 /* kill() */
854 struct
855 {
856 unsigned int _pid;
857 unsigned int _uid;
858 } _kill;
859
860 /* POSIX.1b timers */
861 struct
862 {
863 compat_timer_t _tid;
864 int _overrun;
865 compat_sigval_t _sigval;
866 } _timer;
867
868 /* POSIX.1b signals */
869 struct
870 {
871 unsigned int _pid;
872 unsigned int _uid;
873 compat_sigval_t _sigval;
874 } _rt;
875
876 /* SIGCHLD */
877 struct
878 {
879 unsigned int _pid;
880 unsigned int _uid;
881 int _status;
882 compat_clock_t _utime;
883 compat_clock_t _stime;
884 } _sigchld;
885
886 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
887 struct
888 {
889 unsigned int _addr;
890 } _sigfault;
891
892 /* SIGPOLL */
893 struct
894 {
895 int _band;
896 int _fd;
897 } _sigpoll;
898 } _sifields;
899} compat_siginfo_t;
900
c92b5177
L		 901/* For x32, clock_t in _sigchld is 64bit aligned at 4 bytes. */
902typedef long __attribute__ ((__aligned__ (4))) compat_x32_clock_t;
903
904typedef struct compat_x32_siginfo
905{
906 int si_signo;
907 int si_errno;
908 int si_code;
909
910 union
911 {
912 int _pad[((128 / sizeof (int)) - 3)];
913
914 /* kill() */
915 struct
916 {
917 unsigned int _pid;
918 unsigned int _uid;
919 } _kill;
920
921 /* POSIX.1b timers */
922 struct
923 {
924 compat_timer_t _tid;
925 int _overrun;
926 compat_sigval_t _sigval;
927 } _timer;
928
929 /* POSIX.1b signals */
930 struct
931 {
932 unsigned int _pid;
933 unsigned int _uid;
934 compat_sigval_t _sigval;
935 } _rt;
936
937 /* SIGCHLD */
938 struct
939 {
940 unsigned int _pid;
941 unsigned int _uid;
942 int _status;
943 compat_x32_clock_t _utime;
944 compat_x32_clock_t _stime;
945 } _sigchld;
946
947 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
948 struct
949 {
950 unsigned int _addr;
951 } _sigfault;
952
953 /* SIGPOLL */
954 struct
955 {
956 int _band;
957 int _fd;
958 } _sigpoll;
959 } _sifields;
960} compat_x32_siginfo_t __attribute__ ((__aligned__ (8)));
961
d0722149
DE		 962#define cpt_si_pid _sifields._kill._pid
963#define cpt_si_uid _sifields._kill._uid
964#define cpt_si_timerid _sifields._timer._tid
965#define cpt_si_overrun _sifields._timer._overrun
966#define cpt_si_status _sifields._sigchld._status
967#define cpt_si_utime _sifields._sigchld._utime
968#define cpt_si_stime _sifields._sigchld._stime
969#define cpt_si_ptr _sifields._rt._sigval.sival_ptr
970#define cpt_si_addr _sifields._sigfault._addr
971#define cpt_si_band _sifields._sigpoll._band
972#define cpt_si_fd _sifields._sigpoll._fd
973
974/* glibc at least up to 2.3.2 doesn't have si_timerid, si_overrun.
975 In their place is si_timer1,si_timer2. */
976#ifndef si_timerid
977#define si_timerid si_timer1
978#endif
979#ifndef si_overrun
980#define si_overrun si_timer2
981#endif
982
983static void
984compat_siginfo_from_siginfo (compat_siginfo_t *to, siginfo_t *from)
985{
986 memset (to, 0, sizeof (*to));
987
988 to->si_signo = from->si_signo;
989 to->si_errno = from->si_errno;
990 to->si_code = from->si_code;
991
b53a1623 992 if (to->si_code == SI_TIMER)
d0722149 993 {
b53a1623
PA		 994 to->cpt_si_timerid = from->si_timerid;
995 to->cpt_si_overrun = from->si_overrun;
d0722149
DE		 996 to->cpt_si_ptr = (intptr_t) from->si_ptr;
997 }
998 else if (to->si_code == SI_USER)
999 {
1000 to->cpt_si_pid = from->si_pid;
1001 to->cpt_si_uid = from->si_uid;
1002 }
b53a1623 1003 else if (to->si_code < 0)
d0722149 1004 {
b53a1623
PA		 1005 to->cpt_si_pid = from->si_pid;
1006 to->cpt_si_uid = from->si_uid;
d0722149
DE		 1007 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1008 }
1009 else
1010 {
1011 switch (to->si_signo)
1012 {
1013 case SIGCHLD:
1014 to->cpt_si_pid = from->si_pid;
1015 to->cpt_si_uid = from->si_uid;
1016 to->cpt_si_status = from->si_status;
1017 to->cpt_si_utime = from->si_utime;
1018 to->cpt_si_stime = from->si_stime;
1019 break;
1020 case SIGILL:
1021 case SIGFPE:
1022 case SIGSEGV:
1023 case SIGBUS:
1024 to->cpt_si_addr = (intptr_t) from->si_addr;
1025 break;
1026 case SIGPOLL:
1027 to->cpt_si_band = from->si_band;
1028 to->cpt_si_fd = from->si_fd;
1029 break;
1030 default:
1031 to->cpt_si_pid = from->si_pid;
1032 to->cpt_si_uid = from->si_uid;
1033 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1034 break;
1035 }
1036 }
1037}
1038
1039static void
1040siginfo_from_compat_siginfo (siginfo_t *to, compat_siginfo_t *from)
1041{
1042 memset (to, 0, sizeof (*to));
1043
1044 to->si_signo = from->si_signo;
1045 to->si_errno = from->si_errno;
1046 to->si_code = from->si_code;
1047
b53a1623 1048 if (to->si_code == SI_TIMER)
d0722149 1049 {
b53a1623
PA		 1050 to->si_timerid = from->cpt_si_timerid;
1051 to->si_overrun = from->cpt_si_overrun;
d0722149
DE		 1052 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1053 }
1054 else if (to->si_code == SI_USER)
1055 {
1056 to->si_pid = from->cpt_si_pid;
1057 to->si_uid = from->cpt_si_uid;
1058 }
b53a1623 1059 else if (to->si_code < 0)
d0722149 1060 {
b53a1623
PA		 1061 to->si_pid = from->cpt_si_pid;
1062 to->si_uid = from->cpt_si_uid;
d0722149
DE		 1063 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1064 }
1065 else
1066 {
1067 switch (to->si_signo)
1068 {
1069 case SIGCHLD:
1070 to->si_pid = from->cpt_si_pid;
1071 to->si_uid = from->cpt_si_uid;
1072 to->si_status = from->cpt_si_status;
1073 to->si_utime = from->cpt_si_utime;
1074 to->si_stime = from->cpt_si_stime;
1075 break;
1076 case SIGILL:
1077 case SIGFPE:
1078 case SIGSEGV:
1079 case SIGBUS:
1080 to->si_addr = (void *) (intptr_t) from->cpt_si_addr;
1081 break;
1082 case SIGPOLL:
1083 to->si_band = from->cpt_si_band;
1084 to->si_fd = from->cpt_si_fd;
1085 break;
1086 default:
1087 to->si_pid = from->cpt_si_pid;
1088 to->si_uid = from->cpt_si_uid;
1089 to->si_ptr = (void* ) (intptr_t) from->cpt_si_ptr;
1090 break;
1091 }
1092 }
1093}
1094
c92b5177
L		 1095static void
1096compat_x32_siginfo_from_siginfo (compat_x32_siginfo_t *to,
1097 siginfo_t *from)
1098{
1099 memset (to, 0, sizeof (*to));
1100
1101 to->si_signo = from->si_signo;
1102 to->si_errno = from->si_errno;
1103 to->si_code = from->si_code;
1104
1105 if (to->si_code == SI_TIMER)
1106 {
1107 to->cpt_si_timerid = from->si_timerid;
1108 to->cpt_si_overrun = from->si_overrun;
1109 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1110 }
1111 else if (to->si_code == SI_USER)
1112 {
1113 to->cpt_si_pid = from->si_pid;
1114 to->cpt_si_uid = from->si_uid;
1115 }
1116 else if (to->si_code < 0)
1117 {
1118 to->cpt_si_pid = from->si_pid;
1119 to->cpt_si_uid = from->si_uid;
1120 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1121 }
1122 else
1123 {
1124 switch (to->si_signo)
1125 {
1126 case SIGCHLD:
1127 to->cpt_si_pid = from->si_pid;
1128 to->cpt_si_uid = from->si_uid;
1129 to->cpt_si_status = from->si_status;
1130 to->cpt_si_utime = from->si_utime;
1131 to->cpt_si_stime = from->si_stime;
1132 break;
1133 case SIGILL:
1134 case SIGFPE:
1135 case SIGSEGV:
1136 case SIGBUS:
1137 to->cpt_si_addr = (intptr_t) from->si_addr;
1138 break;
1139 case SIGPOLL:
1140 to->cpt_si_band = from->si_band;
1141 to->cpt_si_fd = from->si_fd;
1142 break;
1143 default:
1144 to->cpt_si_pid = from->si_pid;
1145 to->cpt_si_uid = from->si_uid;
1146 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1147 break;
1148 }
1149 }
1150}
1151
1152static void
1153siginfo_from_compat_x32_siginfo (siginfo_t *to,
1154 compat_x32_siginfo_t *from)
1155{
1156 memset (to, 0, sizeof (*to));
1157
1158 to->si_signo = from->si_signo;
1159 to->si_errno = from->si_errno;
1160 to->si_code = from->si_code;
1161
1162 if (to->si_code == SI_TIMER)
1163 {
1164 to->si_timerid = from->cpt_si_timerid;
1165 to->si_overrun = from->cpt_si_overrun;
1166 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1167 }
1168 else if (to->si_code == SI_USER)
1169 {
1170 to->si_pid = from->cpt_si_pid;
1171 to->si_uid = from->cpt_si_uid;
1172 }
1173 else if (to->si_code < 0)
1174 {
1175 to->si_pid = from->cpt_si_pid;
1176 to->si_uid = from->cpt_si_uid;
1177 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1178 }
1179 else
1180 {
1181 switch (to->si_signo)
1182 {
1183 case SIGCHLD:
1184 to->si_pid = from->cpt_si_pid;
1185 to->si_uid = from->cpt_si_uid;
1186 to->si_status = from->cpt_si_status;
1187 to->si_utime = from->cpt_si_utime;
1188 to->si_stime = from->cpt_si_stime;
1189 break;
1190 case SIGILL:
1191 case SIGFPE:
1192 case SIGSEGV:
1193 case SIGBUS:
1194 to->si_addr = (void *) (intptr_t) from->cpt_si_addr;
1195 break;
1196 case SIGPOLL:
1197 to->si_band = from->cpt_si_band;
1198 to->si_fd = from->cpt_si_fd;
1199 break;
1200 default:
1201 to->si_pid = from->cpt_si_pid;
1202 to->si_uid = from->cpt_si_uid;
1203 to->si_ptr = (void* ) (intptr_t) from->cpt_si_ptr;
1204 break;
1205 }
1206 }
1207}
1208
d0722149
DE		 1209#endif /* __x86_64__ */
1210
1211/* Convert a native/host siginfo object, into/from the siginfo in the
1212 layout of the inferiors' architecture. Returns true if any
1213 conversion was done; false otherwise. If DIRECTION is 1, then copy
1214 from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to
1215 INF. */
1216
1217static int
a5362b9a 1218x86_siginfo_fixup (siginfo_t *native, void *inf, int direction)
d0722149
DE		 1219{
1220#ifdef __x86_64__
760256f9 1221 unsigned int machine;
d86d4aaf 1222 int tid = lwpid_of (current_inferior);
760256f9
PA		 1223 int is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
1224
d0722149 1225 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
3aee8918 1226 if (!is_64bit_tdesc ())
d0722149 1227 {
a5362b9a 1228 if (sizeof (siginfo_t) != sizeof (compat_siginfo_t))
9f1036c1 1229 fatal ("unexpected difference in siginfo");
d0722149
DE		 1230
1231 if (direction == 0)
1232 compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, native);
1233 else
1234 siginfo_from_compat_siginfo (native, (struct compat_siginfo *) inf);
1235
c92b5177
L		 1236 return 1;
1237 }
1238 /* No fixup for native x32 GDB. */
760256f9 1239 else if (!is_elf64 && sizeof (void *) == 8)
c92b5177
L		 1240 {
1241 if (sizeof (siginfo_t) != sizeof (compat_x32_siginfo_t))
1242 fatal ("unexpected difference in siginfo");
1243
1244 if (direction == 0)
1245 compat_x32_siginfo_from_siginfo ((struct compat_x32_siginfo *) inf,
1246 native);
1247 else
1248 siginfo_from_compat_x32_siginfo (native,
1249 (struct compat_x32_siginfo *) inf);
1250
d0722149
DE		 1251 return 1;
1252 }
1253#endif
1254
1255 return 0;
1256}
1257\f
1570b33e
L		 1258static int use_xml;
1259
3aee8918
PA		 1260/* Format of XSAVE extended state is:
1261 struct
1262 {
1263 fxsave_bytes[0..463]
1264 sw_usable_bytes[464..511]
1265 xstate_hdr_bytes[512..575]
1266 avx_bytes[576..831]
1267 future_state etc
1268 };
1269
1270 Same memory layout will be used for the coredump NT_X86_XSTATE
1271 representing the XSAVE extended state registers.
1272
1273 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
1274 extended state mask, which is the same as the extended control register
1275 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
1276 together with the mask saved in the xstate_hdr_bytes to determine what
1277 states the processor/OS supports and what state, used or initialized,
1278 the process/thread is in. */
1279#define I386_LINUX_XSAVE_XCR0_OFFSET 464
1280
1281/* Does the current host support the GETFPXREGS request? The header
1282 file may or may not define it, and even if it is defined, the
1283 kernel will return EIO if it's running on a pre-SSE processor. */
1284int have_ptrace_getfpxregs =
1285#ifdef HAVE_PTRACE_GETFPXREGS
1286 -1
1287#else
1288 0
1289#endif
1290;
1570b33e 1291
3aee8918
PA		 1292/* Does the current host support PTRACE_GETREGSET? */
1293static int have_ptrace_getregset = -1;
1294
1295/* Get Linux/x86 target description from running target. */
1296
1297static const struct target_desc *
1298x86_linux_read_description (void)
1570b33e 1299{
3aee8918
PA		 1300 unsigned int machine;
1301 int is_elf64;
a196ebeb 1302 int xcr0_features;
3aee8918
PA		 1303 int tid;
1304 static uint64_t xcr0;
3a13a53b 1305 struct regset_info *regset;
1570b33e 1306
d86d4aaf 1307 tid = lwpid_of (current_inferior);
1570b33e 1308
3aee8918 1309 is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
45ba0d02 1310
3aee8918 1311 if (sizeof (void *) == 4)
3a13a53b 1312 {
3aee8918
PA		 1313 if (is_elf64 > 0)
1314 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
1315#ifndef __x86_64__
1316 else if (machine == EM_X86_64)
1317 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
1318#endif
1319 }
3a13a53b 1320
3aee8918
PA		 1321#if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
1322 if (machine == EM_386 && have_ptrace_getfpxregs == -1)
1323 {
1324 elf_fpxregset_t fpxregs;
3a13a53b 1325
3aee8918 1326 if (ptrace (PTRACE_GETFPXREGS, tid, 0, (long) &fpxregs) < 0)
3a13a53b 1327 {
3aee8918
PA		 1328 have_ptrace_getfpxregs = 0;
1329 have_ptrace_getregset = 0;
1330 return tdesc_i386_mmx_linux;
3a13a53b 1331 }
3aee8918
PA		 1332 else
1333 have_ptrace_getfpxregs = 1;
3a13a53b 1334 }
1570b33e
L		 1335#endif
1336
1337 if (!use_xml)
1338 {
3aee8918
PA		 1339 x86_xcr0 = I386_XSTATE_SSE_MASK;
1340
1570b33e
L		 1341 /* Don't use XML. */
1342#ifdef __x86_64__
3aee8918
PA		 1343 if (machine == EM_X86_64)
1344 return tdesc_amd64_linux_no_xml;
1570b33e 1345 else
1570b33e 1346#endif
3aee8918 1347 return tdesc_i386_linux_no_xml;
1570b33e
L		 1348 }
1349
1570b33e
L		 1350 if (have_ptrace_getregset == -1)
1351 {
3aee8918 1352 uint64_t xstateregs[(I386_XSTATE_SSE_SIZE / sizeof (uint64_t))];
1570b33e 1353 struct iovec iov;
1570b33e
L		 1354
1355 iov.iov_base = xstateregs;
1356 iov.iov_len = sizeof (xstateregs);
1357
1358 /* Check if PTRACE_GETREGSET works. */
3aee8918
PA		 1359 if (ptrace (PTRACE_GETREGSET, tid,
1360 (unsigned int) NT_X86_XSTATE, (long) &iov) < 0)
1361 have_ptrace_getregset = 0;
1362 else
1570b33e 1363 {
3aee8918
PA		 1364 have_ptrace_getregset = 1;
1365
1366 /* Get XCR0 from XSAVE extended state. */
1367 xcr0 = xstateregs[(I386_LINUX_XSAVE_XCR0_OFFSET
1368 / sizeof (uint64_t))];
1369
1370 /* Use PTRACE_GETREGSET if it is available. */
1371 for (regset = x86_regsets;
1372 regset->fill_function != NULL; regset++)
1373 if (regset->get_request == PTRACE_GETREGSET)
1374 regset->size = I386_XSTATE_SIZE (xcr0);
1375 else if (regset->type != GENERAL_REGS)
1376 regset->size = 0;
1570b33e 1377 }
1570b33e
L		 1378 }
1379
3aee8918 1380 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
a196ebeb
WT		 1381 xcr0_features = (have_ptrace_getregset
1382 && (xcr0 & I386_XSTATE_ALL_MASK));
3aee8918 1383
a196ebeb 1384 if (xcr0_features)
3aee8918 1385 x86_xcr0 = xcr0;
1570b33e 1386
3aee8918
PA		 1387 if (machine == EM_X86_64)
1388 {
1570b33e 1389#ifdef __x86_64__
a196ebeb 1390 if (is_elf64)
3aee8918 1391 {
a196ebeb
WT		 1392 if (xcr0_features)
1393 {
1394 switch (xcr0 & I386_XSTATE_ALL_MASK)
1395 {
01f9f808
MS		 1396 case I386_XSTATE_AVX512_MASK:
1397 return tdesc_amd64_avx512_linux;
1398
a196ebeb
WT		 1399 case I386_XSTATE_MPX_MASK:
1400 return tdesc_amd64_mpx_linux;
1401
1402 case I386_XSTATE_AVX_MASK:
1403 return tdesc_amd64_avx_linux;
1404
1405 default:
1406 return tdesc_amd64_linux;
1407 }
1408 }
4d47af5c 1409 else
a196ebeb 1410 return tdesc_amd64_linux;
3aee8918
PA		 1411 }
1412 else
1413 {
a196ebeb
WT		 1414 if (xcr0_features)
1415 {
1416 switch (xcr0 & I386_XSTATE_ALL_MASK)
1417 {
01f9f808
MS		 1418 case I386_XSTATE_AVX512_MASK:
1419 return tdesc_x32_avx512_linux;
1420
a196ebeb
WT		 1421 case I386_XSTATE_MPX_MASK: /* No MPX on x32. */
1422 case I386_XSTATE_AVX_MASK:
1423 return tdesc_x32_avx_linux;
1424
1425 default:
1426 return tdesc_x32_linux;
1427 }
1428 }
3aee8918 1429 else
a196ebeb 1430 return tdesc_x32_linux;
1570b33e 1431 }
3aee8918 1432#endif
1570b33e 1433 }
3aee8918
PA		 1434 else
1435 {
a196ebeb
WT		 1436 if (xcr0_features)
1437 {
1438 switch (xcr0 & I386_XSTATE_ALL_MASK)
1439 {
01f9f808
MS		 1440 case (I386_XSTATE_AVX512_MASK):
1441 return tdesc_i386_avx512_linux;
1442
a196ebeb
WT		 1443 case (I386_XSTATE_MPX_MASK):
1444 return tdesc_i386_mpx_linux;
1445
1446 case (I386_XSTATE_AVX_MASK):
1447 return tdesc_i386_avx_linux;
1448
1449 default:
1450 return tdesc_i386_linux;
1451 }
1452 }
3aee8918
PA		 1453 else
1454 return tdesc_i386_linux;
1455 }
1456
1457 gdb_assert_not_reached ("failed to return tdesc");
1458}
1459
1460/* Callback for find_inferior. Stops iteration when a thread with a
1461 given PID is found. */
1462
1463static int
1464same_process_callback (struct inferior_list_entry *entry, void *data)
1465{
1466 int pid = *(int *) data;
1467
1468 return (ptid_get_pid (entry->id) == pid);
1469}
1470
1471/* Callback for for_each_inferior. Calls the arch_setup routine for
1472 each process. */
1473
1474static void
1475x86_arch_setup_process_callback (struct inferior_list_entry *entry)
1476{
1477 int pid = ptid_get_pid (entry->id);
1478
1479 /* Look up any thread of this processes. */
1480 current_inferior
1481 = (struct thread_info *) find_inferior (&all_threads,
1482 same_process_callback, &pid);
1483
1484 the_low_target.arch_setup ();
1485}
1486
1487/* Update all the target description of all processes; a new GDB
1488 connected, and it may or not support xml target descriptions. */
1489
1490static void
1491x86_linux_update_xmltarget (void)
1492{
1493 struct thread_info *save_inferior = current_inferior;
1494
1495 /* Before changing the register cache's internal layout, flush the
1496 contents of the current valid caches back to the threads, and
1497 release the current regcache objects. */
1498 regcache_release ();
1499
1500 for_each_inferior (&all_processes, x86_arch_setup_process_callback);
1501
1502 current_inferior = save_inferior;
1570b33e
L		 1503}
1504
1505/* Process qSupported query, "xmlRegisters=". Update the buffer size for
1506 PTRACE_GETREGSET. */
1507
1508static void
1509x86_linux_process_qsupported (const char *query)
1510{
1511 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
1512 with "i386" in qSupported query, it supports x86 XML target
1513 descriptions. */
1514 use_xml = 0;
1515 if (query != NULL && strncmp (query, "xmlRegisters=", 13) == 0)
1516 {
1517 char *copy = xstrdup (query + 13);
1518 char *p;
1519
1520 for (p = strtok (copy, ","); p != NULL; p = strtok (NULL, ","))
1521 {
1522 if (strcmp (p, "i386") == 0)
1523 {
1524 use_xml = 1;
1525 break;
1526 }
1527 }
1528
1529 free (copy);
1530 }
1531
1532 x86_linux_update_xmltarget ();
1533}
1534
3aee8918 1535/* Common for x86/x86-64. */
d0722149 1536
3aee8918
PA		 1537static struct regsets_info x86_regsets_info =
1538 {
1539 x86_regsets, /* regsets */
1540 0, /* num_regsets */
1541 NULL, /* disabled_regsets */
1542 };
214d508e
L		 1543
1544#ifdef __x86_64__
3aee8918
PA		 1545static struct regs_info amd64_linux_regs_info =
1546 {
1547 NULL, /* regset_bitmap */
1548 NULL, /* usrregs_info */
1549 &x86_regsets_info
1550 };
d0722149 1551#endif
3aee8918
PA		 1552static struct usrregs_info i386_linux_usrregs_info =
1553 {
1554 I386_NUM_REGS,
1555 i386_regmap,
1556 };
d0722149 1557
3aee8918
PA		 1558static struct regs_info i386_linux_regs_info =
1559 {
1560 NULL, /* regset_bitmap */
1561 &i386_linux_usrregs_info,
1562 &x86_regsets_info
1563 };
d0722149 1564
3aee8918
PA		 1565const struct regs_info *
1566x86_linux_regs_info (void)
1567{
1568#ifdef __x86_64__
1569 if (is_64bit_tdesc ())
1570 return &amd64_linux_regs_info;
1571 else
1572#endif
1573 return &i386_linux_regs_info;
1574}
d0722149 1575
3aee8918
PA		 1576/* Initialize the target description for the architecture of the
1577 inferior. */
1570b33e 1578
3aee8918
PA		 1579static void
1580x86_arch_setup (void)
1581{
1582 current_process ()->tdesc = x86_linux_read_description ();
d0722149
DE		 1583}
1584
219f2f23
PA		 1585static int
1586x86_supports_tracepoints (void)
1587{
1588 return 1;
1589}
1590
fa593d66
PA		 1591static void
1592append_insns (CORE_ADDR *to, size_t len, const unsigned char *buf)
1593{
1594 write_inferior_memory (*to, buf, len);
1595 *to += len;
1596}
1597
1598static int
1599push_opcode (unsigned char *buf, char *op)
1600{
1601 unsigned char *buf_org = buf;
1602
1603 while (1)
1604 {
1605 char *endptr;
1606 unsigned long ul = strtoul (op, &endptr, 16);
1607
1608 if (endptr == op)
1609 break;
1610
1611 *buf++ = ul;
1612 op = endptr;
1613 }
1614
1615 return buf - buf_org;
1616}
1617
1618#ifdef __x86_64__
1619
1620/* Build a jump pad that saves registers and calls a collection
1621 function. Writes a jump instruction to the jump pad to
1622 JJUMPAD_INSN. The caller is responsible to write it in at the
1623 tracepoint address. */
1624
1625static int
1626amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1627 CORE_ADDR collector,
1628 CORE_ADDR lockaddr,
1629 ULONGEST orig_size,
1630 CORE_ADDR *jump_entry,
405f8e94
SS		 1631 CORE_ADDR *trampoline,
1632 ULONGEST *trampoline_size,
fa593d66
PA		 1633 unsigned char *jjump_pad_insn,
1634 ULONGEST *jjump_pad_insn_size,
1635 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1636 CORE_ADDR *adjusted_insn_addr_end,
1637 char *err)
fa593d66
PA		 1638{
1639 unsigned char buf[40];
1640 int i, offset;
f4647387
YQ		 1641 int64_t loffset;
1642
fa593d66
PA		 1643 CORE_ADDR buildaddr = *jump_entry;
1644
1645 /* Build the jump pad. */
1646
1647 /* First, do tracepoint data collection. Save registers. */
1648 i = 0;
1649 /* Need to ensure stack pointer saved first. */
1650 buf[i++] = 0x54; /* push %rsp */
1651 buf[i++] = 0x55; /* push %rbp */
1652 buf[i++] = 0x57; /* push %rdi */
1653 buf[i++] = 0x56; /* push %rsi */
1654 buf[i++] = 0x52; /* push %rdx */
1655 buf[i++] = 0x51; /* push %rcx */
1656 buf[i++] = 0x53; /* push %rbx */
1657 buf[i++] = 0x50; /* push %rax */
1658 buf[i++] = 0x41; buf[i++] = 0x57; /* push %r15 */
1659 buf[i++] = 0x41; buf[i++] = 0x56; /* push %r14 */
1660 buf[i++] = 0x41; buf[i++] = 0x55; /* push %r13 */
1661 buf[i++] = 0x41; buf[i++] = 0x54; /* push %r12 */
1662 buf[i++] = 0x41; buf[i++] = 0x53; /* push %r11 */
1663 buf[i++] = 0x41; buf[i++] = 0x52; /* push %r10 */
1664 buf[i++] = 0x41; buf[i++] = 0x51; /* push %r9 */
1665 buf[i++] = 0x41; buf[i++] = 0x50; /* push %r8 */
1666 buf[i++] = 0x9c; /* pushfq */
1667 buf[i++] = 0x48; /* movl <addr>,%rdi */
1668 buf[i++] = 0xbf;
1669 *((unsigned long *)(buf + i)) = (unsigned long) tpaddr;
1670 i += sizeof (unsigned long);
1671 buf[i++] = 0x57; /* push %rdi */
1672 append_insns (&buildaddr, i, buf);
1673
1674 /* Stack space for the collecting_t object. */
1675 i = 0;
1676 i += push_opcode (&buf[i], "48 83 ec 18"); /* sub $0x18,%rsp */
1677 i += push_opcode (&buf[i], "48 b8"); /* mov <tpoint>,%rax */
1678 memcpy (buf + i, &tpoint, 8);
1679 i += 8;
1680 i += push_opcode (&buf[i], "48 89 04 24"); /* mov %rax,(%rsp) */
1681 i += push_opcode (&buf[i],
1682 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1683 i += push_opcode (&buf[i], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1684 append_insns (&buildaddr, i, buf);
1685
1686 /* spin-lock. */
1687 i = 0;
1688 i += push_opcode (&buf[i], "48 be"); /* movl <lockaddr>,%rsi */
1689 memcpy (&buf[i], (void *) &lockaddr, 8);
1690 i += 8;
1691 i += push_opcode (&buf[i], "48 89 e1"); /* mov %rsp,%rcx */
1692 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1693 i += push_opcode (&buf[i], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1694 i += push_opcode (&buf[i], "48 85 c0"); /* test %rax,%rax */
1695 i += push_opcode (&buf[i], "75 f4"); /* jne <again> */
1696 append_insns (&buildaddr, i, buf);
1697
1698 /* Set up the gdb_collect call. */
1699 /* At this point, (stack pointer + 0x18) is the base of our saved
1700 register block. */
1701
1702 i = 0;
1703 i += push_opcode (&buf[i], "48 89 e6"); /* mov %rsp,%rsi */
1704 i += push_opcode (&buf[i], "48 83 c6 18"); /* add $0x18,%rsi */
1705
1706 /* tpoint address may be 64-bit wide. */
1707 i += push_opcode (&buf[i], "48 bf"); /* movl <addr>,%rdi */
1708 memcpy (buf + i, &tpoint, 8);
1709 i += 8;
1710 append_insns (&buildaddr, i, buf);
1711
1712 /* The collector function being in the shared library, may be
1713 >31-bits away off the jump pad. */
1714 i = 0;
1715 i += push_opcode (&buf[i], "48 b8"); /* mov $collector,%rax */
1716 memcpy (buf + i, &collector, 8);
1717 i += 8;
1718 i += push_opcode (&buf[i], "ff d0"); /* callq *%rax */
1719 append_insns (&buildaddr, i, buf);
1720
1721 /* Clear the spin-lock. */
1722 i = 0;
1723 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1724 i += push_opcode (&buf[i], "48 a3"); /* mov %rax, lockaddr */
1725 memcpy (buf + i, &lockaddr, 8);
1726 i += 8;
1727 append_insns (&buildaddr, i, buf);
1728
1729 /* Remove stack that had been used for the collect_t object. */
1730 i = 0;
1731 i += push_opcode (&buf[i], "48 83 c4 18"); /* add $0x18,%rsp */
1732 append_insns (&buildaddr, i, buf);
1733
1734 /* Restore register state. */
1735 i = 0;
1736 buf[i++] = 0x48; /* add $0x8,%rsp */
1737 buf[i++] = 0x83;
1738 buf[i++] = 0xc4;
1739 buf[i++] = 0x08;
1740 buf[i++] = 0x9d; /* popfq */
1741 buf[i++] = 0x41; buf[i++] = 0x58; /* pop %r8 */
1742 buf[i++] = 0x41; buf[i++] = 0x59; /* pop %r9 */
1743 buf[i++] = 0x41; buf[i++] = 0x5a; /* pop %r10 */
1744 buf[i++] = 0x41; buf[i++] = 0x5b; /* pop %r11 */
1745 buf[i++] = 0x41; buf[i++] = 0x5c; /* pop %r12 */
1746 buf[i++] = 0x41; buf[i++] = 0x5d; /* pop %r13 */
1747 buf[i++] = 0x41; buf[i++] = 0x5e; /* pop %r14 */
1748 buf[i++] = 0x41; buf[i++] = 0x5f; /* pop %r15 */
1749 buf[i++] = 0x58; /* pop %rax */
1750 buf[i++] = 0x5b; /* pop %rbx */
1751 buf[i++] = 0x59; /* pop %rcx */
1752 buf[i++] = 0x5a; /* pop %rdx */
1753 buf[i++] = 0x5e; /* pop %rsi */
1754 buf[i++] = 0x5f; /* pop %rdi */
1755 buf[i++] = 0x5d; /* pop %rbp */
1756 buf[i++] = 0x5c; /* pop %rsp */
1757 append_insns (&buildaddr, i, buf);
1758
1759 /* Now, adjust the original instruction to execute in the jump
1760 pad. */
1761 *adjusted_insn_addr = buildaddr;
1762 relocate_instruction (&buildaddr, tpaddr);
1763 *adjusted_insn_addr_end = buildaddr;
1764
1765 /* Finally, write a jump back to the program. */
f4647387
YQ		 1766
1767 loffset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn));
1768 if (loffset > INT_MAX || loffset < INT_MIN)
1769 {
1770 sprintf (err,
1771 "E.Jump back from jump pad too far from tracepoint "
1772 "(offset 0x%" PRIx64 " > int32).", loffset);
1773 return 1;
1774 }
1775
1776 offset = (int) loffset;
fa593d66
PA		 1777 memcpy (buf, jump_insn, sizeof (jump_insn));
1778 memcpy (buf + 1, &offset, 4);
1779 append_insns (&buildaddr, sizeof (jump_insn), buf);
1780
1781 /* The jump pad is now built. Wire in a jump to our jump pad. This
1782 is always done last (by our caller actually), so that we can
1783 install fast tracepoints with threads running. This relies on
1784 the agent's atomic write support. */
f4647387
YQ		 1785 loffset = *jump_entry - (tpaddr + sizeof (jump_insn));
1786 if (loffset > INT_MAX || loffset < INT_MIN)
1787 {
1788 sprintf (err,
1789 "E.Jump pad too far from tracepoint "
1790 "(offset 0x%" PRIx64 " > int32).", loffset);
1791 return 1;
1792 }
1793
1794 offset = (int) loffset;
1795
fa593d66
PA		 1796 memcpy (buf, jump_insn, sizeof (jump_insn));
1797 memcpy (buf + 1, &offset, 4);
1798 memcpy (jjump_pad_insn, buf, sizeof (jump_insn));
1799 *jjump_pad_insn_size = sizeof (jump_insn);
1800
1801 /* Return the end address of our pad. */
1802 *jump_entry = buildaddr;
1803
1804 return 0;
1805}
1806
1807#endif /* __x86_64__ */
1808
1809/* Build a jump pad that saves registers and calls a collection
1810 function. Writes a jump instruction to the jump pad to
1811 JJUMPAD_INSN. The caller is responsible to write it in at the
1812 tracepoint address. */
1813
1814static int
1815i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1816 CORE_ADDR collector,
1817 CORE_ADDR lockaddr,
1818 ULONGEST orig_size,
1819 CORE_ADDR *jump_entry,
405f8e94
SS		 1820 CORE_ADDR *trampoline,
1821 ULONGEST *trampoline_size,
fa593d66
PA		 1822 unsigned char *jjump_pad_insn,
1823 ULONGEST *jjump_pad_insn_size,
1824 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1825 CORE_ADDR *adjusted_insn_addr_end,
1826 char *err)
fa593d66
PA		 1827{
1828 unsigned char buf[0x100];
1829 int i, offset;
1830 CORE_ADDR buildaddr = *jump_entry;
1831
1832 /* Build the jump pad. */
1833
1834 /* First, do tracepoint data collection. Save registers. */
1835 i = 0;
1836 buf[i++] = 0x60; /* pushad */
1837 buf[i++] = 0x68; /* push tpaddr aka $pc */
1838 *((int *)(buf + i)) = (int) tpaddr;
1839 i += 4;
1840 buf[i++] = 0x9c; /* pushf */
1841 buf[i++] = 0x1e; /* push %ds */
1842 buf[i++] = 0x06; /* push %es */
1843 buf[i++] = 0x0f; /* push %fs */
1844 buf[i++] = 0xa0;
1845 buf[i++] = 0x0f; /* push %gs */
1846 buf[i++] = 0xa8;
1847 buf[i++] = 0x16; /* push %ss */
1848 buf[i++] = 0x0e; /* push %cs */
1849 append_insns (&buildaddr, i, buf);
1850
1851 /* Stack space for the collecting_t object. */
1852 i = 0;
1853 i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */
1854
1855 /* Build the object. */
1856 i += push_opcode (&buf[i], "b8"); /* mov <tpoint>,%eax */
1857 memcpy (buf + i, &tpoint, 4);
1858 i += 4;
1859 i += push_opcode (&buf[i], "89 04 24"); /* mov %eax,(%esp) */
1860
1861 i += push_opcode (&buf[i], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1862 i += push_opcode (&buf[i], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1863 append_insns (&buildaddr, i, buf);
1864
1865 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1866 If we cared for it, this could be using xchg alternatively. */
1867
1868 i = 0;
1869 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1870 i += push_opcode (&buf[i], "f0 0f b1 25"); /* lock cmpxchg
1871 %esp,<lockaddr> */
1872 memcpy (&buf[i], (void *) &lockaddr, 4);
1873 i += 4;
1874 i += push_opcode (&buf[i], "85 c0"); /* test %eax,%eax */
1875 i += push_opcode (&buf[i], "75 f2"); /* jne <again> */
1876 append_insns (&buildaddr, i, buf);
1877
1878
1879 /* Set up arguments to the gdb_collect call. */
1880 i = 0;
1881 i += push_opcode (&buf[i], "89 e0"); /* mov %esp,%eax */
1882 i += push_opcode (&buf[i], "83 c0 08"); /* add $0x08,%eax */
1883 i += push_opcode (&buf[i], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1884 append_insns (&buildaddr, i, buf);
1885
1886 i = 0;
1887 i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */
1888 append_insns (&buildaddr, i, buf);
1889
1890 i = 0;
1891 i += push_opcode (&buf[i], "c7 04 24"); /* movl <addr>,(%esp) */
1892 memcpy (&buf[i], (void *) &tpoint, 4);
1893 i += 4;
1894 append_insns (&buildaddr, i, buf);
1895
1896 buf[0] = 0xe8; /* call <reladdr> */
1897 offset = collector - (buildaddr + sizeof (jump_insn));
1898 memcpy (buf + 1, &offset, 4);
1899 append_insns (&buildaddr, 5, buf);
1900 /* Clean up after the call. */
1901 buf[0] = 0x83; /* add $0x8,%esp */
1902 buf[1] = 0xc4;
1903 buf[2] = 0x08;
1904 append_insns (&buildaddr, 3, buf);
1905
1906
1907 /* Clear the spin-lock. This would need the LOCK prefix on older
1908 broken archs. */
1909 i = 0;
1910 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1911 i += push_opcode (&buf[i], "a3"); /* mov %eax, lockaddr */
1912 memcpy (buf + i, &lockaddr, 4);
1913 i += 4;
1914 append_insns (&buildaddr, i, buf);
1915
1916
1917 /* Remove stack that had been used for the collect_t object. */
1918 i = 0;
1919 i += push_opcode (&buf[i], "83 c4 08"); /* add $0x08,%esp */
1920 append_insns (&buildaddr, i, buf);
1921
1922 i = 0;
1923 buf[i++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1924 buf[i++] = 0xc4;
1925 buf[i++] = 0x04;
1926 buf[i++] = 0x17; /* pop %ss */
1927 buf[i++] = 0x0f; /* pop %gs */
1928 buf[i++] = 0xa9;
1929 buf[i++] = 0x0f; /* pop %fs */
1930 buf[i++] = 0xa1;
1931 buf[i++] = 0x07; /* pop %es */
405f8e94 1932 buf[i++] = 0x1f; /* pop %ds */
fa593d66
PA		 1933 buf[i++] = 0x9d; /* popf */
1934 buf[i++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1935 buf[i++] = 0xc4;
1936 buf[i++] = 0x04;
1937 buf[i++] = 0x61; /* popad */
1938 append_insns (&buildaddr, i, buf);
1939
1940 /* Now, adjust the original instruction to execute in the jump
1941 pad. */
1942 *adjusted_insn_addr = buildaddr;
1943 relocate_instruction (&buildaddr, tpaddr);
1944 *adjusted_insn_addr_end = buildaddr;
1945
1946 /* Write the jump back to the program. */
1947 offset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn));
1948 memcpy (buf, jump_insn, sizeof (jump_insn));
1949 memcpy (buf + 1, &offset, 4);
1950 append_insns (&buildaddr, sizeof (jump_insn), buf);
1951
1952 /* The jump pad is now built. Wire in a jump to our jump pad. This
1953 is always done last (by our caller actually), so that we can
1954 install fast tracepoints with threads running. This relies on
1955 the agent's atomic write support. */
405f8e94
SS		 1956 if (orig_size == 4)
1957 {
1958 /* Create a trampoline. */
1959 *trampoline_size = sizeof (jump_insn);
1960 if (!claim_trampoline_space (*trampoline_size, trampoline))
1961 {
1962 /* No trampoline space available. */
1963 strcpy (err,
1964 "E.Cannot allocate trampoline space needed for fast "
1965 "tracepoints on 4-byte instructions.");
1966 return 1;
1967 }
1968
1969 offset = *jump_entry - (*trampoline + sizeof (jump_insn));
1970 memcpy (buf, jump_insn, sizeof (jump_insn));
1971 memcpy (buf + 1, &offset, 4);
1972 write_inferior_memory (*trampoline, buf, sizeof (jump_insn));
1973
1974 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1975 offset = (*trampoline - (tpaddr + sizeof (small_jump_insn))) & 0xffff;
1976 memcpy (buf, small_jump_insn, sizeof (small_jump_insn));
1977 memcpy (buf + 2, &offset, 2);
1978 memcpy (jjump_pad_insn, buf, sizeof (small_jump_insn));
1979 *jjump_pad_insn_size = sizeof (small_jump_insn);
1980 }
1981 else
1982 {
1983 /* Else use a 32-bit relative jump instruction. */
1984 offset = *jump_entry - (tpaddr + sizeof (jump_insn));
1985 memcpy (buf, jump_insn, sizeof (jump_insn));
1986 memcpy (buf + 1, &offset, 4);
1987 memcpy (jjump_pad_insn, buf, sizeof (jump_insn));
1988 *jjump_pad_insn_size = sizeof (jump_insn);
1989 }
fa593d66
PA		 1990
1991 /* Return the end address of our pad. */
1992 *jump_entry = buildaddr;
1993
1994 return 0;
1995}
1996
1997static int
1998x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1999 CORE_ADDR collector,
2000 CORE_ADDR lockaddr,
2001 ULONGEST orig_size,
2002 CORE_ADDR *jump_entry,
405f8e94
SS		 2003 CORE_ADDR *trampoline,
2004 ULONGEST *trampoline_size,
fa593d66
PA		 2005 unsigned char *jjump_pad_insn,
2006 ULONGEST *jjump_pad_insn_size,
2007 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 2008 CORE_ADDR *adjusted_insn_addr_end,
2009 char *err)
fa593d66
PA		 2010{
2011#ifdef __x86_64__
3aee8918 2012 if (is_64bit_tdesc ())
fa593d66
PA		 2013 return amd64_install_fast_tracepoint_jump_pad (tpoint, tpaddr,
2014 collector, lockaddr,
2015 orig_size, jump_entry,
405f8e94 2016 trampoline, trampoline_size,
fa593d66
PA		 2017 jjump_pad_insn,
2018 jjump_pad_insn_size,
2019 adjusted_insn_addr,
405f8e94
SS		 2020 adjusted_insn_addr_end,
2021 err);
fa593d66
PA		 2022#endif
2023
2024 return i386_install_fast_tracepoint_jump_pad (tpoint, tpaddr,
2025 collector, lockaddr,
2026 orig_size, jump_entry,
405f8e94 2027 trampoline, trampoline_size,
fa593d66
PA		 2028 jjump_pad_insn,
2029 jjump_pad_insn_size,
2030 adjusted_insn_addr,
405f8e94
SS		 2031 adjusted_insn_addr_end,
2032 err);
2033}
2034
2035/* Return the minimum instruction length for fast tracepoints on x86/x86-64
2036 architectures. */
2037
2038static int
2039x86_get_min_fast_tracepoint_insn_len (void)
2040{
2041 static int warned_about_fast_tracepoints = 0;
2042
2043#ifdef __x86_64__
2044 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
2045 used for fast tracepoints. */
3aee8918 2046 if (is_64bit_tdesc ())
405f8e94
SS		 2047 return 5;
2048#endif
2049
58b4daa5 2050 if (agent_loaded_p ())
405f8e94
SS		 2051 {
2052 char errbuf[IPA_BUFSIZ];
2053
2054 errbuf[0] = '\0';
2055
2056 /* On x86, if trampolines are available, then 4-byte jump instructions
2057 with a 2-byte offset may be used, otherwise 5-byte jump instructions
2058 with a 4-byte offset are used instead. */
2059 if (have_fast_tracepoint_trampoline_buffer (errbuf))
2060 return 4;
2061 else
2062 {
2063 /* GDB has no channel to explain to user why a shorter fast
2064 tracepoint is not possible, but at least make GDBserver
2065 mention that something has gone awry. */
2066 if (!warned_about_fast_tracepoints)
2067 {
2068 warning ("4-byte fast tracepoints not available; %s\n", errbuf);
2069 warned_about_fast_tracepoints = 1;
2070 }
2071 return 5;
2072 }
2073 }
2074 else
2075 {
2076 /* Indicate that the minimum length is currently unknown since the IPA
2077 has not loaded yet. */
2078 return 0;
2079 }
fa593d66
PA		 2080}
2081
6a271cae
PA		 2082static void
2083add_insns (unsigned char *start, int len)
2084{
2085 CORE_ADDR buildaddr = current_insn_ptr;
2086
2087 if (debug_threads)
87ce2a04
DE		 2088 debug_printf ("Adding %d bytes of insn at %s\n",
2089 len, paddress (buildaddr));
6a271cae
PA		 2090
2091 append_insns (&buildaddr, len, start);
2092 current_insn_ptr = buildaddr;
2093}
2094
6a271cae
PA		 2095/* Our general strategy for emitting code is to avoid specifying raw
2096 bytes whenever possible, and instead copy a block of inline asm
2097 that is embedded in the function. This is a little messy, because
2098 we need to keep the compiler from discarding what looks like dead
2099 code, plus suppress various warnings. */
2100
9e4344e5
PA		 2101#define EMIT_ASM(NAME, INSNS) \
2102 do \
2103 { \
2104 extern unsigned char start_ ## NAME, end_ ## NAME; \
2105 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
493e2a69 2106 __asm__ ("jmp end_" #NAME "\n" \
9e4344e5
PA		 2107 "\t" "start_" #NAME ":" \
2108 "\t" INSNS "\n" \
2109 "\t" "end_" #NAME ":"); \
2110 } while (0)
6a271cae
PA		 2111
2112#ifdef __x86_64__
2113
2114#define EMIT_ASM32(NAME,INSNS) \
9e4344e5
PA		 2115 do \
2116 { \
2117 extern unsigned char start_ ## NAME, end_ ## NAME; \
2118 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
2119 __asm__ (".code32\n" \
2120 "\t" "jmp end_" #NAME "\n" \
2121 "\t" "start_" #NAME ":\n" \
2122 "\t" INSNS "\n" \
2123 "\t" "end_" #NAME ":\n" \
2124 ".code64\n"); \
2125 } while (0)
6a271cae
PA		 2126
2127#else
2128
2129#define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
2130
2131#endif
2132
2133#ifdef __x86_64__
2134
2135static void
2136amd64_emit_prologue (void)
2137{
2138 EMIT_ASM (amd64_prologue,
2139 "pushq %rbp\n\t"
2140 "movq %rsp,%rbp\n\t"
2141 "sub $0x20,%rsp\n\t"
2142 "movq %rdi,-8(%rbp)\n\t"
2143 "movq %rsi,-16(%rbp)");
2144}
2145
2146
2147static void
2148amd64_emit_epilogue (void)
2149{
2150 EMIT_ASM (amd64_epilogue,
2151 "movq -16(%rbp),%rdi\n\t"
2152 "movq %rax,(%rdi)\n\t"
2153 "xor %rax,%rax\n\t"
2154 "leave\n\t"
2155 "ret");
2156}
2157
2158static void
2159amd64_emit_add (void)
2160{
2161 EMIT_ASM (amd64_add,
2162 "add (%rsp),%rax\n\t"
2163 "lea 0x8(%rsp),%rsp");
2164}
2165
2166static void
2167amd64_emit_sub (void)
2168{
2169 EMIT_ASM (amd64_sub,
2170 "sub %rax,(%rsp)\n\t"
2171 "pop %rax");
2172}
2173
2174static void
2175amd64_emit_mul (void)
2176{
2177 emit_error = 1;
2178}
2179
2180static void
2181amd64_emit_lsh (void)
2182{
2183 emit_error = 1;
2184}
2185
2186static void
2187amd64_emit_rsh_signed (void)
2188{
2189 emit_error = 1;
2190}
2191
2192static void
2193amd64_emit_rsh_unsigned (void)
2194{
2195 emit_error = 1;
2196}
2197
2198static void
2199amd64_emit_ext (int arg)
2200{
2201 switch (arg)
2202 {
2203 case 8:
2204 EMIT_ASM (amd64_ext_8,
2205 "cbtw\n\t"
2206 "cwtl\n\t"
2207 "cltq");
2208 break;
2209 case 16:
2210 EMIT_ASM (amd64_ext_16,
2211 "cwtl\n\t"
2212 "cltq");
2213 break;
2214 case 32:
2215 EMIT_ASM (amd64_ext_32,
2216 "cltq");
2217 break;
2218 default:
2219 emit_error = 1;
2220 }
2221}
2222
2223static void
2224amd64_emit_log_not (void)
2225{
2226 EMIT_ASM (amd64_log_not,
2227 "test %rax,%rax\n\t"
2228 "sete %cl\n\t"
2229 "movzbq %cl,%rax");
2230}
2231
2232static void
2233amd64_emit_bit_and (void)
2234{
2235 EMIT_ASM (amd64_and,
2236 "and (%rsp),%rax\n\t"
2237 "lea 0x8(%rsp),%rsp");
2238}
2239
2240static void
2241amd64_emit_bit_or (void)
2242{
2243 EMIT_ASM (amd64_or,
2244 "or (%rsp),%rax\n\t"
2245 "lea 0x8(%rsp),%rsp");
2246}
2247
2248static void
2249amd64_emit_bit_xor (void)
2250{
2251 EMIT_ASM (amd64_xor,
2252 "xor (%rsp),%rax\n\t"
2253 "lea 0x8(%rsp),%rsp");
2254}
2255
2256static void
2257amd64_emit_bit_not (void)
2258{
2259 EMIT_ASM (amd64_bit_not,
2260 "xorq $0xffffffffffffffff,%rax");
2261}
2262
2263static void
2264amd64_emit_equal (void)
2265{
2266 EMIT_ASM (amd64_equal,
2267 "cmp %rax,(%rsp)\n\t"
2268 "je .Lamd64_equal_true\n\t"
2269 "xor %rax,%rax\n\t"
2270 "jmp .Lamd64_equal_end\n\t"
2271 ".Lamd64_equal_true:\n\t"
2272 "mov $0x1,%rax\n\t"
2273 ".Lamd64_equal_end:\n\t"
2274 "lea 0x8(%rsp),%rsp");
2275}
2276
2277static void
2278amd64_emit_less_signed (void)
2279{
2280 EMIT_ASM (amd64_less_signed,
2281 "cmp %rax,(%rsp)\n\t"
2282 "jl .Lamd64_less_signed_true\n\t"
2283 "xor %rax,%rax\n\t"
2284 "jmp .Lamd64_less_signed_end\n\t"
2285 ".Lamd64_less_signed_true:\n\t"
2286 "mov $1,%rax\n\t"
2287 ".Lamd64_less_signed_end:\n\t"
2288 "lea 0x8(%rsp),%rsp");
2289}
2290
2291static void
2292amd64_emit_less_unsigned (void)
2293{
2294 EMIT_ASM (amd64_less_unsigned,
2295 "cmp %rax,(%rsp)\n\t"
2296 "jb .Lamd64_less_unsigned_true\n\t"
2297 "xor %rax,%rax\n\t"
2298 "jmp .Lamd64_less_unsigned_end\n\t"
2299 ".Lamd64_less_unsigned_true:\n\t"
2300 "mov $1,%rax\n\t"
2301 ".Lamd64_less_unsigned_end:\n\t"
2302 "lea 0x8(%rsp),%rsp");
2303}
2304
2305static void
2306amd64_emit_ref (int size)
2307{
2308 switch (size)
2309 {
2310 case 1:
2311 EMIT_ASM (amd64_ref1,
2312 "movb (%rax),%al");
2313 break;
2314 case 2:
2315 EMIT_ASM (amd64_ref2,
2316 "movw (%rax),%ax");
2317 break;
2318 case 4:
2319 EMIT_ASM (amd64_ref4,
2320 "movl (%rax),%eax");
2321 break;
2322 case 8:
2323 EMIT_ASM (amd64_ref8,
2324 "movq (%rax),%rax");
2325 break;
2326 }
2327}
2328
2329static void
2330amd64_emit_if_goto (int *offset_p, int *size_p)
2331{
2332 EMIT_ASM (amd64_if_goto,
2333 "mov %rax,%rcx\n\t"
2334 "pop %rax\n\t"
2335 "cmp $0,%rcx\n\t"
2336 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2337 if (offset_p)
2338 *offset_p = 10;
2339 if (size_p)
2340 *size_p = 4;
2341}
2342
2343static void
2344amd64_emit_goto (int *offset_p, int *size_p)
2345{
2346 EMIT_ASM (amd64_goto,
2347 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2348 if (offset_p)
2349 *offset_p = 1;
2350 if (size_p)
2351 *size_p = 4;
2352}
2353
2354static void
2355amd64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2356{
2357 int diff = (to - (from + size));
2358 unsigned char buf[sizeof (int)];
2359
2360 if (size != 4)
2361 {
2362 emit_error = 1;
2363 return;
2364 }
2365
2366 memcpy (buf, &diff, sizeof (int));
2367 write_inferior_memory (from, buf, sizeof (int));
2368}
2369
2370static void
4e29fb54 2371amd64_emit_const (LONGEST num)
6a271cae
PA		 2372{
2373 unsigned char buf[16];
2374 int i;
2375 CORE_ADDR buildaddr = current_insn_ptr;
2376
2377 i = 0;
2378 buf[i++] = 0x48; buf[i++] = 0xb8; /* mov $<n>,%rax */
b00ad6ff 2379 memcpy (&buf[i], &num, sizeof (num));
6a271cae
PA		 2380 i += 8;
2381 append_insns (&buildaddr, i, buf);
2382 current_insn_ptr = buildaddr;
2383}
2384
2385static void
2386amd64_emit_call (CORE_ADDR fn)
2387{
2388 unsigned char buf[16];
2389 int i;
2390 CORE_ADDR buildaddr;
4e29fb54 2391 LONGEST offset64;
6a271cae
PA		 2392
2393 /* The destination function being in the shared library, may be
2394 >31-bits away off the compiled code pad. */
2395
2396 buildaddr = current_insn_ptr;
2397
2398 offset64 = fn - (buildaddr + 1 /* call op */ + 4 /* 32-bit offset */);
2399
2400 i = 0;
2401
2402 if (offset64 > INT_MAX || offset64 < INT_MIN)
2403 {
2404 /* Offset is too large for a call. Use callq, but that requires
2405 a register, so avoid it if possible. Use r10, since it is
2406 call-clobbered, we don't have to push/pop it. */
2407 buf[i++] = 0x48; /* mov $fn,%r10 */
2408 buf[i++] = 0xba;
2409 memcpy (buf + i, &fn, 8);
2410 i += 8;
2411 buf[i++] = 0xff; /* callq *%r10 */
2412 buf[i++] = 0xd2;
2413 }
2414 else
2415 {
2416 int offset32 = offset64; /* we know we can't overflow here. */
2417 memcpy (buf + i, &offset32, 4);
2418 i += 4;
2419 }
2420
2421 append_insns (&buildaddr, i, buf);
2422 current_insn_ptr = buildaddr;
2423}
2424
2425static void
2426amd64_emit_reg (int reg)
2427{
2428 unsigned char buf[16];
2429 int i;
2430 CORE_ADDR buildaddr;
2431
2432 /* Assume raw_regs is still in %rdi. */
2433 buildaddr = current_insn_ptr;
2434 i = 0;
2435 buf[i++] = 0xbe; /* mov $<n>,%esi */
b00ad6ff 2436 memcpy (&buf[i], &reg, sizeof (reg));
6a271cae
PA		 2437 i += 4;
2438 append_insns (&buildaddr, i, buf);
2439 current_insn_ptr = buildaddr;
2440 amd64_emit_call (get_raw_reg_func_addr ());
2441}
2442
2443static void
2444amd64_emit_pop (void)
2445{
2446 EMIT_ASM (amd64_pop,
2447 "pop %rax");
2448}
2449
2450static void
2451amd64_emit_stack_flush (void)
2452{
2453 EMIT_ASM (amd64_stack_flush,
2454 "push %rax");
2455}
2456
2457static void
2458amd64_emit_zero_ext (int arg)
2459{
2460 switch (arg)
2461 {
2462 case 8:
2463 EMIT_ASM (amd64_zero_ext_8,
2464 "and $0xff,%rax");
2465 break;
2466 case 16:
2467 EMIT_ASM (amd64_zero_ext_16,
2468 "and $0xffff,%rax");
2469 break;
2470 case 32:
2471 EMIT_ASM (amd64_zero_ext_32,
2472 "mov $0xffffffff,%rcx\n\t"
2473 "and %rcx,%rax");
2474 break;
2475 default:
2476 emit_error = 1;
2477 }
2478}
2479
2480static void
2481amd64_emit_swap (void)
2482{
2483 EMIT_ASM (amd64_swap,
2484 "mov %rax,%rcx\n\t"
2485 "pop %rax\n\t"
2486 "push %rcx");
2487}
2488
2489static void
2490amd64_emit_stack_adjust (int n)
2491{
2492 unsigned char buf[16];
2493 int i;
2494 CORE_ADDR buildaddr = current_insn_ptr;
2495
2496 i = 0;
2497 buf[i++] = 0x48; /* lea $<n>(%rsp),%rsp */
2498 buf[i++] = 0x8d;
2499 buf[i++] = 0x64;
2500 buf[i++] = 0x24;
2501 /* This only handles adjustments up to 16, but we don't expect any more. */
2502 buf[i++] = n * 8;
2503 append_insns (&buildaddr, i, buf);
2504 current_insn_ptr = buildaddr;
2505}
2506
2507/* FN's prototype is `LONGEST(*fn)(int)'. */
2508
2509static void
2510amd64_emit_int_call_1 (CORE_ADDR fn, int arg1)
2511{
2512 unsigned char buf[16];
2513 int i;
2514 CORE_ADDR buildaddr;
2515
2516 buildaddr = current_insn_ptr;
2517 i = 0;
2518 buf[i++] = 0xbf; /* movl $<n>,%edi */
b00ad6ff 2519 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 2520 i += 4;
2521 append_insns (&buildaddr, i, buf);
2522 current_insn_ptr = buildaddr;
2523 amd64_emit_call (fn);
2524}
2525
4e29fb54 2526/* FN's prototype is `void(*fn)(int,LONGEST)'. */
6a271cae
PA		 2527
2528static void
2529amd64_emit_void_call_2 (CORE_ADDR fn, int arg1)
2530{
2531 unsigned char buf[16];
2532 int i;
2533 CORE_ADDR buildaddr;
2534
2535 buildaddr = current_insn_ptr;
2536 i = 0;
2537 buf[i++] = 0xbf; /* movl $<n>,%edi */
b00ad6ff 2538 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 2539 i += 4;
2540 append_insns (&buildaddr, i, buf);
2541 current_insn_ptr = buildaddr;
2542 EMIT_ASM (amd64_void_call_2_a,
2543 /* Save away a copy of the stack top. */
2544 "push %rax\n\t"
2545 /* Also pass top as the second argument. */
2546 "mov %rax,%rsi");
2547 amd64_emit_call (fn);
2548 EMIT_ASM (amd64_void_call_2_b,
2549 /* Restore the stack top, %rax may have been trashed. */
2550 "pop %rax");
2551}
2552
6b9801d4
SS		 2553void
2554amd64_emit_eq_goto (int *offset_p, int *size_p)
2555{
2556 EMIT_ASM (amd64_eq,
2557 "cmp %rax,(%rsp)\n\t"
2558 "jne .Lamd64_eq_fallthru\n\t"
2559 "lea 0x8(%rsp),%rsp\n\t"
2560 "pop %rax\n\t"
2561 /* jmp, but don't trust the assembler to choose the right jump */
2562 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2563 ".Lamd64_eq_fallthru:\n\t"
2564 "lea 0x8(%rsp),%rsp\n\t"
2565 "pop %rax");
2566
2567 if (offset_p)
2568 *offset_p = 13;
2569 if (size_p)
2570 *size_p = 4;
2571}
2572
2573void
2574amd64_emit_ne_goto (int *offset_p, int *size_p)
2575{
2576 EMIT_ASM (amd64_ne,
2577 "cmp %rax,(%rsp)\n\t"
2578 "je .Lamd64_ne_fallthru\n\t"
2579 "lea 0x8(%rsp),%rsp\n\t"
2580 "pop %rax\n\t"
2581 /* jmp, but don't trust the assembler to choose the right jump */
2582 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2583 ".Lamd64_ne_fallthru:\n\t"
2584 "lea 0x8(%rsp),%rsp\n\t"
2585 "pop %rax");
2586
2587 if (offset_p)
2588 *offset_p = 13;
2589 if (size_p)
2590 *size_p = 4;
2591}
2592
2593void
2594amd64_emit_lt_goto (int *offset_p, int *size_p)
2595{
2596 EMIT_ASM (amd64_lt,
2597 "cmp %rax,(%rsp)\n\t"
2598 "jnl .Lamd64_lt_fallthru\n\t"
2599 "lea 0x8(%rsp),%rsp\n\t"
2600 "pop %rax\n\t"
2601 /* jmp, but don't trust the assembler to choose the right jump */
2602 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2603 ".Lamd64_lt_fallthru:\n\t"
2604 "lea 0x8(%rsp),%rsp\n\t"
2605 "pop %rax");
2606
2607 if (offset_p)
2608 *offset_p = 13;
2609 if (size_p)
2610 *size_p = 4;
2611}
2612
2613void
2614amd64_emit_le_goto (int *offset_p, int *size_p)
2615{
2616 EMIT_ASM (amd64_le,
2617 "cmp %rax,(%rsp)\n\t"
2618 "jnle .Lamd64_le_fallthru\n\t"
2619 "lea 0x8(%rsp),%rsp\n\t"
2620 "pop %rax\n\t"
2621 /* jmp, but don't trust the assembler to choose the right jump */
2622 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2623 ".Lamd64_le_fallthru:\n\t"
2624 "lea 0x8(%rsp),%rsp\n\t"
2625 "pop %rax");
2626
2627 if (offset_p)
2628 *offset_p = 13;
2629 if (size_p)
2630 *size_p = 4;
2631}
2632
2633void
2634amd64_emit_gt_goto (int *offset_p, int *size_p)
2635{
2636 EMIT_ASM (amd64_gt,
2637 "cmp %rax,(%rsp)\n\t"
2638 "jng .Lamd64_gt_fallthru\n\t"
2639 "lea 0x8(%rsp),%rsp\n\t"
2640 "pop %rax\n\t"
2641 /* jmp, but don't trust the assembler to choose the right jump */
2642 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2643 ".Lamd64_gt_fallthru:\n\t"
2644 "lea 0x8(%rsp),%rsp\n\t"
2645 "pop %rax");
2646
2647 if (offset_p)
2648 *offset_p = 13;
2649 if (size_p)
2650 *size_p = 4;
2651}
2652
2653void
2654amd64_emit_ge_goto (int *offset_p, int *size_p)
2655{
2656 EMIT_ASM (amd64_ge,
2657 "cmp %rax,(%rsp)\n\t"
2658 "jnge .Lamd64_ge_fallthru\n\t"
2659 ".Lamd64_ge_jump:\n\t"
2660 "lea 0x8(%rsp),%rsp\n\t"
2661 "pop %rax\n\t"
2662 /* jmp, but don't trust the assembler to choose the right jump */
2663 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2664 ".Lamd64_ge_fallthru:\n\t"
2665 "lea 0x8(%rsp),%rsp\n\t"
2666 "pop %rax");
2667
2668 if (offset_p)
2669 *offset_p = 13;
2670 if (size_p)
2671 *size_p = 4;
2672}
2673
6a271cae
PA		 2674struct emit_ops amd64_emit_ops =
2675 {
2676 amd64_emit_prologue,
2677 amd64_emit_epilogue,
2678 amd64_emit_add,
2679 amd64_emit_sub,
2680 amd64_emit_mul,
2681 amd64_emit_lsh,
2682 amd64_emit_rsh_signed,
2683 amd64_emit_rsh_unsigned,
2684 amd64_emit_ext,
2685 amd64_emit_log_not,
2686 amd64_emit_bit_and,
2687 amd64_emit_bit_or,
2688 amd64_emit_bit_xor,
2689 amd64_emit_bit_not,
2690 amd64_emit_equal,
2691 amd64_emit_less_signed,
2692 amd64_emit_less_unsigned,
2693 amd64_emit_ref,
2694 amd64_emit_if_goto,
2695 amd64_emit_goto,
2696 amd64_write_goto_address,
2697 amd64_emit_const,
2698 amd64_emit_call,
2699 amd64_emit_reg,
2700 amd64_emit_pop,
2701 amd64_emit_stack_flush,
2702 amd64_emit_zero_ext,
2703 amd64_emit_swap,
2704 amd64_emit_stack_adjust,
2705 amd64_emit_int_call_1,
6b9801d4
SS		 2706 amd64_emit_void_call_2,
2707 amd64_emit_eq_goto,
2708 amd64_emit_ne_goto,
2709 amd64_emit_lt_goto,
2710 amd64_emit_le_goto,
2711 amd64_emit_gt_goto,
2712 amd64_emit_ge_goto
6a271cae
PA		 2713 };
2714
2715#endif /* __x86_64__ */
2716
2717static void
2718i386_emit_prologue (void)
2719{
2720 EMIT_ASM32 (i386_prologue,
2721 "push %ebp\n\t"
bf15cbda
SS		 2722 "mov %esp,%ebp\n\t"
2723 "push %ebx");
6a271cae
PA		 2724 /* At this point, the raw regs base address is at 8(%ebp), and the
2725 value pointer is at 12(%ebp). */
2726}
2727
2728static void
2729i386_emit_epilogue (void)
2730{
2731 EMIT_ASM32 (i386_epilogue,
2732 "mov 12(%ebp),%ecx\n\t"
2733 "mov %eax,(%ecx)\n\t"
2734 "mov %ebx,0x4(%ecx)\n\t"
2735 "xor %eax,%eax\n\t"
bf15cbda 2736 "pop %ebx\n\t"
6a271cae
PA		 2737 "pop %ebp\n\t"
2738 "ret");
2739}
2740
2741static void
2742i386_emit_add (void)
2743{
2744 EMIT_ASM32 (i386_add,
2745 "add (%esp),%eax\n\t"
2746 "adc 0x4(%esp),%ebx\n\t"
2747 "lea 0x8(%esp),%esp");
2748}
2749
2750static void
2751i386_emit_sub (void)
2752{
2753 EMIT_ASM32 (i386_sub,
2754 "subl %eax,(%esp)\n\t"
2755 "sbbl %ebx,4(%esp)\n\t"
2756 "pop %eax\n\t"
2757 "pop %ebx\n\t");
2758}
2759
2760static void
2761i386_emit_mul (void)
2762{
2763 emit_error = 1;
2764}
2765
2766static void
2767i386_emit_lsh (void)
2768{
2769 emit_error = 1;
2770}
2771
2772static void
2773i386_emit_rsh_signed (void)
2774{
2775 emit_error = 1;
2776}
2777
2778static void
2779i386_emit_rsh_unsigned (void)
2780{
2781 emit_error = 1;
2782}
2783
2784static void
2785i386_emit_ext (int arg)
2786{
2787 switch (arg)
2788 {
2789 case 8:
2790 EMIT_ASM32 (i386_ext_8,
2791 "cbtw\n\t"
2792 "cwtl\n\t"
2793 "movl %eax,%ebx\n\t"
2794 "sarl $31,%ebx");
2795 break;
2796 case 16:
2797 EMIT_ASM32 (i386_ext_16,
2798 "cwtl\n\t"
2799 "movl %eax,%ebx\n\t"
2800 "sarl $31,%ebx");
2801 break;
2802 case 32:
2803 EMIT_ASM32 (i386_ext_32,
2804 "movl %eax,%ebx\n\t"
2805 "sarl $31,%ebx");
2806 break;
2807 default:
2808 emit_error = 1;
2809 }
2810}
2811
2812static void
2813i386_emit_log_not (void)
2814{
2815 EMIT_ASM32 (i386_log_not,
2816 "or %ebx,%eax\n\t"
2817 "test %eax,%eax\n\t"
2818 "sete %cl\n\t"
2819 "xor %ebx,%ebx\n\t"
2820 "movzbl %cl,%eax");
2821}
2822
2823static void
2824i386_emit_bit_and (void)
2825{
2826 EMIT_ASM32 (i386_and,
2827 "and (%esp),%eax\n\t"
2828 "and 0x4(%esp),%ebx\n\t"
2829 "lea 0x8(%esp),%esp");
2830}
2831
2832static void
2833i386_emit_bit_or (void)
2834{
2835 EMIT_ASM32 (i386_or,
2836 "or (%esp),%eax\n\t"
2837 "or 0x4(%esp),%ebx\n\t"
2838 "lea 0x8(%esp),%esp");
2839}
2840
2841static void
2842i386_emit_bit_xor (void)
2843{
2844 EMIT_ASM32 (i386_xor,
2845 "xor (%esp),%eax\n\t"
2846 "xor 0x4(%esp),%ebx\n\t"
2847 "lea 0x8(%esp),%esp");
2848}
2849
2850static void
2851i386_emit_bit_not (void)
2852{
2853 EMIT_ASM32 (i386_bit_not,
2854 "xor $0xffffffff,%eax\n\t"
2855 "xor $0xffffffff,%ebx\n\t");
2856}
2857
2858static void
2859i386_emit_equal (void)
2860{
2861 EMIT_ASM32 (i386_equal,
2862 "cmpl %ebx,4(%esp)\n\t"
2863 "jne .Li386_equal_false\n\t"
2864 "cmpl %eax,(%esp)\n\t"
2865 "je .Li386_equal_true\n\t"
2866 ".Li386_equal_false:\n\t"
2867 "xor %eax,%eax\n\t"
2868 "jmp .Li386_equal_end\n\t"
2869 ".Li386_equal_true:\n\t"
2870 "mov $1,%eax\n\t"
2871 ".Li386_equal_end:\n\t"
2872 "xor %ebx,%ebx\n\t"
2873 "lea 0x8(%esp),%esp");
2874}
2875
2876static void
2877i386_emit_less_signed (void)
2878{
2879 EMIT_ASM32 (i386_less_signed,
2880 "cmpl %ebx,4(%esp)\n\t"
2881 "jl .Li386_less_signed_true\n\t"
2882 "jne .Li386_less_signed_false\n\t"
2883 "cmpl %eax,(%esp)\n\t"
2884 "jl .Li386_less_signed_true\n\t"
2885 ".Li386_less_signed_false:\n\t"
2886 "xor %eax,%eax\n\t"
2887 "jmp .Li386_less_signed_end\n\t"
2888 ".Li386_less_signed_true:\n\t"
2889 "mov $1,%eax\n\t"
2890 ".Li386_less_signed_end:\n\t"
2891 "xor %ebx,%ebx\n\t"
2892 "lea 0x8(%esp),%esp");
2893}
2894
2895static void
2896i386_emit_less_unsigned (void)
2897{
2898 EMIT_ASM32 (i386_less_unsigned,
2899 "cmpl %ebx,4(%esp)\n\t"
2900 "jb .Li386_less_unsigned_true\n\t"
2901 "jne .Li386_less_unsigned_false\n\t"
2902 "cmpl %eax,(%esp)\n\t"
2903 "jb .Li386_less_unsigned_true\n\t"
2904 ".Li386_less_unsigned_false:\n\t"
2905 "xor %eax,%eax\n\t"
2906 "jmp .Li386_less_unsigned_end\n\t"
2907 ".Li386_less_unsigned_true:\n\t"
2908 "mov $1,%eax\n\t"
2909 ".Li386_less_unsigned_end:\n\t"
2910 "xor %ebx,%ebx\n\t"
2911 "lea 0x8(%esp),%esp");
2912}
2913
2914static void
2915i386_emit_ref (int size)
2916{
2917 switch (size)
2918 {
2919 case 1:
2920 EMIT_ASM32 (i386_ref1,
2921 "movb (%eax),%al");
2922 break;
2923 case 2:
2924 EMIT_ASM32 (i386_ref2,
2925 "movw (%eax),%ax");
2926 break;
2927 case 4:
2928 EMIT_ASM32 (i386_ref4,
2929 "movl (%eax),%eax");
2930 break;
2931 case 8:
2932 EMIT_ASM32 (i386_ref8,
2933 "movl 4(%eax),%ebx\n\t"
2934 "movl (%eax),%eax");
2935 break;
2936 }
2937}
2938
2939static void
2940i386_emit_if_goto (int *offset_p, int *size_p)
2941{
2942 EMIT_ASM32 (i386_if_goto,
2943 "mov %eax,%ecx\n\t"
2944 "or %ebx,%ecx\n\t"
2945 "pop %eax\n\t"
2946 "pop %ebx\n\t"
2947 "cmpl $0,%ecx\n\t"
2948 /* Don't trust the assembler to choose the right jump */
2949 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2950
2951 if (offset_p)
2952 *offset_p = 11; /* be sure that this matches the sequence above */
2953 if (size_p)
2954 *size_p = 4;
2955}
2956
2957static void
2958i386_emit_goto (int *offset_p, int *size_p)
2959{
2960 EMIT_ASM32 (i386_goto,
2961 /* Don't trust the assembler to choose the right jump */
2962 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2963 if (offset_p)
2964 *offset_p = 1;
2965 if (size_p)
2966 *size_p = 4;
2967}
2968
2969static void
2970i386_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2971{
2972 int diff = (to - (from + size));
2973 unsigned char buf[sizeof (int)];
2974
2975 /* We're only doing 4-byte sizes at the moment. */
2976 if (size != 4)
2977 {
2978 emit_error = 1;
2979 return;
2980 }
2981
2982 memcpy (buf, &diff, sizeof (int));
2983 write_inferior_memory (from, buf, sizeof (int));
2984}
2985
2986static void
4e29fb54 2987i386_emit_const (LONGEST num)
6a271cae
PA		 2988{
2989 unsigned char buf[16];
b00ad6ff 2990 int i, hi, lo;
6a271cae
PA		 2991 CORE_ADDR buildaddr = current_insn_ptr;
2992
2993 i = 0;
2994 buf[i++] = 0xb8; /* mov $<n>,%eax */
b00ad6ff
NF		 2995 lo = num & 0xffffffff;
2996 memcpy (&buf[i], &lo, sizeof (lo));
6a271cae
PA		 2997 i += 4;
2998 hi = ((num >> 32) & 0xffffffff);
2999 if (hi)
3000 {
3001 buf[i++] = 0xbb; /* mov $<n>,%ebx */
b00ad6ff 3002 memcpy (&buf[i], &hi, sizeof (hi));
6a271cae
PA		 3003 i += 4;
3004 }
3005 else
3006 {
3007 buf[i++] = 0x31; buf[i++] = 0xdb; /* xor %ebx,%ebx */
3008 }
3009 append_insns (&buildaddr, i, buf);
3010 current_insn_ptr = buildaddr;
3011}
3012
3013static void
3014i386_emit_call (CORE_ADDR fn)
3015{
3016 unsigned char buf[16];
3017 int i, offset;
3018 CORE_ADDR buildaddr;
3019
3020 buildaddr = current_insn_ptr;
3021 i = 0;
3022 buf[i++] = 0xe8; /* call <reladdr> */
3023 offset = ((int) fn) - (buildaddr + 5);
3024 memcpy (buf + 1, &offset, 4);
3025 append_insns (&buildaddr, 5, buf);
3026 current_insn_ptr = buildaddr;
3027}
3028
3029static void
3030i386_emit_reg (int reg)
3031{
3032 unsigned char buf[16];
3033 int i;
3034 CORE_ADDR buildaddr;
3035
3036 EMIT_ASM32 (i386_reg_a,
3037 "sub $0x8,%esp");
3038 buildaddr = current_insn_ptr;
3039 i = 0;
3040 buf[i++] = 0xb8; /* mov $<n>,%eax */
b00ad6ff 3041 memcpy (&buf[i], &reg, sizeof (reg));
6a271cae
PA		 3042 i += 4;
3043 append_insns (&buildaddr, i, buf);
3044 current_insn_ptr = buildaddr;
3045 EMIT_ASM32 (i386_reg_b,
3046 "mov %eax,4(%esp)\n\t"
3047 "mov 8(%ebp),%eax\n\t"
3048 "mov %eax,(%esp)");
3049 i386_emit_call (get_raw_reg_func_addr ());
3050 EMIT_ASM32 (i386_reg_c,
3051 "xor %ebx,%ebx\n\t"
3052 "lea 0x8(%esp),%esp");
3053}
3054
3055static void
3056i386_emit_pop (void)
3057{
3058 EMIT_ASM32 (i386_pop,
3059 "pop %eax\n\t"
3060 "pop %ebx");
3061}
3062
3063static void
3064i386_emit_stack_flush (void)
3065{
3066 EMIT_ASM32 (i386_stack_flush,
3067 "push %ebx\n\t"
3068 "push %eax");
3069}
3070
3071static void
3072i386_emit_zero_ext (int arg)
3073{
3074 switch (arg)
3075 {
3076 case 8:
3077 EMIT_ASM32 (i386_zero_ext_8,
3078 "and $0xff,%eax\n\t"
3079 "xor %ebx,%ebx");
3080 break;
3081 case 16:
3082 EMIT_ASM32 (i386_zero_ext_16,
3083 "and $0xffff,%eax\n\t"
3084 "xor %ebx,%ebx");
3085 break;
3086 case 32:
3087 EMIT_ASM32 (i386_zero_ext_32,
3088 "xor %ebx,%ebx");
3089 break;
3090 default:
3091 emit_error = 1;
3092 }
3093}
3094
3095static void
3096i386_emit_swap (void)
3097{
3098 EMIT_ASM32 (i386_swap,
3099 "mov %eax,%ecx\n\t"
3100 "mov %ebx,%edx\n\t"
3101 "pop %eax\n\t"
3102 "pop %ebx\n\t"
3103 "push %edx\n\t"
3104 "push %ecx");
3105}
3106
3107static void
3108i386_emit_stack_adjust (int n)
3109{
3110 unsigned char buf[16];
3111 int i;
3112 CORE_ADDR buildaddr = current_insn_ptr;
3113
3114 i = 0;
3115 buf[i++] = 0x8d; /* lea $<n>(%esp),%esp */
3116 buf[i++] = 0x64;
3117 buf[i++] = 0x24;
3118 buf[i++] = n * 8;
3119 append_insns (&buildaddr, i, buf);
3120 current_insn_ptr = buildaddr;
3121}
3122
3123/* FN's prototype is `LONGEST(*fn)(int)'. */
3124
3125static void
3126i386_emit_int_call_1 (CORE_ADDR fn, int arg1)
3127{
3128 unsigned char buf[16];
3129 int i;
3130 CORE_ADDR buildaddr;
3131
3132 EMIT_ASM32 (i386_int_call_1_a,
3133 /* Reserve a bit of stack space. */
3134 "sub $0x8,%esp");
3135 /* Put the one argument on the stack. */
3136 buildaddr = current_insn_ptr;
3137 i = 0;
3138 buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */
3139 buf[i++] = 0x04;
3140 buf[i++] = 0x24;
b00ad6ff 3141 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 3142 i += 4;
3143 append_insns (&buildaddr, i, buf);
3144 current_insn_ptr = buildaddr;
3145 i386_emit_call (fn);
3146 EMIT_ASM32 (i386_int_call_1_c,
3147 "mov %edx,%ebx\n\t"
3148 "lea 0x8(%esp),%esp");
3149}
3150
4e29fb54 3151/* FN's prototype is `void(*fn)(int,LONGEST)'. */
6a271cae
PA		 3152
3153static void
3154i386_emit_void_call_2 (CORE_ADDR fn, int arg1)
3155{
3156 unsigned char buf[16];
3157 int i;
3158 CORE_ADDR buildaddr;
3159
3160 EMIT_ASM32 (i386_void_call_2_a,
3161 /* Preserve %eax only; we don't have to worry about %ebx. */
3162 "push %eax\n\t"
3163 /* Reserve a bit of stack space for arguments. */
3164 "sub $0x10,%esp\n\t"
3165 /* Copy "top" to the second argument position. (Note that
3166 we can't assume function won't scribble on its
3167 arguments, so don't try to restore from this.) */
3168 "mov %eax,4(%esp)\n\t"
3169 "mov %ebx,8(%esp)");
3170 /* Put the first argument on the stack. */
3171 buildaddr = current_insn_ptr;
3172 i = 0;
3173 buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */
3174 buf[i++] = 0x04;
3175 buf[i++] = 0x24;
b00ad6ff 3176 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 3177 i += 4;
3178 append_insns (&buildaddr, i, buf);
3179 current_insn_ptr = buildaddr;
3180 i386_emit_call (fn);
3181 EMIT_ASM32 (i386_void_call_2_b,
3182 "lea 0x10(%esp),%esp\n\t"
3183 /* Restore original stack top. */
3184 "pop %eax");
3185}
3186
6b9801d4
SS		 3187
3188void
3189i386_emit_eq_goto (int *offset_p, int *size_p)
3190{
3191 EMIT_ASM32 (eq,
3192 /* Check low half first, more likely to be decider */
3193 "cmpl %eax,(%esp)\n\t"
3194 "jne .Leq_fallthru\n\t"
3195 "cmpl %ebx,4(%esp)\n\t"
3196 "jne .Leq_fallthru\n\t"
3197 "lea 0x8(%esp),%esp\n\t"
3198 "pop %eax\n\t"
3199 "pop %ebx\n\t"
3200 /* jmp, but don't trust the assembler to choose the right jump */
3201 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3202 ".Leq_fallthru:\n\t"
3203 "lea 0x8(%esp),%esp\n\t"
3204 "pop %eax\n\t"
3205 "pop %ebx");
3206
3207 if (offset_p)
3208 *offset_p = 18;
3209 if (size_p)
3210 *size_p = 4;
3211}
3212
3213void
3214i386_emit_ne_goto (int *offset_p, int *size_p)
3215{
3216 EMIT_ASM32 (ne,
3217 /* Check low half first, more likely to be decider */
3218 "cmpl %eax,(%esp)\n\t"
3219 "jne .Lne_jump\n\t"
3220 "cmpl %ebx,4(%esp)\n\t"
3221 "je .Lne_fallthru\n\t"
3222 ".Lne_jump:\n\t"
3223 "lea 0x8(%esp),%esp\n\t"
3224 "pop %eax\n\t"
3225 "pop %ebx\n\t"
3226 /* jmp, but don't trust the assembler to choose the right jump */
3227 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3228 ".Lne_fallthru:\n\t"
3229 "lea 0x8(%esp),%esp\n\t"
3230 "pop %eax\n\t"
3231 "pop %ebx");
3232
3233 if (offset_p)
3234 *offset_p = 18;
3235 if (size_p)
3236 *size_p = 4;
3237}
3238
3239void
3240i386_emit_lt_goto (int *offset_p, int *size_p)
3241{
3242 EMIT_ASM32 (lt,
3243 "cmpl %ebx,4(%esp)\n\t"
3244 "jl .Llt_jump\n\t"
3245 "jne .Llt_fallthru\n\t"
3246 "cmpl %eax,(%esp)\n\t"
3247 "jnl .Llt_fallthru\n\t"
3248 ".Llt_jump:\n\t"
3249 "lea 0x8(%esp),%esp\n\t"
3250 "pop %eax\n\t"
3251 "pop %ebx\n\t"
3252 /* jmp, but don't trust the assembler to choose the right jump */
3253 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3254 ".Llt_fallthru:\n\t"
3255 "lea 0x8(%esp),%esp\n\t"
3256 "pop %eax\n\t"
3257 "pop %ebx");
3258
3259 if (offset_p)
3260 *offset_p = 20;
3261 if (size_p)
3262 *size_p = 4;
3263}
3264
3265void
3266i386_emit_le_goto (int *offset_p, int *size_p)
3267{
3268 EMIT_ASM32 (le,
3269 "cmpl %ebx,4(%esp)\n\t"
3270 "jle .Lle_jump\n\t"
3271 "jne .Lle_fallthru\n\t"
3272 "cmpl %eax,(%esp)\n\t"
3273 "jnle .Lle_fallthru\n\t"
3274 ".Lle_jump:\n\t"
3275 "lea 0x8(%esp),%esp\n\t"
3276 "pop %eax\n\t"
3277 "pop %ebx\n\t"
3278 /* jmp, but don't trust the assembler to choose the right jump */
3279 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3280 ".Lle_fallthru:\n\t"
3281 "lea 0x8(%esp),%esp\n\t"
3282 "pop %eax\n\t"
3283 "pop %ebx");
3284
3285 if (offset_p)
3286 *offset_p = 20;
3287 if (size_p)
3288 *size_p = 4;
3289}
3290
3291void
3292i386_emit_gt_goto (int *offset_p, int *size_p)
3293{
3294 EMIT_ASM32 (gt,
3295 "cmpl %ebx,4(%esp)\n\t"
3296 "jg .Lgt_jump\n\t"
3297 "jne .Lgt_fallthru\n\t"
3298 "cmpl %eax,(%esp)\n\t"
3299 "jng .Lgt_fallthru\n\t"
3300 ".Lgt_jump:\n\t"
3301 "lea 0x8(%esp),%esp\n\t"
3302 "pop %eax\n\t"
3303 "pop %ebx\n\t"
3304 /* jmp, but don't trust the assembler to choose the right jump */
3305 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3306 ".Lgt_fallthru:\n\t"
3307 "lea 0x8(%esp),%esp\n\t"
3308 "pop %eax\n\t"
3309 "pop %ebx");
3310
3311 if (offset_p)
3312 *offset_p = 20;
3313 if (size_p)
3314 *size_p = 4;
3315}
3316
3317void
3318i386_emit_ge_goto (int *offset_p, int *size_p)
3319{
3320 EMIT_ASM32 (ge,
3321 "cmpl %ebx,4(%esp)\n\t"
3322 "jge .Lge_jump\n\t"
3323 "jne .Lge_fallthru\n\t"
3324 "cmpl %eax,(%esp)\n\t"
3325 "jnge .Lge_fallthru\n\t"
3326 ".Lge_jump:\n\t"
3327 "lea 0x8(%esp),%esp\n\t"
3328 "pop %eax\n\t"
3329 "pop %ebx\n\t"
3330 /* jmp, but don't trust the assembler to choose the right jump */
3331 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3332 ".Lge_fallthru:\n\t"
3333 "lea 0x8(%esp),%esp\n\t"
3334 "pop %eax\n\t"
3335 "pop %ebx");
3336
3337 if (offset_p)
3338 *offset_p = 20;
3339 if (size_p)
3340 *size_p = 4;
3341}
3342
6a271cae
PA		 3343struct emit_ops i386_emit_ops =
3344 {
3345 i386_emit_prologue,
3346 i386_emit_epilogue,
3347 i386_emit_add,
3348 i386_emit_sub,
3349 i386_emit_mul,
3350 i386_emit_lsh,
3351 i386_emit_rsh_signed,
3352 i386_emit_rsh_unsigned,
3353 i386_emit_ext,
3354 i386_emit_log_not,
3355 i386_emit_bit_and,
3356 i386_emit_bit_or,
3357 i386_emit_bit_xor,
3358 i386_emit_bit_not,
3359 i386_emit_equal,
3360 i386_emit_less_signed,
3361 i386_emit_less_unsigned,
3362 i386_emit_ref,
3363 i386_emit_if_goto,
3364 i386_emit_goto,
3365 i386_write_goto_address,
3366 i386_emit_const,
3367 i386_emit_call,
3368 i386_emit_reg,
3369 i386_emit_pop,
3370 i386_emit_stack_flush,
3371 i386_emit_zero_ext,
3372 i386_emit_swap,
3373 i386_emit_stack_adjust,
3374 i386_emit_int_call_1,
6b9801d4
SS		 3375 i386_emit_void_call_2,
3376 i386_emit_eq_goto,
3377 i386_emit_ne_goto,
3378 i386_emit_lt_goto,
3379 i386_emit_le_goto,
3380 i386_emit_gt_goto,
3381 i386_emit_ge_goto
6a271cae
PA		 3382 };
3383
3384
3385static struct emit_ops *
3386x86_emit_ops (void)
3387{
3388#ifdef __x86_64__
3aee8918 3389 if (is_64bit_tdesc ())
6a271cae
PA		 3390 return &amd64_emit_ops;
3391 else
3392#endif
3393 return &i386_emit_ops;
3394}
3395
c2d6af84
PA		 3396static int
3397x86_supports_range_stepping (void)
3398{
3399 return 1;
3400}
3401
d0722149
DE		 3402/* This is initialized assuming an amd64 target.
3403 x86_arch_setup will correct it for i386 or amd64 targets. */
3404
3405struct linux_target_ops the_low_target =
3406{
3407 x86_arch_setup,
3aee8918
PA		 3408 x86_linux_regs_info,
3409 x86_cannot_fetch_register,
3410 x86_cannot_store_register,
c14dfd32 3411 NULL, /* fetch_register */
d0722149
DE		 3412 x86_get_pc,
3413 x86_set_pc,
3414 x86_breakpoint,
3415 x86_breakpoint_len,
3416 NULL,
3417 1,
3418 x86_breakpoint_at,
802e8e6d 3419 x86_supports_z_point_type,
aa5ca48f
DE		 3420 x86_insert_point,
3421 x86_remove_point,
3422 x86_stopped_by_watchpoint,
3423 x86_stopped_data_address,
d0722149
DE		 3424 /* collect_ptrace_register/supply_ptrace_register are not needed in the
3425 native i386 case (no registers smaller than an xfer unit), and are not
3426 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
3427 NULL,
3428 NULL,
3429 /* need to fix up i386 siginfo if host is amd64 */
3430 x86_siginfo_fixup,
aa5ca48f
DE		 3431 x86_linux_new_process,
3432 x86_linux_new_thread,
1570b33e 3433 x86_linux_prepare_to_resume,
219f2f23 3434 x86_linux_process_qsupported,
fa593d66
PA		 3435 x86_supports_tracepoints,
3436 x86_get_thread_area,
6a271cae 3437 x86_install_fast_tracepoint_jump_pad,
405f8e94
SS		 3438 x86_emit_ops,
3439 x86_get_min_fast_tracepoint_insn_len,
c2d6af84 3440 x86_supports_range_stepping,
d0722149 3441};
3aee8918
PA		 3442
3443void
3444initialize_low_arch (void)
3445{
3446 /* Initialize the Linux target descriptions. */
3447#ifdef __x86_64__
3448 init_registers_amd64_linux ();
3449 init_registers_amd64_avx_linux ();
01f9f808 3450 init_registers_amd64_avx512_linux ();
a196ebeb
WT		 3451 init_registers_amd64_mpx_linux ();
3452
3aee8918 3453 init_registers_x32_linux ();
7e5aaa09 3454 init_registers_x32_avx_linux ();
01f9f808 3455 init_registers_x32_avx512_linux ();
3aee8918
PA		 3456
3457 tdesc_amd64_linux_no_xml = xmalloc (sizeof (struct target_desc));
3458 copy_target_description (tdesc_amd64_linux_no_xml, tdesc_amd64_linux);
3459 tdesc_amd64_linux_no_xml->xmltarget = xmltarget_amd64_linux_no_xml;
3460#endif
3461 init_registers_i386_linux ();
3462 init_registers_i386_mmx_linux ();
3463 init_registers_i386_avx_linux ();
01f9f808 3464 init_registers_i386_avx512_linux ();
a196ebeb 3465 init_registers_i386_mpx_linux ();
3aee8918
PA		 3466
3467 tdesc_i386_linux_no_xml = xmalloc (sizeof (struct target_desc));
3468 copy_target_description (tdesc_i386_linux_no_xml, tdesc_i386_linux);
3469 tdesc_i386_linux_no_xml->xmltarget = xmltarget_i386_linux_no_xml;
3470
3471 initialize_regsets_info (&x86_regsets_info);
3472}
GDB Binutils - Deliverables
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