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Fix gdbserver qGetTLSAddr for x86_64 -m32
[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-x86-low.c
CommitLineData
d0722149
DE		 1/* GNU/Linux/x86-64 specific low level interface, for the remote server
2 for GDB.
ecd75fc8 3 Copyright (C) 2002-2014 Free Software Foundation, Inc.
d0722149
DE		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
aa5ca48f 20#include <stddef.h>
d0722149 21#include <signal.h>
6a271cae 22#include <limits.h>
f4647387 23#include <inttypes.h>
d0722149
DE		 24#include "server.h"
25#include "linux-low.h"
26#include "i387-fp.h"
aa5ca48f 27#include "i386-low.h"
1570b33e 28#include "i386-xstate.h"
d0722149
DE		 29
30#include "gdb_proc_service.h"
b5737fa9
PA		 31/* Don't include elf/common.h if linux/elf.h got included by
32 gdb_proc_service.h. */
33#ifndef ELFMAG0
34#include "elf/common.h"
35#endif
36
58b4daa5 37#include "agent.h"
3aee8918 38#include "tdesc.h"
c144c7a0 39#include "tracepoint.h"
f699aaba 40#include "ax.h"
d0722149 41
3aee8918 42#ifdef __x86_64__
90884b2b
L		 43/* Defined in auto-generated file amd64-linux.c. */
44void init_registers_amd64_linux (void);
3aee8918
PA		 45extern const struct target_desc *tdesc_amd64_linux;
46
1570b33e
L		 47/* Defined in auto-generated file amd64-avx-linux.c. */
48void init_registers_amd64_avx_linux (void);
3aee8918
PA		 49extern const struct target_desc *tdesc_amd64_avx_linux;
50
01f9f808
MS		 51/* Defined in auto-generated file amd64-avx512-linux.c. */
52void init_registers_amd64_avx512_linux (void);
53extern const struct target_desc *tdesc_amd64_avx512_linux;
54
a196ebeb
WT		 55/* Defined in auto-generated file amd64-mpx-linux.c. */
56void init_registers_amd64_mpx_linux (void);
57extern const struct target_desc *tdesc_amd64_mpx_linux;
58
4d47af5c
L		 59/* Defined in auto-generated file x32-linux.c. */
60void init_registers_x32_linux (void);
3aee8918
PA		 61extern const struct target_desc *tdesc_x32_linux;
62
4d47af5c
L		 63/* Defined in auto-generated file x32-avx-linux.c. */
64void init_registers_x32_avx_linux (void);
3aee8918 65extern const struct target_desc *tdesc_x32_avx_linux;
a196ebeb 66
01f9f808
MS		 67/* Defined in auto-generated file x32-avx512-linux.c. */
68void init_registers_x32_avx512_linux (void);
69extern const struct target_desc *tdesc_x32_avx512_linux;
70
3aee8918
PA		 71#endif
72
73/* Defined in auto-generated file i386-linux.c. */
74void init_registers_i386_linux (void);
75extern const struct target_desc *tdesc_i386_linux;
76
77/* Defined in auto-generated file i386-mmx-linux.c. */
78void init_registers_i386_mmx_linux (void);
79extern const struct target_desc *tdesc_i386_mmx_linux;
80
81/* Defined in auto-generated file i386-avx-linux.c. */
82void init_registers_i386_avx_linux (void);
83extern const struct target_desc *tdesc_i386_avx_linux;
84
01f9f808
MS		 85/* Defined in auto-generated file i386-avx512-linux.c. */
86void init_registers_i386_avx512_linux (void);
87extern const struct target_desc *tdesc_i386_avx512_linux;
88
a196ebeb
WT		 89/* Defined in auto-generated file i386-mpx-linux.c. */
90void init_registers_i386_mpx_linux (void);
91extern const struct target_desc *tdesc_i386_mpx_linux;
92
3aee8918
PA		 93#ifdef __x86_64__
94static struct target_desc *tdesc_amd64_linux_no_xml;
95#endif
96static struct target_desc *tdesc_i386_linux_no_xml;
97
1570b33e 98
fa593d66 99static unsigned char jump_insn[] = { 0xe9, 0, 0, 0, 0 };
405f8e94 100static unsigned char small_jump_insn[] = { 0x66, 0xe9, 0, 0 };
fa593d66 101
1570b33e
L		 102/* Backward compatibility for gdb without XML support. */
103
104static const char *xmltarget_i386_linux_no_xml = "@<target>\
105<architecture>i386</architecture>\
106<osabi>GNU/Linux</osabi>\
107</target>";
f6d1620c
L		 108
109#ifdef __x86_64__
1570b33e
L		 110static const char *xmltarget_amd64_linux_no_xml = "@<target>\
111<architecture>i386:x86-64</architecture>\
112<osabi>GNU/Linux</osabi>\
113</target>";
f6d1620c 114#endif
d0722149
DE		 115
116#include <sys/reg.h>
117#include <sys/procfs.h>
118#include <sys/ptrace.h>
1570b33e
L		 119#include <sys/uio.h>
120
121#ifndef PTRACE_GETREGSET
122#define PTRACE_GETREGSET 0x4204
123#endif
124
125#ifndef PTRACE_SETREGSET
126#define PTRACE_SETREGSET 0x4205
127#endif
128
d0722149
DE		 129
130#ifndef PTRACE_GET_THREAD_AREA
131#define PTRACE_GET_THREAD_AREA 25
132#endif
133
134/* This definition comes from prctl.h, but some kernels may not have it. */
135#ifndef PTRACE_ARCH_PRCTL
136#define PTRACE_ARCH_PRCTL 30
137#endif
138
139/* The following definitions come from prctl.h, but may be absent
140 for certain configurations. */
141#ifndef ARCH_GET_FS
142#define ARCH_SET_GS 0x1001
143#define ARCH_SET_FS 0x1002
144#define ARCH_GET_FS 0x1003
145#define ARCH_GET_GS 0x1004
146#endif
147
aa5ca48f
DE		 148/* Per-process arch-specific data we want to keep. */
149
150struct arch_process_info
151{
152 struct i386_debug_reg_state debug_reg_state;
153};
154
155/* Per-thread arch-specific data we want to keep. */
156
157struct arch_lwp_info
158{
159 /* Non-zero if our copy differs from what's recorded in the thread. */
160 int debug_registers_changed;
161};
162
d0722149
DE		 163#ifdef __x86_64__
164
165/* Mapping between the general-purpose registers in `struct user'
166 format and GDB's register array layout.
167 Note that the transfer layout uses 64-bit regs. */
168static /*const*/ int i386_regmap[] =
169{
170 RAX * 8, RCX * 8, RDX * 8, RBX * 8,
171 RSP * 8, RBP * 8, RSI * 8, RDI * 8,
172 RIP * 8, EFLAGS * 8, CS * 8, SS * 8,
173 DS * 8, ES * 8, FS * 8, GS * 8
174};
175
176#define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
177
178/* So code below doesn't have to care, i386 or amd64. */
179#define ORIG_EAX ORIG_RAX
180
181static const int x86_64_regmap[] =
182{
183 RAX * 8, RBX * 8, RCX * 8, RDX * 8,
184 RSI * 8, RDI * 8, RBP * 8, RSP * 8,
185 R8 * 8, R9 * 8, R10 * 8, R11 * 8,
186 R12 * 8, R13 * 8, R14 * 8, R15 * 8,
187 RIP * 8, EFLAGS * 8, CS * 8, SS * 8,
188 DS * 8, ES * 8, FS * 8, GS * 8,
189 -1, -1, -1, -1, -1, -1, -1, -1,
190 -1, -1, -1, -1, -1, -1, -1, -1,
191 -1, -1, -1, -1, -1, -1, -1, -1,
a196ebeb
WT		 192 -1,
193 -1, -1, -1, -1, -1, -1, -1, -1,
194 ORIG_RAX * 8,
195 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
01f9f808
MS		 196 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
197 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
198 -1, -1, -1, -1, -1, -1, -1, -1,
199 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
200 -1, -1, -1, -1, -1, -1, -1, -1,
201 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
202 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
203 -1, -1, -1, -1, -1, -1, -1, -1,
204 -1, -1, -1, -1, -1, -1, -1, -1,
205 -1, -1, -1, -1, -1, -1, -1, -1
d0722149
DE		 206};
207
208#define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
9e0aa64f 209#define X86_64_USER_REGS (GS + 1)
d0722149
DE		 210
211#else /* ! __x86_64__ */
212
213/* Mapping between the general-purpose registers in `struct user'
214 format and GDB's register array layout. */
215static /*const*/ int i386_regmap[] =
216{
217 EAX * 4, ECX * 4, EDX * 4, EBX * 4,
218 UESP * 4, EBP * 4, ESI * 4, EDI * 4,
219 EIP * 4, EFL * 4, CS * 4, SS * 4,
220 DS * 4, ES * 4, FS * 4, GS * 4
221};
222
223#define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
224
225#endif
3aee8918
PA		 226
227#ifdef __x86_64__
228
229/* Returns true if the current inferior belongs to a x86-64 process,
230 per the tdesc. */
231
232static int
233is_64bit_tdesc (void)
234{
235 struct regcache *regcache = get_thread_regcache (current_inferior, 0);
236
237 return register_size (regcache->tdesc, 0) == 8;
238}
239
240#endif
241
d0722149
DE		 242\f
243/* Called by libthread_db. */
244
245ps_err_e
246ps_get_thread_area (const struct ps_prochandle *ph,
247 lwpid_t lwpid, int idx, void **base)
248{
249#ifdef __x86_64__
3aee8918 250 int use_64bit = is_64bit_tdesc ();
d0722149
DE		 251
252 if (use_64bit)
253 {
254 switch (idx)
255 {
256 case FS:
257 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_FS) == 0)
258 return PS_OK;
259 break;
260 case GS:
261 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_GS) == 0)
262 return PS_OK;
263 break;
264 default:
265 return PS_BADADDR;
266 }
267 return PS_ERR;
268 }
269#endif
270
271 {
272 unsigned int desc[4];
273
274 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid,
275 (void *) (intptr_t) idx, (unsigned long) &desc) < 0)
276 return PS_ERR;
277
d1ec4ce7
DE		 278 /* Ensure we properly extend the value to 64-bits for x86_64. */
279 *base = (void *) (uintptr_t) desc[1];
d0722149
DE		 280 return PS_OK;
281 }
282}
fa593d66
PA		 283
284/* Get the thread area address. This is used to recognize which
285 thread is which when tracing with the in-process agent library. We
286 don't read anything from the address, and treat it as opaque; it's
287 the address itself that we assume is unique per-thread. */
288
289static int
290x86_get_thread_area (int lwpid, CORE_ADDR *addr)
291{
292#ifdef __x86_64__
3aee8918 293 int use_64bit = is_64bit_tdesc ();
fa593d66
PA		 294
295 if (use_64bit)
296 {
297 void *base;
298 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_FS) == 0)
299 {
300 *addr = (CORE_ADDR) (uintptr_t) base;
301 return 0;
302 }
303
304 return -1;
305 }
306#endif
307
308 {
309 struct lwp_info *lwp = find_lwp_pid (pid_to_ptid (lwpid));
d86d4aaf
DE		 310 struct thread_info *thr = get_lwp_thread (lwp);
311 struct regcache *regcache = get_thread_regcache (thr, 1);
fa593d66
PA		 312 unsigned int desc[4];
313 ULONGEST gs = 0;
314 const int reg_thread_area = 3; /* bits to scale down register value. */
315 int idx;
316
317 collect_register_by_name (regcache, "gs", &gs);
318
319 idx = gs >> reg_thread_area;
320
321 if (ptrace (PTRACE_GET_THREAD_AREA,
d86d4aaf 322 lwpid_of (thr),
493e2a69 323 (void *) (long) idx, (unsigned long) &desc) < 0)
fa593d66
PA		 324 return -1;
325
326 *addr = desc[1];
327 return 0;
328 }
329}
330
331
d0722149
DE		 332\f
333static int
3aee8918 334x86_cannot_store_register (int regno)
d0722149 335{
3aee8918
PA		 336#ifdef __x86_64__
337 if (is_64bit_tdesc ())
338 return 0;
339#endif
340
d0722149
DE		 341 return regno >= I386_NUM_REGS;
342}
343
344static int
3aee8918 345x86_cannot_fetch_register (int regno)
d0722149 346{
3aee8918
PA		 347#ifdef __x86_64__
348 if (is_64bit_tdesc ())
349 return 0;
350#endif
351
d0722149
DE		 352 return regno >= I386_NUM_REGS;
353}
354
355static void
442ea881 356x86_fill_gregset (struct regcache *regcache, void *buf)
d0722149
DE		 357{
358 int i;
359
360#ifdef __x86_64__
3aee8918 361 if (register_size (regcache->tdesc, 0) == 8)
d0722149
DE		 362 {
363 for (i = 0; i < X86_64_NUM_REGS; i++)
364 if (x86_64_regmap[i] != -1)
442ea881 365 collect_register (regcache, i, ((char *) buf) + x86_64_regmap[i]);
d0722149
DE		 366 return;
367 }
9e0aa64f
JK		 368
369 /* 32-bit inferior registers need to be zero-extended.
370 Callers would read uninitialized memory otherwise. */
371 memset (buf, 0x00, X86_64_USER_REGS * 8);
d0722149
DE		 372#endif
373
374 for (i = 0; i < I386_NUM_REGS; i++)
442ea881 375 collect_register (regcache, i, ((char *) buf) + i386_regmap[i]);
d0722149 376
442ea881
PA		 377 collect_register_by_name (regcache, "orig_eax",
378 ((char *) buf) + ORIG_EAX * 4);
d0722149
DE		 379}
380
381static void
442ea881 382x86_store_gregset (struct regcache *regcache, const void *buf)
d0722149
DE		 383{
384 int i;
385
386#ifdef __x86_64__
3aee8918 387 if (register_size (regcache->tdesc, 0) == 8)
d0722149
DE		 388 {
389 for (i = 0; i < X86_64_NUM_REGS; i++)
390 if (x86_64_regmap[i] != -1)
442ea881 391 supply_register (regcache, i, ((char *) buf) + x86_64_regmap[i]);
d0722149
DE		 392 return;
393 }
394#endif
395
396 for (i = 0; i < I386_NUM_REGS; i++)
442ea881 397 supply_register (regcache, i, ((char *) buf) + i386_regmap[i]);
d0722149 398
442ea881
PA		 399 supply_register_by_name (regcache, "orig_eax",
400 ((char *) buf) + ORIG_EAX * 4);
d0722149
DE		 401}
402
403static void
442ea881 404x86_fill_fpregset (struct regcache *regcache, void *buf)
d0722149
DE		 405{
406#ifdef __x86_64__
442ea881 407 i387_cache_to_fxsave (regcache, buf);
d0722149 408#else
442ea881 409 i387_cache_to_fsave (regcache, buf);
d0722149
DE		 410#endif
411}
412
413static void
442ea881 414x86_store_fpregset (struct regcache *regcache, const void *buf)
d0722149
DE		 415{
416#ifdef __x86_64__
442ea881 417 i387_fxsave_to_cache (regcache, buf);
d0722149 418#else
442ea881 419 i387_fsave_to_cache (regcache, buf);
d0722149
DE		 420#endif
421}
422
423#ifndef __x86_64__
424
425static void
442ea881 426x86_fill_fpxregset (struct regcache *regcache, void *buf)
d0722149 427{
442ea881 428 i387_cache_to_fxsave (regcache, buf);
d0722149
DE		 429}
430
431static void
442ea881 432x86_store_fpxregset (struct regcache *regcache, const void *buf)
d0722149 433{
442ea881 434 i387_fxsave_to_cache (regcache, buf);
d0722149
DE		 435}
436
437#endif
438
1570b33e
L		 439static void
440x86_fill_xstateregset (struct regcache *regcache, void *buf)
441{
442 i387_cache_to_xsave (regcache, buf);
443}
444
445static void
446x86_store_xstateregset (struct regcache *regcache, const void *buf)
447{
448 i387_xsave_to_cache (regcache, buf);
449}
450
d0722149
DE		 451/* ??? The non-biarch i386 case stores all the i387 regs twice.
452 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
453 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
454 doesn't work. IWBN to avoid the duplication in the case where it
455 does work. Maybe the arch_setup routine could check whether it works
3aee8918 456 and update the supported regsets accordingly. */
d0722149 457
3aee8918 458static struct regset_info x86_regsets[] =
d0722149
DE		 459{
460#ifdef HAVE_PTRACE_GETREGS
1570b33e 461 { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t),
d0722149
DE		 462 GENERAL_REGS,
463 x86_fill_gregset, x86_store_gregset },
1570b33e
L		 464 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_X86_XSTATE, 0,
465 EXTENDED_REGS, x86_fill_xstateregset, x86_store_xstateregset },
d0722149
DE		 466# ifndef __x86_64__
467# ifdef HAVE_PTRACE_GETFPXREGS
1570b33e 468 { PTRACE_GETFPXREGS, PTRACE_SETFPXREGS, 0, sizeof (elf_fpxregset_t),
d0722149
DE		 469 EXTENDED_REGS,
470 x86_fill_fpxregset, x86_store_fpxregset },
471# endif
472# endif
1570b33e 473 { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, sizeof (elf_fpregset_t),
d0722149
DE		 474 FP_REGS,
475 x86_fill_fpregset, x86_store_fpregset },
476#endif /* HAVE_PTRACE_GETREGS */
1570b33e 477 { 0, 0, 0, -1, -1, NULL, NULL }
d0722149
DE		 478};
479
480static CORE_ADDR
442ea881 481x86_get_pc (struct regcache *regcache)
d0722149 482{
3aee8918 483 int use_64bit = register_size (regcache->tdesc, 0) == 8;
d0722149
DE		 484
485 if (use_64bit)
486 {
487 unsigned long pc;
442ea881 488 collect_register_by_name (regcache, "rip", &pc);
d0722149
DE		 489 return (CORE_ADDR) pc;
490 }
491 else
492 {
493 unsigned int pc;
442ea881 494 collect_register_by_name (regcache, "eip", &pc);
d0722149
DE		 495 return (CORE_ADDR) pc;
496 }
497}
498
499static void
442ea881 500x86_set_pc (struct regcache *regcache, CORE_ADDR pc)
d0722149 501{
3aee8918 502 int use_64bit = register_size (regcache->tdesc, 0) == 8;
d0722149
DE		 503
504 if (use_64bit)
505 {
506 unsigned long newpc = pc;
442ea881 507 supply_register_by_name (regcache, "rip", &newpc);
d0722149
DE		 508 }
509 else
510 {
511 unsigned int newpc = pc;
442ea881 512 supply_register_by_name (regcache, "eip", &newpc);
d0722149
DE		 513 }
514}
515\f
516static const unsigned char x86_breakpoint[] = { 0xCC };
517#define x86_breakpoint_len 1
518
519static int
520x86_breakpoint_at (CORE_ADDR pc)
521{
522 unsigned char c;
523
fc7238bb 524 (*the_target->read_memory) (pc, &c, 1);
d0722149
DE		 525 if (c == 0xCC)
526 return 1;
527
528 return 0;
529}
530\f
aa5ca48f
DE		 531/* Support for debug registers. */
532
533static unsigned long
534x86_linux_dr_get (ptid_t ptid, int regnum)
535{
536 int tid;
537 unsigned long value;
538
539 tid = ptid_get_lwp (ptid);
540
541 errno = 0;
542 value = ptrace (PTRACE_PEEKUSER, tid,
543 offsetof (struct user, u_debugreg[regnum]), 0);
544 if (errno != 0)
545 error ("Couldn't read debug register");
546
547 return value;
548}
549
550static void
551x86_linux_dr_set (ptid_t ptid, int regnum, unsigned long value)
552{
553 int tid;
554
555 tid = ptid_get_lwp (ptid);
556
557 errno = 0;
558 ptrace (PTRACE_POKEUSER, tid,
559 offsetof (struct user, u_debugreg[regnum]), value);
560 if (errno != 0)
561 error ("Couldn't write debug register");
562}
563
964e4306
PA		 564static int
565update_debug_registers_callback (struct inferior_list_entry *entry,
566 void *pid_p)
567{
d86d4aaf
DE		 568 struct thread_info *thr = (struct thread_info *) entry;
569 struct lwp_info *lwp = get_thread_lwp (thr);
964e4306
PA		 570 int pid = *(int *) pid_p;
571
572 /* Only update the threads of this process. */
d86d4aaf 573 if (pid_of (thr) == pid)
964e4306
PA		 574 {
575 /* The actual update is done later just before resuming the lwp,
576 we just mark that the registers need updating. */
577 lwp->arch_private->debug_registers_changed = 1;
578
579 /* If the lwp isn't stopped, force it to momentarily pause, so
580 we can update its debug registers. */
581 if (!lwp->stopped)
582 linux_stop_lwp (lwp);
583 }
584
585 return 0;
586}
587
aa5ca48f
DE		 588/* Update the inferior's debug register REGNUM from STATE. */
589
590void
591i386_dr_low_set_addr (const struct i386_debug_reg_state *state, int regnum)
592{
964e4306 593 /* Only update the threads of this process. */
d86d4aaf 594 int pid = pid_of (current_inferior);
aa5ca48f
DE		 595
596 if (! (regnum >= 0 && regnum <= DR_LASTADDR - DR_FIRSTADDR))
597 fatal ("Invalid debug register %d", regnum);
598
d86d4aaf 599 find_inferior (&all_threads, update_debug_registers_callback, &pid);
964e4306 600}
aa5ca48f 601
964e4306 602/* Return the inferior's debug register REGNUM. */
aa5ca48f 603
964e4306
PA		 604CORE_ADDR
605i386_dr_low_get_addr (int regnum)
606{
d86d4aaf 607 ptid_t ptid = ptid_of (current_inferior);
964e4306
PA		 608
609 /* DR6 and DR7 are retrieved with some other way. */
0a5b1e09 610 gdb_assert (DR_FIRSTADDR <= regnum && regnum <= DR_LASTADDR);
964e4306
PA		 611
612 return x86_linux_dr_get (ptid, regnum);
aa5ca48f
DE		 613}
614
615/* Update the inferior's DR7 debug control register from STATE. */
616
617void
618i386_dr_low_set_control (const struct i386_debug_reg_state *state)
619{
964e4306 620 /* Only update the threads of this process. */
d86d4aaf 621 int pid = pid_of (current_inferior);
aa5ca48f 622
d86d4aaf 623 find_inferior (&all_threads, update_debug_registers_callback, &pid);
964e4306 624}
aa5ca48f 625
964e4306
PA		 626/* Return the inferior's DR7 debug control register. */
627
628unsigned
629i386_dr_low_get_control (void)
630{
d86d4aaf 631 ptid_t ptid = ptid_of (current_inferior);
964e4306
PA		 632
633 return x86_linux_dr_get (ptid, DR_CONTROL);
aa5ca48f
DE		 634}
635
636/* Get the value of the DR6 debug status register from the inferior
637 and record it in STATE. */
638
964e4306
PA		 639unsigned
640i386_dr_low_get_status (void)
aa5ca48f 641{
d86d4aaf 642 ptid_t ptid = ptid_of (current_inferior);
aa5ca48f 643
964e4306 644 return x86_linux_dr_get (ptid, DR_STATUS);
aa5ca48f
DE		 645}
646\f
90d74c30 647/* Breakpoint/Watchpoint support. */
aa5ca48f
DE		 648
649static int
650x86_insert_point (char type, CORE_ADDR addr, int len)
651{
652 struct process_info *proc = current_process ();
653 switch (type)
654 {
961bd387 655 case '0': /* software-breakpoint */
90d74c30
PA		 656 {
657 int ret;
658
659 ret = prepare_to_access_memory ();
660 if (ret)
661 return -1;
662 ret = set_gdb_breakpoint_at (addr);
0146f85b 663 done_accessing_memory ();
90d74c30
PA		 664 return ret;
665 }
961bd387
ME		 666 case '1': /* hardware-breakpoint */
667 case '2': /* write watchpoint */
668 case '3': /* read watchpoint */
669 case '4': /* access watchpoint */
a4165e94
PA		 670 {
671 enum target_hw_bp_type hw_type = Z_packet_to_hw_type (type);
672 struct i386_debug_reg_state *state
673 = &proc->private->arch_private->debug_reg_state;
674
675 return i386_low_insert_watchpoint (state, hw_type, addr, len);
676 }
961bd387 677
aa5ca48f
DE		 678 default:
679 /* Unsupported. */
680 return 1;
681 }
682}
683
684static int
685x86_remove_point (char type, CORE_ADDR addr, int len)
686{
687 struct process_info *proc = current_process ();
688 switch (type)
689 {
961bd387 690 case '0': /* software-breakpoint */
90d74c30
PA		 691 {
692 int ret;
693
694 ret = prepare_to_access_memory ();
695 if (ret)
696 return -1;
697 ret = delete_gdb_breakpoint_at (addr);
0146f85b 698 done_accessing_memory ();
90d74c30
PA		 699 return ret;
700 }
961bd387
ME		 701 case '1': /* hardware-breakpoint */
702 case '2': /* write watchpoint */
703 case '3': /* read watchpoint */
704 case '4': /* access watchpoint */
a4165e94
PA		 705 {
706 enum target_hw_bp_type hw_type = Z_packet_to_hw_type (type);
707 struct i386_debug_reg_state *state
708 = &proc->private->arch_private->debug_reg_state;
709
710 return i386_low_remove_watchpoint (state, hw_type, addr, len);
711 }
aa5ca48f
DE		 712 default:
713 /* Unsupported. */
714 return 1;
715 }
716}
717
718static int
719x86_stopped_by_watchpoint (void)
720{
721 struct process_info *proc = current_process ();
722 return i386_low_stopped_by_watchpoint (&proc->private->arch_private->debug_reg_state);
723}
724
725static CORE_ADDR
726x86_stopped_data_address (void)
727{
728 struct process_info *proc = current_process ();
729 CORE_ADDR addr;
730 if (i386_low_stopped_data_address (&proc->private->arch_private->debug_reg_state,
731 &addr))
732 return addr;
733 return 0;
734}
735\f
736/* Called when a new process is created. */
737
738static struct arch_process_info *
739x86_linux_new_process (void)
740{
741 struct arch_process_info *info = xcalloc (1, sizeof (*info));
742
743 i386_low_init_dregs (&info->debug_reg_state);
744
745 return info;
746}
747
748/* Called when a new thread is detected. */
749
750static struct arch_lwp_info *
751x86_linux_new_thread (void)
752{
753 struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
754
755 info->debug_registers_changed = 1;
756
757 return info;
758}
759
760/* Called when resuming a thread.
761 If the debug regs have changed, update the thread's copies. */
762
763static void
764x86_linux_prepare_to_resume (struct lwp_info *lwp)
765{
d86d4aaf 766 ptid_t ptid = ptid_of (get_lwp_thread (lwp));
6210a125 767 int clear_status = 0;
b9a881c2 768
aa5ca48f
DE		 769 if (lwp->arch_private->debug_registers_changed)
770 {
771 int i;
aa5ca48f
DE		 772 int pid = ptid_get_pid (ptid);
773 struct process_info *proc = find_process_pid (pid);
493e2a69
MS		 774 struct i386_debug_reg_state *state
775 = &proc->private->arch_private->debug_reg_state;
aa5ca48f
DE		 776
777 for (i = DR_FIRSTADDR; i <= DR_LASTADDR; i++)
6210a125
PA		 778 if (state->dr_ref_count[i] > 0)
779 {
780 x86_linux_dr_set (ptid, i, state->dr_mirror[i]);
781
782 /* If we're setting a watchpoint, any change the inferior
783 had done itself to the debug registers needs to be
784 discarded, otherwise, i386_low_stopped_data_address can
785 get confused. */
786 clear_status = 1;
787 }
aa5ca48f
DE		 788
789 x86_linux_dr_set (ptid, DR_CONTROL, state->dr_control_mirror);
790
791 lwp->arch_private->debug_registers_changed = 0;
792 }
b9a881c2 793
6210a125 794 if (clear_status || lwp->stopped_by_watchpoint)
b9a881c2 795 x86_linux_dr_set (ptid, DR_STATUS, 0);
aa5ca48f
DE		 796}
797\f
d0722149
DE		 798/* When GDBSERVER is built as a 64-bit application on linux, the
799 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
800 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
801 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
802 conversion in-place ourselves. */
803
804/* These types below (compat_*) define a siginfo type that is layout
805 compatible with the siginfo type exported by the 32-bit userspace
806 support. */
807
808#ifdef __x86_64__
809
810typedef int compat_int_t;
811typedef unsigned int compat_uptr_t;
812
813typedef int compat_time_t;
814typedef int compat_timer_t;
815typedef int compat_clock_t;
816
817struct compat_timeval
818{
819 compat_time_t tv_sec;
820 int tv_usec;
821};
822
823typedef union compat_sigval
824{
825 compat_int_t sival_int;
826 compat_uptr_t sival_ptr;
827} compat_sigval_t;
828
829typedef struct compat_siginfo
830{
831 int si_signo;
832 int si_errno;
833 int si_code;
834
835 union
836 {
837 int _pad[((128 / sizeof (int)) - 3)];
838
839 /* kill() */
840 struct
841 {
842 unsigned int _pid;
843 unsigned int _uid;
844 } _kill;
845
846 /* POSIX.1b timers */
847 struct
848 {
849 compat_timer_t _tid;
850 int _overrun;
851 compat_sigval_t _sigval;
852 } _timer;
853
854 /* POSIX.1b signals */
855 struct
856 {
857 unsigned int _pid;
858 unsigned int _uid;
859 compat_sigval_t _sigval;
860 } _rt;
861
862 /* SIGCHLD */
863 struct
864 {
865 unsigned int _pid;
866 unsigned int _uid;
867 int _status;
868 compat_clock_t _utime;
869 compat_clock_t _stime;
870 } _sigchld;
871
872 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
873 struct
874 {
875 unsigned int _addr;
876 } _sigfault;
877
878 /* SIGPOLL */
879 struct
880 {
881 int _band;
882 int _fd;
883 } _sigpoll;
884 } _sifields;
885} compat_siginfo_t;
886
c92b5177
L		 887/* For x32, clock_t in _sigchld is 64bit aligned at 4 bytes. */
888typedef long __attribute__ ((__aligned__ (4))) compat_x32_clock_t;
889
890typedef struct compat_x32_siginfo
891{
892 int si_signo;
893 int si_errno;
894 int si_code;
895
896 union
897 {
898 int _pad[((128 / sizeof (int)) - 3)];
899
900 /* kill() */
901 struct
902 {
903 unsigned int _pid;
904 unsigned int _uid;
905 } _kill;
906
907 /* POSIX.1b timers */
908 struct
909 {
910 compat_timer_t _tid;
911 int _overrun;
912 compat_sigval_t _sigval;
913 } _timer;
914
915 /* POSIX.1b signals */
916 struct
917 {
918 unsigned int _pid;
919 unsigned int _uid;
920 compat_sigval_t _sigval;
921 } _rt;
922
923 /* SIGCHLD */
924 struct
925 {
926 unsigned int _pid;
927 unsigned int _uid;
928 int _status;
929 compat_x32_clock_t _utime;
930 compat_x32_clock_t _stime;
931 } _sigchld;
932
933 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
934 struct
935 {
936 unsigned int _addr;
937 } _sigfault;
938
939 /* SIGPOLL */
940 struct
941 {
942 int _band;
943 int _fd;
944 } _sigpoll;
945 } _sifields;
946} compat_x32_siginfo_t __attribute__ ((__aligned__ (8)));
947
d0722149
DE		 948#define cpt_si_pid _sifields._kill._pid
949#define cpt_si_uid _sifields._kill._uid
950#define cpt_si_timerid _sifields._timer._tid
951#define cpt_si_overrun _sifields._timer._overrun
952#define cpt_si_status _sifields._sigchld._status
953#define cpt_si_utime _sifields._sigchld._utime
954#define cpt_si_stime _sifields._sigchld._stime
955#define cpt_si_ptr _sifields._rt._sigval.sival_ptr
956#define cpt_si_addr _sifields._sigfault._addr
957#define cpt_si_band _sifields._sigpoll._band
958#define cpt_si_fd _sifields._sigpoll._fd
959
960/* glibc at least up to 2.3.2 doesn't have si_timerid, si_overrun.
961 In their place is si_timer1,si_timer2. */
962#ifndef si_timerid
963#define si_timerid si_timer1
964#endif
965#ifndef si_overrun
966#define si_overrun si_timer2
967#endif
968
969static void
970compat_siginfo_from_siginfo (compat_siginfo_t *to, siginfo_t *from)
971{
972 memset (to, 0, sizeof (*to));
973
974 to->si_signo = from->si_signo;
975 to->si_errno = from->si_errno;
976 to->si_code = from->si_code;
977
b53a1623 978 if (to->si_code == SI_TIMER)
d0722149 979 {
b53a1623
PA		 980 to->cpt_si_timerid = from->si_timerid;
981 to->cpt_si_overrun = from->si_overrun;
d0722149
DE		 982 to->cpt_si_ptr = (intptr_t) from->si_ptr;
983 }
984 else if (to->si_code == SI_USER)
985 {
986 to->cpt_si_pid = from->si_pid;
987 to->cpt_si_uid = from->si_uid;
988 }
b53a1623 989 else if (to->si_code < 0)
d0722149 990 {
b53a1623
PA		 991 to->cpt_si_pid = from->si_pid;
992 to->cpt_si_uid = from->si_uid;
d0722149
DE		 993 to->cpt_si_ptr = (intptr_t) from->si_ptr;
994 }
995 else
996 {
997 switch (to->si_signo)
998 {
999 case SIGCHLD:
1000 to->cpt_si_pid = from->si_pid;
1001 to->cpt_si_uid = from->si_uid;
1002 to->cpt_si_status = from->si_status;
1003 to->cpt_si_utime = from->si_utime;
1004 to->cpt_si_stime = from->si_stime;
1005 break;
1006 case SIGILL:
1007 case SIGFPE:
1008 case SIGSEGV:
1009 case SIGBUS:
1010 to->cpt_si_addr = (intptr_t) from->si_addr;
1011 break;
1012 case SIGPOLL:
1013 to->cpt_si_band = from->si_band;
1014 to->cpt_si_fd = from->si_fd;
1015 break;
1016 default:
1017 to->cpt_si_pid = from->si_pid;
1018 to->cpt_si_uid = from->si_uid;
1019 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1020 break;
1021 }
1022 }
1023}
1024
1025static void
1026siginfo_from_compat_siginfo (siginfo_t *to, compat_siginfo_t *from)
1027{
1028 memset (to, 0, sizeof (*to));
1029
1030 to->si_signo = from->si_signo;
1031 to->si_errno = from->si_errno;
1032 to->si_code = from->si_code;
1033
b53a1623 1034 if (to->si_code == SI_TIMER)
d0722149 1035 {
b53a1623
PA		 1036 to->si_timerid = from->cpt_si_timerid;
1037 to->si_overrun = from->cpt_si_overrun;
d0722149
DE		 1038 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1039 }
1040 else if (to->si_code == SI_USER)
1041 {
1042 to->si_pid = from->cpt_si_pid;
1043 to->si_uid = from->cpt_si_uid;
1044 }
b53a1623 1045 else if (to->si_code < 0)
d0722149 1046 {
b53a1623
PA		 1047 to->si_pid = from->cpt_si_pid;
1048 to->si_uid = from->cpt_si_uid;
d0722149
DE		 1049 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1050 }
1051 else
1052 {
1053 switch (to->si_signo)
1054 {
1055 case SIGCHLD:
1056 to->si_pid = from->cpt_si_pid;
1057 to->si_uid = from->cpt_si_uid;
1058 to->si_status = from->cpt_si_status;
1059 to->si_utime = from->cpt_si_utime;
1060 to->si_stime = from->cpt_si_stime;
1061 break;
1062 case SIGILL:
1063 case SIGFPE:
1064 case SIGSEGV:
1065 case SIGBUS:
1066 to->si_addr = (void *) (intptr_t) from->cpt_si_addr;
1067 break;
1068 case SIGPOLL:
1069 to->si_band = from->cpt_si_band;
1070 to->si_fd = from->cpt_si_fd;
1071 break;
1072 default:
1073 to->si_pid = from->cpt_si_pid;
1074 to->si_uid = from->cpt_si_uid;
1075 to->si_ptr = (void* ) (intptr_t) from->cpt_si_ptr;
1076 break;
1077 }
1078 }
1079}
1080
c92b5177
L		 1081static void
1082compat_x32_siginfo_from_siginfo (compat_x32_siginfo_t *to,
1083 siginfo_t *from)
1084{
1085 memset (to, 0, sizeof (*to));
1086
1087 to->si_signo = from->si_signo;
1088 to->si_errno = from->si_errno;
1089 to->si_code = from->si_code;
1090
1091 if (to->si_code == SI_TIMER)
1092 {
1093 to->cpt_si_timerid = from->si_timerid;
1094 to->cpt_si_overrun = from->si_overrun;
1095 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1096 }
1097 else if (to->si_code == SI_USER)
1098 {
1099 to->cpt_si_pid = from->si_pid;
1100 to->cpt_si_uid = from->si_uid;
1101 }
1102 else if (to->si_code < 0)
1103 {
1104 to->cpt_si_pid = from->si_pid;
1105 to->cpt_si_uid = from->si_uid;
1106 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1107 }
1108 else
1109 {
1110 switch (to->si_signo)
1111 {
1112 case SIGCHLD:
1113 to->cpt_si_pid = from->si_pid;
1114 to->cpt_si_uid = from->si_uid;
1115 to->cpt_si_status = from->si_status;
1116 to->cpt_si_utime = from->si_utime;
1117 to->cpt_si_stime = from->si_stime;
1118 break;
1119 case SIGILL:
1120 case SIGFPE:
1121 case SIGSEGV:
1122 case SIGBUS:
1123 to->cpt_si_addr = (intptr_t) from->si_addr;
1124 break;
1125 case SIGPOLL:
1126 to->cpt_si_band = from->si_band;
1127 to->cpt_si_fd = from->si_fd;
1128 break;
1129 default:
1130 to->cpt_si_pid = from->si_pid;
1131 to->cpt_si_uid = from->si_uid;
1132 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1133 break;
1134 }
1135 }
1136}
1137
1138static void
1139siginfo_from_compat_x32_siginfo (siginfo_t *to,
1140 compat_x32_siginfo_t *from)
1141{
1142 memset (to, 0, sizeof (*to));
1143
1144 to->si_signo = from->si_signo;
1145 to->si_errno = from->si_errno;
1146 to->si_code = from->si_code;
1147
1148 if (to->si_code == SI_TIMER)
1149 {
1150 to->si_timerid = from->cpt_si_timerid;
1151 to->si_overrun = from->cpt_si_overrun;
1152 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1153 }
1154 else if (to->si_code == SI_USER)
1155 {
1156 to->si_pid = from->cpt_si_pid;
1157 to->si_uid = from->cpt_si_uid;
1158 }
1159 else if (to->si_code < 0)
1160 {
1161 to->si_pid = from->cpt_si_pid;
1162 to->si_uid = from->cpt_si_uid;
1163 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1164 }
1165 else
1166 {
1167 switch (to->si_signo)
1168 {
1169 case SIGCHLD:
1170 to->si_pid = from->cpt_si_pid;
1171 to->si_uid = from->cpt_si_uid;
1172 to->si_status = from->cpt_si_status;
1173 to->si_utime = from->cpt_si_utime;
1174 to->si_stime = from->cpt_si_stime;
1175 break;
1176 case SIGILL:
1177 case SIGFPE:
1178 case SIGSEGV:
1179 case SIGBUS:
1180 to->si_addr = (void *) (intptr_t) from->cpt_si_addr;
1181 break;
1182 case SIGPOLL:
1183 to->si_band = from->cpt_si_band;
1184 to->si_fd = from->cpt_si_fd;
1185 break;
1186 default:
1187 to->si_pid = from->cpt_si_pid;
1188 to->si_uid = from->cpt_si_uid;
1189 to->si_ptr = (void* ) (intptr_t) from->cpt_si_ptr;
1190 break;
1191 }
1192 }
1193}
1194
d0722149
DE		 1195#endif /* __x86_64__ */
1196
1197/* Convert a native/host siginfo object, into/from the siginfo in the
1198 layout of the inferiors' architecture. Returns true if any
1199 conversion was done; false otherwise. If DIRECTION is 1, then copy
1200 from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to
1201 INF. */
1202
1203static int
a5362b9a 1204x86_siginfo_fixup (siginfo_t *native, void *inf, int direction)
d0722149
DE		 1205{
1206#ifdef __x86_64__
760256f9 1207 unsigned int machine;
d86d4aaf 1208 int tid = lwpid_of (current_inferior);
760256f9
PA		 1209 int is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
1210
d0722149 1211 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
3aee8918 1212 if (!is_64bit_tdesc ())
d0722149 1213 {
a5362b9a 1214 if (sizeof (siginfo_t) != sizeof (compat_siginfo_t))
9f1036c1 1215 fatal ("unexpected difference in siginfo");
d0722149
DE		 1216
1217 if (direction == 0)
1218 compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, native);
1219 else
1220 siginfo_from_compat_siginfo (native, (struct compat_siginfo *) inf);
1221
c92b5177
L		 1222 return 1;
1223 }
1224 /* No fixup for native x32 GDB. */
760256f9 1225 else if (!is_elf64 && sizeof (void *) == 8)
c92b5177
L		 1226 {
1227 if (sizeof (siginfo_t) != sizeof (compat_x32_siginfo_t))
1228 fatal ("unexpected difference in siginfo");
1229
1230 if (direction == 0)
1231 compat_x32_siginfo_from_siginfo ((struct compat_x32_siginfo *) inf,
1232 native);
1233 else
1234 siginfo_from_compat_x32_siginfo (native,
1235 (struct compat_x32_siginfo *) inf);
1236
d0722149
DE		 1237 return 1;
1238 }
1239#endif
1240
1241 return 0;
1242}
1243\f
1570b33e
L		 1244static int use_xml;
1245
3aee8918
PA		 1246/* Format of XSAVE extended state is:
1247 struct
1248 {
1249 fxsave_bytes[0..463]
1250 sw_usable_bytes[464..511]
1251 xstate_hdr_bytes[512..575]
1252 avx_bytes[576..831]
1253 future_state etc
1254 };
1255
1256 Same memory layout will be used for the coredump NT_X86_XSTATE
1257 representing the XSAVE extended state registers.
1258
1259 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
1260 extended state mask, which is the same as the extended control register
1261 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
1262 together with the mask saved in the xstate_hdr_bytes to determine what
1263 states the processor/OS supports and what state, used or initialized,
1264 the process/thread is in. */
1265#define I386_LINUX_XSAVE_XCR0_OFFSET 464
1266
1267/* Does the current host support the GETFPXREGS request? The header
1268 file may or may not define it, and even if it is defined, the
1269 kernel will return EIO if it's running on a pre-SSE processor. */
1270int have_ptrace_getfpxregs =
1271#ifdef HAVE_PTRACE_GETFPXREGS
1272 -1
1273#else
1274 0
1275#endif
1276;
1570b33e 1277
3aee8918
PA		 1278/* Does the current host support PTRACE_GETREGSET? */
1279static int have_ptrace_getregset = -1;
1280
1281/* Get Linux/x86 target description from running target. */
1282
1283static const struct target_desc *
1284x86_linux_read_description (void)
1570b33e 1285{
3aee8918
PA		 1286 unsigned int machine;
1287 int is_elf64;
a196ebeb 1288 int xcr0_features;
3aee8918
PA		 1289 int tid;
1290 static uint64_t xcr0;
3a13a53b 1291 struct regset_info *regset;
1570b33e 1292
d86d4aaf 1293 tid = lwpid_of (current_inferior);
1570b33e 1294
3aee8918 1295 is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
45ba0d02 1296
3aee8918 1297 if (sizeof (void *) == 4)
3a13a53b 1298 {
3aee8918
PA		 1299 if (is_elf64 > 0)
1300 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
1301#ifndef __x86_64__
1302 else if (machine == EM_X86_64)
1303 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
1304#endif
1305 }
3a13a53b 1306
3aee8918
PA		 1307#if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
1308 if (machine == EM_386 && have_ptrace_getfpxregs == -1)
1309 {
1310 elf_fpxregset_t fpxregs;
3a13a53b 1311
3aee8918 1312 if (ptrace (PTRACE_GETFPXREGS, tid, 0, (long) &fpxregs) < 0)
3a13a53b 1313 {
3aee8918
PA		 1314 have_ptrace_getfpxregs = 0;
1315 have_ptrace_getregset = 0;
1316 return tdesc_i386_mmx_linux;
3a13a53b 1317 }
3aee8918
PA		 1318 else
1319 have_ptrace_getfpxregs = 1;
3a13a53b 1320 }
1570b33e
L		 1321#endif
1322
1323 if (!use_xml)
1324 {
3aee8918
PA		 1325 x86_xcr0 = I386_XSTATE_SSE_MASK;
1326
1570b33e
L		 1327 /* Don't use XML. */
1328#ifdef __x86_64__
3aee8918
PA		 1329 if (machine == EM_X86_64)
1330 return tdesc_amd64_linux_no_xml;
1570b33e 1331 else
1570b33e 1332#endif
3aee8918 1333 return tdesc_i386_linux_no_xml;
1570b33e
L		 1334 }
1335
1570b33e
L		 1336 if (have_ptrace_getregset == -1)
1337 {
3aee8918 1338 uint64_t xstateregs[(I386_XSTATE_SSE_SIZE / sizeof (uint64_t))];
1570b33e 1339 struct iovec iov;
1570b33e
L		 1340
1341 iov.iov_base = xstateregs;
1342 iov.iov_len = sizeof (xstateregs);
1343
1344 /* Check if PTRACE_GETREGSET works. */
3aee8918
PA		 1345 if (ptrace (PTRACE_GETREGSET, tid,
1346 (unsigned int) NT_X86_XSTATE, (long) &iov) < 0)
1347 have_ptrace_getregset = 0;
1348 else
1570b33e 1349 {
3aee8918
PA		 1350 have_ptrace_getregset = 1;
1351
1352 /* Get XCR0 from XSAVE extended state. */
1353 xcr0 = xstateregs[(I386_LINUX_XSAVE_XCR0_OFFSET
1354 / sizeof (uint64_t))];
1355
1356 /* Use PTRACE_GETREGSET if it is available. */
1357 for (regset = x86_regsets;
1358 regset->fill_function != NULL; regset++)
1359 if (regset->get_request == PTRACE_GETREGSET)
1360 regset->size = I386_XSTATE_SIZE (xcr0);
1361 else if (regset->type != GENERAL_REGS)
1362 regset->size = 0;
1570b33e 1363 }
1570b33e
L		 1364 }
1365
3aee8918 1366 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
a196ebeb
WT		 1367 xcr0_features = (have_ptrace_getregset
1368 && (xcr0 & I386_XSTATE_ALL_MASK));
3aee8918 1369
a196ebeb 1370 if (xcr0_features)
3aee8918 1371 x86_xcr0 = xcr0;
1570b33e 1372
3aee8918
PA		 1373 if (machine == EM_X86_64)
1374 {
1570b33e 1375#ifdef __x86_64__
a196ebeb 1376 if (is_elf64)
3aee8918 1377 {
a196ebeb
WT		 1378 if (xcr0_features)
1379 {
1380 switch (xcr0 & I386_XSTATE_ALL_MASK)
1381 {
01f9f808
MS		 1382 case I386_XSTATE_AVX512_MASK:
1383 return tdesc_amd64_avx512_linux;
1384
a196ebeb
WT		 1385 case I386_XSTATE_MPX_MASK:
1386 return tdesc_amd64_mpx_linux;
1387
1388 case I386_XSTATE_AVX_MASK:
1389 return tdesc_amd64_avx_linux;
1390
1391 default:
1392 return tdesc_amd64_linux;
1393 }
1394 }
4d47af5c 1395 else
a196ebeb 1396 return tdesc_amd64_linux;
3aee8918
PA		 1397 }
1398 else
1399 {
a196ebeb
WT		 1400 if (xcr0_features)
1401 {
1402 switch (xcr0 & I386_XSTATE_ALL_MASK)
1403 {
01f9f808
MS		 1404 case I386_XSTATE_AVX512_MASK:
1405 return tdesc_x32_avx512_linux;
1406
a196ebeb
WT		 1407 case I386_XSTATE_MPX_MASK: /* No MPX on x32. */
1408 case I386_XSTATE_AVX_MASK:
1409 return tdesc_x32_avx_linux;
1410
1411 default:
1412 return tdesc_x32_linux;
1413 }
1414 }
3aee8918 1415 else
a196ebeb 1416 return tdesc_x32_linux;
1570b33e 1417 }
3aee8918 1418#endif
1570b33e 1419 }
3aee8918
PA		 1420 else
1421 {
a196ebeb
WT		 1422 if (xcr0_features)
1423 {
1424 switch (xcr0 & I386_XSTATE_ALL_MASK)
1425 {
01f9f808
MS		 1426 case (I386_XSTATE_AVX512_MASK):
1427 return tdesc_i386_avx512_linux;
1428
a196ebeb
WT		 1429 case (I386_XSTATE_MPX_MASK):
1430 return tdesc_i386_mpx_linux;
1431
1432 case (I386_XSTATE_AVX_MASK):
1433 return tdesc_i386_avx_linux;
1434
1435 default:
1436 return tdesc_i386_linux;
1437 }
1438 }
3aee8918
PA		 1439 else
1440 return tdesc_i386_linux;
1441 }
1442
1443 gdb_assert_not_reached ("failed to return tdesc");
1444}
1445
1446/* Callback for find_inferior. Stops iteration when a thread with a
1447 given PID is found. */
1448
1449static int
1450same_process_callback (struct inferior_list_entry *entry, void *data)
1451{
1452 int pid = *(int *) data;
1453
1454 return (ptid_get_pid (entry->id) == pid);
1455}
1456
1457/* Callback for for_each_inferior. Calls the arch_setup routine for
1458 each process. */
1459
1460static void
1461x86_arch_setup_process_callback (struct inferior_list_entry *entry)
1462{
1463 int pid = ptid_get_pid (entry->id);
1464
1465 /* Look up any thread of this processes. */
1466 current_inferior
1467 = (struct thread_info *) find_inferior (&all_threads,
1468 same_process_callback, &pid);
1469
1470 the_low_target.arch_setup ();
1471}
1472
1473/* Update all the target description of all processes; a new GDB
1474 connected, and it may or not support xml target descriptions. */
1475
1476static void
1477x86_linux_update_xmltarget (void)
1478{
1479 struct thread_info *save_inferior = current_inferior;
1480
1481 /* Before changing the register cache's internal layout, flush the
1482 contents of the current valid caches back to the threads, and
1483 release the current regcache objects. */
1484 regcache_release ();
1485
1486 for_each_inferior (&all_processes, x86_arch_setup_process_callback);
1487
1488 current_inferior = save_inferior;
1570b33e
L		 1489}
1490
1491/* Process qSupported query, "xmlRegisters=". Update the buffer size for
1492 PTRACE_GETREGSET. */
1493
1494static void
1495x86_linux_process_qsupported (const char *query)
1496{
1497 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
1498 with "i386" in qSupported query, it supports x86 XML target
1499 descriptions. */
1500 use_xml = 0;
1501 if (query != NULL && strncmp (query, "xmlRegisters=", 13) == 0)
1502 {
1503 char *copy = xstrdup (query + 13);
1504 char *p;
1505
1506 for (p = strtok (copy, ","); p != NULL; p = strtok (NULL, ","))
1507 {
1508 if (strcmp (p, "i386") == 0)
1509 {
1510 use_xml = 1;
1511 break;
1512 }
1513 }
1514
1515 free (copy);
1516 }
1517
1518 x86_linux_update_xmltarget ();
1519}
1520
3aee8918 1521/* Common for x86/x86-64. */
d0722149 1522
3aee8918
PA		 1523static struct regsets_info x86_regsets_info =
1524 {
1525 x86_regsets, /* regsets */
1526 0, /* num_regsets */
1527 NULL, /* disabled_regsets */
1528 };
214d508e
L		 1529
1530#ifdef __x86_64__
3aee8918
PA		 1531static struct regs_info amd64_linux_regs_info =
1532 {
1533 NULL, /* regset_bitmap */
1534 NULL, /* usrregs_info */
1535 &x86_regsets_info
1536 };
d0722149 1537#endif
3aee8918
PA		 1538static struct usrregs_info i386_linux_usrregs_info =
1539 {
1540 I386_NUM_REGS,
1541 i386_regmap,
1542 };
d0722149 1543
3aee8918
PA		 1544static struct regs_info i386_linux_regs_info =
1545 {
1546 NULL, /* regset_bitmap */
1547 &i386_linux_usrregs_info,
1548 &x86_regsets_info
1549 };
d0722149 1550
3aee8918
PA		 1551const struct regs_info *
1552x86_linux_regs_info (void)
1553{
1554#ifdef __x86_64__
1555 if (is_64bit_tdesc ())
1556 return &amd64_linux_regs_info;
1557 else
1558#endif
1559 return &i386_linux_regs_info;
1560}
d0722149 1561
3aee8918
PA		 1562/* Initialize the target description for the architecture of the
1563 inferior. */
1570b33e 1564
3aee8918
PA		 1565static void
1566x86_arch_setup (void)
1567{
1568 current_process ()->tdesc = x86_linux_read_description ();
d0722149
DE		 1569}
1570
219f2f23
PA		 1571static int
1572x86_supports_tracepoints (void)
1573{
1574 return 1;
1575}
1576
fa593d66
PA		 1577static void
1578append_insns (CORE_ADDR *to, size_t len, const unsigned char *buf)
1579{
1580 write_inferior_memory (*to, buf, len);
1581 *to += len;
1582}
1583
1584static int
1585push_opcode (unsigned char *buf, char *op)
1586{
1587 unsigned char *buf_org = buf;
1588
1589 while (1)
1590 {
1591 char *endptr;
1592 unsigned long ul = strtoul (op, &endptr, 16);
1593
1594 if (endptr == op)
1595 break;
1596
1597 *buf++ = ul;
1598 op = endptr;
1599 }
1600
1601 return buf - buf_org;
1602}
1603
1604#ifdef __x86_64__
1605
1606/* Build a jump pad that saves registers and calls a collection
1607 function. Writes a jump instruction to the jump pad to
1608 JJUMPAD_INSN. The caller is responsible to write it in at the
1609 tracepoint address. */
1610
1611static int
1612amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1613 CORE_ADDR collector,
1614 CORE_ADDR lockaddr,
1615 ULONGEST orig_size,
1616 CORE_ADDR *jump_entry,
405f8e94
SS		 1617 CORE_ADDR *trampoline,
1618 ULONGEST *trampoline_size,
fa593d66
PA		 1619 unsigned char *jjump_pad_insn,
1620 ULONGEST *jjump_pad_insn_size,
1621 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1622 CORE_ADDR *adjusted_insn_addr_end,
1623 char *err)
fa593d66
PA		 1624{
1625 unsigned char buf[40];
1626 int i, offset;
f4647387
YQ		 1627 int64_t loffset;
1628
fa593d66
PA		 1629 CORE_ADDR buildaddr = *jump_entry;
1630
1631 /* Build the jump pad. */
1632
1633 /* First, do tracepoint data collection. Save registers. */
1634 i = 0;
1635 /* Need to ensure stack pointer saved first. */
1636 buf[i++] = 0x54; /* push %rsp */
1637 buf[i++] = 0x55; /* push %rbp */
1638 buf[i++] = 0x57; /* push %rdi */
1639 buf[i++] = 0x56; /* push %rsi */
1640 buf[i++] = 0x52; /* push %rdx */
1641 buf[i++] = 0x51; /* push %rcx */
1642 buf[i++] = 0x53; /* push %rbx */
1643 buf[i++] = 0x50; /* push %rax */
1644 buf[i++] = 0x41; buf[i++] = 0x57; /* push %r15 */
1645 buf[i++] = 0x41; buf[i++] = 0x56; /* push %r14 */
1646 buf[i++] = 0x41; buf[i++] = 0x55; /* push %r13 */
1647 buf[i++] = 0x41; buf[i++] = 0x54; /* push %r12 */
1648 buf[i++] = 0x41; buf[i++] = 0x53; /* push %r11 */
1649 buf[i++] = 0x41; buf[i++] = 0x52; /* push %r10 */
1650 buf[i++] = 0x41; buf[i++] = 0x51; /* push %r9 */
1651 buf[i++] = 0x41; buf[i++] = 0x50; /* push %r8 */
1652 buf[i++] = 0x9c; /* pushfq */
1653 buf[i++] = 0x48; /* movl <addr>,%rdi */
1654 buf[i++] = 0xbf;
1655 *((unsigned long *)(buf + i)) = (unsigned long) tpaddr;
1656 i += sizeof (unsigned long);
1657 buf[i++] = 0x57; /* push %rdi */
1658 append_insns (&buildaddr, i, buf);
1659
1660 /* Stack space for the collecting_t object. */
1661 i = 0;
1662 i += push_opcode (&buf[i], "48 83 ec 18"); /* sub $0x18,%rsp */
1663 i += push_opcode (&buf[i], "48 b8"); /* mov <tpoint>,%rax */
1664 memcpy (buf + i, &tpoint, 8);
1665 i += 8;
1666 i += push_opcode (&buf[i], "48 89 04 24"); /* mov %rax,(%rsp) */
1667 i += push_opcode (&buf[i],
1668 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1669 i += push_opcode (&buf[i], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1670 append_insns (&buildaddr, i, buf);
1671
1672 /* spin-lock. */
1673 i = 0;
1674 i += push_opcode (&buf[i], "48 be"); /* movl <lockaddr>,%rsi */
1675 memcpy (&buf[i], (void *) &lockaddr, 8);
1676 i += 8;
1677 i += push_opcode (&buf[i], "48 89 e1"); /* mov %rsp,%rcx */
1678 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1679 i += push_opcode (&buf[i], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1680 i += push_opcode (&buf[i], "48 85 c0"); /* test %rax,%rax */
1681 i += push_opcode (&buf[i], "75 f4"); /* jne <again> */
1682 append_insns (&buildaddr, i, buf);
1683
1684 /* Set up the gdb_collect call. */
1685 /* At this point, (stack pointer + 0x18) is the base of our saved
1686 register block. */
1687
1688 i = 0;
1689 i += push_opcode (&buf[i], "48 89 e6"); /* mov %rsp,%rsi */
1690 i += push_opcode (&buf[i], "48 83 c6 18"); /* add $0x18,%rsi */
1691
1692 /* tpoint address may be 64-bit wide. */
1693 i += push_opcode (&buf[i], "48 bf"); /* movl <addr>,%rdi */
1694 memcpy (buf + i, &tpoint, 8);
1695 i += 8;
1696 append_insns (&buildaddr, i, buf);
1697
1698 /* The collector function being in the shared library, may be
1699 >31-bits away off the jump pad. */
1700 i = 0;
1701 i += push_opcode (&buf[i], "48 b8"); /* mov $collector,%rax */
1702 memcpy (buf + i, &collector, 8);
1703 i += 8;
1704 i += push_opcode (&buf[i], "ff d0"); /* callq *%rax */
1705 append_insns (&buildaddr, i, buf);
1706
1707 /* Clear the spin-lock. */
1708 i = 0;
1709 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1710 i += push_opcode (&buf[i], "48 a3"); /* mov %rax, lockaddr */
1711 memcpy (buf + i, &lockaddr, 8);
1712 i += 8;
1713 append_insns (&buildaddr, i, buf);
1714
1715 /* Remove stack that had been used for the collect_t object. */
1716 i = 0;
1717 i += push_opcode (&buf[i], "48 83 c4 18"); /* add $0x18,%rsp */
1718 append_insns (&buildaddr, i, buf);
1719
1720 /* Restore register state. */
1721 i = 0;
1722 buf[i++] = 0x48; /* add $0x8,%rsp */
1723 buf[i++] = 0x83;
1724 buf[i++] = 0xc4;
1725 buf[i++] = 0x08;
1726 buf[i++] = 0x9d; /* popfq */
1727 buf[i++] = 0x41; buf[i++] = 0x58; /* pop %r8 */
1728 buf[i++] = 0x41; buf[i++] = 0x59; /* pop %r9 */
1729 buf[i++] = 0x41; buf[i++] = 0x5a; /* pop %r10 */
1730 buf[i++] = 0x41; buf[i++] = 0x5b; /* pop %r11 */
1731 buf[i++] = 0x41; buf[i++] = 0x5c; /* pop %r12 */
1732 buf[i++] = 0x41; buf[i++] = 0x5d; /* pop %r13 */
1733 buf[i++] = 0x41; buf[i++] = 0x5e; /* pop %r14 */
1734 buf[i++] = 0x41; buf[i++] = 0x5f; /* pop %r15 */
1735 buf[i++] = 0x58; /* pop %rax */
1736 buf[i++] = 0x5b; /* pop %rbx */
1737 buf[i++] = 0x59; /* pop %rcx */
1738 buf[i++] = 0x5a; /* pop %rdx */
1739 buf[i++] = 0x5e; /* pop %rsi */
1740 buf[i++] = 0x5f; /* pop %rdi */
1741 buf[i++] = 0x5d; /* pop %rbp */
1742 buf[i++] = 0x5c; /* pop %rsp */
1743 append_insns (&buildaddr, i, buf);
1744
1745 /* Now, adjust the original instruction to execute in the jump
1746 pad. */
1747 *adjusted_insn_addr = buildaddr;
1748 relocate_instruction (&buildaddr, tpaddr);
1749 *adjusted_insn_addr_end = buildaddr;
1750
1751 /* Finally, write a jump back to the program. */
f4647387
YQ		 1752
1753 loffset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn));
1754 if (loffset > INT_MAX || loffset < INT_MIN)
1755 {
1756 sprintf (err,
1757 "E.Jump back from jump pad too far from tracepoint "
1758 "(offset 0x%" PRIx64 " > int32).", loffset);
1759 return 1;
1760 }
1761
1762 offset = (int) loffset;
fa593d66
PA		 1763 memcpy (buf, jump_insn, sizeof (jump_insn));
1764 memcpy (buf + 1, &offset, 4);
1765 append_insns (&buildaddr, sizeof (jump_insn), buf);
1766
1767 /* The jump pad is now built. Wire in a jump to our jump pad. This
1768 is always done last (by our caller actually), so that we can
1769 install fast tracepoints with threads running. This relies on
1770 the agent's atomic write support. */
f4647387
YQ		 1771 loffset = *jump_entry - (tpaddr + sizeof (jump_insn));
1772 if (loffset > INT_MAX || loffset < INT_MIN)
1773 {
1774 sprintf (err,
1775 "E.Jump pad too far from tracepoint "
1776 "(offset 0x%" PRIx64 " > int32).", loffset);
1777 return 1;
1778 }
1779
1780 offset = (int) loffset;
1781
fa593d66
PA		 1782 memcpy (buf, jump_insn, sizeof (jump_insn));
1783 memcpy (buf + 1, &offset, 4);
1784 memcpy (jjump_pad_insn, buf, sizeof (jump_insn));
1785 *jjump_pad_insn_size = sizeof (jump_insn);
1786
1787 /* Return the end address of our pad. */
1788 *jump_entry = buildaddr;
1789
1790 return 0;
1791}
1792
1793#endif /* __x86_64__ */
1794
1795/* Build a jump pad that saves registers and calls a collection
1796 function. Writes a jump instruction to the jump pad to
1797 JJUMPAD_INSN. The caller is responsible to write it in at the
1798 tracepoint address. */
1799
1800static int
1801i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1802 CORE_ADDR collector,
1803 CORE_ADDR lockaddr,
1804 ULONGEST orig_size,
1805 CORE_ADDR *jump_entry,
405f8e94
SS		 1806 CORE_ADDR *trampoline,
1807 ULONGEST *trampoline_size,
fa593d66
PA		 1808 unsigned char *jjump_pad_insn,
1809 ULONGEST *jjump_pad_insn_size,
1810 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1811 CORE_ADDR *adjusted_insn_addr_end,
1812 char *err)
fa593d66
PA		 1813{
1814 unsigned char buf[0x100];
1815 int i, offset;
1816 CORE_ADDR buildaddr = *jump_entry;
1817
1818 /* Build the jump pad. */
1819
1820 /* First, do tracepoint data collection. Save registers. */
1821 i = 0;
1822 buf[i++] = 0x60; /* pushad */
1823 buf[i++] = 0x68; /* push tpaddr aka $pc */
1824 *((int *)(buf + i)) = (int) tpaddr;
1825 i += 4;
1826 buf[i++] = 0x9c; /* pushf */
1827 buf[i++] = 0x1e; /* push %ds */
1828 buf[i++] = 0x06; /* push %es */
1829 buf[i++] = 0x0f; /* push %fs */
1830 buf[i++] = 0xa0;
1831 buf[i++] = 0x0f; /* push %gs */
1832 buf[i++] = 0xa8;
1833 buf[i++] = 0x16; /* push %ss */
1834 buf[i++] = 0x0e; /* push %cs */
1835 append_insns (&buildaddr, i, buf);
1836
1837 /* Stack space for the collecting_t object. */
1838 i = 0;
1839 i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */
1840
1841 /* Build the object. */
1842 i += push_opcode (&buf[i], "b8"); /* mov <tpoint>,%eax */
1843 memcpy (buf + i, &tpoint, 4);
1844 i += 4;
1845 i += push_opcode (&buf[i], "89 04 24"); /* mov %eax,(%esp) */
1846
1847 i += push_opcode (&buf[i], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1848 i += push_opcode (&buf[i], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1849 append_insns (&buildaddr, i, buf);
1850
1851 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1852 If we cared for it, this could be using xchg alternatively. */
1853
1854 i = 0;
1855 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1856 i += push_opcode (&buf[i], "f0 0f b1 25"); /* lock cmpxchg
1857 %esp,<lockaddr> */
1858 memcpy (&buf[i], (void *) &lockaddr, 4);
1859 i += 4;
1860 i += push_opcode (&buf[i], "85 c0"); /* test %eax,%eax */
1861 i += push_opcode (&buf[i], "75 f2"); /* jne <again> */
1862 append_insns (&buildaddr, i, buf);
1863
1864
1865 /* Set up arguments to the gdb_collect call. */
1866 i = 0;
1867 i += push_opcode (&buf[i], "89 e0"); /* mov %esp,%eax */
1868 i += push_opcode (&buf[i], "83 c0 08"); /* add $0x08,%eax */
1869 i += push_opcode (&buf[i], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1870 append_insns (&buildaddr, i, buf);
1871
1872 i = 0;
1873 i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */
1874 append_insns (&buildaddr, i, buf);
1875
1876 i = 0;
1877 i += push_opcode (&buf[i], "c7 04 24"); /* movl <addr>,(%esp) */
1878 memcpy (&buf[i], (void *) &tpoint, 4);
1879 i += 4;
1880 append_insns (&buildaddr, i, buf);
1881
1882 buf[0] = 0xe8; /* call <reladdr> */
1883 offset = collector - (buildaddr + sizeof (jump_insn));
1884 memcpy (buf + 1, &offset, 4);
1885 append_insns (&buildaddr, 5, buf);
1886 /* Clean up after the call. */
1887 buf[0] = 0x83; /* add $0x8,%esp */
1888 buf[1] = 0xc4;
1889 buf[2] = 0x08;
1890 append_insns (&buildaddr, 3, buf);
1891
1892
1893 /* Clear the spin-lock. This would need the LOCK prefix on older
1894 broken archs. */
1895 i = 0;
1896 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1897 i += push_opcode (&buf[i], "a3"); /* mov %eax, lockaddr */
1898 memcpy (buf + i, &lockaddr, 4);
1899 i += 4;
1900 append_insns (&buildaddr, i, buf);
1901
1902
1903 /* Remove stack that had been used for the collect_t object. */
1904 i = 0;
1905 i += push_opcode (&buf[i], "83 c4 08"); /* add $0x08,%esp */
1906 append_insns (&buildaddr, i, buf);
1907
1908 i = 0;
1909 buf[i++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1910 buf[i++] = 0xc4;
1911 buf[i++] = 0x04;
1912 buf[i++] = 0x17; /* pop %ss */
1913 buf[i++] = 0x0f; /* pop %gs */
1914 buf[i++] = 0xa9;
1915 buf[i++] = 0x0f; /* pop %fs */
1916 buf[i++] = 0xa1;
1917 buf[i++] = 0x07; /* pop %es */
405f8e94 1918 buf[i++] = 0x1f; /* pop %ds */
fa593d66
PA		 1919 buf[i++] = 0x9d; /* popf */
1920 buf[i++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1921 buf[i++] = 0xc4;
1922 buf[i++] = 0x04;
1923 buf[i++] = 0x61; /* popad */
1924 append_insns (&buildaddr, i, buf);
1925
1926 /* Now, adjust the original instruction to execute in the jump
1927 pad. */
1928 *adjusted_insn_addr = buildaddr;
1929 relocate_instruction (&buildaddr, tpaddr);
1930 *adjusted_insn_addr_end = buildaddr;
1931
1932 /* Write the jump back to the program. */
1933 offset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn));
1934 memcpy (buf, jump_insn, sizeof (jump_insn));
1935 memcpy (buf + 1, &offset, 4);
1936 append_insns (&buildaddr, sizeof (jump_insn), buf);
1937
1938 /* The jump pad is now built. Wire in a jump to our jump pad. This
1939 is always done last (by our caller actually), so that we can
1940 install fast tracepoints with threads running. This relies on
1941 the agent's atomic write support. */
405f8e94
SS		 1942 if (orig_size == 4)
1943 {
1944 /* Create a trampoline. */
1945 *trampoline_size = sizeof (jump_insn);
1946 if (!claim_trampoline_space (*trampoline_size, trampoline))
1947 {
1948 /* No trampoline space available. */
1949 strcpy (err,
1950 "E.Cannot allocate trampoline space needed for fast "
1951 "tracepoints on 4-byte instructions.");
1952 return 1;
1953 }
1954
1955 offset = *jump_entry - (*trampoline + sizeof (jump_insn));
1956 memcpy (buf, jump_insn, sizeof (jump_insn));
1957 memcpy (buf + 1, &offset, 4);
1958 write_inferior_memory (*trampoline, buf, sizeof (jump_insn));
1959
1960 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1961 offset = (*trampoline - (tpaddr + sizeof (small_jump_insn))) & 0xffff;
1962 memcpy (buf, small_jump_insn, sizeof (small_jump_insn));
1963 memcpy (buf + 2, &offset, 2);
1964 memcpy (jjump_pad_insn, buf, sizeof (small_jump_insn));
1965 *jjump_pad_insn_size = sizeof (small_jump_insn);
1966 }
1967 else
1968 {
1969 /* Else use a 32-bit relative jump instruction. */
1970 offset = *jump_entry - (tpaddr + sizeof (jump_insn));
1971 memcpy (buf, jump_insn, sizeof (jump_insn));
1972 memcpy (buf + 1, &offset, 4);
1973 memcpy (jjump_pad_insn, buf, sizeof (jump_insn));
1974 *jjump_pad_insn_size = sizeof (jump_insn);
1975 }
fa593d66
PA		 1976
1977 /* Return the end address of our pad. */
1978 *jump_entry = buildaddr;
1979
1980 return 0;
1981}
1982
1983static int
1984x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1985 CORE_ADDR collector,
1986 CORE_ADDR lockaddr,
1987 ULONGEST orig_size,
1988 CORE_ADDR *jump_entry,
405f8e94
SS		 1989 CORE_ADDR *trampoline,
1990 ULONGEST *trampoline_size,
fa593d66
PA		 1991 unsigned char *jjump_pad_insn,
1992 ULONGEST *jjump_pad_insn_size,
1993 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1994 CORE_ADDR *adjusted_insn_addr_end,
1995 char *err)
fa593d66
PA		 1996{
1997#ifdef __x86_64__
3aee8918 1998 if (is_64bit_tdesc ())
fa593d66
PA		 1999 return amd64_install_fast_tracepoint_jump_pad (tpoint, tpaddr,
2000 collector, lockaddr,
2001 orig_size, jump_entry,
405f8e94 2002 trampoline, trampoline_size,
fa593d66
PA		 2003 jjump_pad_insn,
2004 jjump_pad_insn_size,
2005 adjusted_insn_addr,
405f8e94
SS		 2006 adjusted_insn_addr_end,
2007 err);
fa593d66
PA		 2008#endif
2009
2010 return i386_install_fast_tracepoint_jump_pad (tpoint, tpaddr,
2011 collector, lockaddr,
2012 orig_size, jump_entry,
405f8e94 2013 trampoline, trampoline_size,
fa593d66
PA		 2014 jjump_pad_insn,
2015 jjump_pad_insn_size,
2016 adjusted_insn_addr,
405f8e94
SS		 2017 adjusted_insn_addr_end,
2018 err);
2019}
2020
2021/* Return the minimum instruction length for fast tracepoints on x86/x86-64
2022 architectures. */
2023
2024static int
2025x86_get_min_fast_tracepoint_insn_len (void)
2026{
2027 static int warned_about_fast_tracepoints = 0;
2028
2029#ifdef __x86_64__
2030 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
2031 used for fast tracepoints. */
3aee8918 2032 if (is_64bit_tdesc ())
405f8e94
SS		 2033 return 5;
2034#endif
2035
58b4daa5 2036 if (agent_loaded_p ())
405f8e94
SS		 2037 {
2038 char errbuf[IPA_BUFSIZ];
2039
2040 errbuf[0] = '\0';
2041
2042 /* On x86, if trampolines are available, then 4-byte jump instructions
2043 with a 2-byte offset may be used, otherwise 5-byte jump instructions
2044 with a 4-byte offset are used instead. */
2045 if (have_fast_tracepoint_trampoline_buffer (errbuf))
2046 return 4;
2047 else
2048 {
2049 /* GDB has no channel to explain to user why a shorter fast
2050 tracepoint is not possible, but at least make GDBserver
2051 mention that something has gone awry. */
2052 if (!warned_about_fast_tracepoints)
2053 {
2054 warning ("4-byte fast tracepoints not available; %s\n", errbuf);
2055 warned_about_fast_tracepoints = 1;
2056 }
2057 return 5;
2058 }
2059 }
2060 else
2061 {
2062 /* Indicate that the minimum length is currently unknown since the IPA
2063 has not loaded yet. */
2064 return 0;
2065 }
fa593d66
PA		 2066}
2067
6a271cae
PA		 2068static void
2069add_insns (unsigned char *start, int len)
2070{
2071 CORE_ADDR buildaddr = current_insn_ptr;
2072
2073 if (debug_threads)
87ce2a04
DE		 2074 debug_printf ("Adding %d bytes of insn at %s\n",
2075 len, paddress (buildaddr));
6a271cae
PA		 2076
2077 append_insns (&buildaddr, len, start);
2078 current_insn_ptr = buildaddr;
2079}
2080
6a271cae
PA		 2081/* Our general strategy for emitting code is to avoid specifying raw
2082 bytes whenever possible, and instead copy a block of inline asm
2083 that is embedded in the function. This is a little messy, because
2084 we need to keep the compiler from discarding what looks like dead
2085 code, plus suppress various warnings. */
2086
9e4344e5
PA		 2087#define EMIT_ASM(NAME, INSNS) \
2088 do \
2089 { \
2090 extern unsigned char start_ ## NAME, end_ ## NAME; \
2091 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
493e2a69 2092 __asm__ ("jmp end_" #NAME "\n" \
9e4344e5
PA		 2093 "\t" "start_" #NAME ":" \
2094 "\t" INSNS "\n" \
2095 "\t" "end_" #NAME ":"); \
2096 } while (0)
6a271cae
PA		 2097
2098#ifdef __x86_64__
2099
2100#define EMIT_ASM32(NAME,INSNS) \
9e4344e5
PA		 2101 do \
2102 { \
2103 extern unsigned char start_ ## NAME, end_ ## NAME; \
2104 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
2105 __asm__ (".code32\n" \
2106 "\t" "jmp end_" #NAME "\n" \
2107 "\t" "start_" #NAME ":\n" \
2108 "\t" INSNS "\n" \
2109 "\t" "end_" #NAME ":\n" \
2110 ".code64\n"); \
2111 } while (0)
6a271cae
PA		 2112
2113#else
2114
2115#define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
2116
2117#endif
2118
2119#ifdef __x86_64__
2120
2121static void
2122amd64_emit_prologue (void)
2123{
2124 EMIT_ASM (amd64_prologue,
2125 "pushq %rbp\n\t"
2126 "movq %rsp,%rbp\n\t"
2127 "sub $0x20,%rsp\n\t"
2128 "movq %rdi,-8(%rbp)\n\t"
2129 "movq %rsi,-16(%rbp)");
2130}
2131
2132
2133static void
2134amd64_emit_epilogue (void)
2135{
2136 EMIT_ASM (amd64_epilogue,
2137 "movq -16(%rbp),%rdi\n\t"
2138 "movq %rax,(%rdi)\n\t"
2139 "xor %rax,%rax\n\t"
2140 "leave\n\t"
2141 "ret");
2142}
2143
2144static void
2145amd64_emit_add (void)
2146{
2147 EMIT_ASM (amd64_add,
2148 "add (%rsp),%rax\n\t"
2149 "lea 0x8(%rsp),%rsp");
2150}
2151
2152static void
2153amd64_emit_sub (void)
2154{
2155 EMIT_ASM (amd64_sub,
2156 "sub %rax,(%rsp)\n\t"
2157 "pop %rax");
2158}
2159
2160static void
2161amd64_emit_mul (void)
2162{
2163 emit_error = 1;
2164}
2165
2166static void
2167amd64_emit_lsh (void)
2168{
2169 emit_error = 1;
2170}
2171
2172static void
2173amd64_emit_rsh_signed (void)
2174{
2175 emit_error = 1;
2176}
2177
2178static void
2179amd64_emit_rsh_unsigned (void)
2180{
2181 emit_error = 1;
2182}
2183
2184static void
2185amd64_emit_ext (int arg)
2186{
2187 switch (arg)
2188 {
2189 case 8:
2190 EMIT_ASM (amd64_ext_8,
2191 "cbtw\n\t"
2192 "cwtl\n\t"
2193 "cltq");
2194 break;
2195 case 16:
2196 EMIT_ASM (amd64_ext_16,
2197 "cwtl\n\t"
2198 "cltq");
2199 break;
2200 case 32:
2201 EMIT_ASM (amd64_ext_32,
2202 "cltq");
2203 break;
2204 default:
2205 emit_error = 1;
2206 }
2207}
2208
2209static void
2210amd64_emit_log_not (void)
2211{
2212 EMIT_ASM (amd64_log_not,
2213 "test %rax,%rax\n\t"
2214 "sete %cl\n\t"
2215 "movzbq %cl,%rax");
2216}
2217
2218static void
2219amd64_emit_bit_and (void)
2220{
2221 EMIT_ASM (amd64_and,
2222 "and (%rsp),%rax\n\t"
2223 "lea 0x8(%rsp),%rsp");
2224}
2225
2226static void
2227amd64_emit_bit_or (void)
2228{
2229 EMIT_ASM (amd64_or,
2230 "or (%rsp),%rax\n\t"
2231 "lea 0x8(%rsp),%rsp");
2232}
2233
2234static void
2235amd64_emit_bit_xor (void)
2236{
2237 EMIT_ASM (amd64_xor,
2238 "xor (%rsp),%rax\n\t"
2239 "lea 0x8(%rsp),%rsp");
2240}
2241
2242static void
2243amd64_emit_bit_not (void)
2244{
2245 EMIT_ASM (amd64_bit_not,
2246 "xorq $0xffffffffffffffff,%rax");
2247}
2248
2249static void
2250amd64_emit_equal (void)
2251{
2252 EMIT_ASM (amd64_equal,
2253 "cmp %rax,(%rsp)\n\t"
2254 "je .Lamd64_equal_true\n\t"
2255 "xor %rax,%rax\n\t"
2256 "jmp .Lamd64_equal_end\n\t"
2257 ".Lamd64_equal_true:\n\t"
2258 "mov $0x1,%rax\n\t"
2259 ".Lamd64_equal_end:\n\t"
2260 "lea 0x8(%rsp),%rsp");
2261}
2262
2263static void
2264amd64_emit_less_signed (void)
2265{
2266 EMIT_ASM (amd64_less_signed,
2267 "cmp %rax,(%rsp)\n\t"
2268 "jl .Lamd64_less_signed_true\n\t"
2269 "xor %rax,%rax\n\t"
2270 "jmp .Lamd64_less_signed_end\n\t"
2271 ".Lamd64_less_signed_true:\n\t"
2272 "mov $1,%rax\n\t"
2273 ".Lamd64_less_signed_end:\n\t"
2274 "lea 0x8(%rsp),%rsp");
2275}
2276
2277static void
2278amd64_emit_less_unsigned (void)
2279{
2280 EMIT_ASM (amd64_less_unsigned,
2281 "cmp %rax,(%rsp)\n\t"
2282 "jb .Lamd64_less_unsigned_true\n\t"
2283 "xor %rax,%rax\n\t"
2284 "jmp .Lamd64_less_unsigned_end\n\t"
2285 ".Lamd64_less_unsigned_true:\n\t"
2286 "mov $1,%rax\n\t"
2287 ".Lamd64_less_unsigned_end:\n\t"
2288 "lea 0x8(%rsp),%rsp");
2289}
2290
2291static void
2292amd64_emit_ref (int size)
2293{
2294 switch (size)
2295 {
2296 case 1:
2297 EMIT_ASM (amd64_ref1,
2298 "movb (%rax),%al");
2299 break;
2300 case 2:
2301 EMIT_ASM (amd64_ref2,
2302 "movw (%rax),%ax");
2303 break;
2304 case 4:
2305 EMIT_ASM (amd64_ref4,
2306 "movl (%rax),%eax");
2307 break;
2308 case 8:
2309 EMIT_ASM (amd64_ref8,
2310 "movq (%rax),%rax");
2311 break;
2312 }
2313}
2314
2315static void
2316amd64_emit_if_goto (int *offset_p, int *size_p)
2317{
2318 EMIT_ASM (amd64_if_goto,
2319 "mov %rax,%rcx\n\t"
2320 "pop %rax\n\t"
2321 "cmp $0,%rcx\n\t"
2322 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2323 if (offset_p)
2324 *offset_p = 10;
2325 if (size_p)
2326 *size_p = 4;
2327}
2328
2329static void
2330amd64_emit_goto (int *offset_p, int *size_p)
2331{
2332 EMIT_ASM (amd64_goto,
2333 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2334 if (offset_p)
2335 *offset_p = 1;
2336 if (size_p)
2337 *size_p = 4;
2338}
2339
2340static void
2341amd64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2342{
2343 int diff = (to - (from + size));
2344 unsigned char buf[sizeof (int)];
2345
2346 if (size != 4)
2347 {
2348 emit_error = 1;
2349 return;
2350 }
2351
2352 memcpy (buf, &diff, sizeof (int));
2353 write_inferior_memory (from, buf, sizeof (int));
2354}
2355
2356static void
4e29fb54 2357amd64_emit_const (LONGEST num)
6a271cae
PA		 2358{
2359 unsigned char buf[16];
2360 int i;
2361 CORE_ADDR buildaddr = current_insn_ptr;
2362
2363 i = 0;
2364 buf[i++] = 0x48; buf[i++] = 0xb8; /* mov $<n>,%rax */
b00ad6ff 2365 memcpy (&buf[i], &num, sizeof (num));
6a271cae
PA		 2366 i += 8;
2367 append_insns (&buildaddr, i, buf);
2368 current_insn_ptr = buildaddr;
2369}
2370
2371static void
2372amd64_emit_call (CORE_ADDR fn)
2373{
2374 unsigned char buf[16];
2375 int i;
2376 CORE_ADDR buildaddr;
4e29fb54 2377 LONGEST offset64;
6a271cae
PA		 2378
2379 /* The destination function being in the shared library, may be
2380 >31-bits away off the compiled code pad. */
2381
2382 buildaddr = current_insn_ptr;
2383
2384 offset64 = fn - (buildaddr + 1 /* call op */ + 4 /* 32-bit offset */);
2385
2386 i = 0;
2387
2388 if (offset64 > INT_MAX || offset64 < INT_MIN)
2389 {
2390 /* Offset is too large for a call. Use callq, but that requires
2391 a register, so avoid it if possible. Use r10, since it is
2392 call-clobbered, we don't have to push/pop it. */
2393 buf[i++] = 0x48; /* mov $fn,%r10 */
2394 buf[i++] = 0xba;
2395 memcpy (buf + i, &fn, 8);
2396 i += 8;
2397 buf[i++] = 0xff; /* callq *%r10 */
2398 buf[i++] = 0xd2;
2399 }
2400 else
2401 {
2402 int offset32 = offset64; /* we know we can't overflow here. */
2403 memcpy (buf + i, &offset32, 4);
2404 i += 4;
2405 }
2406
2407 append_insns (&buildaddr, i, buf);
2408 current_insn_ptr = buildaddr;
2409}
2410
2411static void
2412amd64_emit_reg (int reg)
2413{
2414 unsigned char buf[16];
2415 int i;
2416 CORE_ADDR buildaddr;
2417
2418 /* Assume raw_regs is still in %rdi. */
2419 buildaddr = current_insn_ptr;
2420 i = 0;
2421 buf[i++] = 0xbe; /* mov $<n>,%esi */
b00ad6ff 2422 memcpy (&buf[i], &reg, sizeof (reg));
6a271cae
PA		 2423 i += 4;
2424 append_insns (&buildaddr, i, buf);
2425 current_insn_ptr = buildaddr;
2426 amd64_emit_call (get_raw_reg_func_addr ());
2427}
2428
2429static void
2430amd64_emit_pop (void)
2431{
2432 EMIT_ASM (amd64_pop,
2433 "pop %rax");
2434}
2435
2436static void
2437amd64_emit_stack_flush (void)
2438{
2439 EMIT_ASM (amd64_stack_flush,
2440 "push %rax");
2441}
2442
2443static void
2444amd64_emit_zero_ext (int arg)
2445{
2446 switch (arg)
2447 {
2448 case 8:
2449 EMIT_ASM (amd64_zero_ext_8,
2450 "and $0xff,%rax");
2451 break;
2452 case 16:
2453 EMIT_ASM (amd64_zero_ext_16,
2454 "and $0xffff,%rax");
2455 break;
2456 case 32:
2457 EMIT_ASM (amd64_zero_ext_32,
2458 "mov $0xffffffff,%rcx\n\t"
2459 "and %rcx,%rax");
2460 break;
2461 default:
2462 emit_error = 1;
2463 }
2464}
2465
2466static void
2467amd64_emit_swap (void)
2468{
2469 EMIT_ASM (amd64_swap,
2470 "mov %rax,%rcx\n\t"
2471 "pop %rax\n\t"
2472 "push %rcx");
2473}
2474
2475static void
2476amd64_emit_stack_adjust (int n)
2477{
2478 unsigned char buf[16];
2479 int i;
2480 CORE_ADDR buildaddr = current_insn_ptr;
2481
2482 i = 0;
2483 buf[i++] = 0x48; /* lea $<n>(%rsp),%rsp */
2484 buf[i++] = 0x8d;
2485 buf[i++] = 0x64;
2486 buf[i++] = 0x24;
2487 /* This only handles adjustments up to 16, but we don't expect any more. */
2488 buf[i++] = n * 8;
2489 append_insns (&buildaddr, i, buf);
2490 current_insn_ptr = buildaddr;
2491}
2492
2493/* FN's prototype is `LONGEST(*fn)(int)'. */
2494
2495static void
2496amd64_emit_int_call_1 (CORE_ADDR fn, int arg1)
2497{
2498 unsigned char buf[16];
2499 int i;
2500 CORE_ADDR buildaddr;
2501
2502 buildaddr = current_insn_ptr;
2503 i = 0;
2504 buf[i++] = 0xbf; /* movl $<n>,%edi */
b00ad6ff 2505 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 2506 i += 4;
2507 append_insns (&buildaddr, i, buf);
2508 current_insn_ptr = buildaddr;
2509 amd64_emit_call (fn);
2510}
2511
4e29fb54 2512/* FN's prototype is `void(*fn)(int,LONGEST)'. */
6a271cae
PA		 2513
2514static void
2515amd64_emit_void_call_2 (CORE_ADDR fn, int arg1)
2516{
2517 unsigned char buf[16];
2518 int i;
2519 CORE_ADDR buildaddr;
2520
2521 buildaddr = current_insn_ptr;
2522 i = 0;
2523 buf[i++] = 0xbf; /* movl $<n>,%edi */
b00ad6ff 2524 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 2525 i += 4;
2526 append_insns (&buildaddr, i, buf);
2527 current_insn_ptr = buildaddr;
2528 EMIT_ASM (amd64_void_call_2_a,
2529 /* Save away a copy of the stack top. */
2530 "push %rax\n\t"
2531 /* Also pass top as the second argument. */
2532 "mov %rax,%rsi");
2533 amd64_emit_call (fn);
2534 EMIT_ASM (amd64_void_call_2_b,
2535 /* Restore the stack top, %rax may have been trashed. */
2536 "pop %rax");
2537}
2538
6b9801d4
SS		 2539void
2540amd64_emit_eq_goto (int *offset_p, int *size_p)
2541{
2542 EMIT_ASM (amd64_eq,
2543 "cmp %rax,(%rsp)\n\t"
2544 "jne .Lamd64_eq_fallthru\n\t"
2545 "lea 0x8(%rsp),%rsp\n\t"
2546 "pop %rax\n\t"
2547 /* jmp, but don't trust the assembler to choose the right jump */
2548 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2549 ".Lamd64_eq_fallthru:\n\t"
2550 "lea 0x8(%rsp),%rsp\n\t"
2551 "pop %rax");
2552
2553 if (offset_p)
2554 *offset_p = 13;
2555 if (size_p)
2556 *size_p = 4;
2557}
2558
2559void
2560amd64_emit_ne_goto (int *offset_p, int *size_p)
2561{
2562 EMIT_ASM (amd64_ne,
2563 "cmp %rax,(%rsp)\n\t"
2564 "je .Lamd64_ne_fallthru\n\t"
2565 "lea 0x8(%rsp),%rsp\n\t"
2566 "pop %rax\n\t"
2567 /* jmp, but don't trust the assembler to choose the right jump */
2568 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2569 ".Lamd64_ne_fallthru:\n\t"
2570 "lea 0x8(%rsp),%rsp\n\t"
2571 "pop %rax");
2572
2573 if (offset_p)
2574 *offset_p = 13;
2575 if (size_p)
2576 *size_p = 4;
2577}
2578
2579void
2580amd64_emit_lt_goto (int *offset_p, int *size_p)
2581{
2582 EMIT_ASM (amd64_lt,
2583 "cmp %rax,(%rsp)\n\t"
2584 "jnl .Lamd64_lt_fallthru\n\t"
2585 "lea 0x8(%rsp),%rsp\n\t"
2586 "pop %rax\n\t"
2587 /* jmp, but don't trust the assembler to choose the right jump */
2588 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2589 ".Lamd64_lt_fallthru:\n\t"
2590 "lea 0x8(%rsp),%rsp\n\t"
2591 "pop %rax");
2592
2593 if (offset_p)
2594 *offset_p = 13;
2595 if (size_p)
2596 *size_p = 4;
2597}
2598
2599void
2600amd64_emit_le_goto (int *offset_p, int *size_p)
2601{
2602 EMIT_ASM (amd64_le,
2603 "cmp %rax,(%rsp)\n\t"
2604 "jnle .Lamd64_le_fallthru\n\t"
2605 "lea 0x8(%rsp),%rsp\n\t"
2606 "pop %rax\n\t"
2607 /* jmp, but don't trust the assembler to choose the right jump */
2608 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2609 ".Lamd64_le_fallthru:\n\t"
2610 "lea 0x8(%rsp),%rsp\n\t"
2611 "pop %rax");
2612
2613 if (offset_p)
2614 *offset_p = 13;
2615 if (size_p)
2616 *size_p = 4;
2617}
2618
2619void
2620amd64_emit_gt_goto (int *offset_p, int *size_p)
2621{
2622 EMIT_ASM (amd64_gt,
2623 "cmp %rax,(%rsp)\n\t"
2624 "jng .Lamd64_gt_fallthru\n\t"
2625 "lea 0x8(%rsp),%rsp\n\t"
2626 "pop %rax\n\t"
2627 /* jmp, but don't trust the assembler to choose the right jump */
2628 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2629 ".Lamd64_gt_fallthru:\n\t"
2630 "lea 0x8(%rsp),%rsp\n\t"
2631 "pop %rax");
2632
2633 if (offset_p)
2634 *offset_p = 13;
2635 if (size_p)
2636 *size_p = 4;
2637}
2638
2639void
2640amd64_emit_ge_goto (int *offset_p, int *size_p)
2641{
2642 EMIT_ASM (amd64_ge,
2643 "cmp %rax,(%rsp)\n\t"
2644 "jnge .Lamd64_ge_fallthru\n\t"
2645 ".Lamd64_ge_jump:\n\t"
2646 "lea 0x8(%rsp),%rsp\n\t"
2647 "pop %rax\n\t"
2648 /* jmp, but don't trust the assembler to choose the right jump */
2649 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2650 ".Lamd64_ge_fallthru:\n\t"
2651 "lea 0x8(%rsp),%rsp\n\t"
2652 "pop %rax");
2653
2654 if (offset_p)
2655 *offset_p = 13;
2656 if (size_p)
2657 *size_p = 4;
2658}
2659
6a271cae
PA		 2660struct emit_ops amd64_emit_ops =
2661 {
2662 amd64_emit_prologue,
2663 amd64_emit_epilogue,
2664 amd64_emit_add,
2665 amd64_emit_sub,
2666 amd64_emit_mul,
2667 amd64_emit_lsh,
2668 amd64_emit_rsh_signed,
2669 amd64_emit_rsh_unsigned,
2670 amd64_emit_ext,
2671 amd64_emit_log_not,
2672 amd64_emit_bit_and,
2673 amd64_emit_bit_or,
2674 amd64_emit_bit_xor,
2675 amd64_emit_bit_not,
2676 amd64_emit_equal,
2677 amd64_emit_less_signed,
2678 amd64_emit_less_unsigned,
2679 amd64_emit_ref,
2680 amd64_emit_if_goto,
2681 amd64_emit_goto,
2682 amd64_write_goto_address,
2683 amd64_emit_const,
2684 amd64_emit_call,
2685 amd64_emit_reg,
2686 amd64_emit_pop,
2687 amd64_emit_stack_flush,
2688 amd64_emit_zero_ext,
2689 amd64_emit_swap,
2690 amd64_emit_stack_adjust,
2691 amd64_emit_int_call_1,
6b9801d4
SS		 2692 amd64_emit_void_call_2,
2693 amd64_emit_eq_goto,
2694 amd64_emit_ne_goto,
2695 amd64_emit_lt_goto,
2696 amd64_emit_le_goto,
2697 amd64_emit_gt_goto,
2698 amd64_emit_ge_goto
6a271cae
PA		 2699 };
2700
2701#endif /* __x86_64__ */
2702
2703static void
2704i386_emit_prologue (void)
2705{
2706 EMIT_ASM32 (i386_prologue,
2707 "push %ebp\n\t"
bf15cbda
SS		 2708 "mov %esp,%ebp\n\t"
2709 "push %ebx");
6a271cae
PA		 2710 /* At this point, the raw regs base address is at 8(%ebp), and the
2711 value pointer is at 12(%ebp). */
2712}
2713
2714static void
2715i386_emit_epilogue (void)
2716{
2717 EMIT_ASM32 (i386_epilogue,
2718 "mov 12(%ebp),%ecx\n\t"
2719 "mov %eax,(%ecx)\n\t"
2720 "mov %ebx,0x4(%ecx)\n\t"
2721 "xor %eax,%eax\n\t"
bf15cbda 2722 "pop %ebx\n\t"
6a271cae
PA		 2723 "pop %ebp\n\t"
2724 "ret");
2725}
2726
2727static void
2728i386_emit_add (void)
2729{
2730 EMIT_ASM32 (i386_add,
2731 "add (%esp),%eax\n\t"
2732 "adc 0x4(%esp),%ebx\n\t"
2733 "lea 0x8(%esp),%esp");
2734}
2735
2736static void
2737i386_emit_sub (void)
2738{
2739 EMIT_ASM32 (i386_sub,
2740 "subl %eax,(%esp)\n\t"
2741 "sbbl %ebx,4(%esp)\n\t"
2742 "pop %eax\n\t"
2743 "pop %ebx\n\t");
2744}
2745
2746static void
2747i386_emit_mul (void)
2748{
2749 emit_error = 1;
2750}
2751
2752static void
2753i386_emit_lsh (void)
2754{
2755 emit_error = 1;
2756}
2757
2758static void
2759i386_emit_rsh_signed (void)
2760{
2761 emit_error = 1;
2762}
2763
2764static void
2765i386_emit_rsh_unsigned (void)
2766{
2767 emit_error = 1;
2768}
2769
2770static void
2771i386_emit_ext (int arg)
2772{
2773 switch (arg)
2774 {
2775 case 8:
2776 EMIT_ASM32 (i386_ext_8,
2777 "cbtw\n\t"
2778 "cwtl\n\t"
2779 "movl %eax,%ebx\n\t"
2780 "sarl $31,%ebx");
2781 break;
2782 case 16:
2783 EMIT_ASM32 (i386_ext_16,
2784 "cwtl\n\t"
2785 "movl %eax,%ebx\n\t"
2786 "sarl $31,%ebx");
2787 break;
2788 case 32:
2789 EMIT_ASM32 (i386_ext_32,
2790 "movl %eax,%ebx\n\t"
2791 "sarl $31,%ebx");
2792 break;
2793 default:
2794 emit_error = 1;
2795 }
2796}
2797
2798static void
2799i386_emit_log_not (void)
2800{
2801 EMIT_ASM32 (i386_log_not,
2802 "or %ebx,%eax\n\t"
2803 "test %eax,%eax\n\t"
2804 "sete %cl\n\t"
2805 "xor %ebx,%ebx\n\t"
2806 "movzbl %cl,%eax");
2807}
2808
2809static void
2810i386_emit_bit_and (void)
2811{
2812 EMIT_ASM32 (i386_and,
2813 "and (%esp),%eax\n\t"
2814 "and 0x4(%esp),%ebx\n\t"
2815 "lea 0x8(%esp),%esp");
2816}
2817
2818static void
2819i386_emit_bit_or (void)
2820{
2821 EMIT_ASM32 (i386_or,
2822 "or (%esp),%eax\n\t"
2823 "or 0x4(%esp),%ebx\n\t"
2824 "lea 0x8(%esp),%esp");
2825}
2826
2827static void
2828i386_emit_bit_xor (void)
2829{
2830 EMIT_ASM32 (i386_xor,
2831 "xor (%esp),%eax\n\t"
2832 "xor 0x4(%esp),%ebx\n\t"
2833 "lea 0x8(%esp),%esp");
2834}
2835
2836static void
2837i386_emit_bit_not (void)
2838{
2839 EMIT_ASM32 (i386_bit_not,
2840 "xor $0xffffffff,%eax\n\t"
2841 "xor $0xffffffff,%ebx\n\t");
2842}
2843
2844static void
2845i386_emit_equal (void)
2846{
2847 EMIT_ASM32 (i386_equal,
2848 "cmpl %ebx,4(%esp)\n\t"
2849 "jne .Li386_equal_false\n\t"
2850 "cmpl %eax,(%esp)\n\t"
2851 "je .Li386_equal_true\n\t"
2852 ".Li386_equal_false:\n\t"
2853 "xor %eax,%eax\n\t"
2854 "jmp .Li386_equal_end\n\t"
2855 ".Li386_equal_true:\n\t"
2856 "mov $1,%eax\n\t"
2857 ".Li386_equal_end:\n\t"
2858 "xor %ebx,%ebx\n\t"
2859 "lea 0x8(%esp),%esp");
2860}
2861
2862static void
2863i386_emit_less_signed (void)
2864{
2865 EMIT_ASM32 (i386_less_signed,
2866 "cmpl %ebx,4(%esp)\n\t"
2867 "jl .Li386_less_signed_true\n\t"
2868 "jne .Li386_less_signed_false\n\t"
2869 "cmpl %eax,(%esp)\n\t"
2870 "jl .Li386_less_signed_true\n\t"
2871 ".Li386_less_signed_false:\n\t"
2872 "xor %eax,%eax\n\t"
2873 "jmp .Li386_less_signed_end\n\t"
2874 ".Li386_less_signed_true:\n\t"
2875 "mov $1,%eax\n\t"
2876 ".Li386_less_signed_end:\n\t"
2877 "xor %ebx,%ebx\n\t"
2878 "lea 0x8(%esp),%esp");
2879}
2880
2881static void
2882i386_emit_less_unsigned (void)
2883{
2884 EMIT_ASM32 (i386_less_unsigned,
2885 "cmpl %ebx,4(%esp)\n\t"
2886 "jb .Li386_less_unsigned_true\n\t"
2887 "jne .Li386_less_unsigned_false\n\t"
2888 "cmpl %eax,(%esp)\n\t"
2889 "jb .Li386_less_unsigned_true\n\t"
2890 ".Li386_less_unsigned_false:\n\t"
2891 "xor %eax,%eax\n\t"
2892 "jmp .Li386_less_unsigned_end\n\t"
2893 ".Li386_less_unsigned_true:\n\t"
2894 "mov $1,%eax\n\t"
2895 ".Li386_less_unsigned_end:\n\t"
2896 "xor %ebx,%ebx\n\t"
2897 "lea 0x8(%esp),%esp");
2898}
2899
2900static void
2901i386_emit_ref (int size)
2902{
2903 switch (size)
2904 {
2905 case 1:
2906 EMIT_ASM32 (i386_ref1,
2907 "movb (%eax),%al");
2908 break;
2909 case 2:
2910 EMIT_ASM32 (i386_ref2,
2911 "movw (%eax),%ax");
2912 break;
2913 case 4:
2914 EMIT_ASM32 (i386_ref4,
2915 "movl (%eax),%eax");
2916 break;
2917 case 8:
2918 EMIT_ASM32 (i386_ref8,
2919 "movl 4(%eax),%ebx\n\t"
2920 "movl (%eax),%eax");
2921 break;
2922 }
2923}
2924
2925static void
2926i386_emit_if_goto (int *offset_p, int *size_p)
2927{
2928 EMIT_ASM32 (i386_if_goto,
2929 "mov %eax,%ecx\n\t"
2930 "or %ebx,%ecx\n\t"
2931 "pop %eax\n\t"
2932 "pop %ebx\n\t"
2933 "cmpl $0,%ecx\n\t"
2934 /* Don't trust the assembler to choose the right jump */
2935 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2936
2937 if (offset_p)
2938 *offset_p = 11; /* be sure that this matches the sequence above */
2939 if (size_p)
2940 *size_p = 4;
2941}
2942
2943static void
2944i386_emit_goto (int *offset_p, int *size_p)
2945{
2946 EMIT_ASM32 (i386_goto,
2947 /* Don't trust the assembler to choose the right jump */
2948 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2949 if (offset_p)
2950 *offset_p = 1;
2951 if (size_p)
2952 *size_p = 4;
2953}
2954
2955static void
2956i386_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2957{
2958 int diff = (to - (from + size));
2959 unsigned char buf[sizeof (int)];
2960
2961 /* We're only doing 4-byte sizes at the moment. */
2962 if (size != 4)
2963 {
2964 emit_error = 1;
2965 return;
2966 }
2967
2968 memcpy (buf, &diff, sizeof (int));
2969 write_inferior_memory (from, buf, sizeof (int));
2970}
2971
2972static void
4e29fb54 2973i386_emit_const (LONGEST num)
6a271cae
PA		 2974{
2975 unsigned char buf[16];
b00ad6ff 2976 int i, hi, lo;
6a271cae
PA		 2977 CORE_ADDR buildaddr = current_insn_ptr;
2978
2979 i = 0;
2980 buf[i++] = 0xb8; /* mov $<n>,%eax */
b00ad6ff
NF		 2981 lo = num & 0xffffffff;
2982 memcpy (&buf[i], &lo, sizeof (lo));
6a271cae
PA		 2983 i += 4;
2984 hi = ((num >> 32) & 0xffffffff);
2985 if (hi)
2986 {
2987 buf[i++] = 0xbb; /* mov $<n>,%ebx */
b00ad6ff 2988 memcpy (&buf[i], &hi, sizeof (hi));
6a271cae
PA		 2989 i += 4;
2990 }
2991 else
2992 {
2993 buf[i++] = 0x31; buf[i++] = 0xdb; /* xor %ebx,%ebx */
2994 }
2995 append_insns (&buildaddr, i, buf);
2996 current_insn_ptr = buildaddr;
2997}
2998
2999static void
3000i386_emit_call (CORE_ADDR fn)
3001{
3002 unsigned char buf[16];
3003 int i, offset;
3004 CORE_ADDR buildaddr;
3005
3006 buildaddr = current_insn_ptr;
3007 i = 0;
3008 buf[i++] = 0xe8; /* call <reladdr> */
3009 offset = ((int) fn) - (buildaddr + 5);
3010 memcpy (buf + 1, &offset, 4);
3011 append_insns (&buildaddr, 5, buf);
3012 current_insn_ptr = buildaddr;
3013}
3014
3015static void
3016i386_emit_reg (int reg)
3017{
3018 unsigned char buf[16];
3019 int i;
3020 CORE_ADDR buildaddr;
3021
3022 EMIT_ASM32 (i386_reg_a,
3023 "sub $0x8,%esp");
3024 buildaddr = current_insn_ptr;
3025 i = 0;
3026 buf[i++] = 0xb8; /* mov $<n>,%eax */
b00ad6ff 3027 memcpy (&buf[i], &reg, sizeof (reg));
6a271cae
PA		 3028 i += 4;
3029 append_insns (&buildaddr, i, buf);
3030 current_insn_ptr = buildaddr;
3031 EMIT_ASM32 (i386_reg_b,
3032 "mov %eax,4(%esp)\n\t"
3033 "mov 8(%ebp),%eax\n\t"
3034 "mov %eax,(%esp)");
3035 i386_emit_call (get_raw_reg_func_addr ());
3036 EMIT_ASM32 (i386_reg_c,
3037 "xor %ebx,%ebx\n\t"
3038 "lea 0x8(%esp),%esp");
3039}
3040
3041static void
3042i386_emit_pop (void)
3043{
3044 EMIT_ASM32 (i386_pop,
3045 "pop %eax\n\t"
3046 "pop %ebx");
3047}
3048
3049static void
3050i386_emit_stack_flush (void)
3051{
3052 EMIT_ASM32 (i386_stack_flush,
3053 "push %ebx\n\t"
3054 "push %eax");
3055}
3056
3057static void
3058i386_emit_zero_ext (int arg)
3059{
3060 switch (arg)
3061 {
3062 case 8:
3063 EMIT_ASM32 (i386_zero_ext_8,
3064 "and $0xff,%eax\n\t"
3065 "xor %ebx,%ebx");
3066 break;
3067 case 16:
3068 EMIT_ASM32 (i386_zero_ext_16,
3069 "and $0xffff,%eax\n\t"
3070 "xor %ebx,%ebx");
3071 break;
3072 case 32:
3073 EMIT_ASM32 (i386_zero_ext_32,
3074 "xor %ebx,%ebx");
3075 break;
3076 default:
3077 emit_error = 1;
3078 }
3079}
3080
3081static void
3082i386_emit_swap (void)
3083{
3084 EMIT_ASM32 (i386_swap,
3085 "mov %eax,%ecx\n\t"
3086 "mov %ebx,%edx\n\t"
3087 "pop %eax\n\t"
3088 "pop %ebx\n\t"
3089 "push %edx\n\t"
3090 "push %ecx");
3091}
3092
3093static void
3094i386_emit_stack_adjust (int n)
3095{
3096 unsigned char buf[16];
3097 int i;
3098 CORE_ADDR buildaddr = current_insn_ptr;
3099
3100 i = 0;
3101 buf[i++] = 0x8d; /* lea $<n>(%esp),%esp */
3102 buf[i++] = 0x64;
3103 buf[i++] = 0x24;
3104 buf[i++] = n * 8;
3105 append_insns (&buildaddr, i, buf);
3106 current_insn_ptr = buildaddr;
3107}
3108
3109/* FN's prototype is `LONGEST(*fn)(int)'. */
3110
3111static void
3112i386_emit_int_call_1 (CORE_ADDR fn, int arg1)
3113{
3114 unsigned char buf[16];
3115 int i;
3116 CORE_ADDR buildaddr;
3117
3118 EMIT_ASM32 (i386_int_call_1_a,
3119 /* Reserve a bit of stack space. */
3120 "sub $0x8,%esp");
3121 /* Put the one argument on the stack. */
3122 buildaddr = current_insn_ptr;
3123 i = 0;
3124 buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */
3125 buf[i++] = 0x04;
3126 buf[i++] = 0x24;
b00ad6ff 3127 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 3128 i += 4;
3129 append_insns (&buildaddr, i, buf);
3130 current_insn_ptr = buildaddr;
3131 i386_emit_call (fn);
3132 EMIT_ASM32 (i386_int_call_1_c,
3133 "mov %edx,%ebx\n\t"
3134 "lea 0x8(%esp),%esp");
3135}
3136
4e29fb54 3137/* FN's prototype is `void(*fn)(int,LONGEST)'. */
6a271cae
PA		 3138
3139static void
3140i386_emit_void_call_2 (CORE_ADDR fn, int arg1)
3141{
3142 unsigned char buf[16];
3143 int i;
3144 CORE_ADDR buildaddr;
3145
3146 EMIT_ASM32 (i386_void_call_2_a,
3147 /* Preserve %eax only; we don't have to worry about %ebx. */
3148 "push %eax\n\t"
3149 /* Reserve a bit of stack space for arguments. */
3150 "sub $0x10,%esp\n\t"
3151 /* Copy "top" to the second argument position. (Note that
3152 we can't assume function won't scribble on its
3153 arguments, so don't try to restore from this.) */
3154 "mov %eax,4(%esp)\n\t"
3155 "mov %ebx,8(%esp)");
3156 /* Put the first argument on the stack. */
3157 buildaddr = current_insn_ptr;
3158 i = 0;
3159 buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */
3160 buf[i++] = 0x04;
3161 buf[i++] = 0x24;
b00ad6ff 3162 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 3163 i += 4;
3164 append_insns (&buildaddr, i, buf);
3165 current_insn_ptr = buildaddr;
3166 i386_emit_call (fn);
3167 EMIT_ASM32 (i386_void_call_2_b,
3168 "lea 0x10(%esp),%esp\n\t"
3169 /* Restore original stack top. */
3170 "pop %eax");
3171}
3172
6b9801d4
SS		 3173
3174void
3175i386_emit_eq_goto (int *offset_p, int *size_p)
3176{
3177 EMIT_ASM32 (eq,
3178 /* Check low half first, more likely to be decider */
3179 "cmpl %eax,(%esp)\n\t"
3180 "jne .Leq_fallthru\n\t"
3181 "cmpl %ebx,4(%esp)\n\t"
3182 "jne .Leq_fallthru\n\t"
3183 "lea 0x8(%esp),%esp\n\t"
3184 "pop %eax\n\t"
3185 "pop %ebx\n\t"
3186 /* jmp, but don't trust the assembler to choose the right jump */
3187 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3188 ".Leq_fallthru:\n\t"
3189 "lea 0x8(%esp),%esp\n\t"
3190 "pop %eax\n\t"
3191 "pop %ebx");
3192
3193 if (offset_p)
3194 *offset_p = 18;
3195 if (size_p)
3196 *size_p = 4;
3197}
3198
3199void
3200i386_emit_ne_goto (int *offset_p, int *size_p)
3201{
3202 EMIT_ASM32 (ne,
3203 /* Check low half first, more likely to be decider */
3204 "cmpl %eax,(%esp)\n\t"
3205 "jne .Lne_jump\n\t"
3206 "cmpl %ebx,4(%esp)\n\t"
3207 "je .Lne_fallthru\n\t"
3208 ".Lne_jump:\n\t"
3209 "lea 0x8(%esp),%esp\n\t"
3210 "pop %eax\n\t"
3211 "pop %ebx\n\t"
3212 /* jmp, but don't trust the assembler to choose the right jump */
3213 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3214 ".Lne_fallthru:\n\t"
3215 "lea 0x8(%esp),%esp\n\t"
3216 "pop %eax\n\t"
3217 "pop %ebx");
3218
3219 if (offset_p)
3220 *offset_p = 18;
3221 if (size_p)
3222 *size_p = 4;
3223}
3224
3225void
3226i386_emit_lt_goto (int *offset_p, int *size_p)
3227{
3228 EMIT_ASM32 (lt,
3229 "cmpl %ebx,4(%esp)\n\t"
3230 "jl .Llt_jump\n\t"
3231 "jne .Llt_fallthru\n\t"
3232 "cmpl %eax,(%esp)\n\t"
3233 "jnl .Llt_fallthru\n\t"
3234 ".Llt_jump:\n\t"
3235 "lea 0x8(%esp),%esp\n\t"
3236 "pop %eax\n\t"
3237 "pop %ebx\n\t"
3238 /* jmp, but don't trust the assembler to choose the right jump */
3239 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3240 ".Llt_fallthru:\n\t"
3241 "lea 0x8(%esp),%esp\n\t"
3242 "pop %eax\n\t"
3243 "pop %ebx");
3244
3245 if (offset_p)
3246 *offset_p = 20;
3247 if (size_p)
3248 *size_p = 4;
3249}
3250
3251void
3252i386_emit_le_goto (int *offset_p, int *size_p)
3253{
3254 EMIT_ASM32 (le,
3255 "cmpl %ebx,4(%esp)\n\t"
3256 "jle .Lle_jump\n\t"
3257 "jne .Lle_fallthru\n\t"
3258 "cmpl %eax,(%esp)\n\t"
3259 "jnle .Lle_fallthru\n\t"
3260 ".Lle_jump:\n\t"
3261 "lea 0x8(%esp),%esp\n\t"
3262 "pop %eax\n\t"
3263 "pop %ebx\n\t"
3264 /* jmp, but don't trust the assembler to choose the right jump */
3265 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3266 ".Lle_fallthru:\n\t"
3267 "lea 0x8(%esp),%esp\n\t"
3268 "pop %eax\n\t"
3269 "pop %ebx");
3270
3271 if (offset_p)
3272 *offset_p = 20;
3273 if (size_p)
3274 *size_p = 4;
3275}
3276
3277void
3278i386_emit_gt_goto (int *offset_p, int *size_p)
3279{
3280 EMIT_ASM32 (gt,
3281 "cmpl %ebx,4(%esp)\n\t"
3282 "jg .Lgt_jump\n\t"
3283 "jne .Lgt_fallthru\n\t"
3284 "cmpl %eax,(%esp)\n\t"
3285 "jng .Lgt_fallthru\n\t"
3286 ".Lgt_jump:\n\t"
3287 "lea 0x8(%esp),%esp\n\t"
3288 "pop %eax\n\t"
3289 "pop %ebx\n\t"
3290 /* jmp, but don't trust the assembler to choose the right jump */
3291 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3292 ".Lgt_fallthru:\n\t"
3293 "lea 0x8(%esp),%esp\n\t"
3294 "pop %eax\n\t"
3295 "pop %ebx");
3296
3297 if (offset_p)
3298 *offset_p = 20;
3299 if (size_p)
3300 *size_p = 4;
3301}
3302
3303void
3304i386_emit_ge_goto (int *offset_p, int *size_p)
3305{
3306 EMIT_ASM32 (ge,
3307 "cmpl %ebx,4(%esp)\n\t"
3308 "jge .Lge_jump\n\t"
3309 "jne .Lge_fallthru\n\t"
3310 "cmpl %eax,(%esp)\n\t"
3311 "jnge .Lge_fallthru\n\t"
3312 ".Lge_jump:\n\t"
3313 "lea 0x8(%esp),%esp\n\t"
3314 "pop %eax\n\t"
3315 "pop %ebx\n\t"
3316 /* jmp, but don't trust the assembler to choose the right jump */
3317 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3318 ".Lge_fallthru:\n\t"
3319 "lea 0x8(%esp),%esp\n\t"
3320 "pop %eax\n\t"
3321 "pop %ebx");
3322
3323 if (offset_p)
3324 *offset_p = 20;
3325 if (size_p)
3326 *size_p = 4;
3327}
3328
6a271cae
PA		 3329struct emit_ops i386_emit_ops =
3330 {
3331 i386_emit_prologue,
3332 i386_emit_epilogue,
3333 i386_emit_add,
3334 i386_emit_sub,
3335 i386_emit_mul,
3336 i386_emit_lsh,
3337 i386_emit_rsh_signed,
3338 i386_emit_rsh_unsigned,
3339 i386_emit_ext,
3340 i386_emit_log_not,
3341 i386_emit_bit_and,
3342 i386_emit_bit_or,
3343 i386_emit_bit_xor,
3344 i386_emit_bit_not,
3345 i386_emit_equal,
3346 i386_emit_less_signed,
3347 i386_emit_less_unsigned,
3348 i386_emit_ref,
3349 i386_emit_if_goto,
3350 i386_emit_goto,
3351 i386_write_goto_address,
3352 i386_emit_const,
3353 i386_emit_call,
3354 i386_emit_reg,
3355 i386_emit_pop,
3356 i386_emit_stack_flush,
3357 i386_emit_zero_ext,
3358 i386_emit_swap,
3359 i386_emit_stack_adjust,
3360 i386_emit_int_call_1,
6b9801d4
SS		 3361 i386_emit_void_call_2,
3362 i386_emit_eq_goto,
3363 i386_emit_ne_goto,
3364 i386_emit_lt_goto,
3365 i386_emit_le_goto,
3366 i386_emit_gt_goto,
3367 i386_emit_ge_goto
6a271cae
PA		 3368 };
3369
3370
3371static struct emit_ops *
3372x86_emit_ops (void)
3373{
3374#ifdef __x86_64__
3aee8918 3375 if (is_64bit_tdesc ())
6a271cae
PA		 3376 return &amd64_emit_ops;
3377 else
3378#endif
3379 return &i386_emit_ops;
3380}
3381
c2d6af84
PA		 3382static int
3383x86_supports_range_stepping (void)
3384{
3385 return 1;
3386}
3387
d0722149
DE		 3388/* This is initialized assuming an amd64 target.
3389 x86_arch_setup will correct it for i386 or amd64 targets. */
3390
3391struct linux_target_ops the_low_target =
3392{
3393 x86_arch_setup,
3aee8918
PA		 3394 x86_linux_regs_info,
3395 x86_cannot_fetch_register,
3396 x86_cannot_store_register,
c14dfd32 3397 NULL, /* fetch_register */
d0722149
DE		 3398 x86_get_pc,
3399 x86_set_pc,
3400 x86_breakpoint,
3401 x86_breakpoint_len,
3402 NULL,
3403 1,
3404 x86_breakpoint_at,
aa5ca48f
DE		 3405 x86_insert_point,
3406 x86_remove_point,
3407 x86_stopped_by_watchpoint,
3408 x86_stopped_data_address,
d0722149
DE		 3409 /* collect_ptrace_register/supply_ptrace_register are not needed in the
3410 native i386 case (no registers smaller than an xfer unit), and are not
3411 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
3412 NULL,
3413 NULL,
3414 /* need to fix up i386 siginfo if host is amd64 */
3415 x86_siginfo_fixup,
aa5ca48f
DE		 3416 x86_linux_new_process,
3417 x86_linux_new_thread,
1570b33e 3418 x86_linux_prepare_to_resume,
219f2f23 3419 x86_linux_process_qsupported,
fa593d66
PA		 3420 x86_supports_tracepoints,
3421 x86_get_thread_area,
6a271cae 3422 x86_install_fast_tracepoint_jump_pad,
405f8e94
SS		 3423 x86_emit_ops,
3424 x86_get_min_fast_tracepoint_insn_len,
c2d6af84 3425 x86_supports_range_stepping,
d0722149 3426};
3aee8918
PA		 3427
3428void
3429initialize_low_arch (void)
3430{
3431 /* Initialize the Linux target descriptions. */
3432#ifdef __x86_64__
3433 init_registers_amd64_linux ();
3434 init_registers_amd64_avx_linux ();
01f9f808 3435 init_registers_amd64_avx512_linux ();
a196ebeb
WT		 3436 init_registers_amd64_mpx_linux ();
3437
3aee8918 3438 init_registers_x32_linux ();
7e5aaa09 3439 init_registers_x32_avx_linux ();
01f9f808 3440 init_registers_x32_avx512_linux ();
3aee8918
PA		 3441
3442 tdesc_amd64_linux_no_xml = xmalloc (sizeof (struct target_desc));
3443 copy_target_description (tdesc_amd64_linux_no_xml, tdesc_amd64_linux);
3444 tdesc_amd64_linux_no_xml->xmltarget = xmltarget_amd64_linux_no_xml;
3445#endif
3446 init_registers_i386_linux ();
3447 init_registers_i386_mmx_linux ();
3448 init_registers_i386_avx_linux ();
01f9f808 3449 init_registers_i386_avx512_linux ();
a196ebeb 3450 init_registers_i386_mpx_linux ();
3aee8918
PA		 3451
3452 tdesc_i386_linux_no_xml = xmalloc (sizeof (struct target_desc));
3453 copy_target_description (tdesc_i386_linux_no_xml, tdesc_i386_linux);
3454 tdesc_i386_linux_no_xml->xmltarget = xmltarget_i386_linux_no_xml;
3455
3456 initialize_regsets_info (&x86_regsets_info);
3457}
GDB Binutils - Deliverables
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