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d0722149 DE |
1 | /* GNU/Linux/x86-64 specific low level interface, for the remote server |
2 | for GDB. | |
0b302171 | 3 | Copyright (C) 2002, 2004-2012 Free Software Foundation, Inc. |
d0722149 DE |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
aa5ca48f | 20 | #include <stddef.h> |
d0722149 | 21 | #include <signal.h> |
6a271cae | 22 | #include <limits.h> |
f4647387 | 23 | #include <inttypes.h> |
d0722149 DE |
24 | #include "server.h" |
25 | #include "linux-low.h" | |
26 | #include "i387-fp.h" | |
aa5ca48f | 27 | #include "i386-low.h" |
1570b33e L |
28 | #include "i386-xstate.h" |
29 | #include "elf/common.h" | |
d0722149 DE |
30 | |
31 | #include "gdb_proc_service.h" | |
58b4daa5 | 32 | #include "agent.h" |
d0722149 | 33 | |
90884b2b | 34 | /* Defined in auto-generated file i386-linux.c. */ |
d0722149 | 35 | void init_registers_i386_linux (void); |
90884b2b L |
36 | /* Defined in auto-generated file amd64-linux.c. */ |
37 | void init_registers_amd64_linux (void); | |
1570b33e L |
38 | /* Defined in auto-generated file i386-avx-linux.c. */ |
39 | void init_registers_i386_avx_linux (void); | |
40 | /* Defined in auto-generated file amd64-avx-linux.c. */ | |
41 | void init_registers_amd64_avx_linux (void); | |
3a13a53b L |
42 | /* Defined in auto-generated file i386-mmx-linux.c. */ |
43 | void init_registers_i386_mmx_linux (void); | |
1570b33e | 44 | |
fa593d66 | 45 | static unsigned char jump_insn[] = { 0xe9, 0, 0, 0, 0 }; |
405f8e94 | 46 | static unsigned char small_jump_insn[] = { 0x66, 0xe9, 0, 0 }; |
fa593d66 | 47 | |
1570b33e L |
48 | /* Backward compatibility for gdb without XML support. */ |
49 | ||
50 | static const char *xmltarget_i386_linux_no_xml = "@<target>\ | |
51 | <architecture>i386</architecture>\ | |
52 | <osabi>GNU/Linux</osabi>\ | |
53 | </target>"; | |
f6d1620c L |
54 | |
55 | #ifdef __x86_64__ | |
1570b33e L |
56 | static const char *xmltarget_amd64_linux_no_xml = "@<target>\ |
57 | <architecture>i386:x86-64</architecture>\ | |
58 | <osabi>GNU/Linux</osabi>\ | |
59 | </target>"; | |
f6d1620c | 60 | #endif |
d0722149 DE |
61 | |
62 | #include <sys/reg.h> | |
63 | #include <sys/procfs.h> | |
64 | #include <sys/ptrace.h> | |
1570b33e L |
65 | #include <sys/uio.h> |
66 | ||
67 | #ifndef PTRACE_GETREGSET | |
68 | #define PTRACE_GETREGSET 0x4204 | |
69 | #endif | |
70 | ||
71 | #ifndef PTRACE_SETREGSET | |
72 | #define PTRACE_SETREGSET 0x4205 | |
73 | #endif | |
74 | ||
d0722149 DE |
75 | |
76 | #ifndef PTRACE_GET_THREAD_AREA | |
77 | #define PTRACE_GET_THREAD_AREA 25 | |
78 | #endif | |
79 | ||
80 | /* This definition comes from prctl.h, but some kernels may not have it. */ | |
81 | #ifndef PTRACE_ARCH_PRCTL | |
82 | #define PTRACE_ARCH_PRCTL 30 | |
83 | #endif | |
84 | ||
85 | /* The following definitions come from prctl.h, but may be absent | |
86 | for certain configurations. */ | |
87 | #ifndef ARCH_GET_FS | |
88 | #define ARCH_SET_GS 0x1001 | |
89 | #define ARCH_SET_FS 0x1002 | |
90 | #define ARCH_GET_FS 0x1003 | |
91 | #define ARCH_GET_GS 0x1004 | |
92 | #endif | |
93 | ||
aa5ca48f DE |
94 | /* Per-process arch-specific data we want to keep. */ |
95 | ||
96 | struct arch_process_info | |
97 | { | |
98 | struct i386_debug_reg_state debug_reg_state; | |
99 | }; | |
100 | ||
101 | /* Per-thread arch-specific data we want to keep. */ | |
102 | ||
103 | struct arch_lwp_info | |
104 | { | |
105 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
106 | int debug_registers_changed; | |
107 | }; | |
108 | ||
d0722149 DE |
109 | #ifdef __x86_64__ |
110 | ||
111 | /* Mapping between the general-purpose registers in `struct user' | |
112 | format and GDB's register array layout. | |
113 | Note that the transfer layout uses 64-bit regs. */ | |
114 | static /*const*/ int i386_regmap[] = | |
115 | { | |
116 | RAX * 8, RCX * 8, RDX * 8, RBX * 8, | |
117 | RSP * 8, RBP * 8, RSI * 8, RDI * 8, | |
118 | RIP * 8, EFLAGS * 8, CS * 8, SS * 8, | |
119 | DS * 8, ES * 8, FS * 8, GS * 8 | |
120 | }; | |
121 | ||
122 | #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0])) | |
123 | ||
124 | /* So code below doesn't have to care, i386 or amd64. */ | |
125 | #define ORIG_EAX ORIG_RAX | |
126 | ||
127 | static const int x86_64_regmap[] = | |
128 | { | |
129 | RAX * 8, RBX * 8, RCX * 8, RDX * 8, | |
130 | RSI * 8, RDI * 8, RBP * 8, RSP * 8, | |
131 | R8 * 8, R9 * 8, R10 * 8, R11 * 8, | |
132 | R12 * 8, R13 * 8, R14 * 8, R15 * 8, | |
133 | RIP * 8, EFLAGS * 8, CS * 8, SS * 8, | |
134 | DS * 8, ES * 8, FS * 8, GS * 8, | |
135 | -1, -1, -1, -1, -1, -1, -1, -1, | |
136 | -1, -1, -1, -1, -1, -1, -1, -1, | |
137 | -1, -1, -1, -1, -1, -1, -1, -1, | |
138 | -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
139 | ORIG_RAX * 8 | |
140 | }; | |
141 | ||
142 | #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0])) | |
143 | ||
144 | #else /* ! __x86_64__ */ | |
145 | ||
146 | /* Mapping between the general-purpose registers in `struct user' | |
147 | format and GDB's register array layout. */ | |
148 | static /*const*/ int i386_regmap[] = | |
149 | { | |
150 | EAX * 4, ECX * 4, EDX * 4, EBX * 4, | |
151 | UESP * 4, EBP * 4, ESI * 4, EDI * 4, | |
152 | EIP * 4, EFL * 4, CS * 4, SS * 4, | |
153 | DS * 4, ES * 4, FS * 4, GS * 4 | |
154 | }; | |
155 | ||
156 | #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0])) | |
157 | ||
158 | #endif | |
159 | \f | |
160 | /* Called by libthread_db. */ | |
161 | ||
162 | ps_err_e | |
163 | ps_get_thread_area (const struct ps_prochandle *ph, | |
164 | lwpid_t lwpid, int idx, void **base) | |
165 | { | |
166 | #ifdef __x86_64__ | |
167 | int use_64bit = register_size (0) == 8; | |
168 | ||
169 | if (use_64bit) | |
170 | { | |
171 | switch (idx) | |
172 | { | |
173 | case FS: | |
174 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_FS) == 0) | |
175 | return PS_OK; | |
176 | break; | |
177 | case GS: | |
178 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_GS) == 0) | |
179 | return PS_OK; | |
180 | break; | |
181 | default: | |
182 | return PS_BADADDR; | |
183 | } | |
184 | return PS_ERR; | |
185 | } | |
186 | #endif | |
187 | ||
188 | { | |
189 | unsigned int desc[4]; | |
190 | ||
191 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, | |
192 | (void *) (intptr_t) idx, (unsigned long) &desc) < 0) | |
193 | return PS_ERR; | |
194 | ||
195 | *(int *)base = desc[1]; | |
196 | return PS_OK; | |
197 | } | |
198 | } | |
fa593d66 PA |
199 | |
200 | /* Get the thread area address. This is used to recognize which | |
201 | thread is which when tracing with the in-process agent library. We | |
202 | don't read anything from the address, and treat it as opaque; it's | |
203 | the address itself that we assume is unique per-thread. */ | |
204 | ||
205 | static int | |
206 | x86_get_thread_area (int lwpid, CORE_ADDR *addr) | |
207 | { | |
208 | #ifdef __x86_64__ | |
209 | int use_64bit = register_size (0) == 8; | |
210 | ||
211 | if (use_64bit) | |
212 | { | |
213 | void *base; | |
214 | if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_FS) == 0) | |
215 | { | |
216 | *addr = (CORE_ADDR) (uintptr_t) base; | |
217 | return 0; | |
218 | } | |
219 | ||
220 | return -1; | |
221 | } | |
222 | #endif | |
223 | ||
224 | { | |
225 | struct lwp_info *lwp = find_lwp_pid (pid_to_ptid (lwpid)); | |
226 | struct regcache *regcache = get_thread_regcache (get_lwp_thread (lwp), 1); | |
227 | unsigned int desc[4]; | |
228 | ULONGEST gs = 0; | |
229 | const int reg_thread_area = 3; /* bits to scale down register value. */ | |
230 | int idx; | |
231 | ||
232 | collect_register_by_name (regcache, "gs", &gs); | |
233 | ||
234 | idx = gs >> reg_thread_area; | |
235 | ||
236 | if (ptrace (PTRACE_GET_THREAD_AREA, | |
493e2a69 MS |
237 | lwpid_of (lwp), |
238 | (void *) (long) idx, (unsigned long) &desc) < 0) | |
fa593d66 PA |
239 | return -1; |
240 | ||
241 | *addr = desc[1]; | |
242 | return 0; | |
243 | } | |
244 | } | |
245 | ||
246 | ||
d0722149 DE |
247 | \f |
248 | static int | |
249 | i386_cannot_store_register (int regno) | |
250 | { | |
251 | return regno >= I386_NUM_REGS; | |
252 | } | |
253 | ||
254 | static int | |
255 | i386_cannot_fetch_register (int regno) | |
256 | { | |
257 | return regno >= I386_NUM_REGS; | |
258 | } | |
259 | ||
260 | static void | |
442ea881 | 261 | x86_fill_gregset (struct regcache *regcache, void *buf) |
d0722149 DE |
262 | { |
263 | int i; | |
264 | ||
265 | #ifdef __x86_64__ | |
266 | if (register_size (0) == 8) | |
267 | { | |
268 | for (i = 0; i < X86_64_NUM_REGS; i++) | |
269 | if (x86_64_regmap[i] != -1) | |
442ea881 | 270 | collect_register (regcache, i, ((char *) buf) + x86_64_regmap[i]); |
d0722149 DE |
271 | return; |
272 | } | |
273 | #endif | |
274 | ||
275 | for (i = 0; i < I386_NUM_REGS; i++) | |
442ea881 | 276 | collect_register (regcache, i, ((char *) buf) + i386_regmap[i]); |
d0722149 | 277 | |
442ea881 PA |
278 | collect_register_by_name (regcache, "orig_eax", |
279 | ((char *) buf) + ORIG_EAX * 4); | |
d0722149 DE |
280 | } |
281 | ||
282 | static void | |
442ea881 | 283 | x86_store_gregset (struct regcache *regcache, const void *buf) |
d0722149 DE |
284 | { |
285 | int i; | |
286 | ||
287 | #ifdef __x86_64__ | |
288 | if (register_size (0) == 8) | |
289 | { | |
290 | for (i = 0; i < X86_64_NUM_REGS; i++) | |
291 | if (x86_64_regmap[i] != -1) | |
442ea881 | 292 | supply_register (regcache, i, ((char *) buf) + x86_64_regmap[i]); |
d0722149 DE |
293 | return; |
294 | } | |
295 | #endif | |
296 | ||
297 | for (i = 0; i < I386_NUM_REGS; i++) | |
442ea881 | 298 | supply_register (regcache, i, ((char *) buf) + i386_regmap[i]); |
d0722149 | 299 | |
442ea881 PA |
300 | supply_register_by_name (regcache, "orig_eax", |
301 | ((char *) buf) + ORIG_EAX * 4); | |
d0722149 DE |
302 | } |
303 | ||
304 | static void | |
442ea881 | 305 | x86_fill_fpregset (struct regcache *regcache, void *buf) |
d0722149 DE |
306 | { |
307 | #ifdef __x86_64__ | |
442ea881 | 308 | i387_cache_to_fxsave (regcache, buf); |
d0722149 | 309 | #else |
442ea881 | 310 | i387_cache_to_fsave (regcache, buf); |
d0722149 DE |
311 | #endif |
312 | } | |
313 | ||
314 | static void | |
442ea881 | 315 | x86_store_fpregset (struct regcache *regcache, const void *buf) |
d0722149 DE |
316 | { |
317 | #ifdef __x86_64__ | |
442ea881 | 318 | i387_fxsave_to_cache (regcache, buf); |
d0722149 | 319 | #else |
442ea881 | 320 | i387_fsave_to_cache (regcache, buf); |
d0722149 DE |
321 | #endif |
322 | } | |
323 | ||
324 | #ifndef __x86_64__ | |
325 | ||
326 | static void | |
442ea881 | 327 | x86_fill_fpxregset (struct regcache *regcache, void *buf) |
d0722149 | 328 | { |
442ea881 | 329 | i387_cache_to_fxsave (regcache, buf); |
d0722149 DE |
330 | } |
331 | ||
332 | static void | |
442ea881 | 333 | x86_store_fpxregset (struct regcache *regcache, const void *buf) |
d0722149 | 334 | { |
442ea881 | 335 | i387_fxsave_to_cache (regcache, buf); |
d0722149 DE |
336 | } |
337 | ||
338 | #endif | |
339 | ||
1570b33e L |
340 | static void |
341 | x86_fill_xstateregset (struct regcache *regcache, void *buf) | |
342 | { | |
343 | i387_cache_to_xsave (regcache, buf); | |
344 | } | |
345 | ||
346 | static void | |
347 | x86_store_xstateregset (struct regcache *regcache, const void *buf) | |
348 | { | |
349 | i387_xsave_to_cache (regcache, buf); | |
350 | } | |
351 | ||
d0722149 DE |
352 | /* ??? The non-biarch i386 case stores all the i387 regs twice. |
353 | Once in i387_.*fsave.* and once in i387_.*fxsave.*. | |
354 | This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS | |
355 | doesn't work. IWBN to avoid the duplication in the case where it | |
356 | does work. Maybe the arch_setup routine could check whether it works | |
357 | and update target_regsets accordingly, maybe by moving target_regsets | |
358 | to linux_target_ops and set the right one there, rather than having to | |
359 | modify the target_regsets global. */ | |
360 | ||
361 | struct regset_info target_regsets[] = | |
362 | { | |
363 | #ifdef HAVE_PTRACE_GETREGS | |
1570b33e | 364 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), |
d0722149 DE |
365 | GENERAL_REGS, |
366 | x86_fill_gregset, x86_store_gregset }, | |
1570b33e L |
367 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_X86_XSTATE, 0, |
368 | EXTENDED_REGS, x86_fill_xstateregset, x86_store_xstateregset }, | |
d0722149 DE |
369 | # ifndef __x86_64__ |
370 | # ifdef HAVE_PTRACE_GETFPXREGS | |
1570b33e | 371 | { PTRACE_GETFPXREGS, PTRACE_SETFPXREGS, 0, sizeof (elf_fpxregset_t), |
d0722149 DE |
372 | EXTENDED_REGS, |
373 | x86_fill_fpxregset, x86_store_fpxregset }, | |
374 | # endif | |
375 | # endif | |
1570b33e | 376 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, sizeof (elf_fpregset_t), |
d0722149 DE |
377 | FP_REGS, |
378 | x86_fill_fpregset, x86_store_fpregset }, | |
379 | #endif /* HAVE_PTRACE_GETREGS */ | |
1570b33e | 380 | { 0, 0, 0, -1, -1, NULL, NULL } |
d0722149 DE |
381 | }; |
382 | ||
383 | static CORE_ADDR | |
442ea881 | 384 | x86_get_pc (struct regcache *regcache) |
d0722149 DE |
385 | { |
386 | int use_64bit = register_size (0) == 8; | |
387 | ||
388 | if (use_64bit) | |
389 | { | |
390 | unsigned long pc; | |
442ea881 | 391 | collect_register_by_name (regcache, "rip", &pc); |
d0722149 DE |
392 | return (CORE_ADDR) pc; |
393 | } | |
394 | else | |
395 | { | |
396 | unsigned int pc; | |
442ea881 | 397 | collect_register_by_name (regcache, "eip", &pc); |
d0722149 DE |
398 | return (CORE_ADDR) pc; |
399 | } | |
400 | } | |
401 | ||
402 | static void | |
442ea881 | 403 | x86_set_pc (struct regcache *regcache, CORE_ADDR pc) |
d0722149 DE |
404 | { |
405 | int use_64bit = register_size (0) == 8; | |
406 | ||
407 | if (use_64bit) | |
408 | { | |
409 | unsigned long newpc = pc; | |
442ea881 | 410 | supply_register_by_name (regcache, "rip", &newpc); |
d0722149 DE |
411 | } |
412 | else | |
413 | { | |
414 | unsigned int newpc = pc; | |
442ea881 | 415 | supply_register_by_name (regcache, "eip", &newpc); |
d0722149 DE |
416 | } |
417 | } | |
418 | \f | |
419 | static const unsigned char x86_breakpoint[] = { 0xCC }; | |
420 | #define x86_breakpoint_len 1 | |
421 | ||
422 | static int | |
423 | x86_breakpoint_at (CORE_ADDR pc) | |
424 | { | |
425 | unsigned char c; | |
426 | ||
fc7238bb | 427 | (*the_target->read_memory) (pc, &c, 1); |
d0722149 DE |
428 | if (c == 0xCC) |
429 | return 1; | |
430 | ||
431 | return 0; | |
432 | } | |
433 | \f | |
aa5ca48f DE |
434 | /* Support for debug registers. */ |
435 | ||
436 | static unsigned long | |
437 | x86_linux_dr_get (ptid_t ptid, int regnum) | |
438 | { | |
439 | int tid; | |
440 | unsigned long value; | |
441 | ||
442 | tid = ptid_get_lwp (ptid); | |
443 | ||
444 | errno = 0; | |
445 | value = ptrace (PTRACE_PEEKUSER, tid, | |
446 | offsetof (struct user, u_debugreg[regnum]), 0); | |
447 | if (errno != 0) | |
448 | error ("Couldn't read debug register"); | |
449 | ||
450 | return value; | |
451 | } | |
452 | ||
453 | static void | |
454 | x86_linux_dr_set (ptid_t ptid, int regnum, unsigned long value) | |
455 | { | |
456 | int tid; | |
457 | ||
458 | tid = ptid_get_lwp (ptid); | |
459 | ||
460 | errno = 0; | |
461 | ptrace (PTRACE_POKEUSER, tid, | |
462 | offsetof (struct user, u_debugreg[regnum]), value); | |
463 | if (errno != 0) | |
464 | error ("Couldn't write debug register"); | |
465 | } | |
466 | ||
964e4306 PA |
467 | static int |
468 | update_debug_registers_callback (struct inferior_list_entry *entry, | |
469 | void *pid_p) | |
470 | { | |
471 | struct lwp_info *lwp = (struct lwp_info *) entry; | |
472 | int pid = *(int *) pid_p; | |
473 | ||
474 | /* Only update the threads of this process. */ | |
475 | if (pid_of (lwp) == pid) | |
476 | { | |
477 | /* The actual update is done later just before resuming the lwp, | |
478 | we just mark that the registers need updating. */ | |
479 | lwp->arch_private->debug_registers_changed = 1; | |
480 | ||
481 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
482 | we can update its debug registers. */ | |
483 | if (!lwp->stopped) | |
484 | linux_stop_lwp (lwp); | |
485 | } | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
aa5ca48f DE |
490 | /* Update the inferior's debug register REGNUM from STATE. */ |
491 | ||
492 | void | |
493 | i386_dr_low_set_addr (const struct i386_debug_reg_state *state, int regnum) | |
494 | { | |
964e4306 | 495 | /* Only update the threads of this process. */ |
aa5ca48f DE |
496 | int pid = pid_of (get_thread_lwp (current_inferior)); |
497 | ||
498 | if (! (regnum >= 0 && regnum <= DR_LASTADDR - DR_FIRSTADDR)) | |
499 | fatal ("Invalid debug register %d", regnum); | |
500 | ||
964e4306 PA |
501 | find_inferior (&all_lwps, update_debug_registers_callback, &pid); |
502 | } | |
aa5ca48f | 503 | |
964e4306 | 504 | /* Return the inferior's debug register REGNUM. */ |
aa5ca48f | 505 | |
964e4306 PA |
506 | CORE_ADDR |
507 | i386_dr_low_get_addr (int regnum) | |
508 | { | |
509 | struct lwp_info *lwp = get_thread_lwp (current_inferior); | |
510 | ptid_t ptid = ptid_of (lwp); | |
511 | ||
512 | /* DR6 and DR7 are retrieved with some other way. */ | |
0a5b1e09 | 513 | gdb_assert (DR_FIRSTADDR <= regnum && regnum <= DR_LASTADDR); |
964e4306 PA |
514 | |
515 | return x86_linux_dr_get (ptid, regnum); | |
aa5ca48f DE |
516 | } |
517 | ||
518 | /* Update the inferior's DR7 debug control register from STATE. */ | |
519 | ||
520 | void | |
521 | i386_dr_low_set_control (const struct i386_debug_reg_state *state) | |
522 | { | |
964e4306 | 523 | /* Only update the threads of this process. */ |
aa5ca48f DE |
524 | int pid = pid_of (get_thread_lwp (current_inferior)); |
525 | ||
964e4306 PA |
526 | find_inferior (&all_lwps, update_debug_registers_callback, &pid); |
527 | } | |
aa5ca48f | 528 | |
964e4306 PA |
529 | /* Return the inferior's DR7 debug control register. */ |
530 | ||
531 | unsigned | |
532 | i386_dr_low_get_control (void) | |
533 | { | |
534 | struct lwp_info *lwp = get_thread_lwp (current_inferior); | |
535 | ptid_t ptid = ptid_of (lwp); | |
536 | ||
537 | return x86_linux_dr_get (ptid, DR_CONTROL); | |
aa5ca48f DE |
538 | } |
539 | ||
540 | /* Get the value of the DR6 debug status register from the inferior | |
541 | and record it in STATE. */ | |
542 | ||
964e4306 PA |
543 | unsigned |
544 | i386_dr_low_get_status (void) | |
aa5ca48f DE |
545 | { |
546 | struct lwp_info *lwp = get_thread_lwp (current_inferior); | |
547 | ptid_t ptid = ptid_of (lwp); | |
548 | ||
964e4306 | 549 | return x86_linux_dr_get (ptid, DR_STATUS); |
aa5ca48f DE |
550 | } |
551 | \f | |
90d74c30 | 552 | /* Breakpoint/Watchpoint support. */ |
aa5ca48f DE |
553 | |
554 | static int | |
555 | x86_insert_point (char type, CORE_ADDR addr, int len) | |
556 | { | |
557 | struct process_info *proc = current_process (); | |
558 | switch (type) | |
559 | { | |
8b07ae33 | 560 | case '0': |
90d74c30 PA |
561 | { |
562 | int ret; | |
563 | ||
564 | ret = prepare_to_access_memory (); | |
565 | if (ret) | |
566 | return -1; | |
567 | ret = set_gdb_breakpoint_at (addr); | |
0146f85b | 568 | done_accessing_memory (); |
90d74c30 PA |
569 | return ret; |
570 | } | |
aa5ca48f DE |
571 | case '2': |
572 | case '3': | |
573 | case '4': | |
574 | return i386_low_insert_watchpoint (&proc->private->arch_private->debug_reg_state, | |
575 | type, addr, len); | |
576 | default: | |
577 | /* Unsupported. */ | |
578 | return 1; | |
579 | } | |
580 | } | |
581 | ||
582 | static int | |
583 | x86_remove_point (char type, CORE_ADDR addr, int len) | |
584 | { | |
585 | struct process_info *proc = current_process (); | |
586 | switch (type) | |
587 | { | |
8b07ae33 | 588 | case '0': |
90d74c30 PA |
589 | { |
590 | int ret; | |
591 | ||
592 | ret = prepare_to_access_memory (); | |
593 | if (ret) | |
594 | return -1; | |
595 | ret = delete_gdb_breakpoint_at (addr); | |
0146f85b | 596 | done_accessing_memory (); |
90d74c30 PA |
597 | return ret; |
598 | } | |
aa5ca48f DE |
599 | case '2': |
600 | case '3': | |
601 | case '4': | |
602 | return i386_low_remove_watchpoint (&proc->private->arch_private->debug_reg_state, | |
603 | type, addr, len); | |
604 | default: | |
605 | /* Unsupported. */ | |
606 | return 1; | |
607 | } | |
608 | } | |
609 | ||
610 | static int | |
611 | x86_stopped_by_watchpoint (void) | |
612 | { | |
613 | struct process_info *proc = current_process (); | |
614 | return i386_low_stopped_by_watchpoint (&proc->private->arch_private->debug_reg_state); | |
615 | } | |
616 | ||
617 | static CORE_ADDR | |
618 | x86_stopped_data_address (void) | |
619 | { | |
620 | struct process_info *proc = current_process (); | |
621 | CORE_ADDR addr; | |
622 | if (i386_low_stopped_data_address (&proc->private->arch_private->debug_reg_state, | |
623 | &addr)) | |
624 | return addr; | |
625 | return 0; | |
626 | } | |
627 | \f | |
628 | /* Called when a new process is created. */ | |
629 | ||
630 | static struct arch_process_info * | |
631 | x86_linux_new_process (void) | |
632 | { | |
633 | struct arch_process_info *info = xcalloc (1, sizeof (*info)); | |
634 | ||
635 | i386_low_init_dregs (&info->debug_reg_state); | |
636 | ||
637 | return info; | |
638 | } | |
639 | ||
640 | /* Called when a new thread is detected. */ | |
641 | ||
642 | static struct arch_lwp_info * | |
643 | x86_linux_new_thread (void) | |
644 | { | |
645 | struct arch_lwp_info *info = xcalloc (1, sizeof (*info)); | |
646 | ||
647 | info->debug_registers_changed = 1; | |
648 | ||
649 | return info; | |
650 | } | |
651 | ||
652 | /* Called when resuming a thread. | |
653 | If the debug regs have changed, update the thread's copies. */ | |
654 | ||
655 | static void | |
656 | x86_linux_prepare_to_resume (struct lwp_info *lwp) | |
657 | { | |
b9a881c2 | 658 | ptid_t ptid = ptid_of (lwp); |
6210a125 | 659 | int clear_status = 0; |
b9a881c2 | 660 | |
aa5ca48f DE |
661 | if (lwp->arch_private->debug_registers_changed) |
662 | { | |
663 | int i; | |
aa5ca48f DE |
664 | int pid = ptid_get_pid (ptid); |
665 | struct process_info *proc = find_process_pid (pid); | |
493e2a69 MS |
666 | struct i386_debug_reg_state *state |
667 | = &proc->private->arch_private->debug_reg_state; | |
aa5ca48f DE |
668 | |
669 | for (i = DR_FIRSTADDR; i <= DR_LASTADDR; i++) | |
6210a125 PA |
670 | if (state->dr_ref_count[i] > 0) |
671 | { | |
672 | x86_linux_dr_set (ptid, i, state->dr_mirror[i]); | |
673 | ||
674 | /* If we're setting a watchpoint, any change the inferior | |
675 | had done itself to the debug registers needs to be | |
676 | discarded, otherwise, i386_low_stopped_data_address can | |
677 | get confused. */ | |
678 | clear_status = 1; | |
679 | } | |
aa5ca48f DE |
680 | |
681 | x86_linux_dr_set (ptid, DR_CONTROL, state->dr_control_mirror); | |
682 | ||
683 | lwp->arch_private->debug_registers_changed = 0; | |
684 | } | |
b9a881c2 | 685 | |
6210a125 | 686 | if (clear_status || lwp->stopped_by_watchpoint) |
b9a881c2 | 687 | x86_linux_dr_set (ptid, DR_STATUS, 0); |
aa5ca48f DE |
688 | } |
689 | \f | |
d0722149 DE |
690 | /* When GDBSERVER is built as a 64-bit application on linux, the |
691 | PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since | |
692 | debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same | |
693 | as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit | |
694 | conversion in-place ourselves. */ | |
695 | ||
696 | /* These types below (compat_*) define a siginfo type that is layout | |
697 | compatible with the siginfo type exported by the 32-bit userspace | |
698 | support. */ | |
699 | ||
700 | #ifdef __x86_64__ | |
701 | ||
702 | typedef int compat_int_t; | |
703 | typedef unsigned int compat_uptr_t; | |
704 | ||
705 | typedef int compat_time_t; | |
706 | typedef int compat_timer_t; | |
707 | typedef int compat_clock_t; | |
708 | ||
709 | struct compat_timeval | |
710 | { | |
711 | compat_time_t tv_sec; | |
712 | int tv_usec; | |
713 | }; | |
714 | ||
715 | typedef union compat_sigval | |
716 | { | |
717 | compat_int_t sival_int; | |
718 | compat_uptr_t sival_ptr; | |
719 | } compat_sigval_t; | |
720 | ||
721 | typedef struct compat_siginfo | |
722 | { | |
723 | int si_signo; | |
724 | int si_errno; | |
725 | int si_code; | |
726 | ||
727 | union | |
728 | { | |
729 | int _pad[((128 / sizeof (int)) - 3)]; | |
730 | ||
731 | /* kill() */ | |
732 | struct | |
733 | { | |
734 | unsigned int _pid; | |
735 | unsigned int _uid; | |
736 | } _kill; | |
737 | ||
738 | /* POSIX.1b timers */ | |
739 | struct | |
740 | { | |
741 | compat_timer_t _tid; | |
742 | int _overrun; | |
743 | compat_sigval_t _sigval; | |
744 | } _timer; | |
745 | ||
746 | /* POSIX.1b signals */ | |
747 | struct | |
748 | { | |
749 | unsigned int _pid; | |
750 | unsigned int _uid; | |
751 | compat_sigval_t _sigval; | |
752 | } _rt; | |
753 | ||
754 | /* SIGCHLD */ | |
755 | struct | |
756 | { | |
757 | unsigned int _pid; | |
758 | unsigned int _uid; | |
759 | int _status; | |
760 | compat_clock_t _utime; | |
761 | compat_clock_t _stime; | |
762 | } _sigchld; | |
763 | ||
764 | /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ | |
765 | struct | |
766 | { | |
767 | unsigned int _addr; | |
768 | } _sigfault; | |
769 | ||
770 | /* SIGPOLL */ | |
771 | struct | |
772 | { | |
773 | int _band; | |
774 | int _fd; | |
775 | } _sigpoll; | |
776 | } _sifields; | |
777 | } compat_siginfo_t; | |
778 | ||
c92b5177 L |
779 | /* For x32, clock_t in _sigchld is 64bit aligned at 4 bytes. */ |
780 | typedef long __attribute__ ((__aligned__ (4))) compat_x32_clock_t; | |
781 | ||
782 | typedef struct compat_x32_siginfo | |
783 | { | |
784 | int si_signo; | |
785 | int si_errno; | |
786 | int si_code; | |
787 | ||
788 | union | |
789 | { | |
790 | int _pad[((128 / sizeof (int)) - 3)]; | |
791 | ||
792 | /* kill() */ | |
793 | struct | |
794 | { | |
795 | unsigned int _pid; | |
796 | unsigned int _uid; | |
797 | } _kill; | |
798 | ||
799 | /* POSIX.1b timers */ | |
800 | struct | |
801 | { | |
802 | compat_timer_t _tid; | |
803 | int _overrun; | |
804 | compat_sigval_t _sigval; | |
805 | } _timer; | |
806 | ||
807 | /* POSIX.1b signals */ | |
808 | struct | |
809 | { | |
810 | unsigned int _pid; | |
811 | unsigned int _uid; | |
812 | compat_sigval_t _sigval; | |
813 | } _rt; | |
814 | ||
815 | /* SIGCHLD */ | |
816 | struct | |
817 | { | |
818 | unsigned int _pid; | |
819 | unsigned int _uid; | |
820 | int _status; | |
821 | compat_x32_clock_t _utime; | |
822 | compat_x32_clock_t _stime; | |
823 | } _sigchld; | |
824 | ||
825 | /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ | |
826 | struct | |
827 | { | |
828 | unsigned int _addr; | |
829 | } _sigfault; | |
830 | ||
831 | /* SIGPOLL */ | |
832 | struct | |
833 | { | |
834 | int _band; | |
835 | int _fd; | |
836 | } _sigpoll; | |
837 | } _sifields; | |
838 | } compat_x32_siginfo_t __attribute__ ((__aligned__ (8))); | |
839 | ||
d0722149 DE |
840 | #define cpt_si_pid _sifields._kill._pid |
841 | #define cpt_si_uid _sifields._kill._uid | |
842 | #define cpt_si_timerid _sifields._timer._tid | |
843 | #define cpt_si_overrun _sifields._timer._overrun | |
844 | #define cpt_si_status _sifields._sigchld._status | |
845 | #define cpt_si_utime _sifields._sigchld._utime | |
846 | #define cpt_si_stime _sifields._sigchld._stime | |
847 | #define cpt_si_ptr _sifields._rt._sigval.sival_ptr | |
848 | #define cpt_si_addr _sifields._sigfault._addr | |
849 | #define cpt_si_band _sifields._sigpoll._band | |
850 | #define cpt_si_fd _sifields._sigpoll._fd | |
851 | ||
852 | /* glibc at least up to 2.3.2 doesn't have si_timerid, si_overrun. | |
853 | In their place is si_timer1,si_timer2. */ | |
854 | #ifndef si_timerid | |
855 | #define si_timerid si_timer1 | |
856 | #endif | |
857 | #ifndef si_overrun | |
858 | #define si_overrun si_timer2 | |
859 | #endif | |
860 | ||
861 | static void | |
862 | compat_siginfo_from_siginfo (compat_siginfo_t *to, siginfo_t *from) | |
863 | { | |
864 | memset (to, 0, sizeof (*to)); | |
865 | ||
866 | to->si_signo = from->si_signo; | |
867 | to->si_errno = from->si_errno; | |
868 | to->si_code = from->si_code; | |
869 | ||
b53a1623 | 870 | if (to->si_code == SI_TIMER) |
d0722149 | 871 | { |
b53a1623 PA |
872 | to->cpt_si_timerid = from->si_timerid; |
873 | to->cpt_si_overrun = from->si_overrun; | |
d0722149 DE |
874 | to->cpt_si_ptr = (intptr_t) from->si_ptr; |
875 | } | |
876 | else if (to->si_code == SI_USER) | |
877 | { | |
878 | to->cpt_si_pid = from->si_pid; | |
879 | to->cpt_si_uid = from->si_uid; | |
880 | } | |
b53a1623 | 881 | else if (to->si_code < 0) |
d0722149 | 882 | { |
b53a1623 PA |
883 | to->cpt_si_pid = from->si_pid; |
884 | to->cpt_si_uid = from->si_uid; | |
d0722149 DE |
885 | to->cpt_si_ptr = (intptr_t) from->si_ptr; |
886 | } | |
887 | else | |
888 | { | |
889 | switch (to->si_signo) | |
890 | { | |
891 | case SIGCHLD: | |
892 | to->cpt_si_pid = from->si_pid; | |
893 | to->cpt_si_uid = from->si_uid; | |
894 | to->cpt_si_status = from->si_status; | |
895 | to->cpt_si_utime = from->si_utime; | |
896 | to->cpt_si_stime = from->si_stime; | |
897 | break; | |
898 | case SIGILL: | |
899 | case SIGFPE: | |
900 | case SIGSEGV: | |
901 | case SIGBUS: | |
902 | to->cpt_si_addr = (intptr_t) from->si_addr; | |
903 | break; | |
904 | case SIGPOLL: | |
905 | to->cpt_si_band = from->si_band; | |
906 | to->cpt_si_fd = from->si_fd; | |
907 | break; | |
908 | default: | |
909 | to->cpt_si_pid = from->si_pid; | |
910 | to->cpt_si_uid = from->si_uid; | |
911 | to->cpt_si_ptr = (intptr_t) from->si_ptr; | |
912 | break; | |
913 | } | |
914 | } | |
915 | } | |
916 | ||
917 | static void | |
918 | siginfo_from_compat_siginfo (siginfo_t *to, compat_siginfo_t *from) | |
919 | { | |
920 | memset (to, 0, sizeof (*to)); | |
921 | ||
922 | to->si_signo = from->si_signo; | |
923 | to->si_errno = from->si_errno; | |
924 | to->si_code = from->si_code; | |
925 | ||
b53a1623 | 926 | if (to->si_code == SI_TIMER) |
d0722149 | 927 | { |
b53a1623 PA |
928 | to->si_timerid = from->cpt_si_timerid; |
929 | to->si_overrun = from->cpt_si_overrun; | |
d0722149 DE |
930 | to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr; |
931 | } | |
932 | else if (to->si_code == SI_USER) | |
933 | { | |
934 | to->si_pid = from->cpt_si_pid; | |
935 | to->si_uid = from->cpt_si_uid; | |
936 | } | |
b53a1623 | 937 | else if (to->si_code < 0) |
d0722149 | 938 | { |
b53a1623 PA |
939 | to->si_pid = from->cpt_si_pid; |
940 | to->si_uid = from->cpt_si_uid; | |
d0722149 DE |
941 | to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr; |
942 | } | |
943 | else | |
944 | { | |
945 | switch (to->si_signo) | |
946 | { | |
947 | case SIGCHLD: | |
948 | to->si_pid = from->cpt_si_pid; | |
949 | to->si_uid = from->cpt_si_uid; | |
950 | to->si_status = from->cpt_si_status; | |
951 | to->si_utime = from->cpt_si_utime; | |
952 | to->si_stime = from->cpt_si_stime; | |
953 | break; | |
954 | case SIGILL: | |
955 | case SIGFPE: | |
956 | case SIGSEGV: | |
957 | case SIGBUS: | |
958 | to->si_addr = (void *) (intptr_t) from->cpt_si_addr; | |
959 | break; | |
960 | case SIGPOLL: | |
961 | to->si_band = from->cpt_si_band; | |
962 | to->si_fd = from->cpt_si_fd; | |
963 | break; | |
964 | default: | |
965 | to->si_pid = from->cpt_si_pid; | |
966 | to->si_uid = from->cpt_si_uid; | |
967 | to->si_ptr = (void* ) (intptr_t) from->cpt_si_ptr; | |
968 | break; | |
969 | } | |
970 | } | |
971 | } | |
972 | ||
c92b5177 L |
973 | static void |
974 | compat_x32_siginfo_from_siginfo (compat_x32_siginfo_t *to, | |
975 | siginfo_t *from) | |
976 | { | |
977 | memset (to, 0, sizeof (*to)); | |
978 | ||
979 | to->si_signo = from->si_signo; | |
980 | to->si_errno = from->si_errno; | |
981 | to->si_code = from->si_code; | |
982 | ||
983 | if (to->si_code == SI_TIMER) | |
984 | { | |
985 | to->cpt_si_timerid = from->si_timerid; | |
986 | to->cpt_si_overrun = from->si_overrun; | |
987 | to->cpt_si_ptr = (intptr_t) from->si_ptr; | |
988 | } | |
989 | else if (to->si_code == SI_USER) | |
990 | { | |
991 | to->cpt_si_pid = from->si_pid; | |
992 | to->cpt_si_uid = from->si_uid; | |
993 | } | |
994 | else if (to->si_code < 0) | |
995 | { | |
996 | to->cpt_si_pid = from->si_pid; | |
997 | to->cpt_si_uid = from->si_uid; | |
998 | to->cpt_si_ptr = (intptr_t) from->si_ptr; | |
999 | } | |
1000 | else | |
1001 | { | |
1002 | switch (to->si_signo) | |
1003 | { | |
1004 | case SIGCHLD: | |
1005 | to->cpt_si_pid = from->si_pid; | |
1006 | to->cpt_si_uid = from->si_uid; | |
1007 | to->cpt_si_status = from->si_status; | |
1008 | to->cpt_si_utime = from->si_utime; | |
1009 | to->cpt_si_stime = from->si_stime; | |
1010 | break; | |
1011 | case SIGILL: | |
1012 | case SIGFPE: | |
1013 | case SIGSEGV: | |
1014 | case SIGBUS: | |
1015 | to->cpt_si_addr = (intptr_t) from->si_addr; | |
1016 | break; | |
1017 | case SIGPOLL: | |
1018 | to->cpt_si_band = from->si_band; | |
1019 | to->cpt_si_fd = from->si_fd; | |
1020 | break; | |
1021 | default: | |
1022 | to->cpt_si_pid = from->si_pid; | |
1023 | to->cpt_si_uid = from->si_uid; | |
1024 | to->cpt_si_ptr = (intptr_t) from->si_ptr; | |
1025 | break; | |
1026 | } | |
1027 | } | |
1028 | } | |
1029 | ||
1030 | static void | |
1031 | siginfo_from_compat_x32_siginfo (siginfo_t *to, | |
1032 | compat_x32_siginfo_t *from) | |
1033 | { | |
1034 | memset (to, 0, sizeof (*to)); | |
1035 | ||
1036 | to->si_signo = from->si_signo; | |
1037 | to->si_errno = from->si_errno; | |
1038 | to->si_code = from->si_code; | |
1039 | ||
1040 | if (to->si_code == SI_TIMER) | |
1041 | { | |
1042 | to->si_timerid = from->cpt_si_timerid; | |
1043 | to->si_overrun = from->cpt_si_overrun; | |
1044 | to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr; | |
1045 | } | |
1046 | else if (to->si_code == SI_USER) | |
1047 | { | |
1048 | to->si_pid = from->cpt_si_pid; | |
1049 | to->si_uid = from->cpt_si_uid; | |
1050 | } | |
1051 | else if (to->si_code < 0) | |
1052 | { | |
1053 | to->si_pid = from->cpt_si_pid; | |
1054 | to->si_uid = from->cpt_si_uid; | |
1055 | to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr; | |
1056 | } | |
1057 | else | |
1058 | { | |
1059 | switch (to->si_signo) | |
1060 | { | |
1061 | case SIGCHLD: | |
1062 | to->si_pid = from->cpt_si_pid; | |
1063 | to->si_uid = from->cpt_si_uid; | |
1064 | to->si_status = from->cpt_si_status; | |
1065 | to->si_utime = from->cpt_si_utime; | |
1066 | to->si_stime = from->cpt_si_stime; | |
1067 | break; | |
1068 | case SIGILL: | |
1069 | case SIGFPE: | |
1070 | case SIGSEGV: | |
1071 | case SIGBUS: | |
1072 | to->si_addr = (void *) (intptr_t) from->cpt_si_addr; | |
1073 | break; | |
1074 | case SIGPOLL: | |
1075 | to->si_band = from->cpt_si_band; | |
1076 | to->si_fd = from->cpt_si_fd; | |
1077 | break; | |
1078 | default: | |
1079 | to->si_pid = from->cpt_si_pid; | |
1080 | to->si_uid = from->cpt_si_uid; | |
1081 | to->si_ptr = (void* ) (intptr_t) from->cpt_si_ptr; | |
1082 | break; | |
1083 | } | |
1084 | } | |
1085 | } | |
1086 | ||
1087 | /* Is this process 64-bit? */ | |
1088 | static int linux_is_elf64; | |
d0722149 DE |
1089 | #endif /* __x86_64__ */ |
1090 | ||
1091 | /* Convert a native/host siginfo object, into/from the siginfo in the | |
1092 | layout of the inferiors' architecture. Returns true if any | |
1093 | conversion was done; false otherwise. If DIRECTION is 1, then copy | |
1094 | from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to | |
1095 | INF. */ | |
1096 | ||
1097 | static int | |
a5362b9a | 1098 | x86_siginfo_fixup (siginfo_t *native, void *inf, int direction) |
d0722149 DE |
1099 | { |
1100 | #ifdef __x86_64__ | |
1101 | /* Is the inferior 32-bit? If so, then fixup the siginfo object. */ | |
1102 | if (register_size (0) == 4) | |
1103 | { | |
a5362b9a | 1104 | if (sizeof (siginfo_t) != sizeof (compat_siginfo_t)) |
9f1036c1 | 1105 | fatal ("unexpected difference in siginfo"); |
d0722149 DE |
1106 | |
1107 | if (direction == 0) | |
1108 | compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, native); | |
1109 | else | |
1110 | siginfo_from_compat_siginfo (native, (struct compat_siginfo *) inf); | |
1111 | ||
c92b5177 L |
1112 | return 1; |
1113 | } | |
1114 | /* No fixup for native x32 GDB. */ | |
1115 | else if (!linux_is_elf64 && sizeof (void *) == 8) | |
1116 | { | |
1117 | if (sizeof (siginfo_t) != sizeof (compat_x32_siginfo_t)) | |
1118 | fatal ("unexpected difference in siginfo"); | |
1119 | ||
1120 | if (direction == 0) | |
1121 | compat_x32_siginfo_from_siginfo ((struct compat_x32_siginfo *) inf, | |
1122 | native); | |
1123 | else | |
1124 | siginfo_from_compat_x32_siginfo (native, | |
1125 | (struct compat_x32_siginfo *) inf); | |
1126 | ||
d0722149 DE |
1127 | return 1; |
1128 | } | |
1129 | #endif | |
1130 | ||
1131 | return 0; | |
1132 | } | |
1133 | \f | |
1570b33e L |
1134 | static int use_xml; |
1135 | ||
1136 | /* Update gdbserver_xmltarget. */ | |
1137 | ||
1138 | static void | |
1139 | x86_linux_update_xmltarget (void) | |
1140 | { | |
3a13a53b L |
1141 | int pid; |
1142 | struct regset_info *regset; | |
1570b33e L |
1143 | static unsigned long long xcr0; |
1144 | static int have_ptrace_getregset = -1; | |
59e04013 | 1145 | #if !defined(__x86_64__) && defined(HAVE_PTRACE_GETFPXREGS) |
3a13a53b L |
1146 | static int have_ptrace_getfpxregs = -1; |
1147 | #endif | |
1570b33e L |
1148 | |
1149 | if (!current_inferior) | |
1150 | return; | |
1151 | ||
45ba0d02 PA |
1152 | /* Before changing the register cache internal layout or the target |
1153 | regsets, flush the contents of the current valid caches back to | |
1154 | the threads. */ | |
1155 | regcache_invalidate (); | |
1156 | ||
3a13a53b | 1157 | pid = pid_of (get_thread_lwp (current_inferior)); |
1570b33e L |
1158 | #ifdef __x86_64__ |
1159 | if (num_xmm_registers == 8) | |
1160 | init_registers_i386_linux (); | |
1161 | else | |
1162 | init_registers_amd64_linux (); | |
1163 | #else | |
3a13a53b L |
1164 | { |
1165 | # ifdef HAVE_PTRACE_GETFPXREGS | |
1166 | if (have_ptrace_getfpxregs == -1) | |
1167 | { | |
1168 | elf_fpxregset_t fpxregs; | |
1169 | ||
1170 | if (ptrace (PTRACE_GETFPXREGS, pid, 0, (int) &fpxregs) < 0) | |
1171 | { | |
1172 | have_ptrace_getfpxregs = 0; | |
1173 | x86_xcr0 = I386_XSTATE_X87_MASK; | |
1174 | ||
1175 | /* Disable PTRACE_GETFPXREGS. */ | |
1176 | for (regset = target_regsets; | |
1177 | regset->fill_function != NULL; regset++) | |
1178 | if (regset->get_request == PTRACE_GETFPXREGS) | |
1179 | { | |
1180 | regset->size = 0; | |
1181 | break; | |
1182 | } | |
1183 | } | |
1184 | else | |
1185 | have_ptrace_getfpxregs = 1; | |
1186 | } | |
1187 | ||
1188 | if (!have_ptrace_getfpxregs) | |
1189 | { | |
1190 | init_registers_i386_mmx_linux (); | |
1191 | return; | |
1192 | } | |
1193 | # endif | |
1194 | init_registers_i386_linux (); | |
1195 | } | |
1570b33e L |
1196 | #endif |
1197 | ||
1198 | if (!use_xml) | |
1199 | { | |
1200 | /* Don't use XML. */ | |
1201 | #ifdef __x86_64__ | |
1202 | if (num_xmm_registers == 8) | |
1203 | gdbserver_xmltarget = xmltarget_i386_linux_no_xml; | |
1204 | else | |
1205 | gdbserver_xmltarget = xmltarget_amd64_linux_no_xml; | |
1206 | #else | |
1207 | gdbserver_xmltarget = xmltarget_i386_linux_no_xml; | |
1208 | #endif | |
1209 | ||
1210 | x86_xcr0 = I386_XSTATE_SSE_MASK; | |
1211 | ||
1212 | return; | |
1213 | } | |
1214 | ||
1215 | /* Check if XSAVE extended state is supported. */ | |
1216 | if (have_ptrace_getregset == -1) | |
1217 | { | |
1570b33e L |
1218 | unsigned long long xstateregs[I386_XSTATE_SSE_SIZE / sizeof (long long)]; |
1219 | struct iovec iov; | |
1570b33e L |
1220 | |
1221 | iov.iov_base = xstateregs; | |
1222 | iov.iov_len = sizeof (xstateregs); | |
1223 | ||
1224 | /* Check if PTRACE_GETREGSET works. */ | |
1225 | if (ptrace (PTRACE_GETREGSET, pid, (unsigned int) NT_X86_XSTATE, | |
1226 | &iov) < 0) | |
1227 | { | |
1228 | have_ptrace_getregset = 0; | |
1229 | return; | |
1230 | } | |
1231 | else | |
1232 | have_ptrace_getregset = 1; | |
1233 | ||
1234 | /* Get XCR0 from XSAVE extended state at byte 464. */ | |
1235 | xcr0 = xstateregs[464 / sizeof (long long)]; | |
1236 | ||
1237 | /* Use PTRACE_GETREGSET if it is available. */ | |
1238 | for (regset = target_regsets; | |
1239 | regset->fill_function != NULL; regset++) | |
1240 | if (regset->get_request == PTRACE_GETREGSET) | |
1241 | regset->size = I386_XSTATE_SIZE (xcr0); | |
1242 | else if (regset->type != GENERAL_REGS) | |
1243 | regset->size = 0; | |
1244 | } | |
1245 | ||
1246 | if (have_ptrace_getregset) | |
1247 | { | |
1248 | /* AVX is the highest feature we support. */ | |
1249 | if ((xcr0 & I386_XSTATE_AVX_MASK) == I386_XSTATE_AVX_MASK) | |
1250 | { | |
1251 | x86_xcr0 = xcr0; | |
1252 | ||
1253 | #ifdef __x86_64__ | |
1254 | /* I386 has 8 xmm regs. */ | |
1255 | if (num_xmm_registers == 8) | |
1256 | init_registers_i386_avx_linux (); | |
1257 | else | |
1258 | init_registers_amd64_avx_linux (); | |
1259 | #else | |
1260 | init_registers_i386_avx_linux (); | |
1261 | #endif | |
1262 | } | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | /* Process qSupported query, "xmlRegisters=". Update the buffer size for | |
1267 | PTRACE_GETREGSET. */ | |
1268 | ||
1269 | static void | |
1270 | x86_linux_process_qsupported (const char *query) | |
1271 | { | |
1272 | /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters=" | |
1273 | with "i386" in qSupported query, it supports x86 XML target | |
1274 | descriptions. */ | |
1275 | use_xml = 0; | |
1276 | if (query != NULL && strncmp (query, "xmlRegisters=", 13) == 0) | |
1277 | { | |
1278 | char *copy = xstrdup (query + 13); | |
1279 | char *p; | |
1280 | ||
1281 | for (p = strtok (copy, ","); p != NULL; p = strtok (NULL, ",")) | |
1282 | { | |
1283 | if (strcmp (p, "i386") == 0) | |
1284 | { | |
1285 | use_xml = 1; | |
1286 | break; | |
1287 | } | |
1288 | } | |
1289 | ||
1290 | free (copy); | |
1291 | } | |
1292 | ||
1293 | x86_linux_update_xmltarget (); | |
1294 | } | |
1295 | ||
9f1036c1 | 1296 | /* Initialize gdbserver for the architecture of the inferior. */ |
d0722149 DE |
1297 | |
1298 | static void | |
1299 | x86_arch_setup (void) | |
1300 | { | |
d0722149 | 1301 | int pid = pid_of (get_thread_lwp (current_inferior)); |
214d508e L |
1302 | unsigned int machine; |
1303 | int is_elf64 = linux_pid_exe_is_elf_64_file (pid, &machine); | |
d0722149 | 1304 | |
214d508e L |
1305 | if (sizeof (void *) == 4) |
1306 | { | |
1307 | if (is_elf64 > 0) | |
1308 | error (_("Can't debug 64-bit process with 32-bit GDBserver")); | |
1309 | #ifndef __x86_64__ | |
1310 | else if (machine == EM_X86_64) | |
1311 | error (_("Can't debug x86-64 process with 32-bit GDBserver")); | |
1312 | #endif | |
1313 | } | |
1314 | ||
1315 | #ifdef __x86_64__ | |
1316 | if (is_elf64 < 0) | |
d0722149 DE |
1317 | { |
1318 | /* This can only happen if /proc/<pid>/exe is unreadable, | |
1319 | but "that can't happen" if we've gotten this far. | |
1320 | Fall through and assume this is a 32-bit program. */ | |
1321 | } | |
214d508e | 1322 | else if (machine == EM_X86_64) |
d0722149 | 1323 | { |
d0722149 DE |
1324 | /* Amd64 doesn't have HAVE_LINUX_USRREGS. */ |
1325 | the_low_target.num_regs = -1; | |
1326 | the_low_target.regmap = NULL; | |
1327 | the_low_target.cannot_fetch_register = NULL; | |
1328 | the_low_target.cannot_store_register = NULL; | |
1329 | ||
1330 | /* Amd64 has 16 xmm regs. */ | |
1331 | num_xmm_registers = 16; | |
1332 | ||
c92b5177 | 1333 | linux_is_elf64 = is_elf64; |
1570b33e | 1334 | x86_linux_update_xmltarget (); |
d0722149 DE |
1335 | return; |
1336 | } | |
c92b5177 L |
1337 | |
1338 | linux_is_elf64 = 0; | |
d0722149 DE |
1339 | #endif |
1340 | ||
1341 | /* Ok we have a 32-bit inferior. */ | |
1342 | ||
d0722149 DE |
1343 | the_low_target.num_regs = I386_NUM_REGS; |
1344 | the_low_target.regmap = i386_regmap; | |
1345 | the_low_target.cannot_fetch_register = i386_cannot_fetch_register; | |
1346 | the_low_target.cannot_store_register = i386_cannot_store_register; | |
1347 | ||
1348 | /* I386 has 8 xmm regs. */ | |
1349 | num_xmm_registers = 8; | |
1570b33e L |
1350 | |
1351 | x86_linux_update_xmltarget (); | |
d0722149 DE |
1352 | } |
1353 | ||
219f2f23 PA |
1354 | static int |
1355 | x86_supports_tracepoints (void) | |
1356 | { | |
1357 | return 1; | |
1358 | } | |
1359 | ||
fa593d66 PA |
1360 | static void |
1361 | append_insns (CORE_ADDR *to, size_t len, const unsigned char *buf) | |
1362 | { | |
1363 | write_inferior_memory (*to, buf, len); | |
1364 | *to += len; | |
1365 | } | |
1366 | ||
1367 | static int | |
1368 | push_opcode (unsigned char *buf, char *op) | |
1369 | { | |
1370 | unsigned char *buf_org = buf; | |
1371 | ||
1372 | while (1) | |
1373 | { | |
1374 | char *endptr; | |
1375 | unsigned long ul = strtoul (op, &endptr, 16); | |
1376 | ||
1377 | if (endptr == op) | |
1378 | break; | |
1379 | ||
1380 | *buf++ = ul; | |
1381 | op = endptr; | |
1382 | } | |
1383 | ||
1384 | return buf - buf_org; | |
1385 | } | |
1386 | ||
1387 | #ifdef __x86_64__ | |
1388 | ||
1389 | /* Build a jump pad that saves registers and calls a collection | |
1390 | function. Writes a jump instruction to the jump pad to | |
1391 | JJUMPAD_INSN. The caller is responsible to write it in at the | |
1392 | tracepoint address. */ | |
1393 | ||
1394 | static int | |
1395 | amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, | |
1396 | CORE_ADDR collector, | |
1397 | CORE_ADDR lockaddr, | |
1398 | ULONGEST orig_size, | |
1399 | CORE_ADDR *jump_entry, | |
405f8e94 SS |
1400 | CORE_ADDR *trampoline, |
1401 | ULONGEST *trampoline_size, | |
fa593d66 PA |
1402 | unsigned char *jjump_pad_insn, |
1403 | ULONGEST *jjump_pad_insn_size, | |
1404 | CORE_ADDR *adjusted_insn_addr, | |
405f8e94 SS |
1405 | CORE_ADDR *adjusted_insn_addr_end, |
1406 | char *err) | |
fa593d66 PA |
1407 | { |
1408 | unsigned char buf[40]; | |
1409 | int i, offset; | |
f4647387 YQ |
1410 | int64_t loffset; |
1411 | ||
fa593d66 PA |
1412 | CORE_ADDR buildaddr = *jump_entry; |
1413 | ||
1414 | /* Build the jump pad. */ | |
1415 | ||
1416 | /* First, do tracepoint data collection. Save registers. */ | |
1417 | i = 0; | |
1418 | /* Need to ensure stack pointer saved first. */ | |
1419 | buf[i++] = 0x54; /* push %rsp */ | |
1420 | buf[i++] = 0x55; /* push %rbp */ | |
1421 | buf[i++] = 0x57; /* push %rdi */ | |
1422 | buf[i++] = 0x56; /* push %rsi */ | |
1423 | buf[i++] = 0x52; /* push %rdx */ | |
1424 | buf[i++] = 0x51; /* push %rcx */ | |
1425 | buf[i++] = 0x53; /* push %rbx */ | |
1426 | buf[i++] = 0x50; /* push %rax */ | |
1427 | buf[i++] = 0x41; buf[i++] = 0x57; /* push %r15 */ | |
1428 | buf[i++] = 0x41; buf[i++] = 0x56; /* push %r14 */ | |
1429 | buf[i++] = 0x41; buf[i++] = 0x55; /* push %r13 */ | |
1430 | buf[i++] = 0x41; buf[i++] = 0x54; /* push %r12 */ | |
1431 | buf[i++] = 0x41; buf[i++] = 0x53; /* push %r11 */ | |
1432 | buf[i++] = 0x41; buf[i++] = 0x52; /* push %r10 */ | |
1433 | buf[i++] = 0x41; buf[i++] = 0x51; /* push %r9 */ | |
1434 | buf[i++] = 0x41; buf[i++] = 0x50; /* push %r8 */ | |
1435 | buf[i++] = 0x9c; /* pushfq */ | |
1436 | buf[i++] = 0x48; /* movl <addr>,%rdi */ | |
1437 | buf[i++] = 0xbf; | |
1438 | *((unsigned long *)(buf + i)) = (unsigned long) tpaddr; | |
1439 | i += sizeof (unsigned long); | |
1440 | buf[i++] = 0x57; /* push %rdi */ | |
1441 | append_insns (&buildaddr, i, buf); | |
1442 | ||
1443 | /* Stack space for the collecting_t object. */ | |
1444 | i = 0; | |
1445 | i += push_opcode (&buf[i], "48 83 ec 18"); /* sub $0x18,%rsp */ | |
1446 | i += push_opcode (&buf[i], "48 b8"); /* mov <tpoint>,%rax */ | |
1447 | memcpy (buf + i, &tpoint, 8); | |
1448 | i += 8; | |
1449 | i += push_opcode (&buf[i], "48 89 04 24"); /* mov %rax,(%rsp) */ | |
1450 | i += push_opcode (&buf[i], | |
1451 | "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */ | |
1452 | i += push_opcode (&buf[i], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */ | |
1453 | append_insns (&buildaddr, i, buf); | |
1454 | ||
1455 | /* spin-lock. */ | |
1456 | i = 0; | |
1457 | i += push_opcode (&buf[i], "48 be"); /* movl <lockaddr>,%rsi */ | |
1458 | memcpy (&buf[i], (void *) &lockaddr, 8); | |
1459 | i += 8; | |
1460 | i += push_opcode (&buf[i], "48 89 e1"); /* mov %rsp,%rcx */ | |
1461 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ | |
1462 | i += push_opcode (&buf[i], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */ | |
1463 | i += push_opcode (&buf[i], "48 85 c0"); /* test %rax,%rax */ | |
1464 | i += push_opcode (&buf[i], "75 f4"); /* jne <again> */ | |
1465 | append_insns (&buildaddr, i, buf); | |
1466 | ||
1467 | /* Set up the gdb_collect call. */ | |
1468 | /* At this point, (stack pointer + 0x18) is the base of our saved | |
1469 | register block. */ | |
1470 | ||
1471 | i = 0; | |
1472 | i += push_opcode (&buf[i], "48 89 e6"); /* mov %rsp,%rsi */ | |
1473 | i += push_opcode (&buf[i], "48 83 c6 18"); /* add $0x18,%rsi */ | |
1474 | ||
1475 | /* tpoint address may be 64-bit wide. */ | |
1476 | i += push_opcode (&buf[i], "48 bf"); /* movl <addr>,%rdi */ | |
1477 | memcpy (buf + i, &tpoint, 8); | |
1478 | i += 8; | |
1479 | append_insns (&buildaddr, i, buf); | |
1480 | ||
1481 | /* The collector function being in the shared library, may be | |
1482 | >31-bits away off the jump pad. */ | |
1483 | i = 0; | |
1484 | i += push_opcode (&buf[i], "48 b8"); /* mov $collector,%rax */ | |
1485 | memcpy (buf + i, &collector, 8); | |
1486 | i += 8; | |
1487 | i += push_opcode (&buf[i], "ff d0"); /* callq *%rax */ | |
1488 | append_insns (&buildaddr, i, buf); | |
1489 | ||
1490 | /* Clear the spin-lock. */ | |
1491 | i = 0; | |
1492 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ | |
1493 | i += push_opcode (&buf[i], "48 a3"); /* mov %rax, lockaddr */ | |
1494 | memcpy (buf + i, &lockaddr, 8); | |
1495 | i += 8; | |
1496 | append_insns (&buildaddr, i, buf); | |
1497 | ||
1498 | /* Remove stack that had been used for the collect_t object. */ | |
1499 | i = 0; | |
1500 | i += push_opcode (&buf[i], "48 83 c4 18"); /* add $0x18,%rsp */ | |
1501 | append_insns (&buildaddr, i, buf); | |
1502 | ||
1503 | /* Restore register state. */ | |
1504 | i = 0; | |
1505 | buf[i++] = 0x48; /* add $0x8,%rsp */ | |
1506 | buf[i++] = 0x83; | |
1507 | buf[i++] = 0xc4; | |
1508 | buf[i++] = 0x08; | |
1509 | buf[i++] = 0x9d; /* popfq */ | |
1510 | buf[i++] = 0x41; buf[i++] = 0x58; /* pop %r8 */ | |
1511 | buf[i++] = 0x41; buf[i++] = 0x59; /* pop %r9 */ | |
1512 | buf[i++] = 0x41; buf[i++] = 0x5a; /* pop %r10 */ | |
1513 | buf[i++] = 0x41; buf[i++] = 0x5b; /* pop %r11 */ | |
1514 | buf[i++] = 0x41; buf[i++] = 0x5c; /* pop %r12 */ | |
1515 | buf[i++] = 0x41; buf[i++] = 0x5d; /* pop %r13 */ | |
1516 | buf[i++] = 0x41; buf[i++] = 0x5e; /* pop %r14 */ | |
1517 | buf[i++] = 0x41; buf[i++] = 0x5f; /* pop %r15 */ | |
1518 | buf[i++] = 0x58; /* pop %rax */ | |
1519 | buf[i++] = 0x5b; /* pop %rbx */ | |
1520 | buf[i++] = 0x59; /* pop %rcx */ | |
1521 | buf[i++] = 0x5a; /* pop %rdx */ | |
1522 | buf[i++] = 0x5e; /* pop %rsi */ | |
1523 | buf[i++] = 0x5f; /* pop %rdi */ | |
1524 | buf[i++] = 0x5d; /* pop %rbp */ | |
1525 | buf[i++] = 0x5c; /* pop %rsp */ | |
1526 | append_insns (&buildaddr, i, buf); | |
1527 | ||
1528 | /* Now, adjust the original instruction to execute in the jump | |
1529 | pad. */ | |
1530 | *adjusted_insn_addr = buildaddr; | |
1531 | relocate_instruction (&buildaddr, tpaddr); | |
1532 | *adjusted_insn_addr_end = buildaddr; | |
1533 | ||
1534 | /* Finally, write a jump back to the program. */ | |
f4647387 YQ |
1535 | |
1536 | loffset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn)); | |
1537 | if (loffset > INT_MAX || loffset < INT_MIN) | |
1538 | { | |
1539 | sprintf (err, | |
1540 | "E.Jump back from jump pad too far from tracepoint " | |
1541 | "(offset 0x%" PRIx64 " > int32).", loffset); | |
1542 | return 1; | |
1543 | } | |
1544 | ||
1545 | offset = (int) loffset; | |
fa593d66 PA |
1546 | memcpy (buf, jump_insn, sizeof (jump_insn)); |
1547 | memcpy (buf + 1, &offset, 4); | |
1548 | append_insns (&buildaddr, sizeof (jump_insn), buf); | |
1549 | ||
1550 | /* The jump pad is now built. Wire in a jump to our jump pad. This | |
1551 | is always done last (by our caller actually), so that we can | |
1552 | install fast tracepoints with threads running. This relies on | |
1553 | the agent's atomic write support. */ | |
f4647387 YQ |
1554 | loffset = *jump_entry - (tpaddr + sizeof (jump_insn)); |
1555 | if (loffset > INT_MAX || loffset < INT_MIN) | |
1556 | { | |
1557 | sprintf (err, | |
1558 | "E.Jump pad too far from tracepoint " | |
1559 | "(offset 0x%" PRIx64 " > int32).", loffset); | |
1560 | return 1; | |
1561 | } | |
1562 | ||
1563 | offset = (int) loffset; | |
1564 | ||
fa593d66 PA |
1565 | memcpy (buf, jump_insn, sizeof (jump_insn)); |
1566 | memcpy (buf + 1, &offset, 4); | |
1567 | memcpy (jjump_pad_insn, buf, sizeof (jump_insn)); | |
1568 | *jjump_pad_insn_size = sizeof (jump_insn); | |
1569 | ||
1570 | /* Return the end address of our pad. */ | |
1571 | *jump_entry = buildaddr; | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | #endif /* __x86_64__ */ | |
1577 | ||
1578 | /* Build a jump pad that saves registers and calls a collection | |
1579 | function. Writes a jump instruction to the jump pad to | |
1580 | JJUMPAD_INSN. The caller is responsible to write it in at the | |
1581 | tracepoint address. */ | |
1582 | ||
1583 | static int | |
1584 | i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, | |
1585 | CORE_ADDR collector, | |
1586 | CORE_ADDR lockaddr, | |
1587 | ULONGEST orig_size, | |
1588 | CORE_ADDR *jump_entry, | |
405f8e94 SS |
1589 | CORE_ADDR *trampoline, |
1590 | ULONGEST *trampoline_size, | |
fa593d66 PA |
1591 | unsigned char *jjump_pad_insn, |
1592 | ULONGEST *jjump_pad_insn_size, | |
1593 | CORE_ADDR *adjusted_insn_addr, | |
405f8e94 SS |
1594 | CORE_ADDR *adjusted_insn_addr_end, |
1595 | char *err) | |
fa593d66 PA |
1596 | { |
1597 | unsigned char buf[0x100]; | |
1598 | int i, offset; | |
1599 | CORE_ADDR buildaddr = *jump_entry; | |
1600 | ||
1601 | /* Build the jump pad. */ | |
1602 | ||
1603 | /* First, do tracepoint data collection. Save registers. */ | |
1604 | i = 0; | |
1605 | buf[i++] = 0x60; /* pushad */ | |
1606 | buf[i++] = 0x68; /* push tpaddr aka $pc */ | |
1607 | *((int *)(buf + i)) = (int) tpaddr; | |
1608 | i += 4; | |
1609 | buf[i++] = 0x9c; /* pushf */ | |
1610 | buf[i++] = 0x1e; /* push %ds */ | |
1611 | buf[i++] = 0x06; /* push %es */ | |
1612 | buf[i++] = 0x0f; /* push %fs */ | |
1613 | buf[i++] = 0xa0; | |
1614 | buf[i++] = 0x0f; /* push %gs */ | |
1615 | buf[i++] = 0xa8; | |
1616 | buf[i++] = 0x16; /* push %ss */ | |
1617 | buf[i++] = 0x0e; /* push %cs */ | |
1618 | append_insns (&buildaddr, i, buf); | |
1619 | ||
1620 | /* Stack space for the collecting_t object. */ | |
1621 | i = 0; | |
1622 | i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */ | |
1623 | ||
1624 | /* Build the object. */ | |
1625 | i += push_opcode (&buf[i], "b8"); /* mov <tpoint>,%eax */ | |
1626 | memcpy (buf + i, &tpoint, 4); | |
1627 | i += 4; | |
1628 | i += push_opcode (&buf[i], "89 04 24"); /* mov %eax,(%esp) */ | |
1629 | ||
1630 | i += push_opcode (&buf[i], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */ | |
1631 | i += push_opcode (&buf[i], "89 44 24 04"); /* mov %eax,0x4(%esp) */ | |
1632 | append_insns (&buildaddr, i, buf); | |
1633 | ||
1634 | /* spin-lock. Note this is using cmpxchg, which leaves i386 behind. | |
1635 | If we cared for it, this could be using xchg alternatively. */ | |
1636 | ||
1637 | i = 0; | |
1638 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ | |
1639 | i += push_opcode (&buf[i], "f0 0f b1 25"); /* lock cmpxchg | |
1640 | %esp,<lockaddr> */ | |
1641 | memcpy (&buf[i], (void *) &lockaddr, 4); | |
1642 | i += 4; | |
1643 | i += push_opcode (&buf[i], "85 c0"); /* test %eax,%eax */ | |
1644 | i += push_opcode (&buf[i], "75 f2"); /* jne <again> */ | |
1645 | append_insns (&buildaddr, i, buf); | |
1646 | ||
1647 | ||
1648 | /* Set up arguments to the gdb_collect call. */ | |
1649 | i = 0; | |
1650 | i += push_opcode (&buf[i], "89 e0"); /* mov %esp,%eax */ | |
1651 | i += push_opcode (&buf[i], "83 c0 08"); /* add $0x08,%eax */ | |
1652 | i += push_opcode (&buf[i], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */ | |
1653 | append_insns (&buildaddr, i, buf); | |
1654 | ||
1655 | i = 0; | |
1656 | i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */ | |
1657 | append_insns (&buildaddr, i, buf); | |
1658 | ||
1659 | i = 0; | |
1660 | i += push_opcode (&buf[i], "c7 04 24"); /* movl <addr>,(%esp) */ | |
1661 | memcpy (&buf[i], (void *) &tpoint, 4); | |
1662 | i += 4; | |
1663 | append_insns (&buildaddr, i, buf); | |
1664 | ||
1665 | buf[0] = 0xe8; /* call <reladdr> */ | |
1666 | offset = collector - (buildaddr + sizeof (jump_insn)); | |
1667 | memcpy (buf + 1, &offset, 4); | |
1668 | append_insns (&buildaddr, 5, buf); | |
1669 | /* Clean up after the call. */ | |
1670 | buf[0] = 0x83; /* add $0x8,%esp */ | |
1671 | buf[1] = 0xc4; | |
1672 | buf[2] = 0x08; | |
1673 | append_insns (&buildaddr, 3, buf); | |
1674 | ||
1675 | ||
1676 | /* Clear the spin-lock. This would need the LOCK prefix on older | |
1677 | broken archs. */ | |
1678 | i = 0; | |
1679 | i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ | |
1680 | i += push_opcode (&buf[i], "a3"); /* mov %eax, lockaddr */ | |
1681 | memcpy (buf + i, &lockaddr, 4); | |
1682 | i += 4; | |
1683 | append_insns (&buildaddr, i, buf); | |
1684 | ||
1685 | ||
1686 | /* Remove stack that had been used for the collect_t object. */ | |
1687 | i = 0; | |
1688 | i += push_opcode (&buf[i], "83 c4 08"); /* add $0x08,%esp */ | |
1689 | append_insns (&buildaddr, i, buf); | |
1690 | ||
1691 | i = 0; | |
1692 | buf[i++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */ | |
1693 | buf[i++] = 0xc4; | |
1694 | buf[i++] = 0x04; | |
1695 | buf[i++] = 0x17; /* pop %ss */ | |
1696 | buf[i++] = 0x0f; /* pop %gs */ | |
1697 | buf[i++] = 0xa9; | |
1698 | buf[i++] = 0x0f; /* pop %fs */ | |
1699 | buf[i++] = 0xa1; | |
1700 | buf[i++] = 0x07; /* pop %es */ | |
405f8e94 | 1701 | buf[i++] = 0x1f; /* pop %ds */ |
fa593d66 PA |
1702 | buf[i++] = 0x9d; /* popf */ |
1703 | buf[i++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */ | |
1704 | buf[i++] = 0xc4; | |
1705 | buf[i++] = 0x04; | |
1706 | buf[i++] = 0x61; /* popad */ | |
1707 | append_insns (&buildaddr, i, buf); | |
1708 | ||
1709 | /* Now, adjust the original instruction to execute in the jump | |
1710 | pad. */ | |
1711 | *adjusted_insn_addr = buildaddr; | |
1712 | relocate_instruction (&buildaddr, tpaddr); | |
1713 | *adjusted_insn_addr_end = buildaddr; | |
1714 | ||
1715 | /* Write the jump back to the program. */ | |
1716 | offset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn)); | |
1717 | memcpy (buf, jump_insn, sizeof (jump_insn)); | |
1718 | memcpy (buf + 1, &offset, 4); | |
1719 | append_insns (&buildaddr, sizeof (jump_insn), buf); | |
1720 | ||
1721 | /* The jump pad is now built. Wire in a jump to our jump pad. This | |
1722 | is always done last (by our caller actually), so that we can | |
1723 | install fast tracepoints with threads running. This relies on | |
1724 | the agent's atomic write support. */ | |
405f8e94 SS |
1725 | if (orig_size == 4) |
1726 | { | |
1727 | /* Create a trampoline. */ | |
1728 | *trampoline_size = sizeof (jump_insn); | |
1729 | if (!claim_trampoline_space (*trampoline_size, trampoline)) | |
1730 | { | |
1731 | /* No trampoline space available. */ | |
1732 | strcpy (err, | |
1733 | "E.Cannot allocate trampoline space needed for fast " | |
1734 | "tracepoints on 4-byte instructions."); | |
1735 | return 1; | |
1736 | } | |
1737 | ||
1738 | offset = *jump_entry - (*trampoline + sizeof (jump_insn)); | |
1739 | memcpy (buf, jump_insn, sizeof (jump_insn)); | |
1740 | memcpy (buf + 1, &offset, 4); | |
1741 | write_inferior_memory (*trampoline, buf, sizeof (jump_insn)); | |
1742 | ||
1743 | /* Use a 16-bit relative jump instruction to jump to the trampoline. */ | |
1744 | offset = (*trampoline - (tpaddr + sizeof (small_jump_insn))) & 0xffff; | |
1745 | memcpy (buf, small_jump_insn, sizeof (small_jump_insn)); | |
1746 | memcpy (buf + 2, &offset, 2); | |
1747 | memcpy (jjump_pad_insn, buf, sizeof (small_jump_insn)); | |
1748 | *jjump_pad_insn_size = sizeof (small_jump_insn); | |
1749 | } | |
1750 | else | |
1751 | { | |
1752 | /* Else use a 32-bit relative jump instruction. */ | |
1753 | offset = *jump_entry - (tpaddr + sizeof (jump_insn)); | |
1754 | memcpy (buf, jump_insn, sizeof (jump_insn)); | |
1755 | memcpy (buf + 1, &offset, 4); | |
1756 | memcpy (jjump_pad_insn, buf, sizeof (jump_insn)); | |
1757 | *jjump_pad_insn_size = sizeof (jump_insn); | |
1758 | } | |
fa593d66 PA |
1759 | |
1760 | /* Return the end address of our pad. */ | |
1761 | *jump_entry = buildaddr; | |
1762 | ||
1763 | return 0; | |
1764 | } | |
1765 | ||
1766 | static int | |
1767 | x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, | |
1768 | CORE_ADDR collector, | |
1769 | CORE_ADDR lockaddr, | |
1770 | ULONGEST orig_size, | |
1771 | CORE_ADDR *jump_entry, | |
405f8e94 SS |
1772 | CORE_ADDR *trampoline, |
1773 | ULONGEST *trampoline_size, | |
fa593d66 PA |
1774 | unsigned char *jjump_pad_insn, |
1775 | ULONGEST *jjump_pad_insn_size, | |
1776 | CORE_ADDR *adjusted_insn_addr, | |
405f8e94 SS |
1777 | CORE_ADDR *adjusted_insn_addr_end, |
1778 | char *err) | |
fa593d66 PA |
1779 | { |
1780 | #ifdef __x86_64__ | |
1781 | if (register_size (0) == 8) | |
1782 | return amd64_install_fast_tracepoint_jump_pad (tpoint, tpaddr, | |
1783 | collector, lockaddr, | |
1784 | orig_size, jump_entry, | |
405f8e94 | 1785 | trampoline, trampoline_size, |
fa593d66 PA |
1786 | jjump_pad_insn, |
1787 | jjump_pad_insn_size, | |
1788 | adjusted_insn_addr, | |
405f8e94 SS |
1789 | adjusted_insn_addr_end, |
1790 | err); | |
fa593d66 PA |
1791 | #endif |
1792 | ||
1793 | return i386_install_fast_tracepoint_jump_pad (tpoint, tpaddr, | |
1794 | collector, lockaddr, | |
1795 | orig_size, jump_entry, | |
405f8e94 | 1796 | trampoline, trampoline_size, |
fa593d66 PA |
1797 | jjump_pad_insn, |
1798 | jjump_pad_insn_size, | |
1799 | adjusted_insn_addr, | |
405f8e94 SS |
1800 | adjusted_insn_addr_end, |
1801 | err); | |
1802 | } | |
1803 | ||
1804 | /* Return the minimum instruction length for fast tracepoints on x86/x86-64 | |
1805 | architectures. */ | |
1806 | ||
1807 | static int | |
1808 | x86_get_min_fast_tracepoint_insn_len (void) | |
1809 | { | |
1810 | static int warned_about_fast_tracepoints = 0; | |
1811 | ||
1812 | #ifdef __x86_64__ | |
1813 | /* On x86-64, 5-byte jump instructions with a 4-byte offset are always | |
1814 | used for fast tracepoints. */ | |
1815 | if (register_size (0) == 8) | |
1816 | return 5; | |
1817 | #endif | |
1818 | ||
58b4daa5 | 1819 | if (agent_loaded_p ()) |
405f8e94 SS |
1820 | { |
1821 | char errbuf[IPA_BUFSIZ]; | |
1822 | ||
1823 | errbuf[0] = '\0'; | |
1824 | ||
1825 | /* On x86, if trampolines are available, then 4-byte jump instructions | |
1826 | with a 2-byte offset may be used, otherwise 5-byte jump instructions | |
1827 | with a 4-byte offset are used instead. */ | |
1828 | if (have_fast_tracepoint_trampoline_buffer (errbuf)) | |
1829 | return 4; | |
1830 | else | |
1831 | { | |
1832 | /* GDB has no channel to explain to user why a shorter fast | |
1833 | tracepoint is not possible, but at least make GDBserver | |
1834 | mention that something has gone awry. */ | |
1835 | if (!warned_about_fast_tracepoints) | |
1836 | { | |
1837 | warning ("4-byte fast tracepoints not available; %s\n", errbuf); | |
1838 | warned_about_fast_tracepoints = 1; | |
1839 | } | |
1840 | return 5; | |
1841 | } | |
1842 | } | |
1843 | else | |
1844 | { | |
1845 | /* Indicate that the minimum length is currently unknown since the IPA | |
1846 | has not loaded yet. */ | |
1847 | return 0; | |
1848 | } | |
fa593d66 PA |
1849 | } |
1850 | ||
6a271cae PA |
1851 | static void |
1852 | add_insns (unsigned char *start, int len) | |
1853 | { | |
1854 | CORE_ADDR buildaddr = current_insn_ptr; | |
1855 | ||
1856 | if (debug_threads) | |
1857 | fprintf (stderr, "Adding %d bytes of insn at %s\n", | |
1858 | len, paddress (buildaddr)); | |
1859 | ||
1860 | append_insns (&buildaddr, len, start); | |
1861 | current_insn_ptr = buildaddr; | |
1862 | } | |
1863 | ||
6a271cae PA |
1864 | /* Our general strategy for emitting code is to avoid specifying raw |
1865 | bytes whenever possible, and instead copy a block of inline asm | |
1866 | that is embedded in the function. This is a little messy, because | |
1867 | we need to keep the compiler from discarding what looks like dead | |
1868 | code, plus suppress various warnings. */ | |
1869 | ||
9e4344e5 PA |
1870 | #define EMIT_ASM(NAME, INSNS) \ |
1871 | do \ | |
1872 | { \ | |
1873 | extern unsigned char start_ ## NAME, end_ ## NAME; \ | |
1874 | add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \ | |
493e2a69 | 1875 | __asm__ ("jmp end_" #NAME "\n" \ |
9e4344e5 PA |
1876 | "\t" "start_" #NAME ":" \ |
1877 | "\t" INSNS "\n" \ | |
1878 | "\t" "end_" #NAME ":"); \ | |
1879 | } while (0) | |
6a271cae PA |
1880 | |
1881 | #ifdef __x86_64__ | |
1882 | ||
1883 | #define EMIT_ASM32(NAME,INSNS) \ | |
9e4344e5 PA |
1884 | do \ |
1885 | { \ | |
1886 | extern unsigned char start_ ## NAME, end_ ## NAME; \ | |
1887 | add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \ | |
1888 | __asm__ (".code32\n" \ | |
1889 | "\t" "jmp end_" #NAME "\n" \ | |
1890 | "\t" "start_" #NAME ":\n" \ | |
1891 | "\t" INSNS "\n" \ | |
1892 | "\t" "end_" #NAME ":\n" \ | |
1893 | ".code64\n"); \ | |
1894 | } while (0) | |
6a271cae PA |
1895 | |
1896 | #else | |
1897 | ||
1898 | #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS) | |
1899 | ||
1900 | #endif | |
1901 | ||
1902 | #ifdef __x86_64__ | |
1903 | ||
1904 | static void | |
1905 | amd64_emit_prologue (void) | |
1906 | { | |
1907 | EMIT_ASM (amd64_prologue, | |
1908 | "pushq %rbp\n\t" | |
1909 | "movq %rsp,%rbp\n\t" | |
1910 | "sub $0x20,%rsp\n\t" | |
1911 | "movq %rdi,-8(%rbp)\n\t" | |
1912 | "movq %rsi,-16(%rbp)"); | |
1913 | } | |
1914 | ||
1915 | ||
1916 | static void | |
1917 | amd64_emit_epilogue (void) | |
1918 | { | |
1919 | EMIT_ASM (amd64_epilogue, | |
1920 | "movq -16(%rbp),%rdi\n\t" | |
1921 | "movq %rax,(%rdi)\n\t" | |
1922 | "xor %rax,%rax\n\t" | |
1923 | "leave\n\t" | |
1924 | "ret"); | |
1925 | } | |
1926 | ||
1927 | static void | |
1928 | amd64_emit_add (void) | |
1929 | { | |
1930 | EMIT_ASM (amd64_add, | |
1931 | "add (%rsp),%rax\n\t" | |
1932 | "lea 0x8(%rsp),%rsp"); | |
1933 | } | |
1934 | ||
1935 | static void | |
1936 | amd64_emit_sub (void) | |
1937 | { | |
1938 | EMIT_ASM (amd64_sub, | |
1939 | "sub %rax,(%rsp)\n\t" | |
1940 | "pop %rax"); | |
1941 | } | |
1942 | ||
1943 | static void | |
1944 | amd64_emit_mul (void) | |
1945 | { | |
1946 | emit_error = 1; | |
1947 | } | |
1948 | ||
1949 | static void | |
1950 | amd64_emit_lsh (void) | |
1951 | { | |
1952 | emit_error = 1; | |
1953 | } | |
1954 | ||
1955 | static void | |
1956 | amd64_emit_rsh_signed (void) | |
1957 | { | |
1958 | emit_error = 1; | |
1959 | } | |
1960 | ||
1961 | static void | |
1962 | amd64_emit_rsh_unsigned (void) | |
1963 | { | |
1964 | emit_error = 1; | |
1965 | } | |
1966 | ||
1967 | static void | |
1968 | amd64_emit_ext (int arg) | |
1969 | { | |
1970 | switch (arg) | |
1971 | { | |
1972 | case 8: | |
1973 | EMIT_ASM (amd64_ext_8, | |
1974 | "cbtw\n\t" | |
1975 | "cwtl\n\t" | |
1976 | "cltq"); | |
1977 | break; | |
1978 | case 16: | |
1979 | EMIT_ASM (amd64_ext_16, | |
1980 | "cwtl\n\t" | |
1981 | "cltq"); | |
1982 | break; | |
1983 | case 32: | |
1984 | EMIT_ASM (amd64_ext_32, | |
1985 | "cltq"); | |
1986 | break; | |
1987 | default: | |
1988 | emit_error = 1; | |
1989 | } | |
1990 | } | |
1991 | ||
1992 | static void | |
1993 | amd64_emit_log_not (void) | |
1994 | { | |
1995 | EMIT_ASM (amd64_log_not, | |
1996 | "test %rax,%rax\n\t" | |
1997 | "sete %cl\n\t" | |
1998 | "movzbq %cl,%rax"); | |
1999 | } | |
2000 | ||
2001 | static void | |
2002 | amd64_emit_bit_and (void) | |
2003 | { | |
2004 | EMIT_ASM (amd64_and, | |
2005 | "and (%rsp),%rax\n\t" | |
2006 | "lea 0x8(%rsp),%rsp"); | |
2007 | } | |
2008 | ||
2009 | static void | |
2010 | amd64_emit_bit_or (void) | |
2011 | { | |
2012 | EMIT_ASM (amd64_or, | |
2013 | "or (%rsp),%rax\n\t" | |
2014 | "lea 0x8(%rsp),%rsp"); | |
2015 | } | |
2016 | ||
2017 | static void | |
2018 | amd64_emit_bit_xor (void) | |
2019 | { | |
2020 | EMIT_ASM (amd64_xor, | |
2021 | "xor (%rsp),%rax\n\t" | |
2022 | "lea 0x8(%rsp),%rsp"); | |
2023 | } | |
2024 | ||
2025 | static void | |
2026 | amd64_emit_bit_not (void) | |
2027 | { | |
2028 | EMIT_ASM (amd64_bit_not, | |
2029 | "xorq $0xffffffffffffffff,%rax"); | |
2030 | } | |
2031 | ||
2032 | static void | |
2033 | amd64_emit_equal (void) | |
2034 | { | |
2035 | EMIT_ASM (amd64_equal, | |
2036 | "cmp %rax,(%rsp)\n\t" | |
2037 | "je .Lamd64_equal_true\n\t" | |
2038 | "xor %rax,%rax\n\t" | |
2039 | "jmp .Lamd64_equal_end\n\t" | |
2040 | ".Lamd64_equal_true:\n\t" | |
2041 | "mov $0x1,%rax\n\t" | |
2042 | ".Lamd64_equal_end:\n\t" | |
2043 | "lea 0x8(%rsp),%rsp"); | |
2044 | } | |
2045 | ||
2046 | static void | |
2047 | amd64_emit_less_signed (void) | |
2048 | { | |
2049 | EMIT_ASM (amd64_less_signed, | |
2050 | "cmp %rax,(%rsp)\n\t" | |
2051 | "jl .Lamd64_less_signed_true\n\t" | |
2052 | "xor %rax,%rax\n\t" | |
2053 | "jmp .Lamd64_less_signed_end\n\t" | |
2054 | ".Lamd64_less_signed_true:\n\t" | |
2055 | "mov $1,%rax\n\t" | |
2056 | ".Lamd64_less_signed_end:\n\t" | |
2057 | "lea 0x8(%rsp),%rsp"); | |
2058 | } | |
2059 | ||
2060 | static void | |
2061 | amd64_emit_less_unsigned (void) | |
2062 | { | |
2063 | EMIT_ASM (amd64_less_unsigned, | |
2064 | "cmp %rax,(%rsp)\n\t" | |
2065 | "jb .Lamd64_less_unsigned_true\n\t" | |
2066 | "xor %rax,%rax\n\t" | |
2067 | "jmp .Lamd64_less_unsigned_end\n\t" | |
2068 | ".Lamd64_less_unsigned_true:\n\t" | |
2069 | "mov $1,%rax\n\t" | |
2070 | ".Lamd64_less_unsigned_end:\n\t" | |
2071 | "lea 0x8(%rsp),%rsp"); | |
2072 | } | |
2073 | ||
2074 | static void | |
2075 | amd64_emit_ref (int size) | |
2076 | { | |
2077 | switch (size) | |
2078 | { | |
2079 | case 1: | |
2080 | EMIT_ASM (amd64_ref1, | |
2081 | "movb (%rax),%al"); | |
2082 | break; | |
2083 | case 2: | |
2084 | EMIT_ASM (amd64_ref2, | |
2085 | "movw (%rax),%ax"); | |
2086 | break; | |
2087 | case 4: | |
2088 | EMIT_ASM (amd64_ref4, | |
2089 | "movl (%rax),%eax"); | |
2090 | break; | |
2091 | case 8: | |
2092 | EMIT_ASM (amd64_ref8, | |
2093 | "movq (%rax),%rax"); | |
2094 | break; | |
2095 | } | |
2096 | } | |
2097 | ||
2098 | static void | |
2099 | amd64_emit_if_goto (int *offset_p, int *size_p) | |
2100 | { | |
2101 | EMIT_ASM (amd64_if_goto, | |
2102 | "mov %rax,%rcx\n\t" | |
2103 | "pop %rax\n\t" | |
2104 | "cmp $0,%rcx\n\t" | |
2105 | ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0"); | |
2106 | if (offset_p) | |
2107 | *offset_p = 10; | |
2108 | if (size_p) | |
2109 | *size_p = 4; | |
2110 | } | |
2111 | ||
2112 | static void | |
2113 | amd64_emit_goto (int *offset_p, int *size_p) | |
2114 | { | |
2115 | EMIT_ASM (amd64_goto, | |
2116 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0"); | |
2117 | if (offset_p) | |
2118 | *offset_p = 1; | |
2119 | if (size_p) | |
2120 | *size_p = 4; | |
2121 | } | |
2122 | ||
2123 | static void | |
2124 | amd64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) | |
2125 | { | |
2126 | int diff = (to - (from + size)); | |
2127 | unsigned char buf[sizeof (int)]; | |
2128 | ||
2129 | if (size != 4) | |
2130 | { | |
2131 | emit_error = 1; | |
2132 | return; | |
2133 | } | |
2134 | ||
2135 | memcpy (buf, &diff, sizeof (int)); | |
2136 | write_inferior_memory (from, buf, sizeof (int)); | |
2137 | } | |
2138 | ||
2139 | static void | |
4e29fb54 | 2140 | amd64_emit_const (LONGEST num) |
6a271cae PA |
2141 | { |
2142 | unsigned char buf[16]; | |
2143 | int i; | |
2144 | CORE_ADDR buildaddr = current_insn_ptr; | |
2145 | ||
2146 | i = 0; | |
2147 | buf[i++] = 0x48; buf[i++] = 0xb8; /* mov $<n>,%rax */ | |
b00ad6ff | 2148 | memcpy (&buf[i], &num, sizeof (num)); |
6a271cae PA |
2149 | i += 8; |
2150 | append_insns (&buildaddr, i, buf); | |
2151 | current_insn_ptr = buildaddr; | |
2152 | } | |
2153 | ||
2154 | static void | |
2155 | amd64_emit_call (CORE_ADDR fn) | |
2156 | { | |
2157 | unsigned char buf[16]; | |
2158 | int i; | |
2159 | CORE_ADDR buildaddr; | |
4e29fb54 | 2160 | LONGEST offset64; |
6a271cae PA |
2161 | |
2162 | /* The destination function being in the shared library, may be | |
2163 | >31-bits away off the compiled code pad. */ | |
2164 | ||
2165 | buildaddr = current_insn_ptr; | |
2166 | ||
2167 | offset64 = fn - (buildaddr + 1 /* call op */ + 4 /* 32-bit offset */); | |
2168 | ||
2169 | i = 0; | |
2170 | ||
2171 | if (offset64 > INT_MAX || offset64 < INT_MIN) | |
2172 | { | |
2173 | /* Offset is too large for a call. Use callq, but that requires | |
2174 | a register, so avoid it if possible. Use r10, since it is | |
2175 | call-clobbered, we don't have to push/pop it. */ | |
2176 | buf[i++] = 0x48; /* mov $fn,%r10 */ | |
2177 | buf[i++] = 0xba; | |
2178 | memcpy (buf + i, &fn, 8); | |
2179 | i += 8; | |
2180 | buf[i++] = 0xff; /* callq *%r10 */ | |
2181 | buf[i++] = 0xd2; | |
2182 | } | |
2183 | else | |
2184 | { | |
2185 | int offset32 = offset64; /* we know we can't overflow here. */ | |
2186 | memcpy (buf + i, &offset32, 4); | |
2187 | i += 4; | |
2188 | } | |
2189 | ||
2190 | append_insns (&buildaddr, i, buf); | |
2191 | current_insn_ptr = buildaddr; | |
2192 | } | |
2193 | ||
2194 | static void | |
2195 | amd64_emit_reg (int reg) | |
2196 | { | |
2197 | unsigned char buf[16]; | |
2198 | int i; | |
2199 | CORE_ADDR buildaddr; | |
2200 | ||
2201 | /* Assume raw_regs is still in %rdi. */ | |
2202 | buildaddr = current_insn_ptr; | |
2203 | i = 0; | |
2204 | buf[i++] = 0xbe; /* mov $<n>,%esi */ | |
b00ad6ff | 2205 | memcpy (&buf[i], ®, sizeof (reg)); |
6a271cae PA |
2206 | i += 4; |
2207 | append_insns (&buildaddr, i, buf); | |
2208 | current_insn_ptr = buildaddr; | |
2209 | amd64_emit_call (get_raw_reg_func_addr ()); | |
2210 | } | |
2211 | ||
2212 | static void | |
2213 | amd64_emit_pop (void) | |
2214 | { | |
2215 | EMIT_ASM (amd64_pop, | |
2216 | "pop %rax"); | |
2217 | } | |
2218 | ||
2219 | static void | |
2220 | amd64_emit_stack_flush (void) | |
2221 | { | |
2222 | EMIT_ASM (amd64_stack_flush, | |
2223 | "push %rax"); | |
2224 | } | |
2225 | ||
2226 | static void | |
2227 | amd64_emit_zero_ext (int arg) | |
2228 | { | |
2229 | switch (arg) | |
2230 | { | |
2231 | case 8: | |
2232 | EMIT_ASM (amd64_zero_ext_8, | |
2233 | "and $0xff,%rax"); | |
2234 | break; | |
2235 | case 16: | |
2236 | EMIT_ASM (amd64_zero_ext_16, | |
2237 | "and $0xffff,%rax"); | |
2238 | break; | |
2239 | case 32: | |
2240 | EMIT_ASM (amd64_zero_ext_32, | |
2241 | "mov $0xffffffff,%rcx\n\t" | |
2242 | "and %rcx,%rax"); | |
2243 | break; | |
2244 | default: | |
2245 | emit_error = 1; | |
2246 | } | |
2247 | } | |
2248 | ||
2249 | static void | |
2250 | amd64_emit_swap (void) | |
2251 | { | |
2252 | EMIT_ASM (amd64_swap, | |
2253 | "mov %rax,%rcx\n\t" | |
2254 | "pop %rax\n\t" | |
2255 | "push %rcx"); | |
2256 | } | |
2257 | ||
2258 | static void | |
2259 | amd64_emit_stack_adjust (int n) | |
2260 | { | |
2261 | unsigned char buf[16]; | |
2262 | int i; | |
2263 | CORE_ADDR buildaddr = current_insn_ptr; | |
2264 | ||
2265 | i = 0; | |
2266 | buf[i++] = 0x48; /* lea $<n>(%rsp),%rsp */ | |
2267 | buf[i++] = 0x8d; | |
2268 | buf[i++] = 0x64; | |
2269 | buf[i++] = 0x24; | |
2270 | /* This only handles adjustments up to 16, but we don't expect any more. */ | |
2271 | buf[i++] = n * 8; | |
2272 | append_insns (&buildaddr, i, buf); | |
2273 | current_insn_ptr = buildaddr; | |
2274 | } | |
2275 | ||
2276 | /* FN's prototype is `LONGEST(*fn)(int)'. */ | |
2277 | ||
2278 | static void | |
2279 | amd64_emit_int_call_1 (CORE_ADDR fn, int arg1) | |
2280 | { | |
2281 | unsigned char buf[16]; | |
2282 | int i; | |
2283 | CORE_ADDR buildaddr; | |
2284 | ||
2285 | buildaddr = current_insn_ptr; | |
2286 | i = 0; | |
2287 | buf[i++] = 0xbf; /* movl $<n>,%edi */ | |
b00ad6ff | 2288 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
6a271cae PA |
2289 | i += 4; |
2290 | append_insns (&buildaddr, i, buf); | |
2291 | current_insn_ptr = buildaddr; | |
2292 | amd64_emit_call (fn); | |
2293 | } | |
2294 | ||
4e29fb54 | 2295 | /* FN's prototype is `void(*fn)(int,LONGEST)'. */ |
6a271cae PA |
2296 | |
2297 | static void | |
2298 | amd64_emit_void_call_2 (CORE_ADDR fn, int arg1) | |
2299 | { | |
2300 | unsigned char buf[16]; | |
2301 | int i; | |
2302 | CORE_ADDR buildaddr; | |
2303 | ||
2304 | buildaddr = current_insn_ptr; | |
2305 | i = 0; | |
2306 | buf[i++] = 0xbf; /* movl $<n>,%edi */ | |
b00ad6ff | 2307 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
6a271cae PA |
2308 | i += 4; |
2309 | append_insns (&buildaddr, i, buf); | |
2310 | current_insn_ptr = buildaddr; | |
2311 | EMIT_ASM (amd64_void_call_2_a, | |
2312 | /* Save away a copy of the stack top. */ | |
2313 | "push %rax\n\t" | |
2314 | /* Also pass top as the second argument. */ | |
2315 | "mov %rax,%rsi"); | |
2316 | amd64_emit_call (fn); | |
2317 | EMIT_ASM (amd64_void_call_2_b, | |
2318 | /* Restore the stack top, %rax may have been trashed. */ | |
2319 | "pop %rax"); | |
2320 | } | |
2321 | ||
6b9801d4 SS |
2322 | void |
2323 | amd64_emit_eq_goto (int *offset_p, int *size_p) | |
2324 | { | |
2325 | EMIT_ASM (amd64_eq, | |
2326 | "cmp %rax,(%rsp)\n\t" | |
2327 | "jne .Lamd64_eq_fallthru\n\t" | |
2328 | "lea 0x8(%rsp),%rsp\n\t" | |
2329 | "pop %rax\n\t" | |
2330 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2331 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2332 | ".Lamd64_eq_fallthru:\n\t" | |
2333 | "lea 0x8(%rsp),%rsp\n\t" | |
2334 | "pop %rax"); | |
2335 | ||
2336 | if (offset_p) | |
2337 | *offset_p = 13; | |
2338 | if (size_p) | |
2339 | *size_p = 4; | |
2340 | } | |
2341 | ||
2342 | void | |
2343 | amd64_emit_ne_goto (int *offset_p, int *size_p) | |
2344 | { | |
2345 | EMIT_ASM (amd64_ne, | |
2346 | "cmp %rax,(%rsp)\n\t" | |
2347 | "je .Lamd64_ne_fallthru\n\t" | |
2348 | "lea 0x8(%rsp),%rsp\n\t" | |
2349 | "pop %rax\n\t" | |
2350 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2351 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2352 | ".Lamd64_ne_fallthru:\n\t" | |
2353 | "lea 0x8(%rsp),%rsp\n\t" | |
2354 | "pop %rax"); | |
2355 | ||
2356 | if (offset_p) | |
2357 | *offset_p = 13; | |
2358 | if (size_p) | |
2359 | *size_p = 4; | |
2360 | } | |
2361 | ||
2362 | void | |
2363 | amd64_emit_lt_goto (int *offset_p, int *size_p) | |
2364 | { | |
2365 | EMIT_ASM (amd64_lt, | |
2366 | "cmp %rax,(%rsp)\n\t" | |
2367 | "jnl .Lamd64_lt_fallthru\n\t" | |
2368 | "lea 0x8(%rsp),%rsp\n\t" | |
2369 | "pop %rax\n\t" | |
2370 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2371 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2372 | ".Lamd64_lt_fallthru:\n\t" | |
2373 | "lea 0x8(%rsp),%rsp\n\t" | |
2374 | "pop %rax"); | |
2375 | ||
2376 | if (offset_p) | |
2377 | *offset_p = 13; | |
2378 | if (size_p) | |
2379 | *size_p = 4; | |
2380 | } | |
2381 | ||
2382 | void | |
2383 | amd64_emit_le_goto (int *offset_p, int *size_p) | |
2384 | { | |
2385 | EMIT_ASM (amd64_le, | |
2386 | "cmp %rax,(%rsp)\n\t" | |
2387 | "jnle .Lamd64_le_fallthru\n\t" | |
2388 | "lea 0x8(%rsp),%rsp\n\t" | |
2389 | "pop %rax\n\t" | |
2390 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2391 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2392 | ".Lamd64_le_fallthru:\n\t" | |
2393 | "lea 0x8(%rsp),%rsp\n\t" | |
2394 | "pop %rax"); | |
2395 | ||
2396 | if (offset_p) | |
2397 | *offset_p = 13; | |
2398 | if (size_p) | |
2399 | *size_p = 4; | |
2400 | } | |
2401 | ||
2402 | void | |
2403 | amd64_emit_gt_goto (int *offset_p, int *size_p) | |
2404 | { | |
2405 | EMIT_ASM (amd64_gt, | |
2406 | "cmp %rax,(%rsp)\n\t" | |
2407 | "jng .Lamd64_gt_fallthru\n\t" | |
2408 | "lea 0x8(%rsp),%rsp\n\t" | |
2409 | "pop %rax\n\t" | |
2410 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2411 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2412 | ".Lamd64_gt_fallthru:\n\t" | |
2413 | "lea 0x8(%rsp),%rsp\n\t" | |
2414 | "pop %rax"); | |
2415 | ||
2416 | if (offset_p) | |
2417 | *offset_p = 13; | |
2418 | if (size_p) | |
2419 | *size_p = 4; | |
2420 | } | |
2421 | ||
2422 | void | |
2423 | amd64_emit_ge_goto (int *offset_p, int *size_p) | |
2424 | { | |
2425 | EMIT_ASM (amd64_ge, | |
2426 | "cmp %rax,(%rsp)\n\t" | |
2427 | "jnge .Lamd64_ge_fallthru\n\t" | |
2428 | ".Lamd64_ge_jump:\n\t" | |
2429 | "lea 0x8(%rsp),%rsp\n\t" | |
2430 | "pop %rax\n\t" | |
2431 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2432 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2433 | ".Lamd64_ge_fallthru:\n\t" | |
2434 | "lea 0x8(%rsp),%rsp\n\t" | |
2435 | "pop %rax"); | |
2436 | ||
2437 | if (offset_p) | |
2438 | *offset_p = 13; | |
2439 | if (size_p) | |
2440 | *size_p = 4; | |
2441 | } | |
2442 | ||
6a271cae PA |
2443 | struct emit_ops amd64_emit_ops = |
2444 | { | |
2445 | amd64_emit_prologue, | |
2446 | amd64_emit_epilogue, | |
2447 | amd64_emit_add, | |
2448 | amd64_emit_sub, | |
2449 | amd64_emit_mul, | |
2450 | amd64_emit_lsh, | |
2451 | amd64_emit_rsh_signed, | |
2452 | amd64_emit_rsh_unsigned, | |
2453 | amd64_emit_ext, | |
2454 | amd64_emit_log_not, | |
2455 | amd64_emit_bit_and, | |
2456 | amd64_emit_bit_or, | |
2457 | amd64_emit_bit_xor, | |
2458 | amd64_emit_bit_not, | |
2459 | amd64_emit_equal, | |
2460 | amd64_emit_less_signed, | |
2461 | amd64_emit_less_unsigned, | |
2462 | amd64_emit_ref, | |
2463 | amd64_emit_if_goto, | |
2464 | amd64_emit_goto, | |
2465 | amd64_write_goto_address, | |
2466 | amd64_emit_const, | |
2467 | amd64_emit_call, | |
2468 | amd64_emit_reg, | |
2469 | amd64_emit_pop, | |
2470 | amd64_emit_stack_flush, | |
2471 | amd64_emit_zero_ext, | |
2472 | amd64_emit_swap, | |
2473 | amd64_emit_stack_adjust, | |
2474 | amd64_emit_int_call_1, | |
6b9801d4 SS |
2475 | amd64_emit_void_call_2, |
2476 | amd64_emit_eq_goto, | |
2477 | amd64_emit_ne_goto, | |
2478 | amd64_emit_lt_goto, | |
2479 | amd64_emit_le_goto, | |
2480 | amd64_emit_gt_goto, | |
2481 | amd64_emit_ge_goto | |
6a271cae PA |
2482 | }; |
2483 | ||
2484 | #endif /* __x86_64__ */ | |
2485 | ||
2486 | static void | |
2487 | i386_emit_prologue (void) | |
2488 | { | |
2489 | EMIT_ASM32 (i386_prologue, | |
2490 | "push %ebp\n\t" | |
bf15cbda SS |
2491 | "mov %esp,%ebp\n\t" |
2492 | "push %ebx"); | |
6a271cae PA |
2493 | /* At this point, the raw regs base address is at 8(%ebp), and the |
2494 | value pointer is at 12(%ebp). */ | |
2495 | } | |
2496 | ||
2497 | static void | |
2498 | i386_emit_epilogue (void) | |
2499 | { | |
2500 | EMIT_ASM32 (i386_epilogue, | |
2501 | "mov 12(%ebp),%ecx\n\t" | |
2502 | "mov %eax,(%ecx)\n\t" | |
2503 | "mov %ebx,0x4(%ecx)\n\t" | |
2504 | "xor %eax,%eax\n\t" | |
bf15cbda | 2505 | "pop %ebx\n\t" |
6a271cae PA |
2506 | "pop %ebp\n\t" |
2507 | "ret"); | |
2508 | } | |
2509 | ||
2510 | static void | |
2511 | i386_emit_add (void) | |
2512 | { | |
2513 | EMIT_ASM32 (i386_add, | |
2514 | "add (%esp),%eax\n\t" | |
2515 | "adc 0x4(%esp),%ebx\n\t" | |
2516 | "lea 0x8(%esp),%esp"); | |
2517 | } | |
2518 | ||
2519 | static void | |
2520 | i386_emit_sub (void) | |
2521 | { | |
2522 | EMIT_ASM32 (i386_sub, | |
2523 | "subl %eax,(%esp)\n\t" | |
2524 | "sbbl %ebx,4(%esp)\n\t" | |
2525 | "pop %eax\n\t" | |
2526 | "pop %ebx\n\t"); | |
2527 | } | |
2528 | ||
2529 | static void | |
2530 | i386_emit_mul (void) | |
2531 | { | |
2532 | emit_error = 1; | |
2533 | } | |
2534 | ||
2535 | static void | |
2536 | i386_emit_lsh (void) | |
2537 | { | |
2538 | emit_error = 1; | |
2539 | } | |
2540 | ||
2541 | static void | |
2542 | i386_emit_rsh_signed (void) | |
2543 | { | |
2544 | emit_error = 1; | |
2545 | } | |
2546 | ||
2547 | static void | |
2548 | i386_emit_rsh_unsigned (void) | |
2549 | { | |
2550 | emit_error = 1; | |
2551 | } | |
2552 | ||
2553 | static void | |
2554 | i386_emit_ext (int arg) | |
2555 | { | |
2556 | switch (arg) | |
2557 | { | |
2558 | case 8: | |
2559 | EMIT_ASM32 (i386_ext_8, | |
2560 | "cbtw\n\t" | |
2561 | "cwtl\n\t" | |
2562 | "movl %eax,%ebx\n\t" | |
2563 | "sarl $31,%ebx"); | |
2564 | break; | |
2565 | case 16: | |
2566 | EMIT_ASM32 (i386_ext_16, | |
2567 | "cwtl\n\t" | |
2568 | "movl %eax,%ebx\n\t" | |
2569 | "sarl $31,%ebx"); | |
2570 | break; | |
2571 | case 32: | |
2572 | EMIT_ASM32 (i386_ext_32, | |
2573 | "movl %eax,%ebx\n\t" | |
2574 | "sarl $31,%ebx"); | |
2575 | break; | |
2576 | default: | |
2577 | emit_error = 1; | |
2578 | } | |
2579 | } | |
2580 | ||
2581 | static void | |
2582 | i386_emit_log_not (void) | |
2583 | { | |
2584 | EMIT_ASM32 (i386_log_not, | |
2585 | "or %ebx,%eax\n\t" | |
2586 | "test %eax,%eax\n\t" | |
2587 | "sete %cl\n\t" | |
2588 | "xor %ebx,%ebx\n\t" | |
2589 | "movzbl %cl,%eax"); | |
2590 | } | |
2591 | ||
2592 | static void | |
2593 | i386_emit_bit_and (void) | |
2594 | { | |
2595 | EMIT_ASM32 (i386_and, | |
2596 | "and (%esp),%eax\n\t" | |
2597 | "and 0x4(%esp),%ebx\n\t" | |
2598 | "lea 0x8(%esp),%esp"); | |
2599 | } | |
2600 | ||
2601 | static void | |
2602 | i386_emit_bit_or (void) | |
2603 | { | |
2604 | EMIT_ASM32 (i386_or, | |
2605 | "or (%esp),%eax\n\t" | |
2606 | "or 0x4(%esp),%ebx\n\t" | |
2607 | "lea 0x8(%esp),%esp"); | |
2608 | } | |
2609 | ||
2610 | static void | |
2611 | i386_emit_bit_xor (void) | |
2612 | { | |
2613 | EMIT_ASM32 (i386_xor, | |
2614 | "xor (%esp),%eax\n\t" | |
2615 | "xor 0x4(%esp),%ebx\n\t" | |
2616 | "lea 0x8(%esp),%esp"); | |
2617 | } | |
2618 | ||
2619 | static void | |
2620 | i386_emit_bit_not (void) | |
2621 | { | |
2622 | EMIT_ASM32 (i386_bit_not, | |
2623 | "xor $0xffffffff,%eax\n\t" | |
2624 | "xor $0xffffffff,%ebx\n\t"); | |
2625 | } | |
2626 | ||
2627 | static void | |
2628 | i386_emit_equal (void) | |
2629 | { | |
2630 | EMIT_ASM32 (i386_equal, | |
2631 | "cmpl %ebx,4(%esp)\n\t" | |
2632 | "jne .Li386_equal_false\n\t" | |
2633 | "cmpl %eax,(%esp)\n\t" | |
2634 | "je .Li386_equal_true\n\t" | |
2635 | ".Li386_equal_false:\n\t" | |
2636 | "xor %eax,%eax\n\t" | |
2637 | "jmp .Li386_equal_end\n\t" | |
2638 | ".Li386_equal_true:\n\t" | |
2639 | "mov $1,%eax\n\t" | |
2640 | ".Li386_equal_end:\n\t" | |
2641 | "xor %ebx,%ebx\n\t" | |
2642 | "lea 0x8(%esp),%esp"); | |
2643 | } | |
2644 | ||
2645 | static void | |
2646 | i386_emit_less_signed (void) | |
2647 | { | |
2648 | EMIT_ASM32 (i386_less_signed, | |
2649 | "cmpl %ebx,4(%esp)\n\t" | |
2650 | "jl .Li386_less_signed_true\n\t" | |
2651 | "jne .Li386_less_signed_false\n\t" | |
2652 | "cmpl %eax,(%esp)\n\t" | |
2653 | "jl .Li386_less_signed_true\n\t" | |
2654 | ".Li386_less_signed_false:\n\t" | |
2655 | "xor %eax,%eax\n\t" | |
2656 | "jmp .Li386_less_signed_end\n\t" | |
2657 | ".Li386_less_signed_true:\n\t" | |
2658 | "mov $1,%eax\n\t" | |
2659 | ".Li386_less_signed_end:\n\t" | |
2660 | "xor %ebx,%ebx\n\t" | |
2661 | "lea 0x8(%esp),%esp"); | |
2662 | } | |
2663 | ||
2664 | static void | |
2665 | i386_emit_less_unsigned (void) | |
2666 | { | |
2667 | EMIT_ASM32 (i386_less_unsigned, | |
2668 | "cmpl %ebx,4(%esp)\n\t" | |
2669 | "jb .Li386_less_unsigned_true\n\t" | |
2670 | "jne .Li386_less_unsigned_false\n\t" | |
2671 | "cmpl %eax,(%esp)\n\t" | |
2672 | "jb .Li386_less_unsigned_true\n\t" | |
2673 | ".Li386_less_unsigned_false:\n\t" | |
2674 | "xor %eax,%eax\n\t" | |
2675 | "jmp .Li386_less_unsigned_end\n\t" | |
2676 | ".Li386_less_unsigned_true:\n\t" | |
2677 | "mov $1,%eax\n\t" | |
2678 | ".Li386_less_unsigned_end:\n\t" | |
2679 | "xor %ebx,%ebx\n\t" | |
2680 | "lea 0x8(%esp),%esp"); | |
2681 | } | |
2682 | ||
2683 | static void | |
2684 | i386_emit_ref (int size) | |
2685 | { | |
2686 | switch (size) | |
2687 | { | |
2688 | case 1: | |
2689 | EMIT_ASM32 (i386_ref1, | |
2690 | "movb (%eax),%al"); | |
2691 | break; | |
2692 | case 2: | |
2693 | EMIT_ASM32 (i386_ref2, | |
2694 | "movw (%eax),%ax"); | |
2695 | break; | |
2696 | case 4: | |
2697 | EMIT_ASM32 (i386_ref4, | |
2698 | "movl (%eax),%eax"); | |
2699 | break; | |
2700 | case 8: | |
2701 | EMIT_ASM32 (i386_ref8, | |
2702 | "movl 4(%eax),%ebx\n\t" | |
2703 | "movl (%eax),%eax"); | |
2704 | break; | |
2705 | } | |
2706 | } | |
2707 | ||
2708 | static void | |
2709 | i386_emit_if_goto (int *offset_p, int *size_p) | |
2710 | { | |
2711 | EMIT_ASM32 (i386_if_goto, | |
2712 | "mov %eax,%ecx\n\t" | |
2713 | "or %ebx,%ecx\n\t" | |
2714 | "pop %eax\n\t" | |
2715 | "pop %ebx\n\t" | |
2716 | "cmpl $0,%ecx\n\t" | |
2717 | /* Don't trust the assembler to choose the right jump */ | |
2718 | ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0"); | |
2719 | ||
2720 | if (offset_p) | |
2721 | *offset_p = 11; /* be sure that this matches the sequence above */ | |
2722 | if (size_p) | |
2723 | *size_p = 4; | |
2724 | } | |
2725 | ||
2726 | static void | |
2727 | i386_emit_goto (int *offset_p, int *size_p) | |
2728 | { | |
2729 | EMIT_ASM32 (i386_goto, | |
2730 | /* Don't trust the assembler to choose the right jump */ | |
2731 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0"); | |
2732 | if (offset_p) | |
2733 | *offset_p = 1; | |
2734 | if (size_p) | |
2735 | *size_p = 4; | |
2736 | } | |
2737 | ||
2738 | static void | |
2739 | i386_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) | |
2740 | { | |
2741 | int diff = (to - (from + size)); | |
2742 | unsigned char buf[sizeof (int)]; | |
2743 | ||
2744 | /* We're only doing 4-byte sizes at the moment. */ | |
2745 | if (size != 4) | |
2746 | { | |
2747 | emit_error = 1; | |
2748 | return; | |
2749 | } | |
2750 | ||
2751 | memcpy (buf, &diff, sizeof (int)); | |
2752 | write_inferior_memory (from, buf, sizeof (int)); | |
2753 | } | |
2754 | ||
2755 | static void | |
4e29fb54 | 2756 | i386_emit_const (LONGEST num) |
6a271cae PA |
2757 | { |
2758 | unsigned char buf[16]; | |
b00ad6ff | 2759 | int i, hi, lo; |
6a271cae PA |
2760 | CORE_ADDR buildaddr = current_insn_ptr; |
2761 | ||
2762 | i = 0; | |
2763 | buf[i++] = 0xb8; /* mov $<n>,%eax */ | |
b00ad6ff NF |
2764 | lo = num & 0xffffffff; |
2765 | memcpy (&buf[i], &lo, sizeof (lo)); | |
6a271cae PA |
2766 | i += 4; |
2767 | hi = ((num >> 32) & 0xffffffff); | |
2768 | if (hi) | |
2769 | { | |
2770 | buf[i++] = 0xbb; /* mov $<n>,%ebx */ | |
b00ad6ff | 2771 | memcpy (&buf[i], &hi, sizeof (hi)); |
6a271cae PA |
2772 | i += 4; |
2773 | } | |
2774 | else | |
2775 | { | |
2776 | buf[i++] = 0x31; buf[i++] = 0xdb; /* xor %ebx,%ebx */ | |
2777 | } | |
2778 | append_insns (&buildaddr, i, buf); | |
2779 | current_insn_ptr = buildaddr; | |
2780 | } | |
2781 | ||
2782 | static void | |
2783 | i386_emit_call (CORE_ADDR fn) | |
2784 | { | |
2785 | unsigned char buf[16]; | |
2786 | int i, offset; | |
2787 | CORE_ADDR buildaddr; | |
2788 | ||
2789 | buildaddr = current_insn_ptr; | |
2790 | i = 0; | |
2791 | buf[i++] = 0xe8; /* call <reladdr> */ | |
2792 | offset = ((int) fn) - (buildaddr + 5); | |
2793 | memcpy (buf + 1, &offset, 4); | |
2794 | append_insns (&buildaddr, 5, buf); | |
2795 | current_insn_ptr = buildaddr; | |
2796 | } | |
2797 | ||
2798 | static void | |
2799 | i386_emit_reg (int reg) | |
2800 | { | |
2801 | unsigned char buf[16]; | |
2802 | int i; | |
2803 | CORE_ADDR buildaddr; | |
2804 | ||
2805 | EMIT_ASM32 (i386_reg_a, | |
2806 | "sub $0x8,%esp"); | |
2807 | buildaddr = current_insn_ptr; | |
2808 | i = 0; | |
2809 | buf[i++] = 0xb8; /* mov $<n>,%eax */ | |
b00ad6ff | 2810 | memcpy (&buf[i], ®, sizeof (reg)); |
6a271cae PA |
2811 | i += 4; |
2812 | append_insns (&buildaddr, i, buf); | |
2813 | current_insn_ptr = buildaddr; | |
2814 | EMIT_ASM32 (i386_reg_b, | |
2815 | "mov %eax,4(%esp)\n\t" | |
2816 | "mov 8(%ebp),%eax\n\t" | |
2817 | "mov %eax,(%esp)"); | |
2818 | i386_emit_call (get_raw_reg_func_addr ()); | |
2819 | EMIT_ASM32 (i386_reg_c, | |
2820 | "xor %ebx,%ebx\n\t" | |
2821 | "lea 0x8(%esp),%esp"); | |
2822 | } | |
2823 | ||
2824 | static void | |
2825 | i386_emit_pop (void) | |
2826 | { | |
2827 | EMIT_ASM32 (i386_pop, | |
2828 | "pop %eax\n\t" | |
2829 | "pop %ebx"); | |
2830 | } | |
2831 | ||
2832 | static void | |
2833 | i386_emit_stack_flush (void) | |
2834 | { | |
2835 | EMIT_ASM32 (i386_stack_flush, | |
2836 | "push %ebx\n\t" | |
2837 | "push %eax"); | |
2838 | } | |
2839 | ||
2840 | static void | |
2841 | i386_emit_zero_ext (int arg) | |
2842 | { | |
2843 | switch (arg) | |
2844 | { | |
2845 | case 8: | |
2846 | EMIT_ASM32 (i386_zero_ext_8, | |
2847 | "and $0xff,%eax\n\t" | |
2848 | "xor %ebx,%ebx"); | |
2849 | break; | |
2850 | case 16: | |
2851 | EMIT_ASM32 (i386_zero_ext_16, | |
2852 | "and $0xffff,%eax\n\t" | |
2853 | "xor %ebx,%ebx"); | |
2854 | break; | |
2855 | case 32: | |
2856 | EMIT_ASM32 (i386_zero_ext_32, | |
2857 | "xor %ebx,%ebx"); | |
2858 | break; | |
2859 | default: | |
2860 | emit_error = 1; | |
2861 | } | |
2862 | } | |
2863 | ||
2864 | static void | |
2865 | i386_emit_swap (void) | |
2866 | { | |
2867 | EMIT_ASM32 (i386_swap, | |
2868 | "mov %eax,%ecx\n\t" | |
2869 | "mov %ebx,%edx\n\t" | |
2870 | "pop %eax\n\t" | |
2871 | "pop %ebx\n\t" | |
2872 | "push %edx\n\t" | |
2873 | "push %ecx"); | |
2874 | } | |
2875 | ||
2876 | static void | |
2877 | i386_emit_stack_adjust (int n) | |
2878 | { | |
2879 | unsigned char buf[16]; | |
2880 | int i; | |
2881 | CORE_ADDR buildaddr = current_insn_ptr; | |
2882 | ||
2883 | i = 0; | |
2884 | buf[i++] = 0x8d; /* lea $<n>(%esp),%esp */ | |
2885 | buf[i++] = 0x64; | |
2886 | buf[i++] = 0x24; | |
2887 | buf[i++] = n * 8; | |
2888 | append_insns (&buildaddr, i, buf); | |
2889 | current_insn_ptr = buildaddr; | |
2890 | } | |
2891 | ||
2892 | /* FN's prototype is `LONGEST(*fn)(int)'. */ | |
2893 | ||
2894 | static void | |
2895 | i386_emit_int_call_1 (CORE_ADDR fn, int arg1) | |
2896 | { | |
2897 | unsigned char buf[16]; | |
2898 | int i; | |
2899 | CORE_ADDR buildaddr; | |
2900 | ||
2901 | EMIT_ASM32 (i386_int_call_1_a, | |
2902 | /* Reserve a bit of stack space. */ | |
2903 | "sub $0x8,%esp"); | |
2904 | /* Put the one argument on the stack. */ | |
2905 | buildaddr = current_insn_ptr; | |
2906 | i = 0; | |
2907 | buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */ | |
2908 | buf[i++] = 0x04; | |
2909 | buf[i++] = 0x24; | |
b00ad6ff | 2910 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
6a271cae PA |
2911 | i += 4; |
2912 | append_insns (&buildaddr, i, buf); | |
2913 | current_insn_ptr = buildaddr; | |
2914 | i386_emit_call (fn); | |
2915 | EMIT_ASM32 (i386_int_call_1_c, | |
2916 | "mov %edx,%ebx\n\t" | |
2917 | "lea 0x8(%esp),%esp"); | |
2918 | } | |
2919 | ||
4e29fb54 | 2920 | /* FN's prototype is `void(*fn)(int,LONGEST)'. */ |
6a271cae PA |
2921 | |
2922 | static void | |
2923 | i386_emit_void_call_2 (CORE_ADDR fn, int arg1) | |
2924 | { | |
2925 | unsigned char buf[16]; | |
2926 | int i; | |
2927 | CORE_ADDR buildaddr; | |
2928 | ||
2929 | EMIT_ASM32 (i386_void_call_2_a, | |
2930 | /* Preserve %eax only; we don't have to worry about %ebx. */ | |
2931 | "push %eax\n\t" | |
2932 | /* Reserve a bit of stack space for arguments. */ | |
2933 | "sub $0x10,%esp\n\t" | |
2934 | /* Copy "top" to the second argument position. (Note that | |
2935 | we can't assume function won't scribble on its | |
2936 | arguments, so don't try to restore from this.) */ | |
2937 | "mov %eax,4(%esp)\n\t" | |
2938 | "mov %ebx,8(%esp)"); | |
2939 | /* Put the first argument on the stack. */ | |
2940 | buildaddr = current_insn_ptr; | |
2941 | i = 0; | |
2942 | buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */ | |
2943 | buf[i++] = 0x04; | |
2944 | buf[i++] = 0x24; | |
b00ad6ff | 2945 | memcpy (&buf[i], &arg1, sizeof (arg1)); |
6a271cae PA |
2946 | i += 4; |
2947 | append_insns (&buildaddr, i, buf); | |
2948 | current_insn_ptr = buildaddr; | |
2949 | i386_emit_call (fn); | |
2950 | EMIT_ASM32 (i386_void_call_2_b, | |
2951 | "lea 0x10(%esp),%esp\n\t" | |
2952 | /* Restore original stack top. */ | |
2953 | "pop %eax"); | |
2954 | } | |
2955 | ||
6b9801d4 SS |
2956 | |
2957 | void | |
2958 | i386_emit_eq_goto (int *offset_p, int *size_p) | |
2959 | { | |
2960 | EMIT_ASM32 (eq, | |
2961 | /* Check low half first, more likely to be decider */ | |
2962 | "cmpl %eax,(%esp)\n\t" | |
2963 | "jne .Leq_fallthru\n\t" | |
2964 | "cmpl %ebx,4(%esp)\n\t" | |
2965 | "jne .Leq_fallthru\n\t" | |
2966 | "lea 0x8(%esp),%esp\n\t" | |
2967 | "pop %eax\n\t" | |
2968 | "pop %ebx\n\t" | |
2969 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2970 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2971 | ".Leq_fallthru:\n\t" | |
2972 | "lea 0x8(%esp),%esp\n\t" | |
2973 | "pop %eax\n\t" | |
2974 | "pop %ebx"); | |
2975 | ||
2976 | if (offset_p) | |
2977 | *offset_p = 18; | |
2978 | if (size_p) | |
2979 | *size_p = 4; | |
2980 | } | |
2981 | ||
2982 | void | |
2983 | i386_emit_ne_goto (int *offset_p, int *size_p) | |
2984 | { | |
2985 | EMIT_ASM32 (ne, | |
2986 | /* Check low half first, more likely to be decider */ | |
2987 | "cmpl %eax,(%esp)\n\t" | |
2988 | "jne .Lne_jump\n\t" | |
2989 | "cmpl %ebx,4(%esp)\n\t" | |
2990 | "je .Lne_fallthru\n\t" | |
2991 | ".Lne_jump:\n\t" | |
2992 | "lea 0x8(%esp),%esp\n\t" | |
2993 | "pop %eax\n\t" | |
2994 | "pop %ebx\n\t" | |
2995 | /* jmp, but don't trust the assembler to choose the right jump */ | |
2996 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
2997 | ".Lne_fallthru:\n\t" | |
2998 | "lea 0x8(%esp),%esp\n\t" | |
2999 | "pop %eax\n\t" | |
3000 | "pop %ebx"); | |
3001 | ||
3002 | if (offset_p) | |
3003 | *offset_p = 18; | |
3004 | if (size_p) | |
3005 | *size_p = 4; | |
3006 | } | |
3007 | ||
3008 | void | |
3009 | i386_emit_lt_goto (int *offset_p, int *size_p) | |
3010 | { | |
3011 | EMIT_ASM32 (lt, | |
3012 | "cmpl %ebx,4(%esp)\n\t" | |
3013 | "jl .Llt_jump\n\t" | |
3014 | "jne .Llt_fallthru\n\t" | |
3015 | "cmpl %eax,(%esp)\n\t" | |
3016 | "jnl .Llt_fallthru\n\t" | |
3017 | ".Llt_jump:\n\t" | |
3018 | "lea 0x8(%esp),%esp\n\t" | |
3019 | "pop %eax\n\t" | |
3020 | "pop %ebx\n\t" | |
3021 | /* jmp, but don't trust the assembler to choose the right jump */ | |
3022 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
3023 | ".Llt_fallthru:\n\t" | |
3024 | "lea 0x8(%esp),%esp\n\t" | |
3025 | "pop %eax\n\t" | |
3026 | "pop %ebx"); | |
3027 | ||
3028 | if (offset_p) | |
3029 | *offset_p = 20; | |
3030 | if (size_p) | |
3031 | *size_p = 4; | |
3032 | } | |
3033 | ||
3034 | void | |
3035 | i386_emit_le_goto (int *offset_p, int *size_p) | |
3036 | { | |
3037 | EMIT_ASM32 (le, | |
3038 | "cmpl %ebx,4(%esp)\n\t" | |
3039 | "jle .Lle_jump\n\t" | |
3040 | "jne .Lle_fallthru\n\t" | |
3041 | "cmpl %eax,(%esp)\n\t" | |
3042 | "jnle .Lle_fallthru\n\t" | |
3043 | ".Lle_jump:\n\t" | |
3044 | "lea 0x8(%esp),%esp\n\t" | |
3045 | "pop %eax\n\t" | |
3046 | "pop %ebx\n\t" | |
3047 | /* jmp, but don't trust the assembler to choose the right jump */ | |
3048 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
3049 | ".Lle_fallthru:\n\t" | |
3050 | "lea 0x8(%esp),%esp\n\t" | |
3051 | "pop %eax\n\t" | |
3052 | "pop %ebx"); | |
3053 | ||
3054 | if (offset_p) | |
3055 | *offset_p = 20; | |
3056 | if (size_p) | |
3057 | *size_p = 4; | |
3058 | } | |
3059 | ||
3060 | void | |
3061 | i386_emit_gt_goto (int *offset_p, int *size_p) | |
3062 | { | |
3063 | EMIT_ASM32 (gt, | |
3064 | "cmpl %ebx,4(%esp)\n\t" | |
3065 | "jg .Lgt_jump\n\t" | |
3066 | "jne .Lgt_fallthru\n\t" | |
3067 | "cmpl %eax,(%esp)\n\t" | |
3068 | "jng .Lgt_fallthru\n\t" | |
3069 | ".Lgt_jump:\n\t" | |
3070 | "lea 0x8(%esp),%esp\n\t" | |
3071 | "pop %eax\n\t" | |
3072 | "pop %ebx\n\t" | |
3073 | /* jmp, but don't trust the assembler to choose the right jump */ | |
3074 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
3075 | ".Lgt_fallthru:\n\t" | |
3076 | "lea 0x8(%esp),%esp\n\t" | |
3077 | "pop %eax\n\t" | |
3078 | "pop %ebx"); | |
3079 | ||
3080 | if (offset_p) | |
3081 | *offset_p = 20; | |
3082 | if (size_p) | |
3083 | *size_p = 4; | |
3084 | } | |
3085 | ||
3086 | void | |
3087 | i386_emit_ge_goto (int *offset_p, int *size_p) | |
3088 | { | |
3089 | EMIT_ASM32 (ge, | |
3090 | "cmpl %ebx,4(%esp)\n\t" | |
3091 | "jge .Lge_jump\n\t" | |
3092 | "jne .Lge_fallthru\n\t" | |
3093 | "cmpl %eax,(%esp)\n\t" | |
3094 | "jnge .Lge_fallthru\n\t" | |
3095 | ".Lge_jump:\n\t" | |
3096 | "lea 0x8(%esp),%esp\n\t" | |
3097 | "pop %eax\n\t" | |
3098 | "pop %ebx\n\t" | |
3099 | /* jmp, but don't trust the assembler to choose the right jump */ | |
3100 | ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" | |
3101 | ".Lge_fallthru:\n\t" | |
3102 | "lea 0x8(%esp),%esp\n\t" | |
3103 | "pop %eax\n\t" | |
3104 | "pop %ebx"); | |
3105 | ||
3106 | if (offset_p) | |
3107 | *offset_p = 20; | |
3108 | if (size_p) | |
3109 | *size_p = 4; | |
3110 | } | |
3111 | ||
6a271cae PA |
3112 | struct emit_ops i386_emit_ops = |
3113 | { | |
3114 | i386_emit_prologue, | |
3115 | i386_emit_epilogue, | |
3116 | i386_emit_add, | |
3117 | i386_emit_sub, | |
3118 | i386_emit_mul, | |
3119 | i386_emit_lsh, | |
3120 | i386_emit_rsh_signed, | |
3121 | i386_emit_rsh_unsigned, | |
3122 | i386_emit_ext, | |
3123 | i386_emit_log_not, | |
3124 | i386_emit_bit_and, | |
3125 | i386_emit_bit_or, | |
3126 | i386_emit_bit_xor, | |
3127 | i386_emit_bit_not, | |
3128 | i386_emit_equal, | |
3129 | i386_emit_less_signed, | |
3130 | i386_emit_less_unsigned, | |
3131 | i386_emit_ref, | |
3132 | i386_emit_if_goto, | |
3133 | i386_emit_goto, | |
3134 | i386_write_goto_address, | |
3135 | i386_emit_const, | |
3136 | i386_emit_call, | |
3137 | i386_emit_reg, | |
3138 | i386_emit_pop, | |
3139 | i386_emit_stack_flush, | |
3140 | i386_emit_zero_ext, | |
3141 | i386_emit_swap, | |
3142 | i386_emit_stack_adjust, | |
3143 | i386_emit_int_call_1, | |
6b9801d4 SS |
3144 | i386_emit_void_call_2, |
3145 | i386_emit_eq_goto, | |
3146 | i386_emit_ne_goto, | |
3147 | i386_emit_lt_goto, | |
3148 | i386_emit_le_goto, | |
3149 | i386_emit_gt_goto, | |
3150 | i386_emit_ge_goto | |
6a271cae PA |
3151 | }; |
3152 | ||
3153 | ||
3154 | static struct emit_ops * | |
3155 | x86_emit_ops (void) | |
3156 | { | |
3157 | #ifdef __x86_64__ | |
3158 | int use_64bit = register_size (0) == 8; | |
3159 | ||
3160 | if (use_64bit) | |
3161 | return &amd64_emit_ops; | |
3162 | else | |
3163 | #endif | |
3164 | return &i386_emit_ops; | |
3165 | } | |
3166 | ||
d0722149 DE |
3167 | /* This is initialized assuming an amd64 target. |
3168 | x86_arch_setup will correct it for i386 or amd64 targets. */ | |
3169 | ||
3170 | struct linux_target_ops the_low_target = | |
3171 | { | |
3172 | x86_arch_setup, | |
3173 | -1, | |
3174 | NULL, | |
3175 | NULL, | |
3176 | NULL, | |
1faeff08 | 3177 | NULL, |
c14dfd32 | 3178 | NULL, /* fetch_register */ |
d0722149 DE |
3179 | x86_get_pc, |
3180 | x86_set_pc, | |
3181 | x86_breakpoint, | |
3182 | x86_breakpoint_len, | |
3183 | NULL, | |
3184 | 1, | |
3185 | x86_breakpoint_at, | |
aa5ca48f DE |
3186 | x86_insert_point, |
3187 | x86_remove_point, | |
3188 | x86_stopped_by_watchpoint, | |
3189 | x86_stopped_data_address, | |
d0722149 DE |
3190 | /* collect_ptrace_register/supply_ptrace_register are not needed in the |
3191 | native i386 case (no registers smaller than an xfer unit), and are not | |
3192 | used in the biarch case (HAVE_LINUX_USRREGS is not defined). */ | |
3193 | NULL, | |
3194 | NULL, | |
3195 | /* need to fix up i386 siginfo if host is amd64 */ | |
3196 | x86_siginfo_fixup, | |
aa5ca48f DE |
3197 | x86_linux_new_process, |
3198 | x86_linux_new_thread, | |
1570b33e | 3199 | x86_linux_prepare_to_resume, |
219f2f23 | 3200 | x86_linux_process_qsupported, |
fa593d66 PA |
3201 | x86_supports_tracepoints, |
3202 | x86_get_thread_area, | |
6a271cae | 3203 | x86_install_fast_tracepoint_jump_pad, |
405f8e94 SS |
3204 | x86_emit_ops, |
3205 | x86_get_min_fast_tracepoint_insn_len, | |
d0722149 | 3206 | }; |