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7fa2737c MK |
1 | /* Native-dependent code for the i386. |
2 | ||
ecd75fc8 | 3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. |
52b98211 EZ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
52b98211 EZ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
52b98211 EZ |
19 | |
20 | #include "defs.h" | |
0baeab03 | 21 | #include "i386-nat.h" |
52b98211 EZ |
22 | #include "breakpoint.h" |
23 | #include "command.h" | |
24 | #include "gdbcmd.h" | |
c03374d5 | 25 | #include "target.h" |
9bb9e8ad | 26 | #include "gdb_assert.h" |
4403d8e9 | 27 | #include "inferior.h" |
52b98211 | 28 | |
7fa2737c | 29 | /* Support for hardware watchpoints and breakpoints using the i386 |
52b98211 EZ |
30 | debug registers. |
31 | ||
32 | This provides several functions for inserting and removing | |
7fa2737c MK |
33 | hardware-assisted breakpoints and watchpoints, testing if one or |
34 | more of the watchpoints triggered and at what address, checking | |
35 | whether a given region can be watched, etc. | |
36 | ||
7fa2737c MK |
37 | The functions below implement debug registers sharing by reference |
38 | counts, and allow to watch regions up to 16 bytes long. */ | |
52b98211 | 39 | |
ea008da4 GB |
40 | /* Whether or not to print the mirrored debug registers. */ |
41 | static int debug_hw_points; | |
42 | ||
1b6d4134 GB |
43 | /* Function used for printing mirrored debug registers. */ |
44 | #define debug_printf(fmt, args...) \ | |
45 | fprintf_unfiltered (gdb_stdlog, fmt, ##args); | |
46 | ||
6e62758f | 47 | /* Low-level function vector. */ |
9bb9e8ad PM |
48 | struct i386_dr_low_type i386_dr_low; |
49 | ||
e906b9a3 | 50 | /* Support for 8-byte wide hw watchpoints. */ |
1b6d4134 | 51 | #define TARGET_HAS_DR_LEN_8 (i386_get_debug_register_length () == 8) |
e906b9a3 | 52 | |
52b98211 EZ |
53 | /* DR7 Debug Control register fields. */ |
54 | ||
55 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
56 | #define DR_CONTROL_SHIFT 16 | |
57 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
58 | #define DR_CONTROL_SIZE 4 | |
59 | ||
60 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
7fa2737c MK |
61 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ |
62 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
63 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
52b98211 EZ |
64 | |
65 | /* This is here for completeness. No platform supports this | |
7fa2737c | 66 | functionality yet (as of March 2001). Note that the DE flag in the |
52b98211 EZ |
67 | CR4 register needs to be set to support this. */ |
68 | #ifndef DR_RW_IORW | |
7fa2737c | 69 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ |
52b98211 EZ |
70 | #endif |
71 | ||
72 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
73 | is so we could OR this with the read/write field defined above. */ | |
7fa2737c MK |
74 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ |
75 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
76 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
77 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
52b98211 EZ |
78 | |
79 | /* Local and Global Enable flags in DR7. | |
80 | ||
81 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
82 | enabled only for the current task; the processor automatically | |
7fa2737c MK |
83 | clears this flag on every task switch. When the Global Enable flag |
84 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
85 | processor never clears this flag. | |
52b98211 EZ |
86 | |
87 | Currently, all watchpoint are locally enabled. If you need to | |
88 | enable them globally, read the comment which pertains to this in | |
4be83cc2 | 89 | i386_dr_insert_aligned_watchpoint below. */ |
7fa2737c MK |
90 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
91 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
92 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
52b98211 EZ |
93 | |
94 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
95 | flags). These are only required on i386, to allow detection of the | |
96 | exact instruction which caused a watchpoint to break; i486 and | |
97 | later processors do that automatically. We set these flags for | |
7fa2737c | 98 | backwards compatibility. */ |
52b98211 | 99 | #define DR_LOCAL_SLOWDOWN (0x100) |
fc6e2f03 | 100 | #define DR_GLOBAL_SLOWDOWN (0x200) |
52b98211 EZ |
101 | |
102 | /* Fields reserved by Intel. This includes the GD (General Detect | |
103 | Enable) flag, which causes a debug exception to be generated when a | |
104 | MOV instruction accesses one of the debug registers. | |
105 | ||
106 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
107 | #define DR_CONTROL_RESERVED (0xFC00) | |
108 | ||
109 | /* Auxiliary helper macros. */ | |
110 | ||
111 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
7fa2737c | 112 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
52b98211 EZ |
113 | |
114 | /* The I'th debug register is vacant if its Local and Global Enable | |
115 | bits are reset in the Debug Control register. */ | |
fc6e2f03 | 116 | #define I386_DR_VACANT(state, i) \ |
1ced966e | 117 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) |
52b98211 EZ |
118 | |
119 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
120 | #define I386_DR_LOCAL_ENABLE(state, i) \ |
121 | do { \ | |
122 | (state)->dr_control_mirror |= \ | |
123 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
124 | } while (0) | |
52b98211 EZ |
125 | |
126 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
127 | #define I386_DR_GLOBAL_ENABLE(state, i) \ |
128 | do { \ | |
129 | (state)->dr_control_mirror |= \ | |
130 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
131 | } while (0) | |
52b98211 EZ |
132 | |
133 | /* Disable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
134 | #define I386_DR_DISABLE(state, i) \ |
135 | do { \ | |
136 | (state)->dr_control_mirror &= \ | |
137 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
138 | } while (0) | |
52b98211 EZ |
139 | |
140 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e | 141 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ |
52b98211 | 142 | do { \ |
1ced966e PA |
143 | (state)->dr_control_mirror &= \ |
144 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
145 | (state)->dr_control_mirror |= \ | |
146 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
52b98211 EZ |
147 | } while (0) |
148 | ||
149 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e PA |
150 | #define I386_DR_GET_RW_LEN(dr7, i) \ |
151 | (((dr7) \ | |
152 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
52b98211 EZ |
153 | |
154 | /* Did the watchpoint whose address is in the I'th register break? */ | |
1ced966e | 155 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
52b98211 | 156 | |
26cb8b7c PA |
157 | /* Per-process data. We don't bind this to a per-inferior registry |
158 | because of targets like x86 GNU/Linux that need to keep track of | |
159 | processes that aren't bound to any inferior (e.g., fork children, | |
160 | checkpoints). */ | |
1ced966e | 161 | |
26cb8b7c | 162 | struct i386_process_info |
1ced966e | 163 | { |
26cb8b7c PA |
164 | /* Linked list. */ |
165 | struct i386_process_info *next; | |
1ced966e | 166 | |
26cb8b7c PA |
167 | /* The process identifier. */ |
168 | pid_t pid; | |
4403d8e9 | 169 | |
26cb8b7c | 170 | /* Copy of i386 hardware debug registers. */ |
4403d8e9 JK |
171 | struct i386_debug_reg_state state; |
172 | }; | |
173 | ||
26cb8b7c | 174 | static struct i386_process_info *i386_process_list = NULL; |
d0d8b0c6 | 175 | |
26cb8b7c PA |
176 | /* Find process data for process PID. */ |
177 | ||
178 | static struct i386_process_info * | |
179 | i386_find_process_pid (pid_t pid) | |
d0d8b0c6 | 180 | { |
26cb8b7c PA |
181 | struct i386_process_info *proc; |
182 | ||
183 | for (proc = i386_process_list; proc; proc = proc->next) | |
184 | if (proc->pid == pid) | |
185 | return proc; | |
d0d8b0c6 | 186 | |
26cb8b7c | 187 | return NULL; |
d0d8b0c6 JK |
188 | } |
189 | ||
26cb8b7c PA |
190 | /* Add process data for process PID. Returns newly allocated info |
191 | object. */ | |
4403d8e9 | 192 | |
26cb8b7c PA |
193 | static struct i386_process_info * |
194 | i386_add_process (pid_t pid) | |
4403d8e9 | 195 | { |
26cb8b7c | 196 | struct i386_process_info *proc; |
d0d8b0c6 | 197 | |
26cb8b7c PA |
198 | proc = xcalloc (1, sizeof (*proc)); |
199 | proc->pid = pid; | |
4403d8e9 | 200 | |
26cb8b7c PA |
201 | proc->next = i386_process_list; |
202 | i386_process_list = proc; | |
4403d8e9 | 203 | |
26cb8b7c PA |
204 | return proc; |
205 | } | |
4403d8e9 | 206 | |
26cb8b7c PA |
207 | /* Get data specific info for process PID, creating it if necessary. |
208 | Never returns NULL. */ | |
4403d8e9 | 209 | |
26cb8b7c PA |
210 | static struct i386_process_info * |
211 | i386_process_info_get (pid_t pid) | |
212 | { | |
213 | struct i386_process_info *proc; | |
214 | ||
215 | proc = i386_find_process_pid (pid); | |
216 | if (proc == NULL) | |
217 | proc = i386_add_process (pid); | |
4403d8e9 | 218 | |
26cb8b7c | 219 | return proc; |
4403d8e9 JK |
220 | } |
221 | ||
26cb8b7c | 222 | /* Get debug registers state for process PID. */ |
52b98211 | 223 | |
7b50312a | 224 | struct i386_debug_reg_state * |
26cb8b7c | 225 | i386_debug_reg_state (pid_t pid) |
7b50312a | 226 | { |
26cb8b7c PA |
227 | return &i386_process_info_get (pid)->state; |
228 | } | |
229 | ||
230 | /* See declaration in i386-nat.h. */ | |
231 | ||
232 | void | |
233 | i386_forget_process (pid_t pid) | |
234 | { | |
235 | struct i386_process_info *proc, **proc_link; | |
236 | ||
237 | proc = i386_process_list; | |
238 | proc_link = &i386_process_list; | |
239 | ||
240 | while (proc != NULL) | |
241 | { | |
242 | if (proc->pid == pid) | |
243 | { | |
244 | *proc_link = proc->next; | |
245 | ||
246 | xfree (proc); | |
247 | return; | |
248 | } | |
249 | ||
250 | proc_link = &proc->next; | |
251 | proc = *proc_link; | |
252 | } | |
7b50312a PA |
253 | } |
254 | ||
52b98211 EZ |
255 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ |
256 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
257 | ||
52b98211 EZ |
258 | /* Implementation. */ |
259 | ||
7fa2737c MK |
260 | /* Clear the reference counts and forget everything we knew about the |
261 | debug registers. */ | |
262 | ||
52b98211 EZ |
263 | void |
264 | i386_cleanup_dregs (void) | |
265 | { | |
26cb8b7c PA |
266 | /* Starting from scratch has the same effect. */ |
267 | i386_forget_process (ptid_get_pid (inferior_ptid)); | |
52b98211 EZ |
268 | } |
269 | ||
6e62758f | 270 | /* Print the values of the mirrored debug registers. */ |
7fa2737c | 271 | |
4be83cc2 GB |
272 | void |
273 | i386_dr_show (struct i386_debug_reg_state *state, | |
1ced966e | 274 | const char *func, CORE_ADDR addr, |
52b98211 EZ |
275 | int len, enum target_hw_bp_type type) |
276 | { | |
277 | int i; | |
278 | ||
1b6d4134 | 279 | debug_printf ("%s", func); |
52b98211 | 280 | if (addr || len) |
1b6d4134 GB |
281 | debug_printf (" (addr=%s, len=%d, type=%s)", |
282 | phex (addr, 8), len, | |
283 | type == hw_write ? "data-write" | |
284 | : (type == hw_read ? "data-read" | |
285 | : (type == hw_access ? "data-read/write" | |
286 | : (type == hw_execute ? "instruction-execute" | |
287 | /* FIXME: if/when I/O read/write | |
288 | watchpoints are supported, add them | |
289 | here. */ | |
290 | : "??unknown??")))); | |
291 | debug_printf (":\n"); | |
292 | debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", | |
293 | phex (state->dr_control_mirror, 8), | |
294 | phex (state->dr_status_mirror, 8)); | |
fc6e2f03 | 295 | ALL_DEBUG_REGISTERS (i) |
52b98211 | 296 | { |
1b6d4134 | 297 | debug_printf ("\ |
7fa2737c | 298 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", |
1b6d4134 GB |
299 | i, phex (state->dr_mirror[i], |
300 | i386_get_debug_register_length ()), | |
301 | state->dr_ref_count[i], | |
302 | i + 1, phex (state->dr_mirror[i + 1], | |
303 | i386_get_debug_register_length ()), | |
304 | state->dr_ref_count[i + 1]); | |
52b98211 EZ |
305 | i++; |
306 | } | |
307 | } | |
308 | ||
309 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
310 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
311 | have the value of 1, 2, or 4. */ | |
312 | ||
4be83cc2 GB |
313 | unsigned |
314 | i386_dr_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
52b98211 EZ |
315 | { |
316 | unsigned rw; | |
317 | ||
318 | switch (type) | |
319 | { | |
320 | case hw_execute: | |
321 | rw = DR_RW_EXECUTE; | |
322 | break; | |
323 | case hw_write: | |
324 | rw = DR_RW_WRITE; | |
325 | break; | |
7fa2737c | 326 | case hw_read: |
85d721b8 | 327 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
328 | _("The i386 doesn't support " |
329 | "data-read watchpoints.\n")); | |
52b98211 EZ |
330 | case hw_access: |
331 | rw = DR_RW_READ; | |
332 | break; | |
333 | #if 0 | |
7fa2737c MK |
334 | /* Not yet supported. */ |
335 | case hw_io_access: | |
52b98211 EZ |
336 | rw = DR_RW_IORW; |
337 | break; | |
338 | #endif | |
339 | default: | |
e2e0b3e5 | 340 | internal_error (__FILE__, __LINE__, _("\ |
4be83cc2 | 341 | Invalid hardware breakpoint type %d in i386_dr_length_and_rw_bits.\n"), |
7fa2737c | 342 | (int) type); |
52b98211 EZ |
343 | } |
344 | ||
345 | switch (len) | |
346 | { | |
52b98211 EZ |
347 | case 1: |
348 | return (DR_LEN_1 | rw); | |
e906b9a3 JS |
349 | case 2: |
350 | return (DR_LEN_2 | rw); | |
351 | case 4: | |
352 | return (DR_LEN_4 | rw); | |
353 | case 8: | |
354 | if (TARGET_HAS_DR_LEN_8) | |
355 | return (DR_LEN_8 | rw); | |
8fbf6b93 | 356 | /* ELSE FALL THROUGH */ |
52b98211 | 357 | default: |
e2e0b3e5 | 358 | internal_error (__FILE__, __LINE__, _("\ |
4be83cc2 | 359 | Invalid hardware breakpoint length %d in i386_dr_length_and_rw_bits.\n"), len); |
52b98211 EZ |
360 | } |
361 | } | |
362 | ||
363 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
364 | according to the length of the region to watch. LEN_RW_BITS is the | |
365 | value of the bits from DR7 which describes the length and access | |
366 | type of the region to be watched by this watchpoint. Return 0 on | |
367 | success, -1 on failure. */ | |
7fa2737c | 368 | |
4be83cc2 GB |
369 | int |
370 | i386_dr_insert_aligned_watchpoint (struct i386_debug_reg_state *state, | |
371 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
372 | { |
373 | int i; | |
374 | ||
131aa0d4 | 375 | if (!i386_dr_low_can_set_addr () || !i386_dr_low_can_set_control ()) |
9bb9e8ad PM |
376 | return -1; |
377 | ||
52b98211 EZ |
378 | /* First, look for an occupied debug register with the same address |
379 | and the same RW and LEN definitions. If we find one, we can | |
380 | reuse it for this watchpoint as well (and save a register). */ | |
fc6e2f03 | 381 | ALL_DEBUG_REGISTERS (i) |
52b98211 | 382 | { |
1ced966e PA |
383 | if (!I386_DR_VACANT (state, i) |
384 | && state->dr_mirror[i] == addr | |
385 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 386 | { |
1ced966e | 387 | state->dr_ref_count[i]++; |
52b98211 EZ |
388 | return 0; |
389 | } | |
390 | } | |
391 | ||
392 | /* Next, look for a vacant debug register. */ | |
fc6e2f03 | 393 | ALL_DEBUG_REGISTERS (i) |
52b98211 | 394 | { |
1ced966e | 395 | if (I386_DR_VACANT (state, i)) |
52b98211 EZ |
396 | break; |
397 | } | |
398 | ||
399 | /* No more debug registers! */ | |
400 | if (i >= DR_NADDR) | |
401 | return -1; | |
402 | ||
403 | /* Now set up the register I to watch our region. */ | |
404 | ||
405 | /* Record the info in our local mirrored array. */ | |
1ced966e PA |
406 | state->dr_mirror[i] = addr; |
407 | state->dr_ref_count[i] = 1; | |
408 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
52b98211 | 409 | /* Note: we only enable the watchpoint locally, i.e. in the current |
7fa2737c | 410 | task. Currently, no i386 target allows or supports global |
52b98211 EZ |
411 | watchpoints; however, if any target would want that in the |
412 | future, GDB should probably provide a command to control whether | |
413 | to enable watchpoints globally or locally, and the code below | |
414 | should use global or local enable and slow-down flags as | |
415 | appropriate. */ | |
1ced966e PA |
416 | I386_DR_LOCAL_ENABLE (state, i); |
417 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
418 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
a79d3c27 | 419 | |
52b98211 EZ |
420 | return 0; |
421 | } | |
422 | ||
423 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
424 | according to the length of the region to watch. LEN_RW_BITS is the | |
425 | value of the bits from DR7 which describes the length and access | |
426 | type of the region watched by this watchpoint. Return 0 on | |
427 | success, -1 on failure. */ | |
7fa2737c | 428 | |
4be83cc2 GB |
429 | int |
430 | i386_dr_remove_aligned_watchpoint (struct i386_debug_reg_state *state, | |
431 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
432 | { |
433 | int i, retval = -1; | |
434 | ||
fc6e2f03 | 435 | ALL_DEBUG_REGISTERS (i) |
52b98211 | 436 | { |
1ced966e PA |
437 | if (!I386_DR_VACANT (state, i) |
438 | && state->dr_mirror[i] == addr | |
439 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 440 | { |
6e62758f | 441 | if (--state->dr_ref_count[i] == 0) /* No longer in use? */ |
52b98211 EZ |
442 | { |
443 | /* Reset our mirror. */ | |
1ced966e PA |
444 | state->dr_mirror[i] = 0; |
445 | I386_DR_DISABLE (state, i); | |
52b98211 EZ |
446 | } |
447 | retval = 0; | |
448 | } | |
449 | } | |
450 | ||
451 | return retval; | |
452 | } | |
453 | ||
454 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
455 | number of debug registers required to watch a region at address | |
456 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
457 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
458 | about the number of registers, or -1 on failure. If WHAT is not a |
459 | valid value, bombs through internal_error. */ | |
460 | ||
52b98211 | 461 | static int |
1ced966e PA |
462 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
463 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
52b98211 EZ |
464 | enum target_hw_bp_type type) |
465 | { | |
1ced966e | 466 | int retval = 0; |
e906b9a3 | 467 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
52b98211 | 468 | |
9b4550ef | 469 | static const int size_try_array[8][8] = |
52b98211 | 470 | { |
7fa2737c MK |
471 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ |
472 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
473 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
474 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
475 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
476 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
477 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
478 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
52b98211 EZ |
479 | }; |
480 | ||
481 | while (len > 0) | |
482 | { | |
7fa2737c | 483 | int align = addr % max_wp_len; |
f2e7c15d | 484 | /* Four (eight on AMD64) is the maximum length a debug register |
e906b9a3 | 485 | can watch. */ |
7fa2737c MK |
486 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); |
487 | int size = size_try_array[try][align]; | |
488 | ||
52b98211 | 489 | if (what == WP_COUNT) |
7fa2737c MK |
490 | { |
491 | /* size_try_array[] is defined such that each iteration | |
492 | through the loop is guaranteed to produce an address and a | |
493 | size that can be watched with a single debug register. | |
494 | Thus, for counting the registers required to watch a | |
495 | region, we simply need to increment the count on each | |
496 | iteration. */ | |
497 | retval++; | |
498 | } | |
52b98211 EZ |
499 | else |
500 | { | |
4be83cc2 | 501 | unsigned len_rw = i386_dr_length_and_rw_bits (size, type); |
52b98211 EZ |
502 | |
503 | if (what == WP_INSERT) | |
4be83cc2 | 504 | retval = i386_dr_insert_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 505 | else if (what == WP_REMOVE) |
4be83cc2 | 506 | retval = i386_dr_remove_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 507 | else |
e2e0b3e5 AC |
508 | internal_error (__FILE__, __LINE__, _("\ |
509 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
fc6e2f03 | 510 | (int) what); |
1ced966e PA |
511 | if (retval) |
512 | break; | |
52b98211 | 513 | } |
7fa2737c | 514 | |
52b98211 EZ |
515 | addr += size; |
516 | len -= size; | |
517 | } | |
7fa2737c MK |
518 | |
519 | return retval; | |
52b98211 EZ |
520 | } |
521 | ||
d9305f7f GB |
522 | /* Update the inferior debug registers state, in STATE, with the |
523 | new debug registers state, in NEW_STATE. */ | |
1ced966e | 524 | |
4be83cc2 GB |
525 | void |
526 | i386_dr_update_inferior_debug_regs (struct i386_debug_reg_state *state, | |
527 | struct i386_debug_reg_state *new_state) | |
1ced966e PA |
528 | { |
529 | int i; | |
530 | ||
531 | ALL_DEBUG_REGISTERS (i) | |
532 | { | |
4403d8e9 | 533 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (state, i)) |
131aa0d4 | 534 | i386_dr_low_set_addr (new_state, i); |
1ced966e | 535 | else |
4403d8e9 | 536 | gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); |
1ced966e PA |
537 | } |
538 | ||
4403d8e9 | 539 | if (new_state->dr_control_mirror != state->dr_control_mirror) |
131aa0d4 | 540 | i386_dr_low_set_control (new_state); |
1ced966e | 541 | |
4403d8e9 | 542 | *state = *new_state; |
1ced966e PA |
543 | } |
544 | ||
52b98211 EZ |
545 | /* Insert a watchpoint to watch a memory region which starts at |
546 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
547 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
7fa2737c | 548 | |
9bb9e8ad | 549 | static int |
7bb99c53 TT |
550 | i386_insert_watchpoint (struct target_ops *self, |
551 | CORE_ADDR addr, int len, int type, | |
0cf6dd15 | 552 | struct expression *cond) |
52b98211 | 553 | { |
26cb8b7c PA |
554 | struct i386_debug_reg_state *state |
555 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
52b98211 | 556 | int retval; |
1ced966e PA |
557 | /* Work on a local copy of the debug registers, and on success, |
558 | commit the change back to the inferior. */ | |
4403d8e9 | 559 | struct i386_debug_reg_state local_state = *state; |
52b98211 | 560 | |
85d721b8 PA |
561 | if (type == hw_read) |
562 | return 1; /* unsupported */ | |
563 | ||
fc6e2f03 GB |
564 | if (((len != 1 && len != 2 && len != 4) |
565 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
e906b9a3 | 566 | || addr % len != 0) |
fc6e2f03 GB |
567 | { |
568 | retval = i386_handle_nonaligned_watchpoint (&local_state, | |
569 | WP_INSERT, | |
570 | addr, len, type); | |
571 | } | |
52b98211 EZ |
572 | else |
573 | { | |
4be83cc2 | 574 | unsigned len_rw = i386_dr_length_and_rw_bits (len, type); |
52b98211 | 575 | |
4be83cc2 | 576 | retval = i386_dr_insert_aligned_watchpoint (&local_state, |
1ced966e | 577 | addr, len_rw); |
52b98211 EZ |
578 | } |
579 | ||
1ced966e | 580 | if (retval == 0) |
4be83cc2 | 581 | i386_dr_update_inferior_debug_regs (state, &local_state); |
1ced966e | 582 | |
ea008da4 | 583 | if (debug_hw_points) |
4be83cc2 | 584 | i386_dr_show (state, "insert_watchpoint", addr, len, type); |
52b98211 EZ |
585 | |
586 | return retval; | |
587 | } | |
588 | ||
589 | /* Remove a watchpoint that watched the memory region which starts at | |
590 | address ADDR, whose length is LEN bytes, and for accesses of the | |
591 | type TYPE. Return 0 on success, -1 on failure. */ | |
9bb9e8ad | 592 | static int |
11b5219a TT |
593 | i386_remove_watchpoint (struct target_ops *self, |
594 | CORE_ADDR addr, int len, int type, | |
0cf6dd15 | 595 | struct expression *cond) |
52b98211 | 596 | { |
26cb8b7c PA |
597 | struct i386_debug_reg_state *state |
598 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
52b98211 | 599 | int retval; |
1ced966e PA |
600 | /* Work on a local copy of the debug registers, and on success, |
601 | commit the change back to the inferior. */ | |
4403d8e9 | 602 | struct i386_debug_reg_state local_state = *state; |
52b98211 | 603 | |
fc6e2f03 GB |
604 | if (((len != 1 && len != 2 && len != 4) |
605 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
e906b9a3 | 606 | || addr % len != 0) |
fc6e2f03 GB |
607 | { |
608 | retval = i386_handle_nonaligned_watchpoint (&local_state, | |
609 | WP_REMOVE, | |
610 | addr, len, type); | |
611 | } | |
52b98211 EZ |
612 | else |
613 | { | |
4be83cc2 | 614 | unsigned len_rw = i386_dr_length_and_rw_bits (len, type); |
52b98211 | 615 | |
4be83cc2 | 616 | retval = i386_dr_remove_aligned_watchpoint (&local_state, |
1ced966e | 617 | addr, len_rw); |
52b98211 EZ |
618 | } |
619 | ||
1ced966e | 620 | if (retval == 0) |
4be83cc2 | 621 | i386_dr_update_inferior_debug_regs (state, &local_state); |
1ced966e | 622 | |
ea008da4 | 623 | if (debug_hw_points) |
4be83cc2 | 624 | i386_dr_show (state, "remove_watchpoint", addr, len, type); |
52b98211 EZ |
625 | |
626 | return retval; | |
627 | } | |
628 | ||
629 | /* Return non-zero if we can watch a memory region that starts at | |
630 | address ADDR and whose length is LEN bytes. */ | |
7fa2737c | 631 | |
9bb9e8ad | 632 | static int |
31568a15 TT |
633 | i386_region_ok_for_watchpoint (struct target_ops *self, |
634 | CORE_ADDR addr, int len) | |
52b98211 | 635 | { |
26cb8b7c PA |
636 | struct i386_debug_reg_state *state |
637 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
7fa2737c MK |
638 | int nregs; |
639 | ||
52b98211 EZ |
640 | /* Compute how many aligned watchpoints we would need to cover this |
641 | region. */ | |
fc6e2f03 GB |
642 | nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT, |
643 | addr, len, hw_write); | |
52b98211 EZ |
644 | return nregs <= DR_NADDR ? 1 : 0; |
645 | } | |
646 | ||
6e62758f GB |
647 | /* If the inferior has some break/watchpoint that triggered, set the |
648 | address associated with that break/watchpoint and return non-zero. | |
4aa7a7f5 | 649 | Otherwise, return zero. */ |
7fa2737c | 650 | |
9bb9e8ad | 651 | static int |
c03374d5 | 652 | i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) |
52b98211 | 653 | { |
26cb8b7c PA |
654 | struct i386_debug_reg_state *state |
655 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
7fa2737c | 656 | CORE_ADDR addr = 0; |
52b98211 | 657 | int i; |
4aa7a7f5 | 658 | int rc = 0; |
7b50312a PA |
659 | /* The current thread's DR_STATUS. We always need to read this to |
660 | check whether some watchpoint caused the trap. */ | |
1ced966e | 661 | unsigned status; |
7b50312a PA |
662 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a |
663 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
664 | unnecessary extra syscall when no watchpoint triggered. */ | |
665 | int control_p = 0; | |
666 | unsigned control = 0; | |
667 | ||
668 | /* In non-stop/async, threads can be running while we change the | |
6e62758f GB |
669 | global dr_mirror (and friends). Say, we set a watchpoint, and |
670 | let threads resume. Now, say you delete the watchpoint, or | |
671 | add/remove watchpoints such that dr_mirror changes while threads | |
672 | are running. On targets that support non-stop, | |
673 | inserting/deleting watchpoints updates the global dr_mirror only. | |
674 | It does not update the real thread's debug registers; that's only | |
675 | done prior to resume. Instead, if threads are running when the | |
676 | mirror changes, a temporary and transparent stop on all threads | |
677 | is forced so they can get their copy of the debug registers | |
678 | updated on re-resume. Now, say, a thread hit a watchpoint before | |
679 | having been updated with the new dr_mirror contents, and we | |
680 | haven't yet handled the corresponding SIGTRAP. If we trusted | |
681 | dr_mirror below, we'd mistake the real trapped address (from the | |
682 | last time we had updated debug registers in the thread) with | |
683 | whatever was currently in dr_mirror. So to fix this, dr_mirror | |
684 | always represents intention, what we _want_ threads to have in | |
685 | debug registers. To get at the address and cause of the trap, we | |
686 | need to read the state the thread still has in its debug | |
687 | registers. | |
7b50312a PA |
688 | |
689 | In sum, always get the current debug register values the current | |
690 | thread has, instead of trusting the global mirror. If the thread | |
691 | was running when we last changed watchpoints, the mirror no | |
692 | longer represents what was set in this thread's debug | |
693 | registers. */ | |
131aa0d4 | 694 | status = i386_dr_low_get_status (); |
52b98211 | 695 | |
fc6e2f03 | 696 | ALL_DEBUG_REGISTERS (i) |
52b98211 | 697 | { |
7b50312a PA |
698 | if (!I386_DR_WATCH_HIT (status, i)) |
699 | continue; | |
700 | ||
701 | if (!control_p) | |
702 | { | |
131aa0d4 | 703 | control = i386_dr_low_get_control (); |
7b50312a PA |
704 | control_p = 1; |
705 | } | |
706 | ||
707 | /* This second condition makes sure DRi is set up for a data | |
708 | watchpoint, not a hardware breakpoint. The reason is that | |
709 | GDB doesn't call the target_stopped_data_address method | |
710 | except for data watchpoints. In other words, I'm being | |
711 | paranoiac. */ | |
712 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
52b98211 | 713 | { |
131aa0d4 | 714 | addr = i386_dr_low_get_addr (i); |
4aa7a7f5 | 715 | rc = 1; |
ea008da4 | 716 | if (debug_hw_points) |
4be83cc2 | 717 | i386_dr_show (state, "watchpoint_hit", addr, -1, hw_write); |
52b98211 EZ |
718 | } |
719 | } | |
fc6e2f03 | 720 | |
ea008da4 | 721 | if (debug_hw_points && addr == 0) |
4be83cc2 | 722 | i386_dr_show (state, "stopped_data_addr", 0, 0, hw_write); |
52b98211 | 723 | |
4aa7a7f5 JJ |
724 | if (rc) |
725 | *addr_p = addr; | |
726 | return rc; | |
727 | } | |
728 | ||
6e62758f GB |
729 | /* Return non-zero if the inferior has some watchpoint that triggered. |
730 | Otherwise return zero. */ | |
731 | ||
9bb9e8ad | 732 | static int |
6a109b6b | 733 | i386_stopped_by_watchpoint (struct target_ops *ops) |
4aa7a7f5 JJ |
734 | { |
735 | CORE_ADDR addr = 0; | |
6a109b6b | 736 | return i386_stopped_data_address (ops, &addr); |
52b98211 EZ |
737 | } |
738 | ||
8181d85f DJ |
739 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
740 | Return 0 on success, EBUSY on failure. */ | |
9bb9e8ad | 741 | static int |
23a26771 | 742 | i386_insert_hw_breakpoint (struct target_ops *self, struct gdbarch *gdbarch, |
a6d9a66e | 743 | struct bp_target_info *bp_tgt) |
52b98211 | 744 | { |
26cb8b7c PA |
745 | struct i386_debug_reg_state *state |
746 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
4be83cc2 | 747 | unsigned len_rw = i386_dr_length_and_rw_bits (1, hw_execute); |
8181d85f | 748 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
749 | /* Work on a local copy of the debug registers, and on success, |
750 | commit the change back to the inferior. */ | |
4403d8e9 | 751 | struct i386_debug_reg_state local_state = *state; |
4be83cc2 GB |
752 | int retval = i386_dr_insert_aligned_watchpoint (&local_state, |
753 | addr, | |
754 | len_rw) ? EBUSY : 0; | |
52b98211 | 755 | |
edcc485a | 756 | if (retval == 0) |
4be83cc2 | 757 | i386_dr_update_inferior_debug_regs (state, &local_state); |
edcc485a | 758 | |
ea008da4 | 759 | if (debug_hw_points) |
4be83cc2 | 760 | i386_dr_show (state, "insert_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
761 | |
762 | return retval; | |
763 | } | |
764 | ||
8181d85f DJ |
765 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
766 | Return 0 on success, -1 on failure. */ | |
7fa2737c | 767 | |
9bb9e8ad | 768 | static int |
a64dc96c | 769 | i386_remove_hw_breakpoint (struct target_ops *self, struct gdbarch *gdbarch, |
a6d9a66e | 770 | struct bp_target_info *bp_tgt) |
52b98211 | 771 | { |
26cb8b7c PA |
772 | struct i386_debug_reg_state *state |
773 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
4be83cc2 | 774 | unsigned len_rw = i386_dr_length_and_rw_bits (1, hw_execute); |
8181d85f | 775 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
776 | /* Work on a local copy of the debug registers, and on success, |
777 | commit the change back to the inferior. */ | |
4403d8e9 | 778 | struct i386_debug_reg_state local_state = *state; |
4be83cc2 GB |
779 | int retval = i386_dr_remove_aligned_watchpoint (&local_state, |
780 | addr, len_rw); | |
52b98211 | 781 | |
edcc485a | 782 | if (retval == 0) |
4be83cc2 | 783 | i386_dr_update_inferior_debug_regs (state, &local_state); |
edcc485a | 784 | |
ea008da4 | 785 | if (debug_hw_points) |
4be83cc2 | 786 | i386_dr_show (state, "remove_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
787 | |
788 | return retval; | |
789 | } | |
790 | ||
c03374d5 DJ |
791 | /* Returns the number of hardware watchpoints of type TYPE that we can |
792 | set. Value is positive if we can set CNT watchpoints, zero if | |
793 | setting watchpoints of type TYPE is not supported, and negative if | |
794 | CNT is more than the maximum number of watchpoints of type TYPE | |
795 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
796 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
797 | CNT is the number of such watchpoints used so far (including this | |
798 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
799 | currently enabled. | |
800 | ||
801 | We always return 1 here because we don't have enough information | |
802 | about possible overlap of addresses that they want to watch. As an | |
803 | extreme example, consider the case where all the watchpoints watch | |
804 | the same address and the same region length: then we can handle a | |
805 | virtually unlimited number of watchpoints, due to debug register | |
806 | sharing implemented via reference counts in i386-nat.c. */ | |
807 | ||
808 | static int | |
5461485a TT |
809 | i386_can_use_hw_breakpoint (struct target_ops *self, |
810 | int type, int cnt, int othertype) | |
c03374d5 DJ |
811 | { |
812 | return 1; | |
813 | } | |
814 | ||
9bb9e8ad PM |
815 | static void |
816 | add_show_debug_regs_command (void) | |
817 | { | |
818 | /* A maintenance command to enable printing the internal DRi mirror | |
819 | variables. */ | |
820 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
ea008da4 | 821 | &debug_hw_points, _("\ |
9bb9e8ad PM |
822 | Set whether to show variables that mirror the x86 debug registers."), _("\ |
823 | Show whether to show variables that mirror the x86 debug registers."), _("\ | |
824 | Use \"on\" to enable, \"off\" to disable.\n\ | |
825 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
826 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
827 | triggers a breakpoint or watchpoint."), | |
828 | NULL, | |
829 | NULL, | |
830 | &maintenance_set_cmdlist, | |
831 | &maintenance_show_cmdlist); | |
832 | } | |
833 | ||
834 | /* There are only two global functions left. */ | |
835 | ||
c03374d5 DJ |
836 | void |
837 | i386_use_watchpoints (struct target_ops *t) | |
838 | { | |
839 | /* After a watchpoint trap, the PC points to the instruction after the | |
840 | one that caused the trap. Therefore we don't need to step over it. | |
841 | But we do need to reset the status register to avoid another trap. */ | |
842 | t->to_have_continuable_watchpoint = 1; | |
843 | ||
844 | t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; | |
845 | t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; | |
846 | t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; | |
847 | t->to_stopped_data_address = i386_stopped_data_address; | |
848 | t->to_insert_watchpoint = i386_insert_watchpoint; | |
849 | t->to_remove_watchpoint = i386_remove_watchpoint; | |
850 | t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; | |
851 | t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; | |
852 | } | |
853 | ||
52b98211 | 854 | void |
9bb9e8ad | 855 | i386_set_debug_register_length (int len) |
52b98211 | 856 | { |
9bb9e8ad PM |
857 | /* This function should be called only once for each native target. */ |
858 | gdb_assert (i386_dr_low.debug_register_length == 0); | |
859 | gdb_assert (len == 4 || len == 8); | |
860 | i386_dr_low.debug_register_length = len; | |
861 | add_show_debug_regs_command (); | |
52b98211 | 862 | } |