Commit | Line | Data |
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7fa2737c MK |
1 | /* Native-dependent code for the i386. |
2 | ||
ecd75fc8 | 3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. |
52b98211 EZ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
52b98211 EZ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
52b98211 EZ |
19 | |
20 | #include "defs.h" | |
0baeab03 | 21 | #include "i386-nat.h" |
52b98211 EZ |
22 | #include "breakpoint.h" |
23 | #include "command.h" | |
24 | #include "gdbcmd.h" | |
c03374d5 | 25 | #include "target.h" |
9bb9e8ad | 26 | #include "gdb_assert.h" |
4403d8e9 | 27 | #include "inferior.h" |
52b98211 | 28 | |
7fa2737c | 29 | /* Support for hardware watchpoints and breakpoints using the i386 |
52b98211 EZ |
30 | debug registers. |
31 | ||
32 | This provides several functions for inserting and removing | |
7fa2737c MK |
33 | hardware-assisted breakpoints and watchpoints, testing if one or |
34 | more of the watchpoints triggered and at what address, checking | |
35 | whether a given region can be watched, etc. | |
36 | ||
7fa2737c MK |
37 | The functions below implement debug registers sharing by reference |
38 | counts, and allow to watch regions up to 16 bytes long. */ | |
52b98211 | 39 | |
1b6d4134 GB |
40 | /* Function used for printing mirrored debug registers. */ |
41 | #define debug_printf(fmt, args...) \ | |
42 | fprintf_unfiltered (gdb_stdlog, fmt, ##args); | |
43 | ||
6e62758f | 44 | /* Low-level function vector. */ |
9bb9e8ad PM |
45 | struct i386_dr_low_type i386_dr_low; |
46 | ||
1b6d4134 GB |
47 | /* Debug register size, in bytes. */ |
48 | #define i386_get_debug_register_length() \ | |
49 | (i386_dr_low.debug_register_length) | |
50 | ||
e906b9a3 | 51 | /* Support for 8-byte wide hw watchpoints. */ |
1b6d4134 | 52 | #define TARGET_HAS_DR_LEN_8 (i386_get_debug_register_length () == 8) |
e906b9a3 | 53 | |
52b98211 EZ |
54 | /* DR7 Debug Control register fields. */ |
55 | ||
56 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
57 | #define DR_CONTROL_SHIFT 16 | |
58 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
59 | #define DR_CONTROL_SIZE 4 | |
60 | ||
61 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
7fa2737c MK |
62 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ |
63 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
64 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
52b98211 EZ |
65 | |
66 | /* This is here for completeness. No platform supports this | |
7fa2737c | 67 | functionality yet (as of March 2001). Note that the DE flag in the |
52b98211 EZ |
68 | CR4 register needs to be set to support this. */ |
69 | #ifndef DR_RW_IORW | |
7fa2737c | 70 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ |
52b98211 EZ |
71 | #endif |
72 | ||
73 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
74 | is so we could OR this with the read/write field defined above. */ | |
7fa2737c MK |
75 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ |
76 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
77 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
78 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
52b98211 EZ |
79 | |
80 | /* Local and Global Enable flags in DR7. | |
81 | ||
82 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
83 | enabled only for the current task; the processor automatically | |
7fa2737c MK |
84 | clears this flag on every task switch. When the Global Enable flag |
85 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
86 | processor never clears this flag. | |
52b98211 EZ |
87 | |
88 | Currently, all watchpoint are locally enabled. If you need to | |
89 | enable them globally, read the comment which pertains to this in | |
90 | i386_insert_aligned_watchpoint below. */ | |
7fa2737c MK |
91 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
92 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
93 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
52b98211 EZ |
94 | |
95 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
96 | flags). These are only required on i386, to allow detection of the | |
97 | exact instruction which caused a watchpoint to break; i486 and | |
98 | later processors do that automatically. We set these flags for | |
7fa2737c | 99 | backwards compatibility. */ |
52b98211 | 100 | #define DR_LOCAL_SLOWDOWN (0x100) |
fc6e2f03 | 101 | #define DR_GLOBAL_SLOWDOWN (0x200) |
52b98211 EZ |
102 | |
103 | /* Fields reserved by Intel. This includes the GD (General Detect | |
104 | Enable) flag, which causes a debug exception to be generated when a | |
105 | MOV instruction accesses one of the debug registers. | |
106 | ||
107 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
108 | #define DR_CONTROL_RESERVED (0xFC00) | |
109 | ||
110 | /* Auxiliary helper macros. */ | |
111 | ||
112 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
7fa2737c | 113 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
52b98211 EZ |
114 | |
115 | /* The I'th debug register is vacant if its Local and Global Enable | |
116 | bits are reset in the Debug Control register. */ | |
fc6e2f03 | 117 | #define I386_DR_VACANT(state, i) \ |
1ced966e | 118 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) |
52b98211 EZ |
119 | |
120 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
121 | #define I386_DR_LOCAL_ENABLE(state, i) \ |
122 | do { \ | |
123 | (state)->dr_control_mirror |= \ | |
124 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
125 | } while (0) | |
52b98211 EZ |
126 | |
127 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
128 | #define I386_DR_GLOBAL_ENABLE(state, i) \ |
129 | do { \ | |
130 | (state)->dr_control_mirror |= \ | |
131 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
132 | } while (0) | |
52b98211 EZ |
133 | |
134 | /* Disable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
135 | #define I386_DR_DISABLE(state, i) \ |
136 | do { \ | |
137 | (state)->dr_control_mirror &= \ | |
138 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
139 | } while (0) | |
52b98211 EZ |
140 | |
141 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e | 142 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ |
52b98211 | 143 | do { \ |
1ced966e PA |
144 | (state)->dr_control_mirror &= \ |
145 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
146 | (state)->dr_control_mirror |= \ | |
147 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
52b98211 EZ |
148 | } while (0) |
149 | ||
150 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e PA |
151 | #define I386_DR_GET_RW_LEN(dr7, i) \ |
152 | (((dr7) \ | |
153 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
52b98211 EZ |
154 | |
155 | /* Did the watchpoint whose address is in the I'th register break? */ | |
1ced966e | 156 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
52b98211 EZ |
157 | |
158 | /* A macro to loop over all debug registers. */ | |
159 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) | |
160 | ||
26cb8b7c PA |
161 | /* Per-process data. We don't bind this to a per-inferior registry |
162 | because of targets like x86 GNU/Linux that need to keep track of | |
163 | processes that aren't bound to any inferior (e.g., fork children, | |
164 | checkpoints). */ | |
1ced966e | 165 | |
26cb8b7c | 166 | struct i386_process_info |
1ced966e | 167 | { |
26cb8b7c PA |
168 | /* Linked list. */ |
169 | struct i386_process_info *next; | |
1ced966e | 170 | |
26cb8b7c PA |
171 | /* The process identifier. */ |
172 | pid_t pid; | |
4403d8e9 | 173 | |
26cb8b7c | 174 | /* Copy of i386 hardware debug registers. */ |
4403d8e9 JK |
175 | struct i386_debug_reg_state state; |
176 | }; | |
177 | ||
26cb8b7c | 178 | static struct i386_process_info *i386_process_list = NULL; |
d0d8b0c6 | 179 | |
26cb8b7c PA |
180 | /* Find process data for process PID. */ |
181 | ||
182 | static struct i386_process_info * | |
183 | i386_find_process_pid (pid_t pid) | |
d0d8b0c6 | 184 | { |
26cb8b7c PA |
185 | struct i386_process_info *proc; |
186 | ||
187 | for (proc = i386_process_list; proc; proc = proc->next) | |
188 | if (proc->pid == pid) | |
189 | return proc; | |
d0d8b0c6 | 190 | |
26cb8b7c | 191 | return NULL; |
d0d8b0c6 JK |
192 | } |
193 | ||
26cb8b7c PA |
194 | /* Add process data for process PID. Returns newly allocated info |
195 | object. */ | |
4403d8e9 | 196 | |
26cb8b7c PA |
197 | static struct i386_process_info * |
198 | i386_add_process (pid_t pid) | |
4403d8e9 | 199 | { |
26cb8b7c | 200 | struct i386_process_info *proc; |
d0d8b0c6 | 201 | |
26cb8b7c PA |
202 | proc = xcalloc (1, sizeof (*proc)); |
203 | proc->pid = pid; | |
4403d8e9 | 204 | |
26cb8b7c PA |
205 | proc->next = i386_process_list; |
206 | i386_process_list = proc; | |
4403d8e9 | 207 | |
26cb8b7c PA |
208 | return proc; |
209 | } | |
4403d8e9 | 210 | |
26cb8b7c PA |
211 | /* Get data specific info for process PID, creating it if necessary. |
212 | Never returns NULL. */ | |
4403d8e9 | 213 | |
26cb8b7c PA |
214 | static struct i386_process_info * |
215 | i386_process_info_get (pid_t pid) | |
216 | { | |
217 | struct i386_process_info *proc; | |
218 | ||
219 | proc = i386_find_process_pid (pid); | |
220 | if (proc == NULL) | |
221 | proc = i386_add_process (pid); | |
4403d8e9 | 222 | |
26cb8b7c | 223 | return proc; |
4403d8e9 JK |
224 | } |
225 | ||
26cb8b7c | 226 | /* Get debug registers state for process PID. */ |
52b98211 | 227 | |
7b50312a | 228 | struct i386_debug_reg_state * |
26cb8b7c | 229 | i386_debug_reg_state (pid_t pid) |
7b50312a | 230 | { |
26cb8b7c PA |
231 | return &i386_process_info_get (pid)->state; |
232 | } | |
233 | ||
234 | /* See declaration in i386-nat.h. */ | |
235 | ||
236 | void | |
237 | i386_forget_process (pid_t pid) | |
238 | { | |
239 | struct i386_process_info *proc, **proc_link; | |
240 | ||
241 | proc = i386_process_list; | |
242 | proc_link = &i386_process_list; | |
243 | ||
244 | while (proc != NULL) | |
245 | { | |
246 | if (proc->pid == pid) | |
247 | { | |
248 | *proc_link = proc->next; | |
249 | ||
250 | xfree (proc); | |
251 | return; | |
252 | } | |
253 | ||
254 | proc_link = &proc->next; | |
255 | proc = *proc_link; | |
256 | } | |
7b50312a PA |
257 | } |
258 | ||
52b98211 | 259 | /* Whether or not to print the mirrored debug registers. */ |
7fa2737c | 260 | static int maint_show_dr; |
52b98211 EZ |
261 | |
262 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
263 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
264 | ||
52b98211 EZ |
265 | /* Implementation. */ |
266 | ||
7fa2737c MK |
267 | /* Clear the reference counts and forget everything we knew about the |
268 | debug registers. */ | |
269 | ||
52b98211 EZ |
270 | void |
271 | i386_cleanup_dregs (void) | |
272 | { | |
26cb8b7c PA |
273 | /* Starting from scratch has the same effect. */ |
274 | i386_forget_process (ptid_get_pid (inferior_ptid)); | |
52b98211 EZ |
275 | } |
276 | ||
6e62758f | 277 | /* Print the values of the mirrored debug registers. */ |
7fa2737c | 278 | |
52b98211 | 279 | static void |
1ced966e PA |
280 | i386_show_dr (struct i386_debug_reg_state *state, |
281 | const char *func, CORE_ADDR addr, | |
52b98211 EZ |
282 | int len, enum target_hw_bp_type type) |
283 | { | |
284 | int i; | |
285 | ||
1b6d4134 | 286 | debug_printf ("%s", func); |
52b98211 | 287 | if (addr || len) |
1b6d4134 GB |
288 | debug_printf (" (addr=%s, len=%d, type=%s)", |
289 | phex (addr, 8), len, | |
290 | type == hw_write ? "data-write" | |
291 | : (type == hw_read ? "data-read" | |
292 | : (type == hw_access ? "data-read/write" | |
293 | : (type == hw_execute ? "instruction-execute" | |
294 | /* FIXME: if/when I/O read/write | |
295 | watchpoints are supported, add them | |
296 | here. */ | |
297 | : "??unknown??")))); | |
298 | debug_printf (":\n"); | |
299 | debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", | |
300 | phex (state->dr_control_mirror, 8), | |
301 | phex (state->dr_status_mirror, 8)); | |
fc6e2f03 | 302 | ALL_DEBUG_REGISTERS (i) |
52b98211 | 303 | { |
1b6d4134 | 304 | debug_printf ("\ |
7fa2737c | 305 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", |
1b6d4134 GB |
306 | i, phex (state->dr_mirror[i], |
307 | i386_get_debug_register_length ()), | |
308 | state->dr_ref_count[i], | |
309 | i + 1, phex (state->dr_mirror[i + 1], | |
310 | i386_get_debug_register_length ()), | |
311 | state->dr_ref_count[i + 1]); | |
52b98211 EZ |
312 | i++; |
313 | } | |
314 | } | |
315 | ||
316 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
317 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
318 | have the value of 1, 2, or 4. */ | |
319 | ||
52b98211 EZ |
320 | static unsigned |
321 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
322 | { | |
323 | unsigned rw; | |
324 | ||
325 | switch (type) | |
326 | { | |
327 | case hw_execute: | |
328 | rw = DR_RW_EXECUTE; | |
329 | break; | |
330 | case hw_write: | |
331 | rw = DR_RW_WRITE; | |
332 | break; | |
7fa2737c | 333 | case hw_read: |
85d721b8 | 334 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
335 | _("The i386 doesn't support " |
336 | "data-read watchpoints.\n")); | |
52b98211 EZ |
337 | case hw_access: |
338 | rw = DR_RW_READ; | |
339 | break; | |
340 | #if 0 | |
7fa2737c MK |
341 | /* Not yet supported. */ |
342 | case hw_io_access: | |
52b98211 EZ |
343 | rw = DR_RW_IORW; |
344 | break; | |
345 | #endif | |
346 | default: | |
e2e0b3e5 AC |
347 | internal_error (__FILE__, __LINE__, _("\ |
348 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
7fa2737c | 349 | (int) type); |
52b98211 EZ |
350 | } |
351 | ||
352 | switch (len) | |
353 | { | |
52b98211 EZ |
354 | case 1: |
355 | return (DR_LEN_1 | rw); | |
e906b9a3 JS |
356 | case 2: |
357 | return (DR_LEN_2 | rw); | |
358 | case 4: | |
359 | return (DR_LEN_4 | rw); | |
360 | case 8: | |
361 | if (TARGET_HAS_DR_LEN_8) | |
362 | return (DR_LEN_8 | rw); | |
8fbf6b93 | 363 | /* ELSE FALL THROUGH */ |
52b98211 | 364 | default: |
e2e0b3e5 AC |
365 | internal_error (__FILE__, __LINE__, _("\ |
366 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
52b98211 EZ |
367 | } |
368 | } | |
369 | ||
370 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
371 | according to the length of the region to watch. LEN_RW_BITS is the | |
372 | value of the bits from DR7 which describes the length and access | |
373 | type of the region to be watched by this watchpoint. Return 0 on | |
374 | success, -1 on failure. */ | |
7fa2737c | 375 | |
52b98211 | 376 | static int |
1ced966e PA |
377 | i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
378 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
379 | { |
380 | int i; | |
381 | ||
9bb9e8ad PM |
382 | if (!i386_dr_low.set_addr || !i386_dr_low.set_control) |
383 | return -1; | |
384 | ||
52b98211 EZ |
385 | /* First, look for an occupied debug register with the same address |
386 | and the same RW and LEN definitions. If we find one, we can | |
387 | reuse it for this watchpoint as well (and save a register). */ | |
fc6e2f03 | 388 | ALL_DEBUG_REGISTERS (i) |
52b98211 | 389 | { |
1ced966e PA |
390 | if (!I386_DR_VACANT (state, i) |
391 | && state->dr_mirror[i] == addr | |
392 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 393 | { |
1ced966e | 394 | state->dr_ref_count[i]++; |
52b98211 EZ |
395 | return 0; |
396 | } | |
397 | } | |
398 | ||
399 | /* Next, look for a vacant debug register. */ | |
fc6e2f03 | 400 | ALL_DEBUG_REGISTERS (i) |
52b98211 | 401 | { |
1ced966e | 402 | if (I386_DR_VACANT (state, i)) |
52b98211 EZ |
403 | break; |
404 | } | |
405 | ||
406 | /* No more debug registers! */ | |
407 | if (i >= DR_NADDR) | |
408 | return -1; | |
409 | ||
410 | /* Now set up the register I to watch our region. */ | |
411 | ||
412 | /* Record the info in our local mirrored array. */ | |
1ced966e PA |
413 | state->dr_mirror[i] = addr; |
414 | state->dr_ref_count[i] = 1; | |
415 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
52b98211 | 416 | /* Note: we only enable the watchpoint locally, i.e. in the current |
7fa2737c | 417 | task. Currently, no i386 target allows or supports global |
52b98211 EZ |
418 | watchpoints; however, if any target would want that in the |
419 | future, GDB should probably provide a command to control whether | |
420 | to enable watchpoints globally or locally, and the code below | |
421 | should use global or local enable and slow-down flags as | |
422 | appropriate. */ | |
1ced966e PA |
423 | I386_DR_LOCAL_ENABLE (state, i); |
424 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
425 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
a79d3c27 | 426 | |
52b98211 EZ |
427 | return 0; |
428 | } | |
429 | ||
430 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
431 | according to the length of the region to watch. LEN_RW_BITS is the | |
432 | value of the bits from DR7 which describes the length and access | |
433 | type of the region watched by this watchpoint. Return 0 on | |
434 | success, -1 on failure. */ | |
7fa2737c | 435 | |
52b98211 | 436 | static int |
1ced966e PA |
437 | i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
438 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
439 | { |
440 | int i, retval = -1; | |
441 | ||
fc6e2f03 | 442 | ALL_DEBUG_REGISTERS (i) |
52b98211 | 443 | { |
1ced966e PA |
444 | if (!I386_DR_VACANT (state, i) |
445 | && state->dr_mirror[i] == addr | |
446 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 447 | { |
6e62758f | 448 | if (--state->dr_ref_count[i] == 0) /* No longer in use? */ |
52b98211 EZ |
449 | { |
450 | /* Reset our mirror. */ | |
1ced966e PA |
451 | state->dr_mirror[i] = 0; |
452 | I386_DR_DISABLE (state, i); | |
52b98211 EZ |
453 | } |
454 | retval = 0; | |
455 | } | |
456 | } | |
457 | ||
458 | return retval; | |
459 | } | |
460 | ||
461 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
462 | number of debug registers required to watch a region at address | |
463 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
464 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
465 | about the number of registers, or -1 on failure. If WHAT is not a |
466 | valid value, bombs through internal_error. */ | |
467 | ||
52b98211 | 468 | static int |
1ced966e PA |
469 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
470 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
52b98211 EZ |
471 | enum target_hw_bp_type type) |
472 | { | |
1ced966e | 473 | int retval = 0; |
e906b9a3 | 474 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
52b98211 | 475 | |
9b4550ef | 476 | static const int size_try_array[8][8] = |
52b98211 | 477 | { |
7fa2737c MK |
478 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ |
479 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
480 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
481 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
482 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
483 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
484 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
485 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
52b98211 EZ |
486 | }; |
487 | ||
488 | while (len > 0) | |
489 | { | |
7fa2737c | 490 | int align = addr % max_wp_len; |
f2e7c15d | 491 | /* Four (eight on AMD64) is the maximum length a debug register |
e906b9a3 | 492 | can watch. */ |
7fa2737c MK |
493 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); |
494 | int size = size_try_array[try][align]; | |
495 | ||
52b98211 | 496 | if (what == WP_COUNT) |
7fa2737c MK |
497 | { |
498 | /* size_try_array[] is defined such that each iteration | |
499 | through the loop is guaranteed to produce an address and a | |
500 | size that can be watched with a single debug register. | |
501 | Thus, for counting the registers required to watch a | |
502 | region, we simply need to increment the count on each | |
503 | iteration. */ | |
504 | retval++; | |
505 | } | |
52b98211 EZ |
506 | else |
507 | { | |
508 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
509 | ||
510 | if (what == WP_INSERT) | |
1ced966e | 511 | retval = i386_insert_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 512 | else if (what == WP_REMOVE) |
1ced966e | 513 | retval = i386_remove_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 514 | else |
e2e0b3e5 AC |
515 | internal_error (__FILE__, __LINE__, _("\ |
516 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
fc6e2f03 | 517 | (int) what); |
1ced966e PA |
518 | if (retval) |
519 | break; | |
52b98211 | 520 | } |
7fa2737c | 521 | |
52b98211 EZ |
522 | addr += size; |
523 | len -= size; | |
524 | } | |
7fa2737c MK |
525 | |
526 | return retval; | |
52b98211 EZ |
527 | } |
528 | ||
1ced966e PA |
529 | /* Update the inferior's debug registers with the new debug registers |
530 | state, in NEW_STATE, and then update our local mirror to match. */ | |
531 | ||
532 | static void | |
533 | i386_update_inferior_debug_regs (struct i386_debug_reg_state *new_state) | |
534 | { | |
26cb8b7c PA |
535 | struct i386_debug_reg_state *state |
536 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
1ced966e PA |
537 | int i; |
538 | ||
539 | ALL_DEBUG_REGISTERS (i) | |
540 | { | |
4403d8e9 | 541 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (state, i)) |
7b50312a | 542 | i386_dr_low.set_addr (i, new_state->dr_mirror[i]); |
1ced966e | 543 | else |
4403d8e9 | 544 | gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); |
1ced966e PA |
545 | } |
546 | ||
4403d8e9 | 547 | if (new_state->dr_control_mirror != state->dr_control_mirror) |
1ced966e PA |
548 | i386_dr_low.set_control (new_state->dr_control_mirror); |
549 | ||
4403d8e9 | 550 | *state = *new_state; |
1ced966e PA |
551 | } |
552 | ||
52b98211 EZ |
553 | /* Insert a watchpoint to watch a memory region which starts at |
554 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
555 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
7fa2737c | 556 | |
9bb9e8ad | 557 | static int |
7bb99c53 TT |
558 | i386_insert_watchpoint (struct target_ops *self, |
559 | CORE_ADDR addr, int len, int type, | |
0cf6dd15 | 560 | struct expression *cond) |
52b98211 | 561 | { |
26cb8b7c PA |
562 | struct i386_debug_reg_state *state |
563 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
52b98211 | 564 | int retval; |
1ced966e PA |
565 | /* Work on a local copy of the debug registers, and on success, |
566 | commit the change back to the inferior. */ | |
4403d8e9 | 567 | struct i386_debug_reg_state local_state = *state; |
52b98211 | 568 | |
85d721b8 PA |
569 | if (type == hw_read) |
570 | return 1; /* unsupported */ | |
571 | ||
fc6e2f03 GB |
572 | if (((len != 1 && len != 2 && len != 4) |
573 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
e906b9a3 | 574 | || addr % len != 0) |
fc6e2f03 GB |
575 | { |
576 | retval = i386_handle_nonaligned_watchpoint (&local_state, | |
577 | WP_INSERT, | |
578 | addr, len, type); | |
579 | } | |
52b98211 EZ |
580 | else |
581 | { | |
582 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
583 | ||
1ced966e PA |
584 | retval = i386_insert_aligned_watchpoint (&local_state, |
585 | addr, len_rw); | |
52b98211 EZ |
586 | } |
587 | ||
1ced966e PA |
588 | if (retval == 0) |
589 | i386_update_inferior_debug_regs (&local_state); | |
590 | ||
52b98211 | 591 | if (maint_show_dr) |
4403d8e9 | 592 | i386_show_dr (state, "insert_watchpoint", addr, len, type); |
52b98211 EZ |
593 | |
594 | return retval; | |
595 | } | |
596 | ||
597 | /* Remove a watchpoint that watched the memory region which starts at | |
598 | address ADDR, whose length is LEN bytes, and for accesses of the | |
599 | type TYPE. Return 0 on success, -1 on failure. */ | |
9bb9e8ad | 600 | static int |
11b5219a TT |
601 | i386_remove_watchpoint (struct target_ops *self, |
602 | CORE_ADDR addr, int len, int type, | |
0cf6dd15 | 603 | struct expression *cond) |
52b98211 | 604 | { |
26cb8b7c PA |
605 | struct i386_debug_reg_state *state |
606 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
52b98211 | 607 | int retval; |
1ced966e PA |
608 | /* Work on a local copy of the debug registers, and on success, |
609 | commit the change back to the inferior. */ | |
4403d8e9 | 610 | struct i386_debug_reg_state local_state = *state; |
52b98211 | 611 | |
fc6e2f03 GB |
612 | if (((len != 1 && len != 2 && len != 4) |
613 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
e906b9a3 | 614 | || addr % len != 0) |
fc6e2f03 GB |
615 | { |
616 | retval = i386_handle_nonaligned_watchpoint (&local_state, | |
617 | WP_REMOVE, | |
618 | addr, len, type); | |
619 | } | |
52b98211 EZ |
620 | else |
621 | { | |
622 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
623 | ||
1ced966e PA |
624 | retval = i386_remove_aligned_watchpoint (&local_state, |
625 | addr, len_rw); | |
52b98211 EZ |
626 | } |
627 | ||
1ced966e PA |
628 | if (retval == 0) |
629 | i386_update_inferior_debug_regs (&local_state); | |
630 | ||
52b98211 | 631 | if (maint_show_dr) |
4403d8e9 | 632 | i386_show_dr (state, "remove_watchpoint", addr, len, type); |
52b98211 EZ |
633 | |
634 | return retval; | |
635 | } | |
636 | ||
637 | /* Return non-zero if we can watch a memory region that starts at | |
638 | address ADDR and whose length is LEN bytes. */ | |
7fa2737c | 639 | |
9bb9e8ad | 640 | static int |
31568a15 TT |
641 | i386_region_ok_for_watchpoint (struct target_ops *self, |
642 | CORE_ADDR addr, int len) | |
52b98211 | 643 | { |
26cb8b7c PA |
644 | struct i386_debug_reg_state *state |
645 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
7fa2737c MK |
646 | int nregs; |
647 | ||
52b98211 EZ |
648 | /* Compute how many aligned watchpoints we would need to cover this |
649 | region. */ | |
fc6e2f03 GB |
650 | nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT, |
651 | addr, len, hw_write); | |
52b98211 EZ |
652 | return nregs <= DR_NADDR ? 1 : 0; |
653 | } | |
654 | ||
6e62758f GB |
655 | /* If the inferior has some break/watchpoint that triggered, set the |
656 | address associated with that break/watchpoint and return non-zero. | |
4aa7a7f5 | 657 | Otherwise, return zero. */ |
7fa2737c | 658 | |
9bb9e8ad | 659 | static int |
c03374d5 | 660 | i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) |
52b98211 | 661 | { |
26cb8b7c PA |
662 | struct i386_debug_reg_state *state |
663 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
7fa2737c | 664 | CORE_ADDR addr = 0; |
52b98211 | 665 | int i; |
4aa7a7f5 | 666 | int rc = 0; |
7b50312a PA |
667 | /* The current thread's DR_STATUS. We always need to read this to |
668 | check whether some watchpoint caused the trap. */ | |
1ced966e | 669 | unsigned status; |
7b50312a PA |
670 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a |
671 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
672 | unnecessary extra syscall when no watchpoint triggered. */ | |
673 | int control_p = 0; | |
674 | unsigned control = 0; | |
675 | ||
676 | /* In non-stop/async, threads can be running while we change the | |
6e62758f GB |
677 | global dr_mirror (and friends). Say, we set a watchpoint, and |
678 | let threads resume. Now, say you delete the watchpoint, or | |
679 | add/remove watchpoints such that dr_mirror changes while threads | |
680 | are running. On targets that support non-stop, | |
681 | inserting/deleting watchpoints updates the global dr_mirror only. | |
682 | It does not update the real thread's debug registers; that's only | |
683 | done prior to resume. Instead, if threads are running when the | |
684 | mirror changes, a temporary and transparent stop on all threads | |
685 | is forced so they can get their copy of the debug registers | |
686 | updated on re-resume. Now, say, a thread hit a watchpoint before | |
687 | having been updated with the new dr_mirror contents, and we | |
688 | haven't yet handled the corresponding SIGTRAP. If we trusted | |
689 | dr_mirror below, we'd mistake the real trapped address (from the | |
690 | last time we had updated debug registers in the thread) with | |
691 | whatever was currently in dr_mirror. So to fix this, dr_mirror | |
692 | always represents intention, what we _want_ threads to have in | |
693 | debug registers. To get at the address and cause of the trap, we | |
694 | need to read the state the thread still has in its debug | |
695 | registers. | |
7b50312a PA |
696 | |
697 | In sum, always get the current debug register values the current | |
698 | thread has, instead of trusting the global mirror. If the thread | |
699 | was running when we last changed watchpoints, the mirror no | |
700 | longer represents what was set in this thread's debug | |
701 | registers. */ | |
702 | status = i386_dr_low.get_status (); | |
52b98211 | 703 | |
fc6e2f03 | 704 | ALL_DEBUG_REGISTERS (i) |
52b98211 | 705 | { |
7b50312a PA |
706 | if (!I386_DR_WATCH_HIT (status, i)) |
707 | continue; | |
708 | ||
709 | if (!control_p) | |
710 | { | |
711 | control = i386_dr_low.get_control (); | |
712 | control_p = 1; | |
713 | } | |
714 | ||
715 | /* This second condition makes sure DRi is set up for a data | |
716 | watchpoint, not a hardware breakpoint. The reason is that | |
717 | GDB doesn't call the target_stopped_data_address method | |
718 | except for data watchpoints. In other words, I'm being | |
719 | paranoiac. */ | |
720 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
52b98211 | 721 | { |
7b50312a | 722 | addr = i386_dr_low.get_addr (i); |
4aa7a7f5 | 723 | rc = 1; |
52b98211 | 724 | if (maint_show_dr) |
4403d8e9 | 725 | i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write); |
52b98211 EZ |
726 | } |
727 | } | |
fc6e2f03 | 728 | |
7fa2737c | 729 | if (maint_show_dr && addr == 0) |
4403d8e9 | 730 | i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write); |
52b98211 | 731 | |
4aa7a7f5 JJ |
732 | if (rc) |
733 | *addr_p = addr; | |
734 | return rc; | |
735 | } | |
736 | ||
6e62758f GB |
737 | /* Return non-zero if the inferior has some watchpoint that triggered. |
738 | Otherwise return zero. */ | |
739 | ||
9bb9e8ad | 740 | static int |
6a109b6b | 741 | i386_stopped_by_watchpoint (struct target_ops *ops) |
4aa7a7f5 JJ |
742 | { |
743 | CORE_ADDR addr = 0; | |
6a109b6b | 744 | return i386_stopped_data_address (ops, &addr); |
52b98211 EZ |
745 | } |
746 | ||
8181d85f DJ |
747 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
748 | Return 0 on success, EBUSY on failure. */ | |
9bb9e8ad | 749 | static int |
23a26771 | 750 | i386_insert_hw_breakpoint (struct target_ops *self, struct gdbarch *gdbarch, |
a6d9a66e | 751 | struct bp_target_info *bp_tgt) |
52b98211 | 752 | { |
26cb8b7c PA |
753 | struct i386_debug_reg_state *state |
754 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
52b98211 | 755 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); |
8181d85f | 756 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
757 | /* Work on a local copy of the debug registers, and on success, |
758 | commit the change back to the inferior. */ | |
4403d8e9 | 759 | struct i386_debug_reg_state local_state = *state; |
edcc485a | 760 | int retval = i386_insert_aligned_watchpoint (&local_state, |
1ced966e | 761 | addr, len_rw) ? EBUSY : 0; |
52b98211 | 762 | |
edcc485a MR |
763 | if (retval == 0) |
764 | i386_update_inferior_debug_regs (&local_state); | |
765 | ||
52b98211 | 766 | if (maint_show_dr) |
4403d8e9 | 767 | i386_show_dr (state, "insert_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
768 | |
769 | return retval; | |
770 | } | |
771 | ||
8181d85f DJ |
772 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
773 | Return 0 on success, -1 on failure. */ | |
7fa2737c | 774 | |
9bb9e8ad | 775 | static int |
a64dc96c | 776 | i386_remove_hw_breakpoint (struct target_ops *self, struct gdbarch *gdbarch, |
a6d9a66e | 777 | struct bp_target_info *bp_tgt) |
52b98211 | 778 | { |
26cb8b7c PA |
779 | struct i386_debug_reg_state *state |
780 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
52b98211 | 781 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); |
8181d85f | 782 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
783 | /* Work on a local copy of the debug registers, and on success, |
784 | commit the change back to the inferior. */ | |
4403d8e9 | 785 | struct i386_debug_reg_state local_state = *state; |
edcc485a | 786 | int retval = i386_remove_aligned_watchpoint (&local_state, |
1ced966e | 787 | addr, len_rw); |
52b98211 | 788 | |
edcc485a MR |
789 | if (retval == 0) |
790 | i386_update_inferior_debug_regs (&local_state); | |
791 | ||
52b98211 | 792 | if (maint_show_dr) |
4403d8e9 | 793 | i386_show_dr (state, "remove_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
794 | |
795 | return retval; | |
796 | } | |
797 | ||
c03374d5 DJ |
798 | /* Returns the number of hardware watchpoints of type TYPE that we can |
799 | set. Value is positive if we can set CNT watchpoints, zero if | |
800 | setting watchpoints of type TYPE is not supported, and negative if | |
801 | CNT is more than the maximum number of watchpoints of type TYPE | |
802 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
803 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
804 | CNT is the number of such watchpoints used so far (including this | |
805 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
806 | currently enabled. | |
807 | ||
808 | We always return 1 here because we don't have enough information | |
809 | about possible overlap of addresses that they want to watch. As an | |
810 | extreme example, consider the case where all the watchpoints watch | |
811 | the same address and the same region length: then we can handle a | |
812 | virtually unlimited number of watchpoints, due to debug register | |
813 | sharing implemented via reference counts in i386-nat.c. */ | |
814 | ||
815 | static int | |
5461485a TT |
816 | i386_can_use_hw_breakpoint (struct target_ops *self, |
817 | int type, int cnt, int othertype) | |
c03374d5 DJ |
818 | { |
819 | return 1; | |
820 | } | |
821 | ||
9bb9e8ad PM |
822 | static void |
823 | add_show_debug_regs_command (void) | |
824 | { | |
825 | /* A maintenance command to enable printing the internal DRi mirror | |
826 | variables. */ | |
827 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
828 | &maint_show_dr, _("\ | |
829 | Set whether to show variables that mirror the x86 debug registers."), _("\ | |
830 | Show whether to show variables that mirror the x86 debug registers."), _("\ | |
831 | Use \"on\" to enable, \"off\" to disable.\n\ | |
832 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
833 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
834 | triggers a breakpoint or watchpoint."), | |
835 | NULL, | |
836 | NULL, | |
837 | &maintenance_set_cmdlist, | |
838 | &maintenance_show_cmdlist); | |
839 | } | |
840 | ||
841 | /* There are only two global functions left. */ | |
842 | ||
c03374d5 DJ |
843 | void |
844 | i386_use_watchpoints (struct target_ops *t) | |
845 | { | |
846 | /* After a watchpoint trap, the PC points to the instruction after the | |
847 | one that caused the trap. Therefore we don't need to step over it. | |
848 | But we do need to reset the status register to avoid another trap. */ | |
849 | t->to_have_continuable_watchpoint = 1; | |
850 | ||
851 | t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; | |
852 | t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; | |
853 | t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; | |
854 | t->to_stopped_data_address = i386_stopped_data_address; | |
855 | t->to_insert_watchpoint = i386_insert_watchpoint; | |
856 | t->to_remove_watchpoint = i386_remove_watchpoint; | |
857 | t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; | |
858 | t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; | |
859 | } | |
860 | ||
52b98211 | 861 | void |
9bb9e8ad | 862 | i386_set_debug_register_length (int len) |
52b98211 | 863 | { |
9bb9e8ad PM |
864 | /* This function should be called only once for each native target. */ |
865 | gdb_assert (i386_dr_low.debug_register_length == 0); | |
866 | gdb_assert (len == 4 || len == 8); | |
867 | i386_dr_low.debug_register_length = len; | |
868 | add_show_debug_regs_command (); | |
52b98211 | 869 | } |