Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
ecd75fc8 | 3 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
45741a9c | 31 | #include "infrun.h" |
acd5c798 | 32 | #include "gdbcmd.h" |
c906108c | 33 | #include "gdbcore.h" |
e6bb342a | 34 | #include "gdbtypes.h" |
dfe01d39 | 35 | #include "objfiles.h" |
acd5c798 MK |
36 | #include "osabi.h" |
37 | #include "regcache.h" | |
38 | #include "reggroups.h" | |
473f17b0 | 39 | #include "regset.h" |
c0d1d883 | 40 | #include "symfile.h" |
c906108c | 41 | #include "symtab.h" |
acd5c798 | 42 | #include "target.h" |
fd0407d6 | 43 | #include "value.h" |
a89aa300 | 44 | #include "dis-asm.h" |
7a697b8d | 45 | #include "disasm.h" |
c8d5aac9 | 46 | #include "remote.h" |
8fbca658 | 47 | #include "exceptions.h" |
d2a7c97a | 48 | #include "i386-tdep.h" |
61113f8b | 49 | #include "i387-tdep.h" |
df7e5265 | 50 | #include "x86-xstate.h" |
d2a7c97a | 51 | |
7ad10968 | 52 | #include "record.h" |
d02ed0bb | 53 | #include "record-full.h" |
7ad10968 HZ |
54 | #include <stdint.h> |
55 | ||
90884b2b | 56 | #include "features/i386/i386.c" |
c131fcee | 57 | #include "features/i386/i386-avx.c" |
1dbcd68c | 58 | #include "features/i386/i386-mpx.c" |
01f9f808 | 59 | #include "features/i386/i386-avx512.c" |
3a13a53b | 60 | #include "features/i386/i386-mmx.c" |
90884b2b | 61 | |
6710bf39 SS |
62 | #include "ax.h" |
63 | #include "ax-gdb.h" | |
64 | ||
55aa24fb SDJ |
65 | #include "stap-probe.h" |
66 | #include "user-regs.h" | |
67 | #include "cli/cli-utils.h" | |
68 | #include "expression.h" | |
69 | #include "parser-defs.h" | |
70 | #include <ctype.h> | |
71 | ||
c4fc7f1b | 72 | /* Register names. */ |
c40e1eab | 73 | |
90884b2b | 74 | static const char *i386_register_names[] = |
fc633446 MK |
75 | { |
76 | "eax", "ecx", "edx", "ebx", | |
77 | "esp", "ebp", "esi", "edi", | |
78 | "eip", "eflags", "cs", "ss", | |
79 | "ds", "es", "fs", "gs", | |
80 | "st0", "st1", "st2", "st3", | |
81 | "st4", "st5", "st6", "st7", | |
82 | "fctrl", "fstat", "ftag", "fiseg", | |
83 | "fioff", "foseg", "fooff", "fop", | |
84 | "xmm0", "xmm1", "xmm2", "xmm3", | |
85 | "xmm4", "xmm5", "xmm6", "xmm7", | |
86 | "mxcsr" | |
87 | }; | |
88 | ||
01f9f808 MS |
89 | static const char *i386_zmm_names[] = |
90 | { | |
91 | "zmm0", "zmm1", "zmm2", "zmm3", | |
92 | "zmm4", "zmm5", "zmm6", "zmm7" | |
93 | }; | |
94 | ||
95 | static const char *i386_zmmh_names[] = | |
96 | { | |
97 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
98 | "zmm4h", "zmm5h", "zmm6h", "zmm7h" | |
99 | }; | |
100 | ||
101 | static const char *i386_k_names[] = | |
102 | { | |
103 | "k0", "k1", "k2", "k3", | |
104 | "k4", "k5", "k6", "k7" | |
105 | }; | |
106 | ||
c131fcee L |
107 | static const char *i386_ymm_names[] = |
108 | { | |
109 | "ymm0", "ymm1", "ymm2", "ymm3", | |
110 | "ymm4", "ymm5", "ymm6", "ymm7", | |
111 | }; | |
112 | ||
113 | static const char *i386_ymmh_names[] = | |
114 | { | |
115 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
116 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
117 | }; | |
118 | ||
1dbcd68c WT |
119 | static const char *i386_mpx_names[] = |
120 | { | |
121 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
122 | }; | |
123 | ||
124 | /* Register names for MPX pseudo-registers. */ | |
125 | ||
126 | static const char *i386_bnd_names[] = | |
127 | { | |
128 | "bnd0", "bnd1", "bnd2", "bnd3" | |
129 | }; | |
130 | ||
c4fc7f1b | 131 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 132 | |
90884b2b | 133 | static const char *i386_mmx_names[] = |
28fc6740 AC |
134 | { |
135 | "mm0", "mm1", "mm2", "mm3", | |
136 | "mm4", "mm5", "mm6", "mm7" | |
137 | }; | |
c40e1eab | 138 | |
1ba53b71 L |
139 | /* Register names for byte pseudo-registers. */ |
140 | ||
141 | static const char *i386_byte_names[] = | |
142 | { | |
143 | "al", "cl", "dl", "bl", | |
144 | "ah", "ch", "dh", "bh" | |
145 | }; | |
146 | ||
147 | /* Register names for word pseudo-registers. */ | |
148 | ||
149 | static const char *i386_word_names[] = | |
150 | { | |
151 | "ax", "cx", "dx", "bx", | |
9cad29ac | 152 | "", "bp", "si", "di" |
1ba53b71 L |
153 | }; |
154 | ||
01f9f808 MS |
155 | /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have |
156 | 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, | |
157 | we have 16 upper ZMM regs that have to be handled differently. */ | |
158 | ||
159 | const int num_lower_zmm_regs = 16; | |
160 | ||
1ba53b71 | 161 | /* MMX register? */ |
c40e1eab | 162 | |
28fc6740 | 163 | static int |
5716833c | 164 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 165 | { |
1ba53b71 L |
166 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
167 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
168 | |
169 | if (mm0_regnum < 0) | |
170 | return 0; | |
171 | ||
1ba53b71 L |
172 | regnum -= mm0_regnum; |
173 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
174 | } | |
175 | ||
176 | /* Byte register? */ | |
177 | ||
178 | int | |
179 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
180 | { | |
181 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
182 | ||
183 | regnum -= tdep->al_regnum; | |
184 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
185 | } | |
186 | ||
187 | /* Word register? */ | |
188 | ||
189 | int | |
190 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
191 | { | |
192 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
193 | ||
194 | regnum -= tdep->ax_regnum; | |
195 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
196 | } | |
197 | ||
198 | /* Dword register? */ | |
199 | ||
200 | int | |
201 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
202 | { | |
203 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
204 | int eax_regnum = tdep->eax_regnum; | |
205 | ||
206 | if (eax_regnum < 0) | |
207 | return 0; | |
208 | ||
209 | regnum -= eax_regnum; | |
210 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
211 | } |
212 | ||
01f9f808 MS |
213 | /* AVX512 register? */ |
214 | ||
215 | int | |
216 | i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
217 | { | |
218 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
219 | int zmm0h_regnum = tdep->zmm0h_regnum; | |
220 | ||
221 | if (zmm0h_regnum < 0) | |
222 | return 0; | |
223 | ||
224 | regnum -= zmm0h_regnum; | |
225 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
226 | } | |
227 | ||
228 | int | |
229 | i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
230 | { | |
231 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
232 | int zmm0_regnum = tdep->zmm0_regnum; | |
233 | ||
234 | if (zmm0_regnum < 0) | |
235 | return 0; | |
236 | ||
237 | regnum -= zmm0_regnum; | |
238 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
239 | } | |
240 | ||
241 | int | |
242 | i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) | |
243 | { | |
244 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
245 | int k0_regnum = tdep->k0_regnum; | |
246 | ||
247 | if (k0_regnum < 0) | |
248 | return 0; | |
249 | ||
250 | regnum -= k0_regnum; | |
251 | return regnum >= 0 && regnum < I387_NUM_K_REGS; | |
252 | } | |
253 | ||
9191d390 | 254 | static int |
c131fcee L |
255 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
256 | { | |
257 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
258 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
259 | ||
260 | if (ymm0h_regnum < 0) | |
261 | return 0; | |
262 | ||
263 | regnum -= ymm0h_regnum; | |
264 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
265 | } | |
266 | ||
267 | /* AVX register? */ | |
268 | ||
269 | int | |
270 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
271 | { | |
272 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
273 | int ymm0_regnum = tdep->ymm0_regnum; | |
274 | ||
275 | if (ymm0_regnum < 0) | |
276 | return 0; | |
277 | ||
278 | regnum -= ymm0_regnum; | |
279 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
280 | } | |
281 | ||
01f9f808 MS |
282 | static int |
283 | i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
284 | { | |
285 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
286 | int ymm16h_regnum = tdep->ymm16h_regnum; | |
287 | ||
288 | if (ymm16h_regnum < 0) | |
289 | return 0; | |
290 | ||
291 | regnum -= ymm16h_regnum; | |
292 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
293 | } | |
294 | ||
295 | int | |
296 | i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
297 | { | |
298 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
299 | int ymm16_regnum = tdep->ymm16_regnum; | |
300 | ||
301 | if (ymm16_regnum < 0) | |
302 | return 0; | |
303 | ||
304 | regnum -= ymm16_regnum; | |
305 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
306 | } | |
307 | ||
1dbcd68c WT |
308 | /* BND register? */ |
309 | ||
310 | int | |
311 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
312 | { | |
313 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
314 | int bnd0_regnum = tdep->bnd0_regnum; | |
315 | ||
316 | if (bnd0_regnum < 0) | |
317 | return 0; | |
318 | ||
319 | regnum -= bnd0_regnum; | |
320 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
321 | } | |
322 | ||
5716833c | 323 | /* SSE register? */ |
23a34459 | 324 | |
c131fcee L |
325 | int |
326 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 327 | { |
5716833c | 328 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 329 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 330 | |
c131fcee | 331 | if (num_xmm_regs == 0) |
5716833c MK |
332 | return 0; |
333 | ||
c131fcee L |
334 | regnum -= I387_XMM0_REGNUM (tdep); |
335 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
336 | } |
337 | ||
01f9f808 MS |
338 | /* XMM_512 register? */ |
339 | ||
340 | int | |
341 | i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
342 | { | |
343 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
344 | int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); | |
345 | ||
346 | if (num_xmm_avx512_regs == 0) | |
347 | return 0; | |
348 | ||
349 | regnum -= I387_XMM16_REGNUM (tdep); | |
350 | return regnum >= 0 && regnum < num_xmm_avx512_regs; | |
351 | } | |
352 | ||
5716833c MK |
353 | static int |
354 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 355 | { |
5716833c MK |
356 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
357 | ||
20a6ec49 | 358 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
359 | return 0; |
360 | ||
20a6ec49 | 361 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
362 | } |
363 | ||
5716833c | 364 | /* FP register? */ |
23a34459 AC |
365 | |
366 | int | |
20a6ec49 | 367 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 368 | { |
20a6ec49 MD |
369 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
370 | ||
371 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
372 | return 0; |
373 | ||
20a6ec49 MD |
374 | return (I387_ST0_REGNUM (tdep) <= regnum |
375 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
376 | } |
377 | ||
378 | int | |
20a6ec49 | 379 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 380 | { |
20a6ec49 MD |
381 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
382 | ||
383 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
384 | return 0; |
385 | ||
20a6ec49 MD |
386 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
387 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
388 | } |
389 | ||
1dbcd68c WT |
390 | /* BNDr (raw) register? */ |
391 | ||
392 | static int | |
393 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
394 | { | |
395 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
396 | ||
397 | if (I387_BND0R_REGNUM (tdep) < 0) | |
398 | return 0; | |
399 | ||
400 | regnum -= tdep->bnd0r_regnum; | |
401 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
402 | } | |
403 | ||
404 | /* BND control register? */ | |
405 | ||
406 | static int | |
407 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
408 | { | |
409 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
410 | ||
411 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
412 | return 0; | |
413 | ||
414 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
415 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
416 | } | |
417 | ||
c131fcee L |
418 | /* Return the name of register REGNUM, or the empty string if it is |
419 | an anonymous register. */ | |
420 | ||
421 | static const char * | |
422 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
423 | { | |
424 | /* Hide the upper YMM registers. */ | |
425 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
426 | return ""; | |
427 | ||
01f9f808 MS |
428 | /* Hide the upper YMM16-31 registers. */ |
429 | if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) | |
430 | return ""; | |
431 | ||
432 | /* Hide the upper ZMM registers. */ | |
433 | if (i386_zmmh_regnum_p (gdbarch, regnum)) | |
434 | return ""; | |
435 | ||
c131fcee L |
436 | return tdesc_register_name (gdbarch, regnum); |
437 | } | |
438 | ||
30b0e2d8 | 439 | /* Return the name of register REGNUM. */ |
fc633446 | 440 | |
1ba53b71 | 441 | const char * |
90884b2b | 442 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 443 | { |
1ba53b71 | 444 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dbcd68c WT |
445 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
446 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
447 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
448 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
449 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
450 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
451 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
452 | return i386_zmm_names[regnum - tdep->zmm0_regnum]; | |
1ba53b71 L |
453 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
454 | return i386_byte_names[regnum - tdep->al_regnum]; | |
455 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
456 | return i386_word_names[regnum - tdep->ax_regnum]; | |
457 | ||
458 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
459 | } |
460 | ||
c4fc7f1b | 461 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
462 | number used by GDB. */ |
463 | ||
8201327c | 464 | static int |
d3f73121 | 465 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 466 | { |
20a6ec49 MD |
467 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
468 | ||
c4fc7f1b MK |
469 | /* This implements what GCC calls the "default" register map |
470 | (dbx_register_map[]). */ | |
471 | ||
85540d8c MK |
472 | if (reg >= 0 && reg <= 7) |
473 | { | |
9872ad24 JB |
474 | /* General-purpose registers. The debug info calls %ebp |
475 | register 4, and %esp register 5. */ | |
476 | if (reg == 4) | |
477 | return 5; | |
478 | else if (reg == 5) | |
479 | return 4; | |
480 | else return reg; | |
85540d8c MK |
481 | } |
482 | else if (reg >= 12 && reg <= 19) | |
483 | { | |
484 | /* Floating-point registers. */ | |
20a6ec49 | 485 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
486 | } |
487 | else if (reg >= 21 && reg <= 28) | |
488 | { | |
489 | /* SSE registers. */ | |
c131fcee L |
490 | int ymm0_regnum = tdep->ymm0_regnum; |
491 | ||
492 | if (ymm0_regnum >= 0 | |
493 | && i386_xmm_regnum_p (gdbarch, reg)) | |
494 | return reg - 21 + ymm0_regnum; | |
495 | else | |
496 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
497 | } |
498 | else if (reg >= 29 && reg <= 36) | |
499 | { | |
500 | /* MMX registers. */ | |
20a6ec49 | 501 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
502 | } |
503 | ||
504 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 505 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
506 | } |
507 | ||
c4fc7f1b MK |
508 | /* Convert SVR4 register number REG to the appropriate register number |
509 | used by GDB. */ | |
85540d8c | 510 | |
8201327c | 511 | static int |
d3f73121 | 512 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 513 | { |
20a6ec49 MD |
514 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
515 | ||
c4fc7f1b MK |
516 | /* This implements the GCC register map that tries to be compatible |
517 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
518 | ||
519 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
520 | numbers the floating point registers differently. */ |
521 | if (reg >= 0 && reg <= 9) | |
522 | { | |
acd5c798 | 523 | /* General-purpose registers. */ |
85540d8c MK |
524 | return reg; |
525 | } | |
526 | else if (reg >= 11 && reg <= 18) | |
527 | { | |
528 | /* Floating-point registers. */ | |
20a6ec49 | 529 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 530 | } |
c6f4c129 | 531 | else if (reg >= 21 && reg <= 36) |
85540d8c | 532 | { |
c4fc7f1b | 533 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 534 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
535 | } |
536 | ||
c6f4c129 JB |
537 | switch (reg) |
538 | { | |
20a6ec49 MD |
539 | case 37: return I387_FCTRL_REGNUM (tdep); |
540 | case 38: return I387_FSTAT_REGNUM (tdep); | |
541 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
542 | case 40: return I386_ES_REGNUM; |
543 | case 41: return I386_CS_REGNUM; | |
544 | case 42: return I386_SS_REGNUM; | |
545 | case 43: return I386_DS_REGNUM; | |
546 | case 44: return I386_FS_REGNUM; | |
547 | case 45: return I386_GS_REGNUM; | |
548 | } | |
549 | ||
85540d8c | 550 | /* This will hopefully provoke a warning. */ |
d3f73121 | 551 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 552 | } |
5716833c | 553 | |
fc338970 | 554 | \f |
917317f4 | 555 | |
fc338970 MK |
556 | /* This is the variable that is set with "set disassembly-flavor", and |
557 | its legitimate values. */ | |
53904c9e AC |
558 | static const char att_flavor[] = "att"; |
559 | static const char intel_flavor[] = "intel"; | |
40478521 | 560 | static const char *const valid_flavors[] = |
c5aa993b | 561 | { |
c906108c SS |
562 | att_flavor, |
563 | intel_flavor, | |
564 | NULL | |
565 | }; | |
53904c9e | 566 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 567 | \f |
c906108c | 568 | |
acd5c798 MK |
569 | /* Use the program counter to determine the contents and size of a |
570 | breakpoint instruction. Return a pointer to a string of bytes that | |
571 | encode a breakpoint instruction, store the length of the string in | |
572 | *LEN and optionally adjust *PC to point to the correct memory | |
573 | location for inserting the breakpoint. | |
c906108c | 574 | |
acd5c798 MK |
575 | On the i386 we have a single breakpoint that fits in a single byte |
576 | and can be inserted anywhere. | |
c906108c | 577 | |
acd5c798 | 578 | This function is 64-bit safe. */ |
63c0089f MK |
579 | |
580 | static const gdb_byte * | |
67d57894 | 581 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 582 | { |
63c0089f MK |
583 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
584 | ||
acd5c798 MK |
585 | *len = sizeof (break_insn); |
586 | return break_insn; | |
c906108c | 587 | } |
237fc4c9 PA |
588 | \f |
589 | /* Displaced instruction handling. */ | |
590 | ||
1903f0e6 DE |
591 | /* Skip the legacy instruction prefixes in INSN. |
592 | Not all prefixes are valid for any particular insn | |
593 | but we needn't care, the insn will fault if it's invalid. | |
594 | The result is a pointer to the first opcode byte, | |
595 | or NULL if we run off the end of the buffer. */ | |
596 | ||
597 | static gdb_byte * | |
598 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
599 | { | |
600 | gdb_byte *end = insn + max_len; | |
601 | ||
602 | while (insn < end) | |
603 | { | |
604 | switch (*insn) | |
605 | { | |
606 | case DATA_PREFIX_OPCODE: | |
607 | case ADDR_PREFIX_OPCODE: | |
608 | case CS_PREFIX_OPCODE: | |
609 | case DS_PREFIX_OPCODE: | |
610 | case ES_PREFIX_OPCODE: | |
611 | case FS_PREFIX_OPCODE: | |
612 | case GS_PREFIX_OPCODE: | |
613 | case SS_PREFIX_OPCODE: | |
614 | case LOCK_PREFIX_OPCODE: | |
615 | case REPE_PREFIX_OPCODE: | |
616 | case REPNE_PREFIX_OPCODE: | |
617 | ++insn; | |
618 | continue; | |
619 | default: | |
620 | return insn; | |
621 | } | |
622 | } | |
623 | ||
624 | return NULL; | |
625 | } | |
237fc4c9 PA |
626 | |
627 | static int | |
1903f0e6 | 628 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 629 | { |
1777feb0 | 630 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
631 | if (insn[0] == 0xea) |
632 | return 1; | |
633 | ||
634 | if (insn[0] == 0xff) | |
635 | { | |
1777feb0 | 636 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
637 | if ((insn[1] & 0x38) == 0x20) |
638 | return 1; | |
639 | ||
1777feb0 | 640 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
641 | if ((insn[1] & 0x38) == 0x28) |
642 | return 1; | |
643 | } | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
c2170eef MM |
648 | /* Return non-zero if INSN is a jump, zero otherwise. */ |
649 | ||
650 | static int | |
651 | i386_jmp_p (const gdb_byte *insn) | |
652 | { | |
653 | /* jump short, relative. */ | |
654 | if (insn[0] == 0xeb) | |
655 | return 1; | |
656 | ||
657 | /* jump near, relative. */ | |
658 | if (insn[0] == 0xe9) | |
659 | return 1; | |
660 | ||
661 | return i386_absolute_jmp_p (insn); | |
662 | } | |
663 | ||
237fc4c9 | 664 | static int |
1903f0e6 | 665 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 666 | { |
1777feb0 | 667 | /* call far, absolute. */ |
237fc4c9 PA |
668 | if (insn[0] == 0x9a) |
669 | return 1; | |
670 | ||
671 | if (insn[0] == 0xff) | |
672 | { | |
1777feb0 | 673 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
674 | if ((insn[1] & 0x38) == 0x10) |
675 | return 1; | |
676 | ||
1777feb0 | 677 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
678 | if ((insn[1] & 0x38) == 0x18) |
679 | return 1; | |
680 | } | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
685 | static int | |
1903f0e6 | 686 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
687 | { |
688 | switch (insn[0]) | |
689 | { | |
1777feb0 | 690 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 691 | case 0xc3: /* ret near */ |
1777feb0 | 692 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
693 | case 0xcb: /* ret far */ |
694 | case 0xcf: /* iret */ | |
695 | return 1; | |
696 | ||
697 | default: | |
698 | return 0; | |
699 | } | |
700 | } | |
701 | ||
702 | static int | |
1903f0e6 | 703 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
704 | { |
705 | if (i386_absolute_call_p (insn)) | |
706 | return 1; | |
707 | ||
1777feb0 | 708 | /* call near, relative. */ |
237fc4c9 PA |
709 | if (insn[0] == 0xe8) |
710 | return 1; | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
237fc4c9 PA |
715 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
716 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 717 | |
237fc4c9 | 718 | static int |
b55078be | 719 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 720 | { |
9a7f938f JK |
721 | /* Is it 'int $0x80'? */ |
722 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
723 | /* Or is it 'sysenter'? */ | |
724 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
725 | /* Or is it 'syscall'? */ | |
726 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
727 | { |
728 | *lengthp = 2; | |
729 | return 1; | |
730 | } | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
c2170eef MM |
735 | /* The gdbarch insn_is_call method. */ |
736 | ||
737 | static int | |
738 | i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
739 | { | |
740 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
741 | ||
742 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
743 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
744 | ||
745 | return i386_call_p (insn); | |
746 | } | |
747 | ||
748 | /* The gdbarch insn_is_ret method. */ | |
749 | ||
750 | static int | |
751 | i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
752 | { | |
753 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
754 | ||
755 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
756 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
757 | ||
758 | return i386_ret_p (insn); | |
759 | } | |
760 | ||
761 | /* The gdbarch insn_is_jump method. */ | |
762 | ||
763 | static int | |
764 | i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
765 | { | |
766 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
767 | ||
768 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
769 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
770 | ||
771 | return i386_jmp_p (insn); | |
772 | } | |
773 | ||
b55078be DE |
774 | /* Some kernels may run one past a syscall insn, so we have to cope. |
775 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
776 | ||
777 | struct displaced_step_closure * | |
778 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
779 | CORE_ADDR from, CORE_ADDR to, | |
780 | struct regcache *regs) | |
781 | { | |
782 | size_t len = gdbarch_max_insn_length (gdbarch); | |
783 | gdb_byte *buf = xmalloc (len); | |
784 | ||
785 | read_memory (from, buf, len); | |
786 | ||
787 | /* GDB may get control back after the insn after the syscall. | |
788 | Presumably this is a kernel bug. | |
789 | If this is a syscall, make sure there's a nop afterwards. */ | |
790 | { | |
791 | int syscall_length; | |
792 | gdb_byte *insn; | |
793 | ||
794 | insn = i386_skip_prefixes (buf, len); | |
795 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
796 | insn[syscall_length] = NOP_OPCODE; | |
797 | } | |
798 | ||
799 | write_memory (to, buf, len); | |
800 | ||
801 | if (debug_displaced) | |
802 | { | |
803 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
804 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
805 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
806 | } | |
807 | ||
808 | return (struct displaced_step_closure *) buf; | |
809 | } | |
810 | ||
237fc4c9 PA |
811 | /* Fix up the state of registers and memory after having single-stepped |
812 | a displaced instruction. */ | |
1903f0e6 | 813 | |
237fc4c9 PA |
814 | void |
815 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
816 | struct displaced_step_closure *closure, | |
817 | CORE_ADDR from, CORE_ADDR to, | |
818 | struct regcache *regs) | |
819 | { | |
e17a4113 UW |
820 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
821 | ||
237fc4c9 PA |
822 | /* The offset we applied to the instruction's address. |
823 | This could well be negative (when viewed as a signed 32-bit | |
824 | value), but ULONGEST won't reflect that, so take care when | |
825 | applying it. */ | |
826 | ULONGEST insn_offset = to - from; | |
827 | ||
828 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
829 | copy of the instruction. */ | |
830 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
831 | /* The start of the insn, needed in case we see some prefixes. */ |
832 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
833 | |
834 | if (debug_displaced) | |
835 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 836 | "displaced: fixup (%s, %s), " |
237fc4c9 | 837 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
838 | paddress (gdbarch, from), paddress (gdbarch, to), |
839 | insn[0], insn[1]); | |
237fc4c9 PA |
840 | |
841 | /* The list of issues to contend with here is taken from | |
842 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
843 | Yay for Free Software! */ | |
844 | ||
845 | /* Relocate the %eip, if necessary. */ | |
846 | ||
1903f0e6 DE |
847 | /* The instruction recognizers we use assume any leading prefixes |
848 | have been skipped. */ | |
849 | { | |
850 | /* This is the size of the buffer in closure. */ | |
851 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
852 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
853 | /* If there are too many prefixes, just ignore the insn. | |
854 | It will fault when run. */ | |
855 | if (opcode != NULL) | |
856 | insn = opcode; | |
857 | } | |
858 | ||
237fc4c9 PA |
859 | /* Except in the case of absolute or indirect jump or call |
860 | instructions, or a return instruction, the new eip is relative to | |
861 | the displaced instruction; make it relative. Well, signal | |
862 | handler returns don't need relocation either, but we use the | |
863 | value of %eip to recognize those; see below. */ | |
864 | if (! i386_absolute_jmp_p (insn) | |
865 | && ! i386_absolute_call_p (insn) | |
866 | && ! i386_ret_p (insn)) | |
867 | { | |
868 | ULONGEST orig_eip; | |
b55078be | 869 | int insn_len; |
237fc4c9 PA |
870 | |
871 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
872 | ||
873 | /* A signal trampoline system call changes the %eip, resuming | |
874 | execution of the main program after the signal handler has | |
875 | returned. That makes them like 'return' instructions; we | |
876 | shouldn't relocate %eip. | |
877 | ||
878 | But most system calls don't, and we do need to relocate %eip. | |
879 | ||
880 | Our heuristic for distinguishing these cases: if stepping | |
881 | over the system call instruction left control directly after | |
882 | the instruction, the we relocate --- control almost certainly | |
883 | doesn't belong in the displaced copy. Otherwise, we assume | |
884 | the instruction has put control where it belongs, and leave | |
885 | it unrelocated. Goodness help us if there are PC-relative | |
886 | system calls. */ | |
887 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
888 | && orig_eip != to + (insn - insn_start) + insn_len |
889 | /* GDB can get control back after the insn after the syscall. | |
890 | Presumably this is a kernel bug. | |
891 | i386_displaced_step_copy_insn ensures its a nop, | |
892 | we add one to the length for it. */ | |
893 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
894 | { |
895 | if (debug_displaced) | |
896 | fprintf_unfiltered (gdb_stdlog, | |
897 | "displaced: syscall changed %%eip; " | |
898 | "not relocating\n"); | |
899 | } | |
900 | else | |
901 | { | |
902 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
903 | ||
1903f0e6 DE |
904 | /* If we just stepped over a breakpoint insn, we don't backup |
905 | the pc on purpose; this is to match behaviour without | |
906 | stepping. */ | |
237fc4c9 PA |
907 | |
908 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
909 | ||
910 | if (debug_displaced) | |
911 | fprintf_unfiltered (gdb_stdlog, | |
912 | "displaced: " | |
5af949e3 UW |
913 | "relocated %%eip from %s to %s\n", |
914 | paddress (gdbarch, orig_eip), | |
915 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
916 | } |
917 | } | |
918 | ||
919 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
920 | pushed value, and should be cleared. We'll leave this for later, | |
921 | since GDB already messes up the TF flag when stepping over a | |
922 | pushfl. */ | |
923 | ||
924 | /* If the instruction was a call, the return address now atop the | |
925 | stack is the address following the copied instruction. We need | |
926 | to make it the address following the original instruction. */ | |
927 | if (i386_call_p (insn)) | |
928 | { | |
929 | ULONGEST esp; | |
930 | ULONGEST retaddr; | |
931 | const ULONGEST retaddr_len = 4; | |
932 | ||
933 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 934 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 935 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 936 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
937 | |
938 | if (debug_displaced) | |
939 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
940 | "displaced: relocated return addr at %s to %s\n", |
941 | paddress (gdbarch, esp), | |
942 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
943 | } |
944 | } | |
dde08ee1 PA |
945 | |
946 | static void | |
947 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
948 | { | |
949 | target_write_memory (*to, buf, len); | |
950 | *to += len; | |
951 | } | |
952 | ||
953 | static void | |
954 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
955 | CORE_ADDR *to, CORE_ADDR oldloc) | |
956 | { | |
957 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
958 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
959 | int offset = 0, rel32, newrel; | |
960 | int insn_length; | |
961 | gdb_byte *insn = buf; | |
962 | ||
963 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
964 | ||
965 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
966 | I386_MAX_INSN_LEN, oldloc); | |
967 | ||
968 | /* Get past the prefixes. */ | |
969 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
970 | ||
971 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
972 | the address pushed being the location where the original call in | |
973 | the user program would return to. */ | |
974 | if (insn[0] == 0xe8) | |
975 | { | |
976 | gdb_byte push_buf[16]; | |
977 | unsigned int ret_addr; | |
978 | ||
979 | /* Where "ret" in the original code will return to. */ | |
980 | ret_addr = oldloc + insn_length; | |
1777feb0 | 981 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 982 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
983 | /* Push the push. */ |
984 | append_insns (to, 5, push_buf); | |
985 | ||
986 | /* Convert the relative call to a relative jump. */ | |
987 | insn[0] = 0xe9; | |
988 | ||
989 | /* Adjust the destination offset. */ | |
990 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
991 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
992 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
993 | ||
994 | if (debug_displaced) | |
995 | fprintf_unfiltered (gdb_stdlog, | |
996 | "Adjusted insn rel32=%s at %s to" | |
997 | " rel32=%s at %s\n", | |
998 | hex_string (rel32), paddress (gdbarch, oldloc), | |
999 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1000 | |
1001 | /* Write the adjusted jump into its displaced location. */ | |
1002 | append_insns (to, 5, insn); | |
1003 | return; | |
1004 | } | |
1005 | ||
1006 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
1007 | handled above. */ | |
1008 | if (insn[0] == 0xe9) | |
1009 | offset = 1; | |
1010 | /* Adjust conditional jumps. */ | |
1011 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1012 | offset = 2; | |
1013 | ||
1014 | if (offset) | |
1015 | { | |
1016 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1017 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1018 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
1019 | if (debug_displaced) |
1020 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
1021 | "Adjusted insn rel32=%s at %s to" |
1022 | " rel32=%s at %s\n", | |
dde08ee1 PA |
1023 | hex_string (rel32), paddress (gdbarch, oldloc), |
1024 | hex_string (newrel), paddress (gdbarch, *to)); | |
1025 | } | |
1026 | ||
1027 | /* Write the adjusted instructions into their displaced | |
1028 | location. */ | |
1029 | append_insns (to, insn_length, buf); | |
1030 | } | |
1031 | ||
fc338970 | 1032 | \f |
acd5c798 MK |
1033 | #ifdef I386_REGNO_TO_SYMMETRY |
1034 | #error "The Sequent Symmetry is no longer supported." | |
1035 | #endif | |
c906108c | 1036 | |
acd5c798 MK |
1037 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
1038 | and %esp "belong" to the calling function. Therefore these | |
1039 | registers should be saved if they're going to be modified. */ | |
c906108c | 1040 | |
acd5c798 MK |
1041 | /* The maximum number of saved registers. This should include all |
1042 | registers mentioned above, and %eip. */ | |
a3386186 | 1043 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
1044 | |
1045 | struct i386_frame_cache | |
c906108c | 1046 | { |
acd5c798 MK |
1047 | /* Base address. */ |
1048 | CORE_ADDR base; | |
8fbca658 | 1049 | int base_p; |
772562f8 | 1050 | LONGEST sp_offset; |
acd5c798 MK |
1051 | CORE_ADDR pc; |
1052 | ||
fd13a04a AC |
1053 | /* Saved registers. */ |
1054 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 1055 | CORE_ADDR saved_sp; |
e0c62198 | 1056 | int saved_sp_reg; |
acd5c798 MK |
1057 | int pc_in_eax; |
1058 | ||
1059 | /* Stack space reserved for local variables. */ | |
1060 | long locals; | |
1061 | }; | |
1062 | ||
1063 | /* Allocate and initialize a frame cache. */ | |
1064 | ||
1065 | static struct i386_frame_cache * | |
fd13a04a | 1066 | i386_alloc_frame_cache (void) |
acd5c798 MK |
1067 | { |
1068 | struct i386_frame_cache *cache; | |
1069 | int i; | |
1070 | ||
1071 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
1072 | ||
1073 | /* Base address. */ | |
8fbca658 | 1074 | cache->base_p = 0; |
acd5c798 MK |
1075 | cache->base = 0; |
1076 | cache->sp_offset = -4; | |
1077 | cache->pc = 0; | |
1078 | ||
fd13a04a AC |
1079 | /* Saved registers. We initialize these to -1 since zero is a valid |
1080 | offset (that's where %ebp is supposed to be stored). */ | |
1081 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
1082 | cache->saved_regs[i] = -1; | |
acd5c798 | 1083 | cache->saved_sp = 0; |
e0c62198 | 1084 | cache->saved_sp_reg = -1; |
acd5c798 MK |
1085 | cache->pc_in_eax = 0; |
1086 | ||
1087 | /* Frameless until proven otherwise. */ | |
1088 | cache->locals = -1; | |
1089 | ||
1090 | return cache; | |
1091 | } | |
c906108c | 1092 | |
acd5c798 MK |
1093 | /* If the instruction at PC is a jump, return the address of its |
1094 | target. Otherwise, return PC. */ | |
c906108c | 1095 | |
acd5c798 | 1096 | static CORE_ADDR |
e17a4113 | 1097 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 1098 | { |
e17a4113 | 1099 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1100 | gdb_byte op; |
acd5c798 MK |
1101 | long delta = 0; |
1102 | int data16 = 0; | |
c906108c | 1103 | |
0865b04a | 1104 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1105 | return pc; |
1106 | ||
acd5c798 | 1107 | if (op == 0x66) |
c906108c | 1108 | { |
c906108c | 1109 | data16 = 1; |
0865b04a YQ |
1110 | |
1111 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
1112 | } |
1113 | ||
acd5c798 | 1114 | switch (op) |
c906108c SS |
1115 | { |
1116 | case 0xe9: | |
fc338970 | 1117 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
1118 | if (data16) |
1119 | { | |
e17a4113 | 1120 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 1121 | |
fc338970 MK |
1122 | /* Include the size of the jmp instruction (including the |
1123 | 0x66 prefix). */ | |
acd5c798 | 1124 | delta += 4; |
c906108c SS |
1125 | } |
1126 | else | |
1127 | { | |
e17a4113 | 1128 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 1129 | |
acd5c798 MK |
1130 | /* Include the size of the jmp instruction. */ |
1131 | delta += 5; | |
c906108c SS |
1132 | } |
1133 | break; | |
1134 | case 0xeb: | |
fc338970 | 1135 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 1136 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 1137 | |
acd5c798 | 1138 | delta += data16 + 2; |
c906108c SS |
1139 | break; |
1140 | } | |
c906108c | 1141 | |
acd5c798 MK |
1142 | return pc + delta; |
1143 | } | |
fc338970 | 1144 | |
acd5c798 MK |
1145 | /* Check whether PC points at a prologue for a function returning a |
1146 | structure or union. If so, it updates CACHE and returns the | |
1147 | address of the first instruction after the code sequence that | |
1148 | removes the "hidden" argument from the stack or CURRENT_PC, | |
1149 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 1150 | |
acd5c798 MK |
1151 | static CORE_ADDR |
1152 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
1153 | struct i386_frame_cache *cache) | |
c906108c | 1154 | { |
acd5c798 MK |
1155 | /* Functions that return a structure or union start with: |
1156 | ||
1157 | popl %eax 0x58 | |
1158 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
1159 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
1160 | ||
1161 | (the System V compiler puts out the second `xchg' instruction, | |
1162 | and the assembler doesn't try to optimize it, so the 'sib' form | |
1163 | gets generated). This sequence is used to get the address of the | |
1164 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
1165 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
1166 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
1167 | gdb_byte buf[4]; | |
1168 | gdb_byte op; | |
c906108c | 1169 | |
acd5c798 MK |
1170 | if (current_pc <= pc) |
1171 | return pc; | |
1172 | ||
0865b04a | 1173 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1174 | return pc; |
c906108c | 1175 | |
acd5c798 MK |
1176 | if (op != 0x58) /* popl %eax */ |
1177 | return pc; | |
c906108c | 1178 | |
0865b04a | 1179 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1180 | return pc; |
1181 | ||
acd5c798 MK |
1182 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1183 | return pc; | |
c906108c | 1184 | |
acd5c798 | 1185 | if (current_pc == pc) |
c906108c | 1186 | { |
acd5c798 MK |
1187 | cache->sp_offset += 4; |
1188 | return current_pc; | |
c906108c SS |
1189 | } |
1190 | ||
acd5c798 | 1191 | if (current_pc == pc + 1) |
c906108c | 1192 | { |
acd5c798 MK |
1193 | cache->pc_in_eax = 1; |
1194 | return current_pc; | |
1195 | } | |
1196 | ||
1197 | if (buf[1] == proto1[1]) | |
1198 | return pc + 4; | |
1199 | else | |
1200 | return pc + 5; | |
1201 | } | |
1202 | ||
1203 | static CORE_ADDR | |
1204 | i386_skip_probe (CORE_ADDR pc) | |
1205 | { | |
1206 | /* A function may start with | |
fc338970 | 1207 | |
acd5c798 MK |
1208 | pushl constant |
1209 | call _probe | |
1210 | addl $4, %esp | |
fc338970 | 1211 | |
acd5c798 MK |
1212 | followed by |
1213 | ||
1214 | pushl %ebp | |
fc338970 | 1215 | |
acd5c798 | 1216 | etc. */ |
63c0089f MK |
1217 | gdb_byte buf[8]; |
1218 | gdb_byte op; | |
fc338970 | 1219 | |
0865b04a | 1220 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1221 | return pc; |
acd5c798 MK |
1222 | |
1223 | if (op == 0x68 || op == 0x6a) | |
1224 | { | |
1225 | int delta; | |
c906108c | 1226 | |
acd5c798 MK |
1227 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1228 | four-byte operand, depending on the opcode. */ | |
c906108c | 1229 | if (op == 0x68) |
acd5c798 | 1230 | delta = 5; |
c906108c | 1231 | else |
acd5c798 | 1232 | delta = 2; |
c906108c | 1233 | |
acd5c798 MK |
1234 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1235 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1236 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1237 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1238 | pc += delta + sizeof (buf); |
c906108c SS |
1239 | } |
1240 | ||
acd5c798 MK |
1241 | return pc; |
1242 | } | |
1243 | ||
92dd43fa MK |
1244 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1245 | stack pointer. Check whether PC points to such code, and update | |
1246 | CACHE accordingly. Return the first instruction after the code | |
1247 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1248 | recognize the code, return PC. */ | |
1249 | ||
1250 | static CORE_ADDR | |
1251 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1252 | struct i386_frame_cache *cache) | |
1253 | { | |
e0c62198 L |
1254 | /* There are 2 code sequences to re-align stack before the frame |
1255 | gets set up: | |
1256 | ||
1257 | 1. Use a caller-saved saved register: | |
1258 | ||
1259 | leal 4(%esp), %reg | |
1260 | andl $-XXX, %esp | |
1261 | pushl -4(%reg) | |
1262 | ||
1263 | 2. Use a callee-saved saved register: | |
1264 | ||
1265 | pushl %reg | |
1266 | leal 8(%esp), %reg | |
1267 | andl $-XXX, %esp | |
1268 | pushl -4(%reg) | |
1269 | ||
1270 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1271 | ||
1272 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1273 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1274 | */ | |
1275 | ||
1276 | gdb_byte buf[14]; | |
1277 | int reg; | |
1278 | int offset, offset_and; | |
1279 | static int regnums[8] = { | |
1280 | I386_EAX_REGNUM, /* %eax */ | |
1281 | I386_ECX_REGNUM, /* %ecx */ | |
1282 | I386_EDX_REGNUM, /* %edx */ | |
1283 | I386_EBX_REGNUM, /* %ebx */ | |
1284 | I386_ESP_REGNUM, /* %esp */ | |
1285 | I386_EBP_REGNUM, /* %ebp */ | |
1286 | I386_ESI_REGNUM, /* %esi */ | |
1287 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1288 | }; |
92dd43fa | 1289 | |
0865b04a | 1290 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1291 | return pc; |
1292 | ||
1293 | /* Check caller-saved saved register. The first instruction has | |
1294 | to be "leal 4(%esp), %reg". */ | |
1295 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1296 | { | |
1297 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1298 | if ((buf[1] & 0xc7) != 0x44) | |
1299 | return pc; | |
1300 | ||
1301 | /* REG has register number. */ | |
1302 | reg = (buf[1] >> 3) & 7; | |
1303 | offset = 4; | |
1304 | } | |
1305 | else | |
1306 | { | |
1307 | /* Check callee-saved saved register. The first instruction | |
1308 | has to be "pushl %reg". */ | |
1309 | if ((buf[0] & 0xf8) != 0x50) | |
1310 | return pc; | |
1311 | ||
1312 | /* Get register. */ | |
1313 | reg = buf[0] & 0x7; | |
1314 | ||
1315 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1316 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1317 | return pc; | |
1318 | ||
1319 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1320 | if ((buf[2] & 0xc7) != 0x44) | |
1321 | return pc; | |
1322 | ||
1323 | /* REG has register number. Registers in pushl and leal have to | |
1324 | be the same. */ | |
1325 | if (reg != ((buf[2] >> 3) & 7)) | |
1326 | return pc; | |
1327 | ||
1328 | offset = 5; | |
1329 | } | |
1330 | ||
1331 | /* Rigister can't be %esp nor %ebp. */ | |
1332 | if (reg == 4 || reg == 5) | |
1333 | return pc; | |
1334 | ||
1335 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1336 | if (buf[offset + 1] != 0xe4 | |
1337 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1338 | return pc; | |
1339 | ||
1340 | offset_and = offset; | |
1341 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1342 | ||
1343 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1344 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1345 | if (buf[offset] != 0xff | |
1346 | || buf[offset + 2] != 0xfc | |
1347 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1348 | return pc; | |
1349 | ||
1350 | /* R/M has register. Registers in leal and pushl have to be the | |
1351 | same. */ | |
1352 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1353 | return pc; |
1354 | ||
e0c62198 L |
1355 | if (current_pc > pc + offset_and) |
1356 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1357 | |
e0c62198 | 1358 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1359 | } |
1360 | ||
37bdc87e | 1361 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1362 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1363 | |
1364 | /* Instruction description. */ | |
1365 | struct i386_insn | |
1366 | { | |
1367 | size_t len; | |
237fc4c9 PA |
1368 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1369 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1370 | }; |
1371 | ||
a3fcb948 | 1372 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1373 | |
a3fcb948 JG |
1374 | static int |
1375 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1376 | { |
63c0089f | 1377 | gdb_byte op; |
37bdc87e | 1378 | |
0865b04a | 1379 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1380 | return 0; |
37bdc87e | 1381 | |
a3fcb948 | 1382 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1383 | { |
a3fcb948 JG |
1384 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1385 | int insn_matched = 1; | |
1386 | size_t i; | |
37bdc87e | 1387 | |
a3fcb948 JG |
1388 | gdb_assert (pattern.len > 1); |
1389 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1390 | |
0865b04a | 1391 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1392 | return 0; |
613e8135 | 1393 | |
a3fcb948 JG |
1394 | for (i = 1; i < pattern.len; i++) |
1395 | { | |
1396 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1397 | insn_matched = 0; | |
37bdc87e | 1398 | } |
a3fcb948 JG |
1399 | return insn_matched; |
1400 | } | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1405 | the first instruction description that matches. Otherwise, return | |
1406 | NULL. */ | |
1407 | ||
1408 | static struct i386_insn * | |
1409 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1410 | { | |
1411 | struct i386_insn *pattern; | |
1412 | ||
1413 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1414 | { | |
1415 | if (i386_match_pattern (pc, *pattern)) | |
1416 | return pattern; | |
37bdc87e MK |
1417 | } |
1418 | ||
1419 | return NULL; | |
1420 | } | |
1421 | ||
a3fcb948 JG |
1422 | /* Return whether PC points inside a sequence of instructions that |
1423 | matches INSN_PATTERNS. */ | |
1424 | ||
1425 | static int | |
1426 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1427 | { | |
1428 | CORE_ADDR current_pc; | |
1429 | int ix, i; | |
a3fcb948 JG |
1430 | struct i386_insn *insn; |
1431 | ||
1432 | insn = i386_match_insn (pc, insn_patterns); | |
1433 | if (insn == NULL) | |
1434 | return 0; | |
1435 | ||
8bbdd3f4 | 1436 | current_pc = pc; |
a3fcb948 JG |
1437 | ix = insn - insn_patterns; |
1438 | for (i = ix - 1; i >= 0; i--) | |
1439 | { | |
8bbdd3f4 MK |
1440 | current_pc -= insn_patterns[i].len; |
1441 | ||
a3fcb948 JG |
1442 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1443 | return 0; | |
a3fcb948 JG |
1444 | } |
1445 | ||
1446 | current_pc = pc + insn->len; | |
1447 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1448 | { | |
1449 | if (!i386_match_pattern (current_pc, *insn)) | |
1450 | return 0; | |
1451 | ||
1452 | current_pc += insn->len; | |
1453 | } | |
1454 | ||
1455 | return 1; | |
1456 | } | |
1457 | ||
37bdc87e MK |
1458 | /* Some special instructions that might be migrated by GCC into the |
1459 | part of the prologue that sets up the new stack frame. Because the | |
1460 | stack frame hasn't been setup yet, no registers have been saved | |
1461 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1462 | touched. */ | |
1463 | ||
1464 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1465 | { | |
1777feb0 | 1466 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1467 | |
1468 | ??? Should we handle 16-bit operand-sizes here? */ | |
1469 | ||
1470 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1471 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1472 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1473 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1474 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1475 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1476 | { 5, { 0xb8 }, { 0xfe } }, | |
1477 | /* `movl imm32, %edx' */ | |
1478 | { 5, { 0xba }, { 0xff } }, | |
1479 | ||
1480 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1481 | encoding for `mov m32, %eax'. | |
1482 | ||
1483 | ??? Should we handle SIB adressing here? | |
1484 | ??? Should we handle 16-bit operand-sizes here? */ | |
1485 | ||
1486 | /* `movl m32, %eax' */ | |
1487 | { 5, { 0xa1 }, { 0xff } }, | |
1488 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1489 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1490 | /* `movl m32, %edx' */ | |
1491 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1492 | ||
1493 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1494 | Because of the symmetry, there are actually two ways to encode | |
1495 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1496 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1497 | ||
1498 | /* `subl %eax, %eax' */ | |
1499 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1500 | /* `subl %ecx, %ecx' */ | |
1501 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1502 | /* `subl %edx, %edx' */ | |
1503 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1504 | /* `xorl %eax, %eax' */ | |
1505 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1506 | /* `xorl %ecx, %ecx' */ | |
1507 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1508 | /* `xorl %edx, %edx' */ | |
1509 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1510 | { 0 } | |
1511 | }; | |
1512 | ||
e11481da PM |
1513 | |
1514 | /* Check whether PC points to a no-op instruction. */ | |
1515 | static CORE_ADDR | |
1516 | i386_skip_noop (CORE_ADDR pc) | |
1517 | { | |
1518 | gdb_byte op; | |
1519 | int check = 1; | |
1520 | ||
0865b04a | 1521 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1522 | return pc; |
e11481da PM |
1523 | |
1524 | while (check) | |
1525 | { | |
1526 | check = 0; | |
1527 | /* Ignore `nop' instruction. */ | |
1528 | if (op == 0x90) | |
1529 | { | |
1530 | pc += 1; | |
0865b04a | 1531 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1532 | return pc; |
e11481da PM |
1533 | check = 1; |
1534 | } | |
1535 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1536 | Microsoft system dlls often start with | |
1537 | a `mov %edi,%edi' instruction. | |
1538 | The 5 bytes before the function start are | |
1539 | filled with `nop' instructions. | |
1540 | This pattern can be used for hot-patching: | |
1541 | The `mov %edi, %edi' instruction can be replaced by a | |
1542 | near jump to the location of the 5 `nop' instructions | |
1543 | which can be replaced by a 32-bit jump to anywhere | |
1544 | in the 32-bit address space. */ | |
1545 | ||
1546 | else if (op == 0x8b) | |
1547 | { | |
0865b04a | 1548 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1549 | return pc; |
1550 | ||
e11481da PM |
1551 | if (op == 0xff) |
1552 | { | |
1553 | pc += 2; | |
0865b04a | 1554 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1555 | return pc; |
1556 | ||
e11481da PM |
1557 | check = 1; |
1558 | } | |
1559 | } | |
1560 | } | |
1561 | return pc; | |
1562 | } | |
1563 | ||
acd5c798 MK |
1564 | /* Check whether PC points at a code that sets up a new stack frame. |
1565 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1566 | instruction after the sequence that sets up the frame or LIMIT, |
1567 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1568 | |
1569 | static CORE_ADDR | |
e17a4113 UW |
1570 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1571 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1572 | struct i386_frame_cache *cache) |
1573 | { | |
e17a4113 | 1574 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1575 | struct i386_insn *insn; |
63c0089f | 1576 | gdb_byte op; |
26604a34 | 1577 | int skip = 0; |
acd5c798 | 1578 | |
37bdc87e MK |
1579 | if (limit <= pc) |
1580 | return limit; | |
acd5c798 | 1581 | |
0865b04a | 1582 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1583 | return pc; |
acd5c798 | 1584 | |
c906108c | 1585 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1586 | { |
acd5c798 MK |
1587 | /* Take into account that we've executed the `pushl %ebp' that |
1588 | starts this instruction sequence. */ | |
fd13a04a | 1589 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1590 | cache->sp_offset += 4; |
37bdc87e | 1591 | pc++; |
acd5c798 MK |
1592 | |
1593 | /* If that's all, return now. */ | |
37bdc87e MK |
1594 | if (limit <= pc) |
1595 | return limit; | |
26604a34 | 1596 | |
b4632131 | 1597 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1598 | GCC into the prologue and skip them. At this point in the |
1599 | prologue, code should only touch the scratch registers %eax, | |
1600 | %ecx and %edx, so while the number of posibilities is sheer, | |
1601 | it is limited. | |
5daa5b4e | 1602 | |
26604a34 MK |
1603 | Make sure we only skip these instructions if we later see the |
1604 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1605 | while (pc + skip < limit) |
26604a34 | 1606 | { |
37bdc87e MK |
1607 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1608 | if (insn == NULL) | |
1609 | break; | |
b4632131 | 1610 | |
37bdc87e | 1611 | skip += insn->len; |
26604a34 MK |
1612 | } |
1613 | ||
37bdc87e MK |
1614 | /* If that's all, return now. */ |
1615 | if (limit <= pc + skip) | |
1616 | return limit; | |
1617 | ||
0865b04a | 1618 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1619 | return pc + skip; |
37bdc87e | 1620 | |
30f8135b YQ |
1621 | /* The i386 prologue looks like |
1622 | ||
1623 | push %ebp | |
1624 | mov %esp,%ebp | |
1625 | sub $0x10,%esp | |
1626 | ||
1627 | and a different prologue can be generated for atom. | |
1628 | ||
1629 | push %ebp | |
1630 | lea (%esp),%ebp | |
1631 | lea -0x10(%esp),%esp | |
1632 | ||
1633 | We handle both of them here. */ | |
1634 | ||
acd5c798 | 1635 | switch (op) |
c906108c | 1636 | { |
30f8135b | 1637 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1638 | case 0x8b: |
0865b04a | 1639 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1640 | != 0xec) |
37bdc87e | 1641 | return pc; |
30f8135b | 1642 | pc += (skip + 2); |
c906108c SS |
1643 | break; |
1644 | case 0x89: | |
0865b04a | 1645 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1646 | != 0xe5) |
37bdc87e | 1647 | return pc; |
30f8135b YQ |
1648 | pc += (skip + 2); |
1649 | break; | |
1650 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1651 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1652 | != 0x242c) |
1653 | return pc; | |
1654 | pc += (skip + 3); | |
c906108c SS |
1655 | break; |
1656 | default: | |
37bdc87e | 1657 | return pc; |
c906108c | 1658 | } |
acd5c798 | 1659 | |
26604a34 MK |
1660 | /* OK, we actually have a frame. We just don't know how large |
1661 | it is yet. Set its size to zero. We'll adjust it if | |
1662 | necessary. We also now commit to skipping the special | |
1663 | instructions mentioned before. */ | |
acd5c798 MK |
1664 | cache->locals = 0; |
1665 | ||
1666 | /* If that's all, return now. */ | |
37bdc87e MK |
1667 | if (limit <= pc) |
1668 | return limit; | |
acd5c798 | 1669 | |
fc338970 MK |
1670 | /* Check for stack adjustment |
1671 | ||
acd5c798 | 1672 | subl $XXX, %esp |
30f8135b YQ |
1673 | or |
1674 | lea -XXX(%esp),%esp | |
fc338970 | 1675 | |
fd35795f | 1676 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1677 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1678 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1679 | return pc; |
c906108c SS |
1680 | if (op == 0x83) |
1681 | { | |
fd35795f | 1682 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1683 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1684 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1685 | return pc; |
acd5c798 | 1686 | |
37bdc87e MK |
1687 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1688 | make sense to be negative). */ | |
0865b04a | 1689 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1690 | return pc + 3; |
c906108c SS |
1691 | } |
1692 | else if (op == 0x81) | |
1693 | { | |
fd35795f | 1694 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1695 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1696 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1697 | return pc; |
acd5c798 | 1698 | |
fd35795f | 1699 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1700 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1701 | return pc + 6; |
c906108c | 1702 | } |
30f8135b YQ |
1703 | else if (op == 0x8d) |
1704 | { | |
1705 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1706 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1707 | return pc; |
1708 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1709 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1710 | return pc + 4; |
1711 | } | |
c906108c SS |
1712 | else |
1713 | { | |
30f8135b | 1714 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1715 | return pc; |
c906108c SS |
1716 | } |
1717 | } | |
37bdc87e | 1718 | else if (op == 0xc8) /* enter */ |
c906108c | 1719 | { |
0865b04a | 1720 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1721 | return pc + 4; |
c906108c | 1722 | } |
21d0e8a4 | 1723 | |
acd5c798 | 1724 | return pc; |
21d0e8a4 MK |
1725 | } |
1726 | ||
acd5c798 MK |
1727 | /* Check whether PC points at code that saves registers on the stack. |
1728 | If so, it updates CACHE and returns the address of the first | |
1729 | instruction after the register saves or CURRENT_PC, whichever is | |
1730 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1731 | |
1732 | static CORE_ADDR | |
acd5c798 MK |
1733 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1734 | struct i386_frame_cache *cache) | |
6bff26de | 1735 | { |
99ab4326 | 1736 | CORE_ADDR offset = 0; |
63c0089f | 1737 | gdb_byte op; |
99ab4326 | 1738 | int i; |
c0d1d883 | 1739 | |
99ab4326 MK |
1740 | if (cache->locals > 0) |
1741 | offset -= cache->locals; | |
1742 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1743 | { | |
0865b04a | 1744 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1745 | return pc; |
99ab4326 MK |
1746 | if (op < 0x50 || op > 0x57) |
1747 | break; | |
0d17c81d | 1748 | |
99ab4326 MK |
1749 | offset -= 4; |
1750 | cache->saved_regs[op - 0x50] = offset; | |
1751 | cache->sp_offset += 4; | |
1752 | pc++; | |
6bff26de MK |
1753 | } |
1754 | ||
acd5c798 | 1755 | return pc; |
22797942 AC |
1756 | } |
1757 | ||
acd5c798 MK |
1758 | /* Do a full analysis of the prologue at PC and update CACHE |
1759 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1760 | address where the analysis stopped. | |
ed84f6c1 | 1761 | |
fc338970 MK |
1762 | We handle these cases: |
1763 | ||
1764 | The startup sequence can be at the start of the function, or the | |
1765 | function can start with a branch to startup code at the end. | |
1766 | ||
1767 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1768 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1769 | once used in the System V compiler). | |
1770 | ||
1771 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1772 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1773 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1774 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1775 | |
1776 | Next, the registers used by this function are pushed. With the | |
1777 | System V compiler they will always be in the order: %edi, %esi, | |
1778 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1779 | restore %eax); however, the code below is willing to see the pushes | |
1780 | in any order, and will handle up to 8 of them. | |
1781 | ||
1782 | If the setup sequence is at the end of the function, then the next | |
1783 | instruction will be a branch back to the start. */ | |
c906108c | 1784 | |
acd5c798 | 1785 | static CORE_ADDR |
e17a4113 UW |
1786 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1787 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1788 | struct i386_frame_cache *cache) |
c906108c | 1789 | { |
e11481da | 1790 | pc = i386_skip_noop (pc); |
e17a4113 | 1791 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1792 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1793 | pc = i386_skip_probe (pc); | |
92dd43fa | 1794 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1795 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1796 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1797 | } |
1798 | ||
fc338970 | 1799 | /* Return PC of first real instruction. */ |
c906108c | 1800 | |
3a1e71e3 | 1801 | static CORE_ADDR |
6093d2eb | 1802 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1803 | { |
e17a4113 UW |
1804 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1805 | ||
63c0089f | 1806 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1807 | { |
1808 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1809 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1810 | }; |
acd5c798 MK |
1811 | struct i386_frame_cache cache; |
1812 | CORE_ADDR pc; | |
63c0089f | 1813 | gdb_byte op; |
acd5c798 | 1814 | int i; |
56bf0743 | 1815 | CORE_ADDR func_addr; |
4e879fc2 | 1816 | |
56bf0743 KB |
1817 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1818 | { | |
1819 | CORE_ADDR post_prologue_pc | |
1820 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1821 | struct symtab *s = find_pc_symtab (func_addr); | |
1822 | ||
1823 | /* Clang always emits a line note before the prologue and another | |
1824 | one after. We trust clang to emit usable line notes. */ | |
1825 | if (post_prologue_pc | |
1826 | && (s != NULL | |
1827 | && s->producer != NULL | |
1828 | && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0)) | |
1829 | return max (start_pc, post_prologue_pc); | |
1830 | } | |
1831 | ||
e0f33b1f | 1832 | cache.locals = -1; |
e17a4113 | 1833 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1834 | if (cache.locals < 0) |
1835 | return start_pc; | |
c5aa993b | 1836 | |
acd5c798 | 1837 | /* Found valid frame setup. */ |
c906108c | 1838 | |
fc338970 MK |
1839 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1840 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1841 | %ebx: |
1842 | ||
fc338970 MK |
1843 | call 0x0 |
1844 | popl %ebx | |
1845 | movl %ebx,x(%ebp) (optional) | |
1846 | addl y,%ebx | |
1847 | ||
c906108c SS |
1848 | This code is with the rest of the prologue (at the end of the |
1849 | function), so we have to skip it to get to the first real | |
1850 | instruction at the start of the function. */ | |
c5aa993b | 1851 | |
c906108c SS |
1852 | for (i = 0; i < 6; i++) |
1853 | { | |
0865b04a | 1854 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1855 | return pc; |
1856 | ||
c5aa993b | 1857 | if (pic_pat[i] != op) |
c906108c SS |
1858 | break; |
1859 | } | |
1860 | if (i == 6) | |
1861 | { | |
acd5c798 MK |
1862 | int delta = 6; |
1863 | ||
0865b04a | 1864 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1865 | return pc; |
c906108c | 1866 | |
c5aa993b | 1867 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1868 | { |
0865b04a | 1869 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1870 | |
fc338970 | 1871 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1872 | delta += 3; |
fc338970 | 1873 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1874 | delta += 6; |
fc338970 | 1875 | else /* Unexpected instruction. */ |
acd5c798 MK |
1876 | delta = 0; |
1877 | ||
0865b04a | 1878 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1879 | return pc; |
c906108c | 1880 | } |
acd5c798 | 1881 | |
c5aa993b | 1882 | /* addl y,%ebx */ |
acd5c798 | 1883 | if (delta > 0 && op == 0x81 |
0865b04a | 1884 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1885 | == 0xc3) |
c906108c | 1886 | { |
acd5c798 | 1887 | pc += delta + 6; |
c906108c SS |
1888 | } |
1889 | } | |
c5aa993b | 1890 | |
e63bbc88 MK |
1891 | /* If the function starts with a branch (to startup code at the end) |
1892 | the last instruction should bring us back to the first | |
1893 | instruction of the real code. */ | |
e17a4113 UW |
1894 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1895 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1896 | |
1897 | return pc; | |
c906108c SS |
1898 | } |
1899 | ||
4309257c PM |
1900 | /* Check that the code pointed to by PC corresponds to a call to |
1901 | __main, skip it if so. Return PC otherwise. */ | |
1902 | ||
1903 | CORE_ADDR | |
1904 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1905 | { | |
e17a4113 | 1906 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1907 | gdb_byte op; |
1908 | ||
0865b04a | 1909 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1910 | return pc; |
4309257c PM |
1911 | if (op == 0xe8) |
1912 | { | |
1913 | gdb_byte buf[4]; | |
1914 | ||
0865b04a | 1915 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
4309257c PM |
1916 | { |
1917 | /* Make sure address is computed correctly as a 32bit | |
1918 | integer even if CORE_ADDR is 64 bit wide. */ | |
7cbd4a93 | 1919 | struct bound_minimal_symbol s; |
e17a4113 | 1920 | CORE_ADDR call_dest; |
4309257c | 1921 | |
e17a4113 | 1922 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1923 | call_dest = call_dest & 0xffffffffU; |
1924 | s = lookup_minimal_symbol_by_pc (call_dest); | |
7cbd4a93 | 1925 | if (s.minsym != NULL |
efd66ac6 TT |
1926 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL |
1927 | && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0) | |
4309257c PM |
1928 | pc += 5; |
1929 | } | |
1930 | } | |
1931 | ||
1932 | return pc; | |
1933 | } | |
1934 | ||
acd5c798 | 1935 | /* This function is 64-bit safe. */ |
93924b6b | 1936 | |
acd5c798 MK |
1937 | static CORE_ADDR |
1938 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1939 | { |
63c0089f | 1940 | gdb_byte buf[8]; |
acd5c798 | 1941 | |
875f8d0e | 1942 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1943 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1944 | } |
acd5c798 | 1945 | \f |
93924b6b | 1946 | |
acd5c798 | 1947 | /* Normal frames. */ |
c5aa993b | 1948 | |
8fbca658 PA |
1949 | static void |
1950 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1951 | struct i386_frame_cache *cache) | |
a7769679 | 1952 | { |
e17a4113 UW |
1953 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1954 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1955 | gdb_byte buf[4]; |
acd5c798 MK |
1956 | int i; |
1957 | ||
8fbca658 | 1958 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1959 | |
1960 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1961 | which holds the base address for the current stack frame. | |
1962 | However, for functions that don't need it, the frame pointer is | |
1963 | optional. For these "frameless" functions the frame pointer is | |
1964 | actually the frame pointer of the calling frame. Signal | |
1965 | trampolines are just a special case of a "frameless" function. | |
1966 | They (usually) share their frame pointer with the frame that was | |
1967 | in progress when the signal occurred. */ | |
1968 | ||
10458914 | 1969 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1970 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1971 | if (cache->base == 0) |
620fa63a PA |
1972 | { |
1973 | cache->base_p = 1; | |
1974 | return; | |
1975 | } | |
acd5c798 MK |
1976 | |
1977 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1978 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1979 | |
acd5c798 | 1980 | if (cache->pc != 0) |
e17a4113 UW |
1981 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1982 | cache); | |
acd5c798 MK |
1983 | |
1984 | if (cache->locals < 0) | |
1985 | { | |
1986 | /* We didn't find a valid frame, which means that CACHE->base | |
1987 | currently holds the frame pointer for our calling frame. If | |
1988 | we're at the start of a function, or somewhere half-way its | |
1989 | prologue, the function's frame probably hasn't been fully | |
1990 | setup yet. Try to reconstruct the base address for the stack | |
1991 | frame by looking at the stack pointer. For truly "frameless" | |
1992 | functions this might work too. */ | |
1993 | ||
e0c62198 | 1994 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1995 | { |
8fbca658 PA |
1996 | /* Saved stack pointer has been saved. */ |
1997 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
1998 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1999 | ||
92dd43fa MK |
2000 | /* We're halfway aligning the stack. */ |
2001 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
2002 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
2003 | ||
2004 | /* This will be added back below. */ | |
2005 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
2006 | } | |
7618e12b | 2007 | else if (cache->pc != 0 |
0865b04a | 2008 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 2009 | { |
7618e12b DJ |
2010 | /* We're in a known function, but did not find a frame |
2011 | setup. Assume that the function does not use %ebp. | |
2012 | Alternatively, we may have jumped to an invalid | |
2013 | address; in that case there is definitely no new | |
2014 | frame in %ebp. */ | |
10458914 | 2015 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
2016 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
2017 | + cache->sp_offset; | |
92dd43fa | 2018 | } |
7618e12b DJ |
2019 | else |
2020 | /* We're in an unknown function. We could not find the start | |
2021 | of the function to analyze the prologue; our best option is | |
2022 | to assume a typical frame layout with the caller's %ebp | |
2023 | saved. */ | |
2024 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
2025 | } |
2026 | ||
8fbca658 PA |
2027 | if (cache->saved_sp_reg != -1) |
2028 | { | |
2029 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
2030 | register may be unavailable). */ | |
2031 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
2032 | && deprecated_frame_register_read (this_frame, |
2033 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
2034 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
2035 | } | |
acd5c798 MK |
2036 | /* Now that we have the base address for the stack frame we can |
2037 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 2038 | else if (cache->saved_sp == 0) |
92dd43fa | 2039 | cache->saved_sp = cache->base + 8; |
a7769679 | 2040 | |
acd5c798 MK |
2041 | /* Adjust all the saved registers such that they contain addresses |
2042 | instead of offsets. */ | |
2043 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
2044 | if (cache->saved_regs[i] != -1) |
2045 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 2046 | |
8fbca658 PA |
2047 | cache->base_p = 1; |
2048 | } | |
2049 | ||
2050 | static struct i386_frame_cache * | |
2051 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2052 | { | |
2053 | volatile struct gdb_exception ex; | |
2054 | struct i386_frame_cache *cache; | |
2055 | ||
2056 | if (*this_cache) | |
2057 | return *this_cache; | |
2058 | ||
2059 | cache = i386_alloc_frame_cache (); | |
2060 | *this_cache = cache; | |
2061 | ||
2062 | TRY_CATCH (ex, RETURN_MASK_ERROR) | |
2063 | { | |
2064 | i386_frame_cache_1 (this_frame, cache); | |
2065 | } | |
2066 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
2067 | throw_exception (ex); | |
2068 | ||
acd5c798 | 2069 | return cache; |
a7769679 MK |
2070 | } |
2071 | ||
3a1e71e3 | 2072 | static void |
10458914 | 2073 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 2074 | struct frame_id *this_id) |
c906108c | 2075 | { |
10458914 | 2076 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 2077 | |
5ce0145d PA |
2078 | if (!cache->base_p) |
2079 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
2080 | else if (cache->base == 0) | |
2081 | { | |
2082 | /* This marks the outermost frame. */ | |
2083 | } | |
2084 | else | |
2085 | { | |
2086 | /* See the end of i386_push_dummy_call. */ | |
2087 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
2088 | } | |
acd5c798 MK |
2089 | } |
2090 | ||
8fbca658 PA |
2091 | static enum unwind_stop_reason |
2092 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2093 | void **this_cache) | |
2094 | { | |
2095 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
2096 | ||
2097 | if (!cache->base_p) | |
2098 | return UNWIND_UNAVAILABLE; | |
2099 | ||
2100 | /* This marks the outermost frame. */ | |
2101 | if (cache->base == 0) | |
2102 | return UNWIND_OUTERMOST; | |
2103 | ||
2104 | return UNWIND_NO_REASON; | |
2105 | } | |
2106 | ||
10458914 DJ |
2107 | static struct value * |
2108 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2109 | int regnum) | |
acd5c798 | 2110 | { |
10458914 | 2111 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2112 | |
2113 | gdb_assert (regnum >= 0); | |
2114 | ||
2115 | /* The System V ABI says that: | |
2116 | ||
2117 | "The flags register contains the system flags, such as the | |
2118 | direction flag and the carry flag. The direction flag must be | |
2119 | set to the forward (that is, zero) direction before entry and | |
2120 | upon exit from a function. Other user flags have no specified | |
2121 | role in the standard calling sequence and are not preserved." | |
2122 | ||
2123 | To guarantee the "upon exit" part of that statement we fake a | |
2124 | saved flags register that has its direction flag cleared. | |
2125 | ||
2126 | Note that GCC doesn't seem to rely on the fact that the direction | |
2127 | flag is cleared after a function return; it always explicitly | |
2128 | clears the flag before operations where it matters. | |
2129 | ||
2130 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
2131 | right thing to do. The way we fake the flags register here makes | |
2132 | it impossible to change it. */ | |
2133 | ||
2134 | if (regnum == I386_EFLAGS_REGNUM) | |
2135 | { | |
10458914 | 2136 | ULONGEST val; |
c5aa993b | 2137 | |
10458914 DJ |
2138 | val = get_frame_register_unsigned (this_frame, regnum); |
2139 | val &= ~(1 << 10); | |
2140 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 2141 | } |
1211c4e4 | 2142 | |
acd5c798 | 2143 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 2144 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 2145 | |
fcf250e2 UW |
2146 | if (regnum == I386_ESP_REGNUM |
2147 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
2148 | { |
2149 | /* If the SP has been saved, but we don't know where, then this | |
2150 | means that SAVED_SP_REG register was found unavailable back | |
2151 | when we built the cache. */ | |
fcf250e2 | 2152 | if (cache->saved_sp == 0) |
8fbca658 PA |
2153 | return frame_unwind_got_register (this_frame, regnum, |
2154 | cache->saved_sp_reg); | |
2155 | else | |
2156 | return frame_unwind_got_constant (this_frame, regnum, | |
2157 | cache->saved_sp); | |
2158 | } | |
acd5c798 | 2159 | |
fd13a04a | 2160 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2161 | return frame_unwind_got_memory (this_frame, regnum, |
2162 | cache->saved_regs[regnum]); | |
fd13a04a | 2163 | |
10458914 | 2164 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
2165 | } |
2166 | ||
2167 | static const struct frame_unwind i386_frame_unwind = | |
2168 | { | |
2169 | NORMAL_FRAME, | |
8fbca658 | 2170 | i386_frame_unwind_stop_reason, |
acd5c798 | 2171 | i386_frame_this_id, |
10458914 DJ |
2172 | i386_frame_prev_register, |
2173 | NULL, | |
2174 | default_frame_sniffer | |
acd5c798 | 2175 | }; |
06da04c6 MS |
2176 | |
2177 | /* Normal frames, but in a function epilogue. */ | |
2178 | ||
2179 | /* The epilogue is defined here as the 'ret' instruction, which will | |
2180 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
2181 | the function's stack frame. */ | |
2182 | ||
2183 | static int | |
2184 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2185 | { | |
2186 | gdb_byte insn; | |
e0d00bc7 JK |
2187 | struct symtab *symtab; |
2188 | ||
2189 | symtab = find_pc_symtab (pc); | |
2190 | if (symtab && symtab->epilogue_unwind_valid) | |
2191 | return 0; | |
06da04c6 MS |
2192 | |
2193 | if (target_read_memory (pc, &insn, 1)) | |
2194 | return 0; /* Can't read memory at pc. */ | |
2195 | ||
2196 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2197 | return 0; | |
2198 | ||
2199 | return 1; | |
2200 | } | |
2201 | ||
2202 | static int | |
2203 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2204 | struct frame_info *this_frame, | |
2205 | void **this_prologue_cache) | |
2206 | { | |
2207 | if (frame_relative_level (this_frame) == 0) | |
2208 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
2209 | get_frame_pc (this_frame)); | |
2210 | else | |
2211 | return 0; | |
2212 | } | |
2213 | ||
2214 | static struct i386_frame_cache * | |
2215 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2216 | { | |
8fbca658 | 2217 | volatile struct gdb_exception ex; |
06da04c6 | 2218 | struct i386_frame_cache *cache; |
0d6c2135 | 2219 | CORE_ADDR sp; |
06da04c6 MS |
2220 | |
2221 | if (*this_cache) | |
2222 | return *this_cache; | |
2223 | ||
2224 | cache = i386_alloc_frame_cache (); | |
2225 | *this_cache = cache; | |
2226 | ||
8fbca658 PA |
2227 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
2228 | { | |
0d6c2135 | 2229 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2230 | |
0d6c2135 MK |
2231 | /* At this point the stack looks as if we just entered the |
2232 | function, with the return address at the top of the | |
2233 | stack. */ | |
2234 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2235 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2236 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2237 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2238 | |
8fbca658 PA |
2239 | cache->base_p = 1; |
2240 | } | |
2241 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
2242 | throw_exception (ex); | |
06da04c6 MS |
2243 | |
2244 | return cache; | |
2245 | } | |
2246 | ||
8fbca658 PA |
2247 | static enum unwind_stop_reason |
2248 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2249 | void **this_cache) | |
2250 | { | |
0d6c2135 MK |
2251 | struct i386_frame_cache *cache = |
2252 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2253 | |
2254 | if (!cache->base_p) | |
2255 | return UNWIND_UNAVAILABLE; | |
2256 | ||
2257 | return UNWIND_NO_REASON; | |
2258 | } | |
2259 | ||
06da04c6 MS |
2260 | static void |
2261 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2262 | void **this_cache, | |
2263 | struct frame_id *this_id) | |
2264 | { | |
0d6c2135 MK |
2265 | struct i386_frame_cache *cache = |
2266 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2267 | |
8fbca658 | 2268 | if (!cache->base_p) |
5ce0145d PA |
2269 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2270 | else | |
2271 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2272 | } |
2273 | ||
0d6c2135 MK |
2274 | static struct value * |
2275 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2276 | void **this_cache, int regnum) | |
2277 | { | |
2278 | /* Make sure we've initialized the cache. */ | |
2279 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2280 | ||
2281 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2282 | } | |
2283 | ||
06da04c6 MS |
2284 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2285 | { | |
2286 | NORMAL_FRAME, | |
8fbca658 | 2287 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2288 | i386_epilogue_frame_this_id, |
0d6c2135 | 2289 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2290 | NULL, |
2291 | i386_epilogue_frame_sniffer | |
2292 | }; | |
acd5c798 MK |
2293 | \f |
2294 | ||
a3fcb948 JG |
2295 | /* Stack-based trampolines. */ |
2296 | ||
2297 | /* These trampolines are used on cross x86 targets, when taking the | |
2298 | address of a nested function. When executing these trampolines, | |
2299 | no stack frame is set up, so we are in a similar situation as in | |
2300 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2301 | ||
2302 | /* Static chain passed in register. */ | |
2303 | ||
2304 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2305 | { | |
2306 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2307 | { 5, { 0xb8 }, { 0xfe } }, | |
2308 | ||
2309 | /* `jmp imm32' */ | |
2310 | { 5, { 0xe9 }, { 0xff } }, | |
2311 | ||
2312 | {0} | |
2313 | }; | |
2314 | ||
2315 | /* Static chain passed on stack (when regparm=3). */ | |
2316 | ||
2317 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2318 | { | |
2319 | /* `push imm32' */ | |
2320 | { 5, { 0x68 }, { 0xff } }, | |
2321 | ||
2322 | /* `jmp imm32' */ | |
2323 | { 5, { 0xe9 }, { 0xff } }, | |
2324 | ||
2325 | {0} | |
2326 | }; | |
2327 | ||
2328 | /* Return whether PC points inside a stack trampoline. */ | |
2329 | ||
2330 | static int | |
6df81a63 | 2331 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2332 | { |
2333 | gdb_byte insn; | |
2c02bd72 | 2334 | const char *name; |
a3fcb948 JG |
2335 | |
2336 | /* A stack trampoline is detected if no name is associated | |
2337 | to the current pc and if it points inside a trampoline | |
2338 | sequence. */ | |
2339 | ||
2340 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2341 | if (name) | |
2342 | return 0; | |
2343 | ||
2344 | if (target_read_memory (pc, &insn, 1)) | |
2345 | return 0; | |
2346 | ||
2347 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2348 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2349 | return 0; | |
2350 | ||
2351 | return 1; | |
2352 | } | |
2353 | ||
2354 | static int | |
2355 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2356 | struct frame_info *this_frame, |
2357 | void **this_cache) | |
a3fcb948 JG |
2358 | { |
2359 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2360 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2361 | else |
2362 | return 0; | |
2363 | } | |
2364 | ||
2365 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2366 | { | |
2367 | NORMAL_FRAME, | |
2368 | i386_epilogue_frame_unwind_stop_reason, | |
2369 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2370 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2371 | NULL, |
2372 | i386_stack_tramp_frame_sniffer | |
2373 | }; | |
2374 | \f | |
6710bf39 SS |
2375 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2376 | ||
2377 | static void | |
2378 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2379 | struct agent_expr *ax, struct axs_value *value, | |
2380 | CORE_ADDR scope) | |
2381 | { | |
2382 | /* The following sequence assumes the traditional use of the base | |
2383 | register. */ | |
2384 | ax_reg (ax, I386_EBP_REGNUM); | |
2385 | ax_const_l (ax, 4); | |
2386 | ax_simple (ax, aop_add); | |
2387 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2388 | value->kind = axs_lvalue_memory; | |
2389 | } | |
2390 | \f | |
a3fcb948 | 2391 | |
acd5c798 MK |
2392 | /* Signal trampolines. */ |
2393 | ||
2394 | static struct i386_frame_cache * | |
10458914 | 2395 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2396 | { |
e17a4113 UW |
2397 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2398 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2399 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2400 | volatile struct gdb_exception ex; |
acd5c798 | 2401 | struct i386_frame_cache *cache; |
acd5c798 | 2402 | CORE_ADDR addr; |
63c0089f | 2403 | gdb_byte buf[4]; |
acd5c798 MK |
2404 | |
2405 | if (*this_cache) | |
2406 | return *this_cache; | |
2407 | ||
fd13a04a | 2408 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2409 | |
8fbca658 | 2410 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
a3386186 | 2411 | { |
8fbca658 PA |
2412 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2413 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2414 | |
8fbca658 PA |
2415 | addr = tdep->sigcontext_addr (this_frame); |
2416 | if (tdep->sc_reg_offset) | |
2417 | { | |
2418 | int i; | |
a3386186 | 2419 | |
8fbca658 PA |
2420 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2421 | ||
2422 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2423 | if (tdep->sc_reg_offset[i] != -1) | |
2424 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2425 | } | |
2426 | else | |
2427 | { | |
2428 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2429 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2430 | } | |
2431 | ||
2432 | cache->base_p = 1; | |
a3386186 | 2433 | } |
8fbca658 PA |
2434 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
2435 | throw_exception (ex); | |
acd5c798 MK |
2436 | |
2437 | *this_cache = cache; | |
2438 | return cache; | |
2439 | } | |
2440 | ||
8fbca658 PA |
2441 | static enum unwind_stop_reason |
2442 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2443 | void **this_cache) | |
2444 | { | |
2445 | struct i386_frame_cache *cache = | |
2446 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2447 | ||
2448 | if (!cache->base_p) | |
2449 | return UNWIND_UNAVAILABLE; | |
2450 | ||
2451 | return UNWIND_NO_REASON; | |
2452 | } | |
2453 | ||
acd5c798 | 2454 | static void |
10458914 | 2455 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2456 | struct frame_id *this_id) |
2457 | { | |
2458 | struct i386_frame_cache *cache = | |
10458914 | 2459 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2460 | |
8fbca658 | 2461 | if (!cache->base_p) |
5ce0145d PA |
2462 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2463 | else | |
2464 | { | |
2465 | /* See the end of i386_push_dummy_call. */ | |
2466 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2467 | } | |
acd5c798 MK |
2468 | } |
2469 | ||
10458914 DJ |
2470 | static struct value * |
2471 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2472 | void **this_cache, int regnum) | |
acd5c798 MK |
2473 | { |
2474 | /* Make sure we've initialized the cache. */ | |
10458914 | 2475 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2476 | |
10458914 | 2477 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2478 | } |
c0d1d883 | 2479 | |
10458914 DJ |
2480 | static int |
2481 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2482 | struct frame_info *this_frame, | |
2483 | void **this_prologue_cache) | |
acd5c798 | 2484 | { |
10458914 | 2485 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2486 | |
911bc6ee MK |
2487 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2488 | handler. */ | |
2489 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2490 | return 0; |
1c3545ae | 2491 | |
911bc6ee MK |
2492 | if (tdep->sigtramp_p != NULL) |
2493 | { | |
10458914 DJ |
2494 | if (tdep->sigtramp_p (this_frame)) |
2495 | return 1; | |
911bc6ee MK |
2496 | } |
2497 | ||
2498 | if (tdep->sigtramp_start != 0) | |
2499 | { | |
10458914 | 2500 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2501 | |
2502 | gdb_assert (tdep->sigtramp_end != 0); | |
2503 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2504 | return 1; |
911bc6ee | 2505 | } |
acd5c798 | 2506 | |
10458914 | 2507 | return 0; |
acd5c798 | 2508 | } |
10458914 DJ |
2509 | |
2510 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2511 | { | |
2512 | SIGTRAMP_FRAME, | |
8fbca658 | 2513 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2514 | i386_sigtramp_frame_this_id, |
2515 | i386_sigtramp_frame_prev_register, | |
2516 | NULL, | |
2517 | i386_sigtramp_frame_sniffer | |
2518 | }; | |
acd5c798 MK |
2519 | \f |
2520 | ||
2521 | static CORE_ADDR | |
10458914 | 2522 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2523 | { |
10458914 | 2524 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2525 | |
2526 | return cache->base; | |
2527 | } | |
2528 | ||
2529 | static const struct frame_base i386_frame_base = | |
2530 | { | |
2531 | &i386_frame_unwind, | |
2532 | i386_frame_base_address, | |
2533 | i386_frame_base_address, | |
2534 | i386_frame_base_address | |
2535 | }; | |
2536 | ||
acd5c798 | 2537 | static struct frame_id |
10458914 | 2538 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2539 | { |
acd5c798 MK |
2540 | CORE_ADDR fp; |
2541 | ||
10458914 | 2542 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2543 | |
3e210248 | 2544 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2545 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2546 | } |
e04e5beb JM |
2547 | |
2548 | /* _Decimal128 function return values need 16-byte alignment on the | |
2549 | stack. */ | |
2550 | ||
2551 | static CORE_ADDR | |
2552 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2553 | { | |
2554 | return sp & -(CORE_ADDR)16; | |
2555 | } | |
fc338970 | 2556 | \f |
c906108c | 2557 | |
fc338970 MK |
2558 | /* Figure out where the longjmp will land. Slurp the args out of the |
2559 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2560 | structure from which we extract the address that we will land at. |
28bcfd30 | 2561 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2562 | success. */ |
c906108c | 2563 | |
8201327c | 2564 | static int |
60ade65d | 2565 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2566 | { |
436675d3 | 2567 | gdb_byte buf[4]; |
c906108c | 2568 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2569 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2570 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2571 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2572 | |
8201327c MK |
2573 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2574 | longjmp will land. */ | |
2575 | if (jb_pc_offset == -1) | |
c906108c SS |
2576 | return 0; |
2577 | ||
436675d3 | 2578 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2579 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2580 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2581 | return 0; |
2582 | ||
e17a4113 | 2583 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2584 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2585 | return 0; |
c906108c | 2586 | |
e17a4113 | 2587 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2588 | return 1; |
2589 | } | |
fc338970 | 2590 | \f |
c906108c | 2591 | |
7ccc1c74 JM |
2592 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2593 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2594 | unions containing such types must be 16-byte-aligned; other | |
2595 | arguments are 4-byte-aligned. */ | |
2596 | ||
2597 | static int | |
2598 | i386_16_byte_align_p (struct type *type) | |
2599 | { | |
2600 | type = check_typedef (type); | |
2601 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2602 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2603 | && TYPE_LENGTH (type) == 16) | |
2604 | return 1; | |
2605 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2606 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2607 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2608 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2609 | { | |
2610 | int i; | |
2611 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2612 | { | |
2613 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2614 | return 1; | |
2615 | } | |
2616 | } | |
2617 | return 0; | |
2618 | } | |
2619 | ||
a9b8d892 JK |
2620 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2621 | ||
2622 | static CORE_ADDR | |
2623 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2624 | struct value **args, int nargs, struct type *value_type, | |
2625 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2626 | struct regcache *regcache) | |
2627 | { | |
2628 | /* Use 0xcc breakpoint - 1 byte. */ | |
2629 | *bp_addr = sp - 1; | |
2630 | *real_pc = funaddr; | |
2631 | ||
2632 | /* Keep the stack aligned. */ | |
2633 | return sp - 16; | |
2634 | } | |
2635 | ||
3a1e71e3 | 2636 | static CORE_ADDR |
7d9b040b | 2637 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2638 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2639 | struct value **args, CORE_ADDR sp, int struct_return, | |
2640 | CORE_ADDR struct_addr) | |
22f8ba57 | 2641 | { |
e17a4113 | 2642 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2643 | gdb_byte buf[4]; |
acd5c798 | 2644 | int i; |
7ccc1c74 JM |
2645 | int write_pass; |
2646 | int args_space = 0; | |
acd5c798 | 2647 | |
7ccc1c74 JM |
2648 | /* Determine the total space required for arguments and struct |
2649 | return address in a first pass (allowing for 16-byte-aligned | |
2650 | arguments), then push arguments in a second pass. */ | |
2651 | ||
2652 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2653 | { |
7ccc1c74 | 2654 | int args_space_used = 0; |
7ccc1c74 JM |
2655 | |
2656 | if (struct_return) | |
2657 | { | |
2658 | if (write_pass) | |
2659 | { | |
2660 | /* Push value address. */ | |
e17a4113 | 2661 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2662 | write_memory (sp, buf, 4); |
2663 | args_space_used += 4; | |
2664 | } | |
2665 | else | |
2666 | args_space += 4; | |
2667 | } | |
2668 | ||
2669 | for (i = 0; i < nargs; i++) | |
2670 | { | |
2671 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2672 | |
7ccc1c74 JM |
2673 | if (write_pass) |
2674 | { | |
2675 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2676 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2677 | |
7ccc1c74 JM |
2678 | write_memory (sp + args_space_used, |
2679 | value_contents_all (args[i]), len); | |
2680 | /* The System V ABI says that: | |
acd5c798 | 2681 | |
7ccc1c74 JM |
2682 | "An argument's size is increased, if necessary, to make it a |
2683 | multiple of [32-bit] words. This may require tail padding, | |
2684 | depending on the size of the argument." | |
22f8ba57 | 2685 | |
7ccc1c74 JM |
2686 | This makes sure the stack stays word-aligned. */ |
2687 | args_space_used += align_up (len, 4); | |
2688 | } | |
2689 | else | |
2690 | { | |
2691 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2692 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2693 | args_space += align_up (len, 4); |
2694 | } | |
2695 | } | |
2696 | ||
2697 | if (!write_pass) | |
2698 | { | |
7ccc1c74 | 2699 | sp -= args_space; |
284c5a60 MK |
2700 | |
2701 | /* The original System V ABI only requires word alignment, | |
2702 | but modern incarnations need 16-byte alignment in order | |
2703 | to support SSE. Since wasting a few bytes here isn't | |
2704 | harmful we unconditionally enforce 16-byte alignment. */ | |
2705 | sp &= ~0xf; | |
7ccc1c74 | 2706 | } |
22f8ba57 MK |
2707 | } |
2708 | ||
acd5c798 MK |
2709 | /* Store return address. */ |
2710 | sp -= 4; | |
e17a4113 | 2711 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2712 | write_memory (sp, buf, 4); |
2713 | ||
2714 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2715 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2716 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2717 | ||
2718 | /* ...and fake a frame pointer. */ | |
2719 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2720 | ||
3e210248 AC |
2721 | /* MarkK wrote: This "+ 8" is all over the place: |
2722 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2723 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2724 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2725 | definition of the stack address of a frame. Otherwise frame id |
2726 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2727 | stack address *before* the function call as a frame's CFA. On |
2728 | the i386, when %ebp is used as a frame pointer, the offset | |
2729 | between the contents %ebp and the CFA as defined by GCC. */ | |
2730 | return sp + 8; | |
22f8ba57 MK |
2731 | } |
2732 | ||
1a309862 MK |
2733 | /* These registers are used for returning integers (and on some |
2734 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2735 | size and alignment match an integer type). */ |
acd5c798 MK |
2736 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2737 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2738 | |
c5e656c1 MK |
2739 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2740 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2741 | |
3a1e71e3 | 2742 | static void |
c5e656c1 | 2743 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2744 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2745 | { |
c5e656c1 | 2746 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2747 | int len = TYPE_LENGTH (type); |
63c0089f | 2748 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2749 | |
1e8d0a7b | 2750 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2751 | { |
5716833c | 2752 | if (tdep->st0_regnum < 0) |
1a309862 | 2753 | { |
8a3fe4f8 | 2754 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2755 | memset (valbuf, 0, len); |
ef9dff19 | 2756 | return; |
1a309862 MK |
2757 | } |
2758 | ||
c6ba6f0d MK |
2759 | /* Floating-point return values can be found in %st(0). Convert |
2760 | its contents to the desired type. This is probably not | |
2761 | exactly how it would happen on the target itself, but it is | |
2762 | the best we can do. */ | |
acd5c798 | 2763 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2764 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2765 | } |
2766 | else | |
c5aa993b | 2767 | { |
875f8d0e UW |
2768 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2769 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2770 | |
2771 | if (len <= low_size) | |
00f8375e | 2772 | { |
0818c12a | 2773 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2774 | memcpy (valbuf, buf, len); |
2775 | } | |
d4f3574e SS |
2776 | else if (len <= (low_size + high_size)) |
2777 | { | |
0818c12a | 2778 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2779 | memcpy (valbuf, buf, low_size); |
0818c12a | 2780 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2781 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2782 | } |
2783 | else | |
8e65ff28 | 2784 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2785 | _("Cannot extract return value of %d bytes long."), |
2786 | len); | |
c906108c SS |
2787 | } |
2788 | } | |
2789 | ||
c5e656c1 MK |
2790 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2791 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2792 | |
3a1e71e3 | 2793 | static void |
c5e656c1 | 2794 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2795 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2796 | { |
c5e656c1 | 2797 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2798 | int len = TYPE_LENGTH (type); |
2799 | ||
1e8d0a7b | 2800 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2801 | { |
3d7f4f49 | 2802 | ULONGEST fstat; |
63c0089f | 2803 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2804 | |
5716833c | 2805 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2806 | { |
8a3fe4f8 | 2807 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2808 | return; |
2809 | } | |
2810 | ||
635b0cc1 MK |
2811 | /* Returning floating-point values is a bit tricky. Apart from |
2812 | storing the return value in %st(0), we have to simulate the | |
2813 | state of the FPU at function return point. */ | |
2814 | ||
c6ba6f0d MK |
2815 | /* Convert the value found in VALBUF to the extended |
2816 | floating-point format used by the FPU. This is probably | |
2817 | not exactly how it would happen on the target itself, but | |
2818 | it is the best we can do. */ | |
27067745 | 2819 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2820 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2821 | |
635b0cc1 MK |
2822 | /* Set the top of the floating-point register stack to 7. The |
2823 | actual value doesn't really matter, but 7 is what a normal | |
2824 | function return would end up with if the program started out | |
2825 | with a freshly initialized FPU. */ | |
20a6ec49 | 2826 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2827 | fstat |= (7 << 11); |
20a6ec49 | 2828 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2829 | |
635b0cc1 MK |
2830 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2831 | the floating-point register stack to 7, the appropriate value | |
2832 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2833 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2834 | } |
2835 | else | |
2836 | { | |
875f8d0e UW |
2837 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2838 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2839 | |
2840 | if (len <= low_size) | |
3d7f4f49 | 2841 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2842 | else if (len <= (low_size + high_size)) |
2843 | { | |
3d7f4f49 MK |
2844 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2845 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2846 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2847 | } |
2848 | else | |
8e65ff28 | 2849 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2850 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2851 | } |
2852 | } | |
fc338970 | 2853 | \f |
ef9dff19 | 2854 | |
8201327c MK |
2855 | /* This is the variable that is set with "set struct-convention", and |
2856 | its legitimate values. */ | |
2857 | static const char default_struct_convention[] = "default"; | |
2858 | static const char pcc_struct_convention[] = "pcc"; | |
2859 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2860 | static const char *const valid_conventions[] = |
8201327c MK |
2861 | { |
2862 | default_struct_convention, | |
2863 | pcc_struct_convention, | |
2864 | reg_struct_convention, | |
2865 | NULL | |
2866 | }; | |
2867 | static const char *struct_convention = default_struct_convention; | |
2868 | ||
0e4377e1 JB |
2869 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2870 | a union type, or an array type, should be returned in registers | |
2871 | for architecture GDBARCH. */ | |
c5e656c1 | 2872 | |
8201327c | 2873 | static int |
c5e656c1 | 2874 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2875 | { |
c5e656c1 MK |
2876 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2877 | enum type_code code = TYPE_CODE (type); | |
2878 | int len = TYPE_LENGTH (type); | |
8201327c | 2879 | |
0e4377e1 JB |
2880 | gdb_assert (code == TYPE_CODE_STRUCT |
2881 | || code == TYPE_CODE_UNION | |
2882 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2883 | |
2884 | if (struct_convention == pcc_struct_convention | |
2885 | || (struct_convention == default_struct_convention | |
2886 | && tdep->struct_return == pcc_struct_return)) | |
2887 | return 0; | |
2888 | ||
9edde48e MK |
2889 | /* Structures consisting of a single `float', `double' or 'long |
2890 | double' member are returned in %st(0). */ | |
2891 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2892 | { | |
2893 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2894 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2895 | return (len == 4 || len == 8 || len == 12); | |
2896 | } | |
2897 | ||
c5e656c1 MK |
2898 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2899 | } | |
2900 | ||
2901 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2902 | should be returned. If it is supposed to be returned in registers, | |
2903 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2904 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2905 | from WRITEBUF into REGCACHE. */ | |
2906 | ||
2907 | static enum return_value_convention | |
6a3a010b | 2908 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2909 | struct type *type, struct regcache *regcache, |
2910 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2911 | { |
2912 | enum type_code code = TYPE_CODE (type); | |
2913 | ||
5daa78cc TJB |
2914 | if (((code == TYPE_CODE_STRUCT |
2915 | || code == TYPE_CODE_UNION | |
2916 | || code == TYPE_CODE_ARRAY) | |
2917 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2445fd7b MK |
2918 | /* Complex double and long double uses the struct return covention. */ |
2919 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) | |
2920 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2921 | /* 128-bit decimal float uses the struct return convention. */ |
2922 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2923 | { |
2924 | /* The System V ABI says that: | |
2925 | ||
2926 | "A function that returns a structure or union also sets %eax | |
2927 | to the value of the original address of the caller's area | |
2928 | before it returns. Thus when the caller receives control | |
2929 | again, the address of the returned object resides in register | |
2930 | %eax and can be used to access the object." | |
2931 | ||
2932 | So the ABI guarantees that we can always find the return | |
2933 | value just after the function has returned. */ | |
2934 | ||
0e4377e1 JB |
2935 | /* Note that the ABI doesn't mention functions returning arrays, |
2936 | which is something possible in certain languages such as Ada. | |
2937 | In this case, the value is returned as if it was wrapped in | |
2938 | a record, so the convention applied to records also applies | |
2939 | to arrays. */ | |
2940 | ||
31db7b6c MK |
2941 | if (readbuf) |
2942 | { | |
2943 | ULONGEST addr; | |
2944 | ||
2945 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2946 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2947 | } | |
2948 | ||
2949 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2950 | } | |
c5e656c1 MK |
2951 | |
2952 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2953 | `float', `double' or 'long double' member. These structures are |
2954 | returned in %st(0). For these structures, we call ourselves | |
2955 | recursively, changing TYPE into the type of the first member of | |
2956 | the structure. Since that should work for all structures that | |
2957 | have only one member, we don't bother to check the member's type | |
2958 | here. */ | |
c5e656c1 MK |
2959 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2960 | { | |
2961 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
6a3a010b | 2962 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 2963 | readbuf, writebuf); |
c5e656c1 MK |
2964 | } |
2965 | ||
2966 | if (readbuf) | |
2967 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2968 | if (writebuf) | |
2969 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2970 | |
c5e656c1 | 2971 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2972 | } |
2973 | \f | |
2974 | ||
27067745 UW |
2975 | struct type * |
2976 | i387_ext_type (struct gdbarch *gdbarch) | |
2977 | { | |
2978 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2979 | ||
2980 | if (!tdep->i387_ext_type) | |
90884b2b L |
2981 | { |
2982 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2983 | gdb_assert (tdep->i387_ext_type != NULL); | |
2984 | } | |
27067745 UW |
2985 | |
2986 | return tdep->i387_ext_type; | |
2987 | } | |
2988 | ||
1dbcd68c WT |
2989 | /* Construct type for pseudo BND registers. We can't use |
2990 | tdesc_find_type since a complement of one value has to be used | |
2991 | to describe the upper bound. */ | |
2992 | ||
2993 | static struct type * | |
2994 | i386_bnd_type (struct gdbarch *gdbarch) | |
2995 | { | |
2996 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2997 | ||
2998 | ||
2999 | if (!tdep->i386_bnd_type) | |
3000 | { | |
3001 | struct type *t, *bound_t; | |
3002 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3003 | ||
3004 | /* The type we're building is described bellow: */ | |
3005 | #if 0 | |
3006 | struct __bound128 | |
3007 | { | |
3008 | void *lbound; | |
3009 | void *ubound; /* One complement of raw ubound field. */ | |
3010 | }; | |
3011 | #endif | |
3012 | ||
3013 | t = arch_composite_type (gdbarch, | |
3014 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
3015 | ||
3016 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
3017 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
3018 | ||
3019 | TYPE_NAME (t) = "builtin_type_bound128"; | |
3020 | tdep->i386_bnd_type = t; | |
3021 | } | |
3022 | ||
3023 | return tdep->i386_bnd_type; | |
3024 | } | |
3025 | ||
01f9f808 MS |
3026 | /* Construct vector type for pseudo ZMM registers. We can't use |
3027 | tdesc_find_type since ZMM isn't described in target description. */ | |
3028 | ||
3029 | static struct type * | |
3030 | i386_zmm_type (struct gdbarch *gdbarch) | |
3031 | { | |
3032 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3033 | ||
3034 | if (!tdep->i386_zmm_type) | |
3035 | { | |
3036 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3037 | ||
3038 | /* The type we're building is this: */ | |
3039 | #if 0 | |
3040 | union __gdb_builtin_type_vec512i | |
3041 | { | |
3042 | int128_t uint128[4]; | |
3043 | int64_t v4_int64[8]; | |
3044 | int32_t v8_int32[16]; | |
3045 | int16_t v16_int16[32]; | |
3046 | int8_t v32_int8[64]; | |
3047 | double v4_double[8]; | |
3048 | float v8_float[16]; | |
3049 | }; | |
3050 | #endif | |
3051 | ||
3052 | struct type *t; | |
3053 | ||
3054 | t = arch_composite_type (gdbarch, | |
3055 | "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); | |
3056 | append_composite_type_field (t, "v16_float", | |
3057 | init_vector_type (bt->builtin_float, 16)); | |
3058 | append_composite_type_field (t, "v8_double", | |
3059 | init_vector_type (bt->builtin_double, 8)); | |
3060 | append_composite_type_field (t, "v64_int8", | |
3061 | init_vector_type (bt->builtin_int8, 64)); | |
3062 | append_composite_type_field (t, "v32_int16", | |
3063 | init_vector_type (bt->builtin_int16, 32)); | |
3064 | append_composite_type_field (t, "v16_int32", | |
3065 | init_vector_type (bt->builtin_int32, 16)); | |
3066 | append_composite_type_field (t, "v8_int64", | |
3067 | init_vector_type (bt->builtin_int64, 8)); | |
3068 | append_composite_type_field (t, "v4_int128", | |
3069 | init_vector_type (bt->builtin_int128, 4)); | |
3070 | ||
3071 | TYPE_VECTOR (t) = 1; | |
3072 | TYPE_NAME (t) = "builtin_type_vec512i"; | |
3073 | tdep->i386_zmm_type = t; | |
3074 | } | |
3075 | ||
3076 | return tdep->i386_zmm_type; | |
3077 | } | |
3078 | ||
c131fcee L |
3079 | /* Construct vector type for pseudo YMM registers. We can't use |
3080 | tdesc_find_type since YMM isn't described in target description. */ | |
3081 | ||
3082 | static struct type * | |
3083 | i386_ymm_type (struct gdbarch *gdbarch) | |
3084 | { | |
3085 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3086 | ||
3087 | if (!tdep->i386_ymm_type) | |
3088 | { | |
3089 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3090 | ||
3091 | /* The type we're building is this: */ | |
3092 | #if 0 | |
3093 | union __gdb_builtin_type_vec256i | |
3094 | { | |
3095 | int128_t uint128[2]; | |
3096 | int64_t v2_int64[4]; | |
3097 | int32_t v4_int32[8]; | |
3098 | int16_t v8_int16[16]; | |
3099 | int8_t v16_int8[32]; | |
3100 | double v2_double[4]; | |
3101 | float v4_float[8]; | |
3102 | }; | |
3103 | #endif | |
3104 | ||
3105 | struct type *t; | |
3106 | ||
3107 | t = arch_composite_type (gdbarch, | |
3108 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
3109 | append_composite_type_field (t, "v8_float", | |
3110 | init_vector_type (bt->builtin_float, 8)); | |
3111 | append_composite_type_field (t, "v4_double", | |
3112 | init_vector_type (bt->builtin_double, 4)); | |
3113 | append_composite_type_field (t, "v32_int8", | |
3114 | init_vector_type (bt->builtin_int8, 32)); | |
3115 | append_composite_type_field (t, "v16_int16", | |
3116 | init_vector_type (bt->builtin_int16, 16)); | |
3117 | append_composite_type_field (t, "v8_int32", | |
3118 | init_vector_type (bt->builtin_int32, 8)); | |
3119 | append_composite_type_field (t, "v4_int64", | |
3120 | init_vector_type (bt->builtin_int64, 4)); | |
3121 | append_composite_type_field (t, "v2_int128", | |
3122 | init_vector_type (bt->builtin_int128, 2)); | |
3123 | ||
3124 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 3125 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
3126 | tdep->i386_ymm_type = t; |
3127 | } | |
3128 | ||
3129 | return tdep->i386_ymm_type; | |
3130 | } | |
3131 | ||
794ac428 | 3132 | /* Construct vector type for MMX registers. */ |
90884b2b | 3133 | static struct type * |
794ac428 UW |
3134 | i386_mmx_type (struct gdbarch *gdbarch) |
3135 | { | |
3136 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3137 | ||
3138 | if (!tdep->i386_mmx_type) | |
3139 | { | |
df4df182 UW |
3140 | const struct builtin_type *bt = builtin_type (gdbarch); |
3141 | ||
794ac428 UW |
3142 | /* The type we're building is this: */ |
3143 | #if 0 | |
3144 | union __gdb_builtin_type_vec64i | |
3145 | { | |
3146 | int64_t uint64; | |
3147 | int32_t v2_int32[2]; | |
3148 | int16_t v4_int16[4]; | |
3149 | int8_t v8_int8[8]; | |
3150 | }; | |
3151 | #endif | |
3152 | ||
3153 | struct type *t; | |
3154 | ||
e9bb382b UW |
3155 | t = arch_composite_type (gdbarch, |
3156 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
3157 | |
3158 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 3159 | append_composite_type_field (t, "v2_int32", |
df4df182 | 3160 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 3161 | append_composite_type_field (t, "v4_int16", |
df4df182 | 3162 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 3163 | append_composite_type_field (t, "v8_int8", |
df4df182 | 3164 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 3165 | |
876cecd0 | 3166 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
3167 | TYPE_NAME (t) = "builtin_type_vec64i"; |
3168 | tdep->i386_mmx_type = t; | |
3169 | } | |
3170 | ||
3171 | return tdep->i386_mmx_type; | |
3172 | } | |
3173 | ||
d7a0d72c | 3174 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 3175 | register REGNUM. */ |
d7a0d72c | 3176 | |
fff4548b | 3177 | struct type * |
90884b2b | 3178 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 3179 | { |
1dbcd68c WT |
3180 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3181 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
3182 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
3183 | return i386_mmx_type (gdbarch); | |
c131fcee L |
3184 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
3185 | return i386_ymm_type (gdbarch); | |
01f9f808 MS |
3186 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3187 | return i386_ymm_type (gdbarch); | |
3188 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3189 | return i386_zmm_type (gdbarch); | |
1ba53b71 L |
3190 | else |
3191 | { | |
3192 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3193 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
3194 | return bt->builtin_int8; | |
3195 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3196 | return bt->builtin_int16; | |
3197 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
3198 | return bt->builtin_int32; | |
01f9f808 MS |
3199 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3200 | return bt->builtin_int64; | |
1ba53b71 L |
3201 | } |
3202 | ||
3203 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
3204 | } |
3205 | ||
28fc6740 | 3206 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 3207 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
3208 | |
3209 | static int | |
c86c27af | 3210 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 3211 | { |
5716833c MK |
3212 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
3213 | int mmxreg, fpreg; | |
28fc6740 AC |
3214 | ULONGEST fstat; |
3215 | int tos; | |
c86c27af | 3216 | |
5716833c | 3217 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 3218 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 3219 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
3220 | fpreg = (mmxreg + tos) % 8; |
3221 | ||
20a6ec49 | 3222 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
3223 | } |
3224 | ||
3543a589 TT |
3225 | /* A helper function for us by i386_pseudo_register_read_value and |
3226 | amd64_pseudo_register_read_value. It does all the work but reads | |
3227 | the data into an already-allocated value. */ | |
3228 | ||
3229 | void | |
3230 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
3231 | struct regcache *regcache, | |
3232 | int regnum, | |
3233 | struct value *result_value) | |
28fc6740 | 3234 | { |
1ba53b71 | 3235 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 3236 | enum register_status status; |
3543a589 | 3237 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 3238 | |
5716833c | 3239 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3240 | { |
c86c27af MK |
3241 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3242 | ||
28fc6740 | 3243 | /* Extract (always little endian). */ |
05d1431c PA |
3244 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
3245 | if (status != REG_VALID) | |
3543a589 TT |
3246 | mark_value_bytes_unavailable (result_value, 0, |
3247 | TYPE_LENGTH (value_type (result_value))); | |
3248 | else | |
3249 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3250 | } |
3251 | else | |
1ba53b71 L |
3252 | { |
3253 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dbcd68c WT |
3254 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3255 | { | |
3256 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3257 | |
1dbcd68c WT |
3258 | /* Extract (always little endian). Read lower 128bits. */ |
3259 | status = regcache_raw_read (regcache, | |
3260 | I387_BND0R_REGNUM (tdep) + regnum, | |
3261 | raw_buf); | |
3262 | if (status != REG_VALID) | |
3263 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3264 | else | |
3265 | { | |
3266 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3267 | LONGEST upper, lower; | |
3268 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3269 | ||
3270 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3271 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3272 | upper = ~upper; | |
3273 | ||
3274 | memcpy (buf, &lower, size); | |
3275 | memcpy (buf + size, &upper, size); | |
3276 | } | |
3277 | } | |
01f9f808 MS |
3278 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3279 | { | |
3280 | regnum -= tdep->k0_regnum; | |
3281 | ||
3282 | /* Extract (always little endian). */ | |
3283 | status = regcache_raw_read (regcache, | |
3284 | tdep->k0_regnum + regnum, | |
3285 | raw_buf); | |
3286 | if (status != REG_VALID) | |
3287 | mark_value_bytes_unavailable (result_value, 0, 8); | |
3288 | else | |
3289 | memcpy (buf, raw_buf, 8); | |
3290 | } | |
3291 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3292 | { | |
3293 | regnum -= tdep->zmm0_regnum; | |
3294 | ||
3295 | if (regnum < num_lower_zmm_regs) | |
3296 | { | |
3297 | /* Extract (always little endian). Read lower 128bits. */ | |
3298 | status = regcache_raw_read (regcache, | |
3299 | I387_XMM0_REGNUM (tdep) + regnum, | |
3300 | raw_buf); | |
3301 | if (status != REG_VALID) | |
3302 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3303 | else | |
3304 | memcpy (buf, raw_buf, 16); | |
3305 | ||
3306 | /* Extract (always little endian). Read upper 128bits. */ | |
3307 | status = regcache_raw_read (regcache, | |
3308 | tdep->ymm0h_regnum + regnum, | |
3309 | raw_buf); | |
3310 | if (status != REG_VALID) | |
3311 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3312 | else | |
3313 | memcpy (buf + 16, raw_buf, 16); | |
3314 | } | |
3315 | else | |
3316 | { | |
3317 | /* Extract (always little endian). Read lower 128bits. */ | |
3318 | status = regcache_raw_read (regcache, | |
3319 | I387_XMM16_REGNUM (tdep) + regnum | |
3320 | - num_lower_zmm_regs, | |
3321 | raw_buf); | |
3322 | if (status != REG_VALID) | |
3323 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3324 | else | |
3325 | memcpy (buf, raw_buf, 16); | |
3326 | ||
3327 | /* Extract (always little endian). Read upper 128bits. */ | |
3328 | status = regcache_raw_read (regcache, | |
3329 | I387_YMM16H_REGNUM (tdep) + regnum | |
3330 | - num_lower_zmm_regs, | |
3331 | raw_buf); | |
3332 | if (status != REG_VALID) | |
3333 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3334 | else | |
3335 | memcpy (buf + 16, raw_buf, 16); | |
3336 | } | |
3337 | ||
3338 | /* Read upper 256bits. */ | |
3339 | status = regcache_raw_read (regcache, | |
3340 | tdep->zmm0h_regnum + regnum, | |
3341 | raw_buf); | |
3342 | if (status != REG_VALID) | |
3343 | mark_value_bytes_unavailable (result_value, 32, 32); | |
3344 | else | |
3345 | memcpy (buf + 32, raw_buf, 32); | |
3346 | } | |
1dbcd68c | 3347 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3348 | { |
3349 | regnum -= tdep->ymm0_regnum; | |
3350 | ||
1777feb0 | 3351 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
3352 | status = regcache_raw_read (regcache, |
3353 | I387_XMM0_REGNUM (tdep) + regnum, | |
3354 | raw_buf); | |
3355 | if (status != REG_VALID) | |
3543a589 TT |
3356 | mark_value_bytes_unavailable (result_value, 0, 16); |
3357 | else | |
3358 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3359 | /* Read upper 128bits. */ |
05d1431c PA |
3360 | status = regcache_raw_read (regcache, |
3361 | tdep->ymm0h_regnum + regnum, | |
3362 | raw_buf); | |
3363 | if (status != REG_VALID) | |
3543a589 TT |
3364 | mark_value_bytes_unavailable (result_value, 16, 32); |
3365 | else | |
3366 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee | 3367 | } |
01f9f808 MS |
3368 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3369 | { | |
3370 | regnum -= tdep->ymm16_regnum; | |
3371 | /* Extract (always little endian). Read lower 128bits. */ | |
3372 | status = regcache_raw_read (regcache, | |
3373 | I387_XMM16_REGNUM (tdep) + regnum, | |
3374 | raw_buf); | |
3375 | if (status != REG_VALID) | |
3376 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3377 | else | |
3378 | memcpy (buf, raw_buf, 16); | |
3379 | /* Read upper 128bits. */ | |
3380 | status = regcache_raw_read (regcache, | |
3381 | tdep->ymm16h_regnum + regnum, | |
3382 | raw_buf); | |
3383 | if (status != REG_VALID) | |
3384 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3385 | else | |
3386 | memcpy (buf + 16, raw_buf, 16); | |
3387 | } | |
c131fcee | 3388 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3389 | { |
3390 | int gpnum = regnum - tdep->ax_regnum; | |
3391 | ||
3392 | /* Extract (always little endian). */ | |
05d1431c PA |
3393 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
3394 | if (status != REG_VALID) | |
3543a589 TT |
3395 | mark_value_bytes_unavailable (result_value, 0, |
3396 | TYPE_LENGTH (value_type (result_value))); | |
3397 | else | |
3398 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3399 | } |
3400 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3401 | { | |
3402 | /* Check byte pseudo registers last since this function will | |
3403 | be called from amd64_pseudo_register_read, which handles | |
3404 | byte pseudo registers differently. */ | |
3405 | int gpnum = regnum - tdep->al_regnum; | |
3406 | ||
3407 | /* Extract (always little endian). We read both lower and | |
3408 | upper registers. */ | |
05d1431c PA |
3409 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
3410 | if (status != REG_VALID) | |
3543a589 TT |
3411 | mark_value_bytes_unavailable (result_value, 0, |
3412 | TYPE_LENGTH (value_type (result_value))); | |
3413 | else if (gpnum >= 4) | |
1ba53b71 L |
3414 | memcpy (buf, raw_buf + 1, 1); |
3415 | else | |
3416 | memcpy (buf, raw_buf, 1); | |
3417 | } | |
3418 | else | |
3419 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3420 | } | |
3543a589 TT |
3421 | } |
3422 | ||
3423 | static struct value * | |
3424 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
3425 | struct regcache *regcache, | |
3426 | int regnum) | |
3427 | { | |
3428 | struct value *result; | |
3429 | ||
3430 | result = allocate_value (register_type (gdbarch, regnum)); | |
3431 | VALUE_LVAL (result) = lval_register; | |
3432 | VALUE_REGNUM (result) = regnum; | |
3433 | ||
3434 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3435 | |
3543a589 | 3436 | return result; |
28fc6740 AC |
3437 | } |
3438 | ||
1ba53b71 | 3439 | void |
28fc6740 | 3440 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3441 | int regnum, const gdb_byte *buf) |
28fc6740 | 3442 | { |
1ba53b71 L |
3443 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
3444 | ||
5716833c | 3445 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3446 | { |
c86c27af MK |
3447 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3448 | ||
28fc6740 | 3449 | /* Read ... */ |
1ba53b71 | 3450 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 3451 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3452 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3453 | /* ... Write. */ |
1ba53b71 | 3454 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
3455 | } |
3456 | else | |
1ba53b71 L |
3457 | { |
3458 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3459 | ||
1dbcd68c WT |
3460 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3461 | { | |
3462 | ULONGEST upper, lower; | |
3463 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3464 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3465 | ||
3466 | /* New values from input value. */ | |
3467 | regnum -= tdep->bnd0_regnum; | |
3468 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3469 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3470 | ||
3471 | /* Fetching register buffer. */ | |
3472 | regcache_raw_read (regcache, | |
3473 | I387_BND0R_REGNUM (tdep) + regnum, | |
3474 | raw_buf); | |
3475 | ||
3476 | upper = ~upper; | |
3477 | ||
3478 | /* Set register bits. */ | |
3479 | memcpy (raw_buf, &lower, 8); | |
3480 | memcpy (raw_buf + 8, &upper, 8); | |
3481 | ||
3482 | ||
3483 | regcache_raw_write (regcache, | |
3484 | I387_BND0R_REGNUM (tdep) + regnum, | |
3485 | raw_buf); | |
3486 | } | |
01f9f808 MS |
3487 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3488 | { | |
3489 | regnum -= tdep->k0_regnum; | |
3490 | ||
3491 | regcache_raw_write (regcache, | |
3492 | tdep->k0_regnum + regnum, | |
3493 | buf); | |
3494 | } | |
3495 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3496 | { | |
3497 | regnum -= tdep->zmm0_regnum; | |
3498 | ||
3499 | if (regnum < num_lower_zmm_regs) | |
3500 | { | |
3501 | /* Write lower 128bits. */ | |
3502 | regcache_raw_write (regcache, | |
3503 | I387_XMM0_REGNUM (tdep) + regnum, | |
3504 | buf); | |
3505 | /* Write upper 128bits. */ | |
3506 | regcache_raw_write (regcache, | |
3507 | I387_YMM0_REGNUM (tdep) + regnum, | |
3508 | buf + 16); | |
3509 | } | |
3510 | else | |
3511 | { | |
3512 | /* Write lower 128bits. */ | |
3513 | regcache_raw_write (regcache, | |
3514 | I387_XMM16_REGNUM (tdep) + regnum | |
3515 | - num_lower_zmm_regs, | |
3516 | buf); | |
3517 | /* Write upper 128bits. */ | |
3518 | regcache_raw_write (regcache, | |
3519 | I387_YMM16H_REGNUM (tdep) + regnum | |
3520 | - num_lower_zmm_regs, | |
3521 | buf + 16); | |
3522 | } | |
3523 | /* Write upper 256bits. */ | |
3524 | regcache_raw_write (regcache, | |
3525 | tdep->zmm0h_regnum + regnum, | |
3526 | buf + 32); | |
3527 | } | |
1dbcd68c | 3528 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3529 | { |
3530 | regnum -= tdep->ymm0_regnum; | |
3531 | ||
3532 | /* ... Write lower 128bits. */ | |
3533 | regcache_raw_write (regcache, | |
3534 | I387_XMM0_REGNUM (tdep) + regnum, | |
3535 | buf); | |
3536 | /* ... Write upper 128bits. */ | |
3537 | regcache_raw_write (regcache, | |
3538 | tdep->ymm0h_regnum + regnum, | |
3539 | buf + 16); | |
3540 | } | |
01f9f808 MS |
3541 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3542 | { | |
3543 | regnum -= tdep->ymm16_regnum; | |
3544 | ||
3545 | /* ... Write lower 128bits. */ | |
3546 | regcache_raw_write (regcache, | |
3547 | I387_XMM16_REGNUM (tdep) + regnum, | |
3548 | buf); | |
3549 | /* ... Write upper 128bits. */ | |
3550 | regcache_raw_write (regcache, | |
3551 | tdep->ymm16h_regnum + regnum, | |
3552 | buf + 16); | |
3553 | } | |
c131fcee | 3554 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3555 | { |
3556 | int gpnum = regnum - tdep->ax_regnum; | |
3557 | ||
3558 | /* Read ... */ | |
3559 | regcache_raw_read (regcache, gpnum, raw_buf); | |
3560 | /* ... Modify ... (always little endian). */ | |
3561 | memcpy (raw_buf, buf, 2); | |
3562 | /* ... Write. */ | |
3563 | regcache_raw_write (regcache, gpnum, raw_buf); | |
3564 | } | |
3565 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3566 | { | |
3567 | /* Check byte pseudo registers last since this function will | |
3568 | be called from amd64_pseudo_register_read, which handles | |
3569 | byte pseudo registers differently. */ | |
3570 | int gpnum = regnum - tdep->al_regnum; | |
3571 | ||
3572 | /* Read ... We read both lower and upper registers. */ | |
3573 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
3574 | /* ... Modify ... (always little endian). */ | |
3575 | if (gpnum >= 4) | |
3576 | memcpy (raw_buf + 1, buf, 1); | |
3577 | else | |
3578 | memcpy (raw_buf, buf, 1); | |
3579 | /* ... Write. */ | |
3580 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
3581 | } | |
3582 | else | |
3583 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3584 | } | |
28fc6740 | 3585 | } |
ff2e87ac AC |
3586 | \f |
3587 | ||
ff2e87ac AC |
3588 | /* Return the register number of the register allocated by GCC after |
3589 | REGNUM, or -1 if there is no such register. */ | |
3590 | ||
3591 | static int | |
3592 | i386_next_regnum (int regnum) | |
3593 | { | |
3594 | /* GCC allocates the registers in the order: | |
3595 | ||
3596 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3597 | ||
3598 | Since storing a variable in %esp doesn't make any sense we return | |
3599 | -1 for %ebp and for %esp itself. */ | |
3600 | static int next_regnum[] = | |
3601 | { | |
3602 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3603 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3604 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3605 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3606 | -1, -1, /* Slots for %esp and %ebp. */ | |
3607 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3608 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3609 | }; | |
3610 | ||
de5b9bb9 | 3611 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3612 | return next_regnum[regnum]; |
28fc6740 | 3613 | |
ff2e87ac AC |
3614 | return -1; |
3615 | } | |
3616 | ||
3617 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3618 | needs any special handling. */ | |
d7a0d72c | 3619 | |
3a1e71e3 | 3620 | static int |
1777feb0 MS |
3621 | i386_convert_register_p (struct gdbarch *gdbarch, |
3622 | int regnum, struct type *type) | |
d7a0d72c | 3623 | { |
de5b9bb9 MK |
3624 | int len = TYPE_LENGTH (type); |
3625 | ||
ff2e87ac AC |
3626 | /* Values may be spread across multiple registers. Most debugging |
3627 | formats aren't expressive enough to specify the locations, so | |
3628 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3629 | have a length that is a multiple of the word size, since GCC |
3630 | doesn't seem to put any other types into registers. */ | |
3631 | if (len > 4 && len % 4 == 0) | |
3632 | { | |
3633 | int last_regnum = regnum; | |
3634 | ||
3635 | while (len > 4) | |
3636 | { | |
3637 | last_regnum = i386_next_regnum (last_regnum); | |
3638 | len -= 4; | |
3639 | } | |
3640 | ||
3641 | if (last_regnum != -1) | |
3642 | return 1; | |
3643 | } | |
ff2e87ac | 3644 | |
0abe36f5 | 3645 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3646 | } |
3647 | ||
ff2e87ac AC |
3648 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3649 | return its contents in TO. */ | |
ac27f131 | 3650 | |
8dccd430 | 3651 | static int |
ff2e87ac | 3652 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3653 | struct type *type, gdb_byte *to, |
3654 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3655 | { |
20a6ec49 | 3656 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3657 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3658 | |
20a6ec49 | 3659 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3660 | return i387_register_to_value (frame, regnum, type, to, |
3661 | optimizedp, unavailablep); | |
ff2e87ac | 3662 | |
fd35795f | 3663 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3664 | |
3665 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3666 | |
de5b9bb9 MK |
3667 | while (len > 0) |
3668 | { | |
3669 | gdb_assert (regnum != -1); | |
20a6ec49 | 3670 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3671 | |
8dccd430 PA |
3672 | if (!get_frame_register_bytes (frame, regnum, 0, |
3673 | register_size (gdbarch, regnum), | |
3674 | to, optimizedp, unavailablep)) | |
3675 | return 0; | |
3676 | ||
de5b9bb9 MK |
3677 | regnum = i386_next_regnum (regnum); |
3678 | len -= 4; | |
42835c2b | 3679 | to += 4; |
de5b9bb9 | 3680 | } |
8dccd430 PA |
3681 | |
3682 | *optimizedp = *unavailablep = 0; | |
3683 | return 1; | |
ac27f131 MK |
3684 | } |
3685 | ||
ff2e87ac AC |
3686 | /* Write the contents FROM of a value of type TYPE into register |
3687 | REGNUM in frame FRAME. */ | |
ac27f131 | 3688 | |
3a1e71e3 | 3689 | static void |
ff2e87ac | 3690 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3691 | struct type *type, const gdb_byte *from) |
ac27f131 | 3692 | { |
de5b9bb9 | 3693 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3694 | |
20a6ec49 | 3695 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3696 | { |
d532c08f MK |
3697 | i387_value_to_register (frame, regnum, type, from); |
3698 | return; | |
3699 | } | |
3d261580 | 3700 | |
fd35795f | 3701 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3702 | |
3703 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3704 | |
de5b9bb9 MK |
3705 | while (len > 0) |
3706 | { | |
3707 | gdb_assert (regnum != -1); | |
875f8d0e | 3708 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3709 | |
42835c2b | 3710 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3711 | regnum = i386_next_regnum (regnum); |
3712 | len -= 4; | |
42835c2b | 3713 | from += 4; |
de5b9bb9 | 3714 | } |
ac27f131 | 3715 | } |
ff2e87ac | 3716 | \f |
7fdafb5a MK |
3717 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3718 | in the general-purpose register set REGSET to register cache | |
3719 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3720 | |
20187ed5 | 3721 | void |
473f17b0 MK |
3722 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3723 | int regnum, const void *gregs, size_t len) | |
3724 | { | |
09424cff AA |
3725 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3726 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
156cdbee | 3727 | const gdb_byte *regs = gregs; |
473f17b0 MK |
3728 | int i; |
3729 | ||
3730 | gdb_assert (len == tdep->sizeof_gregset); | |
3731 | ||
3732 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3733 | { | |
3734 | if ((regnum == i || regnum == -1) | |
3735 | && tdep->gregset_reg_offset[i] != -1) | |
3736 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3737 | } | |
3738 | } | |
3739 | ||
7fdafb5a MK |
3740 | /* Collect register REGNUM from the register cache REGCACHE and store |
3741 | it in the buffer specified by GREGS and LEN as described by the | |
3742 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3743 | all registers in REGSET. */ | |
3744 | ||
ecc37a5a | 3745 | static void |
7fdafb5a MK |
3746 | i386_collect_gregset (const struct regset *regset, |
3747 | const struct regcache *regcache, | |
3748 | int regnum, void *gregs, size_t len) | |
3749 | { | |
09424cff AA |
3750 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3751 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
156cdbee | 3752 | gdb_byte *regs = gregs; |
7fdafb5a MK |
3753 | int i; |
3754 | ||
3755 | gdb_assert (len == tdep->sizeof_gregset); | |
3756 | ||
3757 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3758 | { | |
3759 | if ((regnum == i || regnum == -1) | |
3760 | && tdep->gregset_reg_offset[i] != -1) | |
3761 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3762 | } | |
3763 | } | |
3764 | ||
3765 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3766 | in the floating-point register set REGSET to register cache | |
3767 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3768 | |
3769 | static void | |
3770 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3771 | int regnum, const void *fpregs, size_t len) | |
3772 | { | |
09424cff AA |
3773 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3774 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
473f17b0 | 3775 | |
66a72d25 MK |
3776 | if (len == I387_SIZEOF_FXSAVE) |
3777 | { | |
3778 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3779 | return; | |
3780 | } | |
3781 | ||
473f17b0 MK |
3782 | gdb_assert (len == tdep->sizeof_fpregset); |
3783 | i387_supply_fsave (regcache, regnum, fpregs); | |
3784 | } | |
8446b36a | 3785 | |
2f305df1 MK |
3786 | /* Collect register REGNUM from the register cache REGCACHE and store |
3787 | it in the buffer specified by FPREGS and LEN as described by the | |
3788 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3789 | all registers in REGSET. */ | |
7fdafb5a MK |
3790 | |
3791 | static void | |
3792 | i386_collect_fpregset (const struct regset *regset, | |
3793 | const struct regcache *regcache, | |
3794 | int regnum, void *fpregs, size_t len) | |
3795 | { | |
09424cff AA |
3796 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3797 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7fdafb5a MK |
3798 | |
3799 | if (len == I387_SIZEOF_FXSAVE) | |
3800 | { | |
3801 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3802 | return; | |
3803 | } | |
3804 | ||
3805 | gdb_assert (len == tdep->sizeof_fpregset); | |
3806 | i387_collect_fsave (regcache, regnum, fpregs); | |
3807 | } | |
3808 | ||
c131fcee L |
3809 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
3810 | ||
3811 | static void | |
3812 | i386_supply_xstateregset (const struct regset *regset, | |
3813 | struct regcache *regcache, int regnum, | |
3814 | const void *xstateregs, size_t len) | |
3815 | { | |
c131fcee L |
3816 | i387_supply_xsave (regcache, regnum, xstateregs); |
3817 | } | |
3818 | ||
3819 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
3820 | ||
3821 | static void | |
3822 | i386_collect_xstateregset (const struct regset *regset, | |
3823 | const struct regcache *regcache, | |
3824 | int regnum, void *xstateregs, size_t len) | |
3825 | { | |
c131fcee L |
3826 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
3827 | } | |
3828 | ||
ecc37a5a AA |
3829 | /* Register set definitions. */ |
3830 | ||
3831 | const struct regset i386_gregset = | |
3832 | { | |
3833 | NULL, i386_supply_gregset, i386_collect_gregset | |
3834 | }; | |
3835 | ||
3836 | static const struct regset i386_fpregset = | |
3837 | { | |
3838 | NULL, i386_supply_fpregset, i386_collect_fpregset | |
3839 | }; | |
3840 | ||
3841 | static const struct regset i386_xstateregset = | |
3842 | { | |
3843 | NULL, i386_supply_xstateregset, i386_collect_xstateregset | |
3844 | }; | |
3845 | ||
8446b36a MK |
3846 | /* Return the appropriate register set for the core section identified |
3847 | by SECT_NAME and SECT_SIZE. */ | |
3848 | ||
3849 | const struct regset * | |
3850 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
3851 | const char *sect_name, size_t sect_size) | |
3852 | { | |
3853 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3854 | ||
3855 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
ecc37a5a | 3856 | return &i386_gregset; |
8446b36a | 3857 | |
66a72d25 MK |
3858 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
3859 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
3860 | && sect_size == I387_SIZEOF_FXSAVE)) | |
ecc37a5a | 3861 | return &i386_fpregset; |
8446b36a | 3862 | |
c131fcee | 3863 | if (strcmp (sect_name, ".reg-xstate") == 0) |
ecc37a5a | 3864 | return &i386_xstateregset; |
c131fcee | 3865 | |
8446b36a MK |
3866 | return NULL; |
3867 | } | |
473f17b0 | 3868 | \f |
fc338970 | 3869 | |
fc338970 | 3870 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3871 | |
3872 | CORE_ADDR | |
e17a4113 UW |
3873 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3874 | CORE_ADDR pc, char *name) | |
c906108c | 3875 | { |
e17a4113 UW |
3876 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3877 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3878 | ||
3879 | /* jmp *(dest) */ | |
3880 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3881 | { |
e17a4113 UW |
3882 | unsigned long indirect = |
3883 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3884 | struct minimal_symbol *indsym = |
7cbd4a93 | 3885 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
efd66ac6 | 3886 | const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3887 | |
c5aa993b | 3888 | if (symname) |
c906108c | 3889 | { |
c5aa993b JM |
3890 | if (strncmp (symname, "__imp_", 6) == 0 |
3891 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
3892 | return name ? 1 : |
3893 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3894 | } |
3895 | } | |
fc338970 | 3896 | return 0; /* Not a trampoline. */ |
c906108c | 3897 | } |
fc338970 MK |
3898 | \f |
3899 | ||
10458914 DJ |
3900 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3901 | routine. */ | |
8201327c | 3902 | |
4bd207ef | 3903 | int |
10458914 | 3904 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3905 | { |
10458914 | 3906 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3907 | const char *name; |
911bc6ee MK |
3908 | |
3909 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3910 | return (name && strcmp ("_sigtramp", name) == 0); |
3911 | } | |
3912 | \f | |
3913 | ||
fc338970 MK |
3914 | /* We have two flavours of disassembly. The machinery on this page |
3915 | deals with switching between those. */ | |
c906108c SS |
3916 | |
3917 | static int | |
a89aa300 | 3918 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3919 | { |
5e3397bb MK |
3920 | gdb_assert (disassembly_flavor == att_flavor |
3921 | || disassembly_flavor == intel_flavor); | |
3922 | ||
3923 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3924 | constified, cast to prevent a compiler warning. */ | |
3925 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3926 | |
3927 | return print_insn_i386 (pc, info); | |
7a292a7a | 3928 | } |
fc338970 | 3929 | \f |
3ce1502b | 3930 | |
8201327c MK |
3931 | /* There are a few i386 architecture variants that differ only |
3932 | slightly from the generic i386 target. For now, we don't give them | |
3933 | their own source file, but include them here. As a consequence, | |
3934 | they'll always be included. */ | |
3ce1502b | 3935 | |
8201327c | 3936 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3937 | |
10458914 DJ |
3938 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3939 | routine. */ | |
911bc6ee | 3940 | |
8201327c | 3941 | static int |
10458914 | 3942 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3943 | { |
10458914 | 3944 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3945 | const char *name; |
911bc6ee | 3946 | |
05b4bd79 | 3947 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 3948 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 3949 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
3950 | || strcmp ("sigvechandler", name) == 0)); |
3951 | } | |
d2a7c97a | 3952 | |
10458914 DJ |
3953 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3954 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3955 | |
3a1e71e3 | 3956 | static CORE_ADDR |
10458914 | 3957 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3958 | { |
e17a4113 UW |
3959 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3960 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3961 | gdb_byte buf[4]; |
acd5c798 | 3962 | CORE_ADDR sp; |
3ce1502b | 3963 | |
10458914 | 3964 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3965 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3966 | |
e17a4113 | 3967 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 3968 | } |
55aa24fb SDJ |
3969 | |
3970 | \f | |
3971 | ||
3972 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
3973 | gdbarch.h. */ | |
3974 | ||
3975 | int | |
3976 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
3977 | { | |
3978 | return (*s == '$' /* Literal number. */ | |
3979 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
3980 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
3981 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
3982 | } | |
3983 | ||
5acfdbae SDJ |
3984 | /* Helper function for i386_stap_parse_special_token. |
3985 | ||
3986 | This function parses operands of the form `-8+3+1(%rbp)', which | |
3987 | must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. | |
3988 | ||
3989 | Return 1 if the operand was parsed successfully, zero | |
3990 | otherwise. */ | |
3991 | ||
3992 | static int | |
3993 | i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, | |
3994 | struct stap_parse_info *p) | |
3995 | { | |
3996 | const char *s = p->arg; | |
3997 | ||
3998 | if (isdigit (*s) || *s == '-' || *s == '+') | |
3999 | { | |
4000 | int got_minus[3]; | |
4001 | int i; | |
4002 | long displacements[3]; | |
4003 | const char *start; | |
4004 | char *regname; | |
4005 | int len; | |
4006 | struct stoken str; | |
4007 | char *endp; | |
4008 | ||
4009 | got_minus[0] = 0; | |
4010 | if (*s == '+') | |
4011 | ++s; | |
4012 | else if (*s == '-') | |
4013 | { | |
4014 | ++s; | |
4015 | got_minus[0] = 1; | |
4016 | } | |
4017 | ||
d7b30f67 SDJ |
4018 | if (!isdigit ((unsigned char) *s)) |
4019 | return 0; | |
4020 | ||
5acfdbae SDJ |
4021 | displacements[0] = strtol (s, &endp, 10); |
4022 | s = endp; | |
4023 | ||
4024 | if (*s != '+' && *s != '-') | |
4025 | { | |
4026 | /* We are not dealing with a triplet. */ | |
4027 | return 0; | |
4028 | } | |
4029 | ||
4030 | got_minus[1] = 0; | |
4031 | if (*s == '+') | |
4032 | ++s; | |
4033 | else | |
4034 | { | |
4035 | ++s; | |
4036 | got_minus[1] = 1; | |
4037 | } | |
4038 | ||
d7b30f67 SDJ |
4039 | if (!isdigit ((unsigned char) *s)) |
4040 | return 0; | |
4041 | ||
5acfdbae SDJ |
4042 | displacements[1] = strtol (s, &endp, 10); |
4043 | s = endp; | |
4044 | ||
4045 | if (*s != '+' && *s != '-') | |
4046 | { | |
4047 | /* We are not dealing with a triplet. */ | |
4048 | return 0; | |
4049 | } | |
4050 | ||
4051 | got_minus[2] = 0; | |
4052 | if (*s == '+') | |
4053 | ++s; | |
4054 | else | |
4055 | { | |
4056 | ++s; | |
4057 | got_minus[2] = 1; | |
4058 | } | |
4059 | ||
d7b30f67 SDJ |
4060 | if (!isdigit ((unsigned char) *s)) |
4061 | return 0; | |
4062 | ||
5acfdbae SDJ |
4063 | displacements[2] = strtol (s, &endp, 10); |
4064 | s = endp; | |
4065 | ||
4066 | if (*s != '(' || s[1] != '%') | |
4067 | return 0; | |
4068 | ||
4069 | s += 2; | |
4070 | start = s; | |
4071 | ||
4072 | while (isalnum (*s)) | |
4073 | ++s; | |
4074 | ||
4075 | if (*s++ != ')') | |
4076 | return 0; | |
4077 | ||
d7b30f67 | 4078 | len = s - start - 1; |
5acfdbae SDJ |
4079 | regname = alloca (len + 1); |
4080 | ||
4081 | strncpy (regname, start, len); | |
4082 | regname[len] = '\0'; | |
4083 | ||
4084 | if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1) | |
4085 | error (_("Invalid register name `%s' on expression `%s'."), | |
4086 | regname, p->saved_arg); | |
4087 | ||
4088 | for (i = 0; i < 3; i++) | |
4089 | { | |
410a0ff2 SDJ |
4090 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4091 | write_exp_elt_type | |
4092 | (&p->pstate, builtin_type (gdbarch)->builtin_long); | |
4093 | write_exp_elt_longcst (&p->pstate, displacements[i]); | |
4094 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4095 | if (got_minus[i]) |
410a0ff2 | 4096 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4097 | } |
4098 | ||
410a0ff2 | 4099 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4100 | str.ptr = regname; |
4101 | str.length = len; | |
410a0ff2 SDJ |
4102 | write_exp_string (&p->pstate, str); |
4103 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae | 4104 | |
410a0ff2 SDJ |
4105 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4106 | write_exp_elt_type (&p->pstate, | |
4107 | builtin_type (gdbarch)->builtin_data_ptr); | |
4108 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4109 | |
410a0ff2 SDJ |
4110 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
4111 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
4112 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
5acfdbae | 4113 | |
410a0ff2 SDJ |
4114 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4115 | write_exp_elt_type (&p->pstate, | |
4116 | lookup_pointer_type (p->arg_type)); | |
4117 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4118 | |
410a0ff2 | 4119 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4120 | |
4121 | p->arg = s; | |
4122 | ||
4123 | return 1; | |
4124 | } | |
4125 | ||
4126 | return 0; | |
4127 | } | |
4128 | ||
4129 | /* Helper function for i386_stap_parse_special_token. | |
4130 | ||
4131 | This function parses operands of the form `register base + | |
4132 | (register index * size) + offset', as represented in | |
4133 | `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4134 | ||
4135 | Return 1 if the operand was parsed successfully, zero | |
4136 | otherwise. */ | |
4137 | ||
4138 | static int | |
4139 | i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, | |
4140 | struct stap_parse_info *p) | |
4141 | { | |
4142 | const char *s = p->arg; | |
4143 | ||
4144 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
4145 | { | |
4146 | int offset_minus = 0; | |
4147 | long offset = 0; | |
4148 | int size_minus = 0; | |
4149 | long size = 0; | |
4150 | const char *start; | |
4151 | char *base; | |
4152 | int len_base; | |
4153 | char *index; | |
4154 | int len_index; | |
4155 | struct stoken base_token, index_token; | |
4156 | ||
4157 | if (*s == '+') | |
4158 | ++s; | |
4159 | else if (*s == '-') | |
4160 | { | |
4161 | ++s; | |
4162 | offset_minus = 1; | |
4163 | } | |
4164 | ||
4165 | if (offset_minus && !isdigit (*s)) | |
4166 | return 0; | |
4167 | ||
4168 | if (isdigit (*s)) | |
4169 | { | |
4170 | char *endp; | |
4171 | ||
4172 | offset = strtol (s, &endp, 10); | |
4173 | s = endp; | |
4174 | } | |
4175 | ||
4176 | if (*s != '(' || s[1] != '%') | |
4177 | return 0; | |
4178 | ||
4179 | s += 2; | |
4180 | start = s; | |
4181 | ||
4182 | while (isalnum (*s)) | |
4183 | ++s; | |
4184 | ||
4185 | if (*s != ',' || s[1] != '%') | |
4186 | return 0; | |
4187 | ||
4188 | len_base = s - start; | |
4189 | base = alloca (len_base + 1); | |
4190 | strncpy (base, start, len_base); | |
4191 | base[len_base] = '\0'; | |
4192 | ||
4193 | if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1) | |
4194 | error (_("Invalid register name `%s' on expression `%s'."), | |
4195 | base, p->saved_arg); | |
4196 | ||
4197 | s += 2; | |
4198 | start = s; | |
4199 | ||
4200 | while (isalnum (*s)) | |
4201 | ++s; | |
4202 | ||
4203 | len_index = s - start; | |
4204 | index = alloca (len_index + 1); | |
4205 | strncpy (index, start, len_index); | |
4206 | index[len_index] = '\0'; | |
4207 | ||
4208 | if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1) | |
4209 | error (_("Invalid register name `%s' on expression `%s'."), | |
4210 | index, p->saved_arg); | |
4211 | ||
4212 | if (*s != ',' && *s != ')') | |
4213 | return 0; | |
4214 | ||
4215 | if (*s == ',') | |
4216 | { | |
4217 | char *endp; | |
4218 | ||
4219 | ++s; | |
4220 | if (*s == '+') | |
4221 | ++s; | |
4222 | else if (*s == '-') | |
4223 | { | |
4224 | ++s; | |
4225 | size_minus = 1; | |
4226 | } | |
4227 | ||
4228 | size = strtol (s, &endp, 10); | |
4229 | s = endp; | |
4230 | ||
4231 | if (*s != ')') | |
4232 | return 0; | |
4233 | } | |
4234 | ||
4235 | ++s; | |
4236 | ||
4237 | if (offset) | |
4238 | { | |
410a0ff2 SDJ |
4239 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4240 | write_exp_elt_type (&p->pstate, | |
4241 | builtin_type (gdbarch)->builtin_long); | |
4242 | write_exp_elt_longcst (&p->pstate, offset); | |
4243 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4244 | if (offset_minus) |
410a0ff2 | 4245 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4246 | } |
4247 | ||
410a0ff2 | 4248 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4249 | base_token.ptr = base; |
4250 | base_token.length = len_base; | |
410a0ff2 SDJ |
4251 | write_exp_string (&p->pstate, base_token); |
4252 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4253 | |
4254 | if (offset) | |
410a0ff2 | 4255 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4256 | |
410a0ff2 | 4257 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4258 | index_token.ptr = index; |
4259 | index_token.length = len_index; | |
410a0ff2 SDJ |
4260 | write_exp_string (&p->pstate, index_token); |
4261 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4262 | |
4263 | if (size) | |
4264 | { | |
410a0ff2 SDJ |
4265 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4266 | write_exp_elt_type (&p->pstate, | |
4267 | builtin_type (gdbarch)->builtin_long); | |
4268 | write_exp_elt_longcst (&p->pstate, size); | |
4269 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4270 | if (size_minus) |
410a0ff2 SDJ |
4271 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
4272 | write_exp_elt_opcode (&p->pstate, BINOP_MUL); | |
5acfdbae SDJ |
4273 | } |
4274 | ||
410a0ff2 | 4275 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4276 | |
410a0ff2 SDJ |
4277 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4278 | write_exp_elt_type (&p->pstate, | |
4279 | lookup_pointer_type (p->arg_type)); | |
4280 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4281 | |
410a0ff2 | 4282 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4283 | |
4284 | p->arg = s; | |
4285 | ||
4286 | return 1; | |
4287 | } | |
4288 | ||
4289 | return 0; | |
4290 | } | |
4291 | ||
55aa24fb SDJ |
4292 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in |
4293 | gdbarch.h. */ | |
4294 | ||
4295 | int | |
4296 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
4297 | struct stap_parse_info *p) | |
4298 | { | |
55aa24fb SDJ |
4299 | /* In order to parse special tokens, we use a state-machine that go |
4300 | through every known token and try to get a match. */ | |
4301 | enum | |
4302 | { | |
4303 | TRIPLET, | |
4304 | THREE_ARG_DISPLACEMENT, | |
4305 | DONE | |
4306 | } current_state; | |
4307 | ||
4308 | current_state = TRIPLET; | |
4309 | ||
4310 | /* The special tokens to be parsed here are: | |
4311 | ||
4312 | - `register base + (register index * size) + offset', as represented | |
4313 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4314 | ||
4315 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
4316 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
4317 | ||
4318 | while (current_state != DONE) | |
4319 | { | |
55aa24fb SDJ |
4320 | switch (current_state) |
4321 | { | |
4322 | case TRIPLET: | |
5acfdbae SDJ |
4323 | if (i386_stap_parse_special_token_triplet (gdbarch, p)) |
4324 | return 1; | |
4325 | break; | |
4326 | ||
55aa24fb | 4327 | case THREE_ARG_DISPLACEMENT: |
5acfdbae SDJ |
4328 | if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p)) |
4329 | return 1; | |
4330 | break; | |
55aa24fb SDJ |
4331 | } |
4332 | ||
4333 | /* Advancing to the next state. */ | |
4334 | ++current_state; | |
4335 | } | |
4336 | ||
4337 | return 0; | |
4338 | } | |
4339 | ||
8201327c | 4340 | \f |
3ce1502b | 4341 | |
8201327c | 4342 | /* Generic ELF. */ |
d2a7c97a | 4343 | |
8201327c MK |
4344 | void |
4345 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4346 | { | |
05c0465e SDJ |
4347 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
4348 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
4349 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
4350 | NULL }; | |
4351 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
4352 | NULL }; | |
4353 | ||
c4fc7f1b MK |
4354 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
4355 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
4356 | |
4357 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
4358 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
4359 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
4360 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
4361 | stap_register_indirection_prefixes); | |
4362 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
4363 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
4364 | set_gdbarch_stap_is_single_operand (gdbarch, |
4365 | i386_stap_is_single_operand); | |
4366 | set_gdbarch_stap_parse_special_token (gdbarch, | |
4367 | i386_stap_parse_special_token); | |
8201327c | 4368 | } |
3ce1502b | 4369 | |
8201327c | 4370 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4371 | |
8201327c MK |
4372 | void |
4373 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4374 | { | |
4375 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 4376 | |
8201327c MK |
4377 | /* System V Release 4 uses ELF. */ |
4378 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 4379 | |
dfe01d39 | 4380 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
4381 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
4382 | ||
911bc6ee | 4383 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 4384 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
4385 | tdep->sc_pc_offset = 36 + 14 * 4; |
4386 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 4387 | |
8201327c | 4388 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
4389 | } |
4390 | ||
8201327c | 4391 | /* DJGPP. */ |
3ce1502b | 4392 | |
3a1e71e3 | 4393 | static void |
8201327c | 4394 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 4395 | { |
8201327c | 4396 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 4397 | |
911bc6ee MK |
4398 | /* DJGPP doesn't have any special frames for signal handlers. */ |
4399 | tdep->sigtramp_p = NULL; | |
3ce1502b | 4400 | |
8201327c | 4401 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
4402 | |
4403 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
4404 | if (! tdesc_has_registers (info.target_desc)) |
4405 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
4406 | |
4407 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
4408 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
4409 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
4410 | set_gdbarch_sdb_reg_to_regnum. */ | |
4411 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
4412 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
4413 | |
4414 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 4415 | } |
8201327c | 4416 | \f |
2acceee2 | 4417 | |
38c968cf AC |
4418 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4419 | and "sse". */ | |
4420 | ||
4421 | static struct reggroup *i386_sse_reggroup; | |
4422 | static struct reggroup *i386_mmx_reggroup; | |
4423 | ||
4424 | static void | |
4425 | i386_init_reggroups (void) | |
4426 | { | |
4427 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4428 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4429 | } | |
4430 | ||
4431 | static void | |
4432 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4433 | { | |
4434 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4435 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
4436 | reggroup_add (gdbarch, general_reggroup); | |
4437 | reggroup_add (gdbarch, float_reggroup); | |
4438 | reggroup_add (gdbarch, all_reggroup); | |
4439 | reggroup_add (gdbarch, save_reggroup); | |
4440 | reggroup_add (gdbarch, restore_reggroup); | |
4441 | reggroup_add (gdbarch, vector_reggroup); | |
4442 | reggroup_add (gdbarch, system_reggroup); | |
4443 | } | |
4444 | ||
4445 | int | |
4446 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
4447 | struct reggroup *group) | |
4448 | { | |
c131fcee L |
4449 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4450 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
01f9f808 MS |
4451 | ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, |
4452 | bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p, | |
4453 | zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p, | |
4454 | avx512_p, avx_p, sse_p; | |
acd5c798 | 4455 | |
1ba53b71 L |
4456 | /* Don't include pseudo registers, except for MMX, in any register |
4457 | groups. */ | |
c131fcee | 4458 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4459 | return 0; |
4460 | ||
c131fcee | 4461 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4462 | return 0; |
4463 | ||
c131fcee | 4464 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4465 | return 0; |
4466 | ||
4467 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4468 | if (group == i386_mmx_reggroup) |
4469 | return mmx_regnum_p; | |
1ba53b71 | 4470 | |
c131fcee | 4471 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
01f9f808 | 4472 | xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); |
c131fcee | 4473 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
38c968cf | 4474 | if (group == i386_sse_reggroup) |
01f9f808 | 4475 | return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; |
c131fcee L |
4476 | |
4477 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4478 | ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); |
4479 | zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); | |
4480 | ||
df7e5265 GB |
4481 | avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) |
4482 | == X86_XSTATE_AVX512_MASK); | |
4483 | avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) | |
4484 | == X86_XSTATE_AVX_MASK) && !avx512_p; | |
4485 | sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) | |
4486 | == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; | |
01f9f808 | 4487 | |
38c968cf | 4488 | if (group == vector_reggroup) |
c131fcee | 4489 | return (mmx_regnum_p |
01f9f808 MS |
4490 | || (zmm_regnum_p && avx512_p) |
4491 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) | |
4492 | || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) | |
4493 | || mxcsr_regnum_p); | |
1ba53b71 L |
4494 | |
4495 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4496 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4497 | if (group == float_reggroup) |
4498 | return fp_regnum_p; | |
1ba53b71 | 4499 | |
c131fcee L |
4500 | /* For "info reg all", don't include upper YMM registers nor XMM |
4501 | registers when AVX is supported. */ | |
4502 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4503 | ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); |
4504 | zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); | |
c131fcee | 4505 | if (group == all_reggroup |
01f9f808 MS |
4506 | && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) |
4507 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) | |
4508 | || ymmh_regnum_p | |
4509 | || ymmh_avx512_regnum_p | |
4510 | || zmmh_regnum_p)) | |
c131fcee L |
4511 | return 0; |
4512 | ||
1dbcd68c WT |
4513 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4514 | if (group == all_reggroup | |
df7e5265 | 4515 | && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4516 | return bnd_regnum_p; |
4517 | ||
4518 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4519 | if (group == all_reggroup | |
df7e5265 | 4520 | && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4521 | return 0; |
4522 | ||
4523 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4524 | if (group == all_reggroup | |
df7e5265 | 4525 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4526 | return mpx_ctrl_regnum_p; |
4527 | ||
38c968cf | 4528 | if (group == general_reggroup) |
1ba53b71 L |
4529 | return (!fp_regnum_p |
4530 | && !mmx_regnum_p | |
c131fcee L |
4531 | && !mxcsr_regnum_p |
4532 | && !xmm_regnum_p | |
01f9f808 | 4533 | && !xmm_avx512_regnum_p |
c131fcee | 4534 | && !ymm_regnum_p |
1dbcd68c | 4535 | && !ymmh_regnum_p |
01f9f808 MS |
4536 | && !ymm_avx512_regnum_p |
4537 | && !ymmh_avx512_regnum_p | |
1dbcd68c WT |
4538 | && !bndr_regnum_p |
4539 | && !bnd_regnum_p | |
01f9f808 MS |
4540 | && !mpx_ctrl_regnum_p |
4541 | && !zmm_regnum_p | |
4542 | && !zmmh_regnum_p); | |
acd5c798 | 4543 | |
38c968cf AC |
4544 | return default_register_reggroup_p (gdbarch, regnum, group); |
4545 | } | |
38c968cf | 4546 | \f |
acd5c798 | 4547 | |
f837910f MK |
4548 | /* Get the ARGIth function argument for the current function. */ |
4549 | ||
42c466d7 | 4550 | static CORE_ADDR |
143985b7 AF |
4551 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
4552 | struct type *type) | |
4553 | { | |
e17a4113 UW |
4554 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4555 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4556 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4557 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4558 | } |
4559 | ||
514f746b AR |
4560 | static void |
4561 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
4562 | { | |
4563 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
4564 | ||
4565 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
4566 | adjust the PC in the regcache. */ | |
4567 | current_pc += 1; | |
4568 | regcache_write_pc (regcache, current_pc); | |
4569 | } | |
4570 | ||
4571 | ||
7ad10968 HZ |
4572 | #define PREFIX_REPZ 0x01 |
4573 | #define PREFIX_REPNZ 0x02 | |
4574 | #define PREFIX_LOCK 0x04 | |
4575 | #define PREFIX_DATA 0x08 | |
4576 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4577 | |
7ad10968 HZ |
4578 | /* operand size */ |
4579 | enum | |
4580 | { | |
4581 | OT_BYTE = 0, | |
4582 | OT_WORD, | |
4583 | OT_LONG, | |
cf648174 | 4584 | OT_QUAD, |
a3c4230a | 4585 | OT_DQUAD, |
7ad10968 | 4586 | }; |
473f17b0 | 4587 | |
7ad10968 HZ |
4588 | /* i386 arith/logic operations */ |
4589 | enum | |
4590 | { | |
4591 | OP_ADDL, | |
4592 | OP_ORL, | |
4593 | OP_ADCL, | |
4594 | OP_SBBL, | |
4595 | OP_ANDL, | |
4596 | OP_SUBL, | |
4597 | OP_XORL, | |
4598 | OP_CMPL, | |
4599 | }; | |
5716833c | 4600 | |
7ad10968 HZ |
4601 | struct i386_record_s |
4602 | { | |
cf648174 | 4603 | struct gdbarch *gdbarch; |
7ad10968 | 4604 | struct regcache *regcache; |
df61f520 | 4605 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4606 | CORE_ADDR addr; |
4607 | int aflag; | |
4608 | int dflag; | |
4609 | int override; | |
4610 | uint8_t modrm; | |
4611 | uint8_t mod, reg, rm; | |
4612 | int ot; | |
cf648174 HZ |
4613 | uint8_t rex_x; |
4614 | uint8_t rex_b; | |
4615 | int rip_offset; | |
4616 | int popl_esp_hack; | |
4617 | const int *regmap; | |
7ad10968 | 4618 | }; |
5716833c | 4619 | |
99c1624c PA |
4620 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4621 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4622 | |
7ad10968 HZ |
4623 | static int |
4624 | i386_record_modrm (struct i386_record_s *irp) | |
4625 | { | |
cf648174 | 4626 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4627 | |
4ffa4fc7 PA |
4628 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4629 | return -1; | |
4630 | ||
7ad10968 HZ |
4631 | irp->addr++; |
4632 | irp->mod = (irp->modrm >> 6) & 3; | |
4633 | irp->reg = (irp->modrm >> 3) & 7; | |
4634 | irp->rm = irp->modrm & 7; | |
5716833c | 4635 | |
7ad10968 HZ |
4636 | return 0; |
4637 | } | |
d2a7c97a | 4638 | |
99c1624c PA |
4639 | /* Extract the memory address that the current instruction writes to, |
4640 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4641 | |
7ad10968 | 4642 | static int |
cf648174 | 4643 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4644 | { |
cf648174 | 4645 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4646 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4647 | gdb_byte buf[4]; | |
4648 | ULONGEST offset64; | |
21d0e8a4 | 4649 | |
7ad10968 | 4650 | *addr = 0; |
1e87984a | 4651 | if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4652 | { |
1e87984a | 4653 | /* 32/64 bits */ |
7ad10968 HZ |
4654 | int havesib = 0; |
4655 | uint8_t scale = 0; | |
648d0c8b | 4656 | uint8_t byte; |
7ad10968 HZ |
4657 | uint8_t index = 0; |
4658 | uint8_t base = irp->rm; | |
896fb97d | 4659 | |
7ad10968 HZ |
4660 | if (base == 4) |
4661 | { | |
4662 | havesib = 1; | |
4ffa4fc7 PA |
4663 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4664 | return -1; | |
7ad10968 | 4665 | irp->addr++; |
648d0c8b MS |
4666 | scale = (byte >> 6) & 3; |
4667 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4668 | base = (byte & 7); | |
7ad10968 | 4669 | } |
cf648174 | 4670 | base |= irp->rex_b; |
21d0e8a4 | 4671 | |
7ad10968 HZ |
4672 | switch (irp->mod) |
4673 | { | |
4674 | case 0: | |
4675 | if ((base & 7) == 5) | |
4676 | { | |
4677 | base = 0xff; | |
4ffa4fc7 PA |
4678 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4679 | return -1; | |
7ad10968 | 4680 | irp->addr += 4; |
60a1502a | 4681 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4682 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4683 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4684 | } |
7ad10968 HZ |
4685 | break; |
4686 | case 1: | |
4ffa4fc7 PA |
4687 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4688 | return -1; | |
7ad10968 | 4689 | irp->addr++; |
60a1502a | 4690 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4691 | break; |
4692 | case 2: | |
4ffa4fc7 PA |
4693 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4694 | return -1; | |
60a1502a | 4695 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4696 | irp->addr += 4; |
4697 | break; | |
4698 | } | |
356a6b3e | 4699 | |
60a1502a | 4700 | offset64 = 0; |
7ad10968 | 4701 | if (base != 0xff) |
cf648174 HZ |
4702 | { |
4703 | if (base == 4 && irp->popl_esp_hack) | |
4704 | *addr += irp->popl_esp_hack; | |
4705 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4706 | &offset64); |
7ad10968 | 4707 | } |
cf648174 HZ |
4708 | if (irp->aflag == 2) |
4709 | { | |
60a1502a | 4710 | *addr += offset64; |
cf648174 HZ |
4711 | } |
4712 | else | |
60a1502a | 4713 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4714 | |
7ad10968 HZ |
4715 | if (havesib && (index != 4 || scale != 0)) |
4716 | { | |
cf648174 | 4717 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4718 | &offset64); |
cf648174 | 4719 | if (irp->aflag == 2) |
60a1502a | 4720 | *addr += offset64 << scale; |
cf648174 | 4721 | else |
60a1502a | 4722 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 | 4723 | } |
e85596e0 L |
4724 | |
4725 | if (!irp->aflag) | |
4726 | { | |
4727 | /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend | |
4728 | address from 32-bit to 64-bit. */ | |
4729 | *addr = (uint32_t) *addr; | |
4730 | } | |
7ad10968 HZ |
4731 | } |
4732 | else | |
4733 | { | |
4734 | /* 16 bits */ | |
4735 | switch (irp->mod) | |
4736 | { | |
4737 | case 0: | |
4738 | if (irp->rm == 6) | |
4739 | { | |
4ffa4fc7 PA |
4740 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4741 | return -1; | |
7ad10968 | 4742 | irp->addr += 2; |
60a1502a | 4743 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4744 | irp->rm = 0; |
4745 | goto no_rm; | |
4746 | } | |
7ad10968 HZ |
4747 | break; |
4748 | case 1: | |
4ffa4fc7 PA |
4749 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4750 | return -1; | |
7ad10968 | 4751 | irp->addr++; |
60a1502a | 4752 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4753 | break; |
4754 | case 2: | |
4ffa4fc7 PA |
4755 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4756 | return -1; | |
7ad10968 | 4757 | irp->addr += 2; |
60a1502a | 4758 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4759 | break; |
4760 | } | |
c4fc7f1b | 4761 | |
7ad10968 HZ |
4762 | switch (irp->rm) |
4763 | { | |
4764 | case 0: | |
cf648174 HZ |
4765 | regcache_raw_read_unsigned (irp->regcache, |
4766 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4767 | &offset64); |
4768 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4769 | regcache_raw_read_unsigned (irp->regcache, |
4770 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4771 | &offset64); |
4772 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4773 | break; |
4774 | case 1: | |
cf648174 HZ |
4775 | regcache_raw_read_unsigned (irp->regcache, |
4776 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4777 | &offset64); |
4778 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4779 | regcache_raw_read_unsigned (irp->regcache, |
4780 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4781 | &offset64); |
4782 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4783 | break; |
4784 | case 2: | |
cf648174 HZ |
4785 | regcache_raw_read_unsigned (irp->regcache, |
4786 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4787 | &offset64); |
4788 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4789 | regcache_raw_read_unsigned (irp->regcache, |
4790 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4791 | &offset64); |
4792 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4793 | break; |
4794 | case 3: | |
cf648174 HZ |
4795 | regcache_raw_read_unsigned (irp->regcache, |
4796 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4797 | &offset64); |
4798 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4799 | regcache_raw_read_unsigned (irp->regcache, |
4800 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4801 | &offset64); |
4802 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4803 | break; |
4804 | case 4: | |
cf648174 HZ |
4805 | regcache_raw_read_unsigned (irp->regcache, |
4806 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4807 | &offset64); |
4808 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4809 | break; |
4810 | case 5: | |
cf648174 HZ |
4811 | regcache_raw_read_unsigned (irp->regcache, |
4812 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4813 | &offset64); |
4814 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4815 | break; |
4816 | case 6: | |
cf648174 HZ |
4817 | regcache_raw_read_unsigned (irp->regcache, |
4818 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4819 | &offset64); |
4820 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4821 | break; |
4822 | case 7: | |
cf648174 HZ |
4823 | regcache_raw_read_unsigned (irp->regcache, |
4824 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4825 | &offset64); |
4826 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4827 | break; |
4828 | } | |
4829 | *addr &= 0xffff; | |
4830 | } | |
c4fc7f1b | 4831 | |
01fe1b41 | 4832 | no_rm: |
7ad10968 HZ |
4833 | return 0; |
4834 | } | |
c4fc7f1b | 4835 | |
99c1624c PA |
4836 | /* Record the address and contents of the memory that will be changed |
4837 | by the current instruction. Return -1 if something goes wrong, 0 | |
4838 | otherwise. */ | |
356a6b3e | 4839 | |
7ad10968 HZ |
4840 | static int |
4841 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4842 | { | |
cf648174 HZ |
4843 | struct gdbarch *gdbarch = irp->gdbarch; |
4844 | uint64_t addr; | |
356a6b3e | 4845 | |
d7877f7e | 4846 | if (irp->override >= 0) |
7ad10968 | 4847 | { |
25ea693b | 4848 | if (record_full_memory_query) |
bb08c432 HZ |
4849 | { |
4850 | int q; | |
4851 | ||
4852 | target_terminal_ours (); | |
4853 | q = yquery (_("\ | |
4854 | Process record ignores the memory change of instruction at address %s\n\ | |
4855 | because it can't get the value of the segment register.\n\ | |
4856 | Do you want to stop the program?"), | |
4857 | paddress (gdbarch, irp->orig_addr)); | |
4858 | target_terminal_inferior (); | |
4859 | if (q) | |
4860 | return -1; | |
4861 | } | |
4862 | ||
7ad10968 HZ |
4863 | return 0; |
4864 | } | |
61113f8b | 4865 | |
7ad10968 HZ |
4866 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4867 | return -1; | |
96297dab | 4868 | |
25ea693b | 4869 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4870 | return -1; |
a62cc96e | 4871 | |
7ad10968 HZ |
4872 | return 0; |
4873 | } | |
b6197528 | 4874 | |
99c1624c PA |
4875 | /* Record the effects of a push operation. Return -1 if something |
4876 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4877 | |
4878 | static int | |
4879 | i386_record_push (struct i386_record_s *irp, int size) | |
4880 | { | |
648d0c8b | 4881 | ULONGEST addr; |
cf648174 | 4882 | |
25ea693b MM |
4883 | if (record_full_arch_list_add_reg (irp->regcache, |
4884 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4885 | return -1; |
4886 | regcache_raw_read_unsigned (irp->regcache, | |
4887 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4888 | &addr); |
25ea693b | 4889 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4890 | return -1; |
4891 | ||
4892 | return 0; | |
4893 | } | |
4894 | ||
0289bdd7 MS |
4895 | |
4896 | /* Defines contents to record. */ | |
4897 | #define I386_SAVE_FPU_REGS 0xfffd | |
4898 | #define I386_SAVE_FPU_ENV 0xfffe | |
4899 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4900 | ||
99c1624c PA |
4901 | /* Record the values of the floating point registers which will be |
4902 | changed by the current instruction. Returns -1 if something is | |
4903 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4904 | |
4905 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4906 | struct i386_record_s *ir, | |
4907 | uint32_t iregnum) | |
4908 | { | |
4909 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4910 | int i; | |
4911 | ||
4912 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4913 | happen. Currently we store st0-st7 registers, but we need not store all | |
4914 | registers all the time, in future we use ftag register and record only | |
4915 | those who are not marked as an empty. */ | |
4916 | ||
4917 | if (I386_SAVE_FPU_REGS == iregnum) | |
4918 | { | |
4919 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
4920 | { | |
25ea693b | 4921 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4922 | return -1; |
4923 | } | |
4924 | } | |
4925 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4926 | { | |
4927 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4928 | { | |
25ea693b | 4929 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4930 | return -1; |
4931 | } | |
4932 | } | |
4933 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4934 | { | |
4935 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4936 | { | |
25ea693b | 4937 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4938 | return -1; |
4939 | } | |
4940 | } | |
4941 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
4942 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
4943 | { | |
25ea693b | 4944 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
0289bdd7 MS |
4945 | return -1; |
4946 | } | |
4947 | else | |
4948 | { | |
4949 | /* Parameter error. */ | |
4950 | return -1; | |
4951 | } | |
4952 | if(I386_SAVE_FPU_ENV != iregnum) | |
4953 | { | |
4954 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4955 | { | |
25ea693b | 4956 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4957 | return -1; |
4958 | } | |
4959 | } | |
4960 | return 0; | |
4961 | } | |
4962 | ||
99c1624c PA |
4963 | /* Parse the current instruction, and record the values of the |
4964 | registers and memory that will be changed by the current | |
4965 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 4966 | |
25ea693b MM |
4967 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
4968 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 4969 | |
a6b808b4 | 4970 | int |
7ad10968 | 4971 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 4972 | CORE_ADDR input_addr) |
7ad10968 | 4973 | { |
60a1502a | 4974 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 4975 | int prefixes = 0; |
580879fc | 4976 | int regnum = 0; |
425b824a | 4977 | uint32_t opcode; |
f4644a3f | 4978 | uint8_t opcode8; |
648d0c8b | 4979 | ULONGEST addr; |
60a1502a | 4980 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 4981 | struct i386_record_s ir; |
0289bdd7 | 4982 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
4983 | uint8_t rex_w = -1; |
4984 | uint8_t rex_r = 0; | |
7ad10968 | 4985 | |
8408d274 | 4986 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 4987 | ir.regcache = regcache; |
648d0c8b MS |
4988 | ir.addr = input_addr; |
4989 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
4990 | ir.aflag = 1; |
4991 | ir.dflag = 1; | |
cf648174 HZ |
4992 | ir.override = -1; |
4993 | ir.popl_esp_hack = 0; | |
a3c4230a | 4994 | ir.regmap = tdep->record_regmap; |
cf648174 | 4995 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
4996 | |
4997 | if (record_debug > 1) | |
4998 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
4999 | "addr = %s\n", |
5000 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5001 | |
5002 | /* prefixes */ | |
5003 | while (1) | |
5004 | { | |
4ffa4fc7 PA |
5005 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5006 | return -1; | |
7ad10968 | 5007 | ir.addr++; |
425b824a | 5008 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 5009 | { |
01fe1b41 | 5010 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
5011 | prefixes |= PREFIX_REPZ; |
5012 | break; | |
01fe1b41 | 5013 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
5014 | prefixes |= PREFIX_REPNZ; |
5015 | break; | |
01fe1b41 | 5016 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
5017 | prefixes |= PREFIX_LOCK; |
5018 | break; | |
01fe1b41 | 5019 | case CS_PREFIX_OPCODE: |
cf648174 | 5020 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 5021 | break; |
01fe1b41 | 5022 | case SS_PREFIX_OPCODE: |
cf648174 | 5023 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 5024 | break; |
01fe1b41 | 5025 | case DS_PREFIX_OPCODE: |
cf648174 | 5026 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 5027 | break; |
01fe1b41 | 5028 | case ES_PREFIX_OPCODE: |
cf648174 | 5029 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 5030 | break; |
01fe1b41 | 5031 | case FS_PREFIX_OPCODE: |
cf648174 | 5032 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 5033 | break; |
01fe1b41 | 5034 | case GS_PREFIX_OPCODE: |
cf648174 | 5035 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 5036 | break; |
01fe1b41 | 5037 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
5038 | prefixes |= PREFIX_DATA; |
5039 | break; | |
01fe1b41 | 5040 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
5041 | prefixes |= PREFIX_ADDR; |
5042 | break; | |
d691bec7 MS |
5043 | case 0x40: /* i386 inc %eax */ |
5044 | case 0x41: /* i386 inc %ecx */ | |
5045 | case 0x42: /* i386 inc %edx */ | |
5046 | case 0x43: /* i386 inc %ebx */ | |
5047 | case 0x44: /* i386 inc %esp */ | |
5048 | case 0x45: /* i386 inc %ebp */ | |
5049 | case 0x46: /* i386 inc %esi */ | |
5050 | case 0x47: /* i386 inc %edi */ | |
5051 | case 0x48: /* i386 dec %eax */ | |
5052 | case 0x49: /* i386 dec %ecx */ | |
5053 | case 0x4a: /* i386 dec %edx */ | |
5054 | case 0x4b: /* i386 dec %ebx */ | |
5055 | case 0x4c: /* i386 dec %esp */ | |
5056 | case 0x4d: /* i386 dec %ebp */ | |
5057 | case 0x4e: /* i386 dec %esi */ | |
5058 | case 0x4f: /* i386 dec %edi */ | |
5059 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
5060 | { |
5061 | /* REX */ | |
425b824a MS |
5062 | rex_w = (opcode8 >> 3) & 1; |
5063 | rex_r = (opcode8 & 0x4) << 1; | |
5064 | ir.rex_x = (opcode8 & 0x2) << 2; | |
5065 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 5066 | } |
d691bec7 MS |
5067 | else /* 32 bit target */ |
5068 | goto out_prefixes; | |
cf648174 | 5069 | break; |
7ad10968 HZ |
5070 | default: |
5071 | goto out_prefixes; | |
5072 | break; | |
5073 | } | |
5074 | } | |
01fe1b41 | 5075 | out_prefixes: |
cf648174 HZ |
5076 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
5077 | { | |
5078 | ir.dflag = 2; | |
5079 | } | |
5080 | else | |
5081 | { | |
5082 | if (prefixes & PREFIX_DATA) | |
5083 | ir.dflag ^= 1; | |
5084 | } | |
7ad10968 HZ |
5085 | if (prefixes & PREFIX_ADDR) |
5086 | ir.aflag ^= 1; | |
cf648174 HZ |
5087 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5088 | ir.aflag = 2; | |
7ad10968 | 5089 | |
1777feb0 | 5090 | /* Now check op code. */ |
425b824a | 5091 | opcode = (uint32_t) opcode8; |
01fe1b41 | 5092 | reswitch: |
7ad10968 HZ |
5093 | switch (opcode) |
5094 | { | |
5095 | case 0x0f: | |
4ffa4fc7 PA |
5096 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5097 | return -1; | |
7ad10968 | 5098 | ir.addr++; |
a3c4230a | 5099 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
5100 | goto reswitch; |
5101 | break; | |
93924b6b | 5102 | |
a38bba38 | 5103 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
5104 | case 0x01: |
5105 | case 0x02: | |
5106 | case 0x03: | |
5107 | case 0x04: | |
5108 | case 0x05: | |
5109 | case 0x08: | |
5110 | case 0x09: | |
5111 | case 0x0a: | |
5112 | case 0x0b: | |
5113 | case 0x0c: | |
5114 | case 0x0d: | |
5115 | case 0x10: | |
5116 | case 0x11: | |
5117 | case 0x12: | |
5118 | case 0x13: | |
5119 | case 0x14: | |
5120 | case 0x15: | |
5121 | case 0x18: | |
5122 | case 0x19: | |
5123 | case 0x1a: | |
5124 | case 0x1b: | |
5125 | case 0x1c: | |
5126 | case 0x1d: | |
5127 | case 0x20: | |
5128 | case 0x21: | |
5129 | case 0x22: | |
5130 | case 0x23: | |
5131 | case 0x24: | |
5132 | case 0x25: | |
5133 | case 0x28: | |
5134 | case 0x29: | |
5135 | case 0x2a: | |
5136 | case 0x2b: | |
5137 | case 0x2c: | |
5138 | case 0x2d: | |
5139 | case 0x30: | |
5140 | case 0x31: | |
5141 | case 0x32: | |
5142 | case 0x33: | |
5143 | case 0x34: | |
5144 | case 0x35: | |
5145 | case 0x38: | |
5146 | case 0x39: | |
5147 | case 0x3a: | |
5148 | case 0x3b: | |
5149 | case 0x3c: | |
5150 | case 0x3d: | |
5151 | if (((opcode >> 3) & 7) != OP_CMPL) | |
5152 | { | |
5153 | if ((opcode & 1) == 0) | |
5154 | ir.ot = OT_BYTE; | |
5155 | else | |
5156 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 5157 | |
7ad10968 HZ |
5158 | switch ((opcode >> 1) & 3) |
5159 | { | |
a38bba38 | 5160 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
5161 | if (i386_record_modrm (&ir)) |
5162 | return -1; | |
5163 | if (ir.mod != 3) | |
5164 | { | |
5165 | if (i386_record_lea_modrm (&ir)) | |
5166 | return -1; | |
5167 | } | |
5168 | else | |
5169 | { | |
cf648174 HZ |
5170 | ir.rm |= ir.rex_b; |
5171 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5172 | ir.rm &= 0x3; |
25ea693b | 5173 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5174 | } |
5175 | break; | |
a38bba38 | 5176 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
5177 | if (i386_record_modrm (&ir)) |
5178 | return -1; | |
cf648174 HZ |
5179 | ir.reg |= rex_r; |
5180 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5181 | ir.reg &= 0x3; |
25ea693b | 5182 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5183 | break; |
a38bba38 | 5184 | case 2: /* OP A, Iv */ |
25ea693b | 5185 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5186 | break; |
5187 | } | |
5188 | } | |
25ea693b | 5189 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5190 | break; |
42fdc8df | 5191 | |
a38bba38 | 5192 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
5193 | case 0x81: |
5194 | case 0x82: | |
5195 | case 0x83: | |
5196 | if (i386_record_modrm (&ir)) | |
5197 | return -1; | |
8201327c | 5198 | |
7ad10968 HZ |
5199 | if (ir.reg != OP_CMPL) |
5200 | { | |
5201 | if ((opcode & 1) == 0) | |
5202 | ir.ot = OT_BYTE; | |
5203 | else | |
5204 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 5205 | |
7ad10968 HZ |
5206 | if (ir.mod != 3) |
5207 | { | |
cf648174 HZ |
5208 | if (opcode == 0x83) |
5209 | ir.rip_offset = 1; | |
5210 | else | |
5211 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5212 | if (i386_record_lea_modrm (&ir)) |
5213 | return -1; | |
5214 | } | |
5215 | else | |
25ea693b | 5216 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 5217 | } |
25ea693b | 5218 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5219 | break; |
5e3397bb | 5220 | |
a38bba38 | 5221 | case 0x40: /* inc */ |
7ad10968 HZ |
5222 | case 0x41: |
5223 | case 0x42: | |
5224 | case 0x43: | |
5225 | case 0x44: | |
5226 | case 0x45: | |
5227 | case 0x46: | |
5228 | case 0x47: | |
a38bba38 MS |
5229 | |
5230 | case 0x48: /* dec */ | |
7ad10968 HZ |
5231 | case 0x49: |
5232 | case 0x4a: | |
5233 | case 0x4b: | |
5234 | case 0x4c: | |
5235 | case 0x4d: | |
5236 | case 0x4e: | |
5237 | case 0x4f: | |
a38bba38 | 5238 | |
25ea693b MM |
5239 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
5240 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 5241 | break; |
acd5c798 | 5242 | |
a38bba38 | 5243 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
5244 | case 0xf7: |
5245 | if ((opcode & 1) == 0) | |
5246 | ir.ot = OT_BYTE; | |
5247 | else | |
5248 | ir.ot = ir.dflag + OT_WORD; | |
5249 | if (i386_record_modrm (&ir)) | |
5250 | return -1; | |
acd5c798 | 5251 | |
cf648174 HZ |
5252 | if (ir.mod != 3 && ir.reg == 0) |
5253 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5254 | ||
7ad10968 HZ |
5255 | switch (ir.reg) |
5256 | { | |
a38bba38 | 5257 | case 0: /* test */ |
25ea693b | 5258 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5259 | break; |
a38bba38 MS |
5260 | case 2: /* not */ |
5261 | case 3: /* neg */ | |
7ad10968 HZ |
5262 | if (ir.mod != 3) |
5263 | { | |
5264 | if (i386_record_lea_modrm (&ir)) | |
5265 | return -1; | |
5266 | } | |
5267 | else | |
5268 | { | |
cf648174 HZ |
5269 | ir.rm |= ir.rex_b; |
5270 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5271 | ir.rm &= 0x3; |
25ea693b | 5272 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5273 | } |
a38bba38 | 5274 | if (ir.reg == 3) /* neg */ |
25ea693b | 5275 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5276 | break; |
a38bba38 MS |
5277 | case 4: /* mul */ |
5278 | case 5: /* imul */ | |
5279 | case 6: /* div */ | |
5280 | case 7: /* idiv */ | |
25ea693b | 5281 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 5282 | if (ir.ot != OT_BYTE) |
25ea693b MM |
5283 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
5284 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5285 | break; |
5286 | default: | |
5287 | ir.addr -= 2; | |
5288 | opcode = opcode << 8 | ir.modrm; | |
5289 | goto no_support; | |
5290 | break; | |
5291 | } | |
5292 | break; | |
5293 | ||
a38bba38 MS |
5294 | case 0xfe: /* GRP4 */ |
5295 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
5296 | if (i386_record_modrm (&ir)) |
5297 | return -1; | |
5298 | if (ir.reg >= 2 && opcode == 0xfe) | |
5299 | { | |
5300 | ir.addr -= 2; | |
5301 | opcode = opcode << 8 | ir.modrm; | |
5302 | goto no_support; | |
5303 | } | |
7ad10968 HZ |
5304 | switch (ir.reg) |
5305 | { | |
a38bba38 MS |
5306 | case 0: /* inc */ |
5307 | case 1: /* dec */ | |
cf648174 HZ |
5308 | if ((opcode & 1) == 0) |
5309 | ir.ot = OT_BYTE; | |
5310 | else | |
5311 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5312 | if (ir.mod != 3) |
5313 | { | |
5314 | if (i386_record_lea_modrm (&ir)) | |
5315 | return -1; | |
5316 | } | |
5317 | else | |
5318 | { | |
cf648174 HZ |
5319 | ir.rm |= ir.rex_b; |
5320 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5321 | ir.rm &= 0x3; |
25ea693b | 5322 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5323 | } |
25ea693b | 5324 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5325 | break; |
a38bba38 | 5326 | case 2: /* call */ |
cf648174 HZ |
5327 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5328 | ir.dflag = 2; | |
5329 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5330 | return -1; |
25ea693b | 5331 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5332 | break; |
a38bba38 | 5333 | case 3: /* lcall */ |
25ea693b | 5334 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 5335 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5336 | return -1; |
25ea693b | 5337 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5338 | break; |
a38bba38 MS |
5339 | case 4: /* jmp */ |
5340 | case 5: /* ljmp */ | |
25ea693b | 5341 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 5342 | break; |
a38bba38 | 5343 | case 6: /* push */ |
cf648174 HZ |
5344 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5345 | ir.dflag = 2; | |
5346 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5347 | return -1; | |
7ad10968 HZ |
5348 | break; |
5349 | default: | |
5350 | ir.addr -= 2; | |
5351 | opcode = opcode << 8 | ir.modrm; | |
5352 | goto no_support; | |
5353 | break; | |
5354 | } | |
5355 | break; | |
5356 | ||
a38bba38 | 5357 | case 0x84: /* test */ |
7ad10968 HZ |
5358 | case 0x85: |
5359 | case 0xa8: | |
5360 | case 0xa9: | |
25ea693b | 5361 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5362 | break; |
5363 | ||
a38bba38 | 5364 | case 0x98: /* CWDE/CBW */ |
25ea693b | 5365 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5366 | break; |
5367 | ||
a38bba38 | 5368 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
5369 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5370 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5371 | break; |
5372 | ||
a38bba38 | 5373 | case 0x0faf: /* imul */ |
7ad10968 HZ |
5374 | case 0x69: |
5375 | case 0x6b: | |
5376 | ir.ot = ir.dflag + OT_WORD; | |
5377 | if (i386_record_modrm (&ir)) | |
5378 | return -1; | |
cf648174 HZ |
5379 | if (opcode == 0x69) |
5380 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5381 | else if (opcode == 0x6b) | |
5382 | ir.rip_offset = 1; | |
5383 | ir.reg |= rex_r; | |
5384 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5385 | ir.reg &= 0x3; |
25ea693b MM |
5386 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
5387 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5388 | break; |
5389 | ||
a38bba38 | 5390 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
5391 | case 0x0fc1: |
5392 | if ((opcode & 1) == 0) | |
5393 | ir.ot = OT_BYTE; | |
5394 | else | |
5395 | ir.ot = ir.dflag + OT_WORD; | |
5396 | if (i386_record_modrm (&ir)) | |
5397 | return -1; | |
cf648174 | 5398 | ir.reg |= rex_r; |
7ad10968 HZ |
5399 | if (ir.mod == 3) |
5400 | { | |
cf648174 | 5401 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5402 | ir.reg &= 0x3; |
25ea693b | 5403 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5404 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5405 | ir.rm &= 0x3; |
25ea693b | 5406 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5407 | } |
5408 | else | |
5409 | { | |
5410 | if (i386_record_lea_modrm (&ir)) | |
5411 | return -1; | |
cf648174 | 5412 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5413 | ir.reg &= 0x3; |
25ea693b | 5414 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5415 | } |
25ea693b | 5416 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5417 | break; |
5418 | ||
a38bba38 | 5419 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
5420 | case 0x0fb1: |
5421 | if ((opcode & 1) == 0) | |
5422 | ir.ot = OT_BYTE; | |
5423 | else | |
5424 | ir.ot = ir.dflag + OT_WORD; | |
5425 | if (i386_record_modrm (&ir)) | |
5426 | return -1; | |
5427 | if (ir.mod == 3) | |
5428 | { | |
cf648174 | 5429 | ir.reg |= rex_r; |
25ea693b | 5430 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 5431 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5432 | ir.reg &= 0x3; |
25ea693b | 5433 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5434 | } |
5435 | else | |
5436 | { | |
25ea693b | 5437 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5438 | if (i386_record_lea_modrm (&ir)) |
5439 | return -1; | |
5440 | } | |
25ea693b | 5441 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5442 | break; |
5443 | ||
a38bba38 | 5444 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
5445 | if (i386_record_modrm (&ir)) |
5446 | return -1; | |
5447 | if (ir.mod == 3) | |
5448 | { | |
5449 | ir.addr -= 2; | |
5450 | opcode = opcode << 8 | ir.modrm; | |
5451 | goto no_support; | |
5452 | } | |
25ea693b MM |
5453 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5454 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5455 | if (i386_record_lea_modrm (&ir)) |
5456 | return -1; | |
25ea693b | 5457 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5458 | break; |
5459 | ||
a38bba38 | 5460 | case 0x50: /* push */ |
7ad10968 HZ |
5461 | case 0x51: |
5462 | case 0x52: | |
5463 | case 0x53: | |
5464 | case 0x54: | |
5465 | case 0x55: | |
5466 | case 0x56: | |
5467 | case 0x57: | |
5468 | case 0x68: | |
5469 | case 0x6a: | |
cf648174 HZ |
5470 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5471 | ir.dflag = 2; | |
5472 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5473 | return -1; | |
5474 | break; | |
5475 | ||
a38bba38 MS |
5476 | case 0x06: /* push es */ |
5477 | case 0x0e: /* push cs */ | |
5478 | case 0x16: /* push ss */ | |
5479 | case 0x1e: /* push ds */ | |
cf648174 HZ |
5480 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5481 | { | |
5482 | ir.addr -= 1; | |
5483 | goto no_support; | |
5484 | } | |
5485 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5486 | return -1; | |
5487 | break; | |
5488 | ||
a38bba38 MS |
5489 | case 0x0fa0: /* push fs */ |
5490 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
5491 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5492 | { | |
5493 | ir.addr -= 2; | |
5494 | goto no_support; | |
5495 | } | |
5496 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5497 | return -1; |
cf648174 HZ |
5498 | break; |
5499 | ||
a38bba38 | 5500 | case 0x60: /* pusha */ |
cf648174 HZ |
5501 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5502 | { | |
5503 | ir.addr -= 1; | |
5504 | goto no_support; | |
5505 | } | |
5506 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5507 | return -1; |
5508 | break; | |
5509 | ||
a38bba38 | 5510 | case 0x58: /* pop */ |
7ad10968 HZ |
5511 | case 0x59: |
5512 | case 0x5a: | |
5513 | case 0x5b: | |
5514 | case 0x5c: | |
5515 | case 0x5d: | |
5516 | case 0x5e: | |
5517 | case 0x5f: | |
25ea693b MM |
5518 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5519 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5520 | break; |
5521 | ||
a38bba38 | 5522 | case 0x61: /* popa */ |
cf648174 HZ |
5523 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5524 | { | |
5525 | ir.addr -= 1; | |
5526 | goto no_support; | |
7ad10968 | 5527 | } |
425b824a MS |
5528 | for (regnum = X86_RECORD_REAX_REGNUM; |
5529 | regnum <= X86_RECORD_REDI_REGNUM; | |
5530 | regnum++) | |
25ea693b | 5531 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5532 | break; |
5533 | ||
a38bba38 | 5534 | case 0x8f: /* pop */ |
cf648174 HZ |
5535 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5536 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5537 | else | |
5538 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5539 | if (i386_record_modrm (&ir)) |
5540 | return -1; | |
5541 | if (ir.mod == 3) | |
25ea693b | 5542 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5543 | else |
5544 | { | |
cf648174 | 5545 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5546 | if (i386_record_lea_modrm (&ir)) |
5547 | return -1; | |
5548 | } | |
25ea693b | 5549 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5550 | break; |
5551 | ||
a38bba38 | 5552 | case 0xc8: /* enter */ |
25ea693b | 5553 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 HZ |
5554 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5555 | ir.dflag = 2; | |
5556 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
5557 | return -1; |
5558 | break; | |
5559 | ||
a38bba38 | 5560 | case 0xc9: /* leave */ |
25ea693b MM |
5561 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5562 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5563 | break; |
5564 | ||
a38bba38 | 5565 | case 0x07: /* pop es */ |
cf648174 HZ |
5566 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5567 | { | |
5568 | ir.addr -= 1; | |
5569 | goto no_support; | |
5570 | } | |
25ea693b MM |
5571 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5572 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5573 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5574 | break; |
5575 | ||
a38bba38 | 5576 | case 0x17: /* pop ss */ |
cf648174 HZ |
5577 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5578 | { | |
5579 | ir.addr -= 1; | |
5580 | goto no_support; | |
5581 | } | |
25ea693b MM |
5582 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5583 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5584 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5585 | break; |
5586 | ||
a38bba38 | 5587 | case 0x1f: /* pop ds */ |
cf648174 HZ |
5588 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5589 | { | |
5590 | ir.addr -= 1; | |
5591 | goto no_support; | |
5592 | } | |
25ea693b MM |
5593 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5594 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5595 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5596 | break; |
5597 | ||
a38bba38 | 5598 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5599 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5600 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5601 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5602 | break; |
5603 | ||
a38bba38 | 5604 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5605 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5606 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5607 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5608 | break; |
5609 | ||
a38bba38 | 5610 | case 0x88: /* mov */ |
7ad10968 HZ |
5611 | case 0x89: |
5612 | case 0xc6: | |
5613 | case 0xc7: | |
5614 | if ((opcode & 1) == 0) | |
5615 | ir.ot = OT_BYTE; | |
5616 | else | |
5617 | ir.ot = ir.dflag + OT_WORD; | |
5618 | ||
5619 | if (i386_record_modrm (&ir)) | |
5620 | return -1; | |
5621 | ||
5622 | if (ir.mod != 3) | |
5623 | { | |
cf648174 HZ |
5624 | if (opcode == 0xc6 || opcode == 0xc7) |
5625 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5626 | if (i386_record_lea_modrm (&ir)) |
5627 | return -1; | |
5628 | } | |
5629 | else | |
5630 | { | |
cf648174 HZ |
5631 | if (opcode == 0xc6 || opcode == 0xc7) |
5632 | ir.rm |= ir.rex_b; | |
5633 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5634 | ir.rm &= 0x3; |
25ea693b | 5635 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5636 | } |
7ad10968 | 5637 | break; |
cf648174 | 5638 | |
a38bba38 | 5639 | case 0x8a: /* mov */ |
7ad10968 HZ |
5640 | case 0x8b: |
5641 | if ((opcode & 1) == 0) | |
5642 | ir.ot = OT_BYTE; | |
5643 | else | |
5644 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5645 | if (i386_record_modrm (&ir)) |
5646 | return -1; | |
cf648174 HZ |
5647 | ir.reg |= rex_r; |
5648 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5649 | ir.reg &= 0x3; |
25ea693b | 5650 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5651 | break; |
7ad10968 | 5652 | |
a38bba38 | 5653 | case 0x8c: /* mov seg */ |
cf648174 | 5654 | if (i386_record_modrm (&ir)) |
7ad10968 | 5655 | return -1; |
cf648174 HZ |
5656 | if (ir.reg > 5) |
5657 | { | |
5658 | ir.addr -= 2; | |
5659 | opcode = opcode << 8 | ir.modrm; | |
5660 | goto no_support; | |
5661 | } | |
5662 | ||
5663 | if (ir.mod == 3) | |
25ea693b | 5664 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5665 | else |
5666 | { | |
5667 | ir.ot = OT_WORD; | |
5668 | if (i386_record_lea_modrm (&ir)) | |
5669 | return -1; | |
5670 | } | |
7ad10968 HZ |
5671 | break; |
5672 | ||
a38bba38 | 5673 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5674 | if (i386_record_modrm (&ir)) |
5675 | return -1; | |
7ad10968 HZ |
5676 | switch (ir.reg) |
5677 | { | |
5678 | case 0: | |
425b824a | 5679 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5680 | break; |
5681 | case 2: | |
425b824a | 5682 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5683 | break; |
5684 | case 3: | |
425b824a | 5685 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5686 | break; |
5687 | case 4: | |
425b824a | 5688 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5689 | break; |
5690 | case 5: | |
425b824a | 5691 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5692 | break; |
5693 | default: | |
5694 | ir.addr -= 2; | |
5695 | opcode = opcode << 8 | ir.modrm; | |
5696 | goto no_support; | |
5697 | break; | |
5698 | } | |
25ea693b MM |
5699 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5700 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5701 | break; |
5702 | ||
a38bba38 MS |
5703 | case 0x0fb6: /* movzbS */ |
5704 | case 0x0fb7: /* movzwS */ | |
5705 | case 0x0fbe: /* movsbS */ | |
5706 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5707 | if (i386_record_modrm (&ir)) |
5708 | return -1; | |
25ea693b | 5709 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5710 | break; |
5711 | ||
a38bba38 | 5712 | case 0x8d: /* lea */ |
7ad10968 HZ |
5713 | if (i386_record_modrm (&ir)) |
5714 | return -1; | |
5715 | if (ir.mod == 3) | |
5716 | { | |
5717 | ir.addr -= 2; | |
5718 | opcode = opcode << 8 | ir.modrm; | |
5719 | goto no_support; | |
5720 | } | |
7ad10968 | 5721 | ir.ot = ir.dflag; |
cf648174 HZ |
5722 | ir.reg |= rex_r; |
5723 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5724 | ir.reg &= 0x3; |
25ea693b | 5725 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5726 | break; |
5727 | ||
a38bba38 | 5728 | case 0xa0: /* mov EAX */ |
7ad10968 | 5729 | case 0xa1: |
a38bba38 MS |
5730 | |
5731 | case 0xd7: /* xlat */ | |
25ea693b | 5732 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5733 | break; |
5734 | ||
a38bba38 | 5735 | case 0xa2: /* mov EAX */ |
7ad10968 | 5736 | case 0xa3: |
d7877f7e | 5737 | if (ir.override >= 0) |
cf648174 | 5738 | { |
25ea693b | 5739 | if (record_full_memory_query) |
bb08c432 HZ |
5740 | { |
5741 | int q; | |
5742 | ||
5743 | target_terminal_ours (); | |
5744 | q = yquery (_("\ | |
5745 | Process record ignores the memory change of instruction at address %s\n\ | |
5746 | because it can't get the value of the segment register.\n\ | |
5747 | Do you want to stop the program?"), | |
5748 | paddress (gdbarch, ir.orig_addr)); | |
5749 | target_terminal_inferior (); | |
5750 | if (q) | |
5751 | return -1; | |
5752 | } | |
cf648174 HZ |
5753 | } |
5754 | else | |
5755 | { | |
5756 | if ((opcode & 1) == 0) | |
5757 | ir.ot = OT_BYTE; | |
5758 | else | |
5759 | ir.ot = ir.dflag + OT_WORD; | |
5760 | if (ir.aflag == 2) | |
5761 | { | |
4ffa4fc7 PA |
5762 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
5763 | return -1; | |
cf648174 | 5764 | ir.addr += 8; |
60a1502a | 5765 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5766 | } |
5767 | else if (ir.aflag) | |
5768 | { | |
4ffa4fc7 PA |
5769 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
5770 | return -1; | |
cf648174 | 5771 | ir.addr += 4; |
60a1502a | 5772 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5773 | } |
5774 | else | |
5775 | { | |
4ffa4fc7 PA |
5776 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
5777 | return -1; | |
cf648174 | 5778 | ir.addr += 2; |
60a1502a | 5779 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5780 | } |
25ea693b | 5781 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5782 | return -1; |
5783 | } | |
7ad10968 HZ |
5784 | break; |
5785 | ||
a38bba38 | 5786 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5787 | case 0xb1: |
5788 | case 0xb2: | |
5789 | case 0xb3: | |
5790 | case 0xb4: | |
5791 | case 0xb5: | |
5792 | case 0xb6: | |
5793 | case 0xb7: | |
25ea693b MM |
5794 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5795 | ? ((opcode & 0x7) | ir.rex_b) | |
5796 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5797 | break; |
5798 | ||
a38bba38 | 5799 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5800 | case 0xb9: |
5801 | case 0xba: | |
5802 | case 0xbb: | |
5803 | case 0xbc: | |
5804 | case 0xbd: | |
5805 | case 0xbe: | |
5806 | case 0xbf: | |
25ea693b | 5807 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5808 | break; |
5809 | ||
a38bba38 | 5810 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5811 | case 0x92: |
5812 | case 0x93: | |
5813 | case 0x94: | |
5814 | case 0x95: | |
5815 | case 0x96: | |
5816 | case 0x97: | |
25ea693b MM |
5817 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5818 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5819 | break; |
5820 | ||
a38bba38 | 5821 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5822 | case 0x87: |
5823 | if ((opcode & 1) == 0) | |
5824 | ir.ot = OT_BYTE; | |
5825 | else | |
5826 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5827 | if (i386_record_modrm (&ir)) |
5828 | return -1; | |
7ad10968 HZ |
5829 | if (ir.mod == 3) |
5830 | { | |
86839d38 | 5831 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5832 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5833 | ir.rm &= 0x3; | |
25ea693b | 5834 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5835 | } |
5836 | else | |
5837 | { | |
5838 | if (i386_record_lea_modrm (&ir)) | |
5839 | return -1; | |
5840 | } | |
cf648174 HZ |
5841 | ir.reg |= rex_r; |
5842 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5843 | ir.reg &= 0x3; |
25ea693b | 5844 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5845 | break; |
5846 | ||
a38bba38 MS |
5847 | case 0xc4: /* les Gv */ |
5848 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5849 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5850 | { | |
5851 | ir.addr -= 1; | |
5852 | goto no_support; | |
5853 | } | |
d3f323f3 | 5854 | /* FALLTHROUGH */ |
a38bba38 MS |
5855 | case 0x0fb2: /* lss Gv */ |
5856 | case 0x0fb4: /* lfs Gv */ | |
5857 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5858 | if (i386_record_modrm (&ir)) |
5859 | return -1; | |
5860 | if (ir.mod == 3) | |
5861 | { | |
5862 | if (opcode > 0xff) | |
5863 | ir.addr -= 3; | |
5864 | else | |
5865 | ir.addr -= 2; | |
5866 | opcode = opcode << 8 | ir.modrm; | |
5867 | goto no_support; | |
5868 | } | |
7ad10968 HZ |
5869 | switch (opcode) |
5870 | { | |
a38bba38 | 5871 | case 0xc4: /* les Gv */ |
425b824a | 5872 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5873 | break; |
a38bba38 | 5874 | case 0xc5: /* lds Gv */ |
425b824a | 5875 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5876 | break; |
a38bba38 | 5877 | case 0x0fb2: /* lss Gv */ |
425b824a | 5878 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5879 | break; |
a38bba38 | 5880 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5881 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5882 | break; |
a38bba38 | 5883 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5884 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5885 | break; |
5886 | } | |
25ea693b MM |
5887 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5888 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5889 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5890 | break; |
5891 | ||
a38bba38 | 5892 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5893 | case 0xc1: |
5894 | case 0xd0: | |
5895 | case 0xd1: | |
5896 | case 0xd2: | |
5897 | case 0xd3: | |
5898 | if ((opcode & 1) == 0) | |
5899 | ir.ot = OT_BYTE; | |
5900 | else | |
5901 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5902 | if (i386_record_modrm (&ir)) |
5903 | return -1; | |
7ad10968 HZ |
5904 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5905 | { | |
5906 | if (i386_record_lea_modrm (&ir)) | |
5907 | return -1; | |
5908 | } | |
5909 | else | |
5910 | { | |
cf648174 HZ |
5911 | ir.rm |= ir.rex_b; |
5912 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5913 | ir.rm &= 0x3; |
25ea693b | 5914 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5915 | } |
25ea693b | 5916 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5917 | break; |
5918 | ||
5919 | case 0x0fa4: | |
5920 | case 0x0fa5: | |
5921 | case 0x0fac: | |
5922 | case 0x0fad: | |
5923 | if (i386_record_modrm (&ir)) | |
5924 | return -1; | |
5925 | if (ir.mod == 3) | |
5926 | { | |
25ea693b | 5927 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
5928 | return -1; |
5929 | } | |
5930 | else | |
5931 | { | |
5932 | if (i386_record_lea_modrm (&ir)) | |
5933 | return -1; | |
5934 | } | |
5935 | break; | |
5936 | ||
a38bba38 | 5937 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
5938 | case 0xd9: |
5939 | case 0xda: | |
5940 | case 0xdb: | |
5941 | case 0xdc: | |
5942 | case 0xdd: | |
5943 | case 0xde: | |
5944 | case 0xdf: | |
5945 | if (i386_record_modrm (&ir)) | |
5946 | return -1; | |
5947 | ir.reg |= ((opcode & 7) << 3); | |
5948 | if (ir.mod != 3) | |
5949 | { | |
1777feb0 | 5950 | /* Memory. */ |
955db0c0 | 5951 | uint64_t addr64; |
7ad10968 | 5952 | |
955db0c0 | 5953 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
5954 | return -1; |
5955 | switch (ir.reg) | |
5956 | { | |
7ad10968 | 5957 | case 0x02: |
0289bdd7 MS |
5958 | case 0x12: |
5959 | case 0x22: | |
5960 | case 0x32: | |
5961 | /* For fcom, ficom nothing to do. */ | |
5962 | break; | |
7ad10968 | 5963 | case 0x03: |
0289bdd7 MS |
5964 | case 0x13: |
5965 | case 0x23: | |
5966 | case 0x33: | |
5967 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
5968 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5969 | return -1; | |
5970 | break; | |
5971 | case 0x00: | |
5972 | case 0x01: | |
7ad10968 HZ |
5973 | case 0x04: |
5974 | case 0x05: | |
5975 | case 0x06: | |
5976 | case 0x07: | |
5977 | case 0x10: | |
5978 | case 0x11: | |
7ad10968 HZ |
5979 | case 0x14: |
5980 | case 0x15: | |
5981 | case 0x16: | |
5982 | case 0x17: | |
5983 | case 0x20: | |
5984 | case 0x21: | |
7ad10968 HZ |
5985 | case 0x24: |
5986 | case 0x25: | |
5987 | case 0x26: | |
5988 | case 0x27: | |
5989 | case 0x30: | |
5990 | case 0x31: | |
7ad10968 HZ |
5991 | case 0x34: |
5992 | case 0x35: | |
5993 | case 0x36: | |
5994 | case 0x37: | |
0289bdd7 MS |
5995 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
5996 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
5997 | of code, always affects st(0) register. */ | |
5998 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5999 | return -1; | |
7ad10968 HZ |
6000 | break; |
6001 | case 0x08: | |
6002 | case 0x0a: | |
6003 | case 0x0b: | |
6004 | case 0x18: | |
6005 | case 0x19: | |
6006 | case 0x1a: | |
6007 | case 0x1b: | |
0289bdd7 | 6008 | case 0x1d: |
7ad10968 HZ |
6009 | case 0x28: |
6010 | case 0x29: | |
6011 | case 0x2a: | |
6012 | case 0x2b: | |
6013 | case 0x38: | |
6014 | case 0x39: | |
6015 | case 0x3a: | |
6016 | case 0x3b: | |
0289bdd7 MS |
6017 | case 0x3c: |
6018 | case 0x3d: | |
7ad10968 HZ |
6019 | switch (ir.reg & 7) |
6020 | { | |
6021 | case 0: | |
0289bdd7 MS |
6022 | /* Handling fld, fild. */ |
6023 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6024 | return -1; | |
7ad10968 HZ |
6025 | break; |
6026 | case 1: | |
6027 | switch (ir.reg >> 4) | |
6028 | { | |
6029 | case 0: | |
25ea693b | 6030 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
6031 | return -1; |
6032 | break; | |
6033 | case 2: | |
25ea693b | 6034 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
6035 | return -1; |
6036 | break; | |
6037 | case 3: | |
0289bdd7 | 6038 | break; |
7ad10968 | 6039 | default: |
25ea693b | 6040 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6041 | return -1; |
6042 | break; | |
6043 | } | |
6044 | break; | |
6045 | default: | |
6046 | switch (ir.reg >> 4) | |
6047 | { | |
6048 | case 0: | |
25ea693b | 6049 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
6050 | return -1; |
6051 | if (3 == (ir.reg & 7)) | |
6052 | { | |
6053 | /* For fstp m32fp. */ | |
6054 | if (i386_record_floats (gdbarch, &ir, | |
6055 | I386_SAVE_FPU_REGS)) | |
6056 | return -1; | |
6057 | } | |
6058 | break; | |
7ad10968 | 6059 | case 1: |
25ea693b | 6060 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 6061 | return -1; |
0289bdd7 MS |
6062 | if ((3 == (ir.reg & 7)) |
6063 | || (5 == (ir.reg & 7)) | |
6064 | || (7 == (ir.reg & 7))) | |
6065 | { | |
6066 | /* For fstp insn. */ | |
6067 | if (i386_record_floats (gdbarch, &ir, | |
6068 | I386_SAVE_FPU_REGS)) | |
6069 | return -1; | |
6070 | } | |
7ad10968 HZ |
6071 | break; |
6072 | case 2: | |
25ea693b | 6073 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6074 | return -1; |
0289bdd7 MS |
6075 | if (3 == (ir.reg & 7)) |
6076 | { | |
6077 | /* For fstp m64fp. */ | |
6078 | if (i386_record_floats (gdbarch, &ir, | |
6079 | I386_SAVE_FPU_REGS)) | |
6080 | return -1; | |
6081 | } | |
7ad10968 HZ |
6082 | break; |
6083 | case 3: | |
0289bdd7 MS |
6084 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
6085 | { | |
6086 | /* For fistp, fbld, fild, fbstp. */ | |
6087 | if (i386_record_floats (gdbarch, &ir, | |
6088 | I386_SAVE_FPU_REGS)) | |
6089 | return -1; | |
6090 | } | |
6091 | /* Fall through */ | |
7ad10968 | 6092 | default: |
25ea693b | 6093 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6094 | return -1; |
6095 | break; | |
6096 | } | |
6097 | break; | |
6098 | } | |
6099 | break; | |
6100 | case 0x0c: | |
0289bdd7 MS |
6101 | /* Insn fldenv. */ |
6102 | if (i386_record_floats (gdbarch, &ir, | |
6103 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6104 | return -1; | |
6105 | break; | |
7ad10968 | 6106 | case 0x0d: |
0289bdd7 MS |
6107 | /* Insn fldcw. */ |
6108 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
6109 | return -1; | |
6110 | break; | |
7ad10968 | 6111 | case 0x2c: |
0289bdd7 MS |
6112 | /* Insn frstor. */ |
6113 | if (i386_record_floats (gdbarch, &ir, | |
6114 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6115 | return -1; | |
7ad10968 HZ |
6116 | break; |
6117 | case 0x0e: | |
6118 | if (ir.dflag) | |
6119 | { | |
25ea693b | 6120 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
6121 | return -1; |
6122 | } | |
6123 | else | |
6124 | { | |
25ea693b | 6125 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
6126 | return -1; |
6127 | } | |
6128 | break; | |
6129 | case 0x0f: | |
6130 | case 0x2f: | |
25ea693b | 6131 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6132 | return -1; |
0289bdd7 MS |
6133 | /* Insn fstp, fbstp. */ |
6134 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6135 | return -1; | |
7ad10968 HZ |
6136 | break; |
6137 | case 0x1f: | |
6138 | case 0x3e: | |
25ea693b | 6139 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
6140 | return -1; |
6141 | break; | |
6142 | case 0x2e: | |
6143 | if (ir.dflag) | |
6144 | { | |
25ea693b | 6145 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 6146 | return -1; |
955db0c0 | 6147 | addr64 += 28; |
7ad10968 HZ |
6148 | } |
6149 | else | |
6150 | { | |
25ea693b | 6151 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 6152 | return -1; |
955db0c0 | 6153 | addr64 += 14; |
7ad10968 | 6154 | } |
25ea693b | 6155 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 6156 | return -1; |
0289bdd7 MS |
6157 | /* Insn fsave. */ |
6158 | if (i386_record_floats (gdbarch, &ir, | |
6159 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6160 | return -1; | |
7ad10968 HZ |
6161 | break; |
6162 | case 0x3f: | |
25ea693b | 6163 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6164 | return -1; |
0289bdd7 MS |
6165 | /* Insn fistp. */ |
6166 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6167 | return -1; | |
7ad10968 HZ |
6168 | break; |
6169 | default: | |
6170 | ir.addr -= 2; | |
6171 | opcode = opcode << 8 | ir.modrm; | |
6172 | goto no_support; | |
6173 | break; | |
6174 | } | |
6175 | } | |
0289bdd7 MS |
6176 | /* Opcode is an extension of modR/M byte. */ |
6177 | else | |
6178 | { | |
6179 | switch (opcode) | |
6180 | { | |
6181 | case 0xd8: | |
6182 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6183 | return -1; | |
6184 | break; | |
6185 | case 0xd9: | |
6186 | if (0x0c == (ir.modrm >> 4)) | |
6187 | { | |
6188 | if ((ir.modrm & 0x0f) <= 7) | |
6189 | { | |
6190 | if (i386_record_floats (gdbarch, &ir, | |
6191 | I386_SAVE_FPU_REGS)) | |
6192 | return -1; | |
6193 | } | |
6194 | else | |
6195 | { | |
6196 | if (i386_record_floats (gdbarch, &ir, | |
6197 | I387_ST0_REGNUM (tdep))) | |
6198 | return -1; | |
6199 | /* If only st(0) is changing, then we have already | |
6200 | recorded. */ | |
6201 | if ((ir.modrm & 0x0f) - 0x08) | |
6202 | { | |
6203 | if (i386_record_floats (gdbarch, &ir, | |
6204 | I387_ST0_REGNUM (tdep) + | |
6205 | ((ir.modrm & 0x0f) - 0x08))) | |
6206 | return -1; | |
6207 | } | |
6208 | } | |
6209 | } | |
6210 | else | |
6211 | { | |
6212 | switch (ir.modrm) | |
6213 | { | |
6214 | case 0xe0: | |
6215 | case 0xe1: | |
6216 | case 0xf0: | |
6217 | case 0xf5: | |
6218 | case 0xf8: | |
6219 | case 0xfa: | |
6220 | case 0xfc: | |
6221 | case 0xfe: | |
6222 | case 0xff: | |
6223 | if (i386_record_floats (gdbarch, &ir, | |
6224 | I387_ST0_REGNUM (tdep))) | |
6225 | return -1; | |
6226 | break; | |
6227 | case 0xf1: | |
6228 | case 0xf2: | |
6229 | case 0xf3: | |
6230 | case 0xf4: | |
6231 | case 0xf6: | |
6232 | case 0xf7: | |
6233 | case 0xe8: | |
6234 | case 0xe9: | |
6235 | case 0xea: | |
6236 | case 0xeb: | |
6237 | case 0xec: | |
6238 | case 0xed: | |
6239 | case 0xee: | |
6240 | case 0xf9: | |
6241 | case 0xfb: | |
6242 | if (i386_record_floats (gdbarch, &ir, | |
6243 | I386_SAVE_FPU_REGS)) | |
6244 | return -1; | |
6245 | break; | |
6246 | case 0xfd: | |
6247 | if (i386_record_floats (gdbarch, &ir, | |
6248 | I387_ST0_REGNUM (tdep))) | |
6249 | return -1; | |
6250 | if (i386_record_floats (gdbarch, &ir, | |
6251 | I387_ST0_REGNUM (tdep) + 1)) | |
6252 | return -1; | |
6253 | break; | |
6254 | } | |
6255 | } | |
6256 | break; | |
6257 | case 0xda: | |
6258 | if (0xe9 == ir.modrm) | |
6259 | { | |
6260 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6261 | return -1; | |
6262 | } | |
6263 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6264 | { | |
6265 | if (i386_record_floats (gdbarch, &ir, | |
6266 | I387_ST0_REGNUM (tdep))) | |
6267 | return -1; | |
6268 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6269 | { | |
6270 | if (i386_record_floats (gdbarch, &ir, | |
6271 | I387_ST0_REGNUM (tdep) + | |
6272 | (ir.modrm & 0x0f))) | |
6273 | return -1; | |
6274 | } | |
6275 | else if ((ir.modrm & 0x0f) - 0x08) | |
6276 | { | |
6277 | if (i386_record_floats (gdbarch, &ir, | |
6278 | I387_ST0_REGNUM (tdep) + | |
6279 | ((ir.modrm & 0x0f) - 0x08))) | |
6280 | return -1; | |
6281 | } | |
6282 | } | |
6283 | break; | |
6284 | case 0xdb: | |
6285 | if (0xe3 == ir.modrm) | |
6286 | { | |
6287 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
6288 | return -1; | |
6289 | } | |
6290 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6291 | { | |
6292 | if (i386_record_floats (gdbarch, &ir, | |
6293 | I387_ST0_REGNUM (tdep))) | |
6294 | return -1; | |
6295 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6296 | { | |
6297 | if (i386_record_floats (gdbarch, &ir, | |
6298 | I387_ST0_REGNUM (tdep) + | |
6299 | (ir.modrm & 0x0f))) | |
6300 | return -1; | |
6301 | } | |
6302 | else if ((ir.modrm & 0x0f) - 0x08) | |
6303 | { | |
6304 | if (i386_record_floats (gdbarch, &ir, | |
6305 | I387_ST0_REGNUM (tdep) + | |
6306 | ((ir.modrm & 0x0f) - 0x08))) | |
6307 | return -1; | |
6308 | } | |
6309 | } | |
6310 | break; | |
6311 | case 0xdc: | |
6312 | if ((0x0c == ir.modrm >> 4) | |
6313 | || (0x0d == ir.modrm >> 4) | |
6314 | || (0x0f == ir.modrm >> 4)) | |
6315 | { | |
6316 | if ((ir.modrm & 0x0f) <= 7) | |
6317 | { | |
6318 | if (i386_record_floats (gdbarch, &ir, | |
6319 | I387_ST0_REGNUM (tdep) + | |
6320 | (ir.modrm & 0x0f))) | |
6321 | return -1; | |
6322 | } | |
6323 | else | |
6324 | { | |
6325 | if (i386_record_floats (gdbarch, &ir, | |
6326 | I387_ST0_REGNUM (tdep) + | |
6327 | ((ir.modrm & 0x0f) - 0x08))) | |
6328 | return -1; | |
6329 | } | |
6330 | } | |
6331 | break; | |
6332 | case 0xdd: | |
6333 | if (0x0c == ir.modrm >> 4) | |
6334 | { | |
6335 | if (i386_record_floats (gdbarch, &ir, | |
6336 | I387_FTAG_REGNUM (tdep))) | |
6337 | return -1; | |
6338 | } | |
6339 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6340 | { | |
6341 | if ((ir.modrm & 0x0f) <= 7) | |
6342 | { | |
6343 | if (i386_record_floats (gdbarch, &ir, | |
6344 | I387_ST0_REGNUM (tdep) + | |
6345 | (ir.modrm & 0x0f))) | |
6346 | return -1; | |
6347 | } | |
6348 | else | |
6349 | { | |
6350 | if (i386_record_floats (gdbarch, &ir, | |
6351 | I386_SAVE_FPU_REGS)) | |
6352 | return -1; | |
6353 | } | |
6354 | } | |
6355 | break; | |
6356 | case 0xde: | |
6357 | if ((0x0c == ir.modrm >> 4) | |
6358 | || (0x0e == ir.modrm >> 4) | |
6359 | || (0x0f == ir.modrm >> 4) | |
6360 | || (0xd9 == ir.modrm)) | |
6361 | { | |
6362 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6363 | return -1; | |
6364 | } | |
6365 | break; | |
6366 | case 0xdf: | |
6367 | if (0xe0 == ir.modrm) | |
6368 | { | |
25ea693b MM |
6369 | if (record_full_arch_list_add_reg (ir.regcache, |
6370 | I386_EAX_REGNUM)) | |
0289bdd7 MS |
6371 | return -1; |
6372 | } | |
6373 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6374 | { | |
6375 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6376 | return -1; | |
6377 | } | |
6378 | break; | |
6379 | } | |
6380 | } | |
7ad10968 | 6381 | break; |
7ad10968 | 6382 | /* string ops */ |
a38bba38 | 6383 | case 0xa4: /* movsS */ |
7ad10968 | 6384 | case 0xa5: |
a38bba38 | 6385 | case 0xaa: /* stosS */ |
7ad10968 | 6386 | case 0xab: |
a38bba38 | 6387 | case 0x6c: /* insS */ |
7ad10968 | 6388 | case 0x6d: |
cf648174 | 6389 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 6390 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
6391 | &addr); |
6392 | if (addr) | |
cf648174 | 6393 | { |
77d7dc92 HZ |
6394 | ULONGEST es, ds; |
6395 | ||
6396 | if ((opcode & 1) == 0) | |
6397 | ir.ot = OT_BYTE; | |
6398 | else | |
6399 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
6400 | regcache_raw_read_unsigned (ir.regcache, |
6401 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 6402 | &addr); |
77d7dc92 | 6403 | |
d7877f7e HZ |
6404 | regcache_raw_read_unsigned (ir.regcache, |
6405 | ir.regmap[X86_RECORD_ES_REGNUM], | |
6406 | &es); | |
6407 | regcache_raw_read_unsigned (ir.regcache, | |
6408 | ir.regmap[X86_RECORD_DS_REGNUM], | |
6409 | &ds); | |
6410 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
6411 | { |
6412 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
25ea693b | 6413 | if (record_full_memory_query) |
bb08c432 HZ |
6414 | { |
6415 | int q; | |
6416 | ||
6417 | target_terminal_ours (); | |
6418 | q = yquery (_("\ | |
6419 | Process record ignores the memory change of instruction at address %s\n\ | |
6420 | because it can't get the value of the segment register.\n\ | |
6421 | Do you want to stop the program?"), | |
6422 | paddress (gdbarch, ir.orig_addr)); | |
6423 | target_terminal_inferior (); | |
6424 | if (q) | |
6425 | return -1; | |
6426 | } | |
df61f520 HZ |
6427 | } |
6428 | else | |
6429 | { | |
25ea693b | 6430 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 6431 | return -1; |
77d7dc92 HZ |
6432 | } |
6433 | ||
6434 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
25ea693b | 6435 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
77d7dc92 | 6436 | if (opcode == 0xa4 || opcode == 0xa5) |
25ea693b MM |
6437 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
6438 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6439 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 6440 | } |
cf648174 | 6441 | break; |
7ad10968 | 6442 | |
a38bba38 | 6443 | case 0xa6: /* cmpsS */ |
cf648174 | 6444 | case 0xa7: |
25ea693b MM |
6445 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6446 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6447 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6448 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6449 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6450 | break; |
6451 | ||
a38bba38 | 6452 | case 0xac: /* lodsS */ |
7ad10968 | 6453 | case 0xad: |
25ea693b MM |
6454 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6455 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6456 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6457 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6458 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6459 | break; |
6460 | ||
a38bba38 | 6461 | case 0xae: /* scasS */ |
7ad10968 | 6462 | case 0xaf: |
25ea693b | 6463 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6464 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6465 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6466 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6467 | break; |
6468 | ||
a38bba38 | 6469 | case 0x6e: /* outsS */ |
cf648174 | 6470 | case 0x6f: |
25ea693b | 6471 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6472 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6473 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6474 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6475 | break; |
6476 | ||
a38bba38 | 6477 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6478 | case 0xe5: |
6479 | case 0xec: | |
6480 | case 0xed: | |
25ea693b MM |
6481 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6482 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6483 | break; |
6484 | ||
6485 | case 0xe6: | |
6486 | case 0xe7: | |
6487 | case 0xee: | |
6488 | case 0xef: | |
6489 | break; | |
6490 | ||
6491 | /* control */ | |
a38bba38 MS |
6492 | case 0xc2: /* ret im */ |
6493 | case 0xc3: /* ret */ | |
25ea693b MM |
6494 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6495 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6496 | break; |
6497 | ||
a38bba38 MS |
6498 | case 0xca: /* lret im */ |
6499 | case 0xcb: /* lret */ | |
6500 | case 0xcf: /* iret */ | |
25ea693b MM |
6501 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6502 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6503 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6504 | break; |
6505 | ||
a38bba38 | 6506 | case 0xe8: /* call im */ |
cf648174 HZ |
6507 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6508 | ir.dflag = 2; | |
6509 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6510 | return -1; | |
7ad10968 HZ |
6511 | break; |
6512 | ||
a38bba38 | 6513 | case 0x9a: /* lcall im */ |
cf648174 HZ |
6514 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6515 | { | |
6516 | ir.addr -= 1; | |
6517 | goto no_support; | |
6518 | } | |
25ea693b | 6519 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 HZ |
6520 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
6521 | return -1; | |
7ad10968 HZ |
6522 | break; |
6523 | ||
a38bba38 MS |
6524 | case 0xe9: /* jmp im */ |
6525 | case 0xea: /* ljmp im */ | |
6526 | case 0xeb: /* jmp Jb */ | |
6527 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6528 | case 0x71: |
6529 | case 0x72: | |
6530 | case 0x73: | |
6531 | case 0x74: | |
6532 | case 0x75: | |
6533 | case 0x76: | |
6534 | case 0x77: | |
6535 | case 0x78: | |
6536 | case 0x79: | |
6537 | case 0x7a: | |
6538 | case 0x7b: | |
6539 | case 0x7c: | |
6540 | case 0x7d: | |
6541 | case 0x7e: | |
6542 | case 0x7f: | |
a38bba38 | 6543 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6544 | case 0x0f81: |
6545 | case 0x0f82: | |
6546 | case 0x0f83: | |
6547 | case 0x0f84: | |
6548 | case 0x0f85: | |
6549 | case 0x0f86: | |
6550 | case 0x0f87: | |
6551 | case 0x0f88: | |
6552 | case 0x0f89: | |
6553 | case 0x0f8a: | |
6554 | case 0x0f8b: | |
6555 | case 0x0f8c: | |
6556 | case 0x0f8d: | |
6557 | case 0x0f8e: | |
6558 | case 0x0f8f: | |
6559 | break; | |
6560 | ||
a38bba38 | 6561 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6562 | case 0x0f91: |
6563 | case 0x0f92: | |
6564 | case 0x0f93: | |
6565 | case 0x0f94: | |
6566 | case 0x0f95: | |
6567 | case 0x0f96: | |
6568 | case 0x0f97: | |
6569 | case 0x0f98: | |
6570 | case 0x0f99: | |
6571 | case 0x0f9a: | |
6572 | case 0x0f9b: | |
6573 | case 0x0f9c: | |
6574 | case 0x0f9d: | |
6575 | case 0x0f9e: | |
6576 | case 0x0f9f: | |
25ea693b | 6577 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6578 | ir.ot = OT_BYTE; |
6579 | if (i386_record_modrm (&ir)) | |
6580 | return -1; | |
6581 | if (ir.mod == 3) | |
25ea693b MM |
6582 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
6583 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
6584 | else |
6585 | { | |
6586 | if (i386_record_lea_modrm (&ir)) | |
6587 | return -1; | |
6588 | } | |
6589 | break; | |
6590 | ||
a38bba38 | 6591 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6592 | case 0x0f41: |
6593 | case 0x0f42: | |
6594 | case 0x0f43: | |
6595 | case 0x0f44: | |
6596 | case 0x0f45: | |
6597 | case 0x0f46: | |
6598 | case 0x0f47: | |
6599 | case 0x0f48: | |
6600 | case 0x0f49: | |
6601 | case 0x0f4a: | |
6602 | case 0x0f4b: | |
6603 | case 0x0f4c: | |
6604 | case 0x0f4d: | |
6605 | case 0x0f4e: | |
6606 | case 0x0f4f: | |
6607 | if (i386_record_modrm (&ir)) | |
6608 | return -1; | |
cf648174 | 6609 | ir.reg |= rex_r; |
7ad10968 HZ |
6610 | if (ir.dflag == OT_BYTE) |
6611 | ir.reg &= 0x3; | |
25ea693b | 6612 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6613 | break; |
6614 | ||
6615 | /* flags */ | |
a38bba38 | 6616 | case 0x9c: /* pushf */ |
25ea693b | 6617 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6618 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6619 | ir.dflag = 2; | |
6620 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6621 | return -1; | |
7ad10968 HZ |
6622 | break; |
6623 | ||
a38bba38 | 6624 | case 0x9d: /* popf */ |
25ea693b MM |
6625 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6626 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6627 | break; |
6628 | ||
a38bba38 | 6629 | case 0x9e: /* sahf */ |
cf648174 HZ |
6630 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6631 | { | |
6632 | ir.addr -= 1; | |
6633 | goto no_support; | |
6634 | } | |
d3f323f3 | 6635 | /* FALLTHROUGH */ |
a38bba38 MS |
6636 | case 0xf5: /* cmc */ |
6637 | case 0xf8: /* clc */ | |
6638 | case 0xf9: /* stc */ | |
6639 | case 0xfc: /* cld */ | |
6640 | case 0xfd: /* std */ | |
25ea693b | 6641 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6642 | break; |
6643 | ||
a38bba38 | 6644 | case 0x9f: /* lahf */ |
cf648174 HZ |
6645 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6646 | { | |
6647 | ir.addr -= 1; | |
6648 | goto no_support; | |
6649 | } | |
25ea693b MM |
6650 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6651 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6652 | break; |
6653 | ||
6654 | /* bit operations */ | |
a38bba38 | 6655 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6656 | ir.ot = ir.dflag + OT_WORD; |
6657 | if (i386_record_modrm (&ir)) | |
6658 | return -1; | |
6659 | if (ir.reg < 4) | |
6660 | { | |
cf648174 | 6661 | ir.addr -= 2; |
7ad10968 HZ |
6662 | opcode = opcode << 8 | ir.modrm; |
6663 | goto no_support; | |
6664 | } | |
cf648174 | 6665 | if (ir.reg != 4) |
7ad10968 | 6666 | { |
cf648174 | 6667 | if (ir.mod == 3) |
25ea693b | 6668 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6669 | else |
6670 | { | |
cf648174 | 6671 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6672 | return -1; |
6673 | } | |
6674 | } | |
25ea693b | 6675 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6676 | break; |
6677 | ||
a38bba38 | 6678 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6679 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6680 | break; |
6681 | ||
a38bba38 MS |
6682 | case 0x0fab: /* bts */ |
6683 | case 0x0fb3: /* btr */ | |
6684 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6685 | ir.ot = ir.dflag + OT_WORD; |
6686 | if (i386_record_modrm (&ir)) | |
6687 | return -1; | |
6688 | if (ir.mod == 3) | |
25ea693b | 6689 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 HZ |
6690 | else |
6691 | { | |
955db0c0 MS |
6692 | uint64_t addr64; |
6693 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6694 | return -1; |
6695 | regcache_raw_read_unsigned (ir.regcache, | |
6696 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6697 | &addr); |
cf648174 HZ |
6698 | switch (ir.dflag) |
6699 | { | |
6700 | case 0: | |
648d0c8b | 6701 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6702 | break; |
6703 | case 1: | |
648d0c8b | 6704 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6705 | break; |
6706 | case 2: | |
648d0c8b | 6707 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6708 | break; |
6709 | } | |
25ea693b | 6710 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6711 | return -1; |
6712 | if (i386_record_lea_modrm (&ir)) | |
6713 | return -1; | |
6714 | } | |
25ea693b | 6715 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6716 | break; |
6717 | ||
a38bba38 MS |
6718 | case 0x0fbc: /* bsf */ |
6719 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6720 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6721 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6722 | break; |
6723 | ||
6724 | /* bcd */ | |
a38bba38 MS |
6725 | case 0x27: /* daa */ |
6726 | case 0x2f: /* das */ | |
6727 | case 0x37: /* aaa */ | |
6728 | case 0x3f: /* aas */ | |
6729 | case 0xd4: /* aam */ | |
6730 | case 0xd5: /* aad */ | |
cf648174 HZ |
6731 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6732 | { | |
6733 | ir.addr -= 1; | |
6734 | goto no_support; | |
6735 | } | |
25ea693b MM |
6736 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6737 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6738 | break; |
6739 | ||
6740 | /* misc */ | |
a38bba38 | 6741 | case 0x90: /* nop */ |
7ad10968 HZ |
6742 | if (prefixes & PREFIX_LOCK) |
6743 | { | |
6744 | ir.addr -= 1; | |
6745 | goto no_support; | |
6746 | } | |
6747 | break; | |
6748 | ||
a38bba38 | 6749 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6750 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6751 | return -1; | |
425b824a | 6752 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6753 | ir.addr++; |
6754 | goto reswitch; | |
7ad10968 HZ |
6755 | break; |
6756 | ||
7ad10968 | 6757 | /* XXX */ |
a38bba38 | 6758 | case 0xcc: /* int3 */ |
a3c4230a | 6759 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6760 | "int3.\n")); |
6761 | ir.addr -= 1; | |
6762 | goto no_support; | |
6763 | break; | |
6764 | ||
7ad10968 | 6765 | /* XXX */ |
a38bba38 | 6766 | case 0xcd: /* int */ |
7ad10968 HZ |
6767 | { |
6768 | int ret; | |
425b824a | 6769 | uint8_t interrupt; |
4ffa4fc7 PA |
6770 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6771 | return -1; | |
7ad10968 | 6772 | ir.addr++; |
425b824a | 6773 | if (interrupt != 0x80 |
a3c4230a | 6774 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6775 | { |
a3c4230a | 6776 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6777 | "instruction int 0x%02x.\n"), |
425b824a | 6778 | interrupt); |
7ad10968 HZ |
6779 | ir.addr -= 2; |
6780 | goto no_support; | |
6781 | } | |
a3c4230a | 6782 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6783 | if (ret) |
6784 | return ret; | |
6785 | } | |
6786 | break; | |
6787 | ||
7ad10968 | 6788 | /* XXX */ |
a38bba38 | 6789 | case 0xce: /* into */ |
a3c4230a | 6790 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6791 | "instruction into.\n")); |
6792 | ir.addr -= 1; | |
6793 | goto no_support; | |
6794 | break; | |
6795 | ||
a38bba38 MS |
6796 | case 0xfa: /* cli */ |
6797 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6798 | break; |
6799 | ||
a38bba38 | 6800 | case 0x62: /* bound */ |
a3c4230a | 6801 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6802 | "instruction bound.\n")); |
6803 | ir.addr -= 1; | |
6804 | goto no_support; | |
6805 | break; | |
6806 | ||
a38bba38 | 6807 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6808 | case 0x0fc9: |
6809 | case 0x0fca: | |
6810 | case 0x0fcb: | |
6811 | case 0x0fcc: | |
6812 | case 0x0fcd: | |
6813 | case 0x0fce: | |
6814 | case 0x0fcf: | |
25ea693b | 6815 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6816 | break; |
6817 | ||
a38bba38 | 6818 | case 0xd6: /* salc */ |
cf648174 HZ |
6819 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6820 | { | |
6821 | ir.addr -= 1; | |
6822 | goto no_support; | |
6823 | } | |
25ea693b MM |
6824 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6825 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6826 | break; |
6827 | ||
a38bba38 MS |
6828 | case 0xe0: /* loopnz */ |
6829 | case 0xe1: /* loopz */ | |
6830 | case 0xe2: /* loop */ | |
6831 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6832 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6833 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6834 | break; |
6835 | ||
a38bba38 | 6836 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6837 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6838 | "instruction wrmsr.\n")); |
6839 | ir.addr -= 2; | |
6840 | goto no_support; | |
6841 | break; | |
6842 | ||
a38bba38 | 6843 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6844 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6845 | "instruction rdmsr.\n")); |
6846 | ir.addr -= 2; | |
6847 | goto no_support; | |
6848 | break; | |
6849 | ||
a38bba38 | 6850 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6851 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6852 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6853 | break; |
6854 | ||
a38bba38 | 6855 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6856 | { |
6857 | int ret; | |
cf648174 HZ |
6858 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6859 | { | |
6860 | ir.addr -= 2; | |
6861 | goto no_support; | |
6862 | } | |
a3c4230a | 6863 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6864 | { |
a3c4230a | 6865 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6866 | "instruction sysenter.\n")); |
6867 | ir.addr -= 2; | |
6868 | goto no_support; | |
6869 | } | |
a3c4230a | 6870 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6871 | if (ret) |
6872 | return ret; | |
6873 | } | |
6874 | break; | |
6875 | ||
a38bba38 | 6876 | case 0x0f35: /* sysexit */ |
a3c4230a | 6877 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6878 | "instruction sysexit.\n")); |
6879 | ir.addr -= 2; | |
6880 | goto no_support; | |
6881 | break; | |
6882 | ||
a38bba38 | 6883 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6884 | { |
6885 | int ret; | |
a3c4230a | 6886 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6887 | { |
a3c4230a | 6888 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6889 | "instruction syscall.\n")); |
6890 | ir.addr -= 2; | |
6891 | goto no_support; | |
6892 | } | |
a3c4230a | 6893 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6894 | if (ret) |
6895 | return ret; | |
6896 | } | |
6897 | break; | |
6898 | ||
a38bba38 | 6899 | case 0x0f07: /* sysret */ |
a3c4230a | 6900 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6901 | "instruction sysret.\n")); |
6902 | ir.addr -= 2; | |
6903 | goto no_support; | |
6904 | break; | |
6905 | ||
a38bba38 | 6906 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
6907 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6908 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6909 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6910 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6911 | break; |
6912 | ||
a38bba38 | 6913 | case 0xf4: /* hlt */ |
a3c4230a | 6914 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6915 | "instruction hlt.\n")); |
6916 | ir.addr -= 1; | |
6917 | goto no_support; | |
6918 | break; | |
6919 | ||
6920 | case 0x0f00: | |
6921 | if (i386_record_modrm (&ir)) | |
6922 | return -1; | |
6923 | switch (ir.reg) | |
6924 | { | |
a38bba38 MS |
6925 | case 0: /* sldt */ |
6926 | case 1: /* str */ | |
7ad10968 | 6927 | if (ir.mod == 3) |
25ea693b | 6928 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6929 | else |
6930 | { | |
6931 | ir.ot = OT_WORD; | |
6932 | if (i386_record_lea_modrm (&ir)) | |
6933 | return -1; | |
6934 | } | |
6935 | break; | |
a38bba38 MS |
6936 | case 2: /* lldt */ |
6937 | case 3: /* ltr */ | |
7ad10968 | 6938 | break; |
a38bba38 MS |
6939 | case 4: /* verr */ |
6940 | case 5: /* verw */ | |
25ea693b | 6941 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6942 | break; |
6943 | default: | |
6944 | ir.addr -= 3; | |
6945 | opcode = opcode << 8 | ir.modrm; | |
6946 | goto no_support; | |
6947 | break; | |
6948 | } | |
6949 | break; | |
6950 | ||
6951 | case 0x0f01: | |
6952 | if (i386_record_modrm (&ir)) | |
6953 | return -1; | |
6954 | switch (ir.reg) | |
6955 | { | |
a38bba38 | 6956 | case 0: /* sgdt */ |
7ad10968 | 6957 | { |
955db0c0 | 6958 | uint64_t addr64; |
7ad10968 HZ |
6959 | |
6960 | if (ir.mod == 3) | |
6961 | { | |
6962 | ir.addr -= 3; | |
6963 | opcode = opcode << 8 | ir.modrm; | |
6964 | goto no_support; | |
6965 | } | |
d7877f7e | 6966 | if (ir.override >= 0) |
7ad10968 | 6967 | { |
25ea693b | 6968 | if (record_full_memory_query) |
bb08c432 HZ |
6969 | { |
6970 | int q; | |
6971 | ||
6972 | target_terminal_ours (); | |
6973 | q = yquery (_("\ | |
6974 | Process record ignores the memory change of instruction at address %s\n\ | |
6975 | because it can't get the value of the segment register.\n\ | |
6976 | Do you want to stop the program?"), | |
6977 | paddress (gdbarch, ir.orig_addr)); | |
6978 | target_terminal_inferior (); | |
6979 | if (q) | |
6980 | return -1; | |
6981 | } | |
7ad10968 HZ |
6982 | } |
6983 | else | |
6984 | { | |
955db0c0 | 6985 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6986 | return -1; |
25ea693b | 6987 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6988 | return -1; |
955db0c0 | 6989 | addr64 += 2; |
cf648174 HZ |
6990 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6991 | { | |
25ea693b | 6992 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6993 | return -1; |
6994 | } | |
6995 | else | |
6996 | { | |
25ea693b | 6997 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6998 | return -1; |
6999 | } | |
7ad10968 HZ |
7000 | } |
7001 | } | |
7002 | break; | |
7003 | case 1: | |
7004 | if (ir.mod == 3) | |
7005 | { | |
7006 | switch (ir.rm) | |
7007 | { | |
a38bba38 | 7008 | case 0: /* monitor */ |
7ad10968 | 7009 | break; |
a38bba38 | 7010 | case 1: /* mwait */ |
25ea693b | 7011 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7012 | break; |
7013 | default: | |
7014 | ir.addr -= 3; | |
7015 | opcode = opcode << 8 | ir.modrm; | |
7016 | goto no_support; | |
7017 | break; | |
7018 | } | |
7019 | } | |
7020 | else | |
7021 | { | |
7022 | /* sidt */ | |
d7877f7e | 7023 | if (ir.override >= 0) |
7ad10968 | 7024 | { |
25ea693b | 7025 | if (record_full_memory_query) |
bb08c432 HZ |
7026 | { |
7027 | int q; | |
7028 | ||
7029 | target_terminal_ours (); | |
7030 | q = yquery (_("\ | |
7031 | Process record ignores the memory change of instruction at address %s\n\ | |
7032 | because it can't get the value of the segment register.\n\ | |
7033 | Do you want to stop the program?"), | |
7034 | paddress (gdbarch, ir.orig_addr)); | |
7035 | target_terminal_inferior (); | |
7036 | if (q) | |
7037 | return -1; | |
7038 | } | |
7ad10968 HZ |
7039 | } |
7040 | else | |
7041 | { | |
955db0c0 | 7042 | uint64_t addr64; |
7ad10968 | 7043 | |
955db0c0 | 7044 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7045 | return -1; |
25ea693b | 7046 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7047 | return -1; |
955db0c0 | 7048 | addr64 += 2; |
cf648174 HZ |
7049 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7050 | { | |
25ea693b | 7051 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7052 | return -1; |
7053 | } | |
7054 | else | |
7055 | { | |
25ea693b | 7056 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7057 | return -1; |
7058 | } | |
7ad10968 HZ |
7059 | } |
7060 | } | |
7061 | break; | |
a38bba38 | 7062 | case 2: /* lgdt */ |
3800e645 MS |
7063 | if (ir.mod == 3) |
7064 | { | |
7065 | /* xgetbv */ | |
7066 | if (ir.rm == 0) | |
7067 | { | |
25ea693b MM |
7068 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7069 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
7070 | break; |
7071 | } | |
7072 | /* xsetbv */ | |
7073 | else if (ir.rm == 1) | |
7074 | break; | |
7075 | } | |
a38bba38 | 7076 | case 3: /* lidt */ |
7ad10968 HZ |
7077 | if (ir.mod == 3) |
7078 | { | |
7079 | ir.addr -= 3; | |
7080 | opcode = opcode << 8 | ir.modrm; | |
7081 | goto no_support; | |
7082 | } | |
7083 | break; | |
a38bba38 | 7084 | case 4: /* smsw */ |
7ad10968 HZ |
7085 | if (ir.mod == 3) |
7086 | { | |
25ea693b | 7087 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
7088 | return -1; |
7089 | } | |
7090 | else | |
7091 | { | |
7092 | ir.ot = OT_WORD; | |
7093 | if (i386_record_lea_modrm (&ir)) | |
7094 | return -1; | |
7095 | } | |
25ea693b | 7096 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7097 | break; |
a38bba38 | 7098 | case 6: /* lmsw */ |
25ea693b | 7099 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 7100 | break; |
a38bba38 | 7101 | case 7: /* invlpg */ |
cf648174 HZ |
7102 | if (ir.mod == 3) |
7103 | { | |
7104 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7105 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 HZ |
7106 | else |
7107 | { | |
7108 | ir.addr -= 3; | |
7109 | opcode = opcode << 8 | ir.modrm; | |
7110 | goto no_support; | |
7111 | } | |
7112 | } | |
7113 | else | |
25ea693b | 7114 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
7115 | break; |
7116 | default: | |
7117 | ir.addr -= 3; | |
7118 | opcode = opcode << 8 | ir.modrm; | |
7119 | goto no_support; | |
7ad10968 HZ |
7120 | break; |
7121 | } | |
7122 | break; | |
7123 | ||
a38bba38 MS |
7124 | case 0x0f08: /* invd */ |
7125 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
7126 | break; |
7127 | ||
a38bba38 | 7128 | case 0x63: /* arpl */ |
7ad10968 HZ |
7129 | if (i386_record_modrm (&ir)) |
7130 | return -1; | |
cf648174 HZ |
7131 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
7132 | { | |
25ea693b MM |
7133 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
7134 | ? (ir.reg | rex_r) : ir.rm); | |
cf648174 | 7135 | } |
7ad10968 | 7136 | else |
cf648174 HZ |
7137 | { |
7138 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
7139 | if (i386_record_lea_modrm (&ir)) | |
7140 | return -1; | |
7141 | } | |
7142 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7143 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7144 | break; |
7145 | ||
a38bba38 MS |
7146 | case 0x0f02: /* lar */ |
7147 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
7148 | if (i386_record_modrm (&ir)) |
7149 | return -1; | |
25ea693b MM |
7150 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7151 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
7152 | break; |
7153 | ||
7154 | case 0x0f18: | |
cf648174 HZ |
7155 | if (i386_record_modrm (&ir)) |
7156 | return -1; | |
7157 | if (ir.mod == 3 && ir.reg == 3) | |
7158 | { | |
7159 | ir.addr -= 3; | |
7160 | opcode = opcode << 8 | ir.modrm; | |
7161 | goto no_support; | |
7162 | } | |
7ad10968 HZ |
7163 | break; |
7164 | ||
7ad10968 HZ |
7165 | case 0x0f19: |
7166 | case 0x0f1a: | |
7167 | case 0x0f1b: | |
7168 | case 0x0f1c: | |
7169 | case 0x0f1d: | |
7170 | case 0x0f1e: | |
7171 | case 0x0f1f: | |
a38bba38 | 7172 | /* nop (multi byte) */ |
7ad10968 HZ |
7173 | break; |
7174 | ||
a38bba38 MS |
7175 | case 0x0f20: /* mov reg, crN */ |
7176 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
7177 | if (i386_record_modrm (&ir)) |
7178 | return -1; | |
7179 | if ((ir.modrm & 0xc0) != 0xc0) | |
7180 | { | |
cf648174 | 7181 | ir.addr -= 3; |
7ad10968 HZ |
7182 | opcode = opcode << 8 | ir.modrm; |
7183 | goto no_support; | |
7184 | } | |
7185 | switch (ir.reg) | |
7186 | { | |
7187 | case 0: | |
7188 | case 2: | |
7189 | case 3: | |
7190 | case 4: | |
7191 | case 8: | |
7192 | if (opcode & 2) | |
25ea693b | 7193 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7194 | else |
25ea693b | 7195 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7196 | break; |
7197 | default: | |
cf648174 | 7198 | ir.addr -= 3; |
7ad10968 HZ |
7199 | opcode = opcode << 8 | ir.modrm; |
7200 | goto no_support; | |
7201 | break; | |
7202 | } | |
7203 | break; | |
7204 | ||
a38bba38 MS |
7205 | case 0x0f21: /* mov reg, drN */ |
7206 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
7207 | if (i386_record_modrm (&ir)) |
7208 | return -1; | |
7209 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
7210 | || ir.reg == 5 || ir.reg >= 8) | |
7211 | { | |
cf648174 | 7212 | ir.addr -= 3; |
7ad10968 HZ |
7213 | opcode = opcode << 8 | ir.modrm; |
7214 | goto no_support; | |
7215 | } | |
7216 | if (opcode & 2) | |
25ea693b | 7217 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7218 | else |
25ea693b | 7219 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7220 | break; |
7221 | ||
a38bba38 | 7222 | case 0x0f06: /* clts */ |
25ea693b | 7223 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7224 | break; |
7225 | ||
a3c4230a HZ |
7226 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
7227 | ||
7228 | case 0x0f0d: /* 3DNow! prefetch */ | |
7229 | break; | |
7230 | ||
7231 | case 0x0f0e: /* 3DNow! femms */ | |
7232 | case 0x0f77: /* emms */ | |
7233 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
7234 | goto no_support; | |
25ea693b | 7235 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
7236 | break; |
7237 | ||
7238 | case 0x0f0f: /* 3DNow! data */ | |
7239 | if (i386_record_modrm (&ir)) | |
7240 | return -1; | |
4ffa4fc7 PA |
7241 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7242 | return -1; | |
a3c4230a HZ |
7243 | ir.addr++; |
7244 | switch (opcode8) | |
7245 | { | |
7246 | case 0x0c: /* 3DNow! pi2fw */ | |
7247 | case 0x0d: /* 3DNow! pi2fd */ | |
7248 | case 0x1c: /* 3DNow! pf2iw */ | |
7249 | case 0x1d: /* 3DNow! pf2id */ | |
7250 | case 0x8a: /* 3DNow! pfnacc */ | |
7251 | case 0x8e: /* 3DNow! pfpnacc */ | |
7252 | case 0x90: /* 3DNow! pfcmpge */ | |
7253 | case 0x94: /* 3DNow! pfmin */ | |
7254 | case 0x96: /* 3DNow! pfrcp */ | |
7255 | case 0x97: /* 3DNow! pfrsqrt */ | |
7256 | case 0x9a: /* 3DNow! pfsub */ | |
7257 | case 0x9e: /* 3DNow! pfadd */ | |
7258 | case 0xa0: /* 3DNow! pfcmpgt */ | |
7259 | case 0xa4: /* 3DNow! pfmax */ | |
7260 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
7261 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
7262 | case 0xaa: /* 3DNow! pfsubr */ | |
7263 | case 0xae: /* 3DNow! pfacc */ | |
7264 | case 0xb0: /* 3DNow! pfcmpeq */ | |
7265 | case 0xb4: /* 3DNow! pfmul */ | |
7266 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
7267 | case 0xb7: /* 3DNow! pmulhrw */ | |
7268 | case 0xbb: /* 3DNow! pswapd */ | |
7269 | case 0xbf: /* 3DNow! pavgusb */ | |
7270 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7271 | goto no_support_3dnow_data; | |
25ea693b | 7272 | record_full_arch_list_add_reg (ir.regcache, ir.reg); |
a3c4230a HZ |
7273 | break; |
7274 | ||
7275 | default: | |
7276 | no_support_3dnow_data: | |
7277 | opcode = (opcode << 8) | opcode8; | |
7278 | goto no_support; | |
7279 | break; | |
7280 | } | |
7281 | break; | |
7282 | ||
7283 | case 0x0faa: /* rsm */ | |
25ea693b MM |
7284 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7285 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7286 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7287 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7288 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7289 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
7290 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7291 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7292 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
7293 | break; |
7294 | ||
7295 | case 0x0fae: | |
7296 | if (i386_record_modrm (&ir)) | |
7297 | return -1; | |
7298 | switch(ir.reg) | |
7299 | { | |
7300 | case 0: /* fxsave */ | |
7301 | { | |
7302 | uint64_t tmpu64; | |
7303 | ||
25ea693b | 7304 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7305 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7306 | return -1; | |
25ea693b | 7307 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
a3c4230a HZ |
7308 | return -1; |
7309 | } | |
7310 | break; | |
7311 | ||
7312 | case 1: /* fxrstor */ | |
7313 | { | |
7314 | int i; | |
7315 | ||
25ea693b | 7316 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7317 | |
7318 | for (i = I387_MM0_REGNUM (tdep); | |
7319 | i386_mmx_regnum_p (gdbarch, i); i++) | |
25ea693b | 7320 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7321 | |
7322 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 7323 | i386_xmm_regnum_p (gdbarch, i); i++) |
25ea693b | 7324 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7325 | |
7326 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
25ea693b MM |
7327 | record_full_arch_list_add_reg (ir.regcache, |
7328 | I387_MXCSR_REGNUM(tdep)); | |
a3c4230a HZ |
7329 | |
7330 | for (i = I387_ST0_REGNUM (tdep); | |
7331 | i386_fp_regnum_p (gdbarch, i); i++) | |
25ea693b | 7332 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7333 | |
7334 | for (i = I387_FCTRL_REGNUM (tdep); | |
7335 | i386_fpc_regnum_p (gdbarch, i); i++) | |
25ea693b | 7336 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7337 | } |
7338 | break; | |
7339 | ||
7340 | case 2: /* ldmxcsr */ | |
7341 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
7342 | goto no_support; | |
25ea693b | 7343 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
a3c4230a HZ |
7344 | break; |
7345 | ||
7346 | case 3: /* stmxcsr */ | |
7347 | ir.ot = OT_LONG; | |
7348 | if (i386_record_lea_modrm (&ir)) | |
7349 | return -1; | |
7350 | break; | |
7351 | ||
7352 | case 5: /* lfence */ | |
7353 | case 6: /* mfence */ | |
7354 | case 7: /* sfence clflush */ | |
7355 | break; | |
7356 | ||
7357 | default: | |
7358 | opcode = (opcode << 8) | ir.modrm; | |
7359 | goto no_support; | |
7360 | break; | |
7361 | } | |
7362 | break; | |
7363 | ||
7364 | case 0x0fc3: /* movnti */ | |
7365 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
7366 | if (i386_record_modrm (&ir)) | |
7367 | return -1; | |
7368 | if (ir.mod == 3) | |
7369 | goto no_support; | |
7370 | ir.reg |= rex_r; | |
7371 | if (i386_record_lea_modrm (&ir)) | |
7372 | return -1; | |
7373 | break; | |
7374 | ||
7375 | /* Add prefix to opcode. */ | |
7376 | case 0x0f10: | |
7377 | case 0x0f11: | |
7378 | case 0x0f12: | |
7379 | case 0x0f13: | |
7380 | case 0x0f14: | |
7381 | case 0x0f15: | |
7382 | case 0x0f16: | |
7383 | case 0x0f17: | |
7384 | case 0x0f28: | |
7385 | case 0x0f29: | |
7386 | case 0x0f2a: | |
7387 | case 0x0f2b: | |
7388 | case 0x0f2c: | |
7389 | case 0x0f2d: | |
7390 | case 0x0f2e: | |
7391 | case 0x0f2f: | |
7392 | case 0x0f38: | |
7393 | case 0x0f39: | |
7394 | case 0x0f3a: | |
7395 | case 0x0f50: | |
7396 | case 0x0f51: | |
7397 | case 0x0f52: | |
7398 | case 0x0f53: | |
7399 | case 0x0f54: | |
7400 | case 0x0f55: | |
7401 | case 0x0f56: | |
7402 | case 0x0f57: | |
7403 | case 0x0f58: | |
7404 | case 0x0f59: | |
7405 | case 0x0f5a: | |
7406 | case 0x0f5b: | |
7407 | case 0x0f5c: | |
7408 | case 0x0f5d: | |
7409 | case 0x0f5e: | |
7410 | case 0x0f5f: | |
7411 | case 0x0f60: | |
7412 | case 0x0f61: | |
7413 | case 0x0f62: | |
7414 | case 0x0f63: | |
7415 | case 0x0f64: | |
7416 | case 0x0f65: | |
7417 | case 0x0f66: | |
7418 | case 0x0f67: | |
7419 | case 0x0f68: | |
7420 | case 0x0f69: | |
7421 | case 0x0f6a: | |
7422 | case 0x0f6b: | |
7423 | case 0x0f6c: | |
7424 | case 0x0f6d: | |
7425 | case 0x0f6e: | |
7426 | case 0x0f6f: | |
7427 | case 0x0f70: | |
7428 | case 0x0f71: | |
7429 | case 0x0f72: | |
7430 | case 0x0f73: | |
7431 | case 0x0f74: | |
7432 | case 0x0f75: | |
7433 | case 0x0f76: | |
7434 | case 0x0f7c: | |
7435 | case 0x0f7d: | |
7436 | case 0x0f7e: | |
7437 | case 0x0f7f: | |
7438 | case 0x0fb8: | |
7439 | case 0x0fc2: | |
7440 | case 0x0fc4: | |
7441 | case 0x0fc5: | |
7442 | case 0x0fc6: | |
7443 | case 0x0fd0: | |
7444 | case 0x0fd1: | |
7445 | case 0x0fd2: | |
7446 | case 0x0fd3: | |
7447 | case 0x0fd4: | |
7448 | case 0x0fd5: | |
7449 | case 0x0fd6: | |
7450 | case 0x0fd7: | |
7451 | case 0x0fd8: | |
7452 | case 0x0fd9: | |
7453 | case 0x0fda: | |
7454 | case 0x0fdb: | |
7455 | case 0x0fdc: | |
7456 | case 0x0fdd: | |
7457 | case 0x0fde: | |
7458 | case 0x0fdf: | |
7459 | case 0x0fe0: | |
7460 | case 0x0fe1: | |
7461 | case 0x0fe2: | |
7462 | case 0x0fe3: | |
7463 | case 0x0fe4: | |
7464 | case 0x0fe5: | |
7465 | case 0x0fe6: | |
7466 | case 0x0fe7: | |
7467 | case 0x0fe8: | |
7468 | case 0x0fe9: | |
7469 | case 0x0fea: | |
7470 | case 0x0feb: | |
7471 | case 0x0fec: | |
7472 | case 0x0fed: | |
7473 | case 0x0fee: | |
7474 | case 0x0fef: | |
7475 | case 0x0ff0: | |
7476 | case 0x0ff1: | |
7477 | case 0x0ff2: | |
7478 | case 0x0ff3: | |
7479 | case 0x0ff4: | |
7480 | case 0x0ff5: | |
7481 | case 0x0ff6: | |
7482 | case 0x0ff7: | |
7483 | case 0x0ff8: | |
7484 | case 0x0ff9: | |
7485 | case 0x0ffa: | |
7486 | case 0x0ffb: | |
7487 | case 0x0ffc: | |
7488 | case 0x0ffd: | |
7489 | case 0x0ffe: | |
f9fda3f5 L |
7490 | /* Mask out PREFIX_ADDR. */ |
7491 | switch ((prefixes & ~PREFIX_ADDR)) | |
a3c4230a HZ |
7492 | { |
7493 | case PREFIX_REPNZ: | |
7494 | opcode |= 0xf20000; | |
7495 | break; | |
7496 | case PREFIX_DATA: | |
7497 | opcode |= 0x660000; | |
7498 | break; | |
7499 | case PREFIX_REPZ: | |
7500 | opcode |= 0xf30000; | |
7501 | break; | |
7502 | } | |
7503 | reswitch_prefix_add: | |
7504 | switch (opcode) | |
7505 | { | |
7506 | case 0x0f38: | |
7507 | case 0x660f38: | |
7508 | case 0xf20f38: | |
7509 | case 0x0f3a: | |
7510 | case 0x660f3a: | |
4ffa4fc7 PA |
7511 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7512 | return -1; | |
a3c4230a HZ |
7513 | ir.addr++; |
7514 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7515 | goto reswitch_prefix_add; | |
7516 | break; | |
7517 | ||
7518 | case 0x0f10: /* movups */ | |
7519 | case 0x660f10: /* movupd */ | |
7520 | case 0xf30f10: /* movss */ | |
7521 | case 0xf20f10: /* movsd */ | |
7522 | case 0x0f12: /* movlps */ | |
7523 | case 0x660f12: /* movlpd */ | |
7524 | case 0xf30f12: /* movsldup */ | |
7525 | case 0xf20f12: /* movddup */ | |
7526 | case 0x0f14: /* unpcklps */ | |
7527 | case 0x660f14: /* unpcklpd */ | |
7528 | case 0x0f15: /* unpckhps */ | |
7529 | case 0x660f15: /* unpckhpd */ | |
7530 | case 0x0f16: /* movhps */ | |
7531 | case 0x660f16: /* movhpd */ | |
7532 | case 0xf30f16: /* movshdup */ | |
7533 | case 0x0f28: /* movaps */ | |
7534 | case 0x660f28: /* movapd */ | |
7535 | case 0x0f2a: /* cvtpi2ps */ | |
7536 | case 0x660f2a: /* cvtpi2pd */ | |
7537 | case 0xf30f2a: /* cvtsi2ss */ | |
7538 | case 0xf20f2a: /* cvtsi2sd */ | |
7539 | case 0x0f2c: /* cvttps2pi */ | |
7540 | case 0x660f2c: /* cvttpd2pi */ | |
7541 | case 0x0f2d: /* cvtps2pi */ | |
7542 | case 0x660f2d: /* cvtpd2pi */ | |
7543 | case 0x660f3800: /* pshufb */ | |
7544 | case 0x660f3801: /* phaddw */ | |
7545 | case 0x660f3802: /* phaddd */ | |
7546 | case 0x660f3803: /* phaddsw */ | |
7547 | case 0x660f3804: /* pmaddubsw */ | |
7548 | case 0x660f3805: /* phsubw */ | |
7549 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 7550 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
7551 | case 0x660f3808: /* psignb */ |
7552 | case 0x660f3809: /* psignw */ | |
7553 | case 0x660f380a: /* psignd */ | |
7554 | case 0x660f380b: /* pmulhrsw */ | |
7555 | case 0x660f3810: /* pblendvb */ | |
7556 | case 0x660f3814: /* blendvps */ | |
7557 | case 0x660f3815: /* blendvpd */ | |
7558 | case 0x660f381c: /* pabsb */ | |
7559 | case 0x660f381d: /* pabsw */ | |
7560 | case 0x660f381e: /* pabsd */ | |
7561 | case 0x660f3820: /* pmovsxbw */ | |
7562 | case 0x660f3821: /* pmovsxbd */ | |
7563 | case 0x660f3822: /* pmovsxbq */ | |
7564 | case 0x660f3823: /* pmovsxwd */ | |
7565 | case 0x660f3824: /* pmovsxwq */ | |
7566 | case 0x660f3825: /* pmovsxdq */ | |
7567 | case 0x660f3828: /* pmuldq */ | |
7568 | case 0x660f3829: /* pcmpeqq */ | |
7569 | case 0x660f382a: /* movntdqa */ | |
7570 | case 0x660f3a08: /* roundps */ | |
7571 | case 0x660f3a09: /* roundpd */ | |
7572 | case 0x660f3a0a: /* roundss */ | |
7573 | case 0x660f3a0b: /* roundsd */ | |
7574 | case 0x660f3a0c: /* blendps */ | |
7575 | case 0x660f3a0d: /* blendpd */ | |
7576 | case 0x660f3a0e: /* pblendw */ | |
7577 | case 0x660f3a0f: /* palignr */ | |
7578 | case 0x660f3a20: /* pinsrb */ | |
7579 | case 0x660f3a21: /* insertps */ | |
7580 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7581 | case 0x660f3a40: /* dpps */ | |
7582 | case 0x660f3a41: /* dppd */ | |
7583 | case 0x660f3a42: /* mpsadbw */ | |
7584 | case 0x660f3a60: /* pcmpestrm */ | |
7585 | case 0x660f3a61: /* pcmpestri */ | |
7586 | case 0x660f3a62: /* pcmpistrm */ | |
7587 | case 0x660f3a63: /* pcmpistri */ | |
7588 | case 0x0f51: /* sqrtps */ | |
7589 | case 0x660f51: /* sqrtpd */ | |
7590 | case 0xf20f51: /* sqrtsd */ | |
7591 | case 0xf30f51: /* sqrtss */ | |
7592 | case 0x0f52: /* rsqrtps */ | |
7593 | case 0xf30f52: /* rsqrtss */ | |
7594 | case 0x0f53: /* rcpps */ | |
7595 | case 0xf30f53: /* rcpss */ | |
7596 | case 0x0f54: /* andps */ | |
7597 | case 0x660f54: /* andpd */ | |
7598 | case 0x0f55: /* andnps */ | |
7599 | case 0x660f55: /* andnpd */ | |
7600 | case 0x0f56: /* orps */ | |
7601 | case 0x660f56: /* orpd */ | |
7602 | case 0x0f57: /* xorps */ | |
7603 | case 0x660f57: /* xorpd */ | |
7604 | case 0x0f58: /* addps */ | |
7605 | case 0x660f58: /* addpd */ | |
7606 | case 0xf20f58: /* addsd */ | |
7607 | case 0xf30f58: /* addss */ | |
7608 | case 0x0f59: /* mulps */ | |
7609 | case 0x660f59: /* mulpd */ | |
7610 | case 0xf20f59: /* mulsd */ | |
7611 | case 0xf30f59: /* mulss */ | |
7612 | case 0x0f5a: /* cvtps2pd */ | |
7613 | case 0x660f5a: /* cvtpd2ps */ | |
7614 | case 0xf20f5a: /* cvtsd2ss */ | |
7615 | case 0xf30f5a: /* cvtss2sd */ | |
7616 | case 0x0f5b: /* cvtdq2ps */ | |
7617 | case 0x660f5b: /* cvtps2dq */ | |
7618 | case 0xf30f5b: /* cvttps2dq */ | |
7619 | case 0x0f5c: /* subps */ | |
7620 | case 0x660f5c: /* subpd */ | |
7621 | case 0xf20f5c: /* subsd */ | |
7622 | case 0xf30f5c: /* subss */ | |
7623 | case 0x0f5d: /* minps */ | |
7624 | case 0x660f5d: /* minpd */ | |
7625 | case 0xf20f5d: /* minsd */ | |
7626 | case 0xf30f5d: /* minss */ | |
7627 | case 0x0f5e: /* divps */ | |
7628 | case 0x660f5e: /* divpd */ | |
7629 | case 0xf20f5e: /* divsd */ | |
7630 | case 0xf30f5e: /* divss */ | |
7631 | case 0x0f5f: /* maxps */ | |
7632 | case 0x660f5f: /* maxpd */ | |
7633 | case 0xf20f5f: /* maxsd */ | |
7634 | case 0xf30f5f: /* maxss */ | |
7635 | case 0x660f60: /* punpcklbw */ | |
7636 | case 0x660f61: /* punpcklwd */ | |
7637 | case 0x660f62: /* punpckldq */ | |
7638 | case 0x660f63: /* packsswb */ | |
7639 | case 0x660f64: /* pcmpgtb */ | |
7640 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 7641 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
7642 | case 0x660f67: /* packuswb */ |
7643 | case 0x660f68: /* punpckhbw */ | |
7644 | case 0x660f69: /* punpckhwd */ | |
7645 | case 0x660f6a: /* punpckhdq */ | |
7646 | case 0x660f6b: /* packssdw */ | |
7647 | case 0x660f6c: /* punpcklqdq */ | |
7648 | case 0x660f6d: /* punpckhqdq */ | |
7649 | case 0x660f6e: /* movd */ | |
7650 | case 0x660f6f: /* movdqa */ | |
7651 | case 0xf30f6f: /* movdqu */ | |
7652 | case 0x660f70: /* pshufd */ | |
7653 | case 0xf20f70: /* pshuflw */ | |
7654 | case 0xf30f70: /* pshufhw */ | |
7655 | case 0x660f74: /* pcmpeqb */ | |
7656 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 7657 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
7658 | case 0x660f7c: /* haddpd */ |
7659 | case 0xf20f7c: /* haddps */ | |
7660 | case 0x660f7d: /* hsubpd */ | |
7661 | case 0xf20f7d: /* hsubps */ | |
7662 | case 0xf30f7e: /* movq */ | |
7663 | case 0x0fc2: /* cmpps */ | |
7664 | case 0x660fc2: /* cmppd */ | |
7665 | case 0xf20fc2: /* cmpsd */ | |
7666 | case 0xf30fc2: /* cmpss */ | |
7667 | case 0x660fc4: /* pinsrw */ | |
7668 | case 0x0fc6: /* shufps */ | |
7669 | case 0x660fc6: /* shufpd */ | |
7670 | case 0x660fd0: /* addsubpd */ | |
7671 | case 0xf20fd0: /* addsubps */ | |
7672 | case 0x660fd1: /* psrlw */ | |
7673 | case 0x660fd2: /* psrld */ | |
7674 | case 0x660fd3: /* psrlq */ | |
7675 | case 0x660fd4: /* paddq */ | |
7676 | case 0x660fd5: /* pmullw */ | |
7677 | case 0xf30fd6: /* movq2dq */ | |
7678 | case 0x660fd8: /* psubusb */ | |
7679 | case 0x660fd9: /* psubusw */ | |
7680 | case 0x660fda: /* pminub */ | |
7681 | case 0x660fdb: /* pand */ | |
7682 | case 0x660fdc: /* paddusb */ | |
7683 | case 0x660fdd: /* paddusw */ | |
7684 | case 0x660fde: /* pmaxub */ | |
7685 | case 0x660fdf: /* pandn */ | |
7686 | case 0x660fe0: /* pavgb */ | |
7687 | case 0x660fe1: /* psraw */ | |
7688 | case 0x660fe2: /* psrad */ | |
7689 | case 0x660fe3: /* pavgw */ | |
7690 | case 0x660fe4: /* pmulhuw */ | |
7691 | case 0x660fe5: /* pmulhw */ | |
7692 | case 0x660fe6: /* cvttpd2dq */ | |
7693 | case 0xf20fe6: /* cvtpd2dq */ | |
7694 | case 0xf30fe6: /* cvtdq2pd */ | |
7695 | case 0x660fe8: /* psubsb */ | |
7696 | case 0x660fe9: /* psubsw */ | |
7697 | case 0x660fea: /* pminsw */ | |
7698 | case 0x660feb: /* por */ | |
7699 | case 0x660fec: /* paddsb */ | |
7700 | case 0x660fed: /* paddsw */ | |
7701 | case 0x660fee: /* pmaxsw */ | |
7702 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7703 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7704 | case 0x660ff1: /* psllw */ |
7705 | case 0x660ff2: /* pslld */ | |
7706 | case 0x660ff3: /* psllq */ | |
7707 | case 0x660ff4: /* pmuludq */ | |
7708 | case 0x660ff5: /* pmaddwd */ | |
7709 | case 0x660ff6: /* psadbw */ | |
7710 | case 0x660ff8: /* psubb */ | |
7711 | case 0x660ff9: /* psubw */ | |
56d2815c | 7712 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7713 | case 0x660ffb: /* psubq */ |
7714 | case 0x660ffc: /* paddb */ | |
7715 | case 0x660ffd: /* paddw */ | |
56d2815c | 7716 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7717 | if (i386_record_modrm (&ir)) |
7718 | return -1; | |
7719 | ir.reg |= rex_r; | |
c131fcee | 7720 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a | 7721 | goto no_support; |
25ea693b MM |
7722 | record_full_arch_list_add_reg (ir.regcache, |
7723 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
a3c4230a | 7724 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
25ea693b | 7725 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7726 | break; |
7727 | ||
7728 | case 0x0f11: /* movups */ | |
7729 | case 0x660f11: /* movupd */ | |
7730 | case 0xf30f11: /* movss */ | |
7731 | case 0xf20f11: /* movsd */ | |
7732 | case 0x0f13: /* movlps */ | |
7733 | case 0x660f13: /* movlpd */ | |
7734 | case 0x0f17: /* movhps */ | |
7735 | case 0x660f17: /* movhpd */ | |
7736 | case 0x0f29: /* movaps */ | |
7737 | case 0x660f29: /* movapd */ | |
7738 | case 0x660f3a14: /* pextrb */ | |
7739 | case 0x660f3a15: /* pextrw */ | |
7740 | case 0x660f3a16: /* pextrd pextrq */ | |
7741 | case 0x660f3a17: /* extractps */ | |
7742 | case 0x660f7f: /* movdqa */ | |
7743 | case 0xf30f7f: /* movdqu */ | |
7744 | if (i386_record_modrm (&ir)) | |
7745 | return -1; | |
7746 | if (ir.mod == 3) | |
7747 | { | |
7748 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7749 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7750 | goto no_support; | |
7751 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7752 | if (!i386_xmm_regnum_p (gdbarch, |
7753 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7754 | goto no_support; |
25ea693b MM |
7755 | record_full_arch_list_add_reg (ir.regcache, |
7756 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7757 | } |
7758 | else | |
7759 | { | |
7760 | switch (opcode) | |
7761 | { | |
7762 | case 0x660f3a14: | |
7763 | ir.ot = OT_BYTE; | |
7764 | break; | |
7765 | case 0x660f3a15: | |
7766 | ir.ot = OT_WORD; | |
7767 | break; | |
7768 | case 0x660f3a16: | |
7769 | ir.ot = OT_LONG; | |
7770 | break; | |
7771 | case 0x660f3a17: | |
7772 | ir.ot = OT_QUAD; | |
7773 | break; | |
7774 | default: | |
7775 | ir.ot = OT_DQUAD; | |
7776 | break; | |
7777 | } | |
7778 | if (i386_record_lea_modrm (&ir)) | |
7779 | return -1; | |
7780 | } | |
7781 | break; | |
7782 | ||
7783 | case 0x0f2b: /* movntps */ | |
7784 | case 0x660f2b: /* movntpd */ | |
7785 | case 0x0fe7: /* movntq */ | |
7786 | case 0x660fe7: /* movntdq */ | |
7787 | if (ir.mod == 3) | |
7788 | goto no_support; | |
7789 | if (opcode == 0x0fe7) | |
7790 | ir.ot = OT_QUAD; | |
7791 | else | |
7792 | ir.ot = OT_DQUAD; | |
7793 | if (i386_record_lea_modrm (&ir)) | |
7794 | return -1; | |
7795 | break; | |
7796 | ||
7797 | case 0xf30f2c: /* cvttss2si */ | |
7798 | case 0xf20f2c: /* cvttsd2si */ | |
7799 | case 0xf30f2d: /* cvtss2si */ | |
7800 | case 0xf20f2d: /* cvtsd2si */ | |
7801 | case 0xf20f38f0: /* crc32 */ | |
7802 | case 0xf20f38f1: /* crc32 */ | |
7803 | case 0x0f50: /* movmskps */ | |
7804 | case 0x660f50: /* movmskpd */ | |
7805 | case 0x0fc5: /* pextrw */ | |
7806 | case 0x660fc5: /* pextrw */ | |
7807 | case 0x0fd7: /* pmovmskb */ | |
7808 | case 0x660fd7: /* pmovmskb */ | |
25ea693b | 7809 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
a3c4230a HZ |
7810 | break; |
7811 | ||
7812 | case 0x0f3800: /* pshufb */ | |
7813 | case 0x0f3801: /* phaddw */ | |
7814 | case 0x0f3802: /* phaddd */ | |
7815 | case 0x0f3803: /* phaddsw */ | |
7816 | case 0x0f3804: /* pmaddubsw */ | |
7817 | case 0x0f3805: /* phsubw */ | |
7818 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7819 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7820 | case 0x0f3808: /* psignb */ |
7821 | case 0x0f3809: /* psignw */ | |
7822 | case 0x0f380a: /* psignd */ | |
7823 | case 0x0f380b: /* pmulhrsw */ | |
7824 | case 0x0f381c: /* pabsb */ | |
7825 | case 0x0f381d: /* pabsw */ | |
7826 | case 0x0f381e: /* pabsd */ | |
7827 | case 0x0f382b: /* packusdw */ | |
7828 | case 0x0f3830: /* pmovzxbw */ | |
7829 | case 0x0f3831: /* pmovzxbd */ | |
7830 | case 0x0f3832: /* pmovzxbq */ | |
7831 | case 0x0f3833: /* pmovzxwd */ | |
7832 | case 0x0f3834: /* pmovzxwq */ | |
7833 | case 0x0f3835: /* pmovzxdq */ | |
7834 | case 0x0f3837: /* pcmpgtq */ | |
7835 | case 0x0f3838: /* pminsb */ | |
7836 | case 0x0f3839: /* pminsd */ | |
7837 | case 0x0f383a: /* pminuw */ | |
7838 | case 0x0f383b: /* pminud */ | |
7839 | case 0x0f383c: /* pmaxsb */ | |
7840 | case 0x0f383d: /* pmaxsd */ | |
7841 | case 0x0f383e: /* pmaxuw */ | |
7842 | case 0x0f383f: /* pmaxud */ | |
7843 | case 0x0f3840: /* pmulld */ | |
7844 | case 0x0f3841: /* phminposuw */ | |
7845 | case 0x0f3a0f: /* palignr */ | |
7846 | case 0x0f60: /* punpcklbw */ | |
7847 | case 0x0f61: /* punpcklwd */ | |
7848 | case 0x0f62: /* punpckldq */ | |
7849 | case 0x0f63: /* packsswb */ | |
7850 | case 0x0f64: /* pcmpgtb */ | |
7851 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7852 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7853 | case 0x0f67: /* packuswb */ |
7854 | case 0x0f68: /* punpckhbw */ | |
7855 | case 0x0f69: /* punpckhwd */ | |
7856 | case 0x0f6a: /* punpckhdq */ | |
7857 | case 0x0f6b: /* packssdw */ | |
7858 | case 0x0f6e: /* movd */ | |
7859 | case 0x0f6f: /* movq */ | |
7860 | case 0x0f70: /* pshufw */ | |
7861 | case 0x0f74: /* pcmpeqb */ | |
7862 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7863 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7864 | case 0x0fc4: /* pinsrw */ |
7865 | case 0x0fd1: /* psrlw */ | |
7866 | case 0x0fd2: /* psrld */ | |
7867 | case 0x0fd3: /* psrlq */ | |
7868 | case 0x0fd4: /* paddq */ | |
7869 | case 0x0fd5: /* pmullw */ | |
7870 | case 0xf20fd6: /* movdq2q */ | |
7871 | case 0x0fd8: /* psubusb */ | |
7872 | case 0x0fd9: /* psubusw */ | |
7873 | case 0x0fda: /* pminub */ | |
7874 | case 0x0fdb: /* pand */ | |
7875 | case 0x0fdc: /* paddusb */ | |
7876 | case 0x0fdd: /* paddusw */ | |
7877 | case 0x0fde: /* pmaxub */ | |
7878 | case 0x0fdf: /* pandn */ | |
7879 | case 0x0fe0: /* pavgb */ | |
7880 | case 0x0fe1: /* psraw */ | |
7881 | case 0x0fe2: /* psrad */ | |
7882 | case 0x0fe3: /* pavgw */ | |
7883 | case 0x0fe4: /* pmulhuw */ | |
7884 | case 0x0fe5: /* pmulhw */ | |
7885 | case 0x0fe8: /* psubsb */ | |
7886 | case 0x0fe9: /* psubsw */ | |
7887 | case 0x0fea: /* pminsw */ | |
7888 | case 0x0feb: /* por */ | |
7889 | case 0x0fec: /* paddsb */ | |
7890 | case 0x0fed: /* paddsw */ | |
7891 | case 0x0fee: /* pmaxsw */ | |
7892 | case 0x0fef: /* pxor */ | |
7893 | case 0x0ff1: /* psllw */ | |
7894 | case 0x0ff2: /* pslld */ | |
7895 | case 0x0ff3: /* psllq */ | |
7896 | case 0x0ff4: /* pmuludq */ | |
7897 | case 0x0ff5: /* pmaddwd */ | |
7898 | case 0x0ff6: /* psadbw */ | |
7899 | case 0x0ff8: /* psubb */ | |
7900 | case 0x0ff9: /* psubw */ | |
56d2815c | 7901 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7902 | case 0x0ffb: /* psubq */ |
7903 | case 0x0ffc: /* paddb */ | |
7904 | case 0x0ffd: /* paddw */ | |
56d2815c | 7905 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7906 | if (i386_record_modrm (&ir)) |
7907 | return -1; | |
7908 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7909 | goto no_support; | |
25ea693b MM |
7910 | record_full_arch_list_add_reg (ir.regcache, |
7911 | I387_MM0_REGNUM (tdep) + ir.reg); | |
a3c4230a HZ |
7912 | break; |
7913 | ||
7914 | case 0x0f71: /* psllw */ | |
7915 | case 0x0f72: /* pslld */ | |
7916 | case 0x0f73: /* psllq */ | |
7917 | if (i386_record_modrm (&ir)) | |
7918 | return -1; | |
7919 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7920 | goto no_support; | |
25ea693b MM |
7921 | record_full_arch_list_add_reg (ir.regcache, |
7922 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7923 | break; |
7924 | ||
7925 | case 0x660f71: /* psllw */ | |
7926 | case 0x660f72: /* pslld */ | |
7927 | case 0x660f73: /* psllq */ | |
7928 | if (i386_record_modrm (&ir)) | |
7929 | return -1; | |
7930 | ir.rm |= ir.rex_b; | |
c131fcee | 7931 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a | 7932 | goto no_support; |
25ea693b MM |
7933 | record_full_arch_list_add_reg (ir.regcache, |
7934 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7935 | break; |
7936 | ||
7937 | case 0x0f7e: /* movd */ | |
7938 | case 0x660f7e: /* movd */ | |
7939 | if (i386_record_modrm (&ir)) | |
7940 | return -1; | |
7941 | if (ir.mod == 3) | |
25ea693b | 7942 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
a3c4230a HZ |
7943 | else |
7944 | { | |
7945 | if (ir.dflag == 2) | |
7946 | ir.ot = OT_QUAD; | |
7947 | else | |
7948 | ir.ot = OT_LONG; | |
7949 | if (i386_record_lea_modrm (&ir)) | |
7950 | return -1; | |
7951 | } | |
7952 | break; | |
7953 | ||
7954 | case 0x0f7f: /* movq */ | |
7955 | if (i386_record_modrm (&ir)) | |
7956 | return -1; | |
7957 | if (ir.mod == 3) | |
7958 | { | |
7959 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7960 | goto no_support; | |
25ea693b MM |
7961 | record_full_arch_list_add_reg (ir.regcache, |
7962 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7963 | } |
7964 | else | |
7965 | { | |
7966 | ir.ot = OT_QUAD; | |
7967 | if (i386_record_lea_modrm (&ir)) | |
7968 | return -1; | |
7969 | } | |
7970 | break; | |
7971 | ||
7972 | case 0xf30fb8: /* popcnt */ | |
7973 | if (i386_record_modrm (&ir)) | |
7974 | return -1; | |
25ea693b MM |
7975 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7976 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
a3c4230a HZ |
7977 | break; |
7978 | ||
7979 | case 0x660fd6: /* movq */ | |
7980 | if (i386_record_modrm (&ir)) | |
7981 | return -1; | |
7982 | if (ir.mod == 3) | |
7983 | { | |
7984 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7985 | if (!i386_xmm_regnum_p (gdbarch, |
7986 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7987 | goto no_support; |
25ea693b MM |
7988 | record_full_arch_list_add_reg (ir.regcache, |
7989 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7990 | } |
7991 | else | |
7992 | { | |
7993 | ir.ot = OT_QUAD; | |
7994 | if (i386_record_lea_modrm (&ir)) | |
7995 | return -1; | |
7996 | } | |
7997 | break; | |
7998 | ||
7999 | case 0x660f3817: /* ptest */ | |
8000 | case 0x0f2e: /* ucomiss */ | |
8001 | case 0x660f2e: /* ucomisd */ | |
8002 | case 0x0f2f: /* comiss */ | |
8003 | case 0x660f2f: /* comisd */ | |
25ea693b | 8004 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
8005 | break; |
8006 | ||
8007 | case 0x0ff7: /* maskmovq */ | |
8008 | regcache_raw_read_unsigned (ir.regcache, | |
8009 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8010 | &addr); | |
25ea693b | 8011 | if (record_full_arch_list_add_mem (addr, 64)) |
a3c4230a HZ |
8012 | return -1; |
8013 | break; | |
8014 | ||
8015 | case 0x660ff7: /* maskmovdqu */ | |
8016 | regcache_raw_read_unsigned (ir.regcache, | |
8017 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8018 | &addr); | |
25ea693b | 8019 | if (record_full_arch_list_add_mem (addr, 128)) |
a3c4230a HZ |
8020 | return -1; |
8021 | break; | |
8022 | ||
8023 | default: | |
8024 | goto no_support; | |
8025 | break; | |
8026 | } | |
8027 | break; | |
7ad10968 HZ |
8028 | |
8029 | default: | |
7ad10968 HZ |
8030 | goto no_support; |
8031 | break; | |
8032 | } | |
8033 | ||
cf648174 | 8034 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
8035 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
8036 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
8037 | return -1; |
8038 | ||
8039 | return 0; | |
8040 | ||
01fe1b41 | 8041 | no_support: |
a3c4230a HZ |
8042 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
8043 | "at address %s.\n"), | |
8044 | (unsigned int) (opcode), | |
8045 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
8046 | return -1; |
8047 | } | |
8048 | ||
cf648174 HZ |
8049 | static const int i386_record_regmap[] = |
8050 | { | |
8051 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
8052 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
8053 | 0, 0, 0, 0, 0, 0, 0, 0, | |
8054 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
8055 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
8056 | }; | |
8057 | ||
7a697b8d | 8058 | /* Check that the given address appears suitable for a fast |
405f8e94 | 8059 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
8060 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
8061 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
8062 | middle of the tracepoint jump. On x86, it may be possible to use |
8063 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
8064 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
8065 | of instruction to replace, and 0 if not, plus an explanatory |
8066 | string. */ | |
8067 | ||
8068 | static int | |
8069 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
8070 | CORE_ADDR addr, int *isize, char **msg) | |
8071 | { | |
8072 | int len, jumplen; | |
8073 | static struct ui_file *gdb_null = NULL; | |
8074 | ||
405f8e94 SS |
8075 | /* Ask the target for the minimum instruction length supported. */ |
8076 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
8077 | ||
8078 | if (jumplen < 0) | |
8079 | { | |
8080 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
8081 | operation, assume that fast tracepoints will always be implemented | |
8082 | using 4-byte relative jumps on both x86 and x86-64. */ | |
8083 | jumplen = 5; | |
8084 | } | |
8085 | else if (jumplen == 0) | |
8086 | { | |
8087 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
8088 | returns zero, then the IPA has not loaded yet. In this case, | |
8089 | we optimistically assume that truncated 2-byte relative jumps | |
8090 | will be available on x86, and compensate later if this assumption | |
8091 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
8092 | jumps will always be used. */ | |
8093 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
8094 | } | |
7a697b8d SS |
8095 | |
8096 | /* Dummy file descriptor for the disassembler. */ | |
8097 | if (!gdb_null) | |
8098 | gdb_null = ui_file_new (); | |
8099 | ||
8100 | /* Check for fit. */ | |
8101 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
405f8e94 SS |
8102 | if (isize) |
8103 | *isize = len; | |
8104 | ||
7a697b8d SS |
8105 | if (len < jumplen) |
8106 | { | |
8107 | /* Return a bit of target-specific detail to add to the caller's | |
8108 | generic failure message. */ | |
8109 | if (msg) | |
1777feb0 MS |
8110 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
8111 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
8112 | len, jumplen); |
8113 | return 0; | |
8114 | } | |
405f8e94 SS |
8115 | else |
8116 | { | |
8117 | if (msg) | |
8118 | *msg = NULL; | |
8119 | return 1; | |
8120 | } | |
7a697b8d SS |
8121 | } |
8122 | ||
90884b2b L |
8123 | static int |
8124 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
8125 | struct tdesc_arch_data *tdesc_data) | |
8126 | { | |
8127 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 8128 | const struct tdesc_feature *feature_core; |
01f9f808 MS |
8129 | |
8130 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, | |
8131 | *feature_avx512; | |
90884b2b L |
8132 | int i, num_regs, valid_p; |
8133 | ||
8134 | if (! tdesc_has_registers (tdesc)) | |
8135 | return 0; | |
8136 | ||
8137 | /* Get core registers. */ | |
8138 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
8139 | if (feature_core == NULL) |
8140 | return 0; | |
90884b2b L |
8141 | |
8142 | /* Get SSE registers. */ | |
c131fcee | 8143 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 8144 | |
c131fcee L |
8145 | /* Try AVX registers. */ |
8146 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
8147 | ||
1dbcd68c WT |
8148 | /* Try MPX registers. */ |
8149 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
8150 | ||
01f9f808 MS |
8151 | /* Try AVX512 registers. */ |
8152 | feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); | |
8153 | ||
90884b2b L |
8154 | valid_p = 1; |
8155 | ||
c131fcee | 8156 | /* The XCR0 bits. */ |
01f9f808 MS |
8157 | if (feature_avx512) |
8158 | { | |
8159 | /* AVX512 register description requires AVX register description. */ | |
8160 | if (!feature_avx) | |
8161 | return 0; | |
8162 | ||
df7e5265 | 8163 | tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK; |
01f9f808 MS |
8164 | |
8165 | /* It may have been set by OSABI initialization function. */ | |
8166 | if (tdep->k0_regnum < 0) | |
8167 | { | |
8168 | tdep->k_register_names = i386_k_names; | |
8169 | tdep->k0_regnum = I386_K0_REGNUM; | |
8170 | } | |
8171 | ||
8172 | for (i = 0; i < I387_NUM_K_REGS; i++) | |
8173 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8174 | tdep->k0_regnum + i, | |
8175 | i386_k_names[i]); | |
8176 | ||
8177 | if (tdep->num_zmm_regs == 0) | |
8178 | { | |
8179 | tdep->zmmh_register_names = i386_zmmh_names; | |
8180 | tdep->num_zmm_regs = 8; | |
8181 | tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; | |
8182 | } | |
8183 | ||
8184 | for (i = 0; i < tdep->num_zmm_regs; i++) | |
8185 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8186 | tdep->zmm0h_regnum + i, | |
8187 | tdep->zmmh_register_names[i]); | |
8188 | ||
8189 | for (i = 0; i < tdep->num_xmm_avx512_regs; i++) | |
8190 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8191 | tdep->xmm16_regnum + i, | |
8192 | tdep->xmm_avx512_register_names[i]); | |
8193 | ||
8194 | for (i = 0; i < tdep->num_ymm_avx512_regs; i++) | |
8195 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8196 | tdep->ymm16h_regnum + i, | |
8197 | tdep->ymm16h_register_names[i]); | |
8198 | } | |
c131fcee L |
8199 | if (feature_avx) |
8200 | { | |
3a13a53b L |
8201 | /* AVX register description requires SSE register description. */ |
8202 | if (!feature_sse) | |
8203 | return 0; | |
8204 | ||
01f9f808 | 8205 | if (!feature_avx512) |
df7e5265 | 8206 | tdep->xcr0 = X86_XSTATE_AVX_MASK; |
c131fcee L |
8207 | |
8208 | /* It may have been set by OSABI initialization function. */ | |
8209 | if (tdep->num_ymm_regs == 0) | |
8210 | { | |
8211 | tdep->ymmh_register_names = i386_ymmh_names; | |
8212 | tdep->num_ymm_regs = 8; | |
8213 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
8214 | } | |
8215 | ||
8216 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
8217 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
8218 | tdep->ymm0h_regnum + i, | |
8219 | tdep->ymmh_register_names[i]); | |
8220 | } | |
3a13a53b | 8221 | else if (feature_sse) |
df7e5265 | 8222 | tdep->xcr0 = X86_XSTATE_SSE_MASK; |
3a13a53b L |
8223 | else |
8224 | { | |
df7e5265 | 8225 | tdep->xcr0 = X86_XSTATE_X87_MASK; |
3a13a53b L |
8226 | tdep->num_xmm_regs = 0; |
8227 | } | |
c131fcee | 8228 | |
90884b2b L |
8229 | num_regs = tdep->num_core_regs; |
8230 | for (i = 0; i < num_regs; i++) | |
8231 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
8232 | tdep->register_names[i]); | |
8233 | ||
3a13a53b L |
8234 | if (feature_sse) |
8235 | { | |
8236 | /* Need to include %mxcsr, so add one. */ | |
8237 | num_regs += tdep->num_xmm_regs + 1; | |
8238 | for (; i < num_regs; i++) | |
8239 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
8240 | tdep->register_names[i]); | |
8241 | } | |
90884b2b | 8242 | |
1dbcd68c WT |
8243 | if (feature_mpx) |
8244 | { | |
df7e5265 | 8245 | tdep->xcr0 |= X86_XSTATE_MPX_MASK; |
1dbcd68c WT |
8246 | |
8247 | if (tdep->bnd0r_regnum < 0) | |
8248 | { | |
8249 | tdep->mpx_register_names = i386_mpx_names; | |
8250 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
8251 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
8252 | } | |
8253 | ||
8254 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
8255 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
8256 | I387_BND0R_REGNUM (tdep) + i, | |
8257 | tdep->mpx_register_names[i]); | |
8258 | } | |
8259 | ||
90884b2b L |
8260 | return valid_p; |
8261 | } | |
8262 | ||
7ad10968 HZ |
8263 | \f |
8264 | static struct gdbarch * | |
8265 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8266 | { | |
8267 | struct gdbarch_tdep *tdep; | |
8268 | struct gdbarch *gdbarch; | |
90884b2b L |
8269 | struct tdesc_arch_data *tdesc_data; |
8270 | const struct target_desc *tdesc; | |
1ba53b71 | 8271 | int mm0_regnum; |
c131fcee | 8272 | int ymm0_regnum; |
1dbcd68c WT |
8273 | int bnd0_regnum; |
8274 | int num_bnd_cooked; | |
01f9f808 MS |
8275 | int k0_regnum; |
8276 | int zmm0_regnum; | |
7ad10968 HZ |
8277 | |
8278 | /* If there is already a candidate, use it. */ | |
8279 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
8280 | if (arches != NULL) | |
8281 | return arches->gdbarch; | |
8282 | ||
8283 | /* Allocate space for the new architecture. */ | |
fc270c35 | 8284 | tdep = XCNEW (struct gdbarch_tdep); |
7ad10968 HZ |
8285 | gdbarch = gdbarch_alloc (&info, tdep); |
8286 | ||
8287 | /* General-purpose registers. */ | |
7ad10968 HZ |
8288 | tdep->gregset_reg_offset = NULL; |
8289 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
8290 | tdep->sizeof_gregset = 0; | |
8291 | ||
8292 | /* Floating-point registers. */ | |
7ad10968 HZ |
8293 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
8294 | ||
8295 | /* The default settings include the FPU registers, the MMX registers | |
8296 | and the SSE registers. This can be overridden for a specific ABI | |
8297 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
8298 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 8299 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
8300 | |
8301 | tdep->st0_regnum = I386_ST0_REGNUM; | |
8302 | ||
7ad10968 HZ |
8303 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
8304 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
8305 | ||
8306 | tdep->jb_pc_offset = -1; | |
8307 | tdep->struct_return = pcc_struct_return; | |
8308 | tdep->sigtramp_start = 0; | |
8309 | tdep->sigtramp_end = 0; | |
8310 | tdep->sigtramp_p = i386_sigtramp_p; | |
8311 | tdep->sigcontext_addr = NULL; | |
8312 | tdep->sc_reg_offset = NULL; | |
8313 | tdep->sc_pc_offset = -1; | |
8314 | tdep->sc_sp_offset = -1; | |
8315 | ||
c131fcee L |
8316 | tdep->xsave_xcr0_offset = -1; |
8317 | ||
cf648174 HZ |
8318 | tdep->record_regmap = i386_record_regmap; |
8319 | ||
205c306f DM |
8320 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
8321 | ||
7ad10968 HZ |
8322 | /* The format used for `long double' on almost all i386 targets is |
8323 | the i387 extended floating-point format. In fact, of all targets | |
8324 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
8325 | on having a `long double' that's not `long' at all. */ | |
8326 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
8327 | ||
8328 | /* Although the i387 extended floating-point has only 80 significant | |
8329 | bits, a `long double' actually takes up 96, probably to enforce | |
8330 | alignment. */ | |
8331 | set_gdbarch_long_double_bit (gdbarch, 96); | |
8332 | ||
7ad10968 HZ |
8333 | /* Register numbers of various important registers. */ |
8334 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
8335 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
8336 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
8337 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
8338 | ||
8339 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
8340 | numbering schemes on the i386: dbx and SVR4. These schemes | |
8341 | differ in how they number %ebp, %esp, %eflags, and the | |
8342 | floating-point registers, and are implemented by the arrays | |
8343 | dbx_register_map[] and svr4_dbx_register_map in | |
8344 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
8345 | gcc/config/i386.c, which it designates as the "default" register | |
8346 | map used in 64bit mode. This last register numbering scheme is | |
8347 | implemented in dbx64_register_map, and is used for AMD64; see | |
8348 | amd64-tdep.c. | |
8349 | ||
8350 | Currently, each GCC i386 target always uses the same register | |
8351 | numbering scheme across all its supported debugging formats | |
8352 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
8353 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
8354 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
8355 | respective config header in a manner independent of the requested | |
8356 | output debugging format. | |
8357 | ||
8358 | This does not match the arrangement below, which presumes that | |
8359 | the SDB and stabs numbering schemes differ from the DWARF and | |
8360 | DWARF 2 ones. The reason for this arrangement is that it is | |
8361 | likely to get the numbering scheme for the target's | |
8362 | default/native debug format right. For targets where GCC is the | |
8363 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
8364 | targets where the native toolchain uses a different numbering | |
8365 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
8366 | the defaults below will have to be overridden, like | |
8367 | i386_elf_init_abi() does. */ | |
8368 | ||
8369 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
8370 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8371 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8372 | ||
8373 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
8374 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8375 | ||
8376 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
8377 | be in use on any of the supported i386 targets. */ | |
8378 | ||
8379 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
8380 | ||
8381 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
8382 | ||
8383 | /* Call dummy code. */ | |
a9b8d892 JK |
8384 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8385 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 8386 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 8387 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
8388 | |
8389 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
8390 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
8391 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
8392 | ||
8393 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
8394 | ||
8395 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
8396 | ||
8397 | /* Stack grows downward. */ | |
8398 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8399 | ||
8400 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
8401 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
8402 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
8403 | ||
8404 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
8405 | ||
7ad10968 HZ |
8406 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
8407 | ||
8408 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
8409 | ||
8410 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
8411 | ||
8412 | /* Add the i386 register groups. */ | |
8413 | i386_add_reggroups (gdbarch); | |
90884b2b | 8414 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 8415 | |
143985b7 AF |
8416 | /* Helper for function argument information. */ |
8417 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
8418 | ||
06da04c6 | 8419 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
8420 | appended to the list first, so that it supercedes the DWARF |
8421 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
8422 | currently fails). */ |
8423 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
8424 | ||
8425 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 8426 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 8427 | CFI info will be used if it is available. */ |
10458914 | 8428 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 8429 | |
acd5c798 | 8430 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 8431 | |
1ba53b71 | 8432 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
8433 | set_gdbarch_pseudo_register_read_value (gdbarch, |
8434 | i386_pseudo_register_read_value); | |
90884b2b L |
8435 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
8436 | ||
8437 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
8438 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
8439 | ||
c131fcee L |
8440 | /* Override the normal target description method to make the AVX |
8441 | upper halves anonymous. */ | |
8442 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
8443 | ||
8444 | /* Even though the default ABI only includes general-purpose registers, | |
8445 | floating-point registers and the SSE registers, we have to leave a | |
01f9f808 MS |
8446 | gap for the upper AVX, MPX and AVX512 registers. */ |
8447 | set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS); | |
90884b2b L |
8448 | |
8449 | /* Get the x86 target description from INFO. */ | |
8450 | tdesc = info.target_desc; | |
8451 | if (! tdesc_has_registers (tdesc)) | |
8452 | tdesc = tdesc_i386; | |
8453 | tdep->tdesc = tdesc; | |
8454 | ||
8455 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
8456 | tdep->register_names = i386_register_names; | |
8457 | ||
c131fcee L |
8458 | /* No upper YMM registers. */ |
8459 | tdep->ymmh_register_names = NULL; | |
8460 | tdep->ymm0h_regnum = -1; | |
8461 | ||
01f9f808 MS |
8462 | /* No upper ZMM registers. */ |
8463 | tdep->zmmh_register_names = NULL; | |
8464 | tdep->zmm0h_regnum = -1; | |
8465 | ||
8466 | /* No high XMM registers. */ | |
8467 | tdep->xmm_avx512_register_names = NULL; | |
8468 | tdep->xmm16_regnum = -1; | |
8469 | ||
8470 | /* No upper YMM16-31 registers. */ | |
8471 | tdep->ymm16h_register_names = NULL; | |
8472 | tdep->ymm16h_regnum = -1; | |
8473 | ||
1ba53b71 L |
8474 | tdep->num_byte_regs = 8; |
8475 | tdep->num_word_regs = 8; | |
8476 | tdep->num_dword_regs = 0; | |
8477 | tdep->num_mmx_regs = 8; | |
c131fcee | 8478 | tdep->num_ymm_regs = 0; |
1ba53b71 | 8479 | |
1dbcd68c WT |
8480 | /* No MPX registers. */ |
8481 | tdep->bnd0r_regnum = -1; | |
8482 | tdep->bndcfgu_regnum = -1; | |
8483 | ||
01f9f808 MS |
8484 | /* No AVX512 registers. */ |
8485 | tdep->k0_regnum = -1; | |
8486 | tdep->num_zmm_regs = 0; | |
8487 | tdep->num_ymm_avx512_regs = 0; | |
8488 | tdep->num_xmm_avx512_regs = 0; | |
8489 | ||
90884b2b L |
8490 | tdesc_data = tdesc_data_alloc (); |
8491 | ||
dde08ee1 PA |
8492 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
8493 | ||
6710bf39 SS |
8494 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
8495 | ||
c2170eef MM |
8496 | set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); |
8497 | set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); | |
8498 | set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); | |
8499 | ||
3ce1502b | 8500 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 8501 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 8502 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 8503 | |
c131fcee L |
8504 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
8505 | { | |
8506 | tdesc_data_cleanup (tdesc_data); | |
8507 | xfree (tdep); | |
8508 | gdbarch_free (gdbarch); | |
8509 | return NULL; | |
8510 | } | |
8511 | ||
1dbcd68c WT |
8512 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
8513 | ||
1ba53b71 L |
8514 | /* Wire in pseudo registers. Number of pseudo registers may be |
8515 | changed. */ | |
8516 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8517 | + tdep->num_word_regs | |
8518 | + tdep->num_dword_regs | |
c131fcee | 8519 | + tdep->num_mmx_regs |
1dbcd68c | 8520 | + tdep->num_ymm_regs |
01f9f808 MS |
8521 | + num_bnd_cooked |
8522 | + tdep->num_ymm_avx512_regs | |
8523 | + tdep->num_zmm_regs)); | |
1ba53b71 | 8524 | |
90884b2b L |
8525 | /* Target description may be changed. */ |
8526 | tdesc = tdep->tdesc; | |
8527 | ||
90884b2b L |
8528 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
8529 | ||
8530 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8531 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8532 | ||
1ba53b71 L |
8533 | /* Make %al the first pseudo-register. */ |
8534 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8535 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8536 | ||
c131fcee | 8537 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8538 | if (tdep->num_dword_regs) |
8539 | { | |
1c6272a6 | 8540 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8541 | tdep->eax_regnum = ymm0_regnum; |
8542 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8543 | } |
8544 | else | |
8545 | tdep->eax_regnum = -1; | |
8546 | ||
c131fcee L |
8547 | mm0_regnum = ymm0_regnum; |
8548 | if (tdep->num_ymm_regs) | |
8549 | { | |
1c6272a6 | 8550 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8551 | tdep->ymm0_regnum = ymm0_regnum; |
8552 | mm0_regnum += tdep->num_ymm_regs; | |
8553 | } | |
8554 | else | |
8555 | tdep->ymm0_regnum = -1; | |
8556 | ||
01f9f808 MS |
8557 | if (tdep->num_ymm_avx512_regs) |
8558 | { | |
8559 | /* Support YMM16-31 pseudo registers if available. */ | |
8560 | tdep->ymm16_regnum = mm0_regnum; | |
8561 | mm0_regnum += tdep->num_ymm_avx512_regs; | |
8562 | } | |
8563 | else | |
8564 | tdep->ymm16_regnum = -1; | |
8565 | ||
8566 | if (tdep->num_zmm_regs) | |
8567 | { | |
8568 | /* Support ZMM pseudo-register if it is available. */ | |
8569 | tdep->zmm0_regnum = mm0_regnum; | |
8570 | mm0_regnum += tdep->num_zmm_regs; | |
8571 | } | |
8572 | else | |
8573 | tdep->zmm0_regnum = -1; | |
8574 | ||
1dbcd68c | 8575 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8576 | if (tdep->num_mmx_regs != 0) |
8577 | { | |
1c6272a6 | 8578 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8579 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8580 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8581 | } |
8582 | else | |
8583 | tdep->mm0_regnum = -1; | |
8584 | ||
1dbcd68c WT |
8585 | if (tdep->bnd0r_regnum > 0) |
8586 | tdep->bnd0_regnum = bnd0_regnum; | |
8587 | else | |
8588 | tdep-> bnd0_regnum = -1; | |
8589 | ||
06da04c6 | 8590 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 8591 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
8592 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
8593 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 8594 | |
8446b36a MK |
8595 | /* If we have a register mapping, enable the generic core file |
8596 | support, unless it has already been enabled. */ | |
8597 | if (tdep->gregset_reg_offset | |
8598 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
8599 | set_gdbarch_regset_from_core_section (gdbarch, | |
8600 | i386_regset_from_core_section); | |
8601 | ||
514f746b AR |
8602 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
8603 | i386_skip_permanent_breakpoint); | |
8604 | ||
7a697b8d SS |
8605 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8606 | i386_fast_tracepoint_valid_at); | |
8607 | ||
a62cc96e AC |
8608 | return gdbarch; |
8609 | } | |
8610 | ||
8201327c MK |
8611 | static enum gdb_osabi |
8612 | i386_coff_osabi_sniffer (bfd *abfd) | |
8613 | { | |
762c5349 MK |
8614 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
8615 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
8616 | return GDB_OSABI_GO32; |
8617 | ||
8618 | return GDB_OSABI_UNKNOWN; | |
8619 | } | |
8201327c MK |
8620 | \f |
8621 | ||
28e9e0f0 MK |
8622 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
8623 | void _initialize_i386_tdep (void); | |
8624 | ||
c906108c | 8625 | void |
fba45db2 | 8626 | _initialize_i386_tdep (void) |
c906108c | 8627 | { |
a62cc96e AC |
8628 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
8629 | ||
fc338970 | 8630 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
8631 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
8632 | &disassembly_flavor, _("\ | |
8633 | Set the disassembly flavor."), _("\ | |
8634 | Show the disassembly flavor."), _("\ | |
8635 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
8636 | NULL, | |
8637 | NULL, /* FIXME: i18n: */ | |
8638 | &setlist, &showlist); | |
8201327c MK |
8639 | |
8640 | /* Add the variable that controls the convention for returning | |
8641 | structs. */ | |
7ab04401 AC |
8642 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
8643 | &struct_convention, _("\ | |
8644 | Set the convention for returning small structs."), _("\ | |
8645 | Show the convention for returning small structs."), _("\ | |
8646 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
8647 | is \"default\"."), | |
8648 | NULL, | |
8649 | NULL, /* FIXME: i18n: */ | |
8650 | &setlist, &showlist); | |
8201327c MK |
8651 | |
8652 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
8653 | i386_coff_osabi_sniffer); | |
8201327c | 8654 | |
05816f70 | 8655 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 8656 | i386_svr4_init_abi); |
05816f70 | 8657 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 8658 | i386_go32_init_abi); |
38c968cf | 8659 | |
209bd28e | 8660 | /* Initialize the i386-specific register groups. */ |
38c968cf | 8661 | i386_init_reggroups (); |
90884b2b L |
8662 | |
8663 | /* Initialize the standard target descriptions. */ | |
8664 | initialize_tdesc_i386 (); | |
3a13a53b | 8665 | initialize_tdesc_i386_mmx (); |
c131fcee | 8666 | initialize_tdesc_i386_avx (); |
1dbcd68c | 8667 | initialize_tdesc_i386_mpx (); |
01f9f808 | 8668 | initialize_tdesc_i386_avx512 (); |
c8d5aac9 L |
8669 | |
8670 | /* Tell remote stub that we support XML target description. */ | |
8671 | register_remote_support_xml ("i386"); | |
c906108c | 8672 | } |