Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
7b6bb8da | 5 | 2010, 2011 Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
7a697b8d | 46 | #include "disasm.h" |
c8d5aac9 | 47 | #include "remote.h" |
8fbca658 | 48 | #include "exceptions.h" |
3d261580 | 49 | #include "gdb_assert.h" |
acd5c798 | 50 | #include "gdb_string.h" |
3d261580 | 51 | |
d2a7c97a | 52 | #include "i386-tdep.h" |
61113f8b | 53 | #include "i387-tdep.h" |
c131fcee | 54 | #include "i386-xstate.h" |
d2a7c97a | 55 | |
7ad10968 HZ |
56 | #include "record.h" |
57 | #include <stdint.h> | |
58 | ||
90884b2b | 59 | #include "features/i386/i386.c" |
c131fcee | 60 | #include "features/i386/i386-avx.c" |
3a13a53b | 61 | #include "features/i386/i386-mmx.c" |
90884b2b | 62 | |
6710bf39 SS |
63 | #include "ax.h" |
64 | #include "ax-gdb.h" | |
65 | ||
c4fc7f1b | 66 | /* Register names. */ |
c40e1eab | 67 | |
90884b2b | 68 | static const char *i386_register_names[] = |
fc633446 MK |
69 | { |
70 | "eax", "ecx", "edx", "ebx", | |
71 | "esp", "ebp", "esi", "edi", | |
72 | "eip", "eflags", "cs", "ss", | |
73 | "ds", "es", "fs", "gs", | |
74 | "st0", "st1", "st2", "st3", | |
75 | "st4", "st5", "st6", "st7", | |
76 | "fctrl", "fstat", "ftag", "fiseg", | |
77 | "fioff", "foseg", "fooff", "fop", | |
78 | "xmm0", "xmm1", "xmm2", "xmm3", | |
79 | "xmm4", "xmm5", "xmm6", "xmm7", | |
80 | "mxcsr" | |
81 | }; | |
82 | ||
c131fcee L |
83 | static const char *i386_ymm_names[] = |
84 | { | |
85 | "ymm0", "ymm1", "ymm2", "ymm3", | |
86 | "ymm4", "ymm5", "ymm6", "ymm7", | |
87 | }; | |
88 | ||
89 | static const char *i386_ymmh_names[] = | |
90 | { | |
91 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
92 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
93 | }; | |
94 | ||
c4fc7f1b | 95 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 96 | |
90884b2b | 97 | static const char *i386_mmx_names[] = |
28fc6740 AC |
98 | { |
99 | "mm0", "mm1", "mm2", "mm3", | |
100 | "mm4", "mm5", "mm6", "mm7" | |
101 | }; | |
c40e1eab | 102 | |
1ba53b71 L |
103 | /* Register names for byte pseudo-registers. */ |
104 | ||
105 | static const char *i386_byte_names[] = | |
106 | { | |
107 | "al", "cl", "dl", "bl", | |
108 | "ah", "ch", "dh", "bh" | |
109 | }; | |
110 | ||
111 | /* Register names for word pseudo-registers. */ | |
112 | ||
113 | static const char *i386_word_names[] = | |
114 | { | |
115 | "ax", "cx", "dx", "bx", | |
9cad29ac | 116 | "", "bp", "si", "di" |
1ba53b71 L |
117 | }; |
118 | ||
119 | /* MMX register? */ | |
c40e1eab | 120 | |
28fc6740 | 121 | static int |
5716833c | 122 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 123 | { |
1ba53b71 L |
124 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
125 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
126 | |
127 | if (mm0_regnum < 0) | |
128 | return 0; | |
129 | ||
1ba53b71 L |
130 | regnum -= mm0_regnum; |
131 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
132 | } | |
133 | ||
134 | /* Byte register? */ | |
135 | ||
136 | int | |
137 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
138 | { | |
139 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
140 | ||
141 | regnum -= tdep->al_regnum; | |
142 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
143 | } | |
144 | ||
145 | /* Word register? */ | |
146 | ||
147 | int | |
148 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
149 | { | |
150 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
151 | ||
152 | regnum -= tdep->ax_regnum; | |
153 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
154 | } | |
155 | ||
156 | /* Dword register? */ | |
157 | ||
158 | int | |
159 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
160 | { | |
161 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
162 | int eax_regnum = tdep->eax_regnum; | |
163 | ||
164 | if (eax_regnum < 0) | |
165 | return 0; | |
166 | ||
167 | regnum -= eax_regnum; | |
168 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
169 | } |
170 | ||
9191d390 | 171 | static int |
c131fcee L |
172 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
173 | { | |
174 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
175 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
176 | ||
177 | if (ymm0h_regnum < 0) | |
178 | return 0; | |
179 | ||
180 | regnum -= ymm0h_regnum; | |
181 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
182 | } | |
183 | ||
184 | /* AVX register? */ | |
185 | ||
186 | int | |
187 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
188 | { | |
189 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
190 | int ymm0_regnum = tdep->ymm0_regnum; | |
191 | ||
192 | if (ymm0_regnum < 0) | |
193 | return 0; | |
194 | ||
195 | regnum -= ymm0_regnum; | |
196 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
197 | } | |
198 | ||
5716833c | 199 | /* SSE register? */ |
23a34459 | 200 | |
c131fcee L |
201 | int |
202 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 203 | { |
5716833c | 204 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 205 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 206 | |
c131fcee | 207 | if (num_xmm_regs == 0) |
5716833c MK |
208 | return 0; |
209 | ||
c131fcee L |
210 | regnum -= I387_XMM0_REGNUM (tdep); |
211 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
212 | } |
213 | ||
5716833c MK |
214 | static int |
215 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 216 | { |
5716833c MK |
217 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
218 | ||
20a6ec49 | 219 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
220 | return 0; |
221 | ||
20a6ec49 | 222 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
223 | } |
224 | ||
5716833c | 225 | /* FP register? */ |
23a34459 AC |
226 | |
227 | int | |
20a6ec49 | 228 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 229 | { |
20a6ec49 MD |
230 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
231 | ||
232 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
233 | return 0; |
234 | ||
20a6ec49 MD |
235 | return (I387_ST0_REGNUM (tdep) <= regnum |
236 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
237 | } |
238 | ||
239 | int | |
20a6ec49 | 240 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 241 | { |
20a6ec49 MD |
242 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
243 | ||
244 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
245 | return 0; |
246 | ||
20a6ec49 MD |
247 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
248 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
249 | } |
250 | ||
c131fcee L |
251 | /* Return the name of register REGNUM, or the empty string if it is |
252 | an anonymous register. */ | |
253 | ||
254 | static const char * | |
255 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
256 | { | |
257 | /* Hide the upper YMM registers. */ | |
258 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
259 | return ""; | |
260 | ||
261 | return tdesc_register_name (gdbarch, regnum); | |
262 | } | |
263 | ||
30b0e2d8 | 264 | /* Return the name of register REGNUM. */ |
fc633446 | 265 | |
1ba53b71 | 266 | const char * |
90884b2b | 267 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 268 | { |
1ba53b71 L |
269 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
270 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
271 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
272 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
273 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
1ba53b71 L |
274 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
275 | return i386_byte_names[regnum - tdep->al_regnum]; | |
276 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
277 | return i386_word_names[regnum - tdep->ax_regnum]; | |
278 | ||
279 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
280 | } |
281 | ||
c4fc7f1b | 282 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
283 | number used by GDB. */ |
284 | ||
8201327c | 285 | static int |
d3f73121 | 286 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 287 | { |
20a6ec49 MD |
288 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
289 | ||
c4fc7f1b MK |
290 | /* This implements what GCC calls the "default" register map |
291 | (dbx_register_map[]). */ | |
292 | ||
85540d8c MK |
293 | if (reg >= 0 && reg <= 7) |
294 | { | |
9872ad24 JB |
295 | /* General-purpose registers. The debug info calls %ebp |
296 | register 4, and %esp register 5. */ | |
297 | if (reg == 4) | |
298 | return 5; | |
299 | else if (reg == 5) | |
300 | return 4; | |
301 | else return reg; | |
85540d8c MK |
302 | } |
303 | else if (reg >= 12 && reg <= 19) | |
304 | { | |
305 | /* Floating-point registers. */ | |
20a6ec49 | 306 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
307 | } |
308 | else if (reg >= 21 && reg <= 28) | |
309 | { | |
310 | /* SSE registers. */ | |
c131fcee L |
311 | int ymm0_regnum = tdep->ymm0_regnum; |
312 | ||
313 | if (ymm0_regnum >= 0 | |
314 | && i386_xmm_regnum_p (gdbarch, reg)) | |
315 | return reg - 21 + ymm0_regnum; | |
316 | else | |
317 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
318 | } |
319 | else if (reg >= 29 && reg <= 36) | |
320 | { | |
321 | /* MMX registers. */ | |
20a6ec49 | 322 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
323 | } |
324 | ||
325 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 326 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
327 | } |
328 | ||
c4fc7f1b MK |
329 | /* Convert SVR4 register number REG to the appropriate register number |
330 | used by GDB. */ | |
85540d8c | 331 | |
8201327c | 332 | static int |
d3f73121 | 333 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 334 | { |
20a6ec49 MD |
335 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
336 | ||
c4fc7f1b MK |
337 | /* This implements the GCC register map that tries to be compatible |
338 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
339 | ||
340 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
341 | numbers the floating point registers differently. */ |
342 | if (reg >= 0 && reg <= 9) | |
343 | { | |
acd5c798 | 344 | /* General-purpose registers. */ |
85540d8c MK |
345 | return reg; |
346 | } | |
347 | else if (reg >= 11 && reg <= 18) | |
348 | { | |
349 | /* Floating-point registers. */ | |
20a6ec49 | 350 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 351 | } |
c6f4c129 | 352 | else if (reg >= 21 && reg <= 36) |
85540d8c | 353 | { |
c4fc7f1b | 354 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 355 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
356 | } |
357 | ||
c6f4c129 JB |
358 | switch (reg) |
359 | { | |
20a6ec49 MD |
360 | case 37: return I387_FCTRL_REGNUM (tdep); |
361 | case 38: return I387_FSTAT_REGNUM (tdep); | |
362 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
363 | case 40: return I386_ES_REGNUM; |
364 | case 41: return I386_CS_REGNUM; | |
365 | case 42: return I386_SS_REGNUM; | |
366 | case 43: return I386_DS_REGNUM; | |
367 | case 44: return I386_FS_REGNUM; | |
368 | case 45: return I386_GS_REGNUM; | |
369 | } | |
370 | ||
85540d8c | 371 | /* This will hopefully provoke a warning. */ |
d3f73121 | 372 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 373 | } |
5716833c | 374 | |
fc338970 | 375 | \f |
917317f4 | 376 | |
fc338970 MK |
377 | /* This is the variable that is set with "set disassembly-flavor", and |
378 | its legitimate values. */ | |
53904c9e AC |
379 | static const char att_flavor[] = "att"; |
380 | static const char intel_flavor[] = "intel"; | |
381 | static const char *valid_flavors[] = | |
c5aa993b | 382 | { |
c906108c SS |
383 | att_flavor, |
384 | intel_flavor, | |
385 | NULL | |
386 | }; | |
53904c9e | 387 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 388 | \f |
c906108c | 389 | |
acd5c798 MK |
390 | /* Use the program counter to determine the contents and size of a |
391 | breakpoint instruction. Return a pointer to a string of bytes that | |
392 | encode a breakpoint instruction, store the length of the string in | |
393 | *LEN and optionally adjust *PC to point to the correct memory | |
394 | location for inserting the breakpoint. | |
c906108c | 395 | |
acd5c798 MK |
396 | On the i386 we have a single breakpoint that fits in a single byte |
397 | and can be inserted anywhere. | |
c906108c | 398 | |
acd5c798 | 399 | This function is 64-bit safe. */ |
63c0089f MK |
400 | |
401 | static const gdb_byte * | |
67d57894 | 402 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 403 | { |
63c0089f MK |
404 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
405 | ||
acd5c798 MK |
406 | *len = sizeof (break_insn); |
407 | return break_insn; | |
c906108c | 408 | } |
237fc4c9 PA |
409 | \f |
410 | /* Displaced instruction handling. */ | |
411 | ||
1903f0e6 DE |
412 | /* Skip the legacy instruction prefixes in INSN. |
413 | Not all prefixes are valid for any particular insn | |
414 | but we needn't care, the insn will fault if it's invalid. | |
415 | The result is a pointer to the first opcode byte, | |
416 | or NULL if we run off the end of the buffer. */ | |
417 | ||
418 | static gdb_byte * | |
419 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
420 | { | |
421 | gdb_byte *end = insn + max_len; | |
422 | ||
423 | while (insn < end) | |
424 | { | |
425 | switch (*insn) | |
426 | { | |
427 | case DATA_PREFIX_OPCODE: | |
428 | case ADDR_PREFIX_OPCODE: | |
429 | case CS_PREFIX_OPCODE: | |
430 | case DS_PREFIX_OPCODE: | |
431 | case ES_PREFIX_OPCODE: | |
432 | case FS_PREFIX_OPCODE: | |
433 | case GS_PREFIX_OPCODE: | |
434 | case SS_PREFIX_OPCODE: | |
435 | case LOCK_PREFIX_OPCODE: | |
436 | case REPE_PREFIX_OPCODE: | |
437 | case REPNE_PREFIX_OPCODE: | |
438 | ++insn; | |
439 | continue; | |
440 | default: | |
441 | return insn; | |
442 | } | |
443 | } | |
444 | ||
445 | return NULL; | |
446 | } | |
237fc4c9 PA |
447 | |
448 | static int | |
1903f0e6 | 449 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 450 | { |
1777feb0 | 451 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
452 | if (insn[0] == 0xea) |
453 | return 1; | |
454 | ||
455 | if (insn[0] == 0xff) | |
456 | { | |
1777feb0 | 457 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
458 | if ((insn[1] & 0x38) == 0x20) |
459 | return 1; | |
460 | ||
1777feb0 | 461 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
462 | if ((insn[1] & 0x38) == 0x28) |
463 | return 1; | |
464 | } | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | static int | |
1903f0e6 | 470 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 471 | { |
1777feb0 | 472 | /* call far, absolute. */ |
237fc4c9 PA |
473 | if (insn[0] == 0x9a) |
474 | return 1; | |
475 | ||
476 | if (insn[0] == 0xff) | |
477 | { | |
1777feb0 | 478 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
479 | if ((insn[1] & 0x38) == 0x10) |
480 | return 1; | |
481 | ||
1777feb0 | 482 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
483 | if ((insn[1] & 0x38) == 0x18) |
484 | return 1; | |
485 | } | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
490 | static int | |
1903f0e6 | 491 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
492 | { |
493 | switch (insn[0]) | |
494 | { | |
1777feb0 | 495 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 496 | case 0xc3: /* ret near */ |
1777feb0 | 497 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
498 | case 0xcb: /* ret far */ |
499 | case 0xcf: /* iret */ | |
500 | return 1; | |
501 | ||
502 | default: | |
503 | return 0; | |
504 | } | |
505 | } | |
506 | ||
507 | static int | |
1903f0e6 | 508 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
509 | { |
510 | if (i386_absolute_call_p (insn)) | |
511 | return 1; | |
512 | ||
1777feb0 | 513 | /* call near, relative. */ |
237fc4c9 PA |
514 | if (insn[0] == 0xe8) |
515 | return 1; | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
237fc4c9 PA |
520 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
521 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 522 | |
237fc4c9 | 523 | static int |
b55078be | 524 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 PA |
525 | { |
526 | if (insn[0] == 0xcd) | |
527 | { | |
528 | *lengthp = 2; | |
529 | return 1; | |
530 | } | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
b55078be DE |
535 | /* Some kernels may run one past a syscall insn, so we have to cope. |
536 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
537 | ||
538 | struct displaced_step_closure * | |
539 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
540 | CORE_ADDR from, CORE_ADDR to, | |
541 | struct regcache *regs) | |
542 | { | |
543 | size_t len = gdbarch_max_insn_length (gdbarch); | |
544 | gdb_byte *buf = xmalloc (len); | |
545 | ||
546 | read_memory (from, buf, len); | |
547 | ||
548 | /* GDB may get control back after the insn after the syscall. | |
549 | Presumably this is a kernel bug. | |
550 | If this is a syscall, make sure there's a nop afterwards. */ | |
551 | { | |
552 | int syscall_length; | |
553 | gdb_byte *insn; | |
554 | ||
555 | insn = i386_skip_prefixes (buf, len); | |
556 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
557 | insn[syscall_length] = NOP_OPCODE; | |
558 | } | |
559 | ||
560 | write_memory (to, buf, len); | |
561 | ||
562 | if (debug_displaced) | |
563 | { | |
564 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
565 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
566 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
567 | } | |
568 | ||
569 | return (struct displaced_step_closure *) buf; | |
570 | } | |
571 | ||
237fc4c9 PA |
572 | /* Fix up the state of registers and memory after having single-stepped |
573 | a displaced instruction. */ | |
1903f0e6 | 574 | |
237fc4c9 PA |
575 | void |
576 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
577 | struct displaced_step_closure *closure, | |
578 | CORE_ADDR from, CORE_ADDR to, | |
579 | struct regcache *regs) | |
580 | { | |
e17a4113 UW |
581 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
582 | ||
237fc4c9 PA |
583 | /* The offset we applied to the instruction's address. |
584 | This could well be negative (when viewed as a signed 32-bit | |
585 | value), but ULONGEST won't reflect that, so take care when | |
586 | applying it. */ | |
587 | ULONGEST insn_offset = to - from; | |
588 | ||
589 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
590 | copy of the instruction. */ | |
591 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
592 | /* The start of the insn, needed in case we see some prefixes. */ |
593 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
594 | |
595 | if (debug_displaced) | |
596 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 597 | "displaced: fixup (%s, %s), " |
237fc4c9 | 598 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
599 | paddress (gdbarch, from), paddress (gdbarch, to), |
600 | insn[0], insn[1]); | |
237fc4c9 PA |
601 | |
602 | /* The list of issues to contend with here is taken from | |
603 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
604 | Yay for Free Software! */ | |
605 | ||
606 | /* Relocate the %eip, if necessary. */ | |
607 | ||
1903f0e6 DE |
608 | /* The instruction recognizers we use assume any leading prefixes |
609 | have been skipped. */ | |
610 | { | |
611 | /* This is the size of the buffer in closure. */ | |
612 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
613 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
614 | /* If there are too many prefixes, just ignore the insn. | |
615 | It will fault when run. */ | |
616 | if (opcode != NULL) | |
617 | insn = opcode; | |
618 | } | |
619 | ||
237fc4c9 PA |
620 | /* Except in the case of absolute or indirect jump or call |
621 | instructions, or a return instruction, the new eip is relative to | |
622 | the displaced instruction; make it relative. Well, signal | |
623 | handler returns don't need relocation either, but we use the | |
624 | value of %eip to recognize those; see below. */ | |
625 | if (! i386_absolute_jmp_p (insn) | |
626 | && ! i386_absolute_call_p (insn) | |
627 | && ! i386_ret_p (insn)) | |
628 | { | |
629 | ULONGEST orig_eip; | |
b55078be | 630 | int insn_len; |
237fc4c9 PA |
631 | |
632 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
633 | ||
634 | /* A signal trampoline system call changes the %eip, resuming | |
635 | execution of the main program after the signal handler has | |
636 | returned. That makes them like 'return' instructions; we | |
637 | shouldn't relocate %eip. | |
638 | ||
639 | But most system calls don't, and we do need to relocate %eip. | |
640 | ||
641 | Our heuristic for distinguishing these cases: if stepping | |
642 | over the system call instruction left control directly after | |
643 | the instruction, the we relocate --- control almost certainly | |
644 | doesn't belong in the displaced copy. Otherwise, we assume | |
645 | the instruction has put control where it belongs, and leave | |
646 | it unrelocated. Goodness help us if there are PC-relative | |
647 | system calls. */ | |
648 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
649 | && orig_eip != to + (insn - insn_start) + insn_len |
650 | /* GDB can get control back after the insn after the syscall. | |
651 | Presumably this is a kernel bug. | |
652 | i386_displaced_step_copy_insn ensures its a nop, | |
653 | we add one to the length for it. */ | |
654 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
655 | { |
656 | if (debug_displaced) | |
657 | fprintf_unfiltered (gdb_stdlog, | |
658 | "displaced: syscall changed %%eip; " | |
659 | "not relocating\n"); | |
660 | } | |
661 | else | |
662 | { | |
663 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
664 | ||
1903f0e6 DE |
665 | /* If we just stepped over a breakpoint insn, we don't backup |
666 | the pc on purpose; this is to match behaviour without | |
667 | stepping. */ | |
237fc4c9 PA |
668 | |
669 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
670 | ||
671 | if (debug_displaced) | |
672 | fprintf_unfiltered (gdb_stdlog, | |
673 | "displaced: " | |
5af949e3 UW |
674 | "relocated %%eip from %s to %s\n", |
675 | paddress (gdbarch, orig_eip), | |
676 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
677 | } |
678 | } | |
679 | ||
680 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
681 | pushed value, and should be cleared. We'll leave this for later, | |
682 | since GDB already messes up the TF flag when stepping over a | |
683 | pushfl. */ | |
684 | ||
685 | /* If the instruction was a call, the return address now atop the | |
686 | stack is the address following the copied instruction. We need | |
687 | to make it the address following the original instruction. */ | |
688 | if (i386_call_p (insn)) | |
689 | { | |
690 | ULONGEST esp; | |
691 | ULONGEST retaddr; | |
692 | const ULONGEST retaddr_len = 4; | |
693 | ||
694 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 695 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 696 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 697 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
698 | |
699 | if (debug_displaced) | |
700 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
701 | "displaced: relocated return addr at %s to %s\n", |
702 | paddress (gdbarch, esp), | |
703 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
704 | } |
705 | } | |
dde08ee1 PA |
706 | |
707 | static void | |
708 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
709 | { | |
710 | target_write_memory (*to, buf, len); | |
711 | *to += len; | |
712 | } | |
713 | ||
714 | static void | |
715 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
716 | CORE_ADDR *to, CORE_ADDR oldloc) | |
717 | { | |
718 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
719 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
720 | int offset = 0, rel32, newrel; | |
721 | int insn_length; | |
722 | gdb_byte *insn = buf; | |
723 | ||
724 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
725 | ||
726 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
727 | I386_MAX_INSN_LEN, oldloc); | |
728 | ||
729 | /* Get past the prefixes. */ | |
730 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
731 | ||
732 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
733 | the address pushed being the location where the original call in | |
734 | the user program would return to. */ | |
735 | if (insn[0] == 0xe8) | |
736 | { | |
737 | gdb_byte push_buf[16]; | |
738 | unsigned int ret_addr; | |
739 | ||
740 | /* Where "ret" in the original code will return to. */ | |
741 | ret_addr = oldloc + insn_length; | |
1777feb0 | 742 | push_buf[0] = 0x68; /* pushq $... */ |
dde08ee1 PA |
743 | memcpy (&push_buf[1], &ret_addr, 4); |
744 | /* Push the push. */ | |
745 | append_insns (to, 5, push_buf); | |
746 | ||
747 | /* Convert the relative call to a relative jump. */ | |
748 | insn[0] = 0xe9; | |
749 | ||
750 | /* Adjust the destination offset. */ | |
751 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
752 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
753 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
754 | ||
755 | if (debug_displaced) | |
756 | fprintf_unfiltered (gdb_stdlog, | |
757 | "Adjusted insn rel32=%s at %s to" | |
758 | " rel32=%s at %s\n", | |
759 | hex_string (rel32), paddress (gdbarch, oldloc), | |
760 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
761 | |
762 | /* Write the adjusted jump into its displaced location. */ | |
763 | append_insns (to, 5, insn); | |
764 | return; | |
765 | } | |
766 | ||
767 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
768 | handled above. */ | |
769 | if (insn[0] == 0xe9) | |
770 | offset = 1; | |
771 | /* Adjust conditional jumps. */ | |
772 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
773 | offset = 2; | |
774 | ||
775 | if (offset) | |
776 | { | |
777 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
778 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 779 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
780 | if (debug_displaced) |
781 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
782 | "Adjusted insn rel32=%s at %s to" |
783 | " rel32=%s at %s\n", | |
dde08ee1 PA |
784 | hex_string (rel32), paddress (gdbarch, oldloc), |
785 | hex_string (newrel), paddress (gdbarch, *to)); | |
786 | } | |
787 | ||
788 | /* Write the adjusted instructions into their displaced | |
789 | location. */ | |
790 | append_insns (to, insn_length, buf); | |
791 | } | |
792 | ||
fc338970 | 793 | \f |
acd5c798 MK |
794 | #ifdef I386_REGNO_TO_SYMMETRY |
795 | #error "The Sequent Symmetry is no longer supported." | |
796 | #endif | |
c906108c | 797 | |
acd5c798 MK |
798 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
799 | and %esp "belong" to the calling function. Therefore these | |
800 | registers should be saved if they're going to be modified. */ | |
c906108c | 801 | |
acd5c798 MK |
802 | /* The maximum number of saved registers. This should include all |
803 | registers mentioned above, and %eip. */ | |
a3386186 | 804 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
805 | |
806 | struct i386_frame_cache | |
c906108c | 807 | { |
acd5c798 MK |
808 | /* Base address. */ |
809 | CORE_ADDR base; | |
8fbca658 | 810 | int base_p; |
772562f8 | 811 | LONGEST sp_offset; |
acd5c798 MK |
812 | CORE_ADDR pc; |
813 | ||
fd13a04a AC |
814 | /* Saved registers. */ |
815 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 816 | CORE_ADDR saved_sp; |
e0c62198 | 817 | int saved_sp_reg; |
acd5c798 MK |
818 | int pc_in_eax; |
819 | ||
820 | /* Stack space reserved for local variables. */ | |
821 | long locals; | |
822 | }; | |
823 | ||
824 | /* Allocate and initialize a frame cache. */ | |
825 | ||
826 | static struct i386_frame_cache * | |
fd13a04a | 827 | i386_alloc_frame_cache (void) |
acd5c798 MK |
828 | { |
829 | struct i386_frame_cache *cache; | |
830 | int i; | |
831 | ||
832 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
833 | ||
834 | /* Base address. */ | |
8fbca658 | 835 | cache->base_p = 0; |
acd5c798 MK |
836 | cache->base = 0; |
837 | cache->sp_offset = -4; | |
838 | cache->pc = 0; | |
839 | ||
fd13a04a AC |
840 | /* Saved registers. We initialize these to -1 since zero is a valid |
841 | offset (that's where %ebp is supposed to be stored). */ | |
842 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
843 | cache->saved_regs[i] = -1; | |
acd5c798 | 844 | cache->saved_sp = 0; |
e0c62198 | 845 | cache->saved_sp_reg = -1; |
acd5c798 MK |
846 | cache->pc_in_eax = 0; |
847 | ||
848 | /* Frameless until proven otherwise. */ | |
849 | cache->locals = -1; | |
850 | ||
851 | return cache; | |
852 | } | |
c906108c | 853 | |
acd5c798 MK |
854 | /* If the instruction at PC is a jump, return the address of its |
855 | target. Otherwise, return PC. */ | |
c906108c | 856 | |
acd5c798 | 857 | static CORE_ADDR |
e17a4113 | 858 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 859 | { |
e17a4113 | 860 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 861 | gdb_byte op; |
acd5c798 MK |
862 | long delta = 0; |
863 | int data16 = 0; | |
c906108c | 864 | |
3dcabaa8 MS |
865 | if (target_read_memory (pc, &op, 1)) |
866 | return pc; | |
867 | ||
acd5c798 | 868 | if (op == 0x66) |
c906108c | 869 | { |
c906108c | 870 | data16 = 1; |
e17a4113 | 871 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
872 | } |
873 | ||
acd5c798 | 874 | switch (op) |
c906108c SS |
875 | { |
876 | case 0xe9: | |
fc338970 | 877 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
878 | if (data16) |
879 | { | |
e17a4113 | 880 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 881 | |
fc338970 MK |
882 | /* Include the size of the jmp instruction (including the |
883 | 0x66 prefix). */ | |
acd5c798 | 884 | delta += 4; |
c906108c SS |
885 | } |
886 | else | |
887 | { | |
e17a4113 | 888 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 889 | |
acd5c798 MK |
890 | /* Include the size of the jmp instruction. */ |
891 | delta += 5; | |
c906108c SS |
892 | } |
893 | break; | |
894 | case 0xeb: | |
fc338970 | 895 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 896 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 897 | |
acd5c798 | 898 | delta += data16 + 2; |
c906108c SS |
899 | break; |
900 | } | |
c906108c | 901 | |
acd5c798 MK |
902 | return pc + delta; |
903 | } | |
fc338970 | 904 | |
acd5c798 MK |
905 | /* Check whether PC points at a prologue for a function returning a |
906 | structure or union. If so, it updates CACHE and returns the | |
907 | address of the first instruction after the code sequence that | |
908 | removes the "hidden" argument from the stack or CURRENT_PC, | |
909 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 910 | |
acd5c798 MK |
911 | static CORE_ADDR |
912 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
913 | struct i386_frame_cache *cache) | |
c906108c | 914 | { |
acd5c798 MK |
915 | /* Functions that return a structure or union start with: |
916 | ||
917 | popl %eax 0x58 | |
918 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
919 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
920 | ||
921 | (the System V compiler puts out the second `xchg' instruction, | |
922 | and the assembler doesn't try to optimize it, so the 'sib' form | |
923 | gets generated). This sequence is used to get the address of the | |
924 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
925 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
926 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
927 | gdb_byte buf[4]; | |
928 | gdb_byte op; | |
c906108c | 929 | |
acd5c798 MK |
930 | if (current_pc <= pc) |
931 | return pc; | |
932 | ||
3dcabaa8 MS |
933 | if (target_read_memory (pc, &op, 1)) |
934 | return pc; | |
c906108c | 935 | |
acd5c798 MK |
936 | if (op != 0x58) /* popl %eax */ |
937 | return pc; | |
c906108c | 938 | |
3dcabaa8 MS |
939 | if (target_read_memory (pc + 1, buf, 4)) |
940 | return pc; | |
941 | ||
acd5c798 MK |
942 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
943 | return pc; | |
c906108c | 944 | |
acd5c798 | 945 | if (current_pc == pc) |
c906108c | 946 | { |
acd5c798 MK |
947 | cache->sp_offset += 4; |
948 | return current_pc; | |
c906108c SS |
949 | } |
950 | ||
acd5c798 | 951 | if (current_pc == pc + 1) |
c906108c | 952 | { |
acd5c798 MK |
953 | cache->pc_in_eax = 1; |
954 | return current_pc; | |
955 | } | |
956 | ||
957 | if (buf[1] == proto1[1]) | |
958 | return pc + 4; | |
959 | else | |
960 | return pc + 5; | |
961 | } | |
962 | ||
963 | static CORE_ADDR | |
964 | i386_skip_probe (CORE_ADDR pc) | |
965 | { | |
966 | /* A function may start with | |
fc338970 | 967 | |
acd5c798 MK |
968 | pushl constant |
969 | call _probe | |
970 | addl $4, %esp | |
fc338970 | 971 | |
acd5c798 MK |
972 | followed by |
973 | ||
974 | pushl %ebp | |
fc338970 | 975 | |
acd5c798 | 976 | etc. */ |
63c0089f MK |
977 | gdb_byte buf[8]; |
978 | gdb_byte op; | |
fc338970 | 979 | |
3dcabaa8 MS |
980 | if (target_read_memory (pc, &op, 1)) |
981 | return pc; | |
acd5c798 MK |
982 | |
983 | if (op == 0x68 || op == 0x6a) | |
984 | { | |
985 | int delta; | |
c906108c | 986 | |
acd5c798 MK |
987 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
988 | four-byte operand, depending on the opcode. */ | |
c906108c | 989 | if (op == 0x68) |
acd5c798 | 990 | delta = 5; |
c906108c | 991 | else |
acd5c798 | 992 | delta = 2; |
c906108c | 993 | |
acd5c798 MK |
994 | /* Read the following 8 bytes, which should be `call _probe' (6 |
995 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
996 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 997 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 998 | pc += delta + sizeof (buf); |
c906108c SS |
999 | } |
1000 | ||
acd5c798 MK |
1001 | return pc; |
1002 | } | |
1003 | ||
92dd43fa MK |
1004 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1005 | stack pointer. Check whether PC points to such code, and update | |
1006 | CACHE accordingly. Return the first instruction after the code | |
1007 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1008 | recognize the code, return PC. */ | |
1009 | ||
1010 | static CORE_ADDR | |
1011 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1012 | struct i386_frame_cache *cache) | |
1013 | { | |
e0c62198 L |
1014 | /* There are 2 code sequences to re-align stack before the frame |
1015 | gets set up: | |
1016 | ||
1017 | 1. Use a caller-saved saved register: | |
1018 | ||
1019 | leal 4(%esp), %reg | |
1020 | andl $-XXX, %esp | |
1021 | pushl -4(%reg) | |
1022 | ||
1023 | 2. Use a callee-saved saved register: | |
1024 | ||
1025 | pushl %reg | |
1026 | leal 8(%esp), %reg | |
1027 | andl $-XXX, %esp | |
1028 | pushl -4(%reg) | |
1029 | ||
1030 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1031 | ||
1032 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1033 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1034 | */ | |
1035 | ||
1036 | gdb_byte buf[14]; | |
1037 | int reg; | |
1038 | int offset, offset_and; | |
1039 | static int regnums[8] = { | |
1040 | I386_EAX_REGNUM, /* %eax */ | |
1041 | I386_ECX_REGNUM, /* %ecx */ | |
1042 | I386_EDX_REGNUM, /* %edx */ | |
1043 | I386_EBX_REGNUM, /* %ebx */ | |
1044 | I386_ESP_REGNUM, /* %esp */ | |
1045 | I386_EBP_REGNUM, /* %ebp */ | |
1046 | I386_ESI_REGNUM, /* %esi */ | |
1047 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1048 | }; |
92dd43fa | 1049 | |
e0c62198 L |
1050 | if (target_read_memory (pc, buf, sizeof buf)) |
1051 | return pc; | |
1052 | ||
1053 | /* Check caller-saved saved register. The first instruction has | |
1054 | to be "leal 4(%esp), %reg". */ | |
1055 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1056 | { | |
1057 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1058 | if ((buf[1] & 0xc7) != 0x44) | |
1059 | return pc; | |
1060 | ||
1061 | /* REG has register number. */ | |
1062 | reg = (buf[1] >> 3) & 7; | |
1063 | offset = 4; | |
1064 | } | |
1065 | else | |
1066 | { | |
1067 | /* Check callee-saved saved register. The first instruction | |
1068 | has to be "pushl %reg". */ | |
1069 | if ((buf[0] & 0xf8) != 0x50) | |
1070 | return pc; | |
1071 | ||
1072 | /* Get register. */ | |
1073 | reg = buf[0] & 0x7; | |
1074 | ||
1075 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1076 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1077 | return pc; | |
1078 | ||
1079 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1080 | if ((buf[2] & 0xc7) != 0x44) | |
1081 | return pc; | |
1082 | ||
1083 | /* REG has register number. Registers in pushl and leal have to | |
1084 | be the same. */ | |
1085 | if (reg != ((buf[2] >> 3) & 7)) | |
1086 | return pc; | |
1087 | ||
1088 | offset = 5; | |
1089 | } | |
1090 | ||
1091 | /* Rigister can't be %esp nor %ebp. */ | |
1092 | if (reg == 4 || reg == 5) | |
1093 | return pc; | |
1094 | ||
1095 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1096 | if (buf[offset + 1] != 0xe4 | |
1097 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1098 | return pc; | |
1099 | ||
1100 | offset_and = offset; | |
1101 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1102 | ||
1103 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1104 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1105 | if (buf[offset] != 0xff | |
1106 | || buf[offset + 2] != 0xfc | |
1107 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1108 | return pc; | |
1109 | ||
1110 | /* R/M has register. Registers in leal and pushl have to be the | |
1111 | same. */ | |
1112 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1113 | return pc; |
1114 | ||
e0c62198 L |
1115 | if (current_pc > pc + offset_and) |
1116 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1117 | |
e0c62198 | 1118 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1119 | } |
1120 | ||
37bdc87e | 1121 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1122 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1123 | |
1124 | /* Instruction description. */ | |
1125 | struct i386_insn | |
1126 | { | |
1127 | size_t len; | |
237fc4c9 PA |
1128 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1129 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1130 | }; |
1131 | ||
a3fcb948 | 1132 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1133 | |
a3fcb948 JG |
1134 | static int |
1135 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1136 | { |
63c0089f | 1137 | gdb_byte op; |
37bdc87e | 1138 | |
3dcabaa8 | 1139 | if (target_read_memory (pc, &op, 1)) |
a3fcb948 | 1140 | return 0; |
37bdc87e | 1141 | |
a3fcb948 | 1142 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1143 | { |
a3fcb948 JG |
1144 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1145 | int insn_matched = 1; | |
1146 | size_t i; | |
37bdc87e | 1147 | |
a3fcb948 JG |
1148 | gdb_assert (pattern.len > 1); |
1149 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1150 | |
a3fcb948 JG |
1151 | if (target_read_memory (pc + 1, buf, pattern.len - 1)) |
1152 | return 0; | |
613e8135 | 1153 | |
a3fcb948 JG |
1154 | for (i = 1; i < pattern.len; i++) |
1155 | { | |
1156 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1157 | insn_matched = 0; | |
37bdc87e | 1158 | } |
a3fcb948 JG |
1159 | return insn_matched; |
1160 | } | |
1161 | return 0; | |
1162 | } | |
1163 | ||
1164 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1165 | the first instruction description that matches. Otherwise, return | |
1166 | NULL. */ | |
1167 | ||
1168 | static struct i386_insn * | |
1169 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1170 | { | |
1171 | struct i386_insn *pattern; | |
1172 | ||
1173 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1174 | { | |
1175 | if (i386_match_pattern (pc, *pattern)) | |
1176 | return pattern; | |
37bdc87e MK |
1177 | } |
1178 | ||
1179 | return NULL; | |
1180 | } | |
1181 | ||
a3fcb948 JG |
1182 | /* Return whether PC points inside a sequence of instructions that |
1183 | matches INSN_PATTERNS. */ | |
1184 | ||
1185 | static int | |
1186 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1187 | { | |
1188 | CORE_ADDR current_pc; | |
1189 | int ix, i; | |
1190 | gdb_byte op; | |
1191 | struct i386_insn *insn; | |
1192 | ||
1193 | insn = i386_match_insn (pc, insn_patterns); | |
1194 | if (insn == NULL) | |
1195 | return 0; | |
1196 | ||
8bbdd3f4 | 1197 | current_pc = pc; |
a3fcb948 JG |
1198 | ix = insn - insn_patterns; |
1199 | for (i = ix - 1; i >= 0; i--) | |
1200 | { | |
8bbdd3f4 MK |
1201 | current_pc -= insn_patterns[i].len; |
1202 | ||
a3fcb948 JG |
1203 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1204 | return 0; | |
a3fcb948 JG |
1205 | } |
1206 | ||
1207 | current_pc = pc + insn->len; | |
1208 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1209 | { | |
1210 | if (!i386_match_pattern (current_pc, *insn)) | |
1211 | return 0; | |
1212 | ||
1213 | current_pc += insn->len; | |
1214 | } | |
1215 | ||
1216 | return 1; | |
1217 | } | |
1218 | ||
37bdc87e MK |
1219 | /* Some special instructions that might be migrated by GCC into the |
1220 | part of the prologue that sets up the new stack frame. Because the | |
1221 | stack frame hasn't been setup yet, no registers have been saved | |
1222 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1223 | touched. */ | |
1224 | ||
1225 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1226 | { | |
1777feb0 | 1227 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1228 | |
1229 | ??? Should we handle 16-bit operand-sizes here? */ | |
1230 | ||
1231 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1232 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1233 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1234 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1235 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1236 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1237 | { 5, { 0xb8 }, { 0xfe } }, | |
1238 | /* `movl imm32, %edx' */ | |
1239 | { 5, { 0xba }, { 0xff } }, | |
1240 | ||
1241 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1242 | encoding for `mov m32, %eax'. | |
1243 | ||
1244 | ??? Should we handle SIB adressing here? | |
1245 | ??? Should we handle 16-bit operand-sizes here? */ | |
1246 | ||
1247 | /* `movl m32, %eax' */ | |
1248 | { 5, { 0xa1 }, { 0xff } }, | |
1249 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1250 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1251 | /* `movl m32, %edx' */ | |
1252 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1253 | ||
1254 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1255 | Because of the symmetry, there are actually two ways to encode | |
1256 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1257 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1258 | ||
1259 | /* `subl %eax, %eax' */ | |
1260 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1261 | /* `subl %ecx, %ecx' */ | |
1262 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1263 | /* `subl %edx, %edx' */ | |
1264 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1265 | /* `xorl %eax, %eax' */ | |
1266 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1267 | /* `xorl %ecx, %ecx' */ | |
1268 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1269 | /* `xorl %edx, %edx' */ | |
1270 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1271 | { 0 } | |
1272 | }; | |
1273 | ||
e11481da PM |
1274 | |
1275 | /* Check whether PC points to a no-op instruction. */ | |
1276 | static CORE_ADDR | |
1277 | i386_skip_noop (CORE_ADDR pc) | |
1278 | { | |
1279 | gdb_byte op; | |
1280 | int check = 1; | |
1281 | ||
3dcabaa8 MS |
1282 | if (target_read_memory (pc, &op, 1)) |
1283 | return pc; | |
e11481da PM |
1284 | |
1285 | while (check) | |
1286 | { | |
1287 | check = 0; | |
1288 | /* Ignore `nop' instruction. */ | |
1289 | if (op == 0x90) | |
1290 | { | |
1291 | pc += 1; | |
3dcabaa8 MS |
1292 | if (target_read_memory (pc, &op, 1)) |
1293 | return pc; | |
e11481da PM |
1294 | check = 1; |
1295 | } | |
1296 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1297 | Microsoft system dlls often start with | |
1298 | a `mov %edi,%edi' instruction. | |
1299 | The 5 bytes before the function start are | |
1300 | filled with `nop' instructions. | |
1301 | This pattern can be used for hot-patching: | |
1302 | The `mov %edi, %edi' instruction can be replaced by a | |
1303 | near jump to the location of the 5 `nop' instructions | |
1304 | which can be replaced by a 32-bit jump to anywhere | |
1305 | in the 32-bit address space. */ | |
1306 | ||
1307 | else if (op == 0x8b) | |
1308 | { | |
3dcabaa8 MS |
1309 | if (target_read_memory (pc + 1, &op, 1)) |
1310 | return pc; | |
1311 | ||
e11481da PM |
1312 | if (op == 0xff) |
1313 | { | |
1314 | pc += 2; | |
3dcabaa8 MS |
1315 | if (target_read_memory (pc, &op, 1)) |
1316 | return pc; | |
1317 | ||
e11481da PM |
1318 | check = 1; |
1319 | } | |
1320 | } | |
1321 | } | |
1322 | return pc; | |
1323 | } | |
1324 | ||
acd5c798 MK |
1325 | /* Check whether PC points at a code that sets up a new stack frame. |
1326 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1327 | instruction after the sequence that sets up the frame or LIMIT, |
1328 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1329 | |
1330 | static CORE_ADDR | |
e17a4113 UW |
1331 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1332 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1333 | struct i386_frame_cache *cache) |
1334 | { | |
e17a4113 | 1335 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1336 | struct i386_insn *insn; |
63c0089f | 1337 | gdb_byte op; |
26604a34 | 1338 | int skip = 0; |
acd5c798 | 1339 | |
37bdc87e MK |
1340 | if (limit <= pc) |
1341 | return limit; | |
acd5c798 | 1342 | |
3dcabaa8 MS |
1343 | if (target_read_memory (pc, &op, 1)) |
1344 | return pc; | |
acd5c798 | 1345 | |
c906108c | 1346 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1347 | { |
acd5c798 MK |
1348 | /* Take into account that we've executed the `pushl %ebp' that |
1349 | starts this instruction sequence. */ | |
fd13a04a | 1350 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1351 | cache->sp_offset += 4; |
37bdc87e | 1352 | pc++; |
acd5c798 MK |
1353 | |
1354 | /* If that's all, return now. */ | |
37bdc87e MK |
1355 | if (limit <= pc) |
1356 | return limit; | |
26604a34 | 1357 | |
b4632131 | 1358 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1359 | GCC into the prologue and skip them. At this point in the |
1360 | prologue, code should only touch the scratch registers %eax, | |
1361 | %ecx and %edx, so while the number of posibilities is sheer, | |
1362 | it is limited. | |
5daa5b4e | 1363 | |
26604a34 MK |
1364 | Make sure we only skip these instructions if we later see the |
1365 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1366 | while (pc + skip < limit) |
26604a34 | 1367 | { |
37bdc87e MK |
1368 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1369 | if (insn == NULL) | |
1370 | break; | |
b4632131 | 1371 | |
37bdc87e | 1372 | skip += insn->len; |
26604a34 MK |
1373 | } |
1374 | ||
37bdc87e MK |
1375 | /* If that's all, return now. */ |
1376 | if (limit <= pc + skip) | |
1377 | return limit; | |
1378 | ||
3dcabaa8 MS |
1379 | if (target_read_memory (pc + skip, &op, 1)) |
1380 | return pc + skip; | |
37bdc87e | 1381 | |
26604a34 | 1382 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1383 | switch (op) |
c906108c SS |
1384 | { |
1385 | case 0x8b: | |
e17a4113 UW |
1386 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1387 | != 0xec) | |
37bdc87e | 1388 | return pc; |
c906108c SS |
1389 | break; |
1390 | case 0x89: | |
e17a4113 UW |
1391 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1392 | != 0xe5) | |
37bdc87e | 1393 | return pc; |
c906108c SS |
1394 | break; |
1395 | default: | |
37bdc87e | 1396 | return pc; |
c906108c | 1397 | } |
acd5c798 | 1398 | |
26604a34 MK |
1399 | /* OK, we actually have a frame. We just don't know how large |
1400 | it is yet. Set its size to zero. We'll adjust it if | |
1401 | necessary. We also now commit to skipping the special | |
1402 | instructions mentioned before. */ | |
acd5c798 | 1403 | cache->locals = 0; |
37bdc87e | 1404 | pc += (skip + 2); |
acd5c798 MK |
1405 | |
1406 | /* If that's all, return now. */ | |
37bdc87e MK |
1407 | if (limit <= pc) |
1408 | return limit; | |
acd5c798 | 1409 | |
fc338970 MK |
1410 | /* Check for stack adjustment |
1411 | ||
acd5c798 | 1412 | subl $XXX, %esp |
fc338970 | 1413 | |
fd35795f | 1414 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1415 | reg, so we don't have to worry about a data16 prefix. */ |
3dcabaa8 MS |
1416 | if (target_read_memory (pc, &op, 1)) |
1417 | return pc; | |
c906108c SS |
1418 | if (op == 0x83) |
1419 | { | |
fd35795f | 1420 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1421 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1422 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1423 | return pc; |
acd5c798 | 1424 | |
37bdc87e MK |
1425 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1426 | make sense to be negative). */ | |
e17a4113 | 1427 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1428 | return pc + 3; |
c906108c SS |
1429 | } |
1430 | else if (op == 0x81) | |
1431 | { | |
fd35795f | 1432 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1433 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1434 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1435 | return pc; |
acd5c798 | 1436 | |
fd35795f | 1437 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1438 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1439 | return pc + 6; |
c906108c SS |
1440 | } |
1441 | else | |
1442 | { | |
acd5c798 | 1443 | /* Some instruction other than `subl'. */ |
37bdc87e | 1444 | return pc; |
c906108c SS |
1445 | } |
1446 | } | |
37bdc87e | 1447 | else if (op == 0xc8) /* enter */ |
c906108c | 1448 | { |
e17a4113 | 1449 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1450 | return pc + 4; |
c906108c | 1451 | } |
21d0e8a4 | 1452 | |
acd5c798 | 1453 | return pc; |
21d0e8a4 MK |
1454 | } |
1455 | ||
acd5c798 MK |
1456 | /* Check whether PC points at code that saves registers on the stack. |
1457 | If so, it updates CACHE and returns the address of the first | |
1458 | instruction after the register saves or CURRENT_PC, whichever is | |
1459 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1460 | |
1461 | static CORE_ADDR | |
acd5c798 MK |
1462 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1463 | struct i386_frame_cache *cache) | |
6bff26de | 1464 | { |
99ab4326 | 1465 | CORE_ADDR offset = 0; |
63c0089f | 1466 | gdb_byte op; |
99ab4326 | 1467 | int i; |
c0d1d883 | 1468 | |
99ab4326 MK |
1469 | if (cache->locals > 0) |
1470 | offset -= cache->locals; | |
1471 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1472 | { | |
3dcabaa8 MS |
1473 | if (target_read_memory (pc, &op, 1)) |
1474 | return pc; | |
99ab4326 MK |
1475 | if (op < 0x50 || op > 0x57) |
1476 | break; | |
0d17c81d | 1477 | |
99ab4326 MK |
1478 | offset -= 4; |
1479 | cache->saved_regs[op - 0x50] = offset; | |
1480 | cache->sp_offset += 4; | |
1481 | pc++; | |
6bff26de MK |
1482 | } |
1483 | ||
acd5c798 | 1484 | return pc; |
22797942 AC |
1485 | } |
1486 | ||
acd5c798 MK |
1487 | /* Do a full analysis of the prologue at PC and update CACHE |
1488 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1489 | address where the analysis stopped. | |
ed84f6c1 | 1490 | |
fc338970 MK |
1491 | We handle these cases: |
1492 | ||
1493 | The startup sequence can be at the start of the function, or the | |
1494 | function can start with a branch to startup code at the end. | |
1495 | ||
1496 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1497 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1498 | once used in the System V compiler). | |
1499 | ||
1500 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1501 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1502 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1503 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1504 | |
1505 | Next, the registers used by this function are pushed. With the | |
1506 | System V compiler they will always be in the order: %edi, %esi, | |
1507 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1508 | restore %eax); however, the code below is willing to see the pushes | |
1509 | in any order, and will handle up to 8 of them. | |
1510 | ||
1511 | If the setup sequence is at the end of the function, then the next | |
1512 | instruction will be a branch back to the start. */ | |
c906108c | 1513 | |
acd5c798 | 1514 | static CORE_ADDR |
e17a4113 UW |
1515 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1516 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1517 | struct i386_frame_cache *cache) |
c906108c | 1518 | { |
e11481da | 1519 | pc = i386_skip_noop (pc); |
e17a4113 | 1520 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1521 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1522 | pc = i386_skip_probe (pc); | |
92dd43fa | 1523 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1524 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1525 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1526 | } |
1527 | ||
fc338970 | 1528 | /* Return PC of first real instruction. */ |
c906108c | 1529 | |
3a1e71e3 | 1530 | static CORE_ADDR |
6093d2eb | 1531 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1532 | { |
e17a4113 UW |
1533 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1534 | ||
63c0089f | 1535 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1536 | { |
1537 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1538 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1539 | }; |
acd5c798 MK |
1540 | struct i386_frame_cache cache; |
1541 | CORE_ADDR pc; | |
63c0089f | 1542 | gdb_byte op; |
acd5c798 | 1543 | int i; |
c5aa993b | 1544 | |
acd5c798 | 1545 | cache.locals = -1; |
e17a4113 | 1546 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1547 | if (cache.locals < 0) |
1548 | return start_pc; | |
c5aa993b | 1549 | |
acd5c798 | 1550 | /* Found valid frame setup. */ |
c906108c | 1551 | |
fc338970 MK |
1552 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1553 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1554 | %ebx: |
1555 | ||
fc338970 MK |
1556 | call 0x0 |
1557 | popl %ebx | |
1558 | movl %ebx,x(%ebp) (optional) | |
1559 | addl y,%ebx | |
1560 | ||
c906108c SS |
1561 | This code is with the rest of the prologue (at the end of the |
1562 | function), so we have to skip it to get to the first real | |
1563 | instruction at the start of the function. */ | |
c5aa993b | 1564 | |
c906108c SS |
1565 | for (i = 0; i < 6; i++) |
1566 | { | |
3dcabaa8 MS |
1567 | if (target_read_memory (pc + i, &op, 1)) |
1568 | return pc; | |
1569 | ||
c5aa993b | 1570 | if (pic_pat[i] != op) |
c906108c SS |
1571 | break; |
1572 | } | |
1573 | if (i == 6) | |
1574 | { | |
acd5c798 MK |
1575 | int delta = 6; |
1576 | ||
3dcabaa8 MS |
1577 | if (target_read_memory (pc + delta, &op, 1)) |
1578 | return pc; | |
c906108c | 1579 | |
c5aa993b | 1580 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1581 | { |
e17a4113 | 1582 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1583 | |
fc338970 | 1584 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1585 | delta += 3; |
fc338970 | 1586 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1587 | delta += 6; |
fc338970 | 1588 | else /* Unexpected instruction. */ |
acd5c798 MK |
1589 | delta = 0; |
1590 | ||
3dcabaa8 MS |
1591 | if (target_read_memory (pc + delta, &op, 1)) |
1592 | return pc; | |
c906108c | 1593 | } |
acd5c798 | 1594 | |
c5aa993b | 1595 | /* addl y,%ebx */ |
acd5c798 | 1596 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1597 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1598 | == 0xc3) | |
c906108c | 1599 | { |
acd5c798 | 1600 | pc += delta + 6; |
c906108c SS |
1601 | } |
1602 | } | |
c5aa993b | 1603 | |
e63bbc88 MK |
1604 | /* If the function starts with a branch (to startup code at the end) |
1605 | the last instruction should bring us back to the first | |
1606 | instruction of the real code. */ | |
e17a4113 UW |
1607 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1608 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1609 | |
1610 | return pc; | |
c906108c SS |
1611 | } |
1612 | ||
4309257c PM |
1613 | /* Check that the code pointed to by PC corresponds to a call to |
1614 | __main, skip it if so. Return PC otherwise. */ | |
1615 | ||
1616 | CORE_ADDR | |
1617 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1618 | { | |
e17a4113 | 1619 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1620 | gdb_byte op; |
1621 | ||
3dcabaa8 MS |
1622 | if (target_read_memory (pc, &op, 1)) |
1623 | return pc; | |
4309257c PM |
1624 | if (op == 0xe8) |
1625 | { | |
1626 | gdb_byte buf[4]; | |
1627 | ||
1628 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1629 | { | |
1630 | /* Make sure address is computed correctly as a 32bit | |
1631 | integer even if CORE_ADDR is 64 bit wide. */ | |
1632 | struct minimal_symbol *s; | |
e17a4113 | 1633 | CORE_ADDR call_dest; |
4309257c | 1634 | |
e17a4113 | 1635 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1636 | call_dest = call_dest & 0xffffffffU; |
1637 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1638 | if (s != NULL | |
1639 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1640 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1641 | pc += 5; | |
1642 | } | |
1643 | } | |
1644 | ||
1645 | return pc; | |
1646 | } | |
1647 | ||
acd5c798 | 1648 | /* This function is 64-bit safe. */ |
93924b6b | 1649 | |
acd5c798 MK |
1650 | static CORE_ADDR |
1651 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1652 | { |
63c0089f | 1653 | gdb_byte buf[8]; |
acd5c798 | 1654 | |
875f8d0e | 1655 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1656 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1657 | } |
acd5c798 | 1658 | \f |
93924b6b | 1659 | |
acd5c798 | 1660 | /* Normal frames. */ |
c5aa993b | 1661 | |
8fbca658 PA |
1662 | static void |
1663 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1664 | struct i386_frame_cache *cache) | |
a7769679 | 1665 | { |
e17a4113 UW |
1666 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1667 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1668 | gdb_byte buf[4]; |
acd5c798 MK |
1669 | int i; |
1670 | ||
8fbca658 | 1671 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1672 | |
1673 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1674 | which holds the base address for the current stack frame. | |
1675 | However, for functions that don't need it, the frame pointer is | |
1676 | optional. For these "frameless" functions the frame pointer is | |
1677 | actually the frame pointer of the calling frame. Signal | |
1678 | trampolines are just a special case of a "frameless" function. | |
1679 | They (usually) share their frame pointer with the frame that was | |
1680 | in progress when the signal occurred. */ | |
1681 | ||
10458914 | 1682 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1683 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1684 | if (cache->base == 0) |
8fbca658 | 1685 | return; |
acd5c798 MK |
1686 | |
1687 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1688 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1689 | |
acd5c798 | 1690 | if (cache->pc != 0) |
e17a4113 UW |
1691 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1692 | cache); | |
acd5c798 MK |
1693 | |
1694 | if (cache->locals < 0) | |
1695 | { | |
1696 | /* We didn't find a valid frame, which means that CACHE->base | |
1697 | currently holds the frame pointer for our calling frame. If | |
1698 | we're at the start of a function, or somewhere half-way its | |
1699 | prologue, the function's frame probably hasn't been fully | |
1700 | setup yet. Try to reconstruct the base address for the stack | |
1701 | frame by looking at the stack pointer. For truly "frameless" | |
1702 | functions this might work too. */ | |
1703 | ||
e0c62198 | 1704 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1705 | { |
8fbca658 PA |
1706 | /* Saved stack pointer has been saved. */ |
1707 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
1708 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1709 | ||
92dd43fa MK |
1710 | /* We're halfway aligning the stack. */ |
1711 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1712 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1713 | ||
1714 | /* This will be added back below. */ | |
1715 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1716 | } | |
7618e12b DJ |
1717 | else if (cache->pc != 0 |
1718 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1719 | { |
7618e12b DJ |
1720 | /* We're in a known function, but did not find a frame |
1721 | setup. Assume that the function does not use %ebp. | |
1722 | Alternatively, we may have jumped to an invalid | |
1723 | address; in that case there is definitely no new | |
1724 | frame in %ebp. */ | |
10458914 | 1725 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1726 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1727 | + cache->sp_offset; | |
92dd43fa | 1728 | } |
7618e12b DJ |
1729 | else |
1730 | /* We're in an unknown function. We could not find the start | |
1731 | of the function to analyze the prologue; our best option is | |
1732 | to assume a typical frame layout with the caller's %ebp | |
1733 | saved. */ | |
1734 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1735 | } |
1736 | ||
8fbca658 PA |
1737 | if (cache->saved_sp_reg != -1) |
1738 | { | |
1739 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
1740 | register may be unavailable). */ | |
1741 | if (cache->saved_sp == 0 | |
1742 | && frame_register_read (this_frame, cache->saved_sp_reg, buf)) | |
1743 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1744 | } | |
acd5c798 MK |
1745 | /* Now that we have the base address for the stack frame we can |
1746 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 1747 | else if (cache->saved_sp == 0) |
92dd43fa | 1748 | cache->saved_sp = cache->base + 8; |
a7769679 | 1749 | |
acd5c798 MK |
1750 | /* Adjust all the saved registers such that they contain addresses |
1751 | instead of offsets. */ | |
1752 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1753 | if (cache->saved_regs[i] != -1) |
1754 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 1755 | |
8fbca658 PA |
1756 | cache->base_p = 1; |
1757 | } | |
1758 | ||
1759 | static struct i386_frame_cache * | |
1760 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1761 | { | |
1762 | volatile struct gdb_exception ex; | |
1763 | struct i386_frame_cache *cache; | |
1764 | ||
1765 | if (*this_cache) | |
1766 | return *this_cache; | |
1767 | ||
1768 | cache = i386_alloc_frame_cache (); | |
1769 | *this_cache = cache; | |
1770 | ||
1771 | TRY_CATCH (ex, RETURN_MASK_ERROR) | |
1772 | { | |
1773 | i386_frame_cache_1 (this_frame, cache); | |
1774 | } | |
1775 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1776 | throw_exception (ex); | |
1777 | ||
acd5c798 | 1778 | return cache; |
a7769679 MK |
1779 | } |
1780 | ||
3a1e71e3 | 1781 | static void |
10458914 | 1782 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1783 | struct frame_id *this_id) |
c906108c | 1784 | { |
10458914 | 1785 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1786 | |
1787 | /* This marks the outermost frame. */ | |
1788 | if (cache->base == 0) | |
1789 | return; | |
1790 | ||
3e210248 | 1791 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1792 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1793 | } | |
1794 | ||
8fbca658 PA |
1795 | static enum unwind_stop_reason |
1796 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1797 | void **this_cache) | |
1798 | { | |
1799 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
1800 | ||
1801 | if (!cache->base_p) | |
1802 | return UNWIND_UNAVAILABLE; | |
1803 | ||
1804 | /* This marks the outermost frame. */ | |
1805 | if (cache->base == 0) | |
1806 | return UNWIND_OUTERMOST; | |
1807 | ||
1808 | return UNWIND_NO_REASON; | |
1809 | } | |
1810 | ||
10458914 DJ |
1811 | static struct value * |
1812 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1813 | int regnum) | |
acd5c798 | 1814 | { |
10458914 | 1815 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1816 | |
1817 | gdb_assert (regnum >= 0); | |
1818 | ||
1819 | /* The System V ABI says that: | |
1820 | ||
1821 | "The flags register contains the system flags, such as the | |
1822 | direction flag and the carry flag. The direction flag must be | |
1823 | set to the forward (that is, zero) direction before entry and | |
1824 | upon exit from a function. Other user flags have no specified | |
1825 | role in the standard calling sequence and are not preserved." | |
1826 | ||
1827 | To guarantee the "upon exit" part of that statement we fake a | |
1828 | saved flags register that has its direction flag cleared. | |
1829 | ||
1830 | Note that GCC doesn't seem to rely on the fact that the direction | |
1831 | flag is cleared after a function return; it always explicitly | |
1832 | clears the flag before operations where it matters. | |
1833 | ||
1834 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1835 | right thing to do. The way we fake the flags register here makes | |
1836 | it impossible to change it. */ | |
1837 | ||
1838 | if (regnum == I386_EFLAGS_REGNUM) | |
1839 | { | |
10458914 | 1840 | ULONGEST val; |
c5aa993b | 1841 | |
10458914 DJ |
1842 | val = get_frame_register_unsigned (this_frame, regnum); |
1843 | val &= ~(1 << 10); | |
1844 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1845 | } |
1211c4e4 | 1846 | |
acd5c798 | 1847 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1848 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 1849 | |
fcf250e2 UW |
1850 | if (regnum == I386_ESP_REGNUM |
1851 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
1852 | { |
1853 | /* If the SP has been saved, but we don't know where, then this | |
1854 | means that SAVED_SP_REG register was found unavailable back | |
1855 | when we built the cache. */ | |
fcf250e2 | 1856 | if (cache->saved_sp == 0) |
8fbca658 PA |
1857 | return frame_unwind_got_register (this_frame, regnum, |
1858 | cache->saved_sp_reg); | |
1859 | else | |
1860 | return frame_unwind_got_constant (this_frame, regnum, | |
1861 | cache->saved_sp); | |
1862 | } | |
acd5c798 | 1863 | |
fd13a04a | 1864 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1865 | return frame_unwind_got_memory (this_frame, regnum, |
1866 | cache->saved_regs[regnum]); | |
fd13a04a | 1867 | |
10458914 | 1868 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1869 | } |
1870 | ||
1871 | static const struct frame_unwind i386_frame_unwind = | |
1872 | { | |
1873 | NORMAL_FRAME, | |
8fbca658 | 1874 | i386_frame_unwind_stop_reason, |
acd5c798 | 1875 | i386_frame_this_id, |
10458914 DJ |
1876 | i386_frame_prev_register, |
1877 | NULL, | |
1878 | default_frame_sniffer | |
acd5c798 | 1879 | }; |
06da04c6 MS |
1880 | |
1881 | /* Normal frames, but in a function epilogue. */ | |
1882 | ||
1883 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1884 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1885 | the function's stack frame. */ | |
1886 | ||
1887 | static int | |
1888 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1889 | { | |
1890 | gdb_byte insn; | |
e0d00bc7 JK |
1891 | struct symtab *symtab; |
1892 | ||
1893 | symtab = find_pc_symtab (pc); | |
1894 | if (symtab && symtab->epilogue_unwind_valid) | |
1895 | return 0; | |
06da04c6 MS |
1896 | |
1897 | if (target_read_memory (pc, &insn, 1)) | |
1898 | return 0; /* Can't read memory at pc. */ | |
1899 | ||
1900 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1901 | return 0; | |
1902 | ||
1903 | return 1; | |
1904 | } | |
1905 | ||
1906 | static int | |
1907 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1908 | struct frame_info *this_frame, | |
1909 | void **this_prologue_cache) | |
1910 | { | |
1911 | if (frame_relative_level (this_frame) == 0) | |
1912 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1913 | get_frame_pc (this_frame)); | |
1914 | else | |
1915 | return 0; | |
1916 | } | |
1917 | ||
1918 | static struct i386_frame_cache * | |
1919 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1920 | { | |
8fbca658 | 1921 | volatile struct gdb_exception ex; |
06da04c6 | 1922 | struct i386_frame_cache *cache; |
0d6c2135 | 1923 | CORE_ADDR sp; |
06da04c6 MS |
1924 | |
1925 | if (*this_cache) | |
1926 | return *this_cache; | |
1927 | ||
1928 | cache = i386_alloc_frame_cache (); | |
1929 | *this_cache = cache; | |
1930 | ||
8fbca658 PA |
1931 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
1932 | { | |
0d6c2135 | 1933 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 1934 | |
0d6c2135 MK |
1935 | /* At this point the stack looks as if we just entered the |
1936 | function, with the return address at the top of the | |
1937 | stack. */ | |
1938 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
1939 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 1940 | cache->saved_sp = cache->base + 8; |
8fbca658 | 1941 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 1942 | |
8fbca658 PA |
1943 | cache->base_p = 1; |
1944 | } | |
1945 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1946 | throw_exception (ex); | |
06da04c6 MS |
1947 | |
1948 | return cache; | |
1949 | } | |
1950 | ||
8fbca658 PA |
1951 | static enum unwind_stop_reason |
1952 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1953 | void **this_cache) | |
1954 | { | |
0d6c2135 MK |
1955 | struct i386_frame_cache *cache = |
1956 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
1957 | |
1958 | if (!cache->base_p) | |
1959 | return UNWIND_UNAVAILABLE; | |
1960 | ||
1961 | return UNWIND_NO_REASON; | |
1962 | } | |
1963 | ||
06da04c6 MS |
1964 | static void |
1965 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1966 | void **this_cache, | |
1967 | struct frame_id *this_id) | |
1968 | { | |
0d6c2135 MK |
1969 | struct i386_frame_cache *cache = |
1970 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 1971 | |
8fbca658 PA |
1972 | if (!cache->base_p) |
1973 | return; | |
1974 | ||
06da04c6 MS |
1975 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1976 | } | |
1977 | ||
0d6c2135 MK |
1978 | static struct value * |
1979 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
1980 | void **this_cache, int regnum) | |
1981 | { | |
1982 | /* Make sure we've initialized the cache. */ | |
1983 | i386_epilogue_frame_cache (this_frame, this_cache); | |
1984 | ||
1985 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
1986 | } | |
1987 | ||
06da04c6 MS |
1988 | static const struct frame_unwind i386_epilogue_frame_unwind = |
1989 | { | |
1990 | NORMAL_FRAME, | |
8fbca658 | 1991 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 1992 | i386_epilogue_frame_this_id, |
0d6c2135 | 1993 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
1994 | NULL, |
1995 | i386_epilogue_frame_sniffer | |
1996 | }; | |
acd5c798 MK |
1997 | \f |
1998 | ||
a3fcb948 JG |
1999 | /* Stack-based trampolines. */ |
2000 | ||
2001 | /* These trampolines are used on cross x86 targets, when taking the | |
2002 | address of a nested function. When executing these trampolines, | |
2003 | no stack frame is set up, so we are in a similar situation as in | |
2004 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2005 | ||
2006 | /* Static chain passed in register. */ | |
2007 | ||
2008 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2009 | { | |
2010 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2011 | { 5, { 0xb8 }, { 0xfe } }, | |
2012 | ||
2013 | /* `jmp imm32' */ | |
2014 | { 5, { 0xe9 }, { 0xff } }, | |
2015 | ||
2016 | {0} | |
2017 | }; | |
2018 | ||
2019 | /* Static chain passed on stack (when regparm=3). */ | |
2020 | ||
2021 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2022 | { | |
2023 | /* `push imm32' */ | |
2024 | { 5, { 0x68 }, { 0xff } }, | |
2025 | ||
2026 | /* `jmp imm32' */ | |
2027 | { 5, { 0xe9 }, { 0xff } }, | |
2028 | ||
2029 | {0} | |
2030 | }; | |
2031 | ||
2032 | /* Return whether PC points inside a stack trampoline. */ | |
2033 | ||
2034 | static int | |
2035 | i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2036 | { | |
2037 | gdb_byte insn; | |
2038 | char *name; | |
2039 | ||
2040 | /* A stack trampoline is detected if no name is associated | |
2041 | to the current pc and if it points inside a trampoline | |
2042 | sequence. */ | |
2043 | ||
2044 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2045 | if (name) | |
2046 | return 0; | |
2047 | ||
2048 | if (target_read_memory (pc, &insn, 1)) | |
2049 | return 0; | |
2050 | ||
2051 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2052 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2053 | return 0; | |
2054 | ||
2055 | return 1; | |
2056 | } | |
2057 | ||
2058 | static int | |
2059 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2060 | struct frame_info *this_frame, |
2061 | void **this_cache) | |
a3fcb948 JG |
2062 | { |
2063 | if (frame_relative_level (this_frame) == 0) | |
2064 | return i386_in_stack_tramp_p (get_frame_arch (this_frame), | |
2065 | get_frame_pc (this_frame)); | |
2066 | else | |
2067 | return 0; | |
2068 | } | |
2069 | ||
2070 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2071 | { | |
2072 | NORMAL_FRAME, | |
2073 | i386_epilogue_frame_unwind_stop_reason, | |
2074 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2075 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2076 | NULL, |
2077 | i386_stack_tramp_frame_sniffer | |
2078 | }; | |
2079 | \f | |
6710bf39 SS |
2080 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2081 | ||
2082 | static void | |
2083 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2084 | struct agent_expr *ax, struct axs_value *value, | |
2085 | CORE_ADDR scope) | |
2086 | { | |
2087 | /* The following sequence assumes the traditional use of the base | |
2088 | register. */ | |
2089 | ax_reg (ax, I386_EBP_REGNUM); | |
2090 | ax_const_l (ax, 4); | |
2091 | ax_simple (ax, aop_add); | |
2092 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2093 | value->kind = axs_lvalue_memory; | |
2094 | } | |
2095 | \f | |
a3fcb948 | 2096 | |
acd5c798 MK |
2097 | /* Signal trampolines. */ |
2098 | ||
2099 | static struct i386_frame_cache * | |
10458914 | 2100 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2101 | { |
e17a4113 UW |
2102 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2103 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2104 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2105 | volatile struct gdb_exception ex; |
acd5c798 | 2106 | struct i386_frame_cache *cache; |
acd5c798 | 2107 | CORE_ADDR addr; |
63c0089f | 2108 | gdb_byte buf[4]; |
acd5c798 MK |
2109 | |
2110 | if (*this_cache) | |
2111 | return *this_cache; | |
2112 | ||
fd13a04a | 2113 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2114 | |
8fbca658 | 2115 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
a3386186 | 2116 | { |
8fbca658 PA |
2117 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2118 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2119 | |
8fbca658 PA |
2120 | addr = tdep->sigcontext_addr (this_frame); |
2121 | if (tdep->sc_reg_offset) | |
2122 | { | |
2123 | int i; | |
a3386186 | 2124 | |
8fbca658 PA |
2125 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2126 | ||
2127 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2128 | if (tdep->sc_reg_offset[i] != -1) | |
2129 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2130 | } | |
2131 | else | |
2132 | { | |
2133 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2134 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2135 | } | |
2136 | ||
2137 | cache->base_p = 1; | |
a3386186 | 2138 | } |
8fbca658 PA |
2139 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
2140 | throw_exception (ex); | |
acd5c798 MK |
2141 | |
2142 | *this_cache = cache; | |
2143 | return cache; | |
2144 | } | |
2145 | ||
8fbca658 PA |
2146 | static enum unwind_stop_reason |
2147 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2148 | void **this_cache) | |
2149 | { | |
2150 | struct i386_frame_cache *cache = | |
2151 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2152 | ||
2153 | if (!cache->base_p) | |
2154 | return UNWIND_UNAVAILABLE; | |
2155 | ||
2156 | return UNWIND_NO_REASON; | |
2157 | } | |
2158 | ||
acd5c798 | 2159 | static void |
10458914 | 2160 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2161 | struct frame_id *this_id) |
2162 | { | |
2163 | struct i386_frame_cache *cache = | |
10458914 | 2164 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2165 | |
8fbca658 PA |
2166 | if (!cache->base_p) |
2167 | return; | |
2168 | ||
3e210248 | 2169 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2170 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
2171 | } |
2172 | ||
10458914 DJ |
2173 | static struct value * |
2174 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2175 | void **this_cache, int regnum) | |
acd5c798 MK |
2176 | { |
2177 | /* Make sure we've initialized the cache. */ | |
10458914 | 2178 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2179 | |
10458914 | 2180 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2181 | } |
c0d1d883 | 2182 | |
10458914 DJ |
2183 | static int |
2184 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2185 | struct frame_info *this_frame, | |
2186 | void **this_prologue_cache) | |
acd5c798 | 2187 | { |
10458914 | 2188 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2189 | |
911bc6ee MK |
2190 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2191 | handler. */ | |
2192 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2193 | return 0; |
1c3545ae | 2194 | |
911bc6ee MK |
2195 | if (tdep->sigtramp_p != NULL) |
2196 | { | |
10458914 DJ |
2197 | if (tdep->sigtramp_p (this_frame)) |
2198 | return 1; | |
911bc6ee MK |
2199 | } |
2200 | ||
2201 | if (tdep->sigtramp_start != 0) | |
2202 | { | |
10458914 | 2203 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2204 | |
2205 | gdb_assert (tdep->sigtramp_end != 0); | |
2206 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2207 | return 1; |
911bc6ee | 2208 | } |
acd5c798 | 2209 | |
10458914 | 2210 | return 0; |
acd5c798 | 2211 | } |
10458914 DJ |
2212 | |
2213 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2214 | { | |
2215 | SIGTRAMP_FRAME, | |
8fbca658 | 2216 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2217 | i386_sigtramp_frame_this_id, |
2218 | i386_sigtramp_frame_prev_register, | |
2219 | NULL, | |
2220 | i386_sigtramp_frame_sniffer | |
2221 | }; | |
acd5c798 MK |
2222 | \f |
2223 | ||
2224 | static CORE_ADDR | |
10458914 | 2225 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2226 | { |
10458914 | 2227 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2228 | |
2229 | return cache->base; | |
2230 | } | |
2231 | ||
2232 | static const struct frame_base i386_frame_base = | |
2233 | { | |
2234 | &i386_frame_unwind, | |
2235 | i386_frame_base_address, | |
2236 | i386_frame_base_address, | |
2237 | i386_frame_base_address | |
2238 | }; | |
2239 | ||
acd5c798 | 2240 | static struct frame_id |
10458914 | 2241 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2242 | { |
acd5c798 MK |
2243 | CORE_ADDR fp; |
2244 | ||
10458914 | 2245 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2246 | |
3e210248 | 2247 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2248 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2249 | } |
e04e5beb JM |
2250 | |
2251 | /* _Decimal128 function return values need 16-byte alignment on the | |
2252 | stack. */ | |
2253 | ||
2254 | static CORE_ADDR | |
2255 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2256 | { | |
2257 | return sp & -(CORE_ADDR)16; | |
2258 | } | |
fc338970 | 2259 | \f |
c906108c | 2260 | |
fc338970 MK |
2261 | /* Figure out where the longjmp will land. Slurp the args out of the |
2262 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2263 | structure from which we extract the address that we will land at. |
28bcfd30 | 2264 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2265 | success. */ |
c906108c | 2266 | |
8201327c | 2267 | static int |
60ade65d | 2268 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2269 | { |
436675d3 | 2270 | gdb_byte buf[4]; |
c906108c | 2271 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2272 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2273 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2274 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2275 | |
8201327c MK |
2276 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2277 | longjmp will land. */ | |
2278 | if (jb_pc_offset == -1) | |
c906108c SS |
2279 | return 0; |
2280 | ||
436675d3 | 2281 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2282 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2283 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2284 | return 0; |
2285 | ||
e17a4113 | 2286 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2287 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2288 | return 0; |
c906108c | 2289 | |
e17a4113 | 2290 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2291 | return 1; |
2292 | } | |
fc338970 | 2293 | \f |
c906108c | 2294 | |
7ccc1c74 JM |
2295 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2296 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2297 | unions containing such types must be 16-byte-aligned; other | |
2298 | arguments are 4-byte-aligned. */ | |
2299 | ||
2300 | static int | |
2301 | i386_16_byte_align_p (struct type *type) | |
2302 | { | |
2303 | type = check_typedef (type); | |
2304 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2305 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2306 | && TYPE_LENGTH (type) == 16) | |
2307 | return 1; | |
2308 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2309 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2310 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2311 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2312 | { | |
2313 | int i; | |
2314 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2315 | { | |
2316 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2317 | return 1; | |
2318 | } | |
2319 | } | |
2320 | return 0; | |
2321 | } | |
2322 | ||
3a1e71e3 | 2323 | static CORE_ADDR |
7d9b040b | 2324 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2325 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2326 | struct value **args, CORE_ADDR sp, int struct_return, | |
2327 | CORE_ADDR struct_addr) | |
22f8ba57 | 2328 | { |
e17a4113 | 2329 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2330 | gdb_byte buf[4]; |
acd5c798 | 2331 | int i; |
7ccc1c74 JM |
2332 | int write_pass; |
2333 | int args_space = 0; | |
acd5c798 | 2334 | |
7ccc1c74 JM |
2335 | /* Determine the total space required for arguments and struct |
2336 | return address in a first pass (allowing for 16-byte-aligned | |
2337 | arguments), then push arguments in a second pass. */ | |
2338 | ||
2339 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2340 | { |
7ccc1c74 JM |
2341 | int args_space_used = 0; |
2342 | int have_16_byte_aligned_arg = 0; | |
2343 | ||
2344 | if (struct_return) | |
2345 | { | |
2346 | if (write_pass) | |
2347 | { | |
2348 | /* Push value address. */ | |
e17a4113 | 2349 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2350 | write_memory (sp, buf, 4); |
2351 | args_space_used += 4; | |
2352 | } | |
2353 | else | |
2354 | args_space += 4; | |
2355 | } | |
2356 | ||
2357 | for (i = 0; i < nargs; i++) | |
2358 | { | |
2359 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2360 | |
7ccc1c74 JM |
2361 | if (write_pass) |
2362 | { | |
2363 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2364 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2365 | |
7ccc1c74 JM |
2366 | write_memory (sp + args_space_used, |
2367 | value_contents_all (args[i]), len); | |
2368 | /* The System V ABI says that: | |
acd5c798 | 2369 | |
7ccc1c74 JM |
2370 | "An argument's size is increased, if necessary, to make it a |
2371 | multiple of [32-bit] words. This may require tail padding, | |
2372 | depending on the size of the argument." | |
22f8ba57 | 2373 | |
7ccc1c74 JM |
2374 | This makes sure the stack stays word-aligned. */ |
2375 | args_space_used += align_up (len, 4); | |
2376 | } | |
2377 | else | |
2378 | { | |
2379 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2380 | { | |
2381 | args_space = align_up (args_space, 16); | |
2382 | have_16_byte_aligned_arg = 1; | |
2383 | } | |
2384 | args_space += align_up (len, 4); | |
2385 | } | |
2386 | } | |
2387 | ||
2388 | if (!write_pass) | |
2389 | { | |
2390 | if (have_16_byte_aligned_arg) | |
2391 | args_space = align_up (args_space, 16); | |
2392 | sp -= args_space; | |
2393 | } | |
22f8ba57 MK |
2394 | } |
2395 | ||
acd5c798 MK |
2396 | /* Store return address. */ |
2397 | sp -= 4; | |
e17a4113 | 2398 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2399 | write_memory (sp, buf, 4); |
2400 | ||
2401 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2402 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2403 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2404 | ||
2405 | /* ...and fake a frame pointer. */ | |
2406 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2407 | ||
3e210248 AC |
2408 | /* MarkK wrote: This "+ 8" is all over the place: |
2409 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2410 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2411 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2412 | definition of the stack address of a frame. Otherwise frame id |
2413 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2414 | stack address *before* the function call as a frame's CFA. On |
2415 | the i386, when %ebp is used as a frame pointer, the offset | |
2416 | between the contents %ebp and the CFA as defined by GCC. */ | |
2417 | return sp + 8; | |
22f8ba57 MK |
2418 | } |
2419 | ||
1a309862 MK |
2420 | /* These registers are used for returning integers (and on some |
2421 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2422 | size and alignment match an integer type). */ |
acd5c798 MK |
2423 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2424 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2425 | |
c5e656c1 MK |
2426 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2427 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2428 | |
3a1e71e3 | 2429 | static void |
c5e656c1 | 2430 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2431 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2432 | { |
c5e656c1 | 2433 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2434 | int len = TYPE_LENGTH (type); |
63c0089f | 2435 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2436 | |
1e8d0a7b | 2437 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2438 | { |
5716833c | 2439 | if (tdep->st0_regnum < 0) |
1a309862 | 2440 | { |
8a3fe4f8 | 2441 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2442 | memset (valbuf, 0, len); |
ef9dff19 | 2443 | return; |
1a309862 MK |
2444 | } |
2445 | ||
c6ba6f0d MK |
2446 | /* Floating-point return values can be found in %st(0). Convert |
2447 | its contents to the desired type. This is probably not | |
2448 | exactly how it would happen on the target itself, but it is | |
2449 | the best we can do. */ | |
acd5c798 | 2450 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2451 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2452 | } |
2453 | else | |
c5aa993b | 2454 | { |
875f8d0e UW |
2455 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2456 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2457 | |
2458 | if (len <= low_size) | |
00f8375e | 2459 | { |
0818c12a | 2460 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2461 | memcpy (valbuf, buf, len); |
2462 | } | |
d4f3574e SS |
2463 | else if (len <= (low_size + high_size)) |
2464 | { | |
0818c12a | 2465 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2466 | memcpy (valbuf, buf, low_size); |
0818c12a | 2467 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2468 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2469 | } |
2470 | else | |
8e65ff28 | 2471 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2472 | _("Cannot extract return value of %d bytes long."), |
2473 | len); | |
c906108c SS |
2474 | } |
2475 | } | |
2476 | ||
c5e656c1 MK |
2477 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2478 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2479 | |
3a1e71e3 | 2480 | static void |
c5e656c1 | 2481 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2482 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2483 | { |
c5e656c1 | 2484 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2485 | int len = TYPE_LENGTH (type); |
2486 | ||
1e8d0a7b | 2487 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2488 | { |
3d7f4f49 | 2489 | ULONGEST fstat; |
63c0089f | 2490 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2491 | |
5716833c | 2492 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2493 | { |
8a3fe4f8 | 2494 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2495 | return; |
2496 | } | |
2497 | ||
635b0cc1 MK |
2498 | /* Returning floating-point values is a bit tricky. Apart from |
2499 | storing the return value in %st(0), we have to simulate the | |
2500 | state of the FPU at function return point. */ | |
2501 | ||
c6ba6f0d MK |
2502 | /* Convert the value found in VALBUF to the extended |
2503 | floating-point format used by the FPU. This is probably | |
2504 | not exactly how it would happen on the target itself, but | |
2505 | it is the best we can do. */ | |
27067745 | 2506 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2507 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2508 | |
635b0cc1 MK |
2509 | /* Set the top of the floating-point register stack to 7. The |
2510 | actual value doesn't really matter, but 7 is what a normal | |
2511 | function return would end up with if the program started out | |
2512 | with a freshly initialized FPU. */ | |
20a6ec49 | 2513 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2514 | fstat |= (7 << 11); |
20a6ec49 | 2515 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2516 | |
635b0cc1 MK |
2517 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2518 | the floating-point register stack to 7, the appropriate value | |
2519 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2520 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2521 | } |
2522 | else | |
2523 | { | |
875f8d0e UW |
2524 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2525 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2526 | |
2527 | if (len <= low_size) | |
3d7f4f49 | 2528 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2529 | else if (len <= (low_size + high_size)) |
2530 | { | |
3d7f4f49 MK |
2531 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2532 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2533 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2534 | } |
2535 | else | |
8e65ff28 | 2536 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2537 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2538 | } |
2539 | } | |
fc338970 | 2540 | \f |
ef9dff19 | 2541 | |
8201327c MK |
2542 | /* This is the variable that is set with "set struct-convention", and |
2543 | its legitimate values. */ | |
2544 | static const char default_struct_convention[] = "default"; | |
2545 | static const char pcc_struct_convention[] = "pcc"; | |
2546 | static const char reg_struct_convention[] = "reg"; | |
2547 | static const char *valid_conventions[] = | |
2548 | { | |
2549 | default_struct_convention, | |
2550 | pcc_struct_convention, | |
2551 | reg_struct_convention, | |
2552 | NULL | |
2553 | }; | |
2554 | static const char *struct_convention = default_struct_convention; | |
2555 | ||
0e4377e1 JB |
2556 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2557 | a union type, or an array type, should be returned in registers | |
2558 | for architecture GDBARCH. */ | |
c5e656c1 | 2559 | |
8201327c | 2560 | static int |
c5e656c1 | 2561 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2562 | { |
c5e656c1 MK |
2563 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2564 | enum type_code code = TYPE_CODE (type); | |
2565 | int len = TYPE_LENGTH (type); | |
8201327c | 2566 | |
0e4377e1 JB |
2567 | gdb_assert (code == TYPE_CODE_STRUCT |
2568 | || code == TYPE_CODE_UNION | |
2569 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2570 | |
2571 | if (struct_convention == pcc_struct_convention | |
2572 | || (struct_convention == default_struct_convention | |
2573 | && tdep->struct_return == pcc_struct_return)) | |
2574 | return 0; | |
2575 | ||
9edde48e MK |
2576 | /* Structures consisting of a single `float', `double' or 'long |
2577 | double' member are returned in %st(0). */ | |
2578 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2579 | { | |
2580 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2581 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2582 | return (len == 4 || len == 8 || len == 12); | |
2583 | } | |
2584 | ||
c5e656c1 MK |
2585 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2586 | } | |
2587 | ||
2588 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2589 | should be returned. If it is supposed to be returned in registers, | |
2590 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2591 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2592 | from WRITEBUF into REGCACHE. */ | |
2593 | ||
2594 | static enum return_value_convention | |
c055b101 CV |
2595 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2596 | struct type *type, struct regcache *regcache, | |
2597 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2598 | { |
2599 | enum type_code code = TYPE_CODE (type); | |
2600 | ||
5daa78cc TJB |
2601 | if (((code == TYPE_CODE_STRUCT |
2602 | || code == TYPE_CODE_UNION | |
2603 | || code == TYPE_CODE_ARRAY) | |
2604 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2605 | /* 128-bit decimal float uses the struct return convention. */ | |
2606 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2607 | { |
2608 | /* The System V ABI says that: | |
2609 | ||
2610 | "A function that returns a structure or union also sets %eax | |
2611 | to the value of the original address of the caller's area | |
2612 | before it returns. Thus when the caller receives control | |
2613 | again, the address of the returned object resides in register | |
2614 | %eax and can be used to access the object." | |
2615 | ||
2616 | So the ABI guarantees that we can always find the return | |
2617 | value just after the function has returned. */ | |
2618 | ||
0e4377e1 JB |
2619 | /* Note that the ABI doesn't mention functions returning arrays, |
2620 | which is something possible in certain languages such as Ada. | |
2621 | In this case, the value is returned as if it was wrapped in | |
2622 | a record, so the convention applied to records also applies | |
2623 | to arrays. */ | |
2624 | ||
31db7b6c MK |
2625 | if (readbuf) |
2626 | { | |
2627 | ULONGEST addr; | |
2628 | ||
2629 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2630 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2631 | } | |
2632 | ||
2633 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2634 | } | |
c5e656c1 MK |
2635 | |
2636 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2637 | `float', `double' or 'long double' member. These structures are |
2638 | returned in %st(0). For these structures, we call ourselves | |
2639 | recursively, changing TYPE into the type of the first member of | |
2640 | the structure. Since that should work for all structures that | |
2641 | have only one member, we don't bother to check the member's type | |
2642 | here. */ | |
c5e656c1 MK |
2643 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2644 | { | |
2645 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2646 | return i386_return_value (gdbarch, func_type, type, regcache, |
2647 | readbuf, writebuf); | |
c5e656c1 MK |
2648 | } |
2649 | ||
2650 | if (readbuf) | |
2651 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2652 | if (writebuf) | |
2653 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2654 | |
c5e656c1 | 2655 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2656 | } |
2657 | \f | |
2658 | ||
27067745 UW |
2659 | struct type * |
2660 | i387_ext_type (struct gdbarch *gdbarch) | |
2661 | { | |
2662 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2663 | ||
2664 | if (!tdep->i387_ext_type) | |
90884b2b L |
2665 | { |
2666 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2667 | gdb_assert (tdep->i387_ext_type != NULL); | |
2668 | } | |
27067745 UW |
2669 | |
2670 | return tdep->i387_ext_type; | |
2671 | } | |
2672 | ||
c131fcee L |
2673 | /* Construct vector type for pseudo YMM registers. We can't use |
2674 | tdesc_find_type since YMM isn't described in target description. */ | |
2675 | ||
2676 | static struct type * | |
2677 | i386_ymm_type (struct gdbarch *gdbarch) | |
2678 | { | |
2679 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2680 | ||
2681 | if (!tdep->i386_ymm_type) | |
2682 | { | |
2683 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2684 | ||
2685 | /* The type we're building is this: */ | |
2686 | #if 0 | |
2687 | union __gdb_builtin_type_vec256i | |
2688 | { | |
2689 | int128_t uint128[2]; | |
2690 | int64_t v2_int64[4]; | |
2691 | int32_t v4_int32[8]; | |
2692 | int16_t v8_int16[16]; | |
2693 | int8_t v16_int8[32]; | |
2694 | double v2_double[4]; | |
2695 | float v4_float[8]; | |
2696 | }; | |
2697 | #endif | |
2698 | ||
2699 | struct type *t; | |
2700 | ||
2701 | t = arch_composite_type (gdbarch, | |
2702 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2703 | append_composite_type_field (t, "v8_float", | |
2704 | init_vector_type (bt->builtin_float, 8)); | |
2705 | append_composite_type_field (t, "v4_double", | |
2706 | init_vector_type (bt->builtin_double, 4)); | |
2707 | append_composite_type_field (t, "v32_int8", | |
2708 | init_vector_type (bt->builtin_int8, 32)); | |
2709 | append_composite_type_field (t, "v16_int16", | |
2710 | init_vector_type (bt->builtin_int16, 16)); | |
2711 | append_composite_type_field (t, "v8_int32", | |
2712 | init_vector_type (bt->builtin_int32, 8)); | |
2713 | append_composite_type_field (t, "v4_int64", | |
2714 | init_vector_type (bt->builtin_int64, 4)); | |
2715 | append_composite_type_field (t, "v2_int128", | |
2716 | init_vector_type (bt->builtin_int128, 2)); | |
2717 | ||
2718 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 2719 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
2720 | tdep->i386_ymm_type = t; |
2721 | } | |
2722 | ||
2723 | return tdep->i386_ymm_type; | |
2724 | } | |
2725 | ||
794ac428 | 2726 | /* Construct vector type for MMX registers. */ |
90884b2b | 2727 | static struct type * |
794ac428 UW |
2728 | i386_mmx_type (struct gdbarch *gdbarch) |
2729 | { | |
2730 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2731 | ||
2732 | if (!tdep->i386_mmx_type) | |
2733 | { | |
df4df182 UW |
2734 | const struct builtin_type *bt = builtin_type (gdbarch); |
2735 | ||
794ac428 UW |
2736 | /* The type we're building is this: */ |
2737 | #if 0 | |
2738 | union __gdb_builtin_type_vec64i | |
2739 | { | |
2740 | int64_t uint64; | |
2741 | int32_t v2_int32[2]; | |
2742 | int16_t v4_int16[4]; | |
2743 | int8_t v8_int8[8]; | |
2744 | }; | |
2745 | #endif | |
2746 | ||
2747 | struct type *t; | |
2748 | ||
e9bb382b UW |
2749 | t = arch_composite_type (gdbarch, |
2750 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2751 | |
2752 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2753 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2754 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2755 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2756 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2757 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2758 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2759 | |
876cecd0 | 2760 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2761 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2762 | tdep->i386_mmx_type = t; | |
2763 | } | |
2764 | ||
2765 | return tdep->i386_mmx_type; | |
2766 | } | |
2767 | ||
d7a0d72c | 2768 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 2769 | register REGNUM. */ |
d7a0d72c | 2770 | |
3a1e71e3 | 2771 | static struct type * |
90884b2b | 2772 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2773 | { |
1ba53b71 L |
2774 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2775 | return i386_mmx_type (gdbarch); | |
c131fcee L |
2776 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
2777 | return i386_ymm_type (gdbarch); | |
1ba53b71 L |
2778 | else |
2779 | { | |
2780 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2781 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2782 | return bt->builtin_int8; | |
2783 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2784 | return bt->builtin_int16; | |
2785 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2786 | return bt->builtin_int32; | |
2787 | } | |
2788 | ||
2789 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2790 | } |
2791 | ||
28fc6740 | 2792 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2793 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2794 | |
2795 | static int | |
c86c27af | 2796 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2797 | { |
5716833c MK |
2798 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2799 | int mmxreg, fpreg; | |
28fc6740 AC |
2800 | ULONGEST fstat; |
2801 | int tos; | |
c86c27af | 2802 | |
5716833c | 2803 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2804 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2805 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2806 | fpreg = (mmxreg + tos) % 8; |
2807 | ||
20a6ec49 | 2808 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2809 | } |
2810 | ||
3543a589 TT |
2811 | /* A helper function for us by i386_pseudo_register_read_value and |
2812 | amd64_pseudo_register_read_value. It does all the work but reads | |
2813 | the data into an already-allocated value. */ | |
2814 | ||
2815 | void | |
2816 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
2817 | struct regcache *regcache, | |
2818 | int regnum, | |
2819 | struct value *result_value) | |
28fc6740 | 2820 | { |
1ba53b71 | 2821 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 2822 | enum register_status status; |
3543a589 | 2823 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 2824 | |
5716833c | 2825 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2826 | { |
c86c27af MK |
2827 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2828 | ||
28fc6740 | 2829 | /* Extract (always little endian). */ |
05d1431c PA |
2830 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
2831 | if (status != REG_VALID) | |
3543a589 TT |
2832 | mark_value_bytes_unavailable (result_value, 0, |
2833 | TYPE_LENGTH (value_type (result_value))); | |
2834 | else | |
2835 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
2836 | } |
2837 | else | |
1ba53b71 L |
2838 | { |
2839 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2840 | ||
c131fcee L |
2841 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2842 | { | |
2843 | regnum -= tdep->ymm0_regnum; | |
2844 | ||
1777feb0 | 2845 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
2846 | status = regcache_raw_read (regcache, |
2847 | I387_XMM0_REGNUM (tdep) + regnum, | |
2848 | raw_buf); | |
2849 | if (status != REG_VALID) | |
3543a589 TT |
2850 | mark_value_bytes_unavailable (result_value, 0, 16); |
2851 | else | |
2852 | memcpy (buf, raw_buf, 16); | |
c131fcee | 2853 | /* Read upper 128bits. */ |
05d1431c PA |
2854 | status = regcache_raw_read (regcache, |
2855 | tdep->ymm0h_regnum + regnum, | |
2856 | raw_buf); | |
2857 | if (status != REG_VALID) | |
3543a589 TT |
2858 | mark_value_bytes_unavailable (result_value, 16, 32); |
2859 | else | |
2860 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee L |
2861 | } |
2862 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2863 | { |
2864 | int gpnum = regnum - tdep->ax_regnum; | |
2865 | ||
2866 | /* Extract (always little endian). */ | |
05d1431c PA |
2867 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
2868 | if (status != REG_VALID) | |
3543a589 TT |
2869 | mark_value_bytes_unavailable (result_value, 0, |
2870 | TYPE_LENGTH (value_type (result_value))); | |
2871 | else | |
2872 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
2873 | } |
2874 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2875 | { | |
2876 | /* Check byte pseudo registers last since this function will | |
2877 | be called from amd64_pseudo_register_read, which handles | |
2878 | byte pseudo registers differently. */ | |
2879 | int gpnum = regnum - tdep->al_regnum; | |
2880 | ||
2881 | /* Extract (always little endian). We read both lower and | |
2882 | upper registers. */ | |
05d1431c PA |
2883 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
2884 | if (status != REG_VALID) | |
3543a589 TT |
2885 | mark_value_bytes_unavailable (result_value, 0, |
2886 | TYPE_LENGTH (value_type (result_value))); | |
2887 | else if (gpnum >= 4) | |
1ba53b71 L |
2888 | memcpy (buf, raw_buf + 1, 1); |
2889 | else | |
2890 | memcpy (buf, raw_buf, 1); | |
2891 | } | |
2892 | else | |
2893 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2894 | } | |
3543a589 TT |
2895 | } |
2896 | ||
2897 | static struct value * | |
2898 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
2899 | struct regcache *regcache, | |
2900 | int regnum) | |
2901 | { | |
2902 | struct value *result; | |
2903 | ||
2904 | result = allocate_value (register_type (gdbarch, regnum)); | |
2905 | VALUE_LVAL (result) = lval_register; | |
2906 | VALUE_REGNUM (result) = regnum; | |
2907 | ||
2908 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 2909 | |
3543a589 | 2910 | return result; |
28fc6740 AC |
2911 | } |
2912 | ||
1ba53b71 | 2913 | void |
28fc6740 | 2914 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2915 | int regnum, const gdb_byte *buf) |
28fc6740 | 2916 | { |
1ba53b71 L |
2917 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2918 | ||
5716833c | 2919 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2920 | { |
c86c27af MK |
2921 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2922 | ||
28fc6740 | 2923 | /* Read ... */ |
1ba53b71 | 2924 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 2925 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 2926 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 2927 | /* ... Write. */ |
1ba53b71 | 2928 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
2929 | } |
2930 | else | |
1ba53b71 L |
2931 | { |
2932 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2933 | ||
c131fcee L |
2934 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2935 | { | |
2936 | regnum -= tdep->ymm0_regnum; | |
2937 | ||
2938 | /* ... Write lower 128bits. */ | |
2939 | regcache_raw_write (regcache, | |
2940 | I387_XMM0_REGNUM (tdep) + regnum, | |
2941 | buf); | |
2942 | /* ... Write upper 128bits. */ | |
2943 | regcache_raw_write (regcache, | |
2944 | tdep->ymm0h_regnum + regnum, | |
2945 | buf + 16); | |
2946 | } | |
2947 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2948 | { |
2949 | int gpnum = regnum - tdep->ax_regnum; | |
2950 | ||
2951 | /* Read ... */ | |
2952 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2953 | /* ... Modify ... (always little endian). */ | |
2954 | memcpy (raw_buf, buf, 2); | |
2955 | /* ... Write. */ | |
2956 | regcache_raw_write (regcache, gpnum, raw_buf); | |
2957 | } | |
2958 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2959 | { | |
2960 | /* Check byte pseudo registers last since this function will | |
2961 | be called from amd64_pseudo_register_read, which handles | |
2962 | byte pseudo registers differently. */ | |
2963 | int gpnum = regnum - tdep->al_regnum; | |
2964 | ||
2965 | /* Read ... We read both lower and upper registers. */ | |
2966 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2967 | /* ... Modify ... (always little endian). */ | |
2968 | if (gpnum >= 4) | |
2969 | memcpy (raw_buf + 1, buf, 1); | |
2970 | else | |
2971 | memcpy (raw_buf, buf, 1); | |
2972 | /* ... Write. */ | |
2973 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
2974 | } | |
2975 | else | |
2976 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2977 | } | |
28fc6740 | 2978 | } |
ff2e87ac AC |
2979 | \f |
2980 | ||
ff2e87ac AC |
2981 | /* Return the register number of the register allocated by GCC after |
2982 | REGNUM, or -1 if there is no such register. */ | |
2983 | ||
2984 | static int | |
2985 | i386_next_regnum (int regnum) | |
2986 | { | |
2987 | /* GCC allocates the registers in the order: | |
2988 | ||
2989 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2990 | ||
2991 | Since storing a variable in %esp doesn't make any sense we return | |
2992 | -1 for %ebp and for %esp itself. */ | |
2993 | static int next_regnum[] = | |
2994 | { | |
2995 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2996 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2997 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2998 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2999 | -1, -1, /* Slots for %esp and %ebp. */ | |
3000 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3001 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3002 | }; | |
3003 | ||
de5b9bb9 | 3004 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3005 | return next_regnum[regnum]; |
28fc6740 | 3006 | |
ff2e87ac AC |
3007 | return -1; |
3008 | } | |
3009 | ||
3010 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3011 | needs any special handling. */ | |
d7a0d72c | 3012 | |
3a1e71e3 | 3013 | static int |
1777feb0 MS |
3014 | i386_convert_register_p (struct gdbarch *gdbarch, |
3015 | int regnum, struct type *type) | |
d7a0d72c | 3016 | { |
de5b9bb9 MK |
3017 | int len = TYPE_LENGTH (type); |
3018 | ||
ff2e87ac AC |
3019 | /* Values may be spread across multiple registers. Most debugging |
3020 | formats aren't expressive enough to specify the locations, so | |
3021 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3022 | have a length that is a multiple of the word size, since GCC |
3023 | doesn't seem to put any other types into registers. */ | |
3024 | if (len > 4 && len % 4 == 0) | |
3025 | { | |
3026 | int last_regnum = regnum; | |
3027 | ||
3028 | while (len > 4) | |
3029 | { | |
3030 | last_regnum = i386_next_regnum (last_regnum); | |
3031 | len -= 4; | |
3032 | } | |
3033 | ||
3034 | if (last_regnum != -1) | |
3035 | return 1; | |
3036 | } | |
ff2e87ac | 3037 | |
0abe36f5 | 3038 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3039 | } |
3040 | ||
ff2e87ac AC |
3041 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3042 | return its contents in TO. */ | |
ac27f131 | 3043 | |
8dccd430 | 3044 | static int |
ff2e87ac | 3045 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3046 | struct type *type, gdb_byte *to, |
3047 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3048 | { |
20a6ec49 | 3049 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3050 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3051 | |
20a6ec49 | 3052 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3053 | return i387_register_to_value (frame, regnum, type, to, |
3054 | optimizedp, unavailablep); | |
ff2e87ac | 3055 | |
fd35795f | 3056 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3057 | |
3058 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3059 | |
de5b9bb9 MK |
3060 | while (len > 0) |
3061 | { | |
3062 | gdb_assert (regnum != -1); | |
20a6ec49 | 3063 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3064 | |
8dccd430 PA |
3065 | if (!get_frame_register_bytes (frame, regnum, 0, |
3066 | register_size (gdbarch, regnum), | |
3067 | to, optimizedp, unavailablep)) | |
3068 | return 0; | |
3069 | ||
de5b9bb9 MK |
3070 | regnum = i386_next_regnum (regnum); |
3071 | len -= 4; | |
42835c2b | 3072 | to += 4; |
de5b9bb9 | 3073 | } |
8dccd430 PA |
3074 | |
3075 | *optimizedp = *unavailablep = 0; | |
3076 | return 1; | |
ac27f131 MK |
3077 | } |
3078 | ||
ff2e87ac AC |
3079 | /* Write the contents FROM of a value of type TYPE into register |
3080 | REGNUM in frame FRAME. */ | |
ac27f131 | 3081 | |
3a1e71e3 | 3082 | static void |
ff2e87ac | 3083 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3084 | struct type *type, const gdb_byte *from) |
ac27f131 | 3085 | { |
de5b9bb9 | 3086 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3087 | |
20a6ec49 | 3088 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3089 | { |
d532c08f MK |
3090 | i387_value_to_register (frame, regnum, type, from); |
3091 | return; | |
3092 | } | |
3d261580 | 3093 | |
fd35795f | 3094 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3095 | |
3096 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3097 | |
de5b9bb9 MK |
3098 | while (len > 0) |
3099 | { | |
3100 | gdb_assert (regnum != -1); | |
875f8d0e | 3101 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3102 | |
42835c2b | 3103 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3104 | regnum = i386_next_regnum (regnum); |
3105 | len -= 4; | |
42835c2b | 3106 | from += 4; |
de5b9bb9 | 3107 | } |
ac27f131 | 3108 | } |
ff2e87ac | 3109 | \f |
7fdafb5a MK |
3110 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3111 | in the general-purpose register set REGSET to register cache | |
3112 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3113 | |
20187ed5 | 3114 | void |
473f17b0 MK |
3115 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3116 | int regnum, const void *gregs, size_t len) | |
3117 | { | |
9ea75c57 | 3118 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 3119 | const gdb_byte *regs = gregs; |
473f17b0 MK |
3120 | int i; |
3121 | ||
3122 | gdb_assert (len == tdep->sizeof_gregset); | |
3123 | ||
3124 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3125 | { | |
3126 | if ((regnum == i || regnum == -1) | |
3127 | && tdep->gregset_reg_offset[i] != -1) | |
3128 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3129 | } | |
3130 | } | |
3131 | ||
7fdafb5a MK |
3132 | /* Collect register REGNUM from the register cache REGCACHE and store |
3133 | it in the buffer specified by GREGS and LEN as described by the | |
3134 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3135 | all registers in REGSET. */ | |
3136 | ||
3137 | void | |
3138 | i386_collect_gregset (const struct regset *regset, | |
3139 | const struct regcache *regcache, | |
3140 | int regnum, void *gregs, size_t len) | |
3141 | { | |
3142 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 3143 | gdb_byte *regs = gregs; |
7fdafb5a MK |
3144 | int i; |
3145 | ||
3146 | gdb_assert (len == tdep->sizeof_gregset); | |
3147 | ||
3148 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3149 | { | |
3150 | if ((regnum == i || regnum == -1) | |
3151 | && tdep->gregset_reg_offset[i] != -1) | |
3152 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3153 | } | |
3154 | } | |
3155 | ||
3156 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3157 | in the floating-point register set REGSET to register cache | |
3158 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3159 | |
3160 | static void | |
3161 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3162 | int regnum, const void *fpregs, size_t len) | |
3163 | { | |
9ea75c57 | 3164 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 3165 | |
66a72d25 MK |
3166 | if (len == I387_SIZEOF_FXSAVE) |
3167 | { | |
3168 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3169 | return; | |
3170 | } | |
3171 | ||
473f17b0 MK |
3172 | gdb_assert (len == tdep->sizeof_fpregset); |
3173 | i387_supply_fsave (regcache, regnum, fpregs); | |
3174 | } | |
8446b36a | 3175 | |
2f305df1 MK |
3176 | /* Collect register REGNUM from the register cache REGCACHE and store |
3177 | it in the buffer specified by FPREGS and LEN as described by the | |
3178 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3179 | all registers in REGSET. */ | |
7fdafb5a MK |
3180 | |
3181 | static void | |
3182 | i386_collect_fpregset (const struct regset *regset, | |
3183 | const struct regcache *regcache, | |
3184 | int regnum, void *fpregs, size_t len) | |
3185 | { | |
3186 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
3187 | ||
3188 | if (len == I387_SIZEOF_FXSAVE) | |
3189 | { | |
3190 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3191 | return; | |
3192 | } | |
3193 | ||
3194 | gdb_assert (len == tdep->sizeof_fpregset); | |
3195 | i387_collect_fsave (regcache, regnum, fpregs); | |
3196 | } | |
3197 | ||
c131fcee L |
3198 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
3199 | ||
3200 | static void | |
3201 | i386_supply_xstateregset (const struct regset *regset, | |
3202 | struct regcache *regcache, int regnum, | |
3203 | const void *xstateregs, size_t len) | |
3204 | { | |
c131fcee L |
3205 | i387_supply_xsave (regcache, regnum, xstateregs); |
3206 | } | |
3207 | ||
3208 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
3209 | ||
3210 | static void | |
3211 | i386_collect_xstateregset (const struct regset *regset, | |
3212 | const struct regcache *regcache, | |
3213 | int regnum, void *xstateregs, size_t len) | |
3214 | { | |
c131fcee L |
3215 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
3216 | } | |
3217 | ||
8446b36a MK |
3218 | /* Return the appropriate register set for the core section identified |
3219 | by SECT_NAME and SECT_SIZE. */ | |
3220 | ||
3221 | const struct regset * | |
3222 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
3223 | const char *sect_name, size_t sect_size) | |
3224 | { | |
3225 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3226 | ||
3227 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
3228 | { | |
3229 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
3230 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
3231 | i386_collect_gregset); | |
8446b36a MK |
3232 | return tdep->gregset; |
3233 | } | |
3234 | ||
66a72d25 MK |
3235 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
3236 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
3237 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
3238 | { |
3239 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
3240 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
3241 | i386_collect_fpregset); | |
8446b36a MK |
3242 | return tdep->fpregset; |
3243 | } | |
3244 | ||
c131fcee L |
3245 | if (strcmp (sect_name, ".reg-xstate") == 0) |
3246 | { | |
3247 | if (tdep->xstateregset == NULL) | |
3248 | tdep->xstateregset = regset_alloc (gdbarch, | |
3249 | i386_supply_xstateregset, | |
3250 | i386_collect_xstateregset); | |
3251 | ||
3252 | return tdep->xstateregset; | |
3253 | } | |
3254 | ||
8446b36a MK |
3255 | return NULL; |
3256 | } | |
473f17b0 | 3257 | \f |
fc338970 | 3258 | |
fc338970 | 3259 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3260 | |
3261 | CORE_ADDR | |
e17a4113 UW |
3262 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3263 | CORE_ADDR pc, char *name) | |
c906108c | 3264 | { |
e17a4113 UW |
3265 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3266 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3267 | ||
3268 | /* jmp *(dest) */ | |
3269 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3270 | { |
e17a4113 UW |
3271 | unsigned long indirect = |
3272 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3273 | struct minimal_symbol *indsym = |
fc338970 | 3274 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 3275 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3276 | |
c5aa993b | 3277 | if (symname) |
c906108c | 3278 | { |
c5aa993b JM |
3279 | if (strncmp (symname, "__imp_", 6) == 0 |
3280 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
3281 | return name ? 1 : |
3282 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3283 | } |
3284 | } | |
fc338970 | 3285 | return 0; /* Not a trampoline. */ |
c906108c | 3286 | } |
fc338970 MK |
3287 | \f |
3288 | ||
10458914 DJ |
3289 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3290 | routine. */ | |
8201327c | 3291 | |
4bd207ef | 3292 | int |
10458914 | 3293 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3294 | { |
10458914 | 3295 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
3296 | char *name; |
3297 | ||
3298 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3299 | return (name && strcmp ("_sigtramp", name) == 0); |
3300 | } | |
3301 | \f | |
3302 | ||
fc338970 MK |
3303 | /* We have two flavours of disassembly. The machinery on this page |
3304 | deals with switching between those. */ | |
c906108c SS |
3305 | |
3306 | static int | |
a89aa300 | 3307 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3308 | { |
5e3397bb MK |
3309 | gdb_assert (disassembly_flavor == att_flavor |
3310 | || disassembly_flavor == intel_flavor); | |
3311 | ||
3312 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3313 | constified, cast to prevent a compiler warning. */ | |
3314 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3315 | |
3316 | return print_insn_i386 (pc, info); | |
7a292a7a | 3317 | } |
fc338970 | 3318 | \f |
3ce1502b | 3319 | |
8201327c MK |
3320 | /* There are a few i386 architecture variants that differ only |
3321 | slightly from the generic i386 target. For now, we don't give them | |
3322 | their own source file, but include them here. As a consequence, | |
3323 | they'll always be included. */ | |
3ce1502b | 3324 | |
8201327c | 3325 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3326 | |
10458914 DJ |
3327 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3328 | routine. */ | |
911bc6ee | 3329 | |
8201327c | 3330 | static int |
10458914 | 3331 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3332 | { |
10458914 | 3333 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
3334 | char *name; |
3335 | ||
acd5c798 MK |
3336 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
3337 | currently unknown. */ | |
911bc6ee | 3338 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
3339 | return (name && (strcmp ("_sigreturn", name) == 0 |
3340 | || strcmp ("_sigacthandler", name) == 0 | |
3341 | || strcmp ("sigvechandler", name) == 0)); | |
3342 | } | |
d2a7c97a | 3343 | |
10458914 DJ |
3344 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3345 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3346 | |
3a1e71e3 | 3347 | static CORE_ADDR |
10458914 | 3348 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3349 | { |
e17a4113 UW |
3350 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3351 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3352 | gdb_byte buf[4]; |
acd5c798 | 3353 | CORE_ADDR sp; |
3ce1502b | 3354 | |
10458914 | 3355 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3356 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3357 | |
e17a4113 | 3358 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c MK |
3359 | } |
3360 | \f | |
3ce1502b | 3361 | |
8201327c | 3362 | /* Generic ELF. */ |
d2a7c97a | 3363 | |
8201327c MK |
3364 | void |
3365 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3366 | { | |
c4fc7f1b MK |
3367 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
3368 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 3369 | } |
3ce1502b | 3370 | |
8201327c | 3371 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3372 | |
8201327c MK |
3373 | void |
3374 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3375 | { | |
3376 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 3377 | |
8201327c MK |
3378 | /* System V Release 4 uses ELF. */ |
3379 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 3380 | |
dfe01d39 | 3381 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
3382 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
3383 | ||
911bc6ee | 3384 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 3385 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
3386 | tdep->sc_pc_offset = 36 + 14 * 4; |
3387 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 3388 | |
8201327c | 3389 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
3390 | } |
3391 | ||
8201327c | 3392 | /* DJGPP. */ |
3ce1502b | 3393 | |
3a1e71e3 | 3394 | static void |
8201327c | 3395 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 3396 | { |
8201327c | 3397 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 3398 | |
911bc6ee MK |
3399 | /* DJGPP doesn't have any special frames for signal handlers. */ |
3400 | tdep->sigtramp_p = NULL; | |
3ce1502b | 3401 | |
8201327c | 3402 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
3403 | |
3404 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
3405 | if (! tdesc_has_registers (info.target_desc)) |
3406 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
3407 | |
3408 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
3409 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
3410 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
3411 | set_gdbarch_sdb_reg_to_regnum. */ | |
3412 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3413 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
3414 | |
3415 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 3416 | } |
8201327c | 3417 | \f |
2acceee2 | 3418 | |
38c968cf AC |
3419 | /* i386 register groups. In addition to the normal groups, add "mmx" |
3420 | and "sse". */ | |
3421 | ||
3422 | static struct reggroup *i386_sse_reggroup; | |
3423 | static struct reggroup *i386_mmx_reggroup; | |
3424 | ||
3425 | static void | |
3426 | i386_init_reggroups (void) | |
3427 | { | |
3428 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
3429 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
3430 | } | |
3431 | ||
3432 | static void | |
3433 | i386_add_reggroups (struct gdbarch *gdbarch) | |
3434 | { | |
3435 | reggroup_add (gdbarch, i386_sse_reggroup); | |
3436 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
3437 | reggroup_add (gdbarch, general_reggroup); | |
3438 | reggroup_add (gdbarch, float_reggroup); | |
3439 | reggroup_add (gdbarch, all_reggroup); | |
3440 | reggroup_add (gdbarch, save_reggroup); | |
3441 | reggroup_add (gdbarch, restore_reggroup); | |
3442 | reggroup_add (gdbarch, vector_reggroup); | |
3443 | reggroup_add (gdbarch, system_reggroup); | |
3444 | } | |
3445 | ||
3446 | int | |
3447 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
3448 | struct reggroup *group) | |
3449 | { | |
c131fcee L |
3450 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3451 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
3452 | ymm_regnum_p, ymmh_regnum_p; | |
acd5c798 | 3453 | |
1ba53b71 L |
3454 | /* Don't include pseudo registers, except for MMX, in any register |
3455 | groups. */ | |
c131fcee | 3456 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3457 | return 0; |
3458 | ||
c131fcee | 3459 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3460 | return 0; |
3461 | ||
c131fcee | 3462 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3463 | return 0; |
3464 | ||
3465 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
3466 | if (group == i386_mmx_reggroup) |
3467 | return mmx_regnum_p; | |
1ba53b71 | 3468 | |
c131fcee L |
3469 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
3470 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); | |
38c968cf | 3471 | if (group == i386_sse_reggroup) |
c131fcee L |
3472 | return xmm_regnum_p || mxcsr_regnum_p; |
3473 | ||
3474 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
38c968cf | 3475 | if (group == vector_reggroup) |
c131fcee L |
3476 | return (mmx_regnum_p |
3477 | || ymm_regnum_p | |
3478 | || mxcsr_regnum_p | |
3479 | || (xmm_regnum_p | |
3480 | && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) | |
3481 | == I386_XSTATE_SSE_MASK))); | |
1ba53b71 L |
3482 | |
3483 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
3484 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
3485 | if (group == float_reggroup) |
3486 | return fp_regnum_p; | |
1ba53b71 | 3487 | |
c131fcee L |
3488 | /* For "info reg all", don't include upper YMM registers nor XMM |
3489 | registers when AVX is supported. */ | |
3490 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
3491 | if (group == all_reggroup | |
3492 | && ((xmm_regnum_p | |
3493 | && (tdep->xcr0 & I386_XSTATE_AVX)) | |
3494 | || ymmh_regnum_p)) | |
3495 | return 0; | |
3496 | ||
38c968cf | 3497 | if (group == general_reggroup) |
1ba53b71 L |
3498 | return (!fp_regnum_p |
3499 | && !mmx_regnum_p | |
c131fcee L |
3500 | && !mxcsr_regnum_p |
3501 | && !xmm_regnum_p | |
3502 | && !ymm_regnum_p | |
3503 | && !ymmh_regnum_p); | |
acd5c798 | 3504 | |
38c968cf AC |
3505 | return default_register_reggroup_p (gdbarch, regnum, group); |
3506 | } | |
38c968cf | 3507 | \f |
acd5c798 | 3508 | |
f837910f MK |
3509 | /* Get the ARGIth function argument for the current function. */ |
3510 | ||
42c466d7 | 3511 | static CORE_ADDR |
143985b7 AF |
3512 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
3513 | struct type *type) | |
3514 | { | |
e17a4113 UW |
3515 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3516 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f837910f | 3517 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 3518 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
3519 | } |
3520 | ||
514f746b AR |
3521 | static void |
3522 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
3523 | { | |
3524 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
3525 | ||
3526 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
3527 | adjust the PC in the regcache. */ | |
3528 | current_pc += 1; | |
3529 | regcache_write_pc (regcache, current_pc); | |
3530 | } | |
3531 | ||
3532 | ||
7ad10968 HZ |
3533 | #define PREFIX_REPZ 0x01 |
3534 | #define PREFIX_REPNZ 0x02 | |
3535 | #define PREFIX_LOCK 0x04 | |
3536 | #define PREFIX_DATA 0x08 | |
3537 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 3538 | |
7ad10968 HZ |
3539 | /* operand size */ |
3540 | enum | |
3541 | { | |
3542 | OT_BYTE = 0, | |
3543 | OT_WORD, | |
3544 | OT_LONG, | |
cf648174 | 3545 | OT_QUAD, |
a3c4230a | 3546 | OT_DQUAD, |
7ad10968 | 3547 | }; |
473f17b0 | 3548 | |
7ad10968 HZ |
3549 | /* i386 arith/logic operations */ |
3550 | enum | |
3551 | { | |
3552 | OP_ADDL, | |
3553 | OP_ORL, | |
3554 | OP_ADCL, | |
3555 | OP_SBBL, | |
3556 | OP_ANDL, | |
3557 | OP_SUBL, | |
3558 | OP_XORL, | |
3559 | OP_CMPL, | |
3560 | }; | |
5716833c | 3561 | |
7ad10968 HZ |
3562 | struct i386_record_s |
3563 | { | |
cf648174 | 3564 | struct gdbarch *gdbarch; |
7ad10968 | 3565 | struct regcache *regcache; |
df61f520 | 3566 | CORE_ADDR orig_addr; |
7ad10968 HZ |
3567 | CORE_ADDR addr; |
3568 | int aflag; | |
3569 | int dflag; | |
3570 | int override; | |
3571 | uint8_t modrm; | |
3572 | uint8_t mod, reg, rm; | |
3573 | int ot; | |
cf648174 HZ |
3574 | uint8_t rex_x; |
3575 | uint8_t rex_b; | |
3576 | int rip_offset; | |
3577 | int popl_esp_hack; | |
3578 | const int *regmap; | |
7ad10968 | 3579 | }; |
5716833c | 3580 | |
7ad10968 | 3581 | /* Parse "modrm" part in current memory address that irp->addr point to |
1777feb0 | 3582 | Return -1 if something wrong. */ |
5716833c | 3583 | |
7ad10968 HZ |
3584 | static int |
3585 | i386_record_modrm (struct i386_record_s *irp) | |
3586 | { | |
cf648174 | 3587 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 3588 | |
7ad10968 HZ |
3589 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
3590 | { | |
3591 | if (record_debug) | |
3592 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3593 | "addr %s len = 1.\n"), |
3594 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3595 | return -1; |
3596 | } | |
3597 | irp->addr++; | |
3598 | irp->mod = (irp->modrm >> 6) & 3; | |
3599 | irp->reg = (irp->modrm >> 3) & 7; | |
3600 | irp->rm = irp->modrm & 7; | |
5716833c | 3601 | |
7ad10968 HZ |
3602 | return 0; |
3603 | } | |
d2a7c97a | 3604 | |
7ad10968 HZ |
3605 | /* Get the memory address that current instruction write to and set it to |
3606 | the argument "addr". | |
1777feb0 | 3607 | Return -1 if something wrong. */ |
8201327c | 3608 | |
7ad10968 | 3609 | static int |
cf648174 | 3610 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 3611 | { |
cf648174 | 3612 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
3613 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3614 | gdb_byte buf[4]; | |
3615 | ULONGEST offset64; | |
21d0e8a4 | 3616 | |
7ad10968 HZ |
3617 | *addr = 0; |
3618 | if (irp->aflag) | |
3619 | { | |
3620 | /* 32 bits */ | |
3621 | int havesib = 0; | |
3622 | uint8_t scale = 0; | |
648d0c8b | 3623 | uint8_t byte; |
7ad10968 HZ |
3624 | uint8_t index = 0; |
3625 | uint8_t base = irp->rm; | |
896fb97d | 3626 | |
7ad10968 HZ |
3627 | if (base == 4) |
3628 | { | |
3629 | havesib = 1; | |
648d0c8b | 3630 | if (target_read_memory (irp->addr, &byte, 1)) |
7ad10968 HZ |
3631 | { |
3632 | if (record_debug) | |
3633 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3634 | "at addr %s len = 1.\n"), |
3635 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3636 | return -1; |
3637 | } | |
3638 | irp->addr++; | |
648d0c8b MS |
3639 | scale = (byte >> 6) & 3; |
3640 | index = ((byte >> 3) & 7) | irp->rex_x; | |
3641 | base = (byte & 7); | |
7ad10968 | 3642 | } |
cf648174 | 3643 | base |= irp->rex_b; |
21d0e8a4 | 3644 | |
7ad10968 HZ |
3645 | switch (irp->mod) |
3646 | { | |
3647 | case 0: | |
3648 | if ((base & 7) == 5) | |
3649 | { | |
3650 | base = 0xff; | |
60a1502a | 3651 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3652 | { |
3653 | if (record_debug) | |
3654 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3655 | "memory at addr %s len = 4.\n"), |
3656 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3657 | return -1; |
3658 | } | |
3659 | irp->addr += 4; | |
60a1502a | 3660 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
3661 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
3662 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 3663 | } |
7ad10968 HZ |
3664 | break; |
3665 | case 1: | |
60a1502a | 3666 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3667 | { |
3668 | if (record_debug) | |
3669 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3670 | "at addr %s len = 1.\n"), |
3671 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3672 | return -1; |
3673 | } | |
3674 | irp->addr++; | |
60a1502a | 3675 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3676 | break; |
3677 | case 2: | |
60a1502a | 3678 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3679 | { |
3680 | if (record_debug) | |
3681 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3682 | "at addr %s len = 4.\n"), |
3683 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3684 | return -1; |
3685 | } | |
60a1502a | 3686 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
3687 | irp->addr += 4; |
3688 | break; | |
3689 | } | |
356a6b3e | 3690 | |
60a1502a | 3691 | offset64 = 0; |
7ad10968 | 3692 | if (base != 0xff) |
cf648174 HZ |
3693 | { |
3694 | if (base == 4 && irp->popl_esp_hack) | |
3695 | *addr += irp->popl_esp_hack; | |
3696 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 3697 | &offset64); |
7ad10968 | 3698 | } |
cf648174 HZ |
3699 | if (irp->aflag == 2) |
3700 | { | |
60a1502a | 3701 | *addr += offset64; |
cf648174 HZ |
3702 | } |
3703 | else | |
60a1502a | 3704 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 3705 | |
7ad10968 HZ |
3706 | if (havesib && (index != 4 || scale != 0)) |
3707 | { | |
cf648174 | 3708 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 3709 | &offset64); |
cf648174 | 3710 | if (irp->aflag == 2) |
60a1502a | 3711 | *addr += offset64 << scale; |
cf648174 | 3712 | else |
60a1502a | 3713 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 HZ |
3714 | } |
3715 | } | |
3716 | else | |
3717 | { | |
3718 | /* 16 bits */ | |
3719 | switch (irp->mod) | |
3720 | { | |
3721 | case 0: | |
3722 | if (irp->rm == 6) | |
3723 | { | |
60a1502a | 3724 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3725 | { |
3726 | if (record_debug) | |
3727 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3728 | "memory at addr %s len = 2.\n"), |
3729 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3730 | return -1; |
3731 | } | |
3732 | irp->addr += 2; | |
60a1502a | 3733 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3734 | irp->rm = 0; |
3735 | goto no_rm; | |
3736 | } | |
7ad10968 HZ |
3737 | break; |
3738 | case 1: | |
60a1502a | 3739 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3740 | { |
3741 | if (record_debug) | |
3742 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3743 | "at addr %s len = 1.\n"), |
3744 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3745 | return -1; |
3746 | } | |
3747 | irp->addr++; | |
60a1502a | 3748 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3749 | break; |
3750 | case 2: | |
60a1502a | 3751 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3752 | { |
3753 | if (record_debug) | |
3754 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3755 | "at addr %s len = 2.\n"), |
3756 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3757 | return -1; |
3758 | } | |
3759 | irp->addr += 2; | |
60a1502a | 3760 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3761 | break; |
3762 | } | |
c4fc7f1b | 3763 | |
7ad10968 HZ |
3764 | switch (irp->rm) |
3765 | { | |
3766 | case 0: | |
cf648174 HZ |
3767 | regcache_raw_read_unsigned (irp->regcache, |
3768 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3769 | &offset64); |
3770 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3771 | regcache_raw_read_unsigned (irp->regcache, |
3772 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3773 | &offset64); |
3774 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3775 | break; |
3776 | case 1: | |
cf648174 HZ |
3777 | regcache_raw_read_unsigned (irp->regcache, |
3778 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3779 | &offset64); |
3780 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3781 | regcache_raw_read_unsigned (irp->regcache, |
3782 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3783 | &offset64); |
3784 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3785 | break; |
3786 | case 2: | |
cf648174 HZ |
3787 | regcache_raw_read_unsigned (irp->regcache, |
3788 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3789 | &offset64); |
3790 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3791 | regcache_raw_read_unsigned (irp->regcache, |
3792 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3793 | &offset64); |
3794 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3795 | break; |
3796 | case 3: | |
cf648174 HZ |
3797 | regcache_raw_read_unsigned (irp->regcache, |
3798 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3799 | &offset64); |
3800 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3801 | regcache_raw_read_unsigned (irp->regcache, |
3802 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3803 | &offset64); |
3804 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3805 | break; |
3806 | case 4: | |
cf648174 HZ |
3807 | regcache_raw_read_unsigned (irp->regcache, |
3808 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3809 | &offset64); |
3810 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3811 | break; |
3812 | case 5: | |
cf648174 HZ |
3813 | regcache_raw_read_unsigned (irp->regcache, |
3814 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3815 | &offset64); |
3816 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3817 | break; |
3818 | case 6: | |
cf648174 HZ |
3819 | regcache_raw_read_unsigned (irp->regcache, |
3820 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3821 | &offset64); |
3822 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3823 | break; |
3824 | case 7: | |
cf648174 HZ |
3825 | regcache_raw_read_unsigned (irp->regcache, |
3826 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3827 | &offset64); |
3828 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3829 | break; |
3830 | } | |
3831 | *addr &= 0xffff; | |
3832 | } | |
c4fc7f1b | 3833 | |
01fe1b41 | 3834 | no_rm: |
7ad10968 HZ |
3835 | return 0; |
3836 | } | |
c4fc7f1b | 3837 | |
7ad10968 HZ |
3838 | /* Record the value of the memory that willbe changed in current instruction |
3839 | to "record_arch_list". | |
1777feb0 | 3840 | Return -1 if something wrong. */ |
356a6b3e | 3841 | |
7ad10968 HZ |
3842 | static int |
3843 | i386_record_lea_modrm (struct i386_record_s *irp) | |
3844 | { | |
cf648174 HZ |
3845 | struct gdbarch *gdbarch = irp->gdbarch; |
3846 | uint64_t addr; | |
356a6b3e | 3847 | |
d7877f7e | 3848 | if (irp->override >= 0) |
7ad10968 | 3849 | { |
bb08c432 HZ |
3850 | if (record_memory_query) |
3851 | { | |
3852 | int q; | |
3853 | ||
3854 | target_terminal_ours (); | |
3855 | q = yquery (_("\ | |
3856 | Process record ignores the memory change of instruction at address %s\n\ | |
3857 | because it can't get the value of the segment register.\n\ | |
3858 | Do you want to stop the program?"), | |
3859 | paddress (gdbarch, irp->orig_addr)); | |
3860 | target_terminal_inferior (); | |
3861 | if (q) | |
3862 | return -1; | |
3863 | } | |
3864 | ||
7ad10968 HZ |
3865 | return 0; |
3866 | } | |
61113f8b | 3867 | |
7ad10968 HZ |
3868 | if (i386_record_lea_modrm_addr (irp, &addr)) |
3869 | return -1; | |
96297dab | 3870 | |
7ad10968 HZ |
3871 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
3872 | return -1; | |
a62cc96e | 3873 | |
7ad10968 HZ |
3874 | return 0; |
3875 | } | |
b6197528 | 3876 | |
cf648174 | 3877 | /* Record the push operation to "record_arch_list". |
1777feb0 | 3878 | Return -1 if something wrong. */ |
cf648174 HZ |
3879 | |
3880 | static int | |
3881 | i386_record_push (struct i386_record_s *irp, int size) | |
3882 | { | |
648d0c8b | 3883 | ULONGEST addr; |
cf648174 HZ |
3884 | |
3885 | if (record_arch_list_add_reg (irp->regcache, | |
3886 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
3887 | return -1; | |
3888 | regcache_raw_read_unsigned (irp->regcache, | |
3889 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b MS |
3890 | &addr); |
3891 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) | |
cf648174 HZ |
3892 | return -1; |
3893 | ||
3894 | return 0; | |
3895 | } | |
3896 | ||
0289bdd7 MS |
3897 | |
3898 | /* Defines contents to record. */ | |
3899 | #define I386_SAVE_FPU_REGS 0xfffd | |
3900 | #define I386_SAVE_FPU_ENV 0xfffe | |
3901 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
3902 | ||
1777feb0 MS |
3903 | /* Record the value of floating point registers which will be changed |
3904 | by the current instruction to "record_arch_list". Return -1 if | |
3905 | something is wrong. */ | |
0289bdd7 MS |
3906 | |
3907 | static int i386_record_floats (struct gdbarch *gdbarch, | |
3908 | struct i386_record_s *ir, | |
3909 | uint32_t iregnum) | |
3910 | { | |
3911 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3912 | int i; | |
3913 | ||
3914 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
3915 | happen. Currently we store st0-st7 registers, but we need not store all | |
3916 | registers all the time, in future we use ftag register and record only | |
3917 | those who are not marked as an empty. */ | |
3918 | ||
3919 | if (I386_SAVE_FPU_REGS == iregnum) | |
3920 | { | |
3921 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
3922 | { | |
3923 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3924 | return -1; | |
3925 | } | |
3926 | } | |
3927 | else if (I386_SAVE_FPU_ENV == iregnum) | |
3928 | { | |
3929 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3930 | { | |
3931 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3932 | return -1; | |
3933 | } | |
3934 | } | |
3935 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
3936 | { | |
3937 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3938 | { | |
3939 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3940 | return -1; | |
3941 | } | |
3942 | } | |
3943 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
3944 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
3945 | { | |
3946 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
3947 | return -1; | |
3948 | } | |
3949 | else | |
3950 | { | |
3951 | /* Parameter error. */ | |
3952 | return -1; | |
3953 | } | |
3954 | if(I386_SAVE_FPU_ENV != iregnum) | |
3955 | { | |
3956 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3957 | { | |
3958 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3959 | return -1; | |
3960 | } | |
3961 | } | |
3962 | return 0; | |
3963 | } | |
3964 | ||
7ad10968 HZ |
3965 | /* Parse the current instruction and record the values of the registers and |
3966 | memory that will be changed in current instruction to "record_arch_list". | |
1777feb0 | 3967 | Return -1 if something wrong. */ |
8201327c | 3968 | |
cf648174 HZ |
3969 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
3970 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
3971 | ||
a6b808b4 | 3972 | int |
7ad10968 | 3973 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 3974 | CORE_ADDR input_addr) |
7ad10968 | 3975 | { |
60a1502a | 3976 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 3977 | int prefixes = 0; |
580879fc | 3978 | int regnum = 0; |
425b824a MS |
3979 | uint32_t opcode; |
3980 | uint8_t opcode8; | |
648d0c8b | 3981 | ULONGEST addr; |
60a1502a | 3982 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 3983 | struct i386_record_s ir; |
0289bdd7 | 3984 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
3985 | int rex = 0; |
3986 | uint8_t rex_w = -1; | |
3987 | uint8_t rex_r = 0; | |
7ad10968 | 3988 | |
8408d274 | 3989 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 3990 | ir.regcache = regcache; |
648d0c8b MS |
3991 | ir.addr = input_addr; |
3992 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
3993 | ir.aflag = 1; |
3994 | ir.dflag = 1; | |
cf648174 HZ |
3995 | ir.override = -1; |
3996 | ir.popl_esp_hack = 0; | |
a3c4230a | 3997 | ir.regmap = tdep->record_regmap; |
cf648174 | 3998 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
3999 | |
4000 | if (record_debug > 1) | |
4001 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
4002 | "addr = %s\n", |
4003 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4004 | |
4005 | /* prefixes */ | |
4006 | while (1) | |
4007 | { | |
425b824a | 4008 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
4009 | { |
4010 | if (record_debug) | |
4011 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
4012 | "addr %s len = 1.\n"), |
4013 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4014 | return -1; |
4015 | } | |
4016 | ir.addr++; | |
425b824a | 4017 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 4018 | { |
01fe1b41 | 4019 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
4020 | prefixes |= PREFIX_REPZ; |
4021 | break; | |
01fe1b41 | 4022 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
4023 | prefixes |= PREFIX_REPNZ; |
4024 | break; | |
01fe1b41 | 4025 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
4026 | prefixes |= PREFIX_LOCK; |
4027 | break; | |
01fe1b41 | 4028 | case CS_PREFIX_OPCODE: |
cf648174 | 4029 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 4030 | break; |
01fe1b41 | 4031 | case SS_PREFIX_OPCODE: |
cf648174 | 4032 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 4033 | break; |
01fe1b41 | 4034 | case DS_PREFIX_OPCODE: |
cf648174 | 4035 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 4036 | break; |
01fe1b41 | 4037 | case ES_PREFIX_OPCODE: |
cf648174 | 4038 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 4039 | break; |
01fe1b41 | 4040 | case FS_PREFIX_OPCODE: |
cf648174 | 4041 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 4042 | break; |
01fe1b41 | 4043 | case GS_PREFIX_OPCODE: |
cf648174 | 4044 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 4045 | break; |
01fe1b41 | 4046 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
4047 | prefixes |= PREFIX_DATA; |
4048 | break; | |
01fe1b41 | 4049 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
4050 | prefixes |= PREFIX_ADDR; |
4051 | break; | |
d691bec7 MS |
4052 | case 0x40: /* i386 inc %eax */ |
4053 | case 0x41: /* i386 inc %ecx */ | |
4054 | case 0x42: /* i386 inc %edx */ | |
4055 | case 0x43: /* i386 inc %ebx */ | |
4056 | case 0x44: /* i386 inc %esp */ | |
4057 | case 0x45: /* i386 inc %ebp */ | |
4058 | case 0x46: /* i386 inc %esi */ | |
4059 | case 0x47: /* i386 inc %edi */ | |
4060 | case 0x48: /* i386 dec %eax */ | |
4061 | case 0x49: /* i386 dec %ecx */ | |
4062 | case 0x4a: /* i386 dec %edx */ | |
4063 | case 0x4b: /* i386 dec %ebx */ | |
4064 | case 0x4c: /* i386 dec %esp */ | |
4065 | case 0x4d: /* i386 dec %ebp */ | |
4066 | case 0x4e: /* i386 dec %esi */ | |
4067 | case 0x4f: /* i386 dec %edi */ | |
4068 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
4069 | { |
4070 | /* REX */ | |
4071 | rex = 1; | |
425b824a MS |
4072 | rex_w = (opcode8 >> 3) & 1; |
4073 | rex_r = (opcode8 & 0x4) << 1; | |
4074 | ir.rex_x = (opcode8 & 0x2) << 2; | |
4075 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 4076 | } |
d691bec7 MS |
4077 | else /* 32 bit target */ |
4078 | goto out_prefixes; | |
cf648174 | 4079 | break; |
7ad10968 HZ |
4080 | default: |
4081 | goto out_prefixes; | |
4082 | break; | |
4083 | } | |
4084 | } | |
01fe1b41 | 4085 | out_prefixes: |
cf648174 HZ |
4086 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
4087 | { | |
4088 | ir.dflag = 2; | |
4089 | } | |
4090 | else | |
4091 | { | |
4092 | if (prefixes & PREFIX_DATA) | |
4093 | ir.dflag ^= 1; | |
4094 | } | |
7ad10968 HZ |
4095 | if (prefixes & PREFIX_ADDR) |
4096 | ir.aflag ^= 1; | |
cf648174 HZ |
4097 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4098 | ir.aflag = 2; | |
7ad10968 | 4099 | |
1777feb0 | 4100 | /* Now check op code. */ |
425b824a | 4101 | opcode = (uint32_t) opcode8; |
01fe1b41 | 4102 | reswitch: |
7ad10968 HZ |
4103 | switch (opcode) |
4104 | { | |
4105 | case 0x0f: | |
425b824a | 4106 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
4107 | { |
4108 | if (record_debug) | |
4109 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
4110 | "addr %s len = 1.\n"), |
4111 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4112 | return -1; |
4113 | } | |
4114 | ir.addr++; | |
a3c4230a | 4115 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
4116 | goto reswitch; |
4117 | break; | |
93924b6b | 4118 | |
a38bba38 | 4119 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
4120 | case 0x01: |
4121 | case 0x02: | |
4122 | case 0x03: | |
4123 | case 0x04: | |
4124 | case 0x05: | |
4125 | case 0x08: | |
4126 | case 0x09: | |
4127 | case 0x0a: | |
4128 | case 0x0b: | |
4129 | case 0x0c: | |
4130 | case 0x0d: | |
4131 | case 0x10: | |
4132 | case 0x11: | |
4133 | case 0x12: | |
4134 | case 0x13: | |
4135 | case 0x14: | |
4136 | case 0x15: | |
4137 | case 0x18: | |
4138 | case 0x19: | |
4139 | case 0x1a: | |
4140 | case 0x1b: | |
4141 | case 0x1c: | |
4142 | case 0x1d: | |
4143 | case 0x20: | |
4144 | case 0x21: | |
4145 | case 0x22: | |
4146 | case 0x23: | |
4147 | case 0x24: | |
4148 | case 0x25: | |
4149 | case 0x28: | |
4150 | case 0x29: | |
4151 | case 0x2a: | |
4152 | case 0x2b: | |
4153 | case 0x2c: | |
4154 | case 0x2d: | |
4155 | case 0x30: | |
4156 | case 0x31: | |
4157 | case 0x32: | |
4158 | case 0x33: | |
4159 | case 0x34: | |
4160 | case 0x35: | |
4161 | case 0x38: | |
4162 | case 0x39: | |
4163 | case 0x3a: | |
4164 | case 0x3b: | |
4165 | case 0x3c: | |
4166 | case 0x3d: | |
4167 | if (((opcode >> 3) & 7) != OP_CMPL) | |
4168 | { | |
4169 | if ((opcode & 1) == 0) | |
4170 | ir.ot = OT_BYTE; | |
4171 | else | |
4172 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 4173 | |
7ad10968 HZ |
4174 | switch ((opcode >> 1) & 3) |
4175 | { | |
a38bba38 | 4176 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
4177 | if (i386_record_modrm (&ir)) |
4178 | return -1; | |
4179 | if (ir.mod != 3) | |
4180 | { | |
4181 | if (i386_record_lea_modrm (&ir)) | |
4182 | return -1; | |
4183 | } | |
4184 | else | |
4185 | { | |
cf648174 HZ |
4186 | ir.rm |= ir.rex_b; |
4187 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4188 | ir.rm &= 0x3; |
cf648174 | 4189 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4190 | } |
4191 | break; | |
a38bba38 | 4192 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
4193 | if (i386_record_modrm (&ir)) |
4194 | return -1; | |
cf648174 HZ |
4195 | ir.reg |= rex_r; |
4196 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4197 | ir.reg &= 0x3; |
cf648174 | 4198 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4199 | break; |
a38bba38 | 4200 | case 2: /* OP A, Iv */ |
cf648174 | 4201 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4202 | break; |
4203 | } | |
4204 | } | |
cf648174 | 4205 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4206 | break; |
42fdc8df | 4207 | |
a38bba38 | 4208 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
4209 | case 0x81: |
4210 | case 0x82: | |
4211 | case 0x83: | |
4212 | if (i386_record_modrm (&ir)) | |
4213 | return -1; | |
8201327c | 4214 | |
7ad10968 HZ |
4215 | if (ir.reg != OP_CMPL) |
4216 | { | |
4217 | if ((opcode & 1) == 0) | |
4218 | ir.ot = OT_BYTE; | |
4219 | else | |
4220 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 4221 | |
7ad10968 HZ |
4222 | if (ir.mod != 3) |
4223 | { | |
cf648174 HZ |
4224 | if (opcode == 0x83) |
4225 | ir.rip_offset = 1; | |
4226 | else | |
4227 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4228 | if (i386_record_lea_modrm (&ir)) |
4229 | return -1; | |
4230 | } | |
4231 | else | |
cf648174 | 4232 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 4233 | } |
cf648174 | 4234 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4235 | break; |
5e3397bb | 4236 | |
a38bba38 | 4237 | case 0x40: /* inc */ |
7ad10968 HZ |
4238 | case 0x41: |
4239 | case 0x42: | |
4240 | case 0x43: | |
4241 | case 0x44: | |
4242 | case 0x45: | |
4243 | case 0x46: | |
4244 | case 0x47: | |
a38bba38 MS |
4245 | |
4246 | case 0x48: /* dec */ | |
7ad10968 HZ |
4247 | case 0x49: |
4248 | case 0x4a: | |
4249 | case 0x4b: | |
4250 | case 0x4c: | |
4251 | case 0x4d: | |
4252 | case 0x4e: | |
4253 | case 0x4f: | |
a38bba38 | 4254 | |
cf648174 HZ |
4255 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
4256 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 4257 | break; |
acd5c798 | 4258 | |
a38bba38 | 4259 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
4260 | case 0xf7: |
4261 | if ((opcode & 1) == 0) | |
4262 | ir.ot = OT_BYTE; | |
4263 | else | |
4264 | ir.ot = ir.dflag + OT_WORD; | |
4265 | if (i386_record_modrm (&ir)) | |
4266 | return -1; | |
acd5c798 | 4267 | |
cf648174 HZ |
4268 | if (ir.mod != 3 && ir.reg == 0) |
4269 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4270 | ||
7ad10968 HZ |
4271 | switch (ir.reg) |
4272 | { | |
a38bba38 | 4273 | case 0: /* test */ |
cf648174 | 4274 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4275 | break; |
a38bba38 MS |
4276 | case 2: /* not */ |
4277 | case 3: /* neg */ | |
7ad10968 HZ |
4278 | if (ir.mod != 3) |
4279 | { | |
4280 | if (i386_record_lea_modrm (&ir)) | |
4281 | return -1; | |
4282 | } | |
4283 | else | |
4284 | { | |
cf648174 HZ |
4285 | ir.rm |= ir.rex_b; |
4286 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4287 | ir.rm &= 0x3; |
cf648174 | 4288 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4289 | } |
a38bba38 | 4290 | if (ir.reg == 3) /* neg */ |
cf648174 | 4291 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4292 | break; |
a38bba38 MS |
4293 | case 4: /* mul */ |
4294 | case 5: /* imul */ | |
4295 | case 6: /* div */ | |
4296 | case 7: /* idiv */ | |
cf648174 | 4297 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 4298 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
4299 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
4300 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4301 | break; |
4302 | default: | |
4303 | ir.addr -= 2; | |
4304 | opcode = opcode << 8 | ir.modrm; | |
4305 | goto no_support; | |
4306 | break; | |
4307 | } | |
4308 | break; | |
4309 | ||
a38bba38 MS |
4310 | case 0xfe: /* GRP4 */ |
4311 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
4312 | if (i386_record_modrm (&ir)) |
4313 | return -1; | |
4314 | if (ir.reg >= 2 && opcode == 0xfe) | |
4315 | { | |
4316 | ir.addr -= 2; | |
4317 | opcode = opcode << 8 | ir.modrm; | |
4318 | goto no_support; | |
4319 | } | |
7ad10968 HZ |
4320 | switch (ir.reg) |
4321 | { | |
a38bba38 MS |
4322 | case 0: /* inc */ |
4323 | case 1: /* dec */ | |
cf648174 HZ |
4324 | if ((opcode & 1) == 0) |
4325 | ir.ot = OT_BYTE; | |
4326 | else | |
4327 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4328 | if (ir.mod != 3) |
4329 | { | |
4330 | if (i386_record_lea_modrm (&ir)) | |
4331 | return -1; | |
4332 | } | |
4333 | else | |
4334 | { | |
cf648174 HZ |
4335 | ir.rm |= ir.rex_b; |
4336 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4337 | ir.rm &= 0x3; |
cf648174 | 4338 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4339 | } |
cf648174 | 4340 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4341 | break; |
a38bba38 | 4342 | case 2: /* call */ |
cf648174 HZ |
4343 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4344 | ir.dflag = 2; | |
4345 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4346 | return -1; |
cf648174 | 4347 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4348 | break; |
a38bba38 | 4349 | case 3: /* lcall */ |
cf648174 HZ |
4350 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4351 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4352 | return -1; |
cf648174 | 4353 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4354 | break; |
a38bba38 MS |
4355 | case 4: /* jmp */ |
4356 | case 5: /* ljmp */ | |
cf648174 HZ |
4357 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4358 | break; | |
a38bba38 | 4359 | case 6: /* push */ |
cf648174 HZ |
4360 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4361 | ir.dflag = 2; | |
4362 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4363 | return -1; | |
7ad10968 HZ |
4364 | break; |
4365 | default: | |
4366 | ir.addr -= 2; | |
4367 | opcode = opcode << 8 | ir.modrm; | |
4368 | goto no_support; | |
4369 | break; | |
4370 | } | |
4371 | break; | |
4372 | ||
a38bba38 | 4373 | case 0x84: /* test */ |
7ad10968 HZ |
4374 | case 0x85: |
4375 | case 0xa8: | |
4376 | case 0xa9: | |
cf648174 | 4377 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4378 | break; |
4379 | ||
a38bba38 | 4380 | case 0x98: /* CWDE/CBW */ |
cf648174 | 4381 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4382 | break; |
4383 | ||
a38bba38 | 4384 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
4385 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4386 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4387 | break; |
4388 | ||
a38bba38 | 4389 | case 0x0faf: /* imul */ |
7ad10968 HZ |
4390 | case 0x69: |
4391 | case 0x6b: | |
4392 | ir.ot = ir.dflag + OT_WORD; | |
4393 | if (i386_record_modrm (&ir)) | |
4394 | return -1; | |
cf648174 HZ |
4395 | if (opcode == 0x69) |
4396 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4397 | else if (opcode == 0x6b) | |
4398 | ir.rip_offset = 1; | |
4399 | ir.reg |= rex_r; | |
4400 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4401 | ir.reg &= 0x3; |
cf648174 HZ |
4402 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4403 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4404 | break; |
4405 | ||
a38bba38 | 4406 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
4407 | case 0x0fc1: |
4408 | if ((opcode & 1) == 0) | |
4409 | ir.ot = OT_BYTE; | |
4410 | else | |
4411 | ir.ot = ir.dflag + OT_WORD; | |
4412 | if (i386_record_modrm (&ir)) | |
4413 | return -1; | |
cf648174 | 4414 | ir.reg |= rex_r; |
7ad10968 HZ |
4415 | if (ir.mod == 3) |
4416 | { | |
cf648174 | 4417 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4418 | ir.reg &= 0x3; |
cf648174 HZ |
4419 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4420 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4421 | ir.rm &= 0x3; |
cf648174 | 4422 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4423 | } |
4424 | else | |
4425 | { | |
4426 | if (i386_record_lea_modrm (&ir)) | |
4427 | return -1; | |
cf648174 | 4428 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4429 | ir.reg &= 0x3; |
cf648174 | 4430 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4431 | } |
cf648174 | 4432 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4433 | break; |
4434 | ||
a38bba38 | 4435 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
4436 | case 0x0fb1: |
4437 | if ((opcode & 1) == 0) | |
4438 | ir.ot = OT_BYTE; | |
4439 | else | |
4440 | ir.ot = ir.dflag + OT_WORD; | |
4441 | if (i386_record_modrm (&ir)) | |
4442 | return -1; | |
4443 | if (ir.mod == 3) | |
4444 | { | |
cf648174 HZ |
4445 | ir.reg |= rex_r; |
4446 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
4447 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4448 | ir.reg &= 0x3; |
cf648174 | 4449 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4450 | } |
4451 | else | |
4452 | { | |
cf648174 | 4453 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4454 | if (i386_record_lea_modrm (&ir)) |
4455 | return -1; | |
4456 | } | |
cf648174 | 4457 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4458 | break; |
4459 | ||
a38bba38 | 4460 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
4461 | if (i386_record_modrm (&ir)) |
4462 | return -1; | |
4463 | if (ir.mod == 3) | |
4464 | { | |
4465 | ir.addr -= 2; | |
4466 | opcode = opcode << 8 | ir.modrm; | |
4467 | goto no_support; | |
4468 | } | |
cf648174 HZ |
4469 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4470 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4471 | if (i386_record_lea_modrm (&ir)) |
4472 | return -1; | |
cf648174 | 4473 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4474 | break; |
4475 | ||
a38bba38 | 4476 | case 0x50: /* push */ |
7ad10968 HZ |
4477 | case 0x51: |
4478 | case 0x52: | |
4479 | case 0x53: | |
4480 | case 0x54: | |
4481 | case 0x55: | |
4482 | case 0x56: | |
4483 | case 0x57: | |
4484 | case 0x68: | |
4485 | case 0x6a: | |
cf648174 HZ |
4486 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4487 | ir.dflag = 2; | |
4488 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4489 | return -1; | |
4490 | break; | |
4491 | ||
a38bba38 MS |
4492 | case 0x06: /* push es */ |
4493 | case 0x0e: /* push cs */ | |
4494 | case 0x16: /* push ss */ | |
4495 | case 0x1e: /* push ds */ | |
cf648174 HZ |
4496 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4497 | { | |
4498 | ir.addr -= 1; | |
4499 | goto no_support; | |
4500 | } | |
4501 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4502 | return -1; | |
4503 | break; | |
4504 | ||
a38bba38 MS |
4505 | case 0x0fa0: /* push fs */ |
4506 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
4507 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4508 | { | |
4509 | ir.addr -= 2; | |
4510 | goto no_support; | |
4511 | } | |
4512 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4513 | return -1; |
cf648174 HZ |
4514 | break; |
4515 | ||
a38bba38 | 4516 | case 0x60: /* pusha */ |
cf648174 HZ |
4517 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4518 | { | |
4519 | ir.addr -= 1; | |
4520 | goto no_support; | |
4521 | } | |
4522 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
4523 | return -1; |
4524 | break; | |
4525 | ||
a38bba38 | 4526 | case 0x58: /* pop */ |
7ad10968 HZ |
4527 | case 0x59: |
4528 | case 0x5a: | |
4529 | case 0x5b: | |
4530 | case 0x5c: | |
4531 | case 0x5d: | |
4532 | case 0x5e: | |
4533 | case 0x5f: | |
cf648174 HZ |
4534 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4535 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
4536 | break; |
4537 | ||
a38bba38 | 4538 | case 0x61: /* popa */ |
cf648174 HZ |
4539 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4540 | { | |
4541 | ir.addr -= 1; | |
4542 | goto no_support; | |
7ad10968 | 4543 | } |
425b824a MS |
4544 | for (regnum = X86_RECORD_REAX_REGNUM; |
4545 | regnum <= X86_RECORD_REDI_REGNUM; | |
4546 | regnum++) | |
4547 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); | |
7ad10968 HZ |
4548 | break; |
4549 | ||
a38bba38 | 4550 | case 0x8f: /* pop */ |
cf648174 HZ |
4551 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4552 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
4553 | else | |
4554 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4555 | if (i386_record_modrm (&ir)) |
4556 | return -1; | |
4557 | if (ir.mod == 3) | |
cf648174 | 4558 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
4559 | else |
4560 | { | |
cf648174 | 4561 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
4562 | if (i386_record_lea_modrm (&ir)) |
4563 | return -1; | |
4564 | } | |
cf648174 | 4565 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
4566 | break; |
4567 | ||
a38bba38 | 4568 | case 0xc8: /* enter */ |
cf648174 HZ |
4569 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
4570 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4571 | ir.dflag = 2; | |
4572 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
4573 | return -1; |
4574 | break; | |
4575 | ||
a38bba38 | 4576 | case 0xc9: /* leave */ |
cf648174 HZ |
4577 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4578 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
4579 | break; |
4580 | ||
a38bba38 | 4581 | case 0x07: /* pop es */ |
cf648174 HZ |
4582 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4583 | { | |
4584 | ir.addr -= 1; | |
4585 | goto no_support; | |
4586 | } | |
4587 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4588 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
4589 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4590 | break; |
4591 | ||
a38bba38 | 4592 | case 0x17: /* pop ss */ |
cf648174 HZ |
4593 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4594 | { | |
4595 | ir.addr -= 1; | |
4596 | goto no_support; | |
4597 | } | |
4598 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4599 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
4600 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4601 | break; |
4602 | ||
a38bba38 | 4603 | case 0x1f: /* pop ds */ |
cf648174 HZ |
4604 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4605 | { | |
4606 | ir.addr -= 1; | |
4607 | goto no_support; | |
4608 | } | |
4609 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4610 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
4611 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4612 | break; |
4613 | ||
a38bba38 | 4614 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
4615 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4616 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
4617 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4618 | break; |
4619 | ||
a38bba38 | 4620 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
4621 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4622 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
4623 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4624 | break; |
4625 | ||
a38bba38 | 4626 | case 0x88: /* mov */ |
7ad10968 HZ |
4627 | case 0x89: |
4628 | case 0xc6: | |
4629 | case 0xc7: | |
4630 | if ((opcode & 1) == 0) | |
4631 | ir.ot = OT_BYTE; | |
4632 | else | |
4633 | ir.ot = ir.dflag + OT_WORD; | |
4634 | ||
4635 | if (i386_record_modrm (&ir)) | |
4636 | return -1; | |
4637 | ||
4638 | if (ir.mod != 3) | |
4639 | { | |
cf648174 HZ |
4640 | if (opcode == 0xc6 || opcode == 0xc7) |
4641 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4642 | if (i386_record_lea_modrm (&ir)) |
4643 | return -1; | |
4644 | } | |
4645 | else | |
4646 | { | |
cf648174 HZ |
4647 | if (opcode == 0xc6 || opcode == 0xc7) |
4648 | ir.rm |= ir.rex_b; | |
4649 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4650 | ir.rm &= 0x3; |
cf648174 | 4651 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4652 | } |
7ad10968 | 4653 | break; |
cf648174 | 4654 | |
a38bba38 | 4655 | case 0x8a: /* mov */ |
7ad10968 HZ |
4656 | case 0x8b: |
4657 | if ((opcode & 1) == 0) | |
4658 | ir.ot = OT_BYTE; | |
4659 | else | |
4660 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4661 | if (i386_record_modrm (&ir)) |
4662 | return -1; | |
cf648174 HZ |
4663 | ir.reg |= rex_r; |
4664 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4665 | ir.reg &= 0x3; |
cf648174 HZ |
4666 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4667 | break; | |
7ad10968 | 4668 | |
a38bba38 | 4669 | case 0x8c: /* mov seg */ |
cf648174 | 4670 | if (i386_record_modrm (&ir)) |
7ad10968 | 4671 | return -1; |
cf648174 HZ |
4672 | if (ir.reg > 5) |
4673 | { | |
4674 | ir.addr -= 2; | |
4675 | opcode = opcode << 8 | ir.modrm; | |
4676 | goto no_support; | |
4677 | } | |
4678 | ||
4679 | if (ir.mod == 3) | |
4680 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
4681 | else | |
4682 | { | |
4683 | ir.ot = OT_WORD; | |
4684 | if (i386_record_lea_modrm (&ir)) | |
4685 | return -1; | |
4686 | } | |
7ad10968 HZ |
4687 | break; |
4688 | ||
a38bba38 | 4689 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
4690 | if (i386_record_modrm (&ir)) |
4691 | return -1; | |
7ad10968 HZ |
4692 | switch (ir.reg) |
4693 | { | |
4694 | case 0: | |
425b824a | 4695 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
4696 | break; |
4697 | case 2: | |
425b824a | 4698 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
4699 | break; |
4700 | case 3: | |
425b824a | 4701 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
4702 | break; |
4703 | case 4: | |
425b824a | 4704 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
4705 | break; |
4706 | case 5: | |
425b824a | 4707 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4708 | break; |
4709 | default: | |
4710 | ir.addr -= 2; | |
4711 | opcode = opcode << 8 | ir.modrm; | |
4712 | goto no_support; | |
4713 | break; | |
4714 | } | |
425b824a | 4715 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 | 4716 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4717 | break; |
4718 | ||
a38bba38 MS |
4719 | case 0x0fb6: /* movzbS */ |
4720 | case 0x0fb7: /* movzwS */ | |
4721 | case 0x0fbe: /* movsbS */ | |
4722 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
4723 | if (i386_record_modrm (&ir)) |
4724 | return -1; | |
cf648174 | 4725 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
4726 | break; |
4727 | ||
a38bba38 | 4728 | case 0x8d: /* lea */ |
7ad10968 HZ |
4729 | if (i386_record_modrm (&ir)) |
4730 | return -1; | |
4731 | if (ir.mod == 3) | |
4732 | { | |
4733 | ir.addr -= 2; | |
4734 | opcode = opcode << 8 | ir.modrm; | |
4735 | goto no_support; | |
4736 | } | |
7ad10968 | 4737 | ir.ot = ir.dflag; |
cf648174 HZ |
4738 | ir.reg |= rex_r; |
4739 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4740 | ir.reg &= 0x3; |
cf648174 | 4741 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4742 | break; |
4743 | ||
a38bba38 | 4744 | case 0xa0: /* mov EAX */ |
7ad10968 | 4745 | case 0xa1: |
a38bba38 MS |
4746 | |
4747 | case 0xd7: /* xlat */ | |
cf648174 | 4748 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4749 | break; |
4750 | ||
a38bba38 | 4751 | case 0xa2: /* mov EAX */ |
7ad10968 | 4752 | case 0xa3: |
d7877f7e | 4753 | if (ir.override >= 0) |
cf648174 | 4754 | { |
bb08c432 HZ |
4755 | if (record_memory_query) |
4756 | { | |
4757 | int q; | |
4758 | ||
4759 | target_terminal_ours (); | |
4760 | q = yquery (_("\ | |
4761 | Process record ignores the memory change of instruction at address %s\n\ | |
4762 | because it can't get the value of the segment register.\n\ | |
4763 | Do you want to stop the program?"), | |
4764 | paddress (gdbarch, ir.orig_addr)); | |
4765 | target_terminal_inferior (); | |
4766 | if (q) | |
4767 | return -1; | |
4768 | } | |
cf648174 HZ |
4769 | } |
4770 | else | |
4771 | { | |
4772 | if ((opcode & 1) == 0) | |
4773 | ir.ot = OT_BYTE; | |
4774 | else | |
4775 | ir.ot = ir.dflag + OT_WORD; | |
4776 | if (ir.aflag == 2) | |
4777 | { | |
60a1502a | 4778 | if (target_read_memory (ir.addr, buf, 8)) |
cf648174 HZ |
4779 | { |
4780 | if (record_debug) | |
4781 | printf_unfiltered (_("Process record: error reading " | |
4782 | "memory at addr 0x%s len = 8.\n"), | |
4783 | paddress (gdbarch, ir.addr)); | |
4784 | return -1; | |
4785 | } | |
4786 | ir.addr += 8; | |
60a1502a | 4787 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
4788 | } |
4789 | else if (ir.aflag) | |
4790 | { | |
60a1502a | 4791 | if (target_read_memory (ir.addr, buf, 4)) |
cf648174 HZ |
4792 | { |
4793 | if (record_debug) | |
4794 | printf_unfiltered (_("Process record: error reading " | |
4795 | "memory at addr 0x%s len = 4.\n"), | |
4796 | paddress (gdbarch, ir.addr)); | |
4797 | return -1; | |
4798 | } | |
4799 | ir.addr += 4; | |
60a1502a | 4800 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
4801 | } |
4802 | else | |
4803 | { | |
60a1502a | 4804 | if (target_read_memory (ir.addr, buf, 2)) |
cf648174 HZ |
4805 | { |
4806 | if (record_debug) | |
4807 | printf_unfiltered (_("Process record: error reading " | |
4808 | "memory at addr 0x%s len = 2.\n"), | |
4809 | paddress (gdbarch, ir.addr)); | |
4810 | return -1; | |
4811 | } | |
4812 | ir.addr += 2; | |
60a1502a | 4813 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 4814 | } |
648d0c8b | 4815 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
4816 | return -1; |
4817 | } | |
7ad10968 HZ |
4818 | break; |
4819 | ||
a38bba38 | 4820 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
4821 | case 0xb1: |
4822 | case 0xb2: | |
4823 | case 0xb3: | |
4824 | case 0xb4: | |
4825 | case 0xb5: | |
4826 | case 0xb6: | |
4827 | case 0xb7: | |
cf648174 HZ |
4828 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
4829 | ? ((opcode & 0x7) | ir.rex_b) | |
4830 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
4831 | break; |
4832 | ||
a38bba38 | 4833 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
4834 | case 0xb9: |
4835 | case 0xba: | |
4836 | case 0xbb: | |
4837 | case 0xbc: | |
4838 | case 0xbd: | |
4839 | case 0xbe: | |
4840 | case 0xbf: | |
cf648174 | 4841 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
4842 | break; |
4843 | ||
a38bba38 | 4844 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
4845 | case 0x92: |
4846 | case 0x93: | |
4847 | case 0x94: | |
4848 | case 0x95: | |
4849 | case 0x96: | |
4850 | case 0x97: | |
cf648174 HZ |
4851 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4852 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
4853 | break; |
4854 | ||
a38bba38 | 4855 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
4856 | case 0x87: |
4857 | if ((opcode & 1) == 0) | |
4858 | ir.ot = OT_BYTE; | |
4859 | else | |
4860 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4861 | if (i386_record_modrm (&ir)) |
4862 | return -1; | |
7ad10968 HZ |
4863 | if (ir.mod == 3) |
4864 | { | |
86839d38 | 4865 | ir.rm |= ir.rex_b; |
cf648174 HZ |
4866 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
4867 | ir.rm &= 0x3; | |
4868 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
4869 | } |
4870 | else | |
4871 | { | |
4872 | if (i386_record_lea_modrm (&ir)) | |
4873 | return -1; | |
4874 | } | |
cf648174 HZ |
4875 | ir.reg |= rex_r; |
4876 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4877 | ir.reg &= 0x3; |
cf648174 | 4878 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4879 | break; |
4880 | ||
a38bba38 MS |
4881 | case 0xc4: /* les Gv */ |
4882 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
4883 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4884 | { | |
4885 | ir.addr -= 1; | |
4886 | goto no_support; | |
4887 | } | |
d3f323f3 | 4888 | /* FALLTHROUGH */ |
a38bba38 MS |
4889 | case 0x0fb2: /* lss Gv */ |
4890 | case 0x0fb4: /* lfs Gv */ | |
4891 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
4892 | if (i386_record_modrm (&ir)) |
4893 | return -1; | |
4894 | if (ir.mod == 3) | |
4895 | { | |
4896 | if (opcode > 0xff) | |
4897 | ir.addr -= 3; | |
4898 | else | |
4899 | ir.addr -= 2; | |
4900 | opcode = opcode << 8 | ir.modrm; | |
4901 | goto no_support; | |
4902 | } | |
7ad10968 HZ |
4903 | switch (opcode) |
4904 | { | |
a38bba38 | 4905 | case 0xc4: /* les Gv */ |
425b824a | 4906 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 4907 | break; |
a38bba38 | 4908 | case 0xc5: /* lds Gv */ |
425b824a | 4909 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 4910 | break; |
a38bba38 | 4911 | case 0x0fb2: /* lss Gv */ |
425b824a | 4912 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 4913 | break; |
a38bba38 | 4914 | case 0x0fb4: /* lfs Gv */ |
425b824a | 4915 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 4916 | break; |
a38bba38 | 4917 | case 0x0fb5: /* lgs Gv */ |
425b824a | 4918 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4919 | break; |
4920 | } | |
425b824a | 4921 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 HZ |
4922 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
4923 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4924 | break; |
4925 | ||
a38bba38 | 4926 | case 0xc0: /* shifts */ |
7ad10968 HZ |
4927 | case 0xc1: |
4928 | case 0xd0: | |
4929 | case 0xd1: | |
4930 | case 0xd2: | |
4931 | case 0xd3: | |
4932 | if ((opcode & 1) == 0) | |
4933 | ir.ot = OT_BYTE; | |
4934 | else | |
4935 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4936 | if (i386_record_modrm (&ir)) |
4937 | return -1; | |
7ad10968 HZ |
4938 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
4939 | { | |
4940 | if (i386_record_lea_modrm (&ir)) | |
4941 | return -1; | |
4942 | } | |
4943 | else | |
4944 | { | |
cf648174 HZ |
4945 | ir.rm |= ir.rex_b; |
4946 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4947 | ir.rm &= 0x3; |
cf648174 | 4948 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4949 | } |
cf648174 | 4950 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4951 | break; |
4952 | ||
4953 | case 0x0fa4: | |
4954 | case 0x0fa5: | |
4955 | case 0x0fac: | |
4956 | case 0x0fad: | |
4957 | if (i386_record_modrm (&ir)) | |
4958 | return -1; | |
4959 | if (ir.mod == 3) | |
4960 | { | |
4961 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4962 | return -1; | |
4963 | } | |
4964 | else | |
4965 | { | |
4966 | if (i386_record_lea_modrm (&ir)) | |
4967 | return -1; | |
4968 | } | |
4969 | break; | |
4970 | ||
a38bba38 | 4971 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
4972 | case 0xd9: |
4973 | case 0xda: | |
4974 | case 0xdb: | |
4975 | case 0xdc: | |
4976 | case 0xdd: | |
4977 | case 0xde: | |
4978 | case 0xdf: | |
4979 | if (i386_record_modrm (&ir)) | |
4980 | return -1; | |
4981 | ir.reg |= ((opcode & 7) << 3); | |
4982 | if (ir.mod != 3) | |
4983 | { | |
1777feb0 | 4984 | /* Memory. */ |
955db0c0 | 4985 | uint64_t addr64; |
7ad10968 | 4986 | |
955db0c0 | 4987 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
4988 | return -1; |
4989 | switch (ir.reg) | |
4990 | { | |
7ad10968 | 4991 | case 0x02: |
0289bdd7 MS |
4992 | case 0x12: |
4993 | case 0x22: | |
4994 | case 0x32: | |
4995 | /* For fcom, ficom nothing to do. */ | |
4996 | break; | |
7ad10968 | 4997 | case 0x03: |
0289bdd7 MS |
4998 | case 0x13: |
4999 | case 0x23: | |
5000 | case 0x33: | |
5001 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
5002 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5003 | return -1; | |
5004 | break; | |
5005 | case 0x00: | |
5006 | case 0x01: | |
7ad10968 HZ |
5007 | case 0x04: |
5008 | case 0x05: | |
5009 | case 0x06: | |
5010 | case 0x07: | |
5011 | case 0x10: | |
5012 | case 0x11: | |
7ad10968 HZ |
5013 | case 0x14: |
5014 | case 0x15: | |
5015 | case 0x16: | |
5016 | case 0x17: | |
5017 | case 0x20: | |
5018 | case 0x21: | |
7ad10968 HZ |
5019 | case 0x24: |
5020 | case 0x25: | |
5021 | case 0x26: | |
5022 | case 0x27: | |
5023 | case 0x30: | |
5024 | case 0x31: | |
7ad10968 HZ |
5025 | case 0x34: |
5026 | case 0x35: | |
5027 | case 0x36: | |
5028 | case 0x37: | |
0289bdd7 MS |
5029 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
5030 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
5031 | of code, always affects st(0) register. */ | |
5032 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5033 | return -1; | |
7ad10968 HZ |
5034 | break; |
5035 | case 0x08: | |
5036 | case 0x0a: | |
5037 | case 0x0b: | |
5038 | case 0x18: | |
5039 | case 0x19: | |
5040 | case 0x1a: | |
5041 | case 0x1b: | |
0289bdd7 | 5042 | case 0x1d: |
7ad10968 HZ |
5043 | case 0x28: |
5044 | case 0x29: | |
5045 | case 0x2a: | |
5046 | case 0x2b: | |
5047 | case 0x38: | |
5048 | case 0x39: | |
5049 | case 0x3a: | |
5050 | case 0x3b: | |
0289bdd7 MS |
5051 | case 0x3c: |
5052 | case 0x3d: | |
7ad10968 HZ |
5053 | switch (ir.reg & 7) |
5054 | { | |
5055 | case 0: | |
0289bdd7 MS |
5056 | /* Handling fld, fild. */ |
5057 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5058 | return -1; | |
7ad10968 HZ |
5059 | break; |
5060 | case 1: | |
5061 | switch (ir.reg >> 4) | |
5062 | { | |
5063 | case 0: | |
955db0c0 | 5064 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
5065 | return -1; |
5066 | break; | |
5067 | case 2: | |
955db0c0 | 5068 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
5069 | return -1; |
5070 | break; | |
5071 | case 3: | |
0289bdd7 | 5072 | break; |
7ad10968 | 5073 | default: |
955db0c0 | 5074 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5075 | return -1; |
5076 | break; | |
5077 | } | |
5078 | break; | |
5079 | default: | |
5080 | switch (ir.reg >> 4) | |
5081 | { | |
5082 | case 0: | |
955db0c0 | 5083 | if (record_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
5084 | return -1; |
5085 | if (3 == (ir.reg & 7)) | |
5086 | { | |
5087 | /* For fstp m32fp. */ | |
5088 | if (i386_record_floats (gdbarch, &ir, | |
5089 | I386_SAVE_FPU_REGS)) | |
5090 | return -1; | |
5091 | } | |
5092 | break; | |
7ad10968 | 5093 | case 1: |
955db0c0 | 5094 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 | 5095 | return -1; |
0289bdd7 MS |
5096 | if ((3 == (ir.reg & 7)) |
5097 | || (5 == (ir.reg & 7)) | |
5098 | || (7 == (ir.reg & 7))) | |
5099 | { | |
5100 | /* For fstp insn. */ | |
5101 | if (i386_record_floats (gdbarch, &ir, | |
5102 | I386_SAVE_FPU_REGS)) | |
5103 | return -1; | |
5104 | } | |
7ad10968 HZ |
5105 | break; |
5106 | case 2: | |
955db0c0 | 5107 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5108 | return -1; |
0289bdd7 MS |
5109 | if (3 == (ir.reg & 7)) |
5110 | { | |
5111 | /* For fstp m64fp. */ | |
5112 | if (i386_record_floats (gdbarch, &ir, | |
5113 | I386_SAVE_FPU_REGS)) | |
5114 | return -1; | |
5115 | } | |
7ad10968 HZ |
5116 | break; |
5117 | case 3: | |
0289bdd7 MS |
5118 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
5119 | { | |
5120 | /* For fistp, fbld, fild, fbstp. */ | |
5121 | if (i386_record_floats (gdbarch, &ir, | |
5122 | I386_SAVE_FPU_REGS)) | |
5123 | return -1; | |
5124 | } | |
5125 | /* Fall through */ | |
7ad10968 | 5126 | default: |
955db0c0 | 5127 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5128 | return -1; |
5129 | break; | |
5130 | } | |
5131 | break; | |
5132 | } | |
5133 | break; | |
5134 | case 0x0c: | |
0289bdd7 MS |
5135 | /* Insn fldenv. */ |
5136 | if (i386_record_floats (gdbarch, &ir, | |
5137 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5138 | return -1; | |
5139 | break; | |
7ad10968 | 5140 | case 0x0d: |
0289bdd7 MS |
5141 | /* Insn fldcw. */ |
5142 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
5143 | return -1; | |
5144 | break; | |
7ad10968 | 5145 | case 0x2c: |
0289bdd7 MS |
5146 | /* Insn frstor. */ |
5147 | if (i386_record_floats (gdbarch, &ir, | |
5148 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5149 | return -1; | |
7ad10968 HZ |
5150 | break; |
5151 | case 0x0e: | |
5152 | if (ir.dflag) | |
5153 | { | |
955db0c0 | 5154 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
5155 | return -1; |
5156 | } | |
5157 | else | |
5158 | { | |
955db0c0 | 5159 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
5160 | return -1; |
5161 | } | |
5162 | break; | |
5163 | case 0x0f: | |
5164 | case 0x2f: | |
955db0c0 | 5165 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5166 | return -1; |
0289bdd7 MS |
5167 | /* Insn fstp, fbstp. */ |
5168 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5169 | return -1; | |
7ad10968 HZ |
5170 | break; |
5171 | case 0x1f: | |
5172 | case 0x3e: | |
955db0c0 | 5173 | if (record_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
5174 | return -1; |
5175 | break; | |
5176 | case 0x2e: | |
5177 | if (ir.dflag) | |
5178 | { | |
955db0c0 | 5179 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 | 5180 | return -1; |
955db0c0 | 5181 | addr64 += 28; |
7ad10968 HZ |
5182 | } |
5183 | else | |
5184 | { | |
955db0c0 | 5185 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 | 5186 | return -1; |
955db0c0 | 5187 | addr64 += 14; |
7ad10968 | 5188 | } |
955db0c0 | 5189 | if (record_arch_list_add_mem (addr64, 80)) |
7ad10968 | 5190 | return -1; |
0289bdd7 MS |
5191 | /* Insn fsave. */ |
5192 | if (i386_record_floats (gdbarch, &ir, | |
5193 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5194 | return -1; | |
7ad10968 HZ |
5195 | break; |
5196 | case 0x3f: | |
955db0c0 | 5197 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5198 | return -1; |
0289bdd7 MS |
5199 | /* Insn fistp. */ |
5200 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5201 | return -1; | |
7ad10968 HZ |
5202 | break; |
5203 | default: | |
5204 | ir.addr -= 2; | |
5205 | opcode = opcode << 8 | ir.modrm; | |
5206 | goto no_support; | |
5207 | break; | |
5208 | } | |
5209 | } | |
0289bdd7 MS |
5210 | /* Opcode is an extension of modR/M byte. */ |
5211 | else | |
5212 | { | |
5213 | switch (opcode) | |
5214 | { | |
5215 | case 0xd8: | |
5216 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5217 | return -1; | |
5218 | break; | |
5219 | case 0xd9: | |
5220 | if (0x0c == (ir.modrm >> 4)) | |
5221 | { | |
5222 | if ((ir.modrm & 0x0f) <= 7) | |
5223 | { | |
5224 | if (i386_record_floats (gdbarch, &ir, | |
5225 | I386_SAVE_FPU_REGS)) | |
5226 | return -1; | |
5227 | } | |
5228 | else | |
5229 | { | |
5230 | if (i386_record_floats (gdbarch, &ir, | |
5231 | I387_ST0_REGNUM (tdep))) | |
5232 | return -1; | |
5233 | /* If only st(0) is changing, then we have already | |
5234 | recorded. */ | |
5235 | if ((ir.modrm & 0x0f) - 0x08) | |
5236 | { | |
5237 | if (i386_record_floats (gdbarch, &ir, | |
5238 | I387_ST0_REGNUM (tdep) + | |
5239 | ((ir.modrm & 0x0f) - 0x08))) | |
5240 | return -1; | |
5241 | } | |
5242 | } | |
5243 | } | |
5244 | else | |
5245 | { | |
5246 | switch (ir.modrm) | |
5247 | { | |
5248 | case 0xe0: | |
5249 | case 0xe1: | |
5250 | case 0xf0: | |
5251 | case 0xf5: | |
5252 | case 0xf8: | |
5253 | case 0xfa: | |
5254 | case 0xfc: | |
5255 | case 0xfe: | |
5256 | case 0xff: | |
5257 | if (i386_record_floats (gdbarch, &ir, | |
5258 | I387_ST0_REGNUM (tdep))) | |
5259 | return -1; | |
5260 | break; | |
5261 | case 0xf1: | |
5262 | case 0xf2: | |
5263 | case 0xf3: | |
5264 | case 0xf4: | |
5265 | case 0xf6: | |
5266 | case 0xf7: | |
5267 | case 0xe8: | |
5268 | case 0xe9: | |
5269 | case 0xea: | |
5270 | case 0xeb: | |
5271 | case 0xec: | |
5272 | case 0xed: | |
5273 | case 0xee: | |
5274 | case 0xf9: | |
5275 | case 0xfb: | |
5276 | if (i386_record_floats (gdbarch, &ir, | |
5277 | I386_SAVE_FPU_REGS)) | |
5278 | return -1; | |
5279 | break; | |
5280 | case 0xfd: | |
5281 | if (i386_record_floats (gdbarch, &ir, | |
5282 | I387_ST0_REGNUM (tdep))) | |
5283 | return -1; | |
5284 | if (i386_record_floats (gdbarch, &ir, | |
5285 | I387_ST0_REGNUM (tdep) + 1)) | |
5286 | return -1; | |
5287 | break; | |
5288 | } | |
5289 | } | |
5290 | break; | |
5291 | case 0xda: | |
5292 | if (0xe9 == ir.modrm) | |
5293 | { | |
5294 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5295 | return -1; | |
5296 | } | |
5297 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5298 | { | |
5299 | if (i386_record_floats (gdbarch, &ir, | |
5300 | I387_ST0_REGNUM (tdep))) | |
5301 | return -1; | |
5302 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5303 | { | |
5304 | if (i386_record_floats (gdbarch, &ir, | |
5305 | I387_ST0_REGNUM (tdep) + | |
5306 | (ir.modrm & 0x0f))) | |
5307 | return -1; | |
5308 | } | |
5309 | else if ((ir.modrm & 0x0f) - 0x08) | |
5310 | { | |
5311 | if (i386_record_floats (gdbarch, &ir, | |
5312 | I387_ST0_REGNUM (tdep) + | |
5313 | ((ir.modrm & 0x0f) - 0x08))) | |
5314 | return -1; | |
5315 | } | |
5316 | } | |
5317 | break; | |
5318 | case 0xdb: | |
5319 | if (0xe3 == ir.modrm) | |
5320 | { | |
5321 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
5322 | return -1; | |
5323 | } | |
5324 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5325 | { | |
5326 | if (i386_record_floats (gdbarch, &ir, | |
5327 | I387_ST0_REGNUM (tdep))) | |
5328 | return -1; | |
5329 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5330 | { | |
5331 | if (i386_record_floats (gdbarch, &ir, | |
5332 | I387_ST0_REGNUM (tdep) + | |
5333 | (ir.modrm & 0x0f))) | |
5334 | return -1; | |
5335 | } | |
5336 | else if ((ir.modrm & 0x0f) - 0x08) | |
5337 | { | |
5338 | if (i386_record_floats (gdbarch, &ir, | |
5339 | I387_ST0_REGNUM (tdep) + | |
5340 | ((ir.modrm & 0x0f) - 0x08))) | |
5341 | return -1; | |
5342 | } | |
5343 | } | |
5344 | break; | |
5345 | case 0xdc: | |
5346 | if ((0x0c == ir.modrm >> 4) | |
5347 | || (0x0d == ir.modrm >> 4) | |
5348 | || (0x0f == ir.modrm >> 4)) | |
5349 | { | |
5350 | if ((ir.modrm & 0x0f) <= 7) | |
5351 | { | |
5352 | if (i386_record_floats (gdbarch, &ir, | |
5353 | I387_ST0_REGNUM (tdep) + | |
5354 | (ir.modrm & 0x0f))) | |
5355 | return -1; | |
5356 | } | |
5357 | else | |
5358 | { | |
5359 | if (i386_record_floats (gdbarch, &ir, | |
5360 | I387_ST0_REGNUM (tdep) + | |
5361 | ((ir.modrm & 0x0f) - 0x08))) | |
5362 | return -1; | |
5363 | } | |
5364 | } | |
5365 | break; | |
5366 | case 0xdd: | |
5367 | if (0x0c == ir.modrm >> 4) | |
5368 | { | |
5369 | if (i386_record_floats (gdbarch, &ir, | |
5370 | I387_FTAG_REGNUM (tdep))) | |
5371 | return -1; | |
5372 | } | |
5373 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5374 | { | |
5375 | if ((ir.modrm & 0x0f) <= 7) | |
5376 | { | |
5377 | if (i386_record_floats (gdbarch, &ir, | |
5378 | I387_ST0_REGNUM (tdep) + | |
5379 | (ir.modrm & 0x0f))) | |
5380 | return -1; | |
5381 | } | |
5382 | else | |
5383 | { | |
5384 | if (i386_record_floats (gdbarch, &ir, | |
5385 | I386_SAVE_FPU_REGS)) | |
5386 | return -1; | |
5387 | } | |
5388 | } | |
5389 | break; | |
5390 | case 0xde: | |
5391 | if ((0x0c == ir.modrm >> 4) | |
5392 | || (0x0e == ir.modrm >> 4) | |
5393 | || (0x0f == ir.modrm >> 4) | |
5394 | || (0xd9 == ir.modrm)) | |
5395 | { | |
5396 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5397 | return -1; | |
5398 | } | |
5399 | break; | |
5400 | case 0xdf: | |
5401 | if (0xe0 == ir.modrm) | |
5402 | { | |
5403 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
5404 | return -1; | |
5405 | } | |
5406 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5407 | { | |
5408 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5409 | return -1; | |
5410 | } | |
5411 | break; | |
5412 | } | |
5413 | } | |
7ad10968 | 5414 | break; |
7ad10968 | 5415 | /* string ops */ |
a38bba38 | 5416 | case 0xa4: /* movsS */ |
7ad10968 | 5417 | case 0xa5: |
a38bba38 | 5418 | case 0xaa: /* stosS */ |
7ad10968 | 5419 | case 0xab: |
a38bba38 | 5420 | case 0x6c: /* insS */ |
7ad10968 | 5421 | case 0x6d: |
cf648174 | 5422 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 5423 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
5424 | &addr); |
5425 | if (addr) | |
cf648174 | 5426 | { |
77d7dc92 HZ |
5427 | ULONGEST es, ds; |
5428 | ||
5429 | if ((opcode & 1) == 0) | |
5430 | ir.ot = OT_BYTE; | |
5431 | else | |
5432 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
5433 | regcache_raw_read_unsigned (ir.regcache, |
5434 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 5435 | &addr); |
77d7dc92 | 5436 | |
d7877f7e HZ |
5437 | regcache_raw_read_unsigned (ir.regcache, |
5438 | ir.regmap[X86_RECORD_ES_REGNUM], | |
5439 | &es); | |
5440 | regcache_raw_read_unsigned (ir.regcache, | |
5441 | ir.regmap[X86_RECORD_DS_REGNUM], | |
5442 | &ds); | |
5443 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
5444 | { |
5445 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
bb08c432 HZ |
5446 | if (record_memory_query) |
5447 | { | |
5448 | int q; | |
5449 | ||
5450 | target_terminal_ours (); | |
5451 | q = yquery (_("\ | |
5452 | Process record ignores the memory change of instruction at address %s\n\ | |
5453 | because it can't get the value of the segment register.\n\ | |
5454 | Do you want to stop the program?"), | |
5455 | paddress (gdbarch, ir.orig_addr)); | |
5456 | target_terminal_inferior (); | |
5457 | if (q) | |
5458 | return -1; | |
5459 | } | |
df61f520 HZ |
5460 | } |
5461 | else | |
5462 | { | |
648d0c8b | 5463 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 5464 | return -1; |
77d7dc92 HZ |
5465 | } |
5466 | ||
5467 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5468 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
5469 | if (opcode == 0xa4 || opcode == 0xa5) |
5470 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5471 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5472 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5473 | } | |
cf648174 | 5474 | break; |
7ad10968 | 5475 | |
a38bba38 | 5476 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
5477 | case 0xa7: |
5478 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5479 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5480 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5481 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5482 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5483 | break; |
5484 | ||
a38bba38 | 5485 | case 0xac: /* lodsS */ |
7ad10968 | 5486 | case 0xad: |
cf648174 HZ |
5487 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5488 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5489 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5490 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5491 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5492 | break; |
5493 | ||
a38bba38 | 5494 | case 0xae: /* scasS */ |
7ad10968 | 5495 | case 0xaf: |
cf648174 | 5496 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 5497 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5498 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5499 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5500 | break; |
5501 | ||
a38bba38 | 5502 | case 0x6e: /* outsS */ |
cf648174 HZ |
5503 | case 0x6f: |
5504 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5505 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5506 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5507 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5508 | break; |
5509 | ||
a38bba38 | 5510 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
5511 | case 0xe5: |
5512 | case 0xec: | |
5513 | case 0xed: | |
cf648174 HZ |
5514 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5515 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5516 | break; |
5517 | ||
5518 | case 0xe6: | |
5519 | case 0xe7: | |
5520 | case 0xee: | |
5521 | case 0xef: | |
5522 | break; | |
5523 | ||
5524 | /* control */ | |
a38bba38 MS |
5525 | case 0xc2: /* ret im */ |
5526 | case 0xc3: /* ret */ | |
cf648174 HZ |
5527 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5528 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5529 | break; | |
5530 | ||
a38bba38 MS |
5531 | case 0xca: /* lret im */ |
5532 | case 0xcb: /* lret */ | |
5533 | case 0xcf: /* iret */ | |
cf648174 HZ |
5534 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
5535 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
5536 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5537 | break; |
5538 | ||
a38bba38 | 5539 | case 0xe8: /* call im */ |
cf648174 HZ |
5540 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5541 | ir.dflag = 2; | |
5542 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5543 | return -1; | |
7ad10968 HZ |
5544 | break; |
5545 | ||
a38bba38 | 5546 | case 0x9a: /* lcall im */ |
cf648174 HZ |
5547 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5548 | { | |
5549 | ir.addr -= 1; | |
5550 | goto no_support; | |
5551 | } | |
5552 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
5553 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5554 | return -1; | |
7ad10968 HZ |
5555 | break; |
5556 | ||
a38bba38 MS |
5557 | case 0xe9: /* jmp im */ |
5558 | case 0xea: /* ljmp im */ | |
5559 | case 0xeb: /* jmp Jb */ | |
5560 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
5561 | case 0x71: |
5562 | case 0x72: | |
5563 | case 0x73: | |
5564 | case 0x74: | |
5565 | case 0x75: | |
5566 | case 0x76: | |
5567 | case 0x77: | |
5568 | case 0x78: | |
5569 | case 0x79: | |
5570 | case 0x7a: | |
5571 | case 0x7b: | |
5572 | case 0x7c: | |
5573 | case 0x7d: | |
5574 | case 0x7e: | |
5575 | case 0x7f: | |
a38bba38 | 5576 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
5577 | case 0x0f81: |
5578 | case 0x0f82: | |
5579 | case 0x0f83: | |
5580 | case 0x0f84: | |
5581 | case 0x0f85: | |
5582 | case 0x0f86: | |
5583 | case 0x0f87: | |
5584 | case 0x0f88: | |
5585 | case 0x0f89: | |
5586 | case 0x0f8a: | |
5587 | case 0x0f8b: | |
5588 | case 0x0f8c: | |
5589 | case 0x0f8d: | |
5590 | case 0x0f8e: | |
5591 | case 0x0f8f: | |
5592 | break; | |
5593 | ||
a38bba38 | 5594 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
5595 | case 0x0f91: |
5596 | case 0x0f92: | |
5597 | case 0x0f93: | |
5598 | case 0x0f94: | |
5599 | case 0x0f95: | |
5600 | case 0x0f96: | |
5601 | case 0x0f97: | |
5602 | case 0x0f98: | |
5603 | case 0x0f99: | |
5604 | case 0x0f9a: | |
5605 | case 0x0f9b: | |
5606 | case 0x0f9c: | |
5607 | case 0x0f9d: | |
5608 | case 0x0f9e: | |
5609 | case 0x0f9f: | |
cf648174 | 5610 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5611 | ir.ot = OT_BYTE; |
5612 | if (i386_record_modrm (&ir)) | |
5613 | return -1; | |
5614 | if (ir.mod == 3) | |
cf648174 HZ |
5615 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
5616 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
5617 | else |
5618 | { | |
5619 | if (i386_record_lea_modrm (&ir)) | |
5620 | return -1; | |
5621 | } | |
5622 | break; | |
5623 | ||
a38bba38 | 5624 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
5625 | case 0x0f41: |
5626 | case 0x0f42: | |
5627 | case 0x0f43: | |
5628 | case 0x0f44: | |
5629 | case 0x0f45: | |
5630 | case 0x0f46: | |
5631 | case 0x0f47: | |
5632 | case 0x0f48: | |
5633 | case 0x0f49: | |
5634 | case 0x0f4a: | |
5635 | case 0x0f4b: | |
5636 | case 0x0f4c: | |
5637 | case 0x0f4d: | |
5638 | case 0x0f4e: | |
5639 | case 0x0f4f: | |
5640 | if (i386_record_modrm (&ir)) | |
5641 | return -1; | |
cf648174 | 5642 | ir.reg |= rex_r; |
7ad10968 HZ |
5643 | if (ir.dflag == OT_BYTE) |
5644 | ir.reg &= 0x3; | |
cf648174 | 5645 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5646 | break; |
5647 | ||
5648 | /* flags */ | |
a38bba38 | 5649 | case 0x9c: /* pushf */ |
cf648174 HZ |
5650 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5651 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
5652 | ir.dflag = 2; | |
5653 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5654 | return -1; | |
7ad10968 HZ |
5655 | break; |
5656 | ||
a38bba38 | 5657 | case 0x9d: /* popf */ |
cf648174 HZ |
5658 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5659 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5660 | break; |
5661 | ||
a38bba38 | 5662 | case 0x9e: /* sahf */ |
cf648174 HZ |
5663 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5664 | { | |
5665 | ir.addr -= 1; | |
5666 | goto no_support; | |
5667 | } | |
d3f323f3 | 5668 | /* FALLTHROUGH */ |
a38bba38 MS |
5669 | case 0xf5: /* cmc */ |
5670 | case 0xf8: /* clc */ | |
5671 | case 0xf9: /* stc */ | |
5672 | case 0xfc: /* cld */ | |
5673 | case 0xfd: /* std */ | |
cf648174 | 5674 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5675 | break; |
5676 | ||
a38bba38 | 5677 | case 0x9f: /* lahf */ |
cf648174 HZ |
5678 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5679 | { | |
5680 | ir.addr -= 1; | |
5681 | goto no_support; | |
5682 | } | |
5683 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5684 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5685 | break; |
5686 | ||
5687 | /* bit operations */ | |
a38bba38 | 5688 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
5689 | ir.ot = ir.dflag + OT_WORD; |
5690 | if (i386_record_modrm (&ir)) | |
5691 | return -1; | |
5692 | if (ir.reg < 4) | |
5693 | { | |
cf648174 | 5694 | ir.addr -= 2; |
7ad10968 HZ |
5695 | opcode = opcode << 8 | ir.modrm; |
5696 | goto no_support; | |
5697 | } | |
cf648174 | 5698 | if (ir.reg != 4) |
7ad10968 | 5699 | { |
cf648174 HZ |
5700 | if (ir.mod == 3) |
5701 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
5702 | else |
5703 | { | |
cf648174 | 5704 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
5705 | return -1; |
5706 | } | |
5707 | } | |
cf648174 | 5708 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5709 | break; |
5710 | ||
a38bba38 | 5711 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
5712 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5713 | break; | |
5714 | ||
a38bba38 MS |
5715 | case 0x0fab: /* bts */ |
5716 | case 0x0fb3: /* btr */ | |
5717 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
5718 | ir.ot = ir.dflag + OT_WORD; |
5719 | if (i386_record_modrm (&ir)) | |
5720 | return -1; | |
5721 | if (ir.mod == 3) | |
5722 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
5723 | else | |
5724 | { | |
955db0c0 MS |
5725 | uint64_t addr64; |
5726 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
5727 | return -1; |
5728 | regcache_raw_read_unsigned (ir.regcache, | |
5729 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 5730 | &addr); |
cf648174 HZ |
5731 | switch (ir.dflag) |
5732 | { | |
5733 | case 0: | |
648d0c8b | 5734 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
5735 | break; |
5736 | case 1: | |
648d0c8b | 5737 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
5738 | break; |
5739 | case 2: | |
648d0c8b | 5740 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
5741 | break; |
5742 | } | |
955db0c0 | 5743 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
5744 | return -1; |
5745 | if (i386_record_lea_modrm (&ir)) | |
5746 | return -1; | |
5747 | } | |
5748 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5749 | break; |
5750 | ||
a38bba38 MS |
5751 | case 0x0fbc: /* bsf */ |
5752 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
5753 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5754 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5755 | break; |
5756 | ||
5757 | /* bcd */ | |
a38bba38 MS |
5758 | case 0x27: /* daa */ |
5759 | case 0x2f: /* das */ | |
5760 | case 0x37: /* aaa */ | |
5761 | case 0x3f: /* aas */ | |
5762 | case 0xd4: /* aam */ | |
5763 | case 0xd5: /* aad */ | |
cf648174 HZ |
5764 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5765 | { | |
5766 | ir.addr -= 1; | |
5767 | goto no_support; | |
5768 | } | |
5769 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5770 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5771 | break; |
5772 | ||
5773 | /* misc */ | |
a38bba38 | 5774 | case 0x90: /* nop */ |
7ad10968 HZ |
5775 | if (prefixes & PREFIX_LOCK) |
5776 | { | |
5777 | ir.addr -= 1; | |
5778 | goto no_support; | |
5779 | } | |
5780 | break; | |
5781 | ||
a38bba38 | 5782 | case 0x9b: /* fwait */ |
425b824a | 5783 | if (target_read_memory (ir.addr, &opcode8, 1)) |
0289bdd7 MS |
5784 | { |
5785 | if (record_debug) | |
5786 | printf_unfiltered (_("Process record: error reading memory at " | |
5787 | "addr 0x%s len = 1.\n"), | |
5788 | paddress (gdbarch, ir.addr)); | |
5789 | return -1; | |
5790 | } | |
425b824a | 5791 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
5792 | ir.addr++; |
5793 | goto reswitch; | |
7ad10968 HZ |
5794 | break; |
5795 | ||
7ad10968 | 5796 | /* XXX */ |
a38bba38 | 5797 | case 0xcc: /* int3 */ |
a3c4230a | 5798 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
5799 | "int3.\n")); |
5800 | ir.addr -= 1; | |
5801 | goto no_support; | |
5802 | break; | |
5803 | ||
7ad10968 | 5804 | /* XXX */ |
a38bba38 | 5805 | case 0xcd: /* int */ |
7ad10968 HZ |
5806 | { |
5807 | int ret; | |
425b824a MS |
5808 | uint8_t interrupt; |
5809 | if (target_read_memory (ir.addr, &interrupt, 1)) | |
7ad10968 HZ |
5810 | { |
5811 | if (record_debug) | |
5812 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
5813 | "at addr %s len = 1.\n"), |
5814 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5815 | return -1; |
5816 | } | |
5817 | ir.addr++; | |
425b824a | 5818 | if (interrupt != 0x80 |
a3c4230a | 5819 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 5820 | { |
a3c4230a | 5821 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 5822 | "instruction int 0x%02x.\n"), |
425b824a | 5823 | interrupt); |
7ad10968 HZ |
5824 | ir.addr -= 2; |
5825 | goto no_support; | |
5826 | } | |
a3c4230a | 5827 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
5828 | if (ret) |
5829 | return ret; | |
5830 | } | |
5831 | break; | |
5832 | ||
7ad10968 | 5833 | /* XXX */ |
a38bba38 | 5834 | case 0xce: /* into */ |
a3c4230a | 5835 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5836 | "instruction into.\n")); |
5837 | ir.addr -= 1; | |
5838 | goto no_support; | |
5839 | break; | |
5840 | ||
a38bba38 MS |
5841 | case 0xfa: /* cli */ |
5842 | case 0xfb: /* sti */ | |
7ad10968 HZ |
5843 | break; |
5844 | ||
a38bba38 | 5845 | case 0x62: /* bound */ |
a3c4230a | 5846 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5847 | "instruction bound.\n")); |
5848 | ir.addr -= 1; | |
5849 | goto no_support; | |
5850 | break; | |
5851 | ||
a38bba38 | 5852 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
5853 | case 0x0fc9: |
5854 | case 0x0fca: | |
5855 | case 0x0fcb: | |
5856 | case 0x0fcc: | |
5857 | case 0x0fcd: | |
5858 | case 0x0fce: | |
5859 | case 0x0fcf: | |
cf648174 | 5860 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
5861 | break; |
5862 | ||
a38bba38 | 5863 | case 0xd6: /* salc */ |
cf648174 HZ |
5864 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5865 | { | |
5866 | ir.addr -= 1; | |
5867 | goto no_support; | |
5868 | } | |
5869 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5870 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5871 | break; |
5872 | ||
a38bba38 MS |
5873 | case 0xe0: /* loopnz */ |
5874 | case 0xe1: /* loopz */ | |
5875 | case 0xe2: /* loop */ | |
5876 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
5877 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5878 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5879 | break; |
5880 | ||
a38bba38 | 5881 | case 0x0f30: /* wrmsr */ |
a3c4230a | 5882 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5883 | "instruction wrmsr.\n")); |
5884 | ir.addr -= 2; | |
5885 | goto no_support; | |
5886 | break; | |
5887 | ||
a38bba38 | 5888 | case 0x0f32: /* rdmsr */ |
a3c4230a | 5889 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5890 | "instruction rdmsr.\n")); |
5891 | ir.addr -= 2; | |
5892 | goto no_support; | |
5893 | break; | |
5894 | ||
a38bba38 | 5895 | case 0x0f31: /* rdtsc */ |
f8c4f480 HZ |
5896 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5897 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5898 | break; |
5899 | ||
a38bba38 | 5900 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
5901 | { |
5902 | int ret; | |
cf648174 HZ |
5903 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5904 | { | |
5905 | ir.addr -= 2; | |
5906 | goto no_support; | |
5907 | } | |
a3c4230a | 5908 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 5909 | { |
a3c4230a | 5910 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5911 | "instruction sysenter.\n")); |
5912 | ir.addr -= 2; | |
5913 | goto no_support; | |
5914 | } | |
a3c4230a | 5915 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
5916 | if (ret) |
5917 | return ret; | |
5918 | } | |
5919 | break; | |
5920 | ||
a38bba38 | 5921 | case 0x0f35: /* sysexit */ |
a3c4230a | 5922 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5923 | "instruction sysexit.\n")); |
5924 | ir.addr -= 2; | |
5925 | goto no_support; | |
5926 | break; | |
5927 | ||
a38bba38 | 5928 | case 0x0f05: /* syscall */ |
cf648174 HZ |
5929 | { |
5930 | int ret; | |
a3c4230a | 5931 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 5932 | { |
a3c4230a | 5933 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
5934 | "instruction syscall.\n")); |
5935 | ir.addr -= 2; | |
5936 | goto no_support; | |
5937 | } | |
a3c4230a | 5938 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
5939 | if (ret) |
5940 | return ret; | |
5941 | } | |
5942 | break; | |
5943 | ||
a38bba38 | 5944 | case 0x0f07: /* sysret */ |
a3c4230a | 5945 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
5946 | "instruction sysret.\n")); |
5947 | ir.addr -= 2; | |
5948 | goto no_support; | |
5949 | break; | |
5950 | ||
a38bba38 | 5951 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
5952 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5953 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5954 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5955 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
5956 | break; |
5957 | ||
a38bba38 | 5958 | case 0xf4: /* hlt */ |
a3c4230a | 5959 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5960 | "instruction hlt.\n")); |
5961 | ir.addr -= 1; | |
5962 | goto no_support; | |
5963 | break; | |
5964 | ||
5965 | case 0x0f00: | |
5966 | if (i386_record_modrm (&ir)) | |
5967 | return -1; | |
5968 | switch (ir.reg) | |
5969 | { | |
a38bba38 MS |
5970 | case 0: /* sldt */ |
5971 | case 1: /* str */ | |
7ad10968 | 5972 | if (ir.mod == 3) |
cf648174 | 5973 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5974 | else |
5975 | { | |
5976 | ir.ot = OT_WORD; | |
5977 | if (i386_record_lea_modrm (&ir)) | |
5978 | return -1; | |
5979 | } | |
5980 | break; | |
a38bba38 MS |
5981 | case 2: /* lldt */ |
5982 | case 3: /* ltr */ | |
7ad10968 | 5983 | break; |
a38bba38 MS |
5984 | case 4: /* verr */ |
5985 | case 5: /* verw */ | |
cf648174 | 5986 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5987 | break; |
5988 | default: | |
5989 | ir.addr -= 3; | |
5990 | opcode = opcode << 8 | ir.modrm; | |
5991 | goto no_support; | |
5992 | break; | |
5993 | } | |
5994 | break; | |
5995 | ||
5996 | case 0x0f01: | |
5997 | if (i386_record_modrm (&ir)) | |
5998 | return -1; | |
5999 | switch (ir.reg) | |
6000 | { | |
a38bba38 | 6001 | case 0: /* sgdt */ |
7ad10968 | 6002 | { |
955db0c0 | 6003 | uint64_t addr64; |
7ad10968 HZ |
6004 | |
6005 | if (ir.mod == 3) | |
6006 | { | |
6007 | ir.addr -= 3; | |
6008 | opcode = opcode << 8 | ir.modrm; | |
6009 | goto no_support; | |
6010 | } | |
d7877f7e | 6011 | if (ir.override >= 0) |
7ad10968 | 6012 | { |
bb08c432 HZ |
6013 | if (record_memory_query) |
6014 | { | |
6015 | int q; | |
6016 | ||
6017 | target_terminal_ours (); | |
6018 | q = yquery (_("\ | |
6019 | Process record ignores the memory change of instruction at address %s\n\ | |
6020 | because it can't get the value of the segment register.\n\ | |
6021 | Do you want to stop the program?"), | |
6022 | paddress (gdbarch, ir.orig_addr)); | |
6023 | target_terminal_inferior (); | |
6024 | if (q) | |
6025 | return -1; | |
6026 | } | |
7ad10968 HZ |
6027 | } |
6028 | else | |
6029 | { | |
955db0c0 | 6030 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6031 | return -1; |
955db0c0 | 6032 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6033 | return -1; |
955db0c0 | 6034 | addr64 += 2; |
cf648174 HZ |
6035 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6036 | { | |
955db0c0 | 6037 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6038 | return -1; |
6039 | } | |
6040 | else | |
6041 | { | |
955db0c0 | 6042 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6043 | return -1; |
6044 | } | |
7ad10968 HZ |
6045 | } |
6046 | } | |
6047 | break; | |
6048 | case 1: | |
6049 | if (ir.mod == 3) | |
6050 | { | |
6051 | switch (ir.rm) | |
6052 | { | |
a38bba38 | 6053 | case 0: /* monitor */ |
7ad10968 | 6054 | break; |
a38bba38 | 6055 | case 1: /* mwait */ |
cf648174 | 6056 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6057 | break; |
6058 | default: | |
6059 | ir.addr -= 3; | |
6060 | opcode = opcode << 8 | ir.modrm; | |
6061 | goto no_support; | |
6062 | break; | |
6063 | } | |
6064 | } | |
6065 | else | |
6066 | { | |
6067 | /* sidt */ | |
d7877f7e | 6068 | if (ir.override >= 0) |
7ad10968 | 6069 | { |
bb08c432 HZ |
6070 | if (record_memory_query) |
6071 | { | |
6072 | int q; | |
6073 | ||
6074 | target_terminal_ours (); | |
6075 | q = yquery (_("\ | |
6076 | Process record ignores the memory change of instruction at address %s\n\ | |
6077 | because it can't get the value of the segment register.\n\ | |
6078 | Do you want to stop the program?"), | |
6079 | paddress (gdbarch, ir.orig_addr)); | |
6080 | target_terminal_inferior (); | |
6081 | if (q) | |
6082 | return -1; | |
6083 | } | |
7ad10968 HZ |
6084 | } |
6085 | else | |
6086 | { | |
955db0c0 | 6087 | uint64_t addr64; |
7ad10968 | 6088 | |
955db0c0 | 6089 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6090 | return -1; |
955db0c0 | 6091 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6092 | return -1; |
955db0c0 | 6093 | addr64 += 2; |
cf648174 HZ |
6094 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6095 | { | |
955db0c0 | 6096 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6097 | return -1; |
6098 | } | |
6099 | else | |
6100 | { | |
955db0c0 | 6101 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6102 | return -1; |
6103 | } | |
7ad10968 HZ |
6104 | } |
6105 | } | |
6106 | break; | |
a38bba38 | 6107 | case 2: /* lgdt */ |
3800e645 MS |
6108 | if (ir.mod == 3) |
6109 | { | |
6110 | /* xgetbv */ | |
6111 | if (ir.rm == 0) | |
6112 | { | |
6113 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6114 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6115 | break; | |
6116 | } | |
6117 | /* xsetbv */ | |
6118 | else if (ir.rm == 1) | |
6119 | break; | |
6120 | } | |
a38bba38 | 6121 | case 3: /* lidt */ |
7ad10968 HZ |
6122 | if (ir.mod == 3) |
6123 | { | |
6124 | ir.addr -= 3; | |
6125 | opcode = opcode << 8 | ir.modrm; | |
6126 | goto no_support; | |
6127 | } | |
6128 | break; | |
a38bba38 | 6129 | case 4: /* smsw */ |
7ad10968 HZ |
6130 | if (ir.mod == 3) |
6131 | { | |
cf648174 | 6132 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
6133 | return -1; |
6134 | } | |
6135 | else | |
6136 | { | |
6137 | ir.ot = OT_WORD; | |
6138 | if (i386_record_lea_modrm (&ir)) | |
6139 | return -1; | |
6140 | } | |
cf648174 | 6141 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6142 | break; |
a38bba38 | 6143 | case 6: /* lmsw */ |
cf648174 HZ |
6144 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6145 | break; | |
a38bba38 | 6146 | case 7: /* invlpg */ |
cf648174 HZ |
6147 | if (ir.mod == 3) |
6148 | { | |
6149 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
6150 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
6151 | else | |
6152 | { | |
6153 | ir.addr -= 3; | |
6154 | opcode = opcode << 8 | ir.modrm; | |
6155 | goto no_support; | |
6156 | } | |
6157 | } | |
6158 | else | |
6159 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6160 | break; | |
6161 | default: | |
6162 | ir.addr -= 3; | |
6163 | opcode = opcode << 8 | ir.modrm; | |
6164 | goto no_support; | |
7ad10968 HZ |
6165 | break; |
6166 | } | |
6167 | break; | |
6168 | ||
a38bba38 MS |
6169 | case 0x0f08: /* invd */ |
6170 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
6171 | break; |
6172 | ||
a38bba38 | 6173 | case 0x63: /* arpl */ |
7ad10968 HZ |
6174 | if (i386_record_modrm (&ir)) |
6175 | return -1; | |
cf648174 HZ |
6176 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
6177 | { | |
6178 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
6179 | ? (ir.reg | rex_r) : ir.rm); | |
6180 | } | |
7ad10968 | 6181 | else |
cf648174 HZ |
6182 | { |
6183 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
6184 | if (i386_record_lea_modrm (&ir)) | |
6185 | return -1; | |
6186 | } | |
6187 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
6188 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6189 | break; |
6190 | ||
a38bba38 MS |
6191 | case 0x0f02: /* lar */ |
6192 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
6193 | if (i386_record_modrm (&ir)) |
6194 | return -1; | |
cf648174 HZ |
6195 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6196 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6197 | break; |
6198 | ||
6199 | case 0x0f18: | |
cf648174 HZ |
6200 | if (i386_record_modrm (&ir)) |
6201 | return -1; | |
6202 | if (ir.mod == 3 && ir.reg == 3) | |
6203 | { | |
6204 | ir.addr -= 3; | |
6205 | opcode = opcode << 8 | ir.modrm; | |
6206 | goto no_support; | |
6207 | } | |
7ad10968 HZ |
6208 | break; |
6209 | ||
7ad10968 HZ |
6210 | case 0x0f19: |
6211 | case 0x0f1a: | |
6212 | case 0x0f1b: | |
6213 | case 0x0f1c: | |
6214 | case 0x0f1d: | |
6215 | case 0x0f1e: | |
6216 | case 0x0f1f: | |
a38bba38 | 6217 | /* nop (multi byte) */ |
7ad10968 HZ |
6218 | break; |
6219 | ||
a38bba38 MS |
6220 | case 0x0f20: /* mov reg, crN */ |
6221 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
6222 | if (i386_record_modrm (&ir)) |
6223 | return -1; | |
6224 | if ((ir.modrm & 0xc0) != 0xc0) | |
6225 | { | |
cf648174 | 6226 | ir.addr -= 3; |
7ad10968 HZ |
6227 | opcode = opcode << 8 | ir.modrm; |
6228 | goto no_support; | |
6229 | } | |
6230 | switch (ir.reg) | |
6231 | { | |
6232 | case 0: | |
6233 | case 2: | |
6234 | case 3: | |
6235 | case 4: | |
6236 | case 8: | |
6237 | if (opcode & 2) | |
cf648174 | 6238 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6239 | else |
cf648174 | 6240 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6241 | break; |
6242 | default: | |
cf648174 | 6243 | ir.addr -= 3; |
7ad10968 HZ |
6244 | opcode = opcode << 8 | ir.modrm; |
6245 | goto no_support; | |
6246 | break; | |
6247 | } | |
6248 | break; | |
6249 | ||
a38bba38 MS |
6250 | case 0x0f21: /* mov reg, drN */ |
6251 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
6252 | if (i386_record_modrm (&ir)) |
6253 | return -1; | |
6254 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
6255 | || ir.reg == 5 || ir.reg >= 8) | |
6256 | { | |
cf648174 | 6257 | ir.addr -= 3; |
7ad10968 HZ |
6258 | opcode = opcode << 8 | ir.modrm; |
6259 | goto no_support; | |
6260 | } | |
6261 | if (opcode & 2) | |
cf648174 | 6262 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6263 | else |
cf648174 | 6264 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6265 | break; |
6266 | ||
a38bba38 | 6267 | case 0x0f06: /* clts */ |
cf648174 | 6268 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6269 | break; |
6270 | ||
a3c4230a HZ |
6271 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
6272 | ||
6273 | case 0x0f0d: /* 3DNow! prefetch */ | |
6274 | break; | |
6275 | ||
6276 | case 0x0f0e: /* 3DNow! femms */ | |
6277 | case 0x0f77: /* emms */ | |
6278 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
6279 | goto no_support; | |
6280 | record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); | |
6281 | break; | |
6282 | ||
6283 | case 0x0f0f: /* 3DNow! data */ | |
6284 | if (i386_record_modrm (&ir)) | |
6285 | return -1; | |
6286 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
6287 | { | |
6288 | printf_unfiltered (_("Process record: error reading memory at " | |
6289 | "addr %s len = 1.\n"), | |
6290 | paddress (gdbarch, ir.addr)); | |
6291 | return -1; | |
6292 | } | |
6293 | ir.addr++; | |
6294 | switch (opcode8) | |
6295 | { | |
6296 | case 0x0c: /* 3DNow! pi2fw */ | |
6297 | case 0x0d: /* 3DNow! pi2fd */ | |
6298 | case 0x1c: /* 3DNow! pf2iw */ | |
6299 | case 0x1d: /* 3DNow! pf2id */ | |
6300 | case 0x8a: /* 3DNow! pfnacc */ | |
6301 | case 0x8e: /* 3DNow! pfpnacc */ | |
6302 | case 0x90: /* 3DNow! pfcmpge */ | |
6303 | case 0x94: /* 3DNow! pfmin */ | |
6304 | case 0x96: /* 3DNow! pfrcp */ | |
6305 | case 0x97: /* 3DNow! pfrsqrt */ | |
6306 | case 0x9a: /* 3DNow! pfsub */ | |
6307 | case 0x9e: /* 3DNow! pfadd */ | |
6308 | case 0xa0: /* 3DNow! pfcmpgt */ | |
6309 | case 0xa4: /* 3DNow! pfmax */ | |
6310 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
6311 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
6312 | case 0xaa: /* 3DNow! pfsubr */ | |
6313 | case 0xae: /* 3DNow! pfacc */ | |
6314 | case 0xb0: /* 3DNow! pfcmpeq */ | |
6315 | case 0xb4: /* 3DNow! pfmul */ | |
6316 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
6317 | case 0xb7: /* 3DNow! pmulhrw */ | |
6318 | case 0xbb: /* 3DNow! pswapd */ | |
6319 | case 0xbf: /* 3DNow! pavgusb */ | |
6320 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6321 | goto no_support_3dnow_data; | |
6322 | record_arch_list_add_reg (ir.regcache, ir.reg); | |
6323 | break; | |
6324 | ||
6325 | default: | |
6326 | no_support_3dnow_data: | |
6327 | opcode = (opcode << 8) | opcode8; | |
6328 | goto no_support; | |
6329 | break; | |
6330 | } | |
6331 | break; | |
6332 | ||
6333 | case 0x0faa: /* rsm */ | |
6334 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6335 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6336 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6337 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6338 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
6339 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6340 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
6341 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6342 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6343 | break; | |
6344 | ||
6345 | case 0x0fae: | |
6346 | if (i386_record_modrm (&ir)) | |
6347 | return -1; | |
6348 | switch(ir.reg) | |
6349 | { | |
6350 | case 0: /* fxsave */ | |
6351 | { | |
6352 | uint64_t tmpu64; | |
6353 | ||
6354 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6355 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) | |
6356 | return -1; | |
6357 | if (record_arch_list_add_mem (tmpu64, 512)) | |
6358 | return -1; | |
6359 | } | |
6360 | break; | |
6361 | ||
6362 | case 1: /* fxrstor */ | |
6363 | { | |
6364 | int i; | |
6365 | ||
6366 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6367 | ||
6368 | for (i = I387_MM0_REGNUM (tdep); | |
6369 | i386_mmx_regnum_p (gdbarch, i); i++) | |
6370 | record_arch_list_add_reg (ir.regcache, i); | |
6371 | ||
6372 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 6373 | i386_xmm_regnum_p (gdbarch, i); i++) |
a3c4230a HZ |
6374 | record_arch_list_add_reg (ir.regcache, i); |
6375 | ||
6376 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6377 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6378 | ||
6379 | for (i = I387_ST0_REGNUM (tdep); | |
6380 | i386_fp_regnum_p (gdbarch, i); i++) | |
6381 | record_arch_list_add_reg (ir.regcache, i); | |
6382 | ||
6383 | for (i = I387_FCTRL_REGNUM (tdep); | |
6384 | i386_fpc_regnum_p (gdbarch, i); i++) | |
6385 | record_arch_list_add_reg (ir.regcache, i); | |
6386 | } | |
6387 | break; | |
6388 | ||
6389 | case 2: /* ldmxcsr */ | |
6390 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6391 | goto no_support; | |
6392 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6393 | break; | |
6394 | ||
6395 | case 3: /* stmxcsr */ | |
6396 | ir.ot = OT_LONG; | |
6397 | if (i386_record_lea_modrm (&ir)) | |
6398 | return -1; | |
6399 | break; | |
6400 | ||
6401 | case 5: /* lfence */ | |
6402 | case 6: /* mfence */ | |
6403 | case 7: /* sfence clflush */ | |
6404 | break; | |
6405 | ||
6406 | default: | |
6407 | opcode = (opcode << 8) | ir.modrm; | |
6408 | goto no_support; | |
6409 | break; | |
6410 | } | |
6411 | break; | |
6412 | ||
6413 | case 0x0fc3: /* movnti */ | |
6414 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
6415 | if (i386_record_modrm (&ir)) | |
6416 | return -1; | |
6417 | if (ir.mod == 3) | |
6418 | goto no_support; | |
6419 | ir.reg |= rex_r; | |
6420 | if (i386_record_lea_modrm (&ir)) | |
6421 | return -1; | |
6422 | break; | |
6423 | ||
6424 | /* Add prefix to opcode. */ | |
6425 | case 0x0f10: | |
6426 | case 0x0f11: | |
6427 | case 0x0f12: | |
6428 | case 0x0f13: | |
6429 | case 0x0f14: | |
6430 | case 0x0f15: | |
6431 | case 0x0f16: | |
6432 | case 0x0f17: | |
6433 | case 0x0f28: | |
6434 | case 0x0f29: | |
6435 | case 0x0f2a: | |
6436 | case 0x0f2b: | |
6437 | case 0x0f2c: | |
6438 | case 0x0f2d: | |
6439 | case 0x0f2e: | |
6440 | case 0x0f2f: | |
6441 | case 0x0f38: | |
6442 | case 0x0f39: | |
6443 | case 0x0f3a: | |
6444 | case 0x0f50: | |
6445 | case 0x0f51: | |
6446 | case 0x0f52: | |
6447 | case 0x0f53: | |
6448 | case 0x0f54: | |
6449 | case 0x0f55: | |
6450 | case 0x0f56: | |
6451 | case 0x0f57: | |
6452 | case 0x0f58: | |
6453 | case 0x0f59: | |
6454 | case 0x0f5a: | |
6455 | case 0x0f5b: | |
6456 | case 0x0f5c: | |
6457 | case 0x0f5d: | |
6458 | case 0x0f5e: | |
6459 | case 0x0f5f: | |
6460 | case 0x0f60: | |
6461 | case 0x0f61: | |
6462 | case 0x0f62: | |
6463 | case 0x0f63: | |
6464 | case 0x0f64: | |
6465 | case 0x0f65: | |
6466 | case 0x0f66: | |
6467 | case 0x0f67: | |
6468 | case 0x0f68: | |
6469 | case 0x0f69: | |
6470 | case 0x0f6a: | |
6471 | case 0x0f6b: | |
6472 | case 0x0f6c: | |
6473 | case 0x0f6d: | |
6474 | case 0x0f6e: | |
6475 | case 0x0f6f: | |
6476 | case 0x0f70: | |
6477 | case 0x0f71: | |
6478 | case 0x0f72: | |
6479 | case 0x0f73: | |
6480 | case 0x0f74: | |
6481 | case 0x0f75: | |
6482 | case 0x0f76: | |
6483 | case 0x0f7c: | |
6484 | case 0x0f7d: | |
6485 | case 0x0f7e: | |
6486 | case 0x0f7f: | |
6487 | case 0x0fb8: | |
6488 | case 0x0fc2: | |
6489 | case 0x0fc4: | |
6490 | case 0x0fc5: | |
6491 | case 0x0fc6: | |
6492 | case 0x0fd0: | |
6493 | case 0x0fd1: | |
6494 | case 0x0fd2: | |
6495 | case 0x0fd3: | |
6496 | case 0x0fd4: | |
6497 | case 0x0fd5: | |
6498 | case 0x0fd6: | |
6499 | case 0x0fd7: | |
6500 | case 0x0fd8: | |
6501 | case 0x0fd9: | |
6502 | case 0x0fda: | |
6503 | case 0x0fdb: | |
6504 | case 0x0fdc: | |
6505 | case 0x0fdd: | |
6506 | case 0x0fde: | |
6507 | case 0x0fdf: | |
6508 | case 0x0fe0: | |
6509 | case 0x0fe1: | |
6510 | case 0x0fe2: | |
6511 | case 0x0fe3: | |
6512 | case 0x0fe4: | |
6513 | case 0x0fe5: | |
6514 | case 0x0fe6: | |
6515 | case 0x0fe7: | |
6516 | case 0x0fe8: | |
6517 | case 0x0fe9: | |
6518 | case 0x0fea: | |
6519 | case 0x0feb: | |
6520 | case 0x0fec: | |
6521 | case 0x0fed: | |
6522 | case 0x0fee: | |
6523 | case 0x0fef: | |
6524 | case 0x0ff0: | |
6525 | case 0x0ff1: | |
6526 | case 0x0ff2: | |
6527 | case 0x0ff3: | |
6528 | case 0x0ff4: | |
6529 | case 0x0ff5: | |
6530 | case 0x0ff6: | |
6531 | case 0x0ff7: | |
6532 | case 0x0ff8: | |
6533 | case 0x0ff9: | |
6534 | case 0x0ffa: | |
6535 | case 0x0ffb: | |
6536 | case 0x0ffc: | |
6537 | case 0x0ffd: | |
6538 | case 0x0ffe: | |
6539 | switch (prefixes) | |
6540 | { | |
6541 | case PREFIX_REPNZ: | |
6542 | opcode |= 0xf20000; | |
6543 | break; | |
6544 | case PREFIX_DATA: | |
6545 | opcode |= 0x660000; | |
6546 | break; | |
6547 | case PREFIX_REPZ: | |
6548 | opcode |= 0xf30000; | |
6549 | break; | |
6550 | } | |
6551 | reswitch_prefix_add: | |
6552 | switch (opcode) | |
6553 | { | |
6554 | case 0x0f38: | |
6555 | case 0x660f38: | |
6556 | case 0xf20f38: | |
6557 | case 0x0f3a: | |
6558 | case 0x660f3a: | |
6559 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
6560 | { | |
6561 | printf_unfiltered (_("Process record: error reading memory at " | |
6562 | "addr %s len = 1.\n"), | |
6563 | paddress (gdbarch, ir.addr)); | |
6564 | return -1; | |
6565 | } | |
6566 | ir.addr++; | |
6567 | opcode = (uint32_t) opcode8 | opcode << 8; | |
6568 | goto reswitch_prefix_add; | |
6569 | break; | |
6570 | ||
6571 | case 0x0f10: /* movups */ | |
6572 | case 0x660f10: /* movupd */ | |
6573 | case 0xf30f10: /* movss */ | |
6574 | case 0xf20f10: /* movsd */ | |
6575 | case 0x0f12: /* movlps */ | |
6576 | case 0x660f12: /* movlpd */ | |
6577 | case 0xf30f12: /* movsldup */ | |
6578 | case 0xf20f12: /* movddup */ | |
6579 | case 0x0f14: /* unpcklps */ | |
6580 | case 0x660f14: /* unpcklpd */ | |
6581 | case 0x0f15: /* unpckhps */ | |
6582 | case 0x660f15: /* unpckhpd */ | |
6583 | case 0x0f16: /* movhps */ | |
6584 | case 0x660f16: /* movhpd */ | |
6585 | case 0xf30f16: /* movshdup */ | |
6586 | case 0x0f28: /* movaps */ | |
6587 | case 0x660f28: /* movapd */ | |
6588 | case 0x0f2a: /* cvtpi2ps */ | |
6589 | case 0x660f2a: /* cvtpi2pd */ | |
6590 | case 0xf30f2a: /* cvtsi2ss */ | |
6591 | case 0xf20f2a: /* cvtsi2sd */ | |
6592 | case 0x0f2c: /* cvttps2pi */ | |
6593 | case 0x660f2c: /* cvttpd2pi */ | |
6594 | case 0x0f2d: /* cvtps2pi */ | |
6595 | case 0x660f2d: /* cvtpd2pi */ | |
6596 | case 0x660f3800: /* pshufb */ | |
6597 | case 0x660f3801: /* phaddw */ | |
6598 | case 0x660f3802: /* phaddd */ | |
6599 | case 0x660f3803: /* phaddsw */ | |
6600 | case 0x660f3804: /* pmaddubsw */ | |
6601 | case 0x660f3805: /* phsubw */ | |
6602 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 6603 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
6604 | case 0x660f3808: /* psignb */ |
6605 | case 0x660f3809: /* psignw */ | |
6606 | case 0x660f380a: /* psignd */ | |
6607 | case 0x660f380b: /* pmulhrsw */ | |
6608 | case 0x660f3810: /* pblendvb */ | |
6609 | case 0x660f3814: /* blendvps */ | |
6610 | case 0x660f3815: /* blendvpd */ | |
6611 | case 0x660f381c: /* pabsb */ | |
6612 | case 0x660f381d: /* pabsw */ | |
6613 | case 0x660f381e: /* pabsd */ | |
6614 | case 0x660f3820: /* pmovsxbw */ | |
6615 | case 0x660f3821: /* pmovsxbd */ | |
6616 | case 0x660f3822: /* pmovsxbq */ | |
6617 | case 0x660f3823: /* pmovsxwd */ | |
6618 | case 0x660f3824: /* pmovsxwq */ | |
6619 | case 0x660f3825: /* pmovsxdq */ | |
6620 | case 0x660f3828: /* pmuldq */ | |
6621 | case 0x660f3829: /* pcmpeqq */ | |
6622 | case 0x660f382a: /* movntdqa */ | |
6623 | case 0x660f3a08: /* roundps */ | |
6624 | case 0x660f3a09: /* roundpd */ | |
6625 | case 0x660f3a0a: /* roundss */ | |
6626 | case 0x660f3a0b: /* roundsd */ | |
6627 | case 0x660f3a0c: /* blendps */ | |
6628 | case 0x660f3a0d: /* blendpd */ | |
6629 | case 0x660f3a0e: /* pblendw */ | |
6630 | case 0x660f3a0f: /* palignr */ | |
6631 | case 0x660f3a20: /* pinsrb */ | |
6632 | case 0x660f3a21: /* insertps */ | |
6633 | case 0x660f3a22: /* pinsrd pinsrq */ | |
6634 | case 0x660f3a40: /* dpps */ | |
6635 | case 0x660f3a41: /* dppd */ | |
6636 | case 0x660f3a42: /* mpsadbw */ | |
6637 | case 0x660f3a60: /* pcmpestrm */ | |
6638 | case 0x660f3a61: /* pcmpestri */ | |
6639 | case 0x660f3a62: /* pcmpistrm */ | |
6640 | case 0x660f3a63: /* pcmpistri */ | |
6641 | case 0x0f51: /* sqrtps */ | |
6642 | case 0x660f51: /* sqrtpd */ | |
6643 | case 0xf20f51: /* sqrtsd */ | |
6644 | case 0xf30f51: /* sqrtss */ | |
6645 | case 0x0f52: /* rsqrtps */ | |
6646 | case 0xf30f52: /* rsqrtss */ | |
6647 | case 0x0f53: /* rcpps */ | |
6648 | case 0xf30f53: /* rcpss */ | |
6649 | case 0x0f54: /* andps */ | |
6650 | case 0x660f54: /* andpd */ | |
6651 | case 0x0f55: /* andnps */ | |
6652 | case 0x660f55: /* andnpd */ | |
6653 | case 0x0f56: /* orps */ | |
6654 | case 0x660f56: /* orpd */ | |
6655 | case 0x0f57: /* xorps */ | |
6656 | case 0x660f57: /* xorpd */ | |
6657 | case 0x0f58: /* addps */ | |
6658 | case 0x660f58: /* addpd */ | |
6659 | case 0xf20f58: /* addsd */ | |
6660 | case 0xf30f58: /* addss */ | |
6661 | case 0x0f59: /* mulps */ | |
6662 | case 0x660f59: /* mulpd */ | |
6663 | case 0xf20f59: /* mulsd */ | |
6664 | case 0xf30f59: /* mulss */ | |
6665 | case 0x0f5a: /* cvtps2pd */ | |
6666 | case 0x660f5a: /* cvtpd2ps */ | |
6667 | case 0xf20f5a: /* cvtsd2ss */ | |
6668 | case 0xf30f5a: /* cvtss2sd */ | |
6669 | case 0x0f5b: /* cvtdq2ps */ | |
6670 | case 0x660f5b: /* cvtps2dq */ | |
6671 | case 0xf30f5b: /* cvttps2dq */ | |
6672 | case 0x0f5c: /* subps */ | |
6673 | case 0x660f5c: /* subpd */ | |
6674 | case 0xf20f5c: /* subsd */ | |
6675 | case 0xf30f5c: /* subss */ | |
6676 | case 0x0f5d: /* minps */ | |
6677 | case 0x660f5d: /* minpd */ | |
6678 | case 0xf20f5d: /* minsd */ | |
6679 | case 0xf30f5d: /* minss */ | |
6680 | case 0x0f5e: /* divps */ | |
6681 | case 0x660f5e: /* divpd */ | |
6682 | case 0xf20f5e: /* divsd */ | |
6683 | case 0xf30f5e: /* divss */ | |
6684 | case 0x0f5f: /* maxps */ | |
6685 | case 0x660f5f: /* maxpd */ | |
6686 | case 0xf20f5f: /* maxsd */ | |
6687 | case 0xf30f5f: /* maxss */ | |
6688 | case 0x660f60: /* punpcklbw */ | |
6689 | case 0x660f61: /* punpcklwd */ | |
6690 | case 0x660f62: /* punpckldq */ | |
6691 | case 0x660f63: /* packsswb */ | |
6692 | case 0x660f64: /* pcmpgtb */ | |
6693 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 6694 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
6695 | case 0x660f67: /* packuswb */ |
6696 | case 0x660f68: /* punpckhbw */ | |
6697 | case 0x660f69: /* punpckhwd */ | |
6698 | case 0x660f6a: /* punpckhdq */ | |
6699 | case 0x660f6b: /* packssdw */ | |
6700 | case 0x660f6c: /* punpcklqdq */ | |
6701 | case 0x660f6d: /* punpckhqdq */ | |
6702 | case 0x660f6e: /* movd */ | |
6703 | case 0x660f6f: /* movdqa */ | |
6704 | case 0xf30f6f: /* movdqu */ | |
6705 | case 0x660f70: /* pshufd */ | |
6706 | case 0xf20f70: /* pshuflw */ | |
6707 | case 0xf30f70: /* pshufhw */ | |
6708 | case 0x660f74: /* pcmpeqb */ | |
6709 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 6710 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
6711 | case 0x660f7c: /* haddpd */ |
6712 | case 0xf20f7c: /* haddps */ | |
6713 | case 0x660f7d: /* hsubpd */ | |
6714 | case 0xf20f7d: /* hsubps */ | |
6715 | case 0xf30f7e: /* movq */ | |
6716 | case 0x0fc2: /* cmpps */ | |
6717 | case 0x660fc2: /* cmppd */ | |
6718 | case 0xf20fc2: /* cmpsd */ | |
6719 | case 0xf30fc2: /* cmpss */ | |
6720 | case 0x660fc4: /* pinsrw */ | |
6721 | case 0x0fc6: /* shufps */ | |
6722 | case 0x660fc6: /* shufpd */ | |
6723 | case 0x660fd0: /* addsubpd */ | |
6724 | case 0xf20fd0: /* addsubps */ | |
6725 | case 0x660fd1: /* psrlw */ | |
6726 | case 0x660fd2: /* psrld */ | |
6727 | case 0x660fd3: /* psrlq */ | |
6728 | case 0x660fd4: /* paddq */ | |
6729 | case 0x660fd5: /* pmullw */ | |
6730 | case 0xf30fd6: /* movq2dq */ | |
6731 | case 0x660fd8: /* psubusb */ | |
6732 | case 0x660fd9: /* psubusw */ | |
6733 | case 0x660fda: /* pminub */ | |
6734 | case 0x660fdb: /* pand */ | |
6735 | case 0x660fdc: /* paddusb */ | |
6736 | case 0x660fdd: /* paddusw */ | |
6737 | case 0x660fde: /* pmaxub */ | |
6738 | case 0x660fdf: /* pandn */ | |
6739 | case 0x660fe0: /* pavgb */ | |
6740 | case 0x660fe1: /* psraw */ | |
6741 | case 0x660fe2: /* psrad */ | |
6742 | case 0x660fe3: /* pavgw */ | |
6743 | case 0x660fe4: /* pmulhuw */ | |
6744 | case 0x660fe5: /* pmulhw */ | |
6745 | case 0x660fe6: /* cvttpd2dq */ | |
6746 | case 0xf20fe6: /* cvtpd2dq */ | |
6747 | case 0xf30fe6: /* cvtdq2pd */ | |
6748 | case 0x660fe8: /* psubsb */ | |
6749 | case 0x660fe9: /* psubsw */ | |
6750 | case 0x660fea: /* pminsw */ | |
6751 | case 0x660feb: /* por */ | |
6752 | case 0x660fec: /* paddsb */ | |
6753 | case 0x660fed: /* paddsw */ | |
6754 | case 0x660fee: /* pmaxsw */ | |
6755 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 6756 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
6757 | case 0x660ff1: /* psllw */ |
6758 | case 0x660ff2: /* pslld */ | |
6759 | case 0x660ff3: /* psllq */ | |
6760 | case 0x660ff4: /* pmuludq */ | |
6761 | case 0x660ff5: /* pmaddwd */ | |
6762 | case 0x660ff6: /* psadbw */ | |
6763 | case 0x660ff8: /* psubb */ | |
6764 | case 0x660ff9: /* psubw */ | |
56d2815c | 6765 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
6766 | case 0x660ffb: /* psubq */ |
6767 | case 0x660ffc: /* paddb */ | |
6768 | case 0x660ffd: /* paddw */ | |
56d2815c | 6769 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
6770 | if (i386_record_modrm (&ir)) |
6771 | return -1; | |
6772 | ir.reg |= rex_r; | |
c131fcee | 6773 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a HZ |
6774 | goto no_support; |
6775 | record_arch_list_add_reg (ir.regcache, | |
6776 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
6777 | if ((opcode & 0xfffffffc) == 0x660f3a60) | |
6778 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6779 | break; | |
6780 | ||
6781 | case 0x0f11: /* movups */ | |
6782 | case 0x660f11: /* movupd */ | |
6783 | case 0xf30f11: /* movss */ | |
6784 | case 0xf20f11: /* movsd */ | |
6785 | case 0x0f13: /* movlps */ | |
6786 | case 0x660f13: /* movlpd */ | |
6787 | case 0x0f17: /* movhps */ | |
6788 | case 0x660f17: /* movhpd */ | |
6789 | case 0x0f29: /* movaps */ | |
6790 | case 0x660f29: /* movapd */ | |
6791 | case 0x660f3a14: /* pextrb */ | |
6792 | case 0x660f3a15: /* pextrw */ | |
6793 | case 0x660f3a16: /* pextrd pextrq */ | |
6794 | case 0x660f3a17: /* extractps */ | |
6795 | case 0x660f7f: /* movdqa */ | |
6796 | case 0xf30f7f: /* movdqu */ | |
6797 | if (i386_record_modrm (&ir)) | |
6798 | return -1; | |
6799 | if (ir.mod == 3) | |
6800 | { | |
6801 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
6802 | || opcode == 0x0f17 || opcode == 0x660f17) | |
6803 | goto no_support; | |
6804 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
6805 | if (!i386_xmm_regnum_p (gdbarch, |
6806 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
6807 | goto no_support; |
6808 | record_arch_list_add_reg (ir.regcache, | |
6809 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6810 | } | |
6811 | else | |
6812 | { | |
6813 | switch (opcode) | |
6814 | { | |
6815 | case 0x660f3a14: | |
6816 | ir.ot = OT_BYTE; | |
6817 | break; | |
6818 | case 0x660f3a15: | |
6819 | ir.ot = OT_WORD; | |
6820 | break; | |
6821 | case 0x660f3a16: | |
6822 | ir.ot = OT_LONG; | |
6823 | break; | |
6824 | case 0x660f3a17: | |
6825 | ir.ot = OT_QUAD; | |
6826 | break; | |
6827 | default: | |
6828 | ir.ot = OT_DQUAD; | |
6829 | break; | |
6830 | } | |
6831 | if (i386_record_lea_modrm (&ir)) | |
6832 | return -1; | |
6833 | } | |
6834 | break; | |
6835 | ||
6836 | case 0x0f2b: /* movntps */ | |
6837 | case 0x660f2b: /* movntpd */ | |
6838 | case 0x0fe7: /* movntq */ | |
6839 | case 0x660fe7: /* movntdq */ | |
6840 | if (ir.mod == 3) | |
6841 | goto no_support; | |
6842 | if (opcode == 0x0fe7) | |
6843 | ir.ot = OT_QUAD; | |
6844 | else | |
6845 | ir.ot = OT_DQUAD; | |
6846 | if (i386_record_lea_modrm (&ir)) | |
6847 | return -1; | |
6848 | break; | |
6849 | ||
6850 | case 0xf30f2c: /* cvttss2si */ | |
6851 | case 0xf20f2c: /* cvttsd2si */ | |
6852 | case 0xf30f2d: /* cvtss2si */ | |
6853 | case 0xf20f2d: /* cvtsd2si */ | |
6854 | case 0xf20f38f0: /* crc32 */ | |
6855 | case 0xf20f38f1: /* crc32 */ | |
6856 | case 0x0f50: /* movmskps */ | |
6857 | case 0x660f50: /* movmskpd */ | |
6858 | case 0x0fc5: /* pextrw */ | |
6859 | case 0x660fc5: /* pextrw */ | |
6860 | case 0x0fd7: /* pmovmskb */ | |
6861 | case 0x660fd7: /* pmovmskb */ | |
6862 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
6863 | break; | |
6864 | ||
6865 | case 0x0f3800: /* pshufb */ | |
6866 | case 0x0f3801: /* phaddw */ | |
6867 | case 0x0f3802: /* phaddd */ | |
6868 | case 0x0f3803: /* phaddsw */ | |
6869 | case 0x0f3804: /* pmaddubsw */ | |
6870 | case 0x0f3805: /* phsubw */ | |
6871 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 6872 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
6873 | case 0x0f3808: /* psignb */ |
6874 | case 0x0f3809: /* psignw */ | |
6875 | case 0x0f380a: /* psignd */ | |
6876 | case 0x0f380b: /* pmulhrsw */ | |
6877 | case 0x0f381c: /* pabsb */ | |
6878 | case 0x0f381d: /* pabsw */ | |
6879 | case 0x0f381e: /* pabsd */ | |
6880 | case 0x0f382b: /* packusdw */ | |
6881 | case 0x0f3830: /* pmovzxbw */ | |
6882 | case 0x0f3831: /* pmovzxbd */ | |
6883 | case 0x0f3832: /* pmovzxbq */ | |
6884 | case 0x0f3833: /* pmovzxwd */ | |
6885 | case 0x0f3834: /* pmovzxwq */ | |
6886 | case 0x0f3835: /* pmovzxdq */ | |
6887 | case 0x0f3837: /* pcmpgtq */ | |
6888 | case 0x0f3838: /* pminsb */ | |
6889 | case 0x0f3839: /* pminsd */ | |
6890 | case 0x0f383a: /* pminuw */ | |
6891 | case 0x0f383b: /* pminud */ | |
6892 | case 0x0f383c: /* pmaxsb */ | |
6893 | case 0x0f383d: /* pmaxsd */ | |
6894 | case 0x0f383e: /* pmaxuw */ | |
6895 | case 0x0f383f: /* pmaxud */ | |
6896 | case 0x0f3840: /* pmulld */ | |
6897 | case 0x0f3841: /* phminposuw */ | |
6898 | case 0x0f3a0f: /* palignr */ | |
6899 | case 0x0f60: /* punpcklbw */ | |
6900 | case 0x0f61: /* punpcklwd */ | |
6901 | case 0x0f62: /* punpckldq */ | |
6902 | case 0x0f63: /* packsswb */ | |
6903 | case 0x0f64: /* pcmpgtb */ | |
6904 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 6905 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
6906 | case 0x0f67: /* packuswb */ |
6907 | case 0x0f68: /* punpckhbw */ | |
6908 | case 0x0f69: /* punpckhwd */ | |
6909 | case 0x0f6a: /* punpckhdq */ | |
6910 | case 0x0f6b: /* packssdw */ | |
6911 | case 0x0f6e: /* movd */ | |
6912 | case 0x0f6f: /* movq */ | |
6913 | case 0x0f70: /* pshufw */ | |
6914 | case 0x0f74: /* pcmpeqb */ | |
6915 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 6916 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
6917 | case 0x0fc4: /* pinsrw */ |
6918 | case 0x0fd1: /* psrlw */ | |
6919 | case 0x0fd2: /* psrld */ | |
6920 | case 0x0fd3: /* psrlq */ | |
6921 | case 0x0fd4: /* paddq */ | |
6922 | case 0x0fd5: /* pmullw */ | |
6923 | case 0xf20fd6: /* movdq2q */ | |
6924 | case 0x0fd8: /* psubusb */ | |
6925 | case 0x0fd9: /* psubusw */ | |
6926 | case 0x0fda: /* pminub */ | |
6927 | case 0x0fdb: /* pand */ | |
6928 | case 0x0fdc: /* paddusb */ | |
6929 | case 0x0fdd: /* paddusw */ | |
6930 | case 0x0fde: /* pmaxub */ | |
6931 | case 0x0fdf: /* pandn */ | |
6932 | case 0x0fe0: /* pavgb */ | |
6933 | case 0x0fe1: /* psraw */ | |
6934 | case 0x0fe2: /* psrad */ | |
6935 | case 0x0fe3: /* pavgw */ | |
6936 | case 0x0fe4: /* pmulhuw */ | |
6937 | case 0x0fe5: /* pmulhw */ | |
6938 | case 0x0fe8: /* psubsb */ | |
6939 | case 0x0fe9: /* psubsw */ | |
6940 | case 0x0fea: /* pminsw */ | |
6941 | case 0x0feb: /* por */ | |
6942 | case 0x0fec: /* paddsb */ | |
6943 | case 0x0fed: /* paddsw */ | |
6944 | case 0x0fee: /* pmaxsw */ | |
6945 | case 0x0fef: /* pxor */ | |
6946 | case 0x0ff1: /* psllw */ | |
6947 | case 0x0ff2: /* pslld */ | |
6948 | case 0x0ff3: /* psllq */ | |
6949 | case 0x0ff4: /* pmuludq */ | |
6950 | case 0x0ff5: /* pmaddwd */ | |
6951 | case 0x0ff6: /* psadbw */ | |
6952 | case 0x0ff8: /* psubb */ | |
6953 | case 0x0ff9: /* psubw */ | |
56d2815c | 6954 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
6955 | case 0x0ffb: /* psubq */ |
6956 | case 0x0ffc: /* paddb */ | |
6957 | case 0x0ffd: /* paddw */ | |
56d2815c | 6958 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
6959 | if (i386_record_modrm (&ir)) |
6960 | return -1; | |
6961 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6962 | goto no_support; | |
6963 | record_arch_list_add_reg (ir.regcache, | |
6964 | I387_MM0_REGNUM (tdep) + ir.reg); | |
6965 | break; | |
6966 | ||
6967 | case 0x0f71: /* psllw */ | |
6968 | case 0x0f72: /* pslld */ | |
6969 | case 0x0f73: /* psllq */ | |
6970 | if (i386_record_modrm (&ir)) | |
6971 | return -1; | |
6972 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
6973 | goto no_support; | |
6974 | record_arch_list_add_reg (ir.regcache, | |
6975 | I387_MM0_REGNUM (tdep) + ir.rm); | |
6976 | break; | |
6977 | ||
6978 | case 0x660f71: /* psllw */ | |
6979 | case 0x660f72: /* pslld */ | |
6980 | case 0x660f73: /* psllq */ | |
6981 | if (i386_record_modrm (&ir)) | |
6982 | return -1; | |
6983 | ir.rm |= ir.rex_b; | |
c131fcee | 6984 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a HZ |
6985 | goto no_support; |
6986 | record_arch_list_add_reg (ir.regcache, | |
6987 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6988 | break; | |
6989 | ||
6990 | case 0x0f7e: /* movd */ | |
6991 | case 0x660f7e: /* movd */ | |
6992 | if (i386_record_modrm (&ir)) | |
6993 | return -1; | |
6994 | if (ir.mod == 3) | |
6995 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
6996 | else | |
6997 | { | |
6998 | if (ir.dflag == 2) | |
6999 | ir.ot = OT_QUAD; | |
7000 | else | |
7001 | ir.ot = OT_LONG; | |
7002 | if (i386_record_lea_modrm (&ir)) | |
7003 | return -1; | |
7004 | } | |
7005 | break; | |
7006 | ||
7007 | case 0x0f7f: /* movq */ | |
7008 | if (i386_record_modrm (&ir)) | |
7009 | return -1; | |
7010 | if (ir.mod == 3) | |
7011 | { | |
7012 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7013 | goto no_support; | |
7014 | record_arch_list_add_reg (ir.regcache, | |
7015 | I387_MM0_REGNUM (tdep) + ir.rm); | |
7016 | } | |
7017 | else | |
7018 | { | |
7019 | ir.ot = OT_QUAD; | |
7020 | if (i386_record_lea_modrm (&ir)) | |
7021 | return -1; | |
7022 | } | |
7023 | break; | |
7024 | ||
7025 | case 0xf30fb8: /* popcnt */ | |
7026 | if (i386_record_modrm (&ir)) | |
7027 | return -1; | |
7028 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); | |
7029 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7030 | break; | |
7031 | ||
7032 | case 0x660fd6: /* movq */ | |
7033 | if (i386_record_modrm (&ir)) | |
7034 | return -1; | |
7035 | if (ir.mod == 3) | |
7036 | { | |
7037 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7038 | if (!i386_xmm_regnum_p (gdbarch, |
7039 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
7040 | goto no_support; |
7041 | record_arch_list_add_reg (ir.regcache, | |
7042 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
7043 | } | |
7044 | else | |
7045 | { | |
7046 | ir.ot = OT_QUAD; | |
7047 | if (i386_record_lea_modrm (&ir)) | |
7048 | return -1; | |
7049 | } | |
7050 | break; | |
7051 | ||
7052 | case 0x660f3817: /* ptest */ | |
7053 | case 0x0f2e: /* ucomiss */ | |
7054 | case 0x660f2e: /* ucomisd */ | |
7055 | case 0x0f2f: /* comiss */ | |
7056 | case 0x660f2f: /* comisd */ | |
7057 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7058 | break; | |
7059 | ||
7060 | case 0x0ff7: /* maskmovq */ | |
7061 | regcache_raw_read_unsigned (ir.regcache, | |
7062 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7063 | &addr); | |
7064 | if (record_arch_list_add_mem (addr, 64)) | |
7065 | return -1; | |
7066 | break; | |
7067 | ||
7068 | case 0x660ff7: /* maskmovdqu */ | |
7069 | regcache_raw_read_unsigned (ir.regcache, | |
7070 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7071 | &addr); | |
7072 | if (record_arch_list_add_mem (addr, 128)) | |
7073 | return -1; | |
7074 | break; | |
7075 | ||
7076 | default: | |
7077 | goto no_support; | |
7078 | break; | |
7079 | } | |
7080 | break; | |
7ad10968 HZ |
7081 | |
7082 | default: | |
7ad10968 HZ |
7083 | goto no_support; |
7084 | break; | |
7085 | } | |
7086 | ||
cf648174 HZ |
7087 | /* In the future, maybe still need to deal with need_dasm. */ |
7088 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
7089 | if (record_arch_list_add_end ()) |
7090 | return -1; | |
7091 | ||
7092 | return 0; | |
7093 | ||
01fe1b41 | 7094 | no_support: |
a3c4230a HZ |
7095 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
7096 | "at address %s.\n"), | |
7097 | (unsigned int) (opcode), | |
7098 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
7099 | return -1; |
7100 | } | |
7101 | ||
cf648174 HZ |
7102 | static const int i386_record_regmap[] = |
7103 | { | |
7104 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
7105 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
7106 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7107 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
7108 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
7109 | }; | |
7110 | ||
7a697b8d SS |
7111 | /* Check that the given address appears suitable for a fast |
7112 | tracepoint, which on x86 means that we need an instruction of at | |
7113 | least 5 bytes, so that we can overwrite it with a 4-byte-offset | |
7114 | jump and not have to worry about program jumps to an address in the | |
7115 | middle of the tracepoint jump. Returns 1 if OK, and writes a size | |
7116 | of instruction to replace, and 0 if not, plus an explanatory | |
7117 | string. */ | |
7118 | ||
7119 | static int | |
7120 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
7121 | CORE_ADDR addr, int *isize, char **msg) | |
7122 | { | |
7123 | int len, jumplen; | |
7124 | static struct ui_file *gdb_null = NULL; | |
7125 | ||
7126 | /* This is based on the target agent using a 4-byte relative jump. | |
7127 | Alternate future possibilities include 8-byte offset for x86-84, | |
7128 | or 3-byte jumps if the program has trampoline space close by. */ | |
7129 | jumplen = 5; | |
7130 | ||
7131 | /* Dummy file descriptor for the disassembler. */ | |
7132 | if (!gdb_null) | |
7133 | gdb_null = ui_file_new (); | |
7134 | ||
7135 | /* Check for fit. */ | |
7136 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
7137 | if (len < jumplen) | |
7138 | { | |
7139 | /* Return a bit of target-specific detail to add to the caller's | |
7140 | generic failure message. */ | |
7141 | if (msg) | |
1777feb0 MS |
7142 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
7143 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
7144 | len, jumplen); |
7145 | return 0; | |
7146 | } | |
7147 | ||
7148 | if (isize) | |
7149 | *isize = len; | |
7150 | if (msg) | |
7151 | *msg = NULL; | |
7152 | return 1; | |
7153 | } | |
7154 | ||
90884b2b L |
7155 | static int |
7156 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
7157 | struct tdesc_arch_data *tdesc_data) | |
7158 | { | |
7159 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee L |
7160 | const struct tdesc_feature *feature_core; |
7161 | const struct tdesc_feature *feature_sse, *feature_avx; | |
90884b2b L |
7162 | int i, num_regs, valid_p; |
7163 | ||
7164 | if (! tdesc_has_registers (tdesc)) | |
7165 | return 0; | |
7166 | ||
7167 | /* Get core registers. */ | |
7168 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
7169 | if (feature_core == NULL) |
7170 | return 0; | |
90884b2b L |
7171 | |
7172 | /* Get SSE registers. */ | |
c131fcee | 7173 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 7174 | |
c131fcee L |
7175 | /* Try AVX registers. */ |
7176 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
7177 | ||
90884b2b L |
7178 | valid_p = 1; |
7179 | ||
c131fcee L |
7180 | /* The XCR0 bits. */ |
7181 | if (feature_avx) | |
7182 | { | |
3a13a53b L |
7183 | /* AVX register description requires SSE register description. */ |
7184 | if (!feature_sse) | |
7185 | return 0; | |
7186 | ||
c131fcee L |
7187 | tdep->xcr0 = I386_XSTATE_AVX_MASK; |
7188 | ||
7189 | /* It may have been set by OSABI initialization function. */ | |
7190 | if (tdep->num_ymm_regs == 0) | |
7191 | { | |
7192 | tdep->ymmh_register_names = i386_ymmh_names; | |
7193 | tdep->num_ymm_regs = 8; | |
7194 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
7195 | } | |
7196 | ||
7197 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
7198 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
7199 | tdep->ymm0h_regnum + i, | |
7200 | tdep->ymmh_register_names[i]); | |
7201 | } | |
3a13a53b | 7202 | else if (feature_sse) |
c131fcee | 7203 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
3a13a53b L |
7204 | else |
7205 | { | |
7206 | tdep->xcr0 = I386_XSTATE_X87_MASK; | |
7207 | tdep->num_xmm_regs = 0; | |
7208 | } | |
c131fcee | 7209 | |
90884b2b L |
7210 | num_regs = tdep->num_core_regs; |
7211 | for (i = 0; i < num_regs; i++) | |
7212 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
7213 | tdep->register_names[i]); | |
7214 | ||
3a13a53b L |
7215 | if (feature_sse) |
7216 | { | |
7217 | /* Need to include %mxcsr, so add one. */ | |
7218 | num_regs += tdep->num_xmm_regs + 1; | |
7219 | for (; i < num_regs; i++) | |
7220 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
7221 | tdep->register_names[i]); | |
7222 | } | |
90884b2b L |
7223 | |
7224 | return valid_p; | |
7225 | } | |
7226 | ||
7ad10968 HZ |
7227 | \f |
7228 | static struct gdbarch * | |
7229 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
7230 | { | |
7231 | struct gdbarch_tdep *tdep; | |
7232 | struct gdbarch *gdbarch; | |
90884b2b L |
7233 | struct tdesc_arch_data *tdesc_data; |
7234 | const struct target_desc *tdesc; | |
1ba53b71 | 7235 | int mm0_regnum; |
c131fcee | 7236 | int ymm0_regnum; |
7ad10968 HZ |
7237 | |
7238 | /* If there is already a candidate, use it. */ | |
7239 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
7240 | if (arches != NULL) | |
7241 | return arches->gdbarch; | |
7242 | ||
7243 | /* Allocate space for the new architecture. */ | |
7244 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
7245 | gdbarch = gdbarch_alloc (&info, tdep); | |
7246 | ||
7247 | /* General-purpose registers. */ | |
7248 | tdep->gregset = NULL; | |
7249 | tdep->gregset_reg_offset = NULL; | |
7250 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
7251 | tdep->sizeof_gregset = 0; | |
7252 | ||
7253 | /* Floating-point registers. */ | |
7254 | tdep->fpregset = NULL; | |
7255 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
7256 | ||
c131fcee L |
7257 | tdep->xstateregset = NULL; |
7258 | ||
7ad10968 HZ |
7259 | /* The default settings include the FPU registers, the MMX registers |
7260 | and the SSE registers. This can be overridden for a specific ABI | |
7261 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
7262 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 7263 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
7264 | |
7265 | tdep->st0_regnum = I386_ST0_REGNUM; | |
7266 | ||
7ad10968 HZ |
7267 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
7268 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
7269 | ||
7270 | tdep->jb_pc_offset = -1; | |
7271 | tdep->struct_return = pcc_struct_return; | |
7272 | tdep->sigtramp_start = 0; | |
7273 | tdep->sigtramp_end = 0; | |
7274 | tdep->sigtramp_p = i386_sigtramp_p; | |
7275 | tdep->sigcontext_addr = NULL; | |
7276 | tdep->sc_reg_offset = NULL; | |
7277 | tdep->sc_pc_offset = -1; | |
7278 | tdep->sc_sp_offset = -1; | |
7279 | ||
c131fcee L |
7280 | tdep->xsave_xcr0_offset = -1; |
7281 | ||
cf648174 HZ |
7282 | tdep->record_regmap = i386_record_regmap; |
7283 | ||
205c306f DM |
7284 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
7285 | ||
7ad10968 HZ |
7286 | /* The format used for `long double' on almost all i386 targets is |
7287 | the i387 extended floating-point format. In fact, of all targets | |
7288 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
7289 | on having a `long double' that's not `long' at all. */ | |
7290 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
7291 | ||
7292 | /* Although the i387 extended floating-point has only 80 significant | |
7293 | bits, a `long double' actually takes up 96, probably to enforce | |
7294 | alignment. */ | |
7295 | set_gdbarch_long_double_bit (gdbarch, 96); | |
7296 | ||
7ad10968 HZ |
7297 | /* Register numbers of various important registers. */ |
7298 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
7299 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
7300 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
7301 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
7302 | ||
7303 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
7304 | numbering schemes on the i386: dbx and SVR4. These schemes | |
7305 | differ in how they number %ebp, %esp, %eflags, and the | |
7306 | floating-point registers, and are implemented by the arrays | |
7307 | dbx_register_map[] and svr4_dbx_register_map in | |
7308 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
7309 | gcc/config/i386.c, which it designates as the "default" register | |
7310 | map used in 64bit mode. This last register numbering scheme is | |
7311 | implemented in dbx64_register_map, and is used for AMD64; see | |
7312 | amd64-tdep.c. | |
7313 | ||
7314 | Currently, each GCC i386 target always uses the same register | |
7315 | numbering scheme across all its supported debugging formats | |
7316 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
7317 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
7318 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
7319 | respective config header in a manner independent of the requested | |
7320 | output debugging format. | |
7321 | ||
7322 | This does not match the arrangement below, which presumes that | |
7323 | the SDB and stabs numbering schemes differ from the DWARF and | |
7324 | DWARF 2 ones. The reason for this arrangement is that it is | |
7325 | likely to get the numbering scheme for the target's | |
7326 | default/native debug format right. For targets where GCC is the | |
7327 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
7328 | targets where the native toolchain uses a different numbering | |
7329 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
7330 | the defaults below will have to be overridden, like | |
7331 | i386_elf_init_abi() does. */ | |
7332 | ||
7333 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
7334 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7335 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7336 | ||
7337 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
7338 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
7339 | ||
7340 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
7341 | be in use on any of the supported i386 targets. */ | |
7342 | ||
7343 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
7344 | ||
7345 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
7346 | ||
7347 | /* Call dummy code. */ | |
7348 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
e04e5beb | 7349 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
7350 | |
7351 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
7352 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
7353 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
7354 | ||
7355 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
7356 | ||
7357 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
7358 | ||
7359 | /* Stack grows downward. */ | |
7360 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7361 | ||
7362 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
7363 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
7364 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
7365 | ||
7366 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
7367 | ||
7ad10968 HZ |
7368 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
7369 | ||
7370 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
7371 | ||
7372 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
7373 | ||
7374 | /* Add the i386 register groups. */ | |
7375 | i386_add_reggroups (gdbarch); | |
90884b2b | 7376 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 7377 | |
143985b7 AF |
7378 | /* Helper for function argument information. */ |
7379 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
7380 | ||
06da04c6 | 7381 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
7382 | appended to the list first, so that it supercedes the DWARF |
7383 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
7384 | currently fails). */ |
7385 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
7386 | ||
7387 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 7388 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 7389 | CFI info will be used if it is available. */ |
10458914 | 7390 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 7391 | |
acd5c798 | 7392 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 7393 | |
1ba53b71 | 7394 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
7395 | set_gdbarch_pseudo_register_read_value (gdbarch, |
7396 | i386_pseudo_register_read_value); | |
90884b2b L |
7397 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
7398 | ||
7399 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
7400 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
7401 | ||
c131fcee L |
7402 | /* Override the normal target description method to make the AVX |
7403 | upper halves anonymous. */ | |
7404 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
7405 | ||
7406 | /* Even though the default ABI only includes general-purpose registers, | |
7407 | floating-point registers and the SSE registers, we have to leave a | |
7408 | gap for the upper AVX registers. */ | |
7409 | set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); | |
90884b2b L |
7410 | |
7411 | /* Get the x86 target description from INFO. */ | |
7412 | tdesc = info.target_desc; | |
7413 | if (! tdesc_has_registers (tdesc)) | |
7414 | tdesc = tdesc_i386; | |
7415 | tdep->tdesc = tdesc; | |
7416 | ||
7417 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
7418 | tdep->register_names = i386_register_names; | |
7419 | ||
c131fcee L |
7420 | /* No upper YMM registers. */ |
7421 | tdep->ymmh_register_names = NULL; | |
7422 | tdep->ymm0h_regnum = -1; | |
7423 | ||
1ba53b71 L |
7424 | tdep->num_byte_regs = 8; |
7425 | tdep->num_word_regs = 8; | |
7426 | tdep->num_dword_regs = 0; | |
7427 | tdep->num_mmx_regs = 8; | |
c131fcee | 7428 | tdep->num_ymm_regs = 0; |
1ba53b71 | 7429 | |
90884b2b L |
7430 | tdesc_data = tdesc_data_alloc (); |
7431 | ||
dde08ee1 PA |
7432 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
7433 | ||
6710bf39 SS |
7434 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
7435 | ||
3ce1502b | 7436 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 7437 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 7438 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 7439 | |
c131fcee L |
7440 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
7441 | { | |
7442 | tdesc_data_cleanup (tdesc_data); | |
7443 | xfree (tdep); | |
7444 | gdbarch_free (gdbarch); | |
7445 | return NULL; | |
7446 | } | |
7447 | ||
1ba53b71 L |
7448 | /* Wire in pseudo registers. Number of pseudo registers may be |
7449 | changed. */ | |
7450 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
7451 | + tdep->num_word_regs | |
7452 | + tdep->num_dword_regs | |
c131fcee L |
7453 | + tdep->num_mmx_regs |
7454 | + tdep->num_ymm_regs)); | |
1ba53b71 | 7455 | |
90884b2b L |
7456 | /* Target description may be changed. */ |
7457 | tdesc = tdep->tdesc; | |
7458 | ||
90884b2b L |
7459 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
7460 | ||
7461 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
7462 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
7463 | ||
1ba53b71 L |
7464 | /* Make %al the first pseudo-register. */ |
7465 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
7466 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
7467 | ||
c131fcee | 7468 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
7469 | if (tdep->num_dword_regs) |
7470 | { | |
1c6272a6 | 7471 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
7472 | tdep->eax_regnum = ymm0_regnum; |
7473 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
7474 | } |
7475 | else | |
7476 | tdep->eax_regnum = -1; | |
7477 | ||
c131fcee L |
7478 | mm0_regnum = ymm0_regnum; |
7479 | if (tdep->num_ymm_regs) | |
7480 | { | |
1c6272a6 | 7481 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
7482 | tdep->ymm0_regnum = ymm0_regnum; |
7483 | mm0_regnum += tdep->num_ymm_regs; | |
7484 | } | |
7485 | else | |
7486 | tdep->ymm0_regnum = -1; | |
7487 | ||
1ba53b71 L |
7488 | if (tdep->num_mmx_regs != 0) |
7489 | { | |
1c6272a6 | 7490 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 L |
7491 | tdep->mm0_regnum = mm0_regnum; |
7492 | } | |
7493 | else | |
7494 | tdep->mm0_regnum = -1; | |
7495 | ||
06da04c6 | 7496 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 7497 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
7498 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
7499 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 7500 | |
8446b36a MK |
7501 | /* If we have a register mapping, enable the generic core file |
7502 | support, unless it has already been enabled. */ | |
7503 | if (tdep->gregset_reg_offset | |
7504 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
7505 | set_gdbarch_regset_from_core_section (gdbarch, | |
7506 | i386_regset_from_core_section); | |
7507 | ||
514f746b AR |
7508 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
7509 | i386_skip_permanent_breakpoint); | |
7510 | ||
7a697b8d SS |
7511 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
7512 | i386_fast_tracepoint_valid_at); | |
7513 | ||
a62cc96e AC |
7514 | return gdbarch; |
7515 | } | |
7516 | ||
8201327c MK |
7517 | static enum gdb_osabi |
7518 | i386_coff_osabi_sniffer (bfd *abfd) | |
7519 | { | |
762c5349 MK |
7520 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
7521 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
7522 | return GDB_OSABI_GO32; |
7523 | ||
7524 | return GDB_OSABI_UNKNOWN; | |
7525 | } | |
8201327c MK |
7526 | \f |
7527 | ||
28e9e0f0 MK |
7528 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
7529 | void _initialize_i386_tdep (void); | |
7530 | ||
c906108c | 7531 | void |
fba45db2 | 7532 | _initialize_i386_tdep (void) |
c906108c | 7533 | { |
a62cc96e AC |
7534 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
7535 | ||
fc338970 | 7536 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
7537 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
7538 | &disassembly_flavor, _("\ | |
7539 | Set the disassembly flavor."), _("\ | |
7540 | Show the disassembly flavor."), _("\ | |
7541 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
7542 | NULL, | |
7543 | NULL, /* FIXME: i18n: */ | |
7544 | &setlist, &showlist); | |
8201327c MK |
7545 | |
7546 | /* Add the variable that controls the convention for returning | |
7547 | structs. */ | |
7ab04401 AC |
7548 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
7549 | &struct_convention, _("\ | |
7550 | Set the convention for returning small structs."), _("\ | |
7551 | Show the convention for returning small structs."), _("\ | |
7552 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
7553 | is \"default\"."), | |
7554 | NULL, | |
7555 | NULL, /* FIXME: i18n: */ | |
7556 | &setlist, &showlist); | |
8201327c MK |
7557 | |
7558 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
7559 | i386_coff_osabi_sniffer); | |
8201327c | 7560 | |
05816f70 | 7561 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 7562 | i386_svr4_init_abi); |
05816f70 | 7563 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 7564 | i386_go32_init_abi); |
38c968cf | 7565 | |
209bd28e | 7566 | /* Initialize the i386-specific register groups. */ |
38c968cf | 7567 | i386_init_reggroups (); |
90884b2b L |
7568 | |
7569 | /* Initialize the standard target descriptions. */ | |
7570 | initialize_tdesc_i386 (); | |
3a13a53b | 7571 | initialize_tdesc_i386_mmx (); |
c131fcee | 7572 | initialize_tdesc_i386_avx (); |
c8d5aac9 L |
7573 | |
7574 | /* Tell remote stub that we support XML target description. */ | |
7575 | register_remote_support_xml ("i386"); | |
c906108c | 7576 | } |