Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
b811d2c2 | 3 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
82ca8957 | 25 | #include "dwarf2/frame.h" |
c906108c | 26 | #include "frame.h" |
acd5c798 MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
c906108c | 29 | #include "inferior.h" |
45741a9c | 30 | #include "infrun.h" |
acd5c798 | 31 | #include "gdbcmd.h" |
c906108c | 32 | #include "gdbcore.h" |
e6bb342a | 33 | #include "gdbtypes.h" |
dfe01d39 | 34 | #include "objfiles.h" |
acd5c798 MK |
35 | #include "osabi.h" |
36 | #include "regcache.h" | |
37 | #include "reggroups.h" | |
473f17b0 | 38 | #include "regset.h" |
c0d1d883 | 39 | #include "symfile.h" |
c906108c | 40 | #include "symtab.h" |
acd5c798 | 41 | #include "target.h" |
3b2ca824 | 42 | #include "target-float.h" |
fd0407d6 | 43 | #include "value.h" |
a89aa300 | 44 | #include "dis-asm.h" |
7a697b8d | 45 | #include "disasm.h" |
c8d5aac9 | 46 | #include "remote.h" |
d2a7c97a | 47 | #include "i386-tdep.h" |
61113f8b | 48 | #include "i387-tdep.h" |
268a13a5 | 49 | #include "gdbsupport/x86-xstate.h" |
1d509aa6 | 50 | #include "x86-tdep.h" |
d2a7c97a | 51 | |
7ad10968 | 52 | #include "record.h" |
d02ed0bb | 53 | #include "record-full.h" |
22916b07 YQ |
54 | #include "target-descriptions.h" |
55 | #include "arch/i386.h" | |
90884b2b | 56 | |
6710bf39 SS |
57 | #include "ax.h" |
58 | #include "ax-gdb.h" | |
59 | ||
55aa24fb SDJ |
60 | #include "stap-probe.h" |
61 | #include "user-regs.h" | |
62 | #include "cli/cli-utils.h" | |
63 | #include "expression.h" | |
64 | #include "parser-defs.h" | |
65 | #include <ctype.h> | |
325fac50 | 66 | #include <algorithm> |
7d7571f0 | 67 | #include <unordered_set> |
55aa24fb | 68 | |
c4fc7f1b | 69 | /* Register names. */ |
c40e1eab | 70 | |
90884b2b | 71 | static const char *i386_register_names[] = |
fc633446 MK |
72 | { |
73 | "eax", "ecx", "edx", "ebx", | |
74 | "esp", "ebp", "esi", "edi", | |
75 | "eip", "eflags", "cs", "ss", | |
76 | "ds", "es", "fs", "gs", | |
77 | "st0", "st1", "st2", "st3", | |
78 | "st4", "st5", "st6", "st7", | |
79 | "fctrl", "fstat", "ftag", "fiseg", | |
80 | "fioff", "foseg", "fooff", "fop", | |
81 | "xmm0", "xmm1", "xmm2", "xmm3", | |
82 | "xmm4", "xmm5", "xmm6", "xmm7", | |
83 | "mxcsr" | |
84 | }; | |
85 | ||
01f9f808 MS |
86 | static const char *i386_zmm_names[] = |
87 | { | |
88 | "zmm0", "zmm1", "zmm2", "zmm3", | |
89 | "zmm4", "zmm5", "zmm6", "zmm7" | |
90 | }; | |
91 | ||
92 | static const char *i386_zmmh_names[] = | |
93 | { | |
94 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
95 | "zmm4h", "zmm5h", "zmm6h", "zmm7h" | |
96 | }; | |
97 | ||
98 | static const char *i386_k_names[] = | |
99 | { | |
100 | "k0", "k1", "k2", "k3", | |
101 | "k4", "k5", "k6", "k7" | |
102 | }; | |
103 | ||
c131fcee L |
104 | static const char *i386_ymm_names[] = |
105 | { | |
106 | "ymm0", "ymm1", "ymm2", "ymm3", | |
107 | "ymm4", "ymm5", "ymm6", "ymm7", | |
108 | }; | |
109 | ||
110 | static const char *i386_ymmh_names[] = | |
111 | { | |
112 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
113 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
114 | }; | |
115 | ||
1dbcd68c WT |
116 | static const char *i386_mpx_names[] = |
117 | { | |
118 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
119 | }; | |
120 | ||
51547df6 MS |
121 | static const char* i386_pkeys_names[] = |
122 | { | |
123 | "pkru" | |
124 | }; | |
125 | ||
1dbcd68c WT |
126 | /* Register names for MPX pseudo-registers. */ |
127 | ||
128 | static const char *i386_bnd_names[] = | |
129 | { | |
130 | "bnd0", "bnd1", "bnd2", "bnd3" | |
131 | }; | |
132 | ||
c4fc7f1b | 133 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 134 | |
90884b2b | 135 | static const char *i386_mmx_names[] = |
28fc6740 AC |
136 | { |
137 | "mm0", "mm1", "mm2", "mm3", | |
138 | "mm4", "mm5", "mm6", "mm7" | |
139 | }; | |
c40e1eab | 140 | |
1ba53b71 L |
141 | /* Register names for byte pseudo-registers. */ |
142 | ||
143 | static const char *i386_byte_names[] = | |
144 | { | |
145 | "al", "cl", "dl", "bl", | |
146 | "ah", "ch", "dh", "bh" | |
147 | }; | |
148 | ||
149 | /* Register names for word pseudo-registers. */ | |
150 | ||
151 | static const char *i386_word_names[] = | |
152 | { | |
153 | "ax", "cx", "dx", "bx", | |
9cad29ac | 154 | "", "bp", "si", "di" |
1ba53b71 L |
155 | }; |
156 | ||
01f9f808 MS |
157 | /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have |
158 | 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, | |
159 | we have 16 upper ZMM regs that have to be handled differently. */ | |
160 | ||
161 | const int num_lower_zmm_regs = 16; | |
162 | ||
1ba53b71 | 163 | /* MMX register? */ |
c40e1eab | 164 | |
28fc6740 | 165 | static int |
5716833c | 166 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 167 | { |
1ba53b71 L |
168 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
169 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
170 | |
171 | if (mm0_regnum < 0) | |
172 | return 0; | |
173 | ||
1ba53b71 L |
174 | regnum -= mm0_regnum; |
175 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
176 | } | |
177 | ||
178 | /* Byte register? */ | |
179 | ||
180 | int | |
181 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
182 | { | |
183 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
184 | ||
185 | regnum -= tdep->al_regnum; | |
186 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
187 | } | |
188 | ||
189 | /* Word register? */ | |
190 | ||
191 | int | |
192 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
193 | { | |
194 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
195 | ||
196 | regnum -= tdep->ax_regnum; | |
197 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
198 | } | |
199 | ||
200 | /* Dword register? */ | |
201 | ||
202 | int | |
203 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
204 | { | |
205 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
206 | int eax_regnum = tdep->eax_regnum; | |
207 | ||
208 | if (eax_regnum < 0) | |
209 | return 0; | |
210 | ||
211 | regnum -= eax_regnum; | |
212 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
213 | } |
214 | ||
01f9f808 MS |
215 | /* AVX512 register? */ |
216 | ||
217 | int | |
218 | i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
219 | { | |
220 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
221 | int zmm0h_regnum = tdep->zmm0h_regnum; | |
222 | ||
223 | if (zmm0h_regnum < 0) | |
224 | return 0; | |
225 | ||
226 | regnum -= zmm0h_regnum; | |
227 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
228 | } | |
229 | ||
230 | int | |
231 | i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
232 | { | |
233 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
234 | int zmm0_regnum = tdep->zmm0_regnum; | |
235 | ||
236 | if (zmm0_regnum < 0) | |
237 | return 0; | |
238 | ||
239 | regnum -= zmm0_regnum; | |
240 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
241 | } | |
242 | ||
243 | int | |
244 | i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) | |
245 | { | |
246 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
247 | int k0_regnum = tdep->k0_regnum; | |
248 | ||
249 | if (k0_regnum < 0) | |
250 | return 0; | |
251 | ||
252 | regnum -= k0_regnum; | |
253 | return regnum >= 0 && regnum < I387_NUM_K_REGS; | |
254 | } | |
255 | ||
9191d390 | 256 | static int |
c131fcee L |
257 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
258 | { | |
259 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
260 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
261 | ||
262 | if (ymm0h_regnum < 0) | |
263 | return 0; | |
264 | ||
265 | regnum -= ymm0h_regnum; | |
266 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
267 | } | |
268 | ||
269 | /* AVX register? */ | |
270 | ||
271 | int | |
272 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
273 | { | |
274 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
275 | int ymm0_regnum = tdep->ymm0_regnum; | |
276 | ||
277 | if (ymm0_regnum < 0) | |
278 | return 0; | |
279 | ||
280 | regnum -= ymm0_regnum; | |
281 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
282 | } | |
283 | ||
01f9f808 MS |
284 | static int |
285 | i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
286 | { | |
287 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
288 | int ymm16h_regnum = tdep->ymm16h_regnum; | |
289 | ||
290 | if (ymm16h_regnum < 0) | |
291 | return 0; | |
292 | ||
293 | regnum -= ymm16h_regnum; | |
294 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
295 | } | |
296 | ||
297 | int | |
298 | i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
299 | { | |
300 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
301 | int ymm16_regnum = tdep->ymm16_regnum; | |
302 | ||
303 | if (ymm16_regnum < 0) | |
304 | return 0; | |
305 | ||
306 | regnum -= ymm16_regnum; | |
307 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
308 | } | |
309 | ||
1dbcd68c WT |
310 | /* BND register? */ |
311 | ||
312 | int | |
313 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
314 | { | |
315 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
316 | int bnd0_regnum = tdep->bnd0_regnum; | |
317 | ||
318 | if (bnd0_regnum < 0) | |
319 | return 0; | |
320 | ||
321 | regnum -= bnd0_regnum; | |
322 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
323 | } | |
324 | ||
5716833c | 325 | /* SSE register? */ |
23a34459 | 326 | |
c131fcee L |
327 | int |
328 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 329 | { |
5716833c | 330 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 331 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 332 | |
c131fcee | 333 | if (num_xmm_regs == 0) |
5716833c MK |
334 | return 0; |
335 | ||
c131fcee L |
336 | regnum -= I387_XMM0_REGNUM (tdep); |
337 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
338 | } |
339 | ||
01f9f808 MS |
340 | /* XMM_512 register? */ |
341 | ||
342 | int | |
343 | i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
344 | { | |
345 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
346 | int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); | |
347 | ||
348 | if (num_xmm_avx512_regs == 0) | |
349 | return 0; | |
350 | ||
351 | regnum -= I387_XMM16_REGNUM (tdep); | |
352 | return regnum >= 0 && regnum < num_xmm_avx512_regs; | |
353 | } | |
354 | ||
5716833c MK |
355 | static int |
356 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 357 | { |
5716833c MK |
358 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
359 | ||
20a6ec49 | 360 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
361 | return 0; |
362 | ||
20a6ec49 | 363 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
364 | } |
365 | ||
5716833c | 366 | /* FP register? */ |
23a34459 AC |
367 | |
368 | int | |
20a6ec49 | 369 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 370 | { |
20a6ec49 MD |
371 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
372 | ||
373 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
374 | return 0; |
375 | ||
20a6ec49 MD |
376 | return (I387_ST0_REGNUM (tdep) <= regnum |
377 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
378 | } |
379 | ||
380 | int | |
20a6ec49 | 381 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 382 | { |
20a6ec49 MD |
383 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
384 | ||
385 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
386 | return 0; |
387 | ||
20a6ec49 MD |
388 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
389 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
390 | } |
391 | ||
1dbcd68c WT |
392 | /* BNDr (raw) register? */ |
393 | ||
394 | static int | |
395 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
396 | { | |
397 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
398 | ||
399 | if (I387_BND0R_REGNUM (tdep) < 0) | |
400 | return 0; | |
401 | ||
402 | regnum -= tdep->bnd0r_regnum; | |
403 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
404 | } | |
405 | ||
406 | /* BND control register? */ | |
407 | ||
408 | static int | |
409 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
410 | { | |
411 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
412 | ||
413 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
414 | return 0; | |
415 | ||
416 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
417 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
418 | } | |
419 | ||
51547df6 MS |
420 | /* PKRU register? */ |
421 | ||
422 | bool | |
423 | i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum) | |
424 | { | |
425 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
426 | int pkru_regnum = tdep->pkru_regnum; | |
427 | ||
428 | if (pkru_regnum < 0) | |
429 | return false; | |
430 | ||
431 | regnum -= pkru_regnum; | |
432 | return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS; | |
433 | } | |
434 | ||
c131fcee L |
435 | /* Return the name of register REGNUM, or the empty string if it is |
436 | an anonymous register. */ | |
437 | ||
438 | static const char * | |
439 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
440 | { | |
441 | /* Hide the upper YMM registers. */ | |
442 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
443 | return ""; | |
444 | ||
01f9f808 MS |
445 | /* Hide the upper YMM16-31 registers. */ |
446 | if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) | |
447 | return ""; | |
448 | ||
449 | /* Hide the upper ZMM registers. */ | |
450 | if (i386_zmmh_regnum_p (gdbarch, regnum)) | |
451 | return ""; | |
452 | ||
c131fcee L |
453 | return tdesc_register_name (gdbarch, regnum); |
454 | } | |
455 | ||
30b0e2d8 | 456 | /* Return the name of register REGNUM. */ |
fc633446 | 457 | |
1ba53b71 | 458 | const char * |
90884b2b | 459 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 460 | { |
1ba53b71 | 461 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dbcd68c WT |
462 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
463 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
464 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
465 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
466 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
467 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
468 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
469 | return i386_zmm_names[regnum - tdep->zmm0_regnum]; | |
1ba53b71 L |
470 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
471 | return i386_byte_names[regnum - tdep->al_regnum]; | |
472 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
473 | return i386_word_names[regnum - tdep->ax_regnum]; | |
474 | ||
475 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
476 | } |
477 | ||
c4fc7f1b | 478 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
479 | number used by GDB. */ |
480 | ||
8201327c | 481 | static int |
d3f73121 | 482 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 483 | { |
20a6ec49 MD |
484 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
485 | ||
c4fc7f1b MK |
486 | /* This implements what GCC calls the "default" register map |
487 | (dbx_register_map[]). */ | |
488 | ||
85540d8c MK |
489 | if (reg >= 0 && reg <= 7) |
490 | { | |
9872ad24 JB |
491 | /* General-purpose registers. The debug info calls %ebp |
492 | register 4, and %esp register 5. */ | |
493 | if (reg == 4) | |
494 | return 5; | |
495 | else if (reg == 5) | |
496 | return 4; | |
497 | else return reg; | |
85540d8c MK |
498 | } |
499 | else if (reg >= 12 && reg <= 19) | |
500 | { | |
501 | /* Floating-point registers. */ | |
20a6ec49 | 502 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
503 | } |
504 | else if (reg >= 21 && reg <= 28) | |
505 | { | |
506 | /* SSE registers. */ | |
c131fcee L |
507 | int ymm0_regnum = tdep->ymm0_regnum; |
508 | ||
509 | if (ymm0_regnum >= 0 | |
510 | && i386_xmm_regnum_p (gdbarch, reg)) | |
511 | return reg - 21 + ymm0_regnum; | |
512 | else | |
513 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
514 | } |
515 | else if (reg >= 29 && reg <= 36) | |
516 | { | |
517 | /* MMX registers. */ | |
20a6ec49 | 518 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
519 | } |
520 | ||
521 | /* This will hopefully provoke a warning. */ | |
f6efe3f8 | 522 | return gdbarch_num_cooked_regs (gdbarch); |
85540d8c MK |
523 | } |
524 | ||
0fde2c53 | 525 | /* Convert SVR4 DWARF register number REG to the appropriate register number |
c4fc7f1b | 526 | used by GDB. */ |
85540d8c | 527 | |
8201327c | 528 | static int |
0fde2c53 | 529 | i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 530 | { |
20a6ec49 MD |
531 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
532 | ||
c4fc7f1b MK |
533 | /* This implements the GCC register map that tries to be compatible |
534 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
535 | ||
536 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
537 | numbers the floating point registers differently. */ |
538 | if (reg >= 0 && reg <= 9) | |
539 | { | |
acd5c798 | 540 | /* General-purpose registers. */ |
85540d8c MK |
541 | return reg; |
542 | } | |
543 | else if (reg >= 11 && reg <= 18) | |
544 | { | |
545 | /* Floating-point registers. */ | |
20a6ec49 | 546 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 547 | } |
c6f4c129 | 548 | else if (reg >= 21 && reg <= 36) |
85540d8c | 549 | { |
c4fc7f1b | 550 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 551 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
552 | } |
553 | ||
c6f4c129 JB |
554 | switch (reg) |
555 | { | |
20a6ec49 MD |
556 | case 37: return I387_FCTRL_REGNUM (tdep); |
557 | case 38: return I387_FSTAT_REGNUM (tdep); | |
558 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
559 | case 40: return I386_ES_REGNUM; |
560 | case 41: return I386_CS_REGNUM; | |
561 | case 42: return I386_SS_REGNUM; | |
562 | case 43: return I386_DS_REGNUM; | |
563 | case 44: return I386_FS_REGNUM; | |
564 | case 45: return I386_GS_REGNUM; | |
565 | } | |
566 | ||
0fde2c53 DE |
567 | return -1; |
568 | } | |
569 | ||
570 | /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return | |
571 | num_regs + num_pseudo_regs for other debug formats. */ | |
572 | ||
8f10c932 | 573 | int |
0fde2c53 DE |
574 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
575 | { | |
576 | int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg); | |
577 | ||
578 | if (regnum == -1) | |
f6efe3f8 | 579 | return gdbarch_num_cooked_regs (gdbarch); |
0fde2c53 | 580 | return regnum; |
85540d8c | 581 | } |
5716833c | 582 | |
fc338970 | 583 | \f |
917317f4 | 584 | |
fc338970 MK |
585 | /* This is the variable that is set with "set disassembly-flavor", and |
586 | its legitimate values. */ | |
53904c9e AC |
587 | static const char att_flavor[] = "att"; |
588 | static const char intel_flavor[] = "intel"; | |
40478521 | 589 | static const char *const valid_flavors[] = |
c5aa993b | 590 | { |
c906108c SS |
591 | att_flavor, |
592 | intel_flavor, | |
593 | NULL | |
594 | }; | |
53904c9e | 595 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 596 | \f |
c906108c | 597 | |
acd5c798 MK |
598 | /* Use the program counter to determine the contents and size of a |
599 | breakpoint instruction. Return a pointer to a string of bytes that | |
600 | encode a breakpoint instruction, store the length of the string in | |
601 | *LEN and optionally adjust *PC to point to the correct memory | |
602 | location for inserting the breakpoint. | |
c906108c | 603 | |
acd5c798 MK |
604 | On the i386 we have a single breakpoint that fits in a single byte |
605 | and can be inserted anywhere. | |
c906108c | 606 | |
acd5c798 | 607 | This function is 64-bit safe. */ |
63c0089f | 608 | |
04180708 YQ |
609 | constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */ |
610 | ||
611 | typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint; | |
63c0089f | 612 | |
237fc4c9 PA |
613 | \f |
614 | /* Displaced instruction handling. */ | |
615 | ||
1903f0e6 DE |
616 | /* Skip the legacy instruction prefixes in INSN. |
617 | Not all prefixes are valid for any particular insn | |
618 | but we needn't care, the insn will fault if it's invalid. | |
619 | The result is a pointer to the first opcode byte, | |
620 | or NULL if we run off the end of the buffer. */ | |
621 | ||
622 | static gdb_byte * | |
623 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
624 | { | |
625 | gdb_byte *end = insn + max_len; | |
626 | ||
627 | while (insn < end) | |
628 | { | |
629 | switch (*insn) | |
630 | { | |
631 | case DATA_PREFIX_OPCODE: | |
632 | case ADDR_PREFIX_OPCODE: | |
633 | case CS_PREFIX_OPCODE: | |
634 | case DS_PREFIX_OPCODE: | |
635 | case ES_PREFIX_OPCODE: | |
636 | case FS_PREFIX_OPCODE: | |
637 | case GS_PREFIX_OPCODE: | |
638 | case SS_PREFIX_OPCODE: | |
639 | case LOCK_PREFIX_OPCODE: | |
640 | case REPE_PREFIX_OPCODE: | |
641 | case REPNE_PREFIX_OPCODE: | |
642 | ++insn; | |
643 | continue; | |
644 | default: | |
645 | return insn; | |
646 | } | |
647 | } | |
648 | ||
649 | return NULL; | |
650 | } | |
237fc4c9 PA |
651 | |
652 | static int | |
1903f0e6 | 653 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 654 | { |
1777feb0 | 655 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
656 | if (insn[0] == 0xea) |
657 | return 1; | |
658 | ||
659 | if (insn[0] == 0xff) | |
660 | { | |
1777feb0 | 661 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
662 | if ((insn[1] & 0x38) == 0x20) |
663 | return 1; | |
664 | ||
1777feb0 | 665 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
666 | if ((insn[1] & 0x38) == 0x28) |
667 | return 1; | |
668 | } | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
c2170eef MM |
673 | /* Return non-zero if INSN is a jump, zero otherwise. */ |
674 | ||
675 | static int | |
676 | i386_jmp_p (const gdb_byte *insn) | |
677 | { | |
678 | /* jump short, relative. */ | |
679 | if (insn[0] == 0xeb) | |
680 | return 1; | |
681 | ||
682 | /* jump near, relative. */ | |
683 | if (insn[0] == 0xe9) | |
684 | return 1; | |
685 | ||
686 | return i386_absolute_jmp_p (insn); | |
687 | } | |
688 | ||
237fc4c9 | 689 | static int |
1903f0e6 | 690 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 691 | { |
1777feb0 | 692 | /* call far, absolute. */ |
237fc4c9 PA |
693 | if (insn[0] == 0x9a) |
694 | return 1; | |
695 | ||
696 | if (insn[0] == 0xff) | |
697 | { | |
1777feb0 | 698 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
699 | if ((insn[1] & 0x38) == 0x10) |
700 | return 1; | |
701 | ||
1777feb0 | 702 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
703 | if ((insn[1] & 0x38) == 0x18) |
704 | return 1; | |
705 | } | |
706 | ||
707 | return 0; | |
708 | } | |
709 | ||
710 | static int | |
1903f0e6 | 711 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
712 | { |
713 | switch (insn[0]) | |
714 | { | |
1777feb0 | 715 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 716 | case 0xc3: /* ret near */ |
1777feb0 | 717 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
718 | case 0xcb: /* ret far */ |
719 | case 0xcf: /* iret */ | |
720 | return 1; | |
721 | ||
722 | default: | |
723 | return 0; | |
724 | } | |
725 | } | |
726 | ||
727 | static int | |
1903f0e6 | 728 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
729 | { |
730 | if (i386_absolute_call_p (insn)) | |
731 | return 1; | |
732 | ||
1777feb0 | 733 | /* call near, relative. */ |
237fc4c9 PA |
734 | if (insn[0] == 0xe8) |
735 | return 1; | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
237fc4c9 PA |
740 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
741 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 742 | |
237fc4c9 | 743 | static int |
b55078be | 744 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 745 | { |
9a7f938f JK |
746 | /* Is it 'int $0x80'? */ |
747 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
748 | /* Or is it 'sysenter'? */ | |
749 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
750 | /* Or is it 'syscall'? */ | |
751 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
752 | { |
753 | *lengthp = 2; | |
754 | return 1; | |
755 | } | |
756 | ||
757 | return 0; | |
758 | } | |
759 | ||
c2170eef MM |
760 | /* The gdbarch insn_is_call method. */ |
761 | ||
762 | static int | |
763 | i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
764 | { | |
765 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
766 | ||
767 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
768 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
769 | ||
770 | return i386_call_p (insn); | |
771 | } | |
772 | ||
773 | /* The gdbarch insn_is_ret method. */ | |
774 | ||
775 | static int | |
776 | i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
777 | { | |
778 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
779 | ||
780 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
781 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
782 | ||
783 | return i386_ret_p (insn); | |
784 | } | |
785 | ||
786 | /* The gdbarch insn_is_jump method. */ | |
787 | ||
788 | static int | |
789 | i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
790 | { | |
791 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
792 | ||
793 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
794 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
795 | ||
796 | return i386_jmp_p (insn); | |
797 | } | |
798 | ||
c2508e90 | 799 | /* Some kernels may run one past a syscall insn, so we have to cope. */ |
b55078be | 800 | |
fdb61c6c | 801 | displaced_step_closure_up |
b55078be DE |
802 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, |
803 | CORE_ADDR from, CORE_ADDR to, | |
804 | struct regcache *regs) | |
805 | { | |
806 | size_t len = gdbarch_max_insn_length (gdbarch); | |
e8217e61 SM |
807 | std::unique_ptr<i386_displaced_step_closure> closure |
808 | (new i386_displaced_step_closure (len)); | |
cfba9872 | 809 | gdb_byte *buf = closure->buf.data (); |
b55078be DE |
810 | |
811 | read_memory (from, buf, len); | |
812 | ||
813 | /* GDB may get control back after the insn after the syscall. | |
814 | Presumably this is a kernel bug. | |
815 | If this is a syscall, make sure there's a nop afterwards. */ | |
816 | { | |
817 | int syscall_length; | |
818 | gdb_byte *insn; | |
819 | ||
820 | insn = i386_skip_prefixes (buf, len); | |
821 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
822 | insn[syscall_length] = NOP_OPCODE; | |
823 | } | |
824 | ||
825 | write_memory (to, buf, len); | |
826 | ||
827 | if (debug_displaced) | |
828 | { | |
829 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
830 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
831 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
832 | } | |
833 | ||
6d0cf446 BE |
834 | /* This is a work around for a problem with g++ 4.8. */ |
835 | return displaced_step_closure_up (closure.release ()); | |
b55078be DE |
836 | } |
837 | ||
237fc4c9 PA |
838 | /* Fix up the state of registers and memory after having single-stepped |
839 | a displaced instruction. */ | |
1903f0e6 | 840 | |
237fc4c9 PA |
841 | void |
842 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
cfba9872 | 843 | struct displaced_step_closure *closure_, |
237fc4c9 PA |
844 | CORE_ADDR from, CORE_ADDR to, |
845 | struct regcache *regs) | |
846 | { | |
e17a4113 UW |
847 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
848 | ||
237fc4c9 PA |
849 | /* The offset we applied to the instruction's address. |
850 | This could well be negative (when viewed as a signed 32-bit | |
851 | value), but ULONGEST won't reflect that, so take care when | |
852 | applying it. */ | |
853 | ULONGEST insn_offset = to - from; | |
854 | ||
cfba9872 SM |
855 | i386_displaced_step_closure *closure |
856 | = (i386_displaced_step_closure *) closure_; | |
857 | gdb_byte *insn = closure->buf.data (); | |
1903f0e6 DE |
858 | /* The start of the insn, needed in case we see some prefixes. */ |
859 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
860 | |
861 | if (debug_displaced) | |
862 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 863 | "displaced: fixup (%s, %s), " |
237fc4c9 | 864 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
865 | paddress (gdbarch, from), paddress (gdbarch, to), |
866 | insn[0], insn[1]); | |
237fc4c9 PA |
867 | |
868 | /* The list of issues to contend with here is taken from | |
869 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
870 | Yay for Free Software! */ | |
871 | ||
872 | /* Relocate the %eip, if necessary. */ | |
873 | ||
1903f0e6 DE |
874 | /* The instruction recognizers we use assume any leading prefixes |
875 | have been skipped. */ | |
876 | { | |
877 | /* This is the size of the buffer in closure. */ | |
878 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
879 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
880 | /* If there are too many prefixes, just ignore the insn. | |
881 | It will fault when run. */ | |
882 | if (opcode != NULL) | |
883 | insn = opcode; | |
884 | } | |
885 | ||
237fc4c9 PA |
886 | /* Except in the case of absolute or indirect jump or call |
887 | instructions, or a return instruction, the new eip is relative to | |
888 | the displaced instruction; make it relative. Well, signal | |
889 | handler returns don't need relocation either, but we use the | |
890 | value of %eip to recognize those; see below. */ | |
891 | if (! i386_absolute_jmp_p (insn) | |
892 | && ! i386_absolute_call_p (insn) | |
893 | && ! i386_ret_p (insn)) | |
894 | { | |
895 | ULONGEST orig_eip; | |
b55078be | 896 | int insn_len; |
237fc4c9 PA |
897 | |
898 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
899 | ||
900 | /* A signal trampoline system call changes the %eip, resuming | |
901 | execution of the main program after the signal handler has | |
902 | returned. That makes them like 'return' instructions; we | |
903 | shouldn't relocate %eip. | |
904 | ||
905 | But most system calls don't, and we do need to relocate %eip. | |
906 | ||
907 | Our heuristic for distinguishing these cases: if stepping | |
908 | over the system call instruction left control directly after | |
909 | the instruction, the we relocate --- control almost certainly | |
910 | doesn't belong in the displaced copy. Otherwise, we assume | |
911 | the instruction has put control where it belongs, and leave | |
912 | it unrelocated. Goodness help us if there are PC-relative | |
913 | system calls. */ | |
914 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
915 | && orig_eip != to + (insn - insn_start) + insn_len |
916 | /* GDB can get control back after the insn after the syscall. | |
917 | Presumably this is a kernel bug. | |
918 | i386_displaced_step_copy_insn ensures its a nop, | |
919 | we add one to the length for it. */ | |
920 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
921 | { |
922 | if (debug_displaced) | |
923 | fprintf_unfiltered (gdb_stdlog, | |
924 | "displaced: syscall changed %%eip; " | |
925 | "not relocating\n"); | |
926 | } | |
927 | else | |
928 | { | |
929 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
930 | ||
1903f0e6 DE |
931 | /* If we just stepped over a breakpoint insn, we don't backup |
932 | the pc on purpose; this is to match behaviour without | |
933 | stepping. */ | |
237fc4c9 PA |
934 | |
935 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
936 | ||
937 | if (debug_displaced) | |
938 | fprintf_unfiltered (gdb_stdlog, | |
939 | "displaced: " | |
5af949e3 UW |
940 | "relocated %%eip from %s to %s\n", |
941 | paddress (gdbarch, orig_eip), | |
942 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
943 | } |
944 | } | |
945 | ||
946 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
947 | pushed value, and should be cleared. We'll leave this for later, | |
948 | since GDB already messes up the TF flag when stepping over a | |
949 | pushfl. */ | |
950 | ||
951 | /* If the instruction was a call, the return address now atop the | |
952 | stack is the address following the copied instruction. We need | |
953 | to make it the address following the original instruction. */ | |
954 | if (i386_call_p (insn)) | |
955 | { | |
956 | ULONGEST esp; | |
957 | ULONGEST retaddr; | |
958 | const ULONGEST retaddr_len = 4; | |
959 | ||
960 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 961 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 962 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 963 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
964 | |
965 | if (debug_displaced) | |
966 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
967 | "displaced: relocated return addr at %s to %s\n", |
968 | paddress (gdbarch, esp), | |
969 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
970 | } |
971 | } | |
dde08ee1 PA |
972 | |
973 | static void | |
974 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
975 | { | |
976 | target_write_memory (*to, buf, len); | |
977 | *to += len; | |
978 | } | |
979 | ||
980 | static void | |
981 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
982 | CORE_ADDR *to, CORE_ADDR oldloc) | |
983 | { | |
984 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
985 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
986 | int offset = 0, rel32, newrel; | |
987 | int insn_length; | |
988 | gdb_byte *insn = buf; | |
989 | ||
990 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
991 | ||
992 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
993 | I386_MAX_INSN_LEN, oldloc); | |
994 | ||
995 | /* Get past the prefixes. */ | |
996 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
997 | ||
998 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
999 | the address pushed being the location where the original call in | |
1000 | the user program would return to. */ | |
1001 | if (insn[0] == 0xe8) | |
1002 | { | |
1003 | gdb_byte push_buf[16]; | |
1004 | unsigned int ret_addr; | |
1005 | ||
1006 | /* Where "ret" in the original code will return to. */ | |
1007 | ret_addr = oldloc + insn_length; | |
1777feb0 | 1008 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 1009 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
1010 | /* Push the push. */ |
1011 | append_insns (to, 5, push_buf); | |
1012 | ||
1013 | /* Convert the relative call to a relative jump. */ | |
1014 | insn[0] = 0xe9; | |
1015 | ||
1016 | /* Adjust the destination offset. */ | |
1017 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
1018 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
1019 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
1020 | ||
1021 | if (debug_displaced) | |
1022 | fprintf_unfiltered (gdb_stdlog, | |
1023 | "Adjusted insn rel32=%s at %s to" | |
1024 | " rel32=%s at %s\n", | |
1025 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1026 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1027 | |
1028 | /* Write the adjusted jump into its displaced location. */ | |
1029 | append_insns (to, 5, insn); | |
1030 | return; | |
1031 | } | |
1032 | ||
1033 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
1034 | handled above. */ | |
1035 | if (insn[0] == 0xe9) | |
1036 | offset = 1; | |
1037 | /* Adjust conditional jumps. */ | |
1038 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1039 | offset = 2; | |
1040 | ||
1041 | if (offset) | |
1042 | { | |
1043 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1044 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1045 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
1046 | if (debug_displaced) |
1047 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
1048 | "Adjusted insn rel32=%s at %s to" |
1049 | " rel32=%s at %s\n", | |
dde08ee1 PA |
1050 | hex_string (rel32), paddress (gdbarch, oldloc), |
1051 | hex_string (newrel), paddress (gdbarch, *to)); | |
1052 | } | |
1053 | ||
1054 | /* Write the adjusted instructions into their displaced | |
1055 | location. */ | |
1056 | append_insns (to, insn_length, buf); | |
1057 | } | |
1058 | ||
fc338970 | 1059 | \f |
acd5c798 MK |
1060 | #ifdef I386_REGNO_TO_SYMMETRY |
1061 | #error "The Sequent Symmetry is no longer supported." | |
1062 | #endif | |
c906108c | 1063 | |
acd5c798 MK |
1064 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
1065 | and %esp "belong" to the calling function. Therefore these | |
1066 | registers should be saved if they're going to be modified. */ | |
c906108c | 1067 | |
acd5c798 MK |
1068 | /* The maximum number of saved registers. This should include all |
1069 | registers mentioned above, and %eip. */ | |
a3386186 | 1070 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
1071 | |
1072 | struct i386_frame_cache | |
c906108c | 1073 | { |
acd5c798 MK |
1074 | /* Base address. */ |
1075 | CORE_ADDR base; | |
8fbca658 | 1076 | int base_p; |
772562f8 | 1077 | LONGEST sp_offset; |
acd5c798 MK |
1078 | CORE_ADDR pc; |
1079 | ||
fd13a04a AC |
1080 | /* Saved registers. */ |
1081 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 1082 | CORE_ADDR saved_sp; |
e0c62198 | 1083 | int saved_sp_reg; |
acd5c798 MK |
1084 | int pc_in_eax; |
1085 | ||
1086 | /* Stack space reserved for local variables. */ | |
1087 | long locals; | |
1088 | }; | |
1089 | ||
1090 | /* Allocate and initialize a frame cache. */ | |
1091 | ||
1092 | static struct i386_frame_cache * | |
fd13a04a | 1093 | i386_alloc_frame_cache (void) |
acd5c798 MK |
1094 | { |
1095 | struct i386_frame_cache *cache; | |
1096 | int i; | |
1097 | ||
1098 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
1099 | ||
1100 | /* Base address. */ | |
8fbca658 | 1101 | cache->base_p = 0; |
acd5c798 MK |
1102 | cache->base = 0; |
1103 | cache->sp_offset = -4; | |
1104 | cache->pc = 0; | |
1105 | ||
fd13a04a AC |
1106 | /* Saved registers. We initialize these to -1 since zero is a valid |
1107 | offset (that's where %ebp is supposed to be stored). */ | |
1108 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
1109 | cache->saved_regs[i] = -1; | |
acd5c798 | 1110 | cache->saved_sp = 0; |
e0c62198 | 1111 | cache->saved_sp_reg = -1; |
acd5c798 MK |
1112 | cache->pc_in_eax = 0; |
1113 | ||
1114 | /* Frameless until proven otherwise. */ | |
1115 | cache->locals = -1; | |
1116 | ||
1117 | return cache; | |
1118 | } | |
c906108c | 1119 | |
acd5c798 MK |
1120 | /* If the instruction at PC is a jump, return the address of its |
1121 | target. Otherwise, return PC. */ | |
c906108c | 1122 | |
acd5c798 | 1123 | static CORE_ADDR |
e17a4113 | 1124 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 1125 | { |
e17a4113 | 1126 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1127 | gdb_byte op; |
acd5c798 MK |
1128 | long delta = 0; |
1129 | int data16 = 0; | |
c906108c | 1130 | |
0865b04a | 1131 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1132 | return pc; |
1133 | ||
acd5c798 | 1134 | if (op == 0x66) |
c906108c | 1135 | { |
c906108c | 1136 | data16 = 1; |
0865b04a YQ |
1137 | |
1138 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
1139 | } |
1140 | ||
acd5c798 | 1141 | switch (op) |
c906108c SS |
1142 | { |
1143 | case 0xe9: | |
fc338970 | 1144 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
1145 | if (data16) |
1146 | { | |
e17a4113 | 1147 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 1148 | |
fc338970 MK |
1149 | /* Include the size of the jmp instruction (including the |
1150 | 0x66 prefix). */ | |
acd5c798 | 1151 | delta += 4; |
c906108c SS |
1152 | } |
1153 | else | |
1154 | { | |
e17a4113 | 1155 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 1156 | |
acd5c798 MK |
1157 | /* Include the size of the jmp instruction. */ |
1158 | delta += 5; | |
c906108c SS |
1159 | } |
1160 | break; | |
1161 | case 0xeb: | |
fc338970 | 1162 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 1163 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 1164 | |
acd5c798 | 1165 | delta += data16 + 2; |
c906108c SS |
1166 | break; |
1167 | } | |
c906108c | 1168 | |
acd5c798 MK |
1169 | return pc + delta; |
1170 | } | |
fc338970 | 1171 | |
acd5c798 MK |
1172 | /* Check whether PC points at a prologue for a function returning a |
1173 | structure or union. If so, it updates CACHE and returns the | |
1174 | address of the first instruction after the code sequence that | |
1175 | removes the "hidden" argument from the stack or CURRENT_PC, | |
1176 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 1177 | |
acd5c798 MK |
1178 | static CORE_ADDR |
1179 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
1180 | struct i386_frame_cache *cache) | |
c906108c | 1181 | { |
acd5c798 MK |
1182 | /* Functions that return a structure or union start with: |
1183 | ||
1184 | popl %eax 0x58 | |
1185 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
1186 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
1187 | ||
1188 | (the System V compiler puts out the second `xchg' instruction, | |
1189 | and the assembler doesn't try to optimize it, so the 'sib' form | |
1190 | gets generated). This sequence is used to get the address of the | |
1191 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
1192 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
1193 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
1194 | gdb_byte buf[4]; | |
1195 | gdb_byte op; | |
c906108c | 1196 | |
acd5c798 MK |
1197 | if (current_pc <= pc) |
1198 | return pc; | |
1199 | ||
0865b04a | 1200 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1201 | return pc; |
c906108c | 1202 | |
acd5c798 MK |
1203 | if (op != 0x58) /* popl %eax */ |
1204 | return pc; | |
c906108c | 1205 | |
0865b04a | 1206 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1207 | return pc; |
1208 | ||
acd5c798 MK |
1209 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1210 | return pc; | |
c906108c | 1211 | |
acd5c798 | 1212 | if (current_pc == pc) |
c906108c | 1213 | { |
acd5c798 MK |
1214 | cache->sp_offset += 4; |
1215 | return current_pc; | |
c906108c SS |
1216 | } |
1217 | ||
acd5c798 | 1218 | if (current_pc == pc + 1) |
c906108c | 1219 | { |
acd5c798 MK |
1220 | cache->pc_in_eax = 1; |
1221 | return current_pc; | |
1222 | } | |
1223 | ||
1224 | if (buf[1] == proto1[1]) | |
1225 | return pc + 4; | |
1226 | else | |
1227 | return pc + 5; | |
1228 | } | |
1229 | ||
1230 | static CORE_ADDR | |
1231 | i386_skip_probe (CORE_ADDR pc) | |
1232 | { | |
1233 | /* A function may start with | |
fc338970 | 1234 | |
acd5c798 MK |
1235 | pushl constant |
1236 | call _probe | |
1237 | addl $4, %esp | |
fc338970 | 1238 | |
acd5c798 MK |
1239 | followed by |
1240 | ||
1241 | pushl %ebp | |
fc338970 | 1242 | |
acd5c798 | 1243 | etc. */ |
63c0089f MK |
1244 | gdb_byte buf[8]; |
1245 | gdb_byte op; | |
fc338970 | 1246 | |
0865b04a | 1247 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1248 | return pc; |
acd5c798 MK |
1249 | |
1250 | if (op == 0x68 || op == 0x6a) | |
1251 | { | |
1252 | int delta; | |
c906108c | 1253 | |
acd5c798 MK |
1254 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1255 | four-byte operand, depending on the opcode. */ | |
c906108c | 1256 | if (op == 0x68) |
acd5c798 | 1257 | delta = 5; |
c906108c | 1258 | else |
acd5c798 | 1259 | delta = 2; |
c906108c | 1260 | |
acd5c798 MK |
1261 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1262 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1263 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1264 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1265 | pc += delta + sizeof (buf); |
c906108c SS |
1266 | } |
1267 | ||
acd5c798 MK |
1268 | return pc; |
1269 | } | |
1270 | ||
92dd43fa MK |
1271 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1272 | stack pointer. Check whether PC points to such code, and update | |
1273 | CACHE accordingly. Return the first instruction after the code | |
1274 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1275 | recognize the code, return PC. */ | |
1276 | ||
1277 | static CORE_ADDR | |
1278 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1279 | struct i386_frame_cache *cache) | |
1280 | { | |
e0c62198 L |
1281 | /* There are 2 code sequences to re-align stack before the frame |
1282 | gets set up: | |
1283 | ||
1284 | 1. Use a caller-saved saved register: | |
1285 | ||
1286 | leal 4(%esp), %reg | |
1287 | andl $-XXX, %esp | |
1288 | pushl -4(%reg) | |
1289 | ||
1290 | 2. Use a callee-saved saved register: | |
1291 | ||
1292 | pushl %reg | |
1293 | leal 8(%esp), %reg | |
1294 | andl $-XXX, %esp | |
1295 | pushl -4(%reg) | |
1296 | ||
1297 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1298 | ||
1299 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1300 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1301 | */ | |
1302 | ||
1303 | gdb_byte buf[14]; | |
1304 | int reg; | |
1305 | int offset, offset_and; | |
1306 | static int regnums[8] = { | |
1307 | I386_EAX_REGNUM, /* %eax */ | |
1308 | I386_ECX_REGNUM, /* %ecx */ | |
1309 | I386_EDX_REGNUM, /* %edx */ | |
1310 | I386_EBX_REGNUM, /* %ebx */ | |
1311 | I386_ESP_REGNUM, /* %esp */ | |
1312 | I386_EBP_REGNUM, /* %ebp */ | |
1313 | I386_ESI_REGNUM, /* %esi */ | |
1314 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1315 | }; |
92dd43fa | 1316 | |
0865b04a | 1317 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1318 | return pc; |
1319 | ||
1320 | /* Check caller-saved saved register. The first instruction has | |
1321 | to be "leal 4(%esp), %reg". */ | |
1322 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1323 | { | |
1324 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1325 | if ((buf[1] & 0xc7) != 0x44) | |
1326 | return pc; | |
1327 | ||
1328 | /* REG has register number. */ | |
1329 | reg = (buf[1] >> 3) & 7; | |
1330 | offset = 4; | |
1331 | } | |
1332 | else | |
1333 | { | |
1334 | /* Check callee-saved saved register. The first instruction | |
1335 | has to be "pushl %reg". */ | |
1336 | if ((buf[0] & 0xf8) != 0x50) | |
1337 | return pc; | |
1338 | ||
1339 | /* Get register. */ | |
1340 | reg = buf[0] & 0x7; | |
1341 | ||
1342 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1343 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1344 | return pc; | |
1345 | ||
1346 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1347 | if ((buf[2] & 0xc7) != 0x44) | |
1348 | return pc; | |
1349 | ||
1350 | /* REG has register number. Registers in pushl and leal have to | |
1351 | be the same. */ | |
1352 | if (reg != ((buf[2] >> 3) & 7)) | |
1353 | return pc; | |
1354 | ||
1355 | offset = 5; | |
1356 | } | |
1357 | ||
1358 | /* Rigister can't be %esp nor %ebp. */ | |
1359 | if (reg == 4 || reg == 5) | |
1360 | return pc; | |
1361 | ||
1362 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1363 | if (buf[offset + 1] != 0xe4 | |
1364 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1365 | return pc; | |
1366 | ||
1367 | offset_and = offset; | |
1368 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1369 | ||
1370 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1371 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1372 | if (buf[offset] != 0xff | |
1373 | || buf[offset + 2] != 0xfc | |
1374 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1375 | return pc; | |
1376 | ||
1377 | /* R/M has register. Registers in leal and pushl have to be the | |
1378 | same. */ | |
1379 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1380 | return pc; |
1381 | ||
e0c62198 L |
1382 | if (current_pc > pc + offset_and) |
1383 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1384 | |
325fac50 | 1385 | return std::min (pc + offset + 3, current_pc); |
92dd43fa MK |
1386 | } |
1387 | ||
37bdc87e | 1388 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1389 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1390 | |
1391 | /* Instruction description. */ | |
1392 | struct i386_insn | |
1393 | { | |
1394 | size_t len; | |
237fc4c9 PA |
1395 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1396 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1397 | }; |
1398 | ||
a3fcb948 | 1399 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1400 | |
a3fcb948 JG |
1401 | static int |
1402 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1403 | { |
63c0089f | 1404 | gdb_byte op; |
37bdc87e | 1405 | |
0865b04a | 1406 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1407 | return 0; |
37bdc87e | 1408 | |
a3fcb948 | 1409 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1410 | { |
a3fcb948 JG |
1411 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1412 | int insn_matched = 1; | |
1413 | size_t i; | |
37bdc87e | 1414 | |
a3fcb948 JG |
1415 | gdb_assert (pattern.len > 1); |
1416 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1417 | |
0865b04a | 1418 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1419 | return 0; |
613e8135 | 1420 | |
a3fcb948 JG |
1421 | for (i = 1; i < pattern.len; i++) |
1422 | { | |
1423 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1424 | insn_matched = 0; | |
37bdc87e | 1425 | } |
a3fcb948 JG |
1426 | return insn_matched; |
1427 | } | |
1428 | return 0; | |
1429 | } | |
1430 | ||
1431 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1432 | the first instruction description that matches. Otherwise, return | |
1433 | NULL. */ | |
1434 | ||
1435 | static struct i386_insn * | |
1436 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1437 | { | |
1438 | struct i386_insn *pattern; | |
1439 | ||
1440 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1441 | { | |
1442 | if (i386_match_pattern (pc, *pattern)) | |
1443 | return pattern; | |
37bdc87e MK |
1444 | } |
1445 | ||
1446 | return NULL; | |
1447 | } | |
1448 | ||
a3fcb948 JG |
1449 | /* Return whether PC points inside a sequence of instructions that |
1450 | matches INSN_PATTERNS. */ | |
1451 | ||
1452 | static int | |
1453 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1454 | { | |
1455 | CORE_ADDR current_pc; | |
1456 | int ix, i; | |
a3fcb948 JG |
1457 | struct i386_insn *insn; |
1458 | ||
1459 | insn = i386_match_insn (pc, insn_patterns); | |
1460 | if (insn == NULL) | |
1461 | return 0; | |
1462 | ||
8bbdd3f4 | 1463 | current_pc = pc; |
a3fcb948 JG |
1464 | ix = insn - insn_patterns; |
1465 | for (i = ix - 1; i >= 0; i--) | |
1466 | { | |
8bbdd3f4 MK |
1467 | current_pc -= insn_patterns[i].len; |
1468 | ||
a3fcb948 JG |
1469 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1470 | return 0; | |
a3fcb948 JG |
1471 | } |
1472 | ||
1473 | current_pc = pc + insn->len; | |
1474 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1475 | { | |
1476 | if (!i386_match_pattern (current_pc, *insn)) | |
1477 | return 0; | |
1478 | ||
1479 | current_pc += insn->len; | |
1480 | } | |
1481 | ||
1482 | return 1; | |
1483 | } | |
1484 | ||
37bdc87e MK |
1485 | /* Some special instructions that might be migrated by GCC into the |
1486 | part of the prologue that sets up the new stack frame. Because the | |
1487 | stack frame hasn't been setup yet, no registers have been saved | |
1488 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1489 | touched. */ | |
1490 | ||
1491 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1492 | { | |
1777feb0 | 1493 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1494 | |
1495 | ??? Should we handle 16-bit operand-sizes here? */ | |
1496 | ||
1497 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1498 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1499 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1500 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1501 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1502 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1503 | { 5, { 0xb8 }, { 0xfe } }, | |
1504 | /* `movl imm32, %edx' */ | |
1505 | { 5, { 0xba }, { 0xff } }, | |
1506 | ||
1507 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1508 | encoding for `mov m32, %eax'. | |
1509 | ||
85102364 | 1510 | ??? Should we handle SIB addressing here? |
37bdc87e MK |
1511 | ??? Should we handle 16-bit operand-sizes here? */ |
1512 | ||
1513 | /* `movl m32, %eax' */ | |
1514 | { 5, { 0xa1 }, { 0xff } }, | |
1515 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1516 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1517 | /* `movl m32, %edx' */ | |
1518 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1519 | ||
1520 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1521 | Because of the symmetry, there are actually two ways to encode | |
1522 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1523 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1524 | ||
1525 | /* `subl %eax, %eax' */ | |
1526 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1527 | /* `subl %ecx, %ecx' */ | |
1528 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1529 | /* `subl %edx, %edx' */ | |
1530 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1531 | /* `xorl %eax, %eax' */ | |
1532 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1533 | /* `xorl %ecx, %ecx' */ | |
1534 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1535 | /* `xorl %edx, %edx' */ | |
1536 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1537 | { 0 } | |
1538 | }; | |
1539 | ||
e11481da PM |
1540 | |
1541 | /* Check whether PC points to a no-op instruction. */ | |
1542 | static CORE_ADDR | |
1543 | i386_skip_noop (CORE_ADDR pc) | |
1544 | { | |
1545 | gdb_byte op; | |
1546 | int check = 1; | |
1547 | ||
0865b04a | 1548 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1549 | return pc; |
e11481da PM |
1550 | |
1551 | while (check) | |
1552 | { | |
1553 | check = 0; | |
1554 | /* Ignore `nop' instruction. */ | |
1555 | if (op == 0x90) | |
1556 | { | |
1557 | pc += 1; | |
0865b04a | 1558 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1559 | return pc; |
e11481da PM |
1560 | check = 1; |
1561 | } | |
1562 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1563 | Microsoft system dlls often start with | |
1564 | a `mov %edi,%edi' instruction. | |
1565 | The 5 bytes before the function start are | |
1566 | filled with `nop' instructions. | |
1567 | This pattern can be used for hot-patching: | |
1568 | The `mov %edi, %edi' instruction can be replaced by a | |
1569 | near jump to the location of the 5 `nop' instructions | |
1570 | which can be replaced by a 32-bit jump to anywhere | |
1571 | in the 32-bit address space. */ | |
1572 | ||
1573 | else if (op == 0x8b) | |
1574 | { | |
0865b04a | 1575 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1576 | return pc; |
1577 | ||
e11481da PM |
1578 | if (op == 0xff) |
1579 | { | |
1580 | pc += 2; | |
0865b04a | 1581 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1582 | return pc; |
1583 | ||
e11481da PM |
1584 | check = 1; |
1585 | } | |
1586 | } | |
1587 | } | |
1588 | return pc; | |
1589 | } | |
1590 | ||
acd5c798 MK |
1591 | /* Check whether PC points at a code that sets up a new stack frame. |
1592 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1593 | instruction after the sequence that sets up the frame or LIMIT, |
1594 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1595 | |
1596 | static CORE_ADDR | |
e17a4113 UW |
1597 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1598 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1599 | struct i386_frame_cache *cache) |
1600 | { | |
e17a4113 | 1601 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1602 | struct i386_insn *insn; |
63c0089f | 1603 | gdb_byte op; |
26604a34 | 1604 | int skip = 0; |
acd5c798 | 1605 | |
37bdc87e MK |
1606 | if (limit <= pc) |
1607 | return limit; | |
acd5c798 | 1608 | |
0865b04a | 1609 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1610 | return pc; |
acd5c798 | 1611 | |
c906108c | 1612 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1613 | { |
acd5c798 MK |
1614 | /* Take into account that we've executed the `pushl %ebp' that |
1615 | starts this instruction sequence. */ | |
fd13a04a | 1616 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1617 | cache->sp_offset += 4; |
37bdc87e | 1618 | pc++; |
acd5c798 MK |
1619 | |
1620 | /* If that's all, return now. */ | |
37bdc87e MK |
1621 | if (limit <= pc) |
1622 | return limit; | |
26604a34 | 1623 | |
b4632131 | 1624 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1625 | GCC into the prologue and skip them. At this point in the |
1626 | prologue, code should only touch the scratch registers %eax, | |
30baf67b | 1627 | %ecx and %edx, so while the number of possibilities is sheer, |
37bdc87e | 1628 | it is limited. |
5daa5b4e | 1629 | |
26604a34 MK |
1630 | Make sure we only skip these instructions if we later see the |
1631 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1632 | while (pc + skip < limit) |
26604a34 | 1633 | { |
37bdc87e MK |
1634 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1635 | if (insn == NULL) | |
1636 | break; | |
b4632131 | 1637 | |
37bdc87e | 1638 | skip += insn->len; |
26604a34 MK |
1639 | } |
1640 | ||
37bdc87e MK |
1641 | /* If that's all, return now. */ |
1642 | if (limit <= pc + skip) | |
1643 | return limit; | |
1644 | ||
0865b04a | 1645 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1646 | return pc + skip; |
37bdc87e | 1647 | |
30f8135b YQ |
1648 | /* The i386 prologue looks like |
1649 | ||
1650 | push %ebp | |
1651 | mov %esp,%ebp | |
1652 | sub $0x10,%esp | |
1653 | ||
1654 | and a different prologue can be generated for atom. | |
1655 | ||
1656 | push %ebp | |
1657 | lea (%esp),%ebp | |
1658 | lea -0x10(%esp),%esp | |
1659 | ||
1660 | We handle both of them here. */ | |
1661 | ||
acd5c798 | 1662 | switch (op) |
c906108c | 1663 | { |
30f8135b | 1664 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1665 | case 0x8b: |
0865b04a | 1666 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1667 | != 0xec) |
37bdc87e | 1668 | return pc; |
30f8135b | 1669 | pc += (skip + 2); |
c906108c SS |
1670 | break; |
1671 | case 0x89: | |
0865b04a | 1672 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1673 | != 0xe5) |
37bdc87e | 1674 | return pc; |
30f8135b YQ |
1675 | pc += (skip + 2); |
1676 | break; | |
1677 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1678 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1679 | != 0x242c) |
1680 | return pc; | |
1681 | pc += (skip + 3); | |
c906108c SS |
1682 | break; |
1683 | default: | |
37bdc87e | 1684 | return pc; |
c906108c | 1685 | } |
acd5c798 | 1686 | |
26604a34 MK |
1687 | /* OK, we actually have a frame. We just don't know how large |
1688 | it is yet. Set its size to zero. We'll adjust it if | |
1689 | necessary. We also now commit to skipping the special | |
1690 | instructions mentioned before. */ | |
acd5c798 MK |
1691 | cache->locals = 0; |
1692 | ||
1693 | /* If that's all, return now. */ | |
37bdc87e MK |
1694 | if (limit <= pc) |
1695 | return limit; | |
acd5c798 | 1696 | |
fc338970 MK |
1697 | /* Check for stack adjustment |
1698 | ||
acd5c798 | 1699 | subl $XXX, %esp |
30f8135b YQ |
1700 | or |
1701 | lea -XXX(%esp),%esp | |
fc338970 | 1702 | |
fd35795f | 1703 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1704 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1705 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1706 | return pc; |
c906108c SS |
1707 | if (op == 0x83) |
1708 | { | |
fd35795f | 1709 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1710 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1711 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1712 | return pc; |
acd5c798 | 1713 | |
37bdc87e MK |
1714 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1715 | make sense to be negative). */ | |
0865b04a | 1716 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1717 | return pc + 3; |
c906108c SS |
1718 | } |
1719 | else if (op == 0x81) | |
1720 | { | |
fd35795f | 1721 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1722 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1723 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1724 | return pc; |
acd5c798 | 1725 | |
fd35795f | 1726 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1727 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1728 | return pc + 6; |
c906108c | 1729 | } |
30f8135b YQ |
1730 | else if (op == 0x8d) |
1731 | { | |
1732 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1733 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1734 | return pc; |
1735 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1736 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1737 | return pc + 4; |
1738 | } | |
c906108c SS |
1739 | else |
1740 | { | |
30f8135b | 1741 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1742 | return pc; |
c906108c SS |
1743 | } |
1744 | } | |
37bdc87e | 1745 | else if (op == 0xc8) /* enter */ |
c906108c | 1746 | { |
0865b04a | 1747 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1748 | return pc + 4; |
c906108c | 1749 | } |
21d0e8a4 | 1750 | |
acd5c798 | 1751 | return pc; |
21d0e8a4 MK |
1752 | } |
1753 | ||
acd5c798 MK |
1754 | /* Check whether PC points at code that saves registers on the stack. |
1755 | If so, it updates CACHE and returns the address of the first | |
1756 | instruction after the register saves or CURRENT_PC, whichever is | |
1757 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1758 | |
1759 | static CORE_ADDR | |
acd5c798 MK |
1760 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1761 | struct i386_frame_cache *cache) | |
6bff26de | 1762 | { |
99ab4326 | 1763 | CORE_ADDR offset = 0; |
63c0089f | 1764 | gdb_byte op; |
99ab4326 | 1765 | int i; |
c0d1d883 | 1766 | |
99ab4326 MK |
1767 | if (cache->locals > 0) |
1768 | offset -= cache->locals; | |
1769 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1770 | { | |
0865b04a | 1771 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1772 | return pc; |
99ab4326 MK |
1773 | if (op < 0x50 || op > 0x57) |
1774 | break; | |
0d17c81d | 1775 | |
99ab4326 MK |
1776 | offset -= 4; |
1777 | cache->saved_regs[op - 0x50] = offset; | |
1778 | cache->sp_offset += 4; | |
1779 | pc++; | |
6bff26de MK |
1780 | } |
1781 | ||
acd5c798 | 1782 | return pc; |
22797942 AC |
1783 | } |
1784 | ||
acd5c798 MK |
1785 | /* Do a full analysis of the prologue at PC and update CACHE |
1786 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1787 | address where the analysis stopped. | |
ed84f6c1 | 1788 | |
fc338970 MK |
1789 | We handle these cases: |
1790 | ||
1791 | The startup sequence can be at the start of the function, or the | |
1792 | function can start with a branch to startup code at the end. | |
1793 | ||
1794 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1795 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1796 | once used in the System V compiler). | |
1797 | ||
1798 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1799 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1800 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1801 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1802 | |
1803 | Next, the registers used by this function are pushed. With the | |
1804 | System V compiler they will always be in the order: %edi, %esi, | |
1805 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1806 | restore %eax); however, the code below is willing to see the pushes | |
1807 | in any order, and will handle up to 8 of them. | |
1808 | ||
1809 | If the setup sequence is at the end of the function, then the next | |
1810 | instruction will be a branch back to the start. */ | |
c906108c | 1811 | |
acd5c798 | 1812 | static CORE_ADDR |
e17a4113 UW |
1813 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1814 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1815 | struct i386_frame_cache *cache) |
c906108c | 1816 | { |
e11481da | 1817 | pc = i386_skip_noop (pc); |
e17a4113 | 1818 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1819 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1820 | pc = i386_skip_probe (pc); | |
92dd43fa | 1821 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1822 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1823 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1824 | } |
1825 | ||
fc338970 | 1826 | /* Return PC of first real instruction. */ |
c906108c | 1827 | |
3a1e71e3 | 1828 | static CORE_ADDR |
6093d2eb | 1829 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1830 | { |
e17a4113 UW |
1831 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1832 | ||
63c0089f | 1833 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1834 | { |
1835 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1836 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1837 | }; |
acd5c798 MK |
1838 | struct i386_frame_cache cache; |
1839 | CORE_ADDR pc; | |
63c0089f | 1840 | gdb_byte op; |
acd5c798 | 1841 | int i; |
56bf0743 | 1842 | CORE_ADDR func_addr; |
4e879fc2 | 1843 | |
56bf0743 KB |
1844 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1845 | { | |
1846 | CORE_ADDR post_prologue_pc | |
1847 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1848 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
56bf0743 KB |
1849 | |
1850 | /* Clang always emits a line note before the prologue and another | |
1851 | one after. We trust clang to emit usable line notes. */ | |
1852 | if (post_prologue_pc | |
43f3e411 DE |
1853 | && (cust != NULL |
1854 | && COMPUNIT_PRODUCER (cust) != NULL | |
61012eef | 1855 | && startswith (COMPUNIT_PRODUCER (cust), "clang "))) |
325fac50 | 1856 | return std::max (start_pc, post_prologue_pc); |
56bf0743 KB |
1857 | } |
1858 | ||
e0f33b1f | 1859 | cache.locals = -1; |
e17a4113 | 1860 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1861 | if (cache.locals < 0) |
1862 | return start_pc; | |
c5aa993b | 1863 | |
acd5c798 | 1864 | /* Found valid frame setup. */ |
c906108c | 1865 | |
fc338970 MK |
1866 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1867 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1868 | %ebx: |
1869 | ||
fc338970 MK |
1870 | call 0x0 |
1871 | popl %ebx | |
1872 | movl %ebx,x(%ebp) (optional) | |
1873 | addl y,%ebx | |
1874 | ||
c906108c SS |
1875 | This code is with the rest of the prologue (at the end of the |
1876 | function), so we have to skip it to get to the first real | |
1877 | instruction at the start of the function. */ | |
c5aa993b | 1878 | |
c906108c SS |
1879 | for (i = 0; i < 6; i++) |
1880 | { | |
0865b04a | 1881 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1882 | return pc; |
1883 | ||
c5aa993b | 1884 | if (pic_pat[i] != op) |
c906108c SS |
1885 | break; |
1886 | } | |
1887 | if (i == 6) | |
1888 | { | |
acd5c798 MK |
1889 | int delta = 6; |
1890 | ||
0865b04a | 1891 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1892 | return pc; |
c906108c | 1893 | |
c5aa993b | 1894 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1895 | { |
0865b04a | 1896 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1897 | |
fc338970 | 1898 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1899 | delta += 3; |
fc338970 | 1900 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1901 | delta += 6; |
fc338970 | 1902 | else /* Unexpected instruction. */ |
acd5c798 MK |
1903 | delta = 0; |
1904 | ||
0865b04a | 1905 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1906 | return pc; |
c906108c | 1907 | } |
acd5c798 | 1908 | |
c5aa993b | 1909 | /* addl y,%ebx */ |
acd5c798 | 1910 | if (delta > 0 && op == 0x81 |
0865b04a | 1911 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1912 | == 0xc3) |
c906108c | 1913 | { |
acd5c798 | 1914 | pc += delta + 6; |
c906108c SS |
1915 | } |
1916 | } | |
c5aa993b | 1917 | |
e63bbc88 MK |
1918 | /* If the function starts with a branch (to startup code at the end) |
1919 | the last instruction should bring us back to the first | |
1920 | instruction of the real code. */ | |
e17a4113 UW |
1921 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1922 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1923 | |
1924 | return pc; | |
c906108c SS |
1925 | } |
1926 | ||
4309257c PM |
1927 | /* Check that the code pointed to by PC corresponds to a call to |
1928 | __main, skip it if so. Return PC otherwise. */ | |
1929 | ||
1930 | CORE_ADDR | |
1931 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1932 | { | |
e17a4113 | 1933 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1934 | gdb_byte op; |
1935 | ||
0865b04a | 1936 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1937 | return pc; |
4309257c PM |
1938 | if (op == 0xe8) |
1939 | { | |
1940 | gdb_byte buf[4]; | |
1941 | ||
0865b04a | 1942 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
4309257c PM |
1943 | { |
1944 | /* Make sure address is computed correctly as a 32bit | |
1945 | integer even if CORE_ADDR is 64 bit wide. */ | |
7cbd4a93 | 1946 | struct bound_minimal_symbol s; |
e17a4113 | 1947 | CORE_ADDR call_dest; |
4309257c | 1948 | |
e17a4113 | 1949 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1950 | call_dest = call_dest & 0xffffffffU; |
1951 | s = lookup_minimal_symbol_by_pc (call_dest); | |
7cbd4a93 | 1952 | if (s.minsym != NULL |
c9d95fa3 CB |
1953 | && s.minsym->linkage_name () != NULL |
1954 | && strcmp (s.minsym->linkage_name (), "__main") == 0) | |
4309257c PM |
1955 | pc += 5; |
1956 | } | |
1957 | } | |
1958 | ||
1959 | return pc; | |
1960 | } | |
1961 | ||
acd5c798 | 1962 | /* This function is 64-bit safe. */ |
93924b6b | 1963 | |
acd5c798 MK |
1964 | static CORE_ADDR |
1965 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1966 | { |
63c0089f | 1967 | gdb_byte buf[8]; |
acd5c798 | 1968 | |
875f8d0e | 1969 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1970 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1971 | } |
acd5c798 | 1972 | \f |
93924b6b | 1973 | |
acd5c798 | 1974 | /* Normal frames. */ |
c5aa993b | 1975 | |
8fbca658 PA |
1976 | static void |
1977 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1978 | struct i386_frame_cache *cache) | |
a7769679 | 1979 | { |
e17a4113 UW |
1980 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1981 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1982 | gdb_byte buf[4]; |
acd5c798 MK |
1983 | int i; |
1984 | ||
8fbca658 | 1985 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1986 | |
1987 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1988 | which holds the base address for the current stack frame. | |
1989 | However, for functions that don't need it, the frame pointer is | |
1990 | optional. For these "frameless" functions the frame pointer is | |
1991 | actually the frame pointer of the calling frame. Signal | |
1992 | trampolines are just a special case of a "frameless" function. | |
1993 | They (usually) share their frame pointer with the frame that was | |
1994 | in progress when the signal occurred. */ | |
1995 | ||
10458914 | 1996 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1997 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1998 | if (cache->base == 0) |
620fa63a PA |
1999 | { |
2000 | cache->base_p = 1; | |
2001 | return; | |
2002 | } | |
acd5c798 MK |
2003 | |
2004 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 2005 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 2006 | |
acd5c798 | 2007 | if (cache->pc != 0) |
e17a4113 UW |
2008 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
2009 | cache); | |
acd5c798 MK |
2010 | |
2011 | if (cache->locals < 0) | |
2012 | { | |
2013 | /* We didn't find a valid frame, which means that CACHE->base | |
2014 | currently holds the frame pointer for our calling frame. If | |
2015 | we're at the start of a function, or somewhere half-way its | |
2016 | prologue, the function's frame probably hasn't been fully | |
2017 | setup yet. Try to reconstruct the base address for the stack | |
2018 | frame by looking at the stack pointer. For truly "frameless" | |
2019 | functions this might work too. */ | |
2020 | ||
e0c62198 | 2021 | if (cache->saved_sp_reg != -1) |
92dd43fa | 2022 | { |
8fbca658 PA |
2023 | /* Saved stack pointer has been saved. */ |
2024 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2025 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
2026 | ||
92dd43fa MK |
2027 | /* We're halfway aligning the stack. */ |
2028 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
2029 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
2030 | ||
2031 | /* This will be added back below. */ | |
2032 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
2033 | } | |
7618e12b | 2034 | else if (cache->pc != 0 |
0865b04a | 2035 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 2036 | { |
7618e12b DJ |
2037 | /* We're in a known function, but did not find a frame |
2038 | setup. Assume that the function does not use %ebp. | |
2039 | Alternatively, we may have jumped to an invalid | |
2040 | address; in that case there is definitely no new | |
2041 | frame in %ebp. */ | |
10458914 | 2042 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
2043 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
2044 | + cache->sp_offset; | |
92dd43fa | 2045 | } |
7618e12b DJ |
2046 | else |
2047 | /* We're in an unknown function. We could not find the start | |
2048 | of the function to analyze the prologue; our best option is | |
2049 | to assume a typical frame layout with the caller's %ebp | |
2050 | saved. */ | |
2051 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
2052 | } |
2053 | ||
8fbca658 PA |
2054 | if (cache->saved_sp_reg != -1) |
2055 | { | |
2056 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
2057 | register may be unavailable). */ | |
2058 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
2059 | && deprecated_frame_register_read (this_frame, |
2060 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
2061 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
2062 | } | |
acd5c798 MK |
2063 | /* Now that we have the base address for the stack frame we can |
2064 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 2065 | else if (cache->saved_sp == 0) |
92dd43fa | 2066 | cache->saved_sp = cache->base + 8; |
a7769679 | 2067 | |
acd5c798 MK |
2068 | /* Adjust all the saved registers such that they contain addresses |
2069 | instead of offsets. */ | |
2070 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
2071 | if (cache->saved_regs[i] != -1) |
2072 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 2073 | |
8fbca658 PA |
2074 | cache->base_p = 1; |
2075 | } | |
2076 | ||
2077 | static struct i386_frame_cache * | |
2078 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2079 | { | |
8fbca658 PA |
2080 | struct i386_frame_cache *cache; |
2081 | ||
2082 | if (*this_cache) | |
9a3c8263 | 2083 | return (struct i386_frame_cache *) *this_cache; |
8fbca658 PA |
2084 | |
2085 | cache = i386_alloc_frame_cache (); | |
2086 | *this_cache = cache; | |
2087 | ||
a70b8144 | 2088 | try |
8fbca658 PA |
2089 | { |
2090 | i386_frame_cache_1 (this_frame, cache); | |
2091 | } | |
230d2906 | 2092 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2093 | { |
2094 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2095 | throw; |
7556d4a4 | 2096 | } |
8fbca658 | 2097 | |
acd5c798 | 2098 | return cache; |
a7769679 MK |
2099 | } |
2100 | ||
3a1e71e3 | 2101 | static void |
10458914 | 2102 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 2103 | struct frame_id *this_id) |
c906108c | 2104 | { |
10458914 | 2105 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 2106 | |
5ce0145d PA |
2107 | if (!cache->base_p) |
2108 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
2109 | else if (cache->base == 0) | |
2110 | { | |
2111 | /* This marks the outermost frame. */ | |
2112 | } | |
2113 | else | |
2114 | { | |
2115 | /* See the end of i386_push_dummy_call. */ | |
2116 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
2117 | } | |
acd5c798 MK |
2118 | } |
2119 | ||
8fbca658 PA |
2120 | static enum unwind_stop_reason |
2121 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2122 | void **this_cache) | |
2123 | { | |
2124 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
2125 | ||
2126 | if (!cache->base_p) | |
2127 | return UNWIND_UNAVAILABLE; | |
2128 | ||
2129 | /* This marks the outermost frame. */ | |
2130 | if (cache->base == 0) | |
2131 | return UNWIND_OUTERMOST; | |
2132 | ||
2133 | return UNWIND_NO_REASON; | |
2134 | } | |
2135 | ||
10458914 DJ |
2136 | static struct value * |
2137 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2138 | int regnum) | |
acd5c798 | 2139 | { |
10458914 | 2140 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2141 | |
2142 | gdb_assert (regnum >= 0); | |
2143 | ||
2144 | /* The System V ABI says that: | |
2145 | ||
2146 | "The flags register contains the system flags, such as the | |
2147 | direction flag and the carry flag. The direction flag must be | |
2148 | set to the forward (that is, zero) direction before entry and | |
2149 | upon exit from a function. Other user flags have no specified | |
2150 | role in the standard calling sequence and are not preserved." | |
2151 | ||
2152 | To guarantee the "upon exit" part of that statement we fake a | |
2153 | saved flags register that has its direction flag cleared. | |
2154 | ||
2155 | Note that GCC doesn't seem to rely on the fact that the direction | |
2156 | flag is cleared after a function return; it always explicitly | |
2157 | clears the flag before operations where it matters. | |
2158 | ||
2159 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
2160 | right thing to do. The way we fake the flags register here makes | |
2161 | it impossible to change it. */ | |
2162 | ||
2163 | if (regnum == I386_EFLAGS_REGNUM) | |
2164 | { | |
10458914 | 2165 | ULONGEST val; |
c5aa993b | 2166 | |
10458914 DJ |
2167 | val = get_frame_register_unsigned (this_frame, regnum); |
2168 | val &= ~(1 << 10); | |
2169 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 2170 | } |
1211c4e4 | 2171 | |
acd5c798 | 2172 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 2173 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 2174 | |
fcf250e2 UW |
2175 | if (regnum == I386_ESP_REGNUM |
2176 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
2177 | { |
2178 | /* If the SP has been saved, but we don't know where, then this | |
2179 | means that SAVED_SP_REG register was found unavailable back | |
2180 | when we built the cache. */ | |
fcf250e2 | 2181 | if (cache->saved_sp == 0) |
8fbca658 PA |
2182 | return frame_unwind_got_register (this_frame, regnum, |
2183 | cache->saved_sp_reg); | |
2184 | else | |
2185 | return frame_unwind_got_constant (this_frame, regnum, | |
2186 | cache->saved_sp); | |
2187 | } | |
acd5c798 | 2188 | |
fd13a04a | 2189 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2190 | return frame_unwind_got_memory (this_frame, regnum, |
2191 | cache->saved_regs[regnum]); | |
fd13a04a | 2192 | |
10458914 | 2193 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
2194 | } |
2195 | ||
2196 | static const struct frame_unwind i386_frame_unwind = | |
2197 | { | |
2198 | NORMAL_FRAME, | |
8fbca658 | 2199 | i386_frame_unwind_stop_reason, |
acd5c798 | 2200 | i386_frame_this_id, |
10458914 DJ |
2201 | i386_frame_prev_register, |
2202 | NULL, | |
2203 | default_frame_sniffer | |
acd5c798 | 2204 | }; |
06da04c6 MS |
2205 | |
2206 | /* Normal frames, but in a function epilogue. */ | |
2207 | ||
c9cf6e20 MG |
2208 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2209 | ||
2210 | The epilogue is defined here as the 'ret' instruction, which will | |
06da04c6 MS |
2211 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
2212 | the function's stack frame. */ | |
2213 | ||
2214 | static int | |
c9cf6e20 | 2215 | i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
06da04c6 MS |
2216 | { |
2217 | gdb_byte insn; | |
43f3e411 | 2218 | struct compunit_symtab *cust; |
e0d00bc7 | 2219 | |
43f3e411 DE |
2220 | cust = find_pc_compunit_symtab (pc); |
2221 | if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) | |
e0d00bc7 | 2222 | return 0; |
06da04c6 MS |
2223 | |
2224 | if (target_read_memory (pc, &insn, 1)) | |
2225 | return 0; /* Can't read memory at pc. */ | |
2226 | ||
2227 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2228 | return 0; | |
2229 | ||
2230 | return 1; | |
2231 | } | |
2232 | ||
2233 | static int | |
2234 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2235 | struct frame_info *this_frame, | |
2236 | void **this_prologue_cache) | |
2237 | { | |
2238 | if (frame_relative_level (this_frame) == 0) | |
c9cf6e20 MG |
2239 | return i386_stack_frame_destroyed_p (get_frame_arch (this_frame), |
2240 | get_frame_pc (this_frame)); | |
06da04c6 MS |
2241 | else |
2242 | return 0; | |
2243 | } | |
2244 | ||
2245 | static struct i386_frame_cache * | |
2246 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2247 | { | |
06da04c6 | 2248 | struct i386_frame_cache *cache; |
0d6c2135 | 2249 | CORE_ADDR sp; |
06da04c6 MS |
2250 | |
2251 | if (*this_cache) | |
9a3c8263 | 2252 | return (struct i386_frame_cache *) *this_cache; |
06da04c6 MS |
2253 | |
2254 | cache = i386_alloc_frame_cache (); | |
2255 | *this_cache = cache; | |
2256 | ||
a70b8144 | 2257 | try |
8fbca658 | 2258 | { |
0d6c2135 | 2259 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2260 | |
0d6c2135 MK |
2261 | /* At this point the stack looks as if we just entered the |
2262 | function, with the return address at the top of the | |
2263 | stack. */ | |
2264 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2265 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2266 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2267 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2268 | |
8fbca658 PA |
2269 | cache->base_p = 1; |
2270 | } | |
230d2906 | 2271 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2272 | { |
2273 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2274 | throw; |
7556d4a4 | 2275 | } |
06da04c6 MS |
2276 | |
2277 | return cache; | |
2278 | } | |
2279 | ||
8fbca658 PA |
2280 | static enum unwind_stop_reason |
2281 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2282 | void **this_cache) | |
2283 | { | |
0d6c2135 MK |
2284 | struct i386_frame_cache *cache = |
2285 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2286 | |
2287 | if (!cache->base_p) | |
2288 | return UNWIND_UNAVAILABLE; | |
2289 | ||
2290 | return UNWIND_NO_REASON; | |
2291 | } | |
2292 | ||
06da04c6 MS |
2293 | static void |
2294 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2295 | void **this_cache, | |
2296 | struct frame_id *this_id) | |
2297 | { | |
0d6c2135 MK |
2298 | struct i386_frame_cache *cache = |
2299 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2300 | |
8fbca658 | 2301 | if (!cache->base_p) |
5ce0145d PA |
2302 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2303 | else | |
2304 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2305 | } |
2306 | ||
0d6c2135 MK |
2307 | static struct value * |
2308 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2309 | void **this_cache, int regnum) | |
2310 | { | |
2311 | /* Make sure we've initialized the cache. */ | |
2312 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2313 | ||
2314 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2315 | } | |
2316 | ||
06da04c6 MS |
2317 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2318 | { | |
2319 | NORMAL_FRAME, | |
8fbca658 | 2320 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2321 | i386_epilogue_frame_this_id, |
0d6c2135 | 2322 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2323 | NULL, |
2324 | i386_epilogue_frame_sniffer | |
2325 | }; | |
acd5c798 MK |
2326 | \f |
2327 | ||
a3fcb948 JG |
2328 | /* Stack-based trampolines. */ |
2329 | ||
2330 | /* These trampolines are used on cross x86 targets, when taking the | |
2331 | address of a nested function. When executing these trampolines, | |
2332 | no stack frame is set up, so we are in a similar situation as in | |
2333 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2334 | ||
2335 | /* Static chain passed in register. */ | |
2336 | ||
2337 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2338 | { | |
2339 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2340 | { 5, { 0xb8 }, { 0xfe } }, | |
2341 | ||
2342 | /* `jmp imm32' */ | |
2343 | { 5, { 0xe9 }, { 0xff } }, | |
2344 | ||
2345 | {0} | |
2346 | }; | |
2347 | ||
2348 | /* Static chain passed on stack (when regparm=3). */ | |
2349 | ||
2350 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2351 | { | |
2352 | /* `push imm32' */ | |
2353 | { 5, { 0x68 }, { 0xff } }, | |
2354 | ||
2355 | /* `jmp imm32' */ | |
2356 | { 5, { 0xe9 }, { 0xff } }, | |
2357 | ||
2358 | {0} | |
2359 | }; | |
2360 | ||
2361 | /* Return whether PC points inside a stack trampoline. */ | |
2362 | ||
2363 | static int | |
6df81a63 | 2364 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2365 | { |
2366 | gdb_byte insn; | |
2c02bd72 | 2367 | const char *name; |
a3fcb948 JG |
2368 | |
2369 | /* A stack trampoline is detected if no name is associated | |
2370 | to the current pc and if it points inside a trampoline | |
2371 | sequence. */ | |
2372 | ||
2373 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2374 | if (name) | |
2375 | return 0; | |
2376 | ||
2377 | if (target_read_memory (pc, &insn, 1)) | |
2378 | return 0; | |
2379 | ||
2380 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2381 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2382 | return 0; | |
2383 | ||
2384 | return 1; | |
2385 | } | |
2386 | ||
2387 | static int | |
2388 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2389 | struct frame_info *this_frame, |
2390 | void **this_cache) | |
a3fcb948 JG |
2391 | { |
2392 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2393 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2394 | else |
2395 | return 0; | |
2396 | } | |
2397 | ||
2398 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2399 | { | |
2400 | NORMAL_FRAME, | |
2401 | i386_epilogue_frame_unwind_stop_reason, | |
2402 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2403 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2404 | NULL, |
2405 | i386_stack_tramp_frame_sniffer | |
2406 | }; | |
2407 | \f | |
6710bf39 SS |
2408 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2409 | ||
2410 | static void | |
2411 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2412 | struct agent_expr *ax, struct axs_value *value, | |
2413 | CORE_ADDR scope) | |
2414 | { | |
2415 | /* The following sequence assumes the traditional use of the base | |
2416 | register. */ | |
2417 | ax_reg (ax, I386_EBP_REGNUM); | |
2418 | ax_const_l (ax, 4); | |
2419 | ax_simple (ax, aop_add); | |
2420 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2421 | value->kind = axs_lvalue_memory; | |
2422 | } | |
2423 | \f | |
a3fcb948 | 2424 | |
acd5c798 MK |
2425 | /* Signal trampolines. */ |
2426 | ||
2427 | static struct i386_frame_cache * | |
10458914 | 2428 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2429 | { |
e17a4113 UW |
2430 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2431 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2432 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 2433 | struct i386_frame_cache *cache; |
acd5c798 | 2434 | CORE_ADDR addr; |
63c0089f | 2435 | gdb_byte buf[4]; |
acd5c798 MK |
2436 | |
2437 | if (*this_cache) | |
9a3c8263 | 2438 | return (struct i386_frame_cache *) *this_cache; |
acd5c798 | 2439 | |
fd13a04a | 2440 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2441 | |
a70b8144 | 2442 | try |
a3386186 | 2443 | { |
8fbca658 PA |
2444 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2445 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2446 | |
8fbca658 PA |
2447 | addr = tdep->sigcontext_addr (this_frame); |
2448 | if (tdep->sc_reg_offset) | |
2449 | { | |
2450 | int i; | |
a3386186 | 2451 | |
8fbca658 PA |
2452 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2453 | ||
2454 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2455 | if (tdep->sc_reg_offset[i] != -1) | |
2456 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2457 | } | |
2458 | else | |
2459 | { | |
2460 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2461 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2462 | } | |
2463 | ||
2464 | cache->base_p = 1; | |
a3386186 | 2465 | } |
230d2906 | 2466 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2467 | { |
2468 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2469 | throw; |
7556d4a4 | 2470 | } |
acd5c798 MK |
2471 | |
2472 | *this_cache = cache; | |
2473 | return cache; | |
2474 | } | |
2475 | ||
8fbca658 PA |
2476 | static enum unwind_stop_reason |
2477 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2478 | void **this_cache) | |
2479 | { | |
2480 | struct i386_frame_cache *cache = | |
2481 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2482 | ||
2483 | if (!cache->base_p) | |
2484 | return UNWIND_UNAVAILABLE; | |
2485 | ||
2486 | return UNWIND_NO_REASON; | |
2487 | } | |
2488 | ||
acd5c798 | 2489 | static void |
10458914 | 2490 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2491 | struct frame_id *this_id) |
2492 | { | |
2493 | struct i386_frame_cache *cache = | |
10458914 | 2494 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2495 | |
8fbca658 | 2496 | if (!cache->base_p) |
5ce0145d PA |
2497 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2498 | else | |
2499 | { | |
2500 | /* See the end of i386_push_dummy_call. */ | |
2501 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2502 | } | |
acd5c798 MK |
2503 | } |
2504 | ||
10458914 DJ |
2505 | static struct value * |
2506 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2507 | void **this_cache, int regnum) | |
acd5c798 MK |
2508 | { |
2509 | /* Make sure we've initialized the cache. */ | |
10458914 | 2510 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2511 | |
10458914 | 2512 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2513 | } |
c0d1d883 | 2514 | |
10458914 DJ |
2515 | static int |
2516 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2517 | struct frame_info *this_frame, | |
2518 | void **this_prologue_cache) | |
acd5c798 | 2519 | { |
10458914 | 2520 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2521 | |
911bc6ee MK |
2522 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2523 | handler. */ | |
2524 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2525 | return 0; |
1c3545ae | 2526 | |
911bc6ee MK |
2527 | if (tdep->sigtramp_p != NULL) |
2528 | { | |
10458914 DJ |
2529 | if (tdep->sigtramp_p (this_frame)) |
2530 | return 1; | |
911bc6ee MK |
2531 | } |
2532 | ||
2533 | if (tdep->sigtramp_start != 0) | |
2534 | { | |
10458914 | 2535 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2536 | |
2537 | gdb_assert (tdep->sigtramp_end != 0); | |
2538 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2539 | return 1; |
911bc6ee | 2540 | } |
acd5c798 | 2541 | |
10458914 | 2542 | return 0; |
acd5c798 | 2543 | } |
10458914 DJ |
2544 | |
2545 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2546 | { | |
2547 | SIGTRAMP_FRAME, | |
8fbca658 | 2548 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2549 | i386_sigtramp_frame_this_id, |
2550 | i386_sigtramp_frame_prev_register, | |
2551 | NULL, | |
2552 | i386_sigtramp_frame_sniffer | |
2553 | }; | |
acd5c798 MK |
2554 | \f |
2555 | ||
2556 | static CORE_ADDR | |
10458914 | 2557 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2558 | { |
10458914 | 2559 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2560 | |
2561 | return cache->base; | |
2562 | } | |
2563 | ||
2564 | static const struct frame_base i386_frame_base = | |
2565 | { | |
2566 | &i386_frame_unwind, | |
2567 | i386_frame_base_address, | |
2568 | i386_frame_base_address, | |
2569 | i386_frame_base_address | |
2570 | }; | |
2571 | ||
acd5c798 | 2572 | static struct frame_id |
10458914 | 2573 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2574 | { |
acd5c798 MK |
2575 | CORE_ADDR fp; |
2576 | ||
10458914 | 2577 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2578 | |
3e210248 | 2579 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2580 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2581 | } |
e04e5beb JM |
2582 | |
2583 | /* _Decimal128 function return values need 16-byte alignment on the | |
2584 | stack. */ | |
2585 | ||
2586 | static CORE_ADDR | |
2587 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2588 | { | |
2589 | return sp & -(CORE_ADDR)16; | |
2590 | } | |
fc338970 | 2591 | \f |
c906108c | 2592 | |
fc338970 MK |
2593 | /* Figure out where the longjmp will land. Slurp the args out of the |
2594 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2595 | structure from which we extract the address that we will land at. |
28bcfd30 | 2596 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2597 | success. */ |
c906108c | 2598 | |
8201327c | 2599 | static int |
60ade65d | 2600 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2601 | { |
436675d3 | 2602 | gdb_byte buf[4]; |
c906108c | 2603 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2604 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2605 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2606 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2607 | |
8201327c MK |
2608 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2609 | longjmp will land. */ | |
2610 | if (jb_pc_offset == -1) | |
c906108c SS |
2611 | return 0; |
2612 | ||
436675d3 | 2613 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2614 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2615 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2616 | return 0; |
2617 | ||
e17a4113 | 2618 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2619 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2620 | return 0; |
c906108c | 2621 | |
e17a4113 | 2622 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2623 | return 1; |
2624 | } | |
fc338970 | 2625 | \f |
c906108c | 2626 | |
7ccc1c74 JM |
2627 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2628 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2629 | unions containing such types must be 16-byte-aligned; other | |
2630 | arguments are 4-byte-aligned. */ | |
2631 | ||
2632 | static int | |
2633 | i386_16_byte_align_p (struct type *type) | |
2634 | { | |
2635 | type = check_typedef (type); | |
2636 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2637 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2638 | && TYPE_LENGTH (type) == 16) | |
2639 | return 1; | |
2640 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2641 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2642 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2643 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2644 | { | |
2645 | int i; | |
2646 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2647 | { | |
2648 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2649 | return 1; | |
2650 | } | |
2651 | } | |
2652 | return 0; | |
2653 | } | |
2654 | ||
a9b8d892 JK |
2655 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2656 | ||
2657 | static CORE_ADDR | |
2658 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2659 | struct value **args, int nargs, struct type *value_type, | |
2660 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2661 | struct regcache *regcache) | |
2662 | { | |
2663 | /* Use 0xcc breakpoint - 1 byte. */ | |
2664 | *bp_addr = sp - 1; | |
2665 | *real_pc = funaddr; | |
2666 | ||
2667 | /* Keep the stack aligned. */ | |
2668 | return sp - 16; | |
2669 | } | |
2670 | ||
3a1e71e3 | 2671 | static CORE_ADDR |
7d9b040b | 2672 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a | 2673 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
cf84fa6b AH |
2674 | struct value **args, CORE_ADDR sp, |
2675 | function_call_return_method return_method, | |
6a65450a | 2676 | CORE_ADDR struct_addr) |
22f8ba57 | 2677 | { |
e17a4113 | 2678 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2679 | gdb_byte buf[4]; |
acd5c798 | 2680 | int i; |
7ccc1c74 JM |
2681 | int write_pass; |
2682 | int args_space = 0; | |
acd5c798 | 2683 | |
4a612d6f WT |
2684 | /* BND registers can be in arbitrary values at the moment of the |
2685 | inferior call. This can cause boundary violations that are not | |
2686 | due to a real bug or even desired by the user. The best to be done | |
2687 | is set the BND registers to allow access to the whole memory, INIT | |
2688 | state, before pushing the inferior call. */ | |
2689 | i387_reset_bnd_regs (gdbarch, regcache); | |
2690 | ||
7ccc1c74 JM |
2691 | /* Determine the total space required for arguments and struct |
2692 | return address in a first pass (allowing for 16-byte-aligned | |
2693 | arguments), then push arguments in a second pass. */ | |
2694 | ||
2695 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2696 | { |
7ccc1c74 | 2697 | int args_space_used = 0; |
7ccc1c74 | 2698 | |
cf84fa6b | 2699 | if (return_method == return_method_struct) |
7ccc1c74 JM |
2700 | { |
2701 | if (write_pass) | |
2702 | { | |
2703 | /* Push value address. */ | |
e17a4113 | 2704 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2705 | write_memory (sp, buf, 4); |
2706 | args_space_used += 4; | |
2707 | } | |
2708 | else | |
2709 | args_space += 4; | |
2710 | } | |
2711 | ||
2712 | for (i = 0; i < nargs; i++) | |
2713 | { | |
2714 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2715 | |
7ccc1c74 JM |
2716 | if (write_pass) |
2717 | { | |
2718 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2719 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2720 | |
7ccc1c74 JM |
2721 | write_memory (sp + args_space_used, |
2722 | value_contents_all (args[i]), len); | |
2723 | /* The System V ABI says that: | |
acd5c798 | 2724 | |
7ccc1c74 JM |
2725 | "An argument's size is increased, if necessary, to make it a |
2726 | multiple of [32-bit] words. This may require tail padding, | |
2727 | depending on the size of the argument." | |
22f8ba57 | 2728 | |
7ccc1c74 JM |
2729 | This makes sure the stack stays word-aligned. */ |
2730 | args_space_used += align_up (len, 4); | |
2731 | } | |
2732 | else | |
2733 | { | |
2734 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2735 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2736 | args_space += align_up (len, 4); |
2737 | } | |
2738 | } | |
2739 | ||
2740 | if (!write_pass) | |
2741 | { | |
7ccc1c74 | 2742 | sp -= args_space; |
284c5a60 MK |
2743 | |
2744 | /* The original System V ABI only requires word alignment, | |
2745 | but modern incarnations need 16-byte alignment in order | |
2746 | to support SSE. Since wasting a few bytes here isn't | |
2747 | harmful we unconditionally enforce 16-byte alignment. */ | |
2748 | sp &= ~0xf; | |
7ccc1c74 | 2749 | } |
22f8ba57 MK |
2750 | } |
2751 | ||
acd5c798 MK |
2752 | /* Store return address. */ |
2753 | sp -= 4; | |
e17a4113 | 2754 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2755 | write_memory (sp, buf, 4); |
2756 | ||
2757 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2758 | store_unsigned_integer (buf, 4, byte_order, sp); |
b66f5587 | 2759 | regcache->cooked_write (I386_ESP_REGNUM, buf); |
acd5c798 MK |
2760 | |
2761 | /* ...and fake a frame pointer. */ | |
b66f5587 | 2762 | regcache->cooked_write (I386_EBP_REGNUM, buf); |
acd5c798 | 2763 | |
3e210248 AC |
2764 | /* MarkK wrote: This "+ 8" is all over the place: |
2765 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2766 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2767 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2768 | definition of the stack address of a frame. Otherwise frame id |
2769 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2770 | stack address *before* the function call as a frame's CFA. On |
2771 | the i386, when %ebp is used as a frame pointer, the offset | |
2772 | between the contents %ebp and the CFA as defined by GCC. */ | |
2773 | return sp + 8; | |
22f8ba57 MK |
2774 | } |
2775 | ||
1a309862 MK |
2776 | /* These registers are used for returning integers (and on some |
2777 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2778 | size and alignment match an integer type). */ |
acd5c798 MK |
2779 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2780 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2781 | |
c5e656c1 MK |
2782 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2783 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2784 | |
3a1e71e3 | 2785 | static void |
c5e656c1 | 2786 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2787 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2788 | { |
c5e656c1 | 2789 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2790 | int len = TYPE_LENGTH (type); |
63c0089f | 2791 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2792 | |
1e8d0a7b | 2793 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2794 | { |
5716833c | 2795 | if (tdep->st0_regnum < 0) |
1a309862 | 2796 | { |
8a3fe4f8 | 2797 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2798 | memset (valbuf, 0, len); |
ef9dff19 | 2799 | return; |
1a309862 MK |
2800 | } |
2801 | ||
c6ba6f0d MK |
2802 | /* Floating-point return values can be found in %st(0). Convert |
2803 | its contents to the desired type. This is probably not | |
2804 | exactly how it would happen on the target itself, but it is | |
2805 | the best we can do. */ | |
0b883586 | 2806 | regcache->raw_read (I386_ST0_REGNUM, buf); |
3b2ca824 | 2807 | target_float_convert (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2808 | } |
2809 | else | |
c5aa993b | 2810 | { |
875f8d0e UW |
2811 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2812 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2813 | |
2814 | if (len <= low_size) | |
00f8375e | 2815 | { |
0b883586 | 2816 | regcache->raw_read (LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2817 | memcpy (valbuf, buf, len); |
2818 | } | |
d4f3574e SS |
2819 | else if (len <= (low_size + high_size)) |
2820 | { | |
0b883586 | 2821 | regcache->raw_read (LOW_RETURN_REGNUM, buf); |
00f8375e | 2822 | memcpy (valbuf, buf, low_size); |
0b883586 | 2823 | regcache->raw_read (HIGH_RETURN_REGNUM, buf); |
63c0089f | 2824 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2825 | } |
2826 | else | |
8e65ff28 | 2827 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2828 | _("Cannot extract return value of %d bytes long."), |
2829 | len); | |
c906108c SS |
2830 | } |
2831 | } | |
2832 | ||
c5e656c1 MK |
2833 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2834 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2835 | |
3a1e71e3 | 2836 | static void |
c5e656c1 | 2837 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2838 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2839 | { |
c5e656c1 | 2840 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2841 | int len = TYPE_LENGTH (type); |
2842 | ||
1e8d0a7b | 2843 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2844 | { |
3d7f4f49 | 2845 | ULONGEST fstat; |
63c0089f | 2846 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2847 | |
5716833c | 2848 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2849 | { |
8a3fe4f8 | 2850 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2851 | return; |
2852 | } | |
2853 | ||
635b0cc1 MK |
2854 | /* Returning floating-point values is a bit tricky. Apart from |
2855 | storing the return value in %st(0), we have to simulate the | |
2856 | state of the FPU at function return point. */ | |
2857 | ||
c6ba6f0d MK |
2858 | /* Convert the value found in VALBUF to the extended |
2859 | floating-point format used by the FPU. This is probably | |
2860 | not exactly how it would happen on the target itself, but | |
2861 | it is the best we can do. */ | |
3b2ca824 | 2862 | target_float_convert (valbuf, type, buf, i387_ext_type (gdbarch)); |
10eaee5f | 2863 | regcache->raw_write (I386_ST0_REGNUM, buf); |
ccb945b8 | 2864 | |
635b0cc1 MK |
2865 | /* Set the top of the floating-point register stack to 7. The |
2866 | actual value doesn't really matter, but 7 is what a normal | |
2867 | function return would end up with if the program started out | |
2868 | with a freshly initialized FPU. */ | |
20a6ec49 | 2869 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2870 | fstat |= (7 << 11); |
20a6ec49 | 2871 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2872 | |
635b0cc1 MK |
2873 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2874 | the floating-point register stack to 7, the appropriate value | |
2875 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2876 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2877 | } |
2878 | else | |
2879 | { | |
875f8d0e UW |
2880 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2881 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2882 | |
2883 | if (len <= low_size) | |
4f0420fd | 2884 | regcache->raw_write_part (LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2885 | else if (len <= (low_size + high_size)) |
2886 | { | |
10eaee5f | 2887 | regcache->raw_write (LOW_RETURN_REGNUM, valbuf); |
4f0420fd SM |
2888 | regcache->raw_write_part (HIGH_RETURN_REGNUM, 0, len - low_size, |
2889 | valbuf + low_size); | |
ef9dff19 MK |
2890 | } |
2891 | else | |
8e65ff28 | 2892 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2893 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2894 | } |
2895 | } | |
fc338970 | 2896 | \f |
ef9dff19 | 2897 | |
8201327c MK |
2898 | /* This is the variable that is set with "set struct-convention", and |
2899 | its legitimate values. */ | |
2900 | static const char default_struct_convention[] = "default"; | |
2901 | static const char pcc_struct_convention[] = "pcc"; | |
2902 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2903 | static const char *const valid_conventions[] = |
8201327c MK |
2904 | { |
2905 | default_struct_convention, | |
2906 | pcc_struct_convention, | |
2907 | reg_struct_convention, | |
2908 | NULL | |
2909 | }; | |
2910 | static const char *struct_convention = default_struct_convention; | |
2911 | ||
0e4377e1 JB |
2912 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2913 | a union type, or an array type, should be returned in registers | |
2914 | for architecture GDBARCH. */ | |
c5e656c1 | 2915 | |
8201327c | 2916 | static int |
c5e656c1 | 2917 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2918 | { |
c5e656c1 MK |
2919 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2920 | enum type_code code = TYPE_CODE (type); | |
2921 | int len = TYPE_LENGTH (type); | |
8201327c | 2922 | |
0e4377e1 JB |
2923 | gdb_assert (code == TYPE_CODE_STRUCT |
2924 | || code == TYPE_CODE_UNION | |
2925 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2926 | |
2927 | if (struct_convention == pcc_struct_convention | |
2928 | || (struct_convention == default_struct_convention | |
2929 | && tdep->struct_return == pcc_struct_return)) | |
2930 | return 0; | |
2931 | ||
9edde48e MK |
2932 | /* Structures consisting of a single `float', `double' or 'long |
2933 | double' member are returned in %st(0). */ | |
2934 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2935 | { | |
2936 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2937 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2938 | return (len == 4 || len == 8 || len == 12); | |
2939 | } | |
2940 | ||
c5e656c1 MK |
2941 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2942 | } | |
2943 | ||
2944 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2945 | should be returned. If it is supposed to be returned in registers, | |
2946 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2947 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2948 | from WRITEBUF into REGCACHE. */ | |
2949 | ||
2950 | static enum return_value_convention | |
6a3a010b | 2951 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2952 | struct type *type, struct regcache *regcache, |
2953 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2954 | { |
2955 | enum type_code code = TYPE_CODE (type); | |
2956 | ||
5daa78cc TJB |
2957 | if (((code == TYPE_CODE_STRUCT |
2958 | || code == TYPE_CODE_UNION | |
2959 | || code == TYPE_CODE_ARRAY) | |
2960 | && !i386_reg_struct_return_p (gdbarch, type)) | |
405feb71 | 2961 | /* Complex double and long double uses the struct return convention. */ |
2445fd7b MK |
2962 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) |
2963 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2964 | /* 128-bit decimal float uses the struct return convention. */ |
2965 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2966 | { |
2967 | /* The System V ABI says that: | |
2968 | ||
2969 | "A function that returns a structure or union also sets %eax | |
2970 | to the value of the original address of the caller's area | |
2971 | before it returns. Thus when the caller receives control | |
2972 | again, the address of the returned object resides in register | |
2973 | %eax and can be used to access the object." | |
2974 | ||
2975 | So the ABI guarantees that we can always find the return | |
2976 | value just after the function has returned. */ | |
2977 | ||
0e4377e1 JB |
2978 | /* Note that the ABI doesn't mention functions returning arrays, |
2979 | which is something possible in certain languages such as Ada. | |
2980 | In this case, the value is returned as if it was wrapped in | |
2981 | a record, so the convention applied to records also applies | |
2982 | to arrays. */ | |
2983 | ||
31db7b6c MK |
2984 | if (readbuf) |
2985 | { | |
2986 | ULONGEST addr; | |
2987 | ||
2988 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2989 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2990 | } | |
2991 | ||
2992 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2993 | } | |
c5e656c1 MK |
2994 | |
2995 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2996 | `float', `double' or 'long double' member. These structures are |
2997 | returned in %st(0). For these structures, we call ourselves | |
2998 | recursively, changing TYPE into the type of the first member of | |
2999 | the structure. Since that should work for all structures that | |
3000 | have only one member, we don't bother to check the member's type | |
3001 | here. */ | |
c5e656c1 MK |
3002 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
3003 | { | |
3004 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
6a3a010b | 3005 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 3006 | readbuf, writebuf); |
c5e656c1 MK |
3007 | } |
3008 | ||
3009 | if (readbuf) | |
3010 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
3011 | if (writebuf) | |
3012 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 3013 | |
c5e656c1 | 3014 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
3015 | } |
3016 | \f | |
3017 | ||
27067745 UW |
3018 | struct type * |
3019 | i387_ext_type (struct gdbarch *gdbarch) | |
3020 | { | |
3021 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3022 | ||
3023 | if (!tdep->i387_ext_type) | |
90884b2b L |
3024 | { |
3025 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
3026 | gdb_assert (tdep->i387_ext_type != NULL); | |
3027 | } | |
27067745 UW |
3028 | |
3029 | return tdep->i387_ext_type; | |
3030 | } | |
3031 | ||
1dbcd68c WT |
3032 | /* Construct type for pseudo BND registers. We can't use |
3033 | tdesc_find_type since a complement of one value has to be used | |
3034 | to describe the upper bound. */ | |
3035 | ||
3036 | static struct type * | |
3037 | i386_bnd_type (struct gdbarch *gdbarch) | |
3038 | { | |
3039 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3040 | ||
3041 | ||
3042 | if (!tdep->i386_bnd_type) | |
3043 | { | |
870f88f7 | 3044 | struct type *t; |
1dbcd68c WT |
3045 | const struct builtin_type *bt = builtin_type (gdbarch); |
3046 | ||
3047 | /* The type we're building is described bellow: */ | |
3048 | #if 0 | |
3049 | struct __bound128 | |
3050 | { | |
3051 | void *lbound; | |
3052 | void *ubound; /* One complement of raw ubound field. */ | |
3053 | }; | |
3054 | #endif | |
3055 | ||
3056 | t = arch_composite_type (gdbarch, | |
3057 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
3058 | ||
3059 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
3060 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
3061 | ||
3062 | TYPE_NAME (t) = "builtin_type_bound128"; | |
3063 | tdep->i386_bnd_type = t; | |
3064 | } | |
3065 | ||
3066 | return tdep->i386_bnd_type; | |
3067 | } | |
3068 | ||
01f9f808 MS |
3069 | /* Construct vector type for pseudo ZMM registers. We can't use |
3070 | tdesc_find_type since ZMM isn't described in target description. */ | |
3071 | ||
3072 | static struct type * | |
3073 | i386_zmm_type (struct gdbarch *gdbarch) | |
3074 | { | |
3075 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3076 | ||
3077 | if (!tdep->i386_zmm_type) | |
3078 | { | |
3079 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3080 | ||
3081 | /* The type we're building is this: */ | |
3082 | #if 0 | |
3083 | union __gdb_builtin_type_vec512i | |
3084 | { | |
3085 | int128_t uint128[4]; | |
3086 | int64_t v4_int64[8]; | |
3087 | int32_t v8_int32[16]; | |
3088 | int16_t v16_int16[32]; | |
3089 | int8_t v32_int8[64]; | |
3090 | double v4_double[8]; | |
3091 | float v8_float[16]; | |
3092 | }; | |
3093 | #endif | |
3094 | ||
3095 | struct type *t; | |
3096 | ||
3097 | t = arch_composite_type (gdbarch, | |
3098 | "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); | |
3099 | append_composite_type_field (t, "v16_float", | |
3100 | init_vector_type (bt->builtin_float, 16)); | |
3101 | append_composite_type_field (t, "v8_double", | |
3102 | init_vector_type (bt->builtin_double, 8)); | |
3103 | append_composite_type_field (t, "v64_int8", | |
3104 | init_vector_type (bt->builtin_int8, 64)); | |
3105 | append_composite_type_field (t, "v32_int16", | |
3106 | init_vector_type (bt->builtin_int16, 32)); | |
3107 | append_composite_type_field (t, "v16_int32", | |
3108 | init_vector_type (bt->builtin_int32, 16)); | |
3109 | append_composite_type_field (t, "v8_int64", | |
3110 | init_vector_type (bt->builtin_int64, 8)); | |
3111 | append_composite_type_field (t, "v4_int128", | |
3112 | init_vector_type (bt->builtin_int128, 4)); | |
3113 | ||
3114 | TYPE_VECTOR (t) = 1; | |
3115 | TYPE_NAME (t) = "builtin_type_vec512i"; | |
3116 | tdep->i386_zmm_type = t; | |
3117 | } | |
3118 | ||
3119 | return tdep->i386_zmm_type; | |
3120 | } | |
3121 | ||
c131fcee L |
3122 | /* Construct vector type for pseudo YMM registers. We can't use |
3123 | tdesc_find_type since YMM isn't described in target description. */ | |
3124 | ||
3125 | static struct type * | |
3126 | i386_ymm_type (struct gdbarch *gdbarch) | |
3127 | { | |
3128 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3129 | ||
3130 | if (!tdep->i386_ymm_type) | |
3131 | { | |
3132 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3133 | ||
3134 | /* The type we're building is this: */ | |
3135 | #if 0 | |
3136 | union __gdb_builtin_type_vec256i | |
3137 | { | |
3138 | int128_t uint128[2]; | |
3139 | int64_t v2_int64[4]; | |
3140 | int32_t v4_int32[8]; | |
3141 | int16_t v8_int16[16]; | |
3142 | int8_t v16_int8[32]; | |
3143 | double v2_double[4]; | |
3144 | float v4_float[8]; | |
3145 | }; | |
3146 | #endif | |
3147 | ||
3148 | struct type *t; | |
3149 | ||
3150 | t = arch_composite_type (gdbarch, | |
3151 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
3152 | append_composite_type_field (t, "v8_float", | |
3153 | init_vector_type (bt->builtin_float, 8)); | |
3154 | append_composite_type_field (t, "v4_double", | |
3155 | init_vector_type (bt->builtin_double, 4)); | |
3156 | append_composite_type_field (t, "v32_int8", | |
3157 | init_vector_type (bt->builtin_int8, 32)); | |
3158 | append_composite_type_field (t, "v16_int16", | |
3159 | init_vector_type (bt->builtin_int16, 16)); | |
3160 | append_composite_type_field (t, "v8_int32", | |
3161 | init_vector_type (bt->builtin_int32, 8)); | |
3162 | append_composite_type_field (t, "v4_int64", | |
3163 | init_vector_type (bt->builtin_int64, 4)); | |
3164 | append_composite_type_field (t, "v2_int128", | |
3165 | init_vector_type (bt->builtin_int128, 2)); | |
3166 | ||
3167 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 3168 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
3169 | tdep->i386_ymm_type = t; |
3170 | } | |
3171 | ||
3172 | return tdep->i386_ymm_type; | |
3173 | } | |
3174 | ||
794ac428 | 3175 | /* Construct vector type for MMX registers. */ |
90884b2b | 3176 | static struct type * |
794ac428 UW |
3177 | i386_mmx_type (struct gdbarch *gdbarch) |
3178 | { | |
3179 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3180 | ||
3181 | if (!tdep->i386_mmx_type) | |
3182 | { | |
df4df182 UW |
3183 | const struct builtin_type *bt = builtin_type (gdbarch); |
3184 | ||
794ac428 UW |
3185 | /* The type we're building is this: */ |
3186 | #if 0 | |
3187 | union __gdb_builtin_type_vec64i | |
3188 | { | |
3189 | int64_t uint64; | |
3190 | int32_t v2_int32[2]; | |
3191 | int16_t v4_int16[4]; | |
3192 | int8_t v8_int8[8]; | |
3193 | }; | |
3194 | #endif | |
3195 | ||
3196 | struct type *t; | |
3197 | ||
e9bb382b UW |
3198 | t = arch_composite_type (gdbarch, |
3199 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
3200 | |
3201 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 3202 | append_composite_type_field (t, "v2_int32", |
df4df182 | 3203 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 3204 | append_composite_type_field (t, "v4_int16", |
df4df182 | 3205 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 3206 | append_composite_type_field (t, "v8_int8", |
df4df182 | 3207 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 3208 | |
876cecd0 | 3209 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
3210 | TYPE_NAME (t) = "builtin_type_vec64i"; |
3211 | tdep->i386_mmx_type = t; | |
3212 | } | |
3213 | ||
3214 | return tdep->i386_mmx_type; | |
3215 | } | |
3216 | ||
d7a0d72c | 3217 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 3218 | register REGNUM. */ |
d7a0d72c | 3219 | |
fff4548b | 3220 | struct type * |
90884b2b | 3221 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 3222 | { |
1dbcd68c WT |
3223 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3224 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
3225 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
3226 | return i386_mmx_type (gdbarch); | |
c131fcee L |
3227 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
3228 | return i386_ymm_type (gdbarch); | |
01f9f808 MS |
3229 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3230 | return i386_ymm_type (gdbarch); | |
3231 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3232 | return i386_zmm_type (gdbarch); | |
1ba53b71 L |
3233 | else |
3234 | { | |
3235 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3236 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
3237 | return bt->builtin_int8; | |
3238 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3239 | return bt->builtin_int16; | |
3240 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
3241 | return bt->builtin_int32; | |
01f9f808 MS |
3242 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3243 | return bt->builtin_int64; | |
1ba53b71 L |
3244 | } |
3245 | ||
3246 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
3247 | } |
3248 | ||
28fc6740 | 3249 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 3250 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
3251 | |
3252 | static int | |
849d0ba8 | 3253 | i386_mmx_regnum_to_fp_regnum (readable_regcache *regcache, int regnum) |
28fc6740 | 3254 | { |
ac7936df | 3255 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
5716833c | 3256 | int mmxreg, fpreg; |
28fc6740 AC |
3257 | ULONGEST fstat; |
3258 | int tos; | |
c86c27af | 3259 | |
5716833c | 3260 | mmxreg = regnum - tdep->mm0_regnum; |
03f50fc8 | 3261 | regcache->raw_read (I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 3262 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
3263 | fpreg = (mmxreg + tos) % 8; |
3264 | ||
20a6ec49 | 3265 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
3266 | } |
3267 | ||
3543a589 TT |
3268 | /* A helper function for us by i386_pseudo_register_read_value and |
3269 | amd64_pseudo_register_read_value. It does all the work but reads | |
3270 | the data into an already-allocated value. */ | |
3271 | ||
3272 | void | |
3273 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
849d0ba8 | 3274 | readable_regcache *regcache, |
3543a589 TT |
3275 | int regnum, |
3276 | struct value *result_value) | |
28fc6740 | 3277 | { |
975c21ab | 3278 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
05d1431c | 3279 | enum register_status status; |
3543a589 | 3280 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 3281 | |
5716833c | 3282 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3283 | { |
c86c27af MK |
3284 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3285 | ||
28fc6740 | 3286 | /* Extract (always little endian). */ |
03f50fc8 | 3287 | status = regcache->raw_read (fpnum, raw_buf); |
05d1431c | 3288 | if (status != REG_VALID) |
3543a589 TT |
3289 | mark_value_bytes_unavailable (result_value, 0, |
3290 | TYPE_LENGTH (value_type (result_value))); | |
3291 | else | |
3292 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3293 | } |
3294 | else | |
1ba53b71 L |
3295 | { |
3296 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dbcd68c WT |
3297 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3298 | { | |
3299 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3300 | |
1dbcd68c | 3301 | /* Extract (always little endian). Read lower 128bits. */ |
03f50fc8 YQ |
3302 | status = regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum, |
3303 | raw_buf); | |
1dbcd68c WT |
3304 | if (status != REG_VALID) |
3305 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3306 | else | |
3307 | { | |
3308 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3309 | LONGEST upper, lower; | |
3310 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3311 | ||
3312 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3313 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3314 | upper = ~upper; | |
3315 | ||
3316 | memcpy (buf, &lower, size); | |
3317 | memcpy (buf + size, &upper, size); | |
3318 | } | |
3319 | } | |
01f9f808 MS |
3320 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3321 | { | |
3322 | regnum -= tdep->k0_regnum; | |
3323 | ||
3324 | /* Extract (always little endian). */ | |
03f50fc8 | 3325 | status = regcache->raw_read (tdep->k0_regnum + regnum, raw_buf); |
01f9f808 MS |
3326 | if (status != REG_VALID) |
3327 | mark_value_bytes_unavailable (result_value, 0, 8); | |
3328 | else | |
3329 | memcpy (buf, raw_buf, 8); | |
3330 | } | |
3331 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3332 | { | |
3333 | regnum -= tdep->zmm0_regnum; | |
3334 | ||
3335 | if (regnum < num_lower_zmm_regs) | |
3336 | { | |
3337 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3338 | status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum, |
3339 | raw_buf); | |
01f9f808 MS |
3340 | if (status != REG_VALID) |
3341 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3342 | else | |
3343 | memcpy (buf, raw_buf, 16); | |
3344 | ||
3345 | /* Extract (always little endian). Read upper 128bits. */ | |
03f50fc8 YQ |
3346 | status = regcache->raw_read (tdep->ymm0h_regnum + regnum, |
3347 | raw_buf); | |
01f9f808 MS |
3348 | if (status != REG_VALID) |
3349 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3350 | else | |
3351 | memcpy (buf + 16, raw_buf, 16); | |
3352 | } | |
3353 | else | |
3354 | { | |
3355 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3356 | status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum |
3357 | - num_lower_zmm_regs, | |
3358 | raw_buf); | |
01f9f808 MS |
3359 | if (status != REG_VALID) |
3360 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3361 | else | |
3362 | memcpy (buf, raw_buf, 16); | |
3363 | ||
3364 | /* Extract (always little endian). Read upper 128bits. */ | |
03f50fc8 YQ |
3365 | status = regcache->raw_read (I387_YMM16H_REGNUM (tdep) + regnum |
3366 | - num_lower_zmm_regs, | |
3367 | raw_buf); | |
01f9f808 MS |
3368 | if (status != REG_VALID) |
3369 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3370 | else | |
3371 | memcpy (buf + 16, raw_buf, 16); | |
3372 | } | |
3373 | ||
3374 | /* Read upper 256bits. */ | |
03f50fc8 YQ |
3375 | status = regcache->raw_read (tdep->zmm0h_regnum + regnum, |
3376 | raw_buf); | |
01f9f808 MS |
3377 | if (status != REG_VALID) |
3378 | mark_value_bytes_unavailable (result_value, 32, 32); | |
3379 | else | |
3380 | memcpy (buf + 32, raw_buf, 32); | |
3381 | } | |
1dbcd68c | 3382 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3383 | { |
3384 | regnum -= tdep->ymm0_regnum; | |
3385 | ||
1777feb0 | 3386 | /* Extract (always little endian). Read lower 128bits. */ |
03f50fc8 YQ |
3387 | status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum, |
3388 | raw_buf); | |
05d1431c | 3389 | if (status != REG_VALID) |
3543a589 TT |
3390 | mark_value_bytes_unavailable (result_value, 0, 16); |
3391 | else | |
3392 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3393 | /* Read upper 128bits. */ |
03f50fc8 YQ |
3394 | status = regcache->raw_read (tdep->ymm0h_regnum + regnum, |
3395 | raw_buf); | |
05d1431c | 3396 | if (status != REG_VALID) |
3543a589 TT |
3397 | mark_value_bytes_unavailable (result_value, 16, 32); |
3398 | else | |
3399 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee | 3400 | } |
01f9f808 MS |
3401 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3402 | { | |
3403 | regnum -= tdep->ymm16_regnum; | |
3404 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3405 | status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum, |
3406 | raw_buf); | |
01f9f808 MS |
3407 | if (status != REG_VALID) |
3408 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3409 | else | |
3410 | memcpy (buf, raw_buf, 16); | |
3411 | /* Read upper 128bits. */ | |
03f50fc8 YQ |
3412 | status = regcache->raw_read (tdep->ymm16h_regnum + regnum, |
3413 | raw_buf); | |
01f9f808 MS |
3414 | if (status != REG_VALID) |
3415 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3416 | else | |
3417 | memcpy (buf + 16, raw_buf, 16); | |
3418 | } | |
c131fcee | 3419 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3420 | { |
3421 | int gpnum = regnum - tdep->ax_regnum; | |
3422 | ||
3423 | /* Extract (always little endian). */ | |
03f50fc8 | 3424 | status = regcache->raw_read (gpnum, raw_buf); |
05d1431c | 3425 | if (status != REG_VALID) |
3543a589 TT |
3426 | mark_value_bytes_unavailable (result_value, 0, |
3427 | TYPE_LENGTH (value_type (result_value))); | |
3428 | else | |
3429 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3430 | } |
3431 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3432 | { | |
1ba53b71 L |
3433 | int gpnum = regnum - tdep->al_regnum; |
3434 | ||
3435 | /* Extract (always little endian). We read both lower and | |
3436 | upper registers. */ | |
03f50fc8 | 3437 | status = regcache->raw_read (gpnum % 4, raw_buf); |
05d1431c | 3438 | if (status != REG_VALID) |
3543a589 TT |
3439 | mark_value_bytes_unavailable (result_value, 0, |
3440 | TYPE_LENGTH (value_type (result_value))); | |
3441 | else if (gpnum >= 4) | |
1ba53b71 L |
3442 | memcpy (buf, raw_buf + 1, 1); |
3443 | else | |
3444 | memcpy (buf, raw_buf, 1); | |
3445 | } | |
3446 | else | |
3447 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3448 | } | |
3543a589 TT |
3449 | } |
3450 | ||
3451 | static struct value * | |
3452 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
849d0ba8 | 3453 | readable_regcache *regcache, |
3543a589 TT |
3454 | int regnum) |
3455 | { | |
3456 | struct value *result; | |
3457 | ||
3458 | result = allocate_value (register_type (gdbarch, regnum)); | |
3459 | VALUE_LVAL (result) = lval_register; | |
3460 | VALUE_REGNUM (result) = regnum; | |
3461 | ||
3462 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3463 | |
3543a589 | 3464 | return result; |
28fc6740 AC |
3465 | } |
3466 | ||
1ba53b71 | 3467 | void |
28fc6740 | 3468 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3469 | int regnum, const gdb_byte *buf) |
28fc6740 | 3470 | { |
975c21ab | 3471 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
1ba53b71 | 3472 | |
5716833c | 3473 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3474 | { |
c86c27af MK |
3475 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3476 | ||
28fc6740 | 3477 | /* Read ... */ |
0b883586 | 3478 | regcache->raw_read (fpnum, raw_buf); |
28fc6740 | 3479 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3480 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3481 | /* ... Write. */ |
10eaee5f | 3482 | regcache->raw_write (fpnum, raw_buf); |
28fc6740 AC |
3483 | } |
3484 | else | |
1ba53b71 L |
3485 | { |
3486 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3487 | ||
1dbcd68c WT |
3488 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3489 | { | |
3490 | ULONGEST upper, lower; | |
3491 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3492 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3493 | ||
3494 | /* New values from input value. */ | |
3495 | regnum -= tdep->bnd0_regnum; | |
3496 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3497 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3498 | ||
3499 | /* Fetching register buffer. */ | |
0b883586 SM |
3500 | regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum, |
3501 | raw_buf); | |
1dbcd68c WT |
3502 | |
3503 | upper = ~upper; | |
3504 | ||
3505 | /* Set register bits. */ | |
3506 | memcpy (raw_buf, &lower, 8); | |
3507 | memcpy (raw_buf + 8, &upper, 8); | |
3508 | ||
10eaee5f | 3509 | regcache->raw_write (I387_BND0R_REGNUM (tdep) + regnum, raw_buf); |
1dbcd68c | 3510 | } |
01f9f808 MS |
3511 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3512 | { | |
3513 | regnum -= tdep->k0_regnum; | |
3514 | ||
10eaee5f | 3515 | regcache->raw_write (tdep->k0_regnum + regnum, buf); |
01f9f808 MS |
3516 | } |
3517 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3518 | { | |
3519 | regnum -= tdep->zmm0_regnum; | |
3520 | ||
3521 | if (regnum < num_lower_zmm_regs) | |
3522 | { | |
3523 | /* Write lower 128bits. */ | |
10eaee5f | 3524 | regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf); |
01f9f808 | 3525 | /* Write upper 128bits. */ |
10eaee5f | 3526 | regcache->raw_write (I387_YMM0_REGNUM (tdep) + regnum, buf + 16); |
01f9f808 MS |
3527 | } |
3528 | else | |
3529 | { | |
3530 | /* Write lower 128bits. */ | |
10eaee5f SM |
3531 | regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum |
3532 | - num_lower_zmm_regs, buf); | |
01f9f808 | 3533 | /* Write upper 128bits. */ |
10eaee5f SM |
3534 | regcache->raw_write (I387_YMM16H_REGNUM (tdep) + regnum |
3535 | - num_lower_zmm_regs, buf + 16); | |
01f9f808 MS |
3536 | } |
3537 | /* Write upper 256bits. */ | |
10eaee5f | 3538 | regcache->raw_write (tdep->zmm0h_regnum + regnum, buf + 32); |
01f9f808 | 3539 | } |
1dbcd68c | 3540 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3541 | { |
3542 | regnum -= tdep->ymm0_regnum; | |
3543 | ||
3544 | /* ... Write lower 128bits. */ | |
10eaee5f | 3545 | regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf); |
c131fcee | 3546 | /* ... Write upper 128bits. */ |
10eaee5f | 3547 | regcache->raw_write (tdep->ymm0h_regnum + regnum, buf + 16); |
c131fcee | 3548 | } |
01f9f808 MS |
3549 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3550 | { | |
3551 | regnum -= tdep->ymm16_regnum; | |
3552 | ||
3553 | /* ... Write lower 128bits. */ | |
10eaee5f | 3554 | regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum, buf); |
01f9f808 | 3555 | /* ... Write upper 128bits. */ |
10eaee5f | 3556 | regcache->raw_write (tdep->ymm16h_regnum + regnum, buf + 16); |
01f9f808 | 3557 | } |
c131fcee | 3558 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3559 | { |
3560 | int gpnum = regnum - tdep->ax_regnum; | |
3561 | ||
3562 | /* Read ... */ | |
0b883586 | 3563 | regcache->raw_read (gpnum, raw_buf); |
1ba53b71 L |
3564 | /* ... Modify ... (always little endian). */ |
3565 | memcpy (raw_buf, buf, 2); | |
3566 | /* ... Write. */ | |
10eaee5f | 3567 | regcache->raw_write (gpnum, raw_buf); |
1ba53b71 L |
3568 | } |
3569 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3570 | { | |
1ba53b71 L |
3571 | int gpnum = regnum - tdep->al_regnum; |
3572 | ||
3573 | /* Read ... We read both lower and upper registers. */ | |
0b883586 | 3574 | regcache->raw_read (gpnum % 4, raw_buf); |
1ba53b71 L |
3575 | /* ... Modify ... (always little endian). */ |
3576 | if (gpnum >= 4) | |
3577 | memcpy (raw_buf + 1, buf, 1); | |
3578 | else | |
3579 | memcpy (raw_buf, buf, 1); | |
3580 | /* ... Write. */ | |
10eaee5f | 3581 | regcache->raw_write (gpnum % 4, raw_buf); |
1ba53b71 L |
3582 | } |
3583 | else | |
3584 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3585 | } | |
28fc6740 | 3586 | } |
62e5fd57 MK |
3587 | |
3588 | /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ | |
3589 | ||
3590 | int | |
3591 | i386_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3592 | struct agent_expr *ax, int regnum) | |
3593 | { | |
3594 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3595 | ||
3596 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
3597 | { | |
3598 | /* MMX to FPU register mapping depends on current TOS. Let's just | |
3599 | not care and collect everything... */ | |
3600 | int i; | |
3601 | ||
3602 | ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep)); | |
3603 | for (i = 0; i < 8; i++) | |
3604 | ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i); | |
3605 | return 0; | |
3606 | } | |
3607 | else if (i386_bnd_regnum_p (gdbarch, regnum)) | |
3608 | { | |
3609 | regnum -= tdep->bnd0_regnum; | |
3610 | ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum); | |
3611 | return 0; | |
3612 | } | |
3613 | else if (i386_k_regnum_p (gdbarch, regnum)) | |
3614 | { | |
3615 | regnum -= tdep->k0_regnum; | |
3616 | ax_reg_mask (ax, tdep->k0_regnum + regnum); | |
3617 | return 0; | |
3618 | } | |
3619 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3620 | { | |
3621 | regnum -= tdep->zmm0_regnum; | |
3622 | if (regnum < num_lower_zmm_regs) | |
3623 | { | |
3624 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3625 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3626 | } | |
3627 | else | |
3628 | { | |
3629 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum | |
3630 | - num_lower_zmm_regs); | |
3631 | ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum | |
3632 | - num_lower_zmm_regs); | |
3633 | } | |
3634 | ax_reg_mask (ax, tdep->zmm0h_regnum + regnum); | |
3635 | return 0; | |
3636 | } | |
3637 | else if (i386_ymm_regnum_p (gdbarch, regnum)) | |
3638 | { | |
3639 | regnum -= tdep->ymm0_regnum; | |
3640 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3641 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3642 | return 0; | |
3643 | } | |
3644 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) | |
3645 | { | |
3646 | regnum -= tdep->ymm16_regnum; | |
3647 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum); | |
3648 | ax_reg_mask (ax, tdep->ymm16h_regnum + regnum); | |
3649 | return 0; | |
3650 | } | |
3651 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3652 | { | |
3653 | int gpnum = regnum - tdep->ax_regnum; | |
3654 | ||
3655 | ax_reg_mask (ax, gpnum); | |
3656 | return 0; | |
3657 | } | |
3658 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3659 | { | |
3660 | int gpnum = regnum - tdep->al_regnum; | |
3661 | ||
3662 | ax_reg_mask (ax, gpnum % 4); | |
3663 | return 0; | |
3664 | } | |
3665 | else | |
3666 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3667 | return 1; | |
3668 | } | |
ff2e87ac AC |
3669 | \f |
3670 | ||
ff2e87ac AC |
3671 | /* Return the register number of the register allocated by GCC after |
3672 | REGNUM, or -1 if there is no such register. */ | |
3673 | ||
3674 | static int | |
3675 | i386_next_regnum (int regnum) | |
3676 | { | |
3677 | /* GCC allocates the registers in the order: | |
3678 | ||
3679 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3680 | ||
3681 | Since storing a variable in %esp doesn't make any sense we return | |
3682 | -1 for %ebp and for %esp itself. */ | |
3683 | static int next_regnum[] = | |
3684 | { | |
3685 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3686 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3687 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3688 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3689 | -1, -1, /* Slots for %esp and %ebp. */ | |
3690 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3691 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3692 | }; | |
3693 | ||
de5b9bb9 | 3694 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3695 | return next_regnum[regnum]; |
28fc6740 | 3696 | |
ff2e87ac AC |
3697 | return -1; |
3698 | } | |
3699 | ||
3700 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3701 | needs any special handling. */ | |
d7a0d72c | 3702 | |
3a1e71e3 | 3703 | static int |
1777feb0 MS |
3704 | i386_convert_register_p (struct gdbarch *gdbarch, |
3705 | int regnum, struct type *type) | |
d7a0d72c | 3706 | { |
de5b9bb9 MK |
3707 | int len = TYPE_LENGTH (type); |
3708 | ||
ff2e87ac AC |
3709 | /* Values may be spread across multiple registers. Most debugging |
3710 | formats aren't expressive enough to specify the locations, so | |
3711 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3712 | have a length that is a multiple of the word size, since GCC |
3713 | doesn't seem to put any other types into registers. */ | |
3714 | if (len > 4 && len % 4 == 0) | |
3715 | { | |
3716 | int last_regnum = regnum; | |
3717 | ||
3718 | while (len > 4) | |
3719 | { | |
3720 | last_regnum = i386_next_regnum (last_regnum); | |
3721 | len -= 4; | |
3722 | } | |
3723 | ||
3724 | if (last_regnum != -1) | |
3725 | return 1; | |
3726 | } | |
ff2e87ac | 3727 | |
0abe36f5 | 3728 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3729 | } |
3730 | ||
ff2e87ac AC |
3731 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3732 | return its contents in TO. */ | |
ac27f131 | 3733 | |
8dccd430 | 3734 | static int |
ff2e87ac | 3735 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3736 | struct type *type, gdb_byte *to, |
3737 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3738 | { |
20a6ec49 | 3739 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3740 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3741 | |
20a6ec49 | 3742 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3743 | return i387_register_to_value (frame, regnum, type, to, |
3744 | optimizedp, unavailablep); | |
ff2e87ac | 3745 | |
fd35795f | 3746 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3747 | |
3748 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3749 | |
de5b9bb9 MK |
3750 | while (len > 0) |
3751 | { | |
3752 | gdb_assert (regnum != -1); | |
20a6ec49 | 3753 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3754 | |
8dccd430 PA |
3755 | if (!get_frame_register_bytes (frame, regnum, 0, |
3756 | register_size (gdbarch, regnum), | |
3757 | to, optimizedp, unavailablep)) | |
3758 | return 0; | |
3759 | ||
de5b9bb9 MK |
3760 | regnum = i386_next_regnum (regnum); |
3761 | len -= 4; | |
42835c2b | 3762 | to += 4; |
de5b9bb9 | 3763 | } |
8dccd430 PA |
3764 | |
3765 | *optimizedp = *unavailablep = 0; | |
3766 | return 1; | |
ac27f131 MK |
3767 | } |
3768 | ||
ff2e87ac AC |
3769 | /* Write the contents FROM of a value of type TYPE into register |
3770 | REGNUM in frame FRAME. */ | |
ac27f131 | 3771 | |
3a1e71e3 | 3772 | static void |
ff2e87ac | 3773 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3774 | struct type *type, const gdb_byte *from) |
ac27f131 | 3775 | { |
de5b9bb9 | 3776 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3777 | |
20a6ec49 | 3778 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3779 | { |
d532c08f MK |
3780 | i387_value_to_register (frame, regnum, type, from); |
3781 | return; | |
3782 | } | |
3d261580 | 3783 | |
fd35795f | 3784 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3785 | |
3786 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3787 | |
de5b9bb9 MK |
3788 | while (len > 0) |
3789 | { | |
3790 | gdb_assert (regnum != -1); | |
875f8d0e | 3791 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3792 | |
42835c2b | 3793 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3794 | regnum = i386_next_regnum (regnum); |
3795 | len -= 4; | |
42835c2b | 3796 | from += 4; |
de5b9bb9 | 3797 | } |
ac27f131 | 3798 | } |
ff2e87ac | 3799 | \f |
7fdafb5a MK |
3800 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3801 | in the general-purpose register set REGSET to register cache | |
3802 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3803 | |
20187ed5 | 3804 | void |
473f17b0 MK |
3805 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3806 | int regnum, const void *gregs, size_t len) | |
3807 | { | |
ac7936df | 3808 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3809 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9a3c8263 | 3810 | const gdb_byte *regs = (const gdb_byte *) gregs; |
473f17b0 MK |
3811 | int i; |
3812 | ||
1528345d | 3813 | gdb_assert (len >= tdep->sizeof_gregset); |
473f17b0 MK |
3814 | |
3815 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3816 | { | |
3817 | if ((regnum == i || regnum == -1) | |
3818 | && tdep->gregset_reg_offset[i] != -1) | |
73e1c03f | 3819 | regcache->raw_supply (i, regs + tdep->gregset_reg_offset[i]); |
473f17b0 MK |
3820 | } |
3821 | } | |
3822 | ||
7fdafb5a MK |
3823 | /* Collect register REGNUM from the register cache REGCACHE and store |
3824 | it in the buffer specified by GREGS and LEN as described by the | |
3825 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3826 | all registers in REGSET. */ | |
3827 | ||
ecc37a5a | 3828 | static void |
7fdafb5a MK |
3829 | i386_collect_gregset (const struct regset *regset, |
3830 | const struct regcache *regcache, | |
3831 | int regnum, void *gregs, size_t len) | |
3832 | { | |
ac7936df | 3833 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3834 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9a3c8263 | 3835 | gdb_byte *regs = (gdb_byte *) gregs; |
7fdafb5a MK |
3836 | int i; |
3837 | ||
1528345d | 3838 | gdb_assert (len >= tdep->sizeof_gregset); |
7fdafb5a MK |
3839 | |
3840 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3841 | { | |
3842 | if ((regnum == i || regnum == -1) | |
3843 | && tdep->gregset_reg_offset[i] != -1) | |
34a79281 | 3844 | regcache->raw_collect (i, regs + tdep->gregset_reg_offset[i]); |
7fdafb5a MK |
3845 | } |
3846 | } | |
3847 | ||
3848 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3849 | in the floating-point register set REGSET to register cache | |
3850 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3851 | |
3852 | static void | |
3853 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3854 | int regnum, const void *fpregs, size_t len) | |
3855 | { | |
ac7936df | 3856 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3857 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
473f17b0 | 3858 | |
66a72d25 MK |
3859 | if (len == I387_SIZEOF_FXSAVE) |
3860 | { | |
3861 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3862 | return; | |
3863 | } | |
3864 | ||
1528345d | 3865 | gdb_assert (len >= tdep->sizeof_fpregset); |
473f17b0 MK |
3866 | i387_supply_fsave (regcache, regnum, fpregs); |
3867 | } | |
8446b36a | 3868 | |
2f305df1 MK |
3869 | /* Collect register REGNUM from the register cache REGCACHE and store |
3870 | it in the buffer specified by FPREGS and LEN as described by the | |
3871 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3872 | all registers in REGSET. */ | |
7fdafb5a MK |
3873 | |
3874 | static void | |
3875 | i386_collect_fpregset (const struct regset *regset, | |
3876 | const struct regcache *regcache, | |
3877 | int regnum, void *fpregs, size_t len) | |
3878 | { | |
ac7936df | 3879 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3880 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7fdafb5a MK |
3881 | |
3882 | if (len == I387_SIZEOF_FXSAVE) | |
3883 | { | |
3884 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3885 | return; | |
3886 | } | |
3887 | ||
1528345d | 3888 | gdb_assert (len >= tdep->sizeof_fpregset); |
7fdafb5a MK |
3889 | i387_collect_fsave (regcache, regnum, fpregs); |
3890 | } | |
3891 | ||
ecc37a5a AA |
3892 | /* Register set definitions. */ |
3893 | ||
3894 | const struct regset i386_gregset = | |
3895 | { | |
3896 | NULL, i386_supply_gregset, i386_collect_gregset | |
3897 | }; | |
3898 | ||
8f0435f7 | 3899 | const struct regset i386_fpregset = |
ecc37a5a AA |
3900 | { |
3901 | NULL, i386_supply_fpregset, i386_collect_fpregset | |
3902 | }; | |
3903 | ||
490496c3 | 3904 | /* Default iterator over core file register note sections. */ |
8446b36a | 3905 | |
490496c3 AA |
3906 | void |
3907 | i386_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
3908 | iterate_over_regset_sections_cb *cb, | |
3909 | void *cb_data, | |
3910 | const struct regcache *regcache) | |
8446b36a MK |
3911 | { |
3912 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3913 | ||
a616bb94 AH |
3914 | cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, &i386_gregset, NULL, |
3915 | cb_data); | |
490496c3 | 3916 | if (tdep->sizeof_fpregset) |
a616bb94 AH |
3917 | cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, |
3918 | NULL, cb_data); | |
8446b36a | 3919 | } |
473f17b0 | 3920 | \f |
fc338970 | 3921 | |
fc338970 | 3922 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3923 | |
3924 | CORE_ADDR | |
e17a4113 UW |
3925 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3926 | CORE_ADDR pc, char *name) | |
c906108c | 3927 | { |
e17a4113 UW |
3928 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3929 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3930 | ||
3931 | /* jmp *(dest) */ | |
3932 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3933 | { |
e17a4113 UW |
3934 | unsigned long indirect = |
3935 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3936 | struct minimal_symbol *indsym = |
7cbd4a93 | 3937 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
c9d95fa3 | 3938 | const char *symname = indsym ? indsym->linkage_name () : 0; |
c906108c | 3939 | |
c5aa993b | 3940 | if (symname) |
c906108c | 3941 | { |
61012eef GB |
3942 | if (startswith (symname, "__imp_") |
3943 | || startswith (symname, "_imp_")) | |
e17a4113 UW |
3944 | return name ? 1 : |
3945 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3946 | } |
3947 | } | |
fc338970 | 3948 | return 0; /* Not a trampoline. */ |
c906108c | 3949 | } |
fc338970 MK |
3950 | \f |
3951 | ||
10458914 DJ |
3952 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3953 | routine. */ | |
8201327c | 3954 | |
4bd207ef | 3955 | int |
10458914 | 3956 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3957 | { |
10458914 | 3958 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3959 | const char *name; |
911bc6ee MK |
3960 | |
3961 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3962 | return (name && strcmp ("_sigtramp", name) == 0); |
3963 | } | |
3964 | \f | |
3965 | ||
fc338970 MK |
3966 | /* We have two flavours of disassembly. The machinery on this page |
3967 | deals with switching between those. */ | |
c906108c SS |
3968 | |
3969 | static int | |
a89aa300 | 3970 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3971 | { |
5e3397bb MK |
3972 | gdb_assert (disassembly_flavor == att_flavor |
3973 | || disassembly_flavor == intel_flavor); | |
3974 | ||
f995bbe8 | 3975 | info->disassembler_options = disassembly_flavor; |
5e3397bb | 3976 | |
6394c606 | 3977 | return default_print_insn (pc, info); |
7a292a7a | 3978 | } |
fc338970 | 3979 | \f |
3ce1502b | 3980 | |
8201327c MK |
3981 | /* There are a few i386 architecture variants that differ only |
3982 | slightly from the generic i386 target. For now, we don't give them | |
3983 | their own source file, but include them here. As a consequence, | |
3984 | they'll always be included. */ | |
3ce1502b | 3985 | |
8201327c | 3986 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3987 | |
10458914 DJ |
3988 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3989 | routine. */ | |
911bc6ee | 3990 | |
8201327c | 3991 | static int |
10458914 | 3992 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3993 | { |
10458914 | 3994 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3995 | const char *name; |
911bc6ee | 3996 | |
05b4bd79 | 3997 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 3998 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 3999 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
4000 | || strcmp ("sigvechandler", name) == 0)); |
4001 | } | |
d2a7c97a | 4002 | |
10458914 DJ |
4003 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
4004 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 4005 | |
3a1e71e3 | 4006 | static CORE_ADDR |
10458914 | 4007 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 4008 | { |
e17a4113 UW |
4009 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
4010 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 4011 | gdb_byte buf[4]; |
acd5c798 | 4012 | CORE_ADDR sp; |
3ce1502b | 4013 | |
10458914 | 4014 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 4015 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 4016 | |
e17a4113 | 4017 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 4018 | } |
55aa24fb SDJ |
4019 | |
4020 | \f | |
4021 | ||
4022 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
4023 | gdbarch.h. */ | |
4024 | ||
4025 | int | |
4026 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
4027 | { | |
4028 | return (*s == '$' /* Literal number. */ | |
4029 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
4030 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
4031 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
4032 | } | |
4033 | ||
5acfdbae SDJ |
4034 | /* Helper function for i386_stap_parse_special_token. |
4035 | ||
4036 | This function parses operands of the form `-8+3+1(%rbp)', which | |
4037 | must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. | |
4038 | ||
af2d9bee | 4039 | Return true if the operand was parsed successfully, false |
5acfdbae SDJ |
4040 | otherwise. */ |
4041 | ||
af2d9bee | 4042 | static bool |
5acfdbae SDJ |
4043 | i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, |
4044 | struct stap_parse_info *p) | |
4045 | { | |
4046 | const char *s = p->arg; | |
4047 | ||
4048 | if (isdigit (*s) || *s == '-' || *s == '+') | |
4049 | { | |
af2d9bee | 4050 | bool got_minus[3]; |
5acfdbae SDJ |
4051 | int i; |
4052 | long displacements[3]; | |
4053 | const char *start; | |
4054 | char *regname; | |
4055 | int len; | |
4056 | struct stoken str; | |
4057 | char *endp; | |
4058 | ||
af2d9bee | 4059 | got_minus[0] = false; |
5acfdbae SDJ |
4060 | if (*s == '+') |
4061 | ++s; | |
4062 | else if (*s == '-') | |
4063 | { | |
4064 | ++s; | |
af2d9bee | 4065 | got_minus[0] = true; |
5acfdbae SDJ |
4066 | } |
4067 | ||
d7b30f67 | 4068 | if (!isdigit ((unsigned char) *s)) |
af2d9bee | 4069 | return false; |
d7b30f67 | 4070 | |
5acfdbae SDJ |
4071 | displacements[0] = strtol (s, &endp, 10); |
4072 | s = endp; | |
4073 | ||
4074 | if (*s != '+' && *s != '-') | |
4075 | { | |
4076 | /* We are not dealing with a triplet. */ | |
af2d9bee | 4077 | return false; |
5acfdbae SDJ |
4078 | } |
4079 | ||
af2d9bee | 4080 | got_minus[1] = false; |
5acfdbae SDJ |
4081 | if (*s == '+') |
4082 | ++s; | |
4083 | else | |
4084 | { | |
4085 | ++s; | |
af2d9bee | 4086 | got_minus[1] = true; |
5acfdbae SDJ |
4087 | } |
4088 | ||
d7b30f67 | 4089 | if (!isdigit ((unsigned char) *s)) |
af2d9bee | 4090 | return false; |
d7b30f67 | 4091 | |
5acfdbae SDJ |
4092 | displacements[1] = strtol (s, &endp, 10); |
4093 | s = endp; | |
4094 | ||
4095 | if (*s != '+' && *s != '-') | |
4096 | { | |
4097 | /* We are not dealing with a triplet. */ | |
af2d9bee | 4098 | return false; |
5acfdbae SDJ |
4099 | } |
4100 | ||
af2d9bee | 4101 | got_minus[2] = false; |
5acfdbae SDJ |
4102 | if (*s == '+') |
4103 | ++s; | |
4104 | else | |
4105 | { | |
4106 | ++s; | |
af2d9bee | 4107 | got_minus[2] = true; |
5acfdbae SDJ |
4108 | } |
4109 | ||
d7b30f67 | 4110 | if (!isdigit ((unsigned char) *s)) |
af2d9bee | 4111 | return false; |
d7b30f67 | 4112 | |
5acfdbae SDJ |
4113 | displacements[2] = strtol (s, &endp, 10); |
4114 | s = endp; | |
4115 | ||
4116 | if (*s != '(' || s[1] != '%') | |
af2d9bee | 4117 | return false; |
5acfdbae SDJ |
4118 | |
4119 | s += 2; | |
4120 | start = s; | |
4121 | ||
4122 | while (isalnum (*s)) | |
4123 | ++s; | |
4124 | ||
4125 | if (*s++ != ')') | |
af2d9bee | 4126 | return false; |
5acfdbae | 4127 | |
d7b30f67 | 4128 | len = s - start - 1; |
224c3ddb | 4129 | regname = (char *) alloca (len + 1); |
5acfdbae SDJ |
4130 | |
4131 | strncpy (regname, start, len); | |
4132 | regname[len] = '\0'; | |
4133 | ||
4134 | if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1) | |
4135 | error (_("Invalid register name `%s' on expression `%s'."), | |
4136 | regname, p->saved_arg); | |
4137 | ||
4138 | for (i = 0; i < 3; i++) | |
4139 | { | |
410a0ff2 SDJ |
4140 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4141 | write_exp_elt_type | |
4142 | (&p->pstate, builtin_type (gdbarch)->builtin_long); | |
4143 | write_exp_elt_longcst (&p->pstate, displacements[i]); | |
4144 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4145 | if (got_minus[i]) |
410a0ff2 | 4146 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4147 | } |
4148 | ||
410a0ff2 | 4149 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4150 | str.ptr = regname; |
4151 | str.length = len; | |
410a0ff2 SDJ |
4152 | write_exp_string (&p->pstate, str); |
4153 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae | 4154 | |
410a0ff2 SDJ |
4155 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4156 | write_exp_elt_type (&p->pstate, | |
4157 | builtin_type (gdbarch)->builtin_data_ptr); | |
4158 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4159 | |
410a0ff2 SDJ |
4160 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
4161 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
4162 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
5acfdbae | 4163 | |
410a0ff2 SDJ |
4164 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4165 | write_exp_elt_type (&p->pstate, | |
4166 | lookup_pointer_type (p->arg_type)); | |
4167 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4168 | |
410a0ff2 | 4169 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4170 | |
4171 | p->arg = s; | |
4172 | ||
af2d9bee | 4173 | return true; |
5acfdbae SDJ |
4174 | } |
4175 | ||
af2d9bee | 4176 | return false; |
5acfdbae SDJ |
4177 | } |
4178 | ||
4179 | /* Helper function for i386_stap_parse_special_token. | |
4180 | ||
4181 | This function parses operands of the form `register base + | |
4182 | (register index * size) + offset', as represented in | |
4183 | `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4184 | ||
af2d9bee | 4185 | Return true if the operand was parsed successfully, false |
5acfdbae SDJ |
4186 | otherwise. */ |
4187 | ||
af2d9bee | 4188 | static bool |
5acfdbae SDJ |
4189 | i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, |
4190 | struct stap_parse_info *p) | |
4191 | { | |
4192 | const char *s = p->arg; | |
4193 | ||
4194 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
4195 | { | |
af2d9bee | 4196 | bool offset_minus = false; |
5acfdbae | 4197 | long offset = 0; |
af2d9bee | 4198 | bool size_minus = false; |
5acfdbae SDJ |
4199 | long size = 0; |
4200 | const char *start; | |
4201 | char *base; | |
4202 | int len_base; | |
4203 | char *index; | |
4204 | int len_index; | |
4205 | struct stoken base_token, index_token; | |
4206 | ||
4207 | if (*s == '+') | |
4208 | ++s; | |
4209 | else if (*s == '-') | |
4210 | { | |
4211 | ++s; | |
af2d9bee | 4212 | offset_minus = true; |
5acfdbae SDJ |
4213 | } |
4214 | ||
4215 | if (offset_minus && !isdigit (*s)) | |
af2d9bee | 4216 | return false; |
5acfdbae SDJ |
4217 | |
4218 | if (isdigit (*s)) | |
4219 | { | |
4220 | char *endp; | |
4221 | ||
4222 | offset = strtol (s, &endp, 10); | |
4223 | s = endp; | |
4224 | } | |
4225 | ||
4226 | if (*s != '(' || s[1] != '%') | |
af2d9bee | 4227 | return false; |
5acfdbae SDJ |
4228 | |
4229 | s += 2; | |
4230 | start = s; | |
4231 | ||
4232 | while (isalnum (*s)) | |
4233 | ++s; | |
4234 | ||
4235 | if (*s != ',' || s[1] != '%') | |
af2d9bee | 4236 | return false; |
5acfdbae SDJ |
4237 | |
4238 | len_base = s - start; | |
224c3ddb | 4239 | base = (char *) alloca (len_base + 1); |
5acfdbae SDJ |
4240 | strncpy (base, start, len_base); |
4241 | base[len_base] = '\0'; | |
4242 | ||
4243 | if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1) | |
4244 | error (_("Invalid register name `%s' on expression `%s'."), | |
4245 | base, p->saved_arg); | |
4246 | ||
4247 | s += 2; | |
4248 | start = s; | |
4249 | ||
4250 | while (isalnum (*s)) | |
4251 | ++s; | |
4252 | ||
4253 | len_index = s - start; | |
224c3ddb | 4254 | index = (char *) alloca (len_index + 1); |
5acfdbae SDJ |
4255 | strncpy (index, start, len_index); |
4256 | index[len_index] = '\0'; | |
4257 | ||
4258 | if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1) | |
4259 | error (_("Invalid register name `%s' on expression `%s'."), | |
4260 | index, p->saved_arg); | |
4261 | ||
4262 | if (*s != ',' && *s != ')') | |
af2d9bee | 4263 | return false; |
5acfdbae SDJ |
4264 | |
4265 | if (*s == ',') | |
4266 | { | |
4267 | char *endp; | |
4268 | ||
4269 | ++s; | |
4270 | if (*s == '+') | |
4271 | ++s; | |
4272 | else if (*s == '-') | |
4273 | { | |
4274 | ++s; | |
af2d9bee | 4275 | size_minus = true; |
5acfdbae SDJ |
4276 | } |
4277 | ||
4278 | size = strtol (s, &endp, 10); | |
4279 | s = endp; | |
4280 | ||
4281 | if (*s != ')') | |
af2d9bee | 4282 | return false; |
5acfdbae SDJ |
4283 | } |
4284 | ||
4285 | ++s; | |
4286 | ||
4287 | if (offset) | |
4288 | { | |
410a0ff2 SDJ |
4289 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4290 | write_exp_elt_type (&p->pstate, | |
4291 | builtin_type (gdbarch)->builtin_long); | |
4292 | write_exp_elt_longcst (&p->pstate, offset); | |
4293 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4294 | if (offset_minus) |
410a0ff2 | 4295 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4296 | } |
4297 | ||
410a0ff2 | 4298 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4299 | base_token.ptr = base; |
4300 | base_token.length = len_base; | |
410a0ff2 SDJ |
4301 | write_exp_string (&p->pstate, base_token); |
4302 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4303 | |
4304 | if (offset) | |
410a0ff2 | 4305 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4306 | |
410a0ff2 | 4307 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4308 | index_token.ptr = index; |
4309 | index_token.length = len_index; | |
410a0ff2 SDJ |
4310 | write_exp_string (&p->pstate, index_token); |
4311 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4312 | |
4313 | if (size) | |
4314 | { | |
410a0ff2 SDJ |
4315 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4316 | write_exp_elt_type (&p->pstate, | |
4317 | builtin_type (gdbarch)->builtin_long); | |
4318 | write_exp_elt_longcst (&p->pstate, size); | |
4319 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4320 | if (size_minus) |
410a0ff2 SDJ |
4321 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
4322 | write_exp_elt_opcode (&p->pstate, BINOP_MUL); | |
5acfdbae SDJ |
4323 | } |
4324 | ||
410a0ff2 | 4325 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4326 | |
410a0ff2 SDJ |
4327 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4328 | write_exp_elt_type (&p->pstate, | |
4329 | lookup_pointer_type (p->arg_type)); | |
4330 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4331 | |
410a0ff2 | 4332 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4333 | |
4334 | p->arg = s; | |
4335 | ||
af2d9bee | 4336 | return true; |
5acfdbae SDJ |
4337 | } |
4338 | ||
af2d9bee | 4339 | return false; |
5acfdbae SDJ |
4340 | } |
4341 | ||
55aa24fb SDJ |
4342 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in |
4343 | gdbarch.h. */ | |
4344 | ||
4345 | int | |
4346 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
4347 | struct stap_parse_info *p) | |
4348 | { | |
55aa24fb SDJ |
4349 | /* In order to parse special tokens, we use a state-machine that go |
4350 | through every known token and try to get a match. */ | |
4351 | enum | |
4352 | { | |
4353 | TRIPLET, | |
4354 | THREE_ARG_DISPLACEMENT, | |
4355 | DONE | |
570dc176 TT |
4356 | }; |
4357 | int current_state; | |
55aa24fb SDJ |
4358 | |
4359 | current_state = TRIPLET; | |
4360 | ||
4361 | /* The special tokens to be parsed here are: | |
4362 | ||
4363 | - `register base + (register index * size) + offset', as represented | |
4364 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4365 | ||
4366 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
4367 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
4368 | ||
4369 | while (current_state != DONE) | |
4370 | { | |
55aa24fb SDJ |
4371 | switch (current_state) |
4372 | { | |
4373 | case TRIPLET: | |
5acfdbae SDJ |
4374 | if (i386_stap_parse_special_token_triplet (gdbarch, p)) |
4375 | return 1; | |
4376 | break; | |
4377 | ||
55aa24fb | 4378 | case THREE_ARG_DISPLACEMENT: |
5acfdbae SDJ |
4379 | if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p)) |
4380 | return 1; | |
4381 | break; | |
55aa24fb SDJ |
4382 | } |
4383 | ||
4384 | /* Advancing to the next state. */ | |
4385 | ++current_state; | |
4386 | } | |
4387 | ||
4388 | return 0; | |
4389 | } | |
4390 | ||
7d7571f0 SDJ |
4391 | /* Implementation of 'gdbarch_stap_adjust_register', as defined in |
4392 | gdbarch.h. */ | |
4393 | ||
6b78c3f8 | 4394 | static std::string |
7d7571f0 | 4395 | i386_stap_adjust_register (struct gdbarch *gdbarch, struct stap_parse_info *p, |
6b78c3f8 | 4396 | const std::string ®name, int regnum) |
7d7571f0 SDJ |
4397 | { |
4398 | static const std::unordered_set<std::string> reg_assoc | |
4399 | = { "ax", "bx", "cx", "dx", | |
4400 | "si", "di", "bp", "sp" }; | |
4401 | ||
6b78c3f8 AB |
4402 | /* If we are dealing with a register whose size is less than the size |
4403 | specified by the "[-]N@" prefix, and it is one of the registers that | |
4404 | we know has an extended variant available, then use the extended | |
4405 | version of the register instead. */ | |
4406 | if (register_size (gdbarch, regnum) < TYPE_LENGTH (p->arg_type) | |
4407 | && reg_assoc.find (regname) != reg_assoc.end ()) | |
4408 | return "e" + regname; | |
7d7571f0 | 4409 | |
6b78c3f8 AB |
4410 | /* Otherwise, just use the requested register. */ |
4411 | return regname; | |
7d7571f0 SDJ |
4412 | } |
4413 | ||
8201327c | 4414 | \f |
3ce1502b | 4415 | |
ac04f72b TT |
4416 | /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always |
4417 | also supplies -m64 or -m32 by gdbarch_gcc_target_options. */ | |
4418 | ||
4419 | static const char * | |
4420 | i386_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
4421 | { | |
4422 | return "(x86_64|i.86)"; | |
4423 | } | |
4424 | ||
4425 | \f | |
4426 | ||
1d509aa6 MM |
4427 | /* Implement the "in_indirect_branch_thunk" gdbarch function. */ |
4428 | ||
4429 | static bool | |
4430 | i386_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4431 | { | |
4432 | return x86_in_indirect_branch_thunk (pc, i386_register_names, | |
4433 | I386_EAX_REGNUM, I386_EIP_REGNUM); | |
4434 | } | |
4435 | ||
8201327c | 4436 | /* Generic ELF. */ |
d2a7c97a | 4437 | |
8201327c MK |
4438 | void |
4439 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4440 | { | |
05c0465e SDJ |
4441 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
4442 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
4443 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
4444 | NULL }; | |
4445 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
4446 | NULL }; | |
4447 | ||
c4fc7f1b MK |
4448 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
4449 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
4450 | |
4451 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
4452 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
4453 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
4454 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
4455 | stap_register_indirection_prefixes); | |
4456 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
4457 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
4458 | set_gdbarch_stap_is_single_operand (gdbarch, |
4459 | i386_stap_is_single_operand); | |
4460 | set_gdbarch_stap_parse_special_token (gdbarch, | |
4461 | i386_stap_parse_special_token); | |
7d7571f0 SDJ |
4462 | set_gdbarch_stap_adjust_register (gdbarch, |
4463 | i386_stap_adjust_register); | |
1d509aa6 MM |
4464 | |
4465 | set_gdbarch_in_indirect_branch_thunk (gdbarch, | |
4466 | i386_in_indirect_branch_thunk); | |
8201327c | 4467 | } |
3ce1502b | 4468 | |
8201327c | 4469 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4470 | |
8201327c MK |
4471 | void |
4472 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4473 | { | |
4474 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 4475 | |
8201327c MK |
4476 | /* System V Release 4 uses ELF. */ |
4477 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 4478 | |
dfe01d39 | 4479 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
4480 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
4481 | ||
911bc6ee | 4482 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 4483 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
4484 | tdep->sc_pc_offset = 36 + 14 * 4; |
4485 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 4486 | |
8201327c | 4487 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
4488 | } |
4489 | ||
8201327c | 4490 | \f |
2acceee2 | 4491 | |
38c968cf AC |
4492 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4493 | and "sse". */ | |
4494 | ||
4495 | static struct reggroup *i386_sse_reggroup; | |
4496 | static struct reggroup *i386_mmx_reggroup; | |
4497 | ||
4498 | static void | |
4499 | i386_init_reggroups (void) | |
4500 | { | |
4501 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4502 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4503 | } | |
4504 | ||
4505 | static void | |
4506 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4507 | { | |
4508 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4509 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
4510 | reggroup_add (gdbarch, general_reggroup); | |
4511 | reggroup_add (gdbarch, float_reggroup); | |
4512 | reggroup_add (gdbarch, all_reggroup); | |
4513 | reggroup_add (gdbarch, save_reggroup); | |
4514 | reggroup_add (gdbarch, restore_reggroup); | |
4515 | reggroup_add (gdbarch, vector_reggroup); | |
4516 | reggroup_add (gdbarch, system_reggroup); | |
4517 | } | |
4518 | ||
4519 | int | |
4520 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
4521 | struct reggroup *group) | |
4522 | { | |
c131fcee L |
4523 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4524 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
01f9f808 | 4525 | ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, |
798a7429 SM |
4526 | bndr_regnum_p, bnd_regnum_p, zmm_regnum_p, zmmh_regnum_p, |
4527 | mpx_ctrl_regnum_p, xmm_avx512_regnum_p, | |
51547df6 | 4528 | avx512_p, avx_p, sse_p, pkru_regnum_p; |
acd5c798 | 4529 | |
1ba53b71 L |
4530 | /* Don't include pseudo registers, except for MMX, in any register |
4531 | groups. */ | |
c131fcee | 4532 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4533 | return 0; |
4534 | ||
c131fcee | 4535 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4536 | return 0; |
4537 | ||
c131fcee | 4538 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4539 | return 0; |
4540 | ||
4541 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4542 | if (group == i386_mmx_reggroup) |
4543 | return mmx_regnum_p; | |
1ba53b71 | 4544 | |
51547df6 | 4545 | pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum); |
c131fcee | 4546 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
01f9f808 | 4547 | xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); |
c131fcee | 4548 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
38c968cf | 4549 | if (group == i386_sse_reggroup) |
01f9f808 | 4550 | return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; |
c131fcee L |
4551 | |
4552 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4553 | ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); |
4554 | zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); | |
4555 | ||
22049425 MS |
4556 | avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
4557 | == X86_XSTATE_AVX_AVX512_MASK); | |
4558 | avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) | |
df7e5265 | 4559 | == X86_XSTATE_AVX_MASK) && !avx512_p; |
22049425 | 4560 | sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
df7e5265 | 4561 | == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; |
01f9f808 | 4562 | |
38c968cf | 4563 | if (group == vector_reggroup) |
c131fcee | 4564 | return (mmx_regnum_p |
01f9f808 MS |
4565 | || (zmm_regnum_p && avx512_p) |
4566 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) | |
4567 | || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) | |
4568 | || mxcsr_regnum_p); | |
1ba53b71 L |
4569 | |
4570 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4571 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4572 | if (group == float_reggroup) |
4573 | return fp_regnum_p; | |
1ba53b71 | 4574 | |
c131fcee L |
4575 | /* For "info reg all", don't include upper YMM registers nor XMM |
4576 | registers when AVX is supported. */ | |
4577 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4578 | ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); |
4579 | zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); | |
c131fcee | 4580 | if (group == all_reggroup |
01f9f808 MS |
4581 | && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) |
4582 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) | |
4583 | || ymmh_regnum_p | |
4584 | || ymmh_avx512_regnum_p | |
4585 | || zmmh_regnum_p)) | |
c131fcee L |
4586 | return 0; |
4587 | ||
1dbcd68c WT |
4588 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4589 | if (group == all_reggroup | |
df7e5265 | 4590 | && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4591 | return bnd_regnum_p; |
4592 | ||
4593 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4594 | if (group == all_reggroup | |
df7e5265 | 4595 | && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4596 | return 0; |
4597 | ||
4598 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4599 | if (group == all_reggroup | |
df7e5265 | 4600 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4601 | return mpx_ctrl_regnum_p; |
4602 | ||
38c968cf | 4603 | if (group == general_reggroup) |
1ba53b71 L |
4604 | return (!fp_regnum_p |
4605 | && !mmx_regnum_p | |
c131fcee L |
4606 | && !mxcsr_regnum_p |
4607 | && !xmm_regnum_p | |
01f9f808 | 4608 | && !xmm_avx512_regnum_p |
c131fcee | 4609 | && !ymm_regnum_p |
1dbcd68c | 4610 | && !ymmh_regnum_p |
01f9f808 MS |
4611 | && !ymm_avx512_regnum_p |
4612 | && !ymmh_avx512_regnum_p | |
1dbcd68c WT |
4613 | && !bndr_regnum_p |
4614 | && !bnd_regnum_p | |
01f9f808 MS |
4615 | && !mpx_ctrl_regnum_p |
4616 | && !zmm_regnum_p | |
51547df6 MS |
4617 | && !zmmh_regnum_p |
4618 | && !pkru_regnum_p); | |
acd5c798 | 4619 | |
38c968cf AC |
4620 | return default_register_reggroup_p (gdbarch, regnum, group); |
4621 | } | |
38c968cf | 4622 | \f |
acd5c798 | 4623 | |
f837910f MK |
4624 | /* Get the ARGIth function argument for the current function. */ |
4625 | ||
42c466d7 | 4626 | static CORE_ADDR |
143985b7 AF |
4627 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
4628 | struct type *type) | |
4629 | { | |
e17a4113 UW |
4630 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4631 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4632 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4633 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4634 | } |
4635 | ||
7ad10968 HZ |
4636 | #define PREFIX_REPZ 0x01 |
4637 | #define PREFIX_REPNZ 0x02 | |
4638 | #define PREFIX_LOCK 0x04 | |
4639 | #define PREFIX_DATA 0x08 | |
4640 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4641 | |
7ad10968 HZ |
4642 | /* operand size */ |
4643 | enum | |
4644 | { | |
4645 | OT_BYTE = 0, | |
4646 | OT_WORD, | |
4647 | OT_LONG, | |
cf648174 | 4648 | OT_QUAD, |
a3c4230a | 4649 | OT_DQUAD, |
7ad10968 | 4650 | }; |
473f17b0 | 4651 | |
7ad10968 HZ |
4652 | /* i386 arith/logic operations */ |
4653 | enum | |
4654 | { | |
4655 | OP_ADDL, | |
4656 | OP_ORL, | |
4657 | OP_ADCL, | |
4658 | OP_SBBL, | |
4659 | OP_ANDL, | |
4660 | OP_SUBL, | |
4661 | OP_XORL, | |
4662 | OP_CMPL, | |
4663 | }; | |
5716833c | 4664 | |
7ad10968 HZ |
4665 | struct i386_record_s |
4666 | { | |
cf648174 | 4667 | struct gdbarch *gdbarch; |
7ad10968 | 4668 | struct regcache *regcache; |
df61f520 | 4669 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4670 | CORE_ADDR addr; |
4671 | int aflag; | |
4672 | int dflag; | |
4673 | int override; | |
4674 | uint8_t modrm; | |
4675 | uint8_t mod, reg, rm; | |
4676 | int ot; | |
cf648174 HZ |
4677 | uint8_t rex_x; |
4678 | uint8_t rex_b; | |
4679 | int rip_offset; | |
4680 | int popl_esp_hack; | |
4681 | const int *regmap; | |
7ad10968 | 4682 | }; |
5716833c | 4683 | |
99c1624c PA |
4684 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4685 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4686 | |
7ad10968 HZ |
4687 | static int |
4688 | i386_record_modrm (struct i386_record_s *irp) | |
4689 | { | |
cf648174 | 4690 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4691 | |
4ffa4fc7 PA |
4692 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4693 | return -1; | |
4694 | ||
7ad10968 HZ |
4695 | irp->addr++; |
4696 | irp->mod = (irp->modrm >> 6) & 3; | |
4697 | irp->reg = (irp->modrm >> 3) & 7; | |
4698 | irp->rm = irp->modrm & 7; | |
5716833c | 4699 | |
7ad10968 HZ |
4700 | return 0; |
4701 | } | |
d2a7c97a | 4702 | |
99c1624c PA |
4703 | /* Extract the memory address that the current instruction writes to, |
4704 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4705 | |
7ad10968 | 4706 | static int |
cf648174 | 4707 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4708 | { |
cf648174 | 4709 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4710 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4711 | gdb_byte buf[4]; | |
4712 | ULONGEST offset64; | |
21d0e8a4 | 4713 | |
7ad10968 | 4714 | *addr = 0; |
1e87984a | 4715 | if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4716 | { |
1e87984a | 4717 | /* 32/64 bits */ |
7ad10968 HZ |
4718 | int havesib = 0; |
4719 | uint8_t scale = 0; | |
648d0c8b | 4720 | uint8_t byte; |
7ad10968 HZ |
4721 | uint8_t index = 0; |
4722 | uint8_t base = irp->rm; | |
896fb97d | 4723 | |
7ad10968 HZ |
4724 | if (base == 4) |
4725 | { | |
4726 | havesib = 1; | |
4ffa4fc7 PA |
4727 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4728 | return -1; | |
7ad10968 | 4729 | irp->addr++; |
648d0c8b MS |
4730 | scale = (byte >> 6) & 3; |
4731 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4732 | base = (byte & 7); | |
7ad10968 | 4733 | } |
cf648174 | 4734 | base |= irp->rex_b; |
21d0e8a4 | 4735 | |
7ad10968 HZ |
4736 | switch (irp->mod) |
4737 | { | |
4738 | case 0: | |
4739 | if ((base & 7) == 5) | |
4740 | { | |
4741 | base = 0xff; | |
4ffa4fc7 PA |
4742 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4743 | return -1; | |
7ad10968 | 4744 | irp->addr += 4; |
60a1502a | 4745 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4746 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4747 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4748 | } |
7ad10968 HZ |
4749 | break; |
4750 | case 1: | |
4ffa4fc7 PA |
4751 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4752 | return -1; | |
7ad10968 | 4753 | irp->addr++; |
60a1502a | 4754 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4755 | break; |
4756 | case 2: | |
4ffa4fc7 PA |
4757 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4758 | return -1; | |
60a1502a | 4759 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4760 | irp->addr += 4; |
4761 | break; | |
4762 | } | |
356a6b3e | 4763 | |
60a1502a | 4764 | offset64 = 0; |
7ad10968 | 4765 | if (base != 0xff) |
cf648174 HZ |
4766 | { |
4767 | if (base == 4 && irp->popl_esp_hack) | |
4768 | *addr += irp->popl_esp_hack; | |
4769 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4770 | &offset64); |
7ad10968 | 4771 | } |
cf648174 HZ |
4772 | if (irp->aflag == 2) |
4773 | { | |
60a1502a | 4774 | *addr += offset64; |
cf648174 HZ |
4775 | } |
4776 | else | |
60a1502a | 4777 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4778 | |
7ad10968 HZ |
4779 | if (havesib && (index != 4 || scale != 0)) |
4780 | { | |
cf648174 | 4781 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4782 | &offset64); |
cf648174 | 4783 | if (irp->aflag == 2) |
60a1502a | 4784 | *addr += offset64 << scale; |
cf648174 | 4785 | else |
60a1502a | 4786 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 | 4787 | } |
e85596e0 L |
4788 | |
4789 | if (!irp->aflag) | |
4790 | { | |
4791 | /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend | |
4792 | address from 32-bit to 64-bit. */ | |
4793 | *addr = (uint32_t) *addr; | |
4794 | } | |
7ad10968 HZ |
4795 | } |
4796 | else | |
4797 | { | |
4798 | /* 16 bits */ | |
4799 | switch (irp->mod) | |
4800 | { | |
4801 | case 0: | |
4802 | if (irp->rm == 6) | |
4803 | { | |
4ffa4fc7 PA |
4804 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4805 | return -1; | |
7ad10968 | 4806 | irp->addr += 2; |
60a1502a | 4807 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4808 | irp->rm = 0; |
4809 | goto no_rm; | |
4810 | } | |
7ad10968 HZ |
4811 | break; |
4812 | case 1: | |
4ffa4fc7 PA |
4813 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4814 | return -1; | |
7ad10968 | 4815 | irp->addr++; |
60a1502a | 4816 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4817 | break; |
4818 | case 2: | |
4ffa4fc7 PA |
4819 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4820 | return -1; | |
7ad10968 | 4821 | irp->addr += 2; |
60a1502a | 4822 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4823 | break; |
4824 | } | |
c4fc7f1b | 4825 | |
7ad10968 HZ |
4826 | switch (irp->rm) |
4827 | { | |
4828 | case 0: | |
cf648174 HZ |
4829 | regcache_raw_read_unsigned (irp->regcache, |
4830 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4831 | &offset64); |
4832 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4833 | regcache_raw_read_unsigned (irp->regcache, |
4834 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4835 | &offset64); |
4836 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4837 | break; |
4838 | case 1: | |
cf648174 HZ |
4839 | regcache_raw_read_unsigned (irp->regcache, |
4840 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4841 | &offset64); |
4842 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4843 | regcache_raw_read_unsigned (irp->regcache, |
4844 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4845 | &offset64); |
4846 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4847 | break; |
4848 | case 2: | |
cf648174 HZ |
4849 | regcache_raw_read_unsigned (irp->regcache, |
4850 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4851 | &offset64); |
4852 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4853 | regcache_raw_read_unsigned (irp->regcache, |
4854 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4855 | &offset64); |
4856 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4857 | break; |
4858 | case 3: | |
cf648174 HZ |
4859 | regcache_raw_read_unsigned (irp->regcache, |
4860 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4861 | &offset64); |
4862 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4863 | regcache_raw_read_unsigned (irp->regcache, |
4864 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4865 | &offset64); |
4866 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4867 | break; |
4868 | case 4: | |
cf648174 HZ |
4869 | regcache_raw_read_unsigned (irp->regcache, |
4870 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4871 | &offset64); |
4872 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4873 | break; |
4874 | case 5: | |
cf648174 HZ |
4875 | regcache_raw_read_unsigned (irp->regcache, |
4876 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4877 | &offset64); |
4878 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4879 | break; |
4880 | case 6: | |
cf648174 HZ |
4881 | regcache_raw_read_unsigned (irp->regcache, |
4882 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4883 | &offset64); |
4884 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4885 | break; |
4886 | case 7: | |
cf648174 HZ |
4887 | regcache_raw_read_unsigned (irp->regcache, |
4888 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4889 | &offset64); |
4890 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4891 | break; |
4892 | } | |
4893 | *addr &= 0xffff; | |
4894 | } | |
c4fc7f1b | 4895 | |
01fe1b41 | 4896 | no_rm: |
7ad10968 HZ |
4897 | return 0; |
4898 | } | |
c4fc7f1b | 4899 | |
99c1624c PA |
4900 | /* Record the address and contents of the memory that will be changed |
4901 | by the current instruction. Return -1 if something goes wrong, 0 | |
4902 | otherwise. */ | |
356a6b3e | 4903 | |
7ad10968 HZ |
4904 | static int |
4905 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4906 | { | |
cf648174 HZ |
4907 | struct gdbarch *gdbarch = irp->gdbarch; |
4908 | uint64_t addr; | |
356a6b3e | 4909 | |
d7877f7e | 4910 | if (irp->override >= 0) |
7ad10968 | 4911 | { |
25ea693b | 4912 | if (record_full_memory_query) |
bb08c432 | 4913 | { |
651ce16a | 4914 | if (yquery (_("\ |
bb08c432 HZ |
4915 | Process record ignores the memory change of instruction at address %s\n\ |
4916 | because it can't get the value of the segment register.\n\ | |
4917 | Do you want to stop the program?"), | |
651ce16a PA |
4918 | paddress (gdbarch, irp->orig_addr))) |
4919 | return -1; | |
bb08c432 HZ |
4920 | } |
4921 | ||
7ad10968 HZ |
4922 | return 0; |
4923 | } | |
61113f8b | 4924 | |
7ad10968 HZ |
4925 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4926 | return -1; | |
96297dab | 4927 | |
25ea693b | 4928 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4929 | return -1; |
a62cc96e | 4930 | |
7ad10968 HZ |
4931 | return 0; |
4932 | } | |
b6197528 | 4933 | |
99c1624c PA |
4934 | /* Record the effects of a push operation. Return -1 if something |
4935 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4936 | |
4937 | static int | |
4938 | i386_record_push (struct i386_record_s *irp, int size) | |
4939 | { | |
648d0c8b | 4940 | ULONGEST addr; |
cf648174 | 4941 | |
25ea693b MM |
4942 | if (record_full_arch_list_add_reg (irp->regcache, |
4943 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4944 | return -1; |
4945 | regcache_raw_read_unsigned (irp->regcache, | |
4946 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4947 | &addr); |
25ea693b | 4948 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4949 | return -1; |
4950 | ||
4951 | return 0; | |
4952 | } | |
4953 | ||
0289bdd7 MS |
4954 | |
4955 | /* Defines contents to record. */ | |
4956 | #define I386_SAVE_FPU_REGS 0xfffd | |
4957 | #define I386_SAVE_FPU_ENV 0xfffe | |
4958 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4959 | ||
99c1624c PA |
4960 | /* Record the values of the floating point registers which will be |
4961 | changed by the current instruction. Returns -1 if something is | |
4962 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4963 | |
4964 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4965 | struct i386_record_s *ir, | |
4966 | uint32_t iregnum) | |
4967 | { | |
4968 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4969 | int i; | |
4970 | ||
4971 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4972 | happen. Currently we store st0-st7 registers, but we need not store all | |
4973 | registers all the time, in future we use ftag register and record only | |
4974 | those who are not marked as an empty. */ | |
4975 | ||
4976 | if (I386_SAVE_FPU_REGS == iregnum) | |
4977 | { | |
4978 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
4979 | { | |
25ea693b | 4980 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4981 | return -1; |
4982 | } | |
4983 | } | |
4984 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4985 | { | |
4986 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4987 | { | |
25ea693b | 4988 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4989 | return -1; |
4990 | } | |
4991 | } | |
4992 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4993 | { | |
4994 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4995 | { | |
25ea693b | 4996 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4997 | return -1; |
4998 | } | |
4999 | } | |
5000 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
5001 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
5002 | { | |
25ea693b | 5003 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
0289bdd7 MS |
5004 | return -1; |
5005 | } | |
5006 | else | |
5007 | { | |
5008 | /* Parameter error. */ | |
5009 | return -1; | |
5010 | } | |
5011 | if(I386_SAVE_FPU_ENV != iregnum) | |
5012 | { | |
5013 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5014 | { | |
25ea693b | 5015 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
5016 | return -1; |
5017 | } | |
5018 | } | |
5019 | return 0; | |
5020 | } | |
5021 | ||
99c1624c PA |
5022 | /* Parse the current instruction, and record the values of the |
5023 | registers and memory that will be changed by the current | |
5024 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 5025 | |
25ea693b MM |
5026 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
5027 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 5028 | |
a6b808b4 | 5029 | int |
7ad10968 | 5030 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 5031 | CORE_ADDR input_addr) |
7ad10968 | 5032 | { |
60a1502a | 5033 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 5034 | int prefixes = 0; |
580879fc | 5035 | int regnum = 0; |
425b824a | 5036 | uint32_t opcode; |
f4644a3f | 5037 | uint8_t opcode8; |
648d0c8b | 5038 | ULONGEST addr; |
975c21ab | 5039 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
7ad10968 | 5040 | struct i386_record_s ir; |
0289bdd7 | 5041 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
5042 | uint8_t rex_w = -1; |
5043 | uint8_t rex_r = 0; | |
7ad10968 | 5044 | |
8408d274 | 5045 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 5046 | ir.regcache = regcache; |
648d0c8b MS |
5047 | ir.addr = input_addr; |
5048 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
5049 | ir.aflag = 1; |
5050 | ir.dflag = 1; | |
cf648174 HZ |
5051 | ir.override = -1; |
5052 | ir.popl_esp_hack = 0; | |
a3c4230a | 5053 | ir.regmap = tdep->record_regmap; |
cf648174 | 5054 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
5055 | |
5056 | if (record_debug > 1) | |
5057 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
5058 | "addr = %s\n", |
5059 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5060 | |
5061 | /* prefixes */ | |
5062 | while (1) | |
5063 | { | |
4ffa4fc7 PA |
5064 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5065 | return -1; | |
7ad10968 | 5066 | ir.addr++; |
425b824a | 5067 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 5068 | { |
01fe1b41 | 5069 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
5070 | prefixes |= PREFIX_REPZ; |
5071 | break; | |
01fe1b41 | 5072 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
5073 | prefixes |= PREFIX_REPNZ; |
5074 | break; | |
01fe1b41 | 5075 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
5076 | prefixes |= PREFIX_LOCK; |
5077 | break; | |
01fe1b41 | 5078 | case CS_PREFIX_OPCODE: |
cf648174 | 5079 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 5080 | break; |
01fe1b41 | 5081 | case SS_PREFIX_OPCODE: |
cf648174 | 5082 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 5083 | break; |
01fe1b41 | 5084 | case DS_PREFIX_OPCODE: |
cf648174 | 5085 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 5086 | break; |
01fe1b41 | 5087 | case ES_PREFIX_OPCODE: |
cf648174 | 5088 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 5089 | break; |
01fe1b41 | 5090 | case FS_PREFIX_OPCODE: |
cf648174 | 5091 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 5092 | break; |
01fe1b41 | 5093 | case GS_PREFIX_OPCODE: |
cf648174 | 5094 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 5095 | break; |
01fe1b41 | 5096 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
5097 | prefixes |= PREFIX_DATA; |
5098 | break; | |
01fe1b41 | 5099 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
5100 | prefixes |= PREFIX_ADDR; |
5101 | break; | |
d691bec7 MS |
5102 | case 0x40: /* i386 inc %eax */ |
5103 | case 0x41: /* i386 inc %ecx */ | |
5104 | case 0x42: /* i386 inc %edx */ | |
5105 | case 0x43: /* i386 inc %ebx */ | |
5106 | case 0x44: /* i386 inc %esp */ | |
5107 | case 0x45: /* i386 inc %ebp */ | |
5108 | case 0x46: /* i386 inc %esi */ | |
5109 | case 0x47: /* i386 inc %edi */ | |
5110 | case 0x48: /* i386 dec %eax */ | |
5111 | case 0x49: /* i386 dec %ecx */ | |
5112 | case 0x4a: /* i386 dec %edx */ | |
5113 | case 0x4b: /* i386 dec %ebx */ | |
5114 | case 0x4c: /* i386 dec %esp */ | |
5115 | case 0x4d: /* i386 dec %ebp */ | |
5116 | case 0x4e: /* i386 dec %esi */ | |
5117 | case 0x4f: /* i386 dec %edi */ | |
5118 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
5119 | { |
5120 | /* REX */ | |
425b824a MS |
5121 | rex_w = (opcode8 >> 3) & 1; |
5122 | rex_r = (opcode8 & 0x4) << 1; | |
5123 | ir.rex_x = (opcode8 & 0x2) << 2; | |
5124 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 5125 | } |
d691bec7 MS |
5126 | else /* 32 bit target */ |
5127 | goto out_prefixes; | |
cf648174 | 5128 | break; |
7ad10968 HZ |
5129 | default: |
5130 | goto out_prefixes; | |
5131 | break; | |
5132 | } | |
5133 | } | |
01fe1b41 | 5134 | out_prefixes: |
cf648174 HZ |
5135 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
5136 | { | |
5137 | ir.dflag = 2; | |
5138 | } | |
5139 | else | |
5140 | { | |
5141 | if (prefixes & PREFIX_DATA) | |
5142 | ir.dflag ^= 1; | |
5143 | } | |
7ad10968 HZ |
5144 | if (prefixes & PREFIX_ADDR) |
5145 | ir.aflag ^= 1; | |
cf648174 HZ |
5146 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5147 | ir.aflag = 2; | |
7ad10968 | 5148 | |
1777feb0 | 5149 | /* Now check op code. */ |
425b824a | 5150 | opcode = (uint32_t) opcode8; |
01fe1b41 | 5151 | reswitch: |
7ad10968 HZ |
5152 | switch (opcode) |
5153 | { | |
5154 | case 0x0f: | |
4ffa4fc7 PA |
5155 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5156 | return -1; | |
7ad10968 | 5157 | ir.addr++; |
a3c4230a | 5158 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
5159 | goto reswitch; |
5160 | break; | |
93924b6b | 5161 | |
a38bba38 | 5162 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
5163 | case 0x01: |
5164 | case 0x02: | |
5165 | case 0x03: | |
5166 | case 0x04: | |
5167 | case 0x05: | |
5168 | case 0x08: | |
5169 | case 0x09: | |
5170 | case 0x0a: | |
5171 | case 0x0b: | |
5172 | case 0x0c: | |
5173 | case 0x0d: | |
5174 | case 0x10: | |
5175 | case 0x11: | |
5176 | case 0x12: | |
5177 | case 0x13: | |
5178 | case 0x14: | |
5179 | case 0x15: | |
5180 | case 0x18: | |
5181 | case 0x19: | |
5182 | case 0x1a: | |
5183 | case 0x1b: | |
5184 | case 0x1c: | |
5185 | case 0x1d: | |
5186 | case 0x20: | |
5187 | case 0x21: | |
5188 | case 0x22: | |
5189 | case 0x23: | |
5190 | case 0x24: | |
5191 | case 0x25: | |
5192 | case 0x28: | |
5193 | case 0x29: | |
5194 | case 0x2a: | |
5195 | case 0x2b: | |
5196 | case 0x2c: | |
5197 | case 0x2d: | |
5198 | case 0x30: | |
5199 | case 0x31: | |
5200 | case 0x32: | |
5201 | case 0x33: | |
5202 | case 0x34: | |
5203 | case 0x35: | |
5204 | case 0x38: | |
5205 | case 0x39: | |
5206 | case 0x3a: | |
5207 | case 0x3b: | |
5208 | case 0x3c: | |
5209 | case 0x3d: | |
5210 | if (((opcode >> 3) & 7) != OP_CMPL) | |
5211 | { | |
5212 | if ((opcode & 1) == 0) | |
5213 | ir.ot = OT_BYTE; | |
5214 | else | |
5215 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 5216 | |
7ad10968 HZ |
5217 | switch ((opcode >> 1) & 3) |
5218 | { | |
a38bba38 | 5219 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
5220 | if (i386_record_modrm (&ir)) |
5221 | return -1; | |
5222 | if (ir.mod != 3) | |
5223 | { | |
5224 | if (i386_record_lea_modrm (&ir)) | |
5225 | return -1; | |
5226 | } | |
5227 | else | |
5228 | { | |
cf648174 HZ |
5229 | ir.rm |= ir.rex_b; |
5230 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5231 | ir.rm &= 0x3; |
25ea693b | 5232 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5233 | } |
5234 | break; | |
a38bba38 | 5235 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
5236 | if (i386_record_modrm (&ir)) |
5237 | return -1; | |
cf648174 HZ |
5238 | ir.reg |= rex_r; |
5239 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5240 | ir.reg &= 0x3; |
25ea693b | 5241 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5242 | break; |
a38bba38 | 5243 | case 2: /* OP A, Iv */ |
25ea693b | 5244 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5245 | break; |
5246 | } | |
5247 | } | |
25ea693b | 5248 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5249 | break; |
42fdc8df | 5250 | |
a38bba38 | 5251 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
5252 | case 0x81: |
5253 | case 0x82: | |
5254 | case 0x83: | |
5255 | if (i386_record_modrm (&ir)) | |
5256 | return -1; | |
8201327c | 5257 | |
7ad10968 HZ |
5258 | if (ir.reg != OP_CMPL) |
5259 | { | |
5260 | if ((opcode & 1) == 0) | |
5261 | ir.ot = OT_BYTE; | |
5262 | else | |
5263 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 5264 | |
7ad10968 HZ |
5265 | if (ir.mod != 3) |
5266 | { | |
cf648174 HZ |
5267 | if (opcode == 0x83) |
5268 | ir.rip_offset = 1; | |
5269 | else | |
5270 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5271 | if (i386_record_lea_modrm (&ir)) |
5272 | return -1; | |
5273 | } | |
5274 | else | |
25ea693b | 5275 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 5276 | } |
25ea693b | 5277 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5278 | break; |
5e3397bb | 5279 | |
a38bba38 | 5280 | case 0x40: /* inc */ |
7ad10968 HZ |
5281 | case 0x41: |
5282 | case 0x42: | |
5283 | case 0x43: | |
5284 | case 0x44: | |
5285 | case 0x45: | |
5286 | case 0x46: | |
5287 | case 0x47: | |
a38bba38 MS |
5288 | |
5289 | case 0x48: /* dec */ | |
7ad10968 HZ |
5290 | case 0x49: |
5291 | case 0x4a: | |
5292 | case 0x4b: | |
5293 | case 0x4c: | |
5294 | case 0x4d: | |
5295 | case 0x4e: | |
5296 | case 0x4f: | |
a38bba38 | 5297 | |
25ea693b MM |
5298 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
5299 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 5300 | break; |
acd5c798 | 5301 | |
a38bba38 | 5302 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
5303 | case 0xf7: |
5304 | if ((opcode & 1) == 0) | |
5305 | ir.ot = OT_BYTE; | |
5306 | else | |
5307 | ir.ot = ir.dflag + OT_WORD; | |
5308 | if (i386_record_modrm (&ir)) | |
5309 | return -1; | |
acd5c798 | 5310 | |
cf648174 HZ |
5311 | if (ir.mod != 3 && ir.reg == 0) |
5312 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5313 | ||
7ad10968 HZ |
5314 | switch (ir.reg) |
5315 | { | |
a38bba38 | 5316 | case 0: /* test */ |
25ea693b | 5317 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5318 | break; |
a38bba38 MS |
5319 | case 2: /* not */ |
5320 | case 3: /* neg */ | |
7ad10968 HZ |
5321 | if (ir.mod != 3) |
5322 | { | |
5323 | if (i386_record_lea_modrm (&ir)) | |
5324 | return -1; | |
5325 | } | |
5326 | else | |
5327 | { | |
cf648174 HZ |
5328 | ir.rm |= ir.rex_b; |
5329 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5330 | ir.rm &= 0x3; |
25ea693b | 5331 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5332 | } |
a38bba38 | 5333 | if (ir.reg == 3) /* neg */ |
25ea693b | 5334 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5335 | break; |
a38bba38 MS |
5336 | case 4: /* mul */ |
5337 | case 5: /* imul */ | |
5338 | case 6: /* div */ | |
5339 | case 7: /* idiv */ | |
25ea693b | 5340 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 5341 | if (ir.ot != OT_BYTE) |
25ea693b MM |
5342 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
5343 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5344 | break; |
5345 | default: | |
5346 | ir.addr -= 2; | |
5347 | opcode = opcode << 8 | ir.modrm; | |
5348 | goto no_support; | |
5349 | break; | |
5350 | } | |
5351 | break; | |
5352 | ||
a38bba38 MS |
5353 | case 0xfe: /* GRP4 */ |
5354 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
5355 | if (i386_record_modrm (&ir)) |
5356 | return -1; | |
5357 | if (ir.reg >= 2 && opcode == 0xfe) | |
5358 | { | |
5359 | ir.addr -= 2; | |
5360 | opcode = opcode << 8 | ir.modrm; | |
5361 | goto no_support; | |
5362 | } | |
7ad10968 HZ |
5363 | switch (ir.reg) |
5364 | { | |
a38bba38 MS |
5365 | case 0: /* inc */ |
5366 | case 1: /* dec */ | |
cf648174 HZ |
5367 | if ((opcode & 1) == 0) |
5368 | ir.ot = OT_BYTE; | |
5369 | else | |
5370 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5371 | if (ir.mod != 3) |
5372 | { | |
5373 | if (i386_record_lea_modrm (&ir)) | |
5374 | return -1; | |
5375 | } | |
5376 | else | |
5377 | { | |
cf648174 HZ |
5378 | ir.rm |= ir.rex_b; |
5379 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5380 | ir.rm &= 0x3; |
25ea693b | 5381 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5382 | } |
25ea693b | 5383 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5384 | break; |
a38bba38 | 5385 | case 2: /* call */ |
cf648174 HZ |
5386 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5387 | ir.dflag = 2; | |
5388 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5389 | return -1; |
25ea693b | 5390 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5391 | break; |
a38bba38 | 5392 | case 3: /* lcall */ |
25ea693b | 5393 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 5394 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5395 | return -1; |
25ea693b | 5396 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5397 | break; |
a38bba38 MS |
5398 | case 4: /* jmp */ |
5399 | case 5: /* ljmp */ | |
25ea693b | 5400 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 5401 | break; |
a38bba38 | 5402 | case 6: /* push */ |
cf648174 HZ |
5403 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5404 | ir.dflag = 2; | |
5405 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5406 | return -1; | |
7ad10968 HZ |
5407 | break; |
5408 | default: | |
5409 | ir.addr -= 2; | |
5410 | opcode = opcode << 8 | ir.modrm; | |
5411 | goto no_support; | |
5412 | break; | |
5413 | } | |
5414 | break; | |
5415 | ||
a38bba38 | 5416 | case 0x84: /* test */ |
7ad10968 HZ |
5417 | case 0x85: |
5418 | case 0xa8: | |
5419 | case 0xa9: | |
25ea693b | 5420 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5421 | break; |
5422 | ||
a38bba38 | 5423 | case 0x98: /* CWDE/CBW */ |
25ea693b | 5424 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5425 | break; |
5426 | ||
a38bba38 | 5427 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
5428 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5429 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5430 | break; |
5431 | ||
a38bba38 | 5432 | case 0x0faf: /* imul */ |
7ad10968 HZ |
5433 | case 0x69: |
5434 | case 0x6b: | |
5435 | ir.ot = ir.dflag + OT_WORD; | |
5436 | if (i386_record_modrm (&ir)) | |
5437 | return -1; | |
cf648174 HZ |
5438 | if (opcode == 0x69) |
5439 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5440 | else if (opcode == 0x6b) | |
5441 | ir.rip_offset = 1; | |
5442 | ir.reg |= rex_r; | |
5443 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5444 | ir.reg &= 0x3; |
25ea693b MM |
5445 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
5446 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5447 | break; |
5448 | ||
a38bba38 | 5449 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
5450 | case 0x0fc1: |
5451 | if ((opcode & 1) == 0) | |
5452 | ir.ot = OT_BYTE; | |
5453 | else | |
5454 | ir.ot = ir.dflag + OT_WORD; | |
5455 | if (i386_record_modrm (&ir)) | |
5456 | return -1; | |
cf648174 | 5457 | ir.reg |= rex_r; |
7ad10968 HZ |
5458 | if (ir.mod == 3) |
5459 | { | |
cf648174 | 5460 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5461 | ir.reg &= 0x3; |
25ea693b | 5462 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5463 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5464 | ir.rm &= 0x3; |
25ea693b | 5465 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5466 | } |
5467 | else | |
5468 | { | |
5469 | if (i386_record_lea_modrm (&ir)) | |
5470 | return -1; | |
cf648174 | 5471 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5472 | ir.reg &= 0x3; |
25ea693b | 5473 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5474 | } |
25ea693b | 5475 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5476 | break; |
5477 | ||
a38bba38 | 5478 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
5479 | case 0x0fb1: |
5480 | if ((opcode & 1) == 0) | |
5481 | ir.ot = OT_BYTE; | |
5482 | else | |
5483 | ir.ot = ir.dflag + OT_WORD; | |
5484 | if (i386_record_modrm (&ir)) | |
5485 | return -1; | |
5486 | if (ir.mod == 3) | |
5487 | { | |
cf648174 | 5488 | ir.reg |= rex_r; |
25ea693b | 5489 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 5490 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5491 | ir.reg &= 0x3; |
25ea693b | 5492 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5493 | } |
5494 | else | |
5495 | { | |
25ea693b | 5496 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5497 | if (i386_record_lea_modrm (&ir)) |
5498 | return -1; | |
5499 | } | |
25ea693b | 5500 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5501 | break; |
5502 | ||
20b477a7 | 5503 | case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */ |
7ad10968 HZ |
5504 | if (i386_record_modrm (&ir)) |
5505 | return -1; | |
5506 | if (ir.mod == 3) | |
5507 | { | |
20b477a7 LM |
5508 | /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as |
5509 | an extended opcode. rdrand has bits 110 (/6) and rdseed | |
5510 | has bits 111 (/7). */ | |
5511 | if (ir.reg == 6 || ir.reg == 7) | |
5512 | { | |
5513 | /* The storage register is described by the 3 R/M bits, but the | |
5514 | REX.B prefix may be used to give access to registers | |
5515 | R8~R15. In this case ir.rex_b + R/M will give us the register | |
5516 | in the range R8~R15. | |
5517 | ||
5518 | REX.W may also be used to access 64-bit registers, but we | |
5519 | already record entire registers and not just partial bits | |
5520 | of them. */ | |
5521 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm); | |
5522 | /* These instructions also set conditional bits. */ | |
5523 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5524 | break; | |
5525 | } | |
5526 | else | |
5527 | { | |
5528 | /* We don't handle this particular instruction yet. */ | |
5529 | ir.addr -= 2; | |
5530 | opcode = opcode << 8 | ir.modrm; | |
5531 | goto no_support; | |
5532 | } | |
7ad10968 | 5533 | } |
25ea693b MM |
5534 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5535 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5536 | if (i386_record_lea_modrm (&ir)) |
5537 | return -1; | |
25ea693b | 5538 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5539 | break; |
5540 | ||
a38bba38 | 5541 | case 0x50: /* push */ |
7ad10968 HZ |
5542 | case 0x51: |
5543 | case 0x52: | |
5544 | case 0x53: | |
5545 | case 0x54: | |
5546 | case 0x55: | |
5547 | case 0x56: | |
5548 | case 0x57: | |
5549 | case 0x68: | |
5550 | case 0x6a: | |
cf648174 HZ |
5551 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5552 | ir.dflag = 2; | |
5553 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5554 | return -1; | |
5555 | break; | |
5556 | ||
a38bba38 MS |
5557 | case 0x06: /* push es */ |
5558 | case 0x0e: /* push cs */ | |
5559 | case 0x16: /* push ss */ | |
5560 | case 0x1e: /* push ds */ | |
cf648174 HZ |
5561 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5562 | { | |
5563 | ir.addr -= 1; | |
5564 | goto no_support; | |
5565 | } | |
5566 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5567 | return -1; | |
5568 | break; | |
5569 | ||
a38bba38 MS |
5570 | case 0x0fa0: /* push fs */ |
5571 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
5572 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5573 | { | |
5574 | ir.addr -= 2; | |
5575 | goto no_support; | |
5576 | } | |
5577 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5578 | return -1; |
cf648174 HZ |
5579 | break; |
5580 | ||
a38bba38 | 5581 | case 0x60: /* pusha */ |
cf648174 HZ |
5582 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5583 | { | |
5584 | ir.addr -= 1; | |
5585 | goto no_support; | |
5586 | } | |
5587 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5588 | return -1; |
5589 | break; | |
5590 | ||
a38bba38 | 5591 | case 0x58: /* pop */ |
7ad10968 HZ |
5592 | case 0x59: |
5593 | case 0x5a: | |
5594 | case 0x5b: | |
5595 | case 0x5c: | |
5596 | case 0x5d: | |
5597 | case 0x5e: | |
5598 | case 0x5f: | |
25ea693b MM |
5599 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5600 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5601 | break; |
5602 | ||
a38bba38 | 5603 | case 0x61: /* popa */ |
cf648174 HZ |
5604 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5605 | { | |
5606 | ir.addr -= 1; | |
5607 | goto no_support; | |
7ad10968 | 5608 | } |
425b824a MS |
5609 | for (regnum = X86_RECORD_REAX_REGNUM; |
5610 | regnum <= X86_RECORD_REDI_REGNUM; | |
5611 | regnum++) | |
25ea693b | 5612 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5613 | break; |
5614 | ||
a38bba38 | 5615 | case 0x8f: /* pop */ |
cf648174 HZ |
5616 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5617 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5618 | else | |
5619 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5620 | if (i386_record_modrm (&ir)) |
5621 | return -1; | |
5622 | if (ir.mod == 3) | |
25ea693b | 5623 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5624 | else |
5625 | { | |
cf648174 | 5626 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5627 | if (i386_record_lea_modrm (&ir)) |
5628 | return -1; | |
5629 | } | |
25ea693b | 5630 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5631 | break; |
5632 | ||
a38bba38 | 5633 | case 0xc8: /* enter */ |
25ea693b | 5634 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 HZ |
5635 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5636 | ir.dflag = 2; | |
5637 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
5638 | return -1; |
5639 | break; | |
5640 | ||
a38bba38 | 5641 | case 0xc9: /* leave */ |
25ea693b MM |
5642 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5643 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5644 | break; |
5645 | ||
a38bba38 | 5646 | case 0x07: /* pop es */ |
cf648174 HZ |
5647 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5648 | { | |
5649 | ir.addr -= 1; | |
5650 | goto no_support; | |
5651 | } | |
25ea693b MM |
5652 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5653 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5654 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5655 | break; |
5656 | ||
a38bba38 | 5657 | case 0x17: /* pop ss */ |
cf648174 HZ |
5658 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5659 | { | |
5660 | ir.addr -= 1; | |
5661 | goto no_support; | |
5662 | } | |
25ea693b MM |
5663 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5664 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5665 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5666 | break; |
5667 | ||
a38bba38 | 5668 | case 0x1f: /* pop ds */ |
cf648174 HZ |
5669 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5670 | { | |
5671 | ir.addr -= 1; | |
5672 | goto no_support; | |
5673 | } | |
25ea693b MM |
5674 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5675 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5676 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5677 | break; |
5678 | ||
a38bba38 | 5679 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5680 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5681 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5682 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5683 | break; |
5684 | ||
a38bba38 | 5685 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5686 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5687 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5688 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5689 | break; |
5690 | ||
a38bba38 | 5691 | case 0x88: /* mov */ |
7ad10968 HZ |
5692 | case 0x89: |
5693 | case 0xc6: | |
5694 | case 0xc7: | |
5695 | if ((opcode & 1) == 0) | |
5696 | ir.ot = OT_BYTE; | |
5697 | else | |
5698 | ir.ot = ir.dflag + OT_WORD; | |
5699 | ||
5700 | if (i386_record_modrm (&ir)) | |
5701 | return -1; | |
5702 | ||
5703 | if (ir.mod != 3) | |
5704 | { | |
cf648174 HZ |
5705 | if (opcode == 0xc6 || opcode == 0xc7) |
5706 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5707 | if (i386_record_lea_modrm (&ir)) |
5708 | return -1; | |
5709 | } | |
5710 | else | |
5711 | { | |
cf648174 HZ |
5712 | if (opcode == 0xc6 || opcode == 0xc7) |
5713 | ir.rm |= ir.rex_b; | |
5714 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5715 | ir.rm &= 0x3; |
25ea693b | 5716 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5717 | } |
7ad10968 | 5718 | break; |
cf648174 | 5719 | |
a38bba38 | 5720 | case 0x8a: /* mov */ |
7ad10968 HZ |
5721 | case 0x8b: |
5722 | if ((opcode & 1) == 0) | |
5723 | ir.ot = OT_BYTE; | |
5724 | else | |
5725 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5726 | if (i386_record_modrm (&ir)) |
5727 | return -1; | |
cf648174 HZ |
5728 | ir.reg |= rex_r; |
5729 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5730 | ir.reg &= 0x3; |
25ea693b | 5731 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5732 | break; |
7ad10968 | 5733 | |
a38bba38 | 5734 | case 0x8c: /* mov seg */ |
cf648174 | 5735 | if (i386_record_modrm (&ir)) |
7ad10968 | 5736 | return -1; |
cf648174 HZ |
5737 | if (ir.reg > 5) |
5738 | { | |
5739 | ir.addr -= 2; | |
5740 | opcode = opcode << 8 | ir.modrm; | |
5741 | goto no_support; | |
5742 | } | |
5743 | ||
5744 | if (ir.mod == 3) | |
25ea693b | 5745 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5746 | else |
5747 | { | |
5748 | ir.ot = OT_WORD; | |
5749 | if (i386_record_lea_modrm (&ir)) | |
5750 | return -1; | |
5751 | } | |
7ad10968 HZ |
5752 | break; |
5753 | ||
a38bba38 | 5754 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5755 | if (i386_record_modrm (&ir)) |
5756 | return -1; | |
7ad10968 HZ |
5757 | switch (ir.reg) |
5758 | { | |
5759 | case 0: | |
425b824a | 5760 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5761 | break; |
5762 | case 2: | |
425b824a | 5763 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5764 | break; |
5765 | case 3: | |
425b824a | 5766 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5767 | break; |
5768 | case 4: | |
425b824a | 5769 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5770 | break; |
5771 | case 5: | |
425b824a | 5772 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5773 | break; |
5774 | default: | |
5775 | ir.addr -= 2; | |
5776 | opcode = opcode << 8 | ir.modrm; | |
5777 | goto no_support; | |
5778 | break; | |
5779 | } | |
25ea693b MM |
5780 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5781 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5782 | break; |
5783 | ||
a38bba38 MS |
5784 | case 0x0fb6: /* movzbS */ |
5785 | case 0x0fb7: /* movzwS */ | |
5786 | case 0x0fbe: /* movsbS */ | |
5787 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5788 | if (i386_record_modrm (&ir)) |
5789 | return -1; | |
25ea693b | 5790 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5791 | break; |
5792 | ||
a38bba38 | 5793 | case 0x8d: /* lea */ |
7ad10968 HZ |
5794 | if (i386_record_modrm (&ir)) |
5795 | return -1; | |
5796 | if (ir.mod == 3) | |
5797 | { | |
5798 | ir.addr -= 2; | |
5799 | opcode = opcode << 8 | ir.modrm; | |
5800 | goto no_support; | |
5801 | } | |
7ad10968 | 5802 | ir.ot = ir.dflag; |
cf648174 HZ |
5803 | ir.reg |= rex_r; |
5804 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5805 | ir.reg &= 0x3; |
25ea693b | 5806 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5807 | break; |
5808 | ||
a38bba38 | 5809 | case 0xa0: /* mov EAX */ |
7ad10968 | 5810 | case 0xa1: |
a38bba38 MS |
5811 | |
5812 | case 0xd7: /* xlat */ | |
25ea693b | 5813 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5814 | break; |
5815 | ||
a38bba38 | 5816 | case 0xa2: /* mov EAX */ |
7ad10968 | 5817 | case 0xa3: |
d7877f7e | 5818 | if (ir.override >= 0) |
cf648174 | 5819 | { |
25ea693b | 5820 | if (record_full_memory_query) |
bb08c432 | 5821 | { |
651ce16a | 5822 | if (yquery (_("\ |
bb08c432 HZ |
5823 | Process record ignores the memory change of instruction at address %s\n\ |
5824 | because it can't get the value of the segment register.\n\ | |
5825 | Do you want to stop the program?"), | |
651ce16a | 5826 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
5827 | return -1; |
5828 | } | |
cf648174 HZ |
5829 | } |
5830 | else | |
5831 | { | |
5832 | if ((opcode & 1) == 0) | |
5833 | ir.ot = OT_BYTE; | |
5834 | else | |
5835 | ir.ot = ir.dflag + OT_WORD; | |
5836 | if (ir.aflag == 2) | |
5837 | { | |
4ffa4fc7 PA |
5838 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
5839 | return -1; | |
cf648174 | 5840 | ir.addr += 8; |
60a1502a | 5841 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5842 | } |
5843 | else if (ir.aflag) | |
5844 | { | |
4ffa4fc7 PA |
5845 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
5846 | return -1; | |
cf648174 | 5847 | ir.addr += 4; |
60a1502a | 5848 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5849 | } |
5850 | else | |
5851 | { | |
4ffa4fc7 PA |
5852 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
5853 | return -1; | |
cf648174 | 5854 | ir.addr += 2; |
60a1502a | 5855 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5856 | } |
25ea693b | 5857 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5858 | return -1; |
5859 | } | |
7ad10968 HZ |
5860 | break; |
5861 | ||
a38bba38 | 5862 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5863 | case 0xb1: |
5864 | case 0xb2: | |
5865 | case 0xb3: | |
5866 | case 0xb4: | |
5867 | case 0xb5: | |
5868 | case 0xb6: | |
5869 | case 0xb7: | |
25ea693b MM |
5870 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5871 | ? ((opcode & 0x7) | ir.rex_b) | |
5872 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5873 | break; |
5874 | ||
a38bba38 | 5875 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5876 | case 0xb9: |
5877 | case 0xba: | |
5878 | case 0xbb: | |
5879 | case 0xbc: | |
5880 | case 0xbd: | |
5881 | case 0xbe: | |
5882 | case 0xbf: | |
25ea693b | 5883 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5884 | break; |
5885 | ||
a38bba38 | 5886 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5887 | case 0x92: |
5888 | case 0x93: | |
5889 | case 0x94: | |
5890 | case 0x95: | |
5891 | case 0x96: | |
5892 | case 0x97: | |
25ea693b MM |
5893 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5894 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5895 | break; |
5896 | ||
a38bba38 | 5897 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5898 | case 0x87: |
5899 | if ((opcode & 1) == 0) | |
5900 | ir.ot = OT_BYTE; | |
5901 | else | |
5902 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5903 | if (i386_record_modrm (&ir)) |
5904 | return -1; | |
7ad10968 HZ |
5905 | if (ir.mod == 3) |
5906 | { | |
86839d38 | 5907 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5908 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5909 | ir.rm &= 0x3; | |
25ea693b | 5910 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5911 | } |
5912 | else | |
5913 | { | |
5914 | if (i386_record_lea_modrm (&ir)) | |
5915 | return -1; | |
5916 | } | |
cf648174 HZ |
5917 | ir.reg |= rex_r; |
5918 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5919 | ir.reg &= 0x3; |
25ea693b | 5920 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5921 | break; |
5922 | ||
a38bba38 MS |
5923 | case 0xc4: /* les Gv */ |
5924 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5925 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5926 | { | |
5927 | ir.addr -= 1; | |
5928 | goto no_support; | |
5929 | } | |
d3f323f3 | 5930 | /* FALLTHROUGH */ |
a38bba38 MS |
5931 | case 0x0fb2: /* lss Gv */ |
5932 | case 0x0fb4: /* lfs Gv */ | |
5933 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5934 | if (i386_record_modrm (&ir)) |
5935 | return -1; | |
5936 | if (ir.mod == 3) | |
5937 | { | |
5938 | if (opcode > 0xff) | |
5939 | ir.addr -= 3; | |
5940 | else | |
5941 | ir.addr -= 2; | |
5942 | opcode = opcode << 8 | ir.modrm; | |
5943 | goto no_support; | |
5944 | } | |
7ad10968 HZ |
5945 | switch (opcode) |
5946 | { | |
a38bba38 | 5947 | case 0xc4: /* les Gv */ |
425b824a | 5948 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5949 | break; |
a38bba38 | 5950 | case 0xc5: /* lds Gv */ |
425b824a | 5951 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5952 | break; |
a38bba38 | 5953 | case 0x0fb2: /* lss Gv */ |
425b824a | 5954 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5955 | break; |
a38bba38 | 5956 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5957 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5958 | break; |
a38bba38 | 5959 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5960 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5961 | break; |
5962 | } | |
25ea693b MM |
5963 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5964 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5965 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5966 | break; |
5967 | ||
a38bba38 | 5968 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5969 | case 0xc1: |
5970 | case 0xd0: | |
5971 | case 0xd1: | |
5972 | case 0xd2: | |
5973 | case 0xd3: | |
5974 | if ((opcode & 1) == 0) | |
5975 | ir.ot = OT_BYTE; | |
5976 | else | |
5977 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5978 | if (i386_record_modrm (&ir)) |
5979 | return -1; | |
7ad10968 HZ |
5980 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5981 | { | |
5982 | if (i386_record_lea_modrm (&ir)) | |
5983 | return -1; | |
5984 | } | |
5985 | else | |
5986 | { | |
cf648174 HZ |
5987 | ir.rm |= ir.rex_b; |
5988 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5989 | ir.rm &= 0x3; |
25ea693b | 5990 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5991 | } |
25ea693b | 5992 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5993 | break; |
5994 | ||
5995 | case 0x0fa4: | |
5996 | case 0x0fa5: | |
5997 | case 0x0fac: | |
5998 | case 0x0fad: | |
5999 | if (i386_record_modrm (&ir)) | |
6000 | return -1; | |
6001 | if (ir.mod == 3) | |
6002 | { | |
25ea693b | 6003 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
6004 | return -1; |
6005 | } | |
6006 | else | |
6007 | { | |
6008 | if (i386_record_lea_modrm (&ir)) | |
6009 | return -1; | |
6010 | } | |
6011 | break; | |
6012 | ||
a38bba38 | 6013 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
6014 | case 0xd9: |
6015 | case 0xda: | |
6016 | case 0xdb: | |
6017 | case 0xdc: | |
6018 | case 0xdd: | |
6019 | case 0xde: | |
6020 | case 0xdf: | |
6021 | if (i386_record_modrm (&ir)) | |
6022 | return -1; | |
6023 | ir.reg |= ((opcode & 7) << 3); | |
6024 | if (ir.mod != 3) | |
6025 | { | |
1777feb0 | 6026 | /* Memory. */ |
955db0c0 | 6027 | uint64_t addr64; |
7ad10968 | 6028 | |
955db0c0 | 6029 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
6030 | return -1; |
6031 | switch (ir.reg) | |
6032 | { | |
7ad10968 | 6033 | case 0x02: |
0289bdd7 MS |
6034 | case 0x12: |
6035 | case 0x22: | |
6036 | case 0x32: | |
6037 | /* For fcom, ficom nothing to do. */ | |
6038 | break; | |
7ad10968 | 6039 | case 0x03: |
0289bdd7 MS |
6040 | case 0x13: |
6041 | case 0x23: | |
6042 | case 0x33: | |
6043 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
6044 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6045 | return -1; | |
6046 | break; | |
6047 | case 0x00: | |
6048 | case 0x01: | |
7ad10968 HZ |
6049 | case 0x04: |
6050 | case 0x05: | |
6051 | case 0x06: | |
6052 | case 0x07: | |
6053 | case 0x10: | |
6054 | case 0x11: | |
7ad10968 HZ |
6055 | case 0x14: |
6056 | case 0x15: | |
6057 | case 0x16: | |
6058 | case 0x17: | |
6059 | case 0x20: | |
6060 | case 0x21: | |
7ad10968 HZ |
6061 | case 0x24: |
6062 | case 0x25: | |
6063 | case 0x26: | |
6064 | case 0x27: | |
6065 | case 0x30: | |
6066 | case 0x31: | |
7ad10968 HZ |
6067 | case 0x34: |
6068 | case 0x35: | |
6069 | case 0x36: | |
6070 | case 0x37: | |
0289bdd7 MS |
6071 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
6072 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
6073 | of code, always affects st(0) register. */ | |
6074 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6075 | return -1; | |
7ad10968 HZ |
6076 | break; |
6077 | case 0x08: | |
6078 | case 0x0a: | |
6079 | case 0x0b: | |
6080 | case 0x18: | |
6081 | case 0x19: | |
6082 | case 0x1a: | |
6083 | case 0x1b: | |
0289bdd7 | 6084 | case 0x1d: |
7ad10968 HZ |
6085 | case 0x28: |
6086 | case 0x29: | |
6087 | case 0x2a: | |
6088 | case 0x2b: | |
6089 | case 0x38: | |
6090 | case 0x39: | |
6091 | case 0x3a: | |
6092 | case 0x3b: | |
0289bdd7 MS |
6093 | case 0x3c: |
6094 | case 0x3d: | |
7ad10968 HZ |
6095 | switch (ir.reg & 7) |
6096 | { | |
6097 | case 0: | |
0289bdd7 MS |
6098 | /* Handling fld, fild. */ |
6099 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6100 | return -1; | |
7ad10968 HZ |
6101 | break; |
6102 | case 1: | |
6103 | switch (ir.reg >> 4) | |
6104 | { | |
6105 | case 0: | |
25ea693b | 6106 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
6107 | return -1; |
6108 | break; | |
6109 | case 2: | |
25ea693b | 6110 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
6111 | return -1; |
6112 | break; | |
6113 | case 3: | |
0289bdd7 | 6114 | break; |
7ad10968 | 6115 | default: |
25ea693b | 6116 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6117 | return -1; |
6118 | break; | |
6119 | } | |
6120 | break; | |
6121 | default: | |
6122 | switch (ir.reg >> 4) | |
6123 | { | |
6124 | case 0: | |
25ea693b | 6125 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
6126 | return -1; |
6127 | if (3 == (ir.reg & 7)) | |
6128 | { | |
6129 | /* For fstp m32fp. */ | |
6130 | if (i386_record_floats (gdbarch, &ir, | |
6131 | I386_SAVE_FPU_REGS)) | |
6132 | return -1; | |
6133 | } | |
6134 | break; | |
7ad10968 | 6135 | case 1: |
25ea693b | 6136 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 6137 | return -1; |
0289bdd7 MS |
6138 | if ((3 == (ir.reg & 7)) |
6139 | || (5 == (ir.reg & 7)) | |
6140 | || (7 == (ir.reg & 7))) | |
6141 | { | |
6142 | /* For fstp insn. */ | |
6143 | if (i386_record_floats (gdbarch, &ir, | |
6144 | I386_SAVE_FPU_REGS)) | |
6145 | return -1; | |
6146 | } | |
7ad10968 HZ |
6147 | break; |
6148 | case 2: | |
25ea693b | 6149 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6150 | return -1; |
0289bdd7 MS |
6151 | if (3 == (ir.reg & 7)) |
6152 | { | |
6153 | /* For fstp m64fp. */ | |
6154 | if (i386_record_floats (gdbarch, &ir, | |
6155 | I386_SAVE_FPU_REGS)) | |
6156 | return -1; | |
6157 | } | |
7ad10968 HZ |
6158 | break; |
6159 | case 3: | |
0289bdd7 MS |
6160 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
6161 | { | |
6162 | /* For fistp, fbld, fild, fbstp. */ | |
6163 | if (i386_record_floats (gdbarch, &ir, | |
6164 | I386_SAVE_FPU_REGS)) | |
6165 | return -1; | |
6166 | } | |
6167 | /* Fall through */ | |
7ad10968 | 6168 | default: |
25ea693b | 6169 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6170 | return -1; |
6171 | break; | |
6172 | } | |
6173 | break; | |
6174 | } | |
6175 | break; | |
6176 | case 0x0c: | |
0289bdd7 MS |
6177 | /* Insn fldenv. */ |
6178 | if (i386_record_floats (gdbarch, &ir, | |
6179 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6180 | return -1; | |
6181 | break; | |
7ad10968 | 6182 | case 0x0d: |
0289bdd7 MS |
6183 | /* Insn fldcw. */ |
6184 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
6185 | return -1; | |
6186 | break; | |
7ad10968 | 6187 | case 0x2c: |
0289bdd7 MS |
6188 | /* Insn frstor. */ |
6189 | if (i386_record_floats (gdbarch, &ir, | |
6190 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6191 | return -1; | |
7ad10968 HZ |
6192 | break; |
6193 | case 0x0e: | |
6194 | if (ir.dflag) | |
6195 | { | |
25ea693b | 6196 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
6197 | return -1; |
6198 | } | |
6199 | else | |
6200 | { | |
25ea693b | 6201 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
6202 | return -1; |
6203 | } | |
6204 | break; | |
6205 | case 0x0f: | |
6206 | case 0x2f: | |
25ea693b | 6207 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6208 | return -1; |
0289bdd7 MS |
6209 | /* Insn fstp, fbstp. */ |
6210 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6211 | return -1; | |
7ad10968 HZ |
6212 | break; |
6213 | case 0x1f: | |
6214 | case 0x3e: | |
25ea693b | 6215 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
6216 | return -1; |
6217 | break; | |
6218 | case 0x2e: | |
6219 | if (ir.dflag) | |
6220 | { | |
25ea693b | 6221 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 6222 | return -1; |
955db0c0 | 6223 | addr64 += 28; |
7ad10968 HZ |
6224 | } |
6225 | else | |
6226 | { | |
25ea693b | 6227 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 6228 | return -1; |
955db0c0 | 6229 | addr64 += 14; |
7ad10968 | 6230 | } |
25ea693b | 6231 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 6232 | return -1; |
0289bdd7 MS |
6233 | /* Insn fsave. */ |
6234 | if (i386_record_floats (gdbarch, &ir, | |
6235 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6236 | return -1; | |
7ad10968 HZ |
6237 | break; |
6238 | case 0x3f: | |
25ea693b | 6239 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6240 | return -1; |
0289bdd7 MS |
6241 | /* Insn fistp. */ |
6242 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6243 | return -1; | |
7ad10968 HZ |
6244 | break; |
6245 | default: | |
6246 | ir.addr -= 2; | |
6247 | opcode = opcode << 8 | ir.modrm; | |
6248 | goto no_support; | |
6249 | break; | |
6250 | } | |
6251 | } | |
0289bdd7 MS |
6252 | /* Opcode is an extension of modR/M byte. */ |
6253 | else | |
6254 | { | |
6255 | switch (opcode) | |
6256 | { | |
6257 | case 0xd8: | |
6258 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6259 | return -1; | |
6260 | break; | |
6261 | case 0xd9: | |
6262 | if (0x0c == (ir.modrm >> 4)) | |
6263 | { | |
6264 | if ((ir.modrm & 0x0f) <= 7) | |
6265 | { | |
6266 | if (i386_record_floats (gdbarch, &ir, | |
6267 | I386_SAVE_FPU_REGS)) | |
6268 | return -1; | |
6269 | } | |
6270 | else | |
6271 | { | |
6272 | if (i386_record_floats (gdbarch, &ir, | |
6273 | I387_ST0_REGNUM (tdep))) | |
6274 | return -1; | |
6275 | /* If only st(0) is changing, then we have already | |
6276 | recorded. */ | |
6277 | if ((ir.modrm & 0x0f) - 0x08) | |
6278 | { | |
6279 | if (i386_record_floats (gdbarch, &ir, | |
6280 | I387_ST0_REGNUM (tdep) + | |
6281 | ((ir.modrm & 0x0f) - 0x08))) | |
6282 | return -1; | |
6283 | } | |
6284 | } | |
6285 | } | |
6286 | else | |
6287 | { | |
6288 | switch (ir.modrm) | |
6289 | { | |
6290 | case 0xe0: | |
6291 | case 0xe1: | |
6292 | case 0xf0: | |
6293 | case 0xf5: | |
6294 | case 0xf8: | |
6295 | case 0xfa: | |
6296 | case 0xfc: | |
6297 | case 0xfe: | |
6298 | case 0xff: | |
6299 | if (i386_record_floats (gdbarch, &ir, | |
6300 | I387_ST0_REGNUM (tdep))) | |
6301 | return -1; | |
6302 | break; | |
6303 | case 0xf1: | |
6304 | case 0xf2: | |
6305 | case 0xf3: | |
6306 | case 0xf4: | |
6307 | case 0xf6: | |
6308 | case 0xf7: | |
6309 | case 0xe8: | |
6310 | case 0xe9: | |
6311 | case 0xea: | |
6312 | case 0xeb: | |
6313 | case 0xec: | |
6314 | case 0xed: | |
6315 | case 0xee: | |
6316 | case 0xf9: | |
6317 | case 0xfb: | |
6318 | if (i386_record_floats (gdbarch, &ir, | |
6319 | I386_SAVE_FPU_REGS)) | |
6320 | return -1; | |
6321 | break; | |
6322 | case 0xfd: | |
6323 | if (i386_record_floats (gdbarch, &ir, | |
6324 | I387_ST0_REGNUM (tdep))) | |
6325 | return -1; | |
6326 | if (i386_record_floats (gdbarch, &ir, | |
6327 | I387_ST0_REGNUM (tdep) + 1)) | |
6328 | return -1; | |
6329 | break; | |
6330 | } | |
6331 | } | |
6332 | break; | |
6333 | case 0xda: | |
6334 | if (0xe9 == ir.modrm) | |
6335 | { | |
6336 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6337 | return -1; | |
6338 | } | |
6339 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6340 | { | |
6341 | if (i386_record_floats (gdbarch, &ir, | |
6342 | I387_ST0_REGNUM (tdep))) | |
6343 | return -1; | |
6344 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6345 | { | |
6346 | if (i386_record_floats (gdbarch, &ir, | |
6347 | I387_ST0_REGNUM (tdep) + | |
6348 | (ir.modrm & 0x0f))) | |
6349 | return -1; | |
6350 | } | |
6351 | else if ((ir.modrm & 0x0f) - 0x08) | |
6352 | { | |
6353 | if (i386_record_floats (gdbarch, &ir, | |
6354 | I387_ST0_REGNUM (tdep) + | |
6355 | ((ir.modrm & 0x0f) - 0x08))) | |
6356 | return -1; | |
6357 | } | |
6358 | } | |
6359 | break; | |
6360 | case 0xdb: | |
6361 | if (0xe3 == ir.modrm) | |
6362 | { | |
6363 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
6364 | return -1; | |
6365 | } | |
6366 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6367 | { | |
6368 | if (i386_record_floats (gdbarch, &ir, | |
6369 | I387_ST0_REGNUM (tdep))) | |
6370 | return -1; | |
6371 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6372 | { | |
6373 | if (i386_record_floats (gdbarch, &ir, | |
6374 | I387_ST0_REGNUM (tdep) + | |
6375 | (ir.modrm & 0x0f))) | |
6376 | return -1; | |
6377 | } | |
6378 | else if ((ir.modrm & 0x0f) - 0x08) | |
6379 | { | |
6380 | if (i386_record_floats (gdbarch, &ir, | |
6381 | I387_ST0_REGNUM (tdep) + | |
6382 | ((ir.modrm & 0x0f) - 0x08))) | |
6383 | return -1; | |
6384 | } | |
6385 | } | |
6386 | break; | |
6387 | case 0xdc: | |
6388 | if ((0x0c == ir.modrm >> 4) | |
6389 | || (0x0d == ir.modrm >> 4) | |
6390 | || (0x0f == ir.modrm >> 4)) | |
6391 | { | |
6392 | if ((ir.modrm & 0x0f) <= 7) | |
6393 | { | |
6394 | if (i386_record_floats (gdbarch, &ir, | |
6395 | I387_ST0_REGNUM (tdep) + | |
6396 | (ir.modrm & 0x0f))) | |
6397 | return -1; | |
6398 | } | |
6399 | else | |
6400 | { | |
6401 | if (i386_record_floats (gdbarch, &ir, | |
6402 | I387_ST0_REGNUM (tdep) + | |
6403 | ((ir.modrm & 0x0f) - 0x08))) | |
6404 | return -1; | |
6405 | } | |
6406 | } | |
6407 | break; | |
6408 | case 0xdd: | |
6409 | if (0x0c == ir.modrm >> 4) | |
6410 | { | |
6411 | if (i386_record_floats (gdbarch, &ir, | |
6412 | I387_FTAG_REGNUM (tdep))) | |
6413 | return -1; | |
6414 | } | |
6415 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6416 | { | |
6417 | if ((ir.modrm & 0x0f) <= 7) | |
6418 | { | |
6419 | if (i386_record_floats (gdbarch, &ir, | |
6420 | I387_ST0_REGNUM (tdep) + | |
6421 | (ir.modrm & 0x0f))) | |
6422 | return -1; | |
6423 | } | |
6424 | else | |
6425 | { | |
6426 | if (i386_record_floats (gdbarch, &ir, | |
6427 | I386_SAVE_FPU_REGS)) | |
6428 | return -1; | |
6429 | } | |
6430 | } | |
6431 | break; | |
6432 | case 0xde: | |
6433 | if ((0x0c == ir.modrm >> 4) | |
6434 | || (0x0e == ir.modrm >> 4) | |
6435 | || (0x0f == ir.modrm >> 4) | |
6436 | || (0xd9 == ir.modrm)) | |
6437 | { | |
6438 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6439 | return -1; | |
6440 | } | |
6441 | break; | |
6442 | case 0xdf: | |
6443 | if (0xe0 == ir.modrm) | |
6444 | { | |
25ea693b MM |
6445 | if (record_full_arch_list_add_reg (ir.regcache, |
6446 | I386_EAX_REGNUM)) | |
0289bdd7 MS |
6447 | return -1; |
6448 | } | |
6449 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6450 | { | |
6451 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6452 | return -1; | |
6453 | } | |
6454 | break; | |
6455 | } | |
6456 | } | |
7ad10968 | 6457 | break; |
7ad10968 | 6458 | /* string ops */ |
a38bba38 | 6459 | case 0xa4: /* movsS */ |
7ad10968 | 6460 | case 0xa5: |
a38bba38 | 6461 | case 0xaa: /* stosS */ |
7ad10968 | 6462 | case 0xab: |
a38bba38 | 6463 | case 0x6c: /* insS */ |
7ad10968 | 6464 | case 0x6d: |
cf648174 | 6465 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 6466 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
6467 | &addr); |
6468 | if (addr) | |
cf648174 | 6469 | { |
77d7dc92 HZ |
6470 | ULONGEST es, ds; |
6471 | ||
6472 | if ((opcode & 1) == 0) | |
6473 | ir.ot = OT_BYTE; | |
6474 | else | |
6475 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
6476 | regcache_raw_read_unsigned (ir.regcache, |
6477 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 6478 | &addr); |
77d7dc92 | 6479 | |
d7877f7e HZ |
6480 | regcache_raw_read_unsigned (ir.regcache, |
6481 | ir.regmap[X86_RECORD_ES_REGNUM], | |
6482 | &es); | |
6483 | regcache_raw_read_unsigned (ir.regcache, | |
6484 | ir.regmap[X86_RECORD_DS_REGNUM], | |
6485 | &ds); | |
6486 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
6487 | { |
6488 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
25ea693b | 6489 | if (record_full_memory_query) |
bb08c432 | 6490 | { |
651ce16a | 6491 | if (yquery (_("\ |
bb08c432 HZ |
6492 | Process record ignores the memory change of instruction at address %s\n\ |
6493 | because it can't get the value of the segment register.\n\ | |
6494 | Do you want to stop the program?"), | |
651ce16a | 6495 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
6496 | return -1; |
6497 | } | |
df61f520 HZ |
6498 | } |
6499 | else | |
6500 | { | |
25ea693b | 6501 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 6502 | return -1; |
77d7dc92 HZ |
6503 | } |
6504 | ||
6505 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
25ea693b | 6506 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
77d7dc92 | 6507 | if (opcode == 0xa4 || opcode == 0xa5) |
25ea693b MM |
6508 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
6509 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6510 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 6511 | } |
cf648174 | 6512 | break; |
7ad10968 | 6513 | |
a38bba38 | 6514 | case 0xa6: /* cmpsS */ |
cf648174 | 6515 | case 0xa7: |
25ea693b MM |
6516 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6517 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6518 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6519 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6520 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6521 | break; |
6522 | ||
a38bba38 | 6523 | case 0xac: /* lodsS */ |
7ad10968 | 6524 | case 0xad: |
25ea693b MM |
6525 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6526 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6527 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6528 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6529 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6530 | break; |
6531 | ||
a38bba38 | 6532 | case 0xae: /* scasS */ |
7ad10968 | 6533 | case 0xaf: |
25ea693b | 6534 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6535 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6536 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6537 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6538 | break; |
6539 | ||
a38bba38 | 6540 | case 0x6e: /* outsS */ |
cf648174 | 6541 | case 0x6f: |
25ea693b | 6542 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6543 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6544 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6545 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6546 | break; |
6547 | ||
a38bba38 | 6548 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6549 | case 0xe5: |
6550 | case 0xec: | |
6551 | case 0xed: | |
25ea693b MM |
6552 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6553 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6554 | break; |
6555 | ||
6556 | case 0xe6: | |
6557 | case 0xe7: | |
6558 | case 0xee: | |
6559 | case 0xef: | |
6560 | break; | |
6561 | ||
6562 | /* control */ | |
a38bba38 MS |
6563 | case 0xc2: /* ret im */ |
6564 | case 0xc3: /* ret */ | |
25ea693b MM |
6565 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6566 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6567 | break; |
6568 | ||
a38bba38 MS |
6569 | case 0xca: /* lret im */ |
6570 | case 0xcb: /* lret */ | |
6571 | case 0xcf: /* iret */ | |
25ea693b MM |
6572 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6573 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6574 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6575 | break; |
6576 | ||
a38bba38 | 6577 | case 0xe8: /* call im */ |
cf648174 HZ |
6578 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6579 | ir.dflag = 2; | |
6580 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6581 | return -1; | |
7ad10968 HZ |
6582 | break; |
6583 | ||
a38bba38 | 6584 | case 0x9a: /* lcall im */ |
cf648174 HZ |
6585 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6586 | { | |
6587 | ir.addr -= 1; | |
6588 | goto no_support; | |
6589 | } | |
25ea693b | 6590 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 HZ |
6591 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
6592 | return -1; | |
7ad10968 HZ |
6593 | break; |
6594 | ||
a38bba38 MS |
6595 | case 0xe9: /* jmp im */ |
6596 | case 0xea: /* ljmp im */ | |
6597 | case 0xeb: /* jmp Jb */ | |
6598 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6599 | case 0x71: |
6600 | case 0x72: | |
6601 | case 0x73: | |
6602 | case 0x74: | |
6603 | case 0x75: | |
6604 | case 0x76: | |
6605 | case 0x77: | |
6606 | case 0x78: | |
6607 | case 0x79: | |
6608 | case 0x7a: | |
6609 | case 0x7b: | |
6610 | case 0x7c: | |
6611 | case 0x7d: | |
6612 | case 0x7e: | |
6613 | case 0x7f: | |
a38bba38 | 6614 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6615 | case 0x0f81: |
6616 | case 0x0f82: | |
6617 | case 0x0f83: | |
6618 | case 0x0f84: | |
6619 | case 0x0f85: | |
6620 | case 0x0f86: | |
6621 | case 0x0f87: | |
6622 | case 0x0f88: | |
6623 | case 0x0f89: | |
6624 | case 0x0f8a: | |
6625 | case 0x0f8b: | |
6626 | case 0x0f8c: | |
6627 | case 0x0f8d: | |
6628 | case 0x0f8e: | |
6629 | case 0x0f8f: | |
6630 | break; | |
6631 | ||
a38bba38 | 6632 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6633 | case 0x0f91: |
6634 | case 0x0f92: | |
6635 | case 0x0f93: | |
6636 | case 0x0f94: | |
6637 | case 0x0f95: | |
6638 | case 0x0f96: | |
6639 | case 0x0f97: | |
6640 | case 0x0f98: | |
6641 | case 0x0f99: | |
6642 | case 0x0f9a: | |
6643 | case 0x0f9b: | |
6644 | case 0x0f9c: | |
6645 | case 0x0f9d: | |
6646 | case 0x0f9e: | |
6647 | case 0x0f9f: | |
25ea693b | 6648 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6649 | ir.ot = OT_BYTE; |
6650 | if (i386_record_modrm (&ir)) | |
6651 | return -1; | |
6652 | if (ir.mod == 3) | |
25ea693b MM |
6653 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
6654 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
6655 | else |
6656 | { | |
6657 | if (i386_record_lea_modrm (&ir)) | |
6658 | return -1; | |
6659 | } | |
6660 | break; | |
6661 | ||
a38bba38 | 6662 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6663 | case 0x0f41: |
6664 | case 0x0f42: | |
6665 | case 0x0f43: | |
6666 | case 0x0f44: | |
6667 | case 0x0f45: | |
6668 | case 0x0f46: | |
6669 | case 0x0f47: | |
6670 | case 0x0f48: | |
6671 | case 0x0f49: | |
6672 | case 0x0f4a: | |
6673 | case 0x0f4b: | |
6674 | case 0x0f4c: | |
6675 | case 0x0f4d: | |
6676 | case 0x0f4e: | |
6677 | case 0x0f4f: | |
6678 | if (i386_record_modrm (&ir)) | |
6679 | return -1; | |
cf648174 | 6680 | ir.reg |= rex_r; |
7ad10968 HZ |
6681 | if (ir.dflag == OT_BYTE) |
6682 | ir.reg &= 0x3; | |
25ea693b | 6683 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6684 | break; |
6685 | ||
6686 | /* flags */ | |
a38bba38 | 6687 | case 0x9c: /* pushf */ |
25ea693b | 6688 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6689 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6690 | ir.dflag = 2; | |
6691 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6692 | return -1; | |
7ad10968 HZ |
6693 | break; |
6694 | ||
a38bba38 | 6695 | case 0x9d: /* popf */ |
25ea693b MM |
6696 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6697 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6698 | break; |
6699 | ||
a38bba38 | 6700 | case 0x9e: /* sahf */ |
cf648174 HZ |
6701 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6702 | { | |
6703 | ir.addr -= 1; | |
6704 | goto no_support; | |
6705 | } | |
d3f323f3 | 6706 | /* FALLTHROUGH */ |
a38bba38 MS |
6707 | case 0xf5: /* cmc */ |
6708 | case 0xf8: /* clc */ | |
6709 | case 0xf9: /* stc */ | |
6710 | case 0xfc: /* cld */ | |
6711 | case 0xfd: /* std */ | |
25ea693b | 6712 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6713 | break; |
6714 | ||
a38bba38 | 6715 | case 0x9f: /* lahf */ |
cf648174 HZ |
6716 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6717 | { | |
6718 | ir.addr -= 1; | |
6719 | goto no_support; | |
6720 | } | |
25ea693b MM |
6721 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6722 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6723 | break; |
6724 | ||
6725 | /* bit operations */ | |
a38bba38 | 6726 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6727 | ir.ot = ir.dflag + OT_WORD; |
6728 | if (i386_record_modrm (&ir)) | |
6729 | return -1; | |
6730 | if (ir.reg < 4) | |
6731 | { | |
cf648174 | 6732 | ir.addr -= 2; |
7ad10968 HZ |
6733 | opcode = opcode << 8 | ir.modrm; |
6734 | goto no_support; | |
6735 | } | |
cf648174 | 6736 | if (ir.reg != 4) |
7ad10968 | 6737 | { |
cf648174 | 6738 | if (ir.mod == 3) |
25ea693b | 6739 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6740 | else |
6741 | { | |
cf648174 | 6742 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6743 | return -1; |
6744 | } | |
6745 | } | |
25ea693b | 6746 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6747 | break; |
6748 | ||
a38bba38 | 6749 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6750 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6751 | break; |
6752 | ||
a38bba38 MS |
6753 | case 0x0fab: /* bts */ |
6754 | case 0x0fb3: /* btr */ | |
6755 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6756 | ir.ot = ir.dflag + OT_WORD; |
6757 | if (i386_record_modrm (&ir)) | |
6758 | return -1; | |
6759 | if (ir.mod == 3) | |
25ea693b | 6760 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 HZ |
6761 | else |
6762 | { | |
955db0c0 MS |
6763 | uint64_t addr64; |
6764 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6765 | return -1; |
6766 | regcache_raw_read_unsigned (ir.regcache, | |
6767 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6768 | &addr); |
cf648174 HZ |
6769 | switch (ir.dflag) |
6770 | { | |
6771 | case 0: | |
648d0c8b | 6772 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6773 | break; |
6774 | case 1: | |
648d0c8b | 6775 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6776 | break; |
6777 | case 2: | |
648d0c8b | 6778 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6779 | break; |
6780 | } | |
25ea693b | 6781 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6782 | return -1; |
6783 | if (i386_record_lea_modrm (&ir)) | |
6784 | return -1; | |
6785 | } | |
25ea693b | 6786 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6787 | break; |
6788 | ||
a38bba38 MS |
6789 | case 0x0fbc: /* bsf */ |
6790 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6791 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6792 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6793 | break; |
6794 | ||
6795 | /* bcd */ | |
a38bba38 MS |
6796 | case 0x27: /* daa */ |
6797 | case 0x2f: /* das */ | |
6798 | case 0x37: /* aaa */ | |
6799 | case 0x3f: /* aas */ | |
6800 | case 0xd4: /* aam */ | |
6801 | case 0xd5: /* aad */ | |
cf648174 HZ |
6802 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6803 | { | |
6804 | ir.addr -= 1; | |
6805 | goto no_support; | |
6806 | } | |
25ea693b MM |
6807 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6808 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6809 | break; |
6810 | ||
6811 | /* misc */ | |
a38bba38 | 6812 | case 0x90: /* nop */ |
7ad10968 HZ |
6813 | if (prefixes & PREFIX_LOCK) |
6814 | { | |
6815 | ir.addr -= 1; | |
6816 | goto no_support; | |
6817 | } | |
6818 | break; | |
6819 | ||
a38bba38 | 6820 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6821 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6822 | return -1; | |
425b824a | 6823 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6824 | ir.addr++; |
6825 | goto reswitch; | |
7ad10968 HZ |
6826 | break; |
6827 | ||
7ad10968 | 6828 | /* XXX */ |
a38bba38 | 6829 | case 0xcc: /* int3 */ |
a3c4230a | 6830 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6831 | "int3.\n")); |
6832 | ir.addr -= 1; | |
6833 | goto no_support; | |
6834 | break; | |
6835 | ||
7ad10968 | 6836 | /* XXX */ |
a38bba38 | 6837 | case 0xcd: /* int */ |
7ad10968 HZ |
6838 | { |
6839 | int ret; | |
425b824a | 6840 | uint8_t interrupt; |
4ffa4fc7 PA |
6841 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6842 | return -1; | |
7ad10968 | 6843 | ir.addr++; |
425b824a | 6844 | if (interrupt != 0x80 |
a3c4230a | 6845 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6846 | { |
a3c4230a | 6847 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6848 | "instruction int 0x%02x.\n"), |
425b824a | 6849 | interrupt); |
7ad10968 HZ |
6850 | ir.addr -= 2; |
6851 | goto no_support; | |
6852 | } | |
a3c4230a | 6853 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6854 | if (ret) |
6855 | return ret; | |
6856 | } | |
6857 | break; | |
6858 | ||
7ad10968 | 6859 | /* XXX */ |
a38bba38 | 6860 | case 0xce: /* into */ |
a3c4230a | 6861 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6862 | "instruction into.\n")); |
6863 | ir.addr -= 1; | |
6864 | goto no_support; | |
6865 | break; | |
6866 | ||
a38bba38 MS |
6867 | case 0xfa: /* cli */ |
6868 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6869 | break; |
6870 | ||
a38bba38 | 6871 | case 0x62: /* bound */ |
a3c4230a | 6872 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6873 | "instruction bound.\n")); |
6874 | ir.addr -= 1; | |
6875 | goto no_support; | |
6876 | break; | |
6877 | ||
a38bba38 | 6878 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6879 | case 0x0fc9: |
6880 | case 0x0fca: | |
6881 | case 0x0fcb: | |
6882 | case 0x0fcc: | |
6883 | case 0x0fcd: | |
6884 | case 0x0fce: | |
6885 | case 0x0fcf: | |
25ea693b | 6886 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6887 | break; |
6888 | ||
a38bba38 | 6889 | case 0xd6: /* salc */ |
cf648174 HZ |
6890 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6891 | { | |
6892 | ir.addr -= 1; | |
6893 | goto no_support; | |
6894 | } | |
25ea693b MM |
6895 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6896 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6897 | break; |
6898 | ||
a38bba38 MS |
6899 | case 0xe0: /* loopnz */ |
6900 | case 0xe1: /* loopz */ | |
6901 | case 0xe2: /* loop */ | |
6902 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6903 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6904 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6905 | break; |
6906 | ||
a38bba38 | 6907 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6908 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6909 | "instruction wrmsr.\n")); |
6910 | ir.addr -= 2; | |
6911 | goto no_support; | |
6912 | break; | |
6913 | ||
a38bba38 | 6914 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6915 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6916 | "instruction rdmsr.\n")); |
6917 | ir.addr -= 2; | |
6918 | goto no_support; | |
6919 | break; | |
6920 | ||
a38bba38 | 6921 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6922 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6923 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6924 | break; |
6925 | ||
a38bba38 | 6926 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6927 | { |
6928 | int ret; | |
cf648174 HZ |
6929 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6930 | { | |
6931 | ir.addr -= 2; | |
6932 | goto no_support; | |
6933 | } | |
a3c4230a | 6934 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6935 | { |
a3c4230a | 6936 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6937 | "instruction sysenter.\n")); |
6938 | ir.addr -= 2; | |
6939 | goto no_support; | |
6940 | } | |
a3c4230a | 6941 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6942 | if (ret) |
6943 | return ret; | |
6944 | } | |
6945 | break; | |
6946 | ||
a38bba38 | 6947 | case 0x0f35: /* sysexit */ |
a3c4230a | 6948 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6949 | "instruction sysexit.\n")); |
6950 | ir.addr -= 2; | |
6951 | goto no_support; | |
6952 | break; | |
6953 | ||
a38bba38 | 6954 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6955 | { |
6956 | int ret; | |
a3c4230a | 6957 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6958 | { |
a3c4230a | 6959 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6960 | "instruction syscall.\n")); |
6961 | ir.addr -= 2; | |
6962 | goto no_support; | |
6963 | } | |
a3c4230a | 6964 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6965 | if (ret) |
6966 | return ret; | |
6967 | } | |
6968 | break; | |
6969 | ||
a38bba38 | 6970 | case 0x0f07: /* sysret */ |
a3c4230a | 6971 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6972 | "instruction sysret.\n")); |
6973 | ir.addr -= 2; | |
6974 | goto no_support; | |
6975 | break; | |
6976 | ||
a38bba38 | 6977 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
6978 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6979 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6980 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6981 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6982 | break; |
6983 | ||
a38bba38 | 6984 | case 0xf4: /* hlt */ |
a3c4230a | 6985 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6986 | "instruction hlt.\n")); |
6987 | ir.addr -= 1; | |
6988 | goto no_support; | |
6989 | break; | |
6990 | ||
6991 | case 0x0f00: | |
6992 | if (i386_record_modrm (&ir)) | |
6993 | return -1; | |
6994 | switch (ir.reg) | |
6995 | { | |
a38bba38 MS |
6996 | case 0: /* sldt */ |
6997 | case 1: /* str */ | |
7ad10968 | 6998 | if (ir.mod == 3) |
25ea693b | 6999 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7000 | else |
7001 | { | |
7002 | ir.ot = OT_WORD; | |
7003 | if (i386_record_lea_modrm (&ir)) | |
7004 | return -1; | |
7005 | } | |
7006 | break; | |
a38bba38 MS |
7007 | case 2: /* lldt */ |
7008 | case 3: /* ltr */ | |
7ad10968 | 7009 | break; |
a38bba38 MS |
7010 | case 4: /* verr */ |
7011 | case 5: /* verw */ | |
25ea693b | 7012 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7013 | break; |
7014 | default: | |
7015 | ir.addr -= 3; | |
7016 | opcode = opcode << 8 | ir.modrm; | |
7017 | goto no_support; | |
7018 | break; | |
7019 | } | |
7020 | break; | |
7021 | ||
7022 | case 0x0f01: | |
7023 | if (i386_record_modrm (&ir)) | |
7024 | return -1; | |
7025 | switch (ir.reg) | |
7026 | { | |
a38bba38 | 7027 | case 0: /* sgdt */ |
7ad10968 | 7028 | { |
955db0c0 | 7029 | uint64_t addr64; |
7ad10968 HZ |
7030 | |
7031 | if (ir.mod == 3) | |
7032 | { | |
7033 | ir.addr -= 3; | |
7034 | opcode = opcode << 8 | ir.modrm; | |
7035 | goto no_support; | |
7036 | } | |
d7877f7e | 7037 | if (ir.override >= 0) |
7ad10968 | 7038 | { |
25ea693b | 7039 | if (record_full_memory_query) |
bb08c432 | 7040 | { |
651ce16a | 7041 | if (yquery (_("\ |
bb08c432 HZ |
7042 | Process record ignores the memory change of instruction at address %s\n\ |
7043 | because it can't get the value of the segment register.\n\ | |
7044 | Do you want to stop the program?"), | |
651ce16a PA |
7045 | paddress (gdbarch, ir.orig_addr))) |
7046 | return -1; | |
bb08c432 | 7047 | } |
7ad10968 HZ |
7048 | } |
7049 | else | |
7050 | { | |
955db0c0 | 7051 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7052 | return -1; |
25ea693b | 7053 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7054 | return -1; |
955db0c0 | 7055 | addr64 += 2; |
cf648174 HZ |
7056 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7057 | { | |
25ea693b | 7058 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7059 | return -1; |
7060 | } | |
7061 | else | |
7062 | { | |
25ea693b | 7063 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7064 | return -1; |
7065 | } | |
7ad10968 HZ |
7066 | } |
7067 | } | |
7068 | break; | |
7069 | case 1: | |
7070 | if (ir.mod == 3) | |
7071 | { | |
7072 | switch (ir.rm) | |
7073 | { | |
a38bba38 | 7074 | case 0: /* monitor */ |
7ad10968 | 7075 | break; |
a38bba38 | 7076 | case 1: /* mwait */ |
25ea693b | 7077 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7078 | break; |
7079 | default: | |
7080 | ir.addr -= 3; | |
7081 | opcode = opcode << 8 | ir.modrm; | |
7082 | goto no_support; | |
7083 | break; | |
7084 | } | |
7085 | } | |
7086 | else | |
7087 | { | |
7088 | /* sidt */ | |
d7877f7e | 7089 | if (ir.override >= 0) |
7ad10968 | 7090 | { |
25ea693b | 7091 | if (record_full_memory_query) |
bb08c432 | 7092 | { |
651ce16a | 7093 | if (yquery (_("\ |
bb08c432 HZ |
7094 | Process record ignores the memory change of instruction at address %s\n\ |
7095 | because it can't get the value of the segment register.\n\ | |
7096 | Do you want to stop the program?"), | |
651ce16a | 7097 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
7098 | return -1; |
7099 | } | |
7ad10968 HZ |
7100 | } |
7101 | else | |
7102 | { | |
955db0c0 | 7103 | uint64_t addr64; |
7ad10968 | 7104 | |
955db0c0 | 7105 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7106 | return -1; |
25ea693b | 7107 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7108 | return -1; |
955db0c0 | 7109 | addr64 += 2; |
cf648174 HZ |
7110 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7111 | { | |
25ea693b | 7112 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7113 | return -1; |
7114 | } | |
7115 | else | |
7116 | { | |
25ea693b | 7117 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7118 | return -1; |
7119 | } | |
7ad10968 HZ |
7120 | } |
7121 | } | |
7122 | break; | |
a38bba38 | 7123 | case 2: /* lgdt */ |
3800e645 MS |
7124 | if (ir.mod == 3) |
7125 | { | |
7126 | /* xgetbv */ | |
7127 | if (ir.rm == 0) | |
7128 | { | |
25ea693b MM |
7129 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7130 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
7131 | break; |
7132 | } | |
7133 | /* xsetbv */ | |
7134 | else if (ir.rm == 1) | |
7135 | break; | |
7136 | } | |
da0e1563 | 7137 | /* Fall through. */ |
a38bba38 | 7138 | case 3: /* lidt */ |
7ad10968 HZ |
7139 | if (ir.mod == 3) |
7140 | { | |
7141 | ir.addr -= 3; | |
7142 | opcode = opcode << 8 | ir.modrm; | |
7143 | goto no_support; | |
7144 | } | |
7145 | break; | |
a38bba38 | 7146 | case 4: /* smsw */ |
7ad10968 HZ |
7147 | if (ir.mod == 3) |
7148 | { | |
25ea693b | 7149 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
7150 | return -1; |
7151 | } | |
7152 | else | |
7153 | { | |
7154 | ir.ot = OT_WORD; | |
7155 | if (i386_record_lea_modrm (&ir)) | |
7156 | return -1; | |
7157 | } | |
25ea693b | 7158 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7159 | break; |
a38bba38 | 7160 | case 6: /* lmsw */ |
25ea693b | 7161 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 7162 | break; |
a38bba38 | 7163 | case 7: /* invlpg */ |
cf648174 HZ |
7164 | if (ir.mod == 3) |
7165 | { | |
7166 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7167 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 HZ |
7168 | else |
7169 | { | |
7170 | ir.addr -= 3; | |
7171 | opcode = opcode << 8 | ir.modrm; | |
7172 | goto no_support; | |
7173 | } | |
7174 | } | |
7175 | else | |
25ea693b | 7176 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
7177 | break; |
7178 | default: | |
7179 | ir.addr -= 3; | |
7180 | opcode = opcode << 8 | ir.modrm; | |
7181 | goto no_support; | |
7ad10968 HZ |
7182 | break; |
7183 | } | |
7184 | break; | |
7185 | ||
a38bba38 MS |
7186 | case 0x0f08: /* invd */ |
7187 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
7188 | break; |
7189 | ||
a38bba38 | 7190 | case 0x63: /* arpl */ |
7ad10968 HZ |
7191 | if (i386_record_modrm (&ir)) |
7192 | return -1; | |
cf648174 HZ |
7193 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
7194 | { | |
25ea693b MM |
7195 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
7196 | ? (ir.reg | rex_r) : ir.rm); | |
cf648174 | 7197 | } |
7ad10968 | 7198 | else |
cf648174 HZ |
7199 | { |
7200 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
7201 | if (i386_record_lea_modrm (&ir)) | |
7202 | return -1; | |
7203 | } | |
7204 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7205 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7206 | break; |
7207 | ||
a38bba38 MS |
7208 | case 0x0f02: /* lar */ |
7209 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
7210 | if (i386_record_modrm (&ir)) |
7211 | return -1; | |
25ea693b MM |
7212 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7213 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
7214 | break; |
7215 | ||
7216 | case 0x0f18: | |
cf648174 HZ |
7217 | if (i386_record_modrm (&ir)) |
7218 | return -1; | |
7219 | if (ir.mod == 3 && ir.reg == 3) | |
7220 | { | |
7221 | ir.addr -= 3; | |
7222 | opcode = opcode << 8 | ir.modrm; | |
7223 | goto no_support; | |
7224 | } | |
7ad10968 HZ |
7225 | break; |
7226 | ||
7ad10968 HZ |
7227 | case 0x0f19: |
7228 | case 0x0f1a: | |
7229 | case 0x0f1b: | |
7230 | case 0x0f1c: | |
7231 | case 0x0f1d: | |
7232 | case 0x0f1e: | |
7233 | case 0x0f1f: | |
a38bba38 | 7234 | /* nop (multi byte) */ |
7ad10968 HZ |
7235 | break; |
7236 | ||
a38bba38 MS |
7237 | case 0x0f20: /* mov reg, crN */ |
7238 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
7239 | if (i386_record_modrm (&ir)) |
7240 | return -1; | |
7241 | if ((ir.modrm & 0xc0) != 0xc0) | |
7242 | { | |
cf648174 | 7243 | ir.addr -= 3; |
7ad10968 HZ |
7244 | opcode = opcode << 8 | ir.modrm; |
7245 | goto no_support; | |
7246 | } | |
7247 | switch (ir.reg) | |
7248 | { | |
7249 | case 0: | |
7250 | case 2: | |
7251 | case 3: | |
7252 | case 4: | |
7253 | case 8: | |
7254 | if (opcode & 2) | |
25ea693b | 7255 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7256 | else |
25ea693b | 7257 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7258 | break; |
7259 | default: | |
cf648174 | 7260 | ir.addr -= 3; |
7ad10968 HZ |
7261 | opcode = opcode << 8 | ir.modrm; |
7262 | goto no_support; | |
7263 | break; | |
7264 | } | |
7265 | break; | |
7266 | ||
a38bba38 MS |
7267 | case 0x0f21: /* mov reg, drN */ |
7268 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
7269 | if (i386_record_modrm (&ir)) |
7270 | return -1; | |
7271 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
7272 | || ir.reg == 5 || ir.reg >= 8) | |
7273 | { | |
cf648174 | 7274 | ir.addr -= 3; |
7ad10968 HZ |
7275 | opcode = opcode << 8 | ir.modrm; |
7276 | goto no_support; | |
7277 | } | |
7278 | if (opcode & 2) | |
25ea693b | 7279 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7280 | else |
25ea693b | 7281 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7282 | break; |
7283 | ||
a38bba38 | 7284 | case 0x0f06: /* clts */ |
25ea693b | 7285 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7286 | break; |
7287 | ||
a3c4230a HZ |
7288 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
7289 | ||
7290 | case 0x0f0d: /* 3DNow! prefetch */ | |
7291 | break; | |
7292 | ||
7293 | case 0x0f0e: /* 3DNow! femms */ | |
7294 | case 0x0f77: /* emms */ | |
7295 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
7296 | goto no_support; | |
25ea693b | 7297 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
7298 | break; |
7299 | ||
7300 | case 0x0f0f: /* 3DNow! data */ | |
7301 | if (i386_record_modrm (&ir)) | |
7302 | return -1; | |
4ffa4fc7 PA |
7303 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7304 | return -1; | |
a3c4230a HZ |
7305 | ir.addr++; |
7306 | switch (opcode8) | |
7307 | { | |
7308 | case 0x0c: /* 3DNow! pi2fw */ | |
7309 | case 0x0d: /* 3DNow! pi2fd */ | |
7310 | case 0x1c: /* 3DNow! pf2iw */ | |
7311 | case 0x1d: /* 3DNow! pf2id */ | |
7312 | case 0x8a: /* 3DNow! pfnacc */ | |
7313 | case 0x8e: /* 3DNow! pfpnacc */ | |
7314 | case 0x90: /* 3DNow! pfcmpge */ | |
7315 | case 0x94: /* 3DNow! pfmin */ | |
7316 | case 0x96: /* 3DNow! pfrcp */ | |
7317 | case 0x97: /* 3DNow! pfrsqrt */ | |
7318 | case 0x9a: /* 3DNow! pfsub */ | |
7319 | case 0x9e: /* 3DNow! pfadd */ | |
7320 | case 0xa0: /* 3DNow! pfcmpgt */ | |
7321 | case 0xa4: /* 3DNow! pfmax */ | |
7322 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
7323 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
7324 | case 0xaa: /* 3DNow! pfsubr */ | |
7325 | case 0xae: /* 3DNow! pfacc */ | |
7326 | case 0xb0: /* 3DNow! pfcmpeq */ | |
7327 | case 0xb4: /* 3DNow! pfmul */ | |
7328 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
7329 | case 0xb7: /* 3DNow! pmulhrw */ | |
7330 | case 0xbb: /* 3DNow! pswapd */ | |
7331 | case 0xbf: /* 3DNow! pavgusb */ | |
7332 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7333 | goto no_support_3dnow_data; | |
25ea693b | 7334 | record_full_arch_list_add_reg (ir.regcache, ir.reg); |
a3c4230a HZ |
7335 | break; |
7336 | ||
7337 | default: | |
7338 | no_support_3dnow_data: | |
7339 | opcode = (opcode << 8) | opcode8; | |
7340 | goto no_support; | |
7341 | break; | |
7342 | } | |
7343 | break; | |
7344 | ||
7345 | case 0x0faa: /* rsm */ | |
25ea693b MM |
7346 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7347 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7348 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7349 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7350 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7351 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
7352 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7353 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7354 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
7355 | break; |
7356 | ||
7357 | case 0x0fae: | |
7358 | if (i386_record_modrm (&ir)) | |
7359 | return -1; | |
7360 | switch(ir.reg) | |
7361 | { | |
7362 | case 0: /* fxsave */ | |
7363 | { | |
7364 | uint64_t tmpu64; | |
7365 | ||
25ea693b | 7366 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7367 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7368 | return -1; | |
25ea693b | 7369 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
a3c4230a HZ |
7370 | return -1; |
7371 | } | |
7372 | break; | |
7373 | ||
7374 | case 1: /* fxrstor */ | |
7375 | { | |
7376 | int i; | |
7377 | ||
25ea693b | 7378 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7379 | |
7380 | for (i = I387_MM0_REGNUM (tdep); | |
7381 | i386_mmx_regnum_p (gdbarch, i); i++) | |
25ea693b | 7382 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7383 | |
7384 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 7385 | i386_xmm_regnum_p (gdbarch, i); i++) |
25ea693b | 7386 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7387 | |
7388 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
25ea693b MM |
7389 | record_full_arch_list_add_reg (ir.regcache, |
7390 | I387_MXCSR_REGNUM(tdep)); | |
a3c4230a HZ |
7391 | |
7392 | for (i = I387_ST0_REGNUM (tdep); | |
7393 | i386_fp_regnum_p (gdbarch, i); i++) | |
25ea693b | 7394 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7395 | |
7396 | for (i = I387_FCTRL_REGNUM (tdep); | |
7397 | i386_fpc_regnum_p (gdbarch, i); i++) | |
25ea693b | 7398 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7399 | } |
7400 | break; | |
7401 | ||
7402 | case 2: /* ldmxcsr */ | |
7403 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
7404 | goto no_support; | |
25ea693b | 7405 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
a3c4230a HZ |
7406 | break; |
7407 | ||
7408 | case 3: /* stmxcsr */ | |
7409 | ir.ot = OT_LONG; | |
7410 | if (i386_record_lea_modrm (&ir)) | |
7411 | return -1; | |
7412 | break; | |
7413 | ||
7414 | case 5: /* lfence */ | |
7415 | case 6: /* mfence */ | |
7416 | case 7: /* sfence clflush */ | |
7417 | break; | |
7418 | ||
7419 | default: | |
7420 | opcode = (opcode << 8) | ir.modrm; | |
7421 | goto no_support; | |
7422 | break; | |
7423 | } | |
7424 | break; | |
7425 | ||
7426 | case 0x0fc3: /* movnti */ | |
7427 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
7428 | if (i386_record_modrm (&ir)) | |
7429 | return -1; | |
7430 | if (ir.mod == 3) | |
7431 | goto no_support; | |
7432 | ir.reg |= rex_r; | |
7433 | if (i386_record_lea_modrm (&ir)) | |
7434 | return -1; | |
7435 | break; | |
7436 | ||
7437 | /* Add prefix to opcode. */ | |
7438 | case 0x0f10: | |
7439 | case 0x0f11: | |
7440 | case 0x0f12: | |
7441 | case 0x0f13: | |
7442 | case 0x0f14: | |
7443 | case 0x0f15: | |
7444 | case 0x0f16: | |
7445 | case 0x0f17: | |
7446 | case 0x0f28: | |
7447 | case 0x0f29: | |
7448 | case 0x0f2a: | |
7449 | case 0x0f2b: | |
7450 | case 0x0f2c: | |
7451 | case 0x0f2d: | |
7452 | case 0x0f2e: | |
7453 | case 0x0f2f: | |
7454 | case 0x0f38: | |
7455 | case 0x0f39: | |
7456 | case 0x0f3a: | |
7457 | case 0x0f50: | |
7458 | case 0x0f51: | |
7459 | case 0x0f52: | |
7460 | case 0x0f53: | |
7461 | case 0x0f54: | |
7462 | case 0x0f55: | |
7463 | case 0x0f56: | |
7464 | case 0x0f57: | |
7465 | case 0x0f58: | |
7466 | case 0x0f59: | |
7467 | case 0x0f5a: | |
7468 | case 0x0f5b: | |
7469 | case 0x0f5c: | |
7470 | case 0x0f5d: | |
7471 | case 0x0f5e: | |
7472 | case 0x0f5f: | |
7473 | case 0x0f60: | |
7474 | case 0x0f61: | |
7475 | case 0x0f62: | |
7476 | case 0x0f63: | |
7477 | case 0x0f64: | |
7478 | case 0x0f65: | |
7479 | case 0x0f66: | |
7480 | case 0x0f67: | |
7481 | case 0x0f68: | |
7482 | case 0x0f69: | |
7483 | case 0x0f6a: | |
7484 | case 0x0f6b: | |
7485 | case 0x0f6c: | |
7486 | case 0x0f6d: | |
7487 | case 0x0f6e: | |
7488 | case 0x0f6f: | |
7489 | case 0x0f70: | |
7490 | case 0x0f71: | |
7491 | case 0x0f72: | |
7492 | case 0x0f73: | |
7493 | case 0x0f74: | |
7494 | case 0x0f75: | |
7495 | case 0x0f76: | |
7496 | case 0x0f7c: | |
7497 | case 0x0f7d: | |
7498 | case 0x0f7e: | |
7499 | case 0x0f7f: | |
7500 | case 0x0fb8: | |
7501 | case 0x0fc2: | |
7502 | case 0x0fc4: | |
7503 | case 0x0fc5: | |
7504 | case 0x0fc6: | |
7505 | case 0x0fd0: | |
7506 | case 0x0fd1: | |
7507 | case 0x0fd2: | |
7508 | case 0x0fd3: | |
7509 | case 0x0fd4: | |
7510 | case 0x0fd5: | |
7511 | case 0x0fd6: | |
7512 | case 0x0fd7: | |
7513 | case 0x0fd8: | |
7514 | case 0x0fd9: | |
7515 | case 0x0fda: | |
7516 | case 0x0fdb: | |
7517 | case 0x0fdc: | |
7518 | case 0x0fdd: | |
7519 | case 0x0fde: | |
7520 | case 0x0fdf: | |
7521 | case 0x0fe0: | |
7522 | case 0x0fe1: | |
7523 | case 0x0fe2: | |
7524 | case 0x0fe3: | |
7525 | case 0x0fe4: | |
7526 | case 0x0fe5: | |
7527 | case 0x0fe6: | |
7528 | case 0x0fe7: | |
7529 | case 0x0fe8: | |
7530 | case 0x0fe9: | |
7531 | case 0x0fea: | |
7532 | case 0x0feb: | |
7533 | case 0x0fec: | |
7534 | case 0x0fed: | |
7535 | case 0x0fee: | |
7536 | case 0x0fef: | |
7537 | case 0x0ff0: | |
7538 | case 0x0ff1: | |
7539 | case 0x0ff2: | |
7540 | case 0x0ff3: | |
7541 | case 0x0ff4: | |
7542 | case 0x0ff5: | |
7543 | case 0x0ff6: | |
7544 | case 0x0ff7: | |
7545 | case 0x0ff8: | |
7546 | case 0x0ff9: | |
7547 | case 0x0ffa: | |
7548 | case 0x0ffb: | |
7549 | case 0x0ffc: | |
7550 | case 0x0ffd: | |
7551 | case 0x0ffe: | |
f9fda3f5 L |
7552 | /* Mask out PREFIX_ADDR. */ |
7553 | switch ((prefixes & ~PREFIX_ADDR)) | |
a3c4230a HZ |
7554 | { |
7555 | case PREFIX_REPNZ: | |
7556 | opcode |= 0xf20000; | |
7557 | break; | |
7558 | case PREFIX_DATA: | |
7559 | opcode |= 0x660000; | |
7560 | break; | |
7561 | case PREFIX_REPZ: | |
7562 | opcode |= 0xf30000; | |
7563 | break; | |
7564 | } | |
7565 | reswitch_prefix_add: | |
7566 | switch (opcode) | |
7567 | { | |
7568 | case 0x0f38: | |
7569 | case 0x660f38: | |
7570 | case 0xf20f38: | |
7571 | case 0x0f3a: | |
7572 | case 0x660f3a: | |
4ffa4fc7 PA |
7573 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7574 | return -1; | |
a3c4230a HZ |
7575 | ir.addr++; |
7576 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7577 | goto reswitch_prefix_add; | |
7578 | break; | |
7579 | ||
7580 | case 0x0f10: /* movups */ | |
7581 | case 0x660f10: /* movupd */ | |
7582 | case 0xf30f10: /* movss */ | |
7583 | case 0xf20f10: /* movsd */ | |
7584 | case 0x0f12: /* movlps */ | |
7585 | case 0x660f12: /* movlpd */ | |
7586 | case 0xf30f12: /* movsldup */ | |
7587 | case 0xf20f12: /* movddup */ | |
7588 | case 0x0f14: /* unpcklps */ | |
7589 | case 0x660f14: /* unpcklpd */ | |
7590 | case 0x0f15: /* unpckhps */ | |
7591 | case 0x660f15: /* unpckhpd */ | |
7592 | case 0x0f16: /* movhps */ | |
7593 | case 0x660f16: /* movhpd */ | |
7594 | case 0xf30f16: /* movshdup */ | |
7595 | case 0x0f28: /* movaps */ | |
7596 | case 0x660f28: /* movapd */ | |
7597 | case 0x0f2a: /* cvtpi2ps */ | |
7598 | case 0x660f2a: /* cvtpi2pd */ | |
7599 | case 0xf30f2a: /* cvtsi2ss */ | |
7600 | case 0xf20f2a: /* cvtsi2sd */ | |
7601 | case 0x0f2c: /* cvttps2pi */ | |
7602 | case 0x660f2c: /* cvttpd2pi */ | |
7603 | case 0x0f2d: /* cvtps2pi */ | |
7604 | case 0x660f2d: /* cvtpd2pi */ | |
7605 | case 0x660f3800: /* pshufb */ | |
7606 | case 0x660f3801: /* phaddw */ | |
7607 | case 0x660f3802: /* phaddd */ | |
7608 | case 0x660f3803: /* phaddsw */ | |
7609 | case 0x660f3804: /* pmaddubsw */ | |
7610 | case 0x660f3805: /* phsubw */ | |
7611 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 7612 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
7613 | case 0x660f3808: /* psignb */ |
7614 | case 0x660f3809: /* psignw */ | |
7615 | case 0x660f380a: /* psignd */ | |
7616 | case 0x660f380b: /* pmulhrsw */ | |
7617 | case 0x660f3810: /* pblendvb */ | |
7618 | case 0x660f3814: /* blendvps */ | |
7619 | case 0x660f3815: /* blendvpd */ | |
7620 | case 0x660f381c: /* pabsb */ | |
7621 | case 0x660f381d: /* pabsw */ | |
7622 | case 0x660f381e: /* pabsd */ | |
7623 | case 0x660f3820: /* pmovsxbw */ | |
7624 | case 0x660f3821: /* pmovsxbd */ | |
7625 | case 0x660f3822: /* pmovsxbq */ | |
7626 | case 0x660f3823: /* pmovsxwd */ | |
7627 | case 0x660f3824: /* pmovsxwq */ | |
7628 | case 0x660f3825: /* pmovsxdq */ | |
7629 | case 0x660f3828: /* pmuldq */ | |
7630 | case 0x660f3829: /* pcmpeqq */ | |
7631 | case 0x660f382a: /* movntdqa */ | |
7632 | case 0x660f3a08: /* roundps */ | |
7633 | case 0x660f3a09: /* roundpd */ | |
7634 | case 0x660f3a0a: /* roundss */ | |
7635 | case 0x660f3a0b: /* roundsd */ | |
7636 | case 0x660f3a0c: /* blendps */ | |
7637 | case 0x660f3a0d: /* blendpd */ | |
7638 | case 0x660f3a0e: /* pblendw */ | |
7639 | case 0x660f3a0f: /* palignr */ | |
7640 | case 0x660f3a20: /* pinsrb */ | |
7641 | case 0x660f3a21: /* insertps */ | |
7642 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7643 | case 0x660f3a40: /* dpps */ | |
7644 | case 0x660f3a41: /* dppd */ | |
7645 | case 0x660f3a42: /* mpsadbw */ | |
7646 | case 0x660f3a60: /* pcmpestrm */ | |
7647 | case 0x660f3a61: /* pcmpestri */ | |
7648 | case 0x660f3a62: /* pcmpistrm */ | |
7649 | case 0x660f3a63: /* pcmpistri */ | |
7650 | case 0x0f51: /* sqrtps */ | |
7651 | case 0x660f51: /* sqrtpd */ | |
7652 | case 0xf20f51: /* sqrtsd */ | |
7653 | case 0xf30f51: /* sqrtss */ | |
7654 | case 0x0f52: /* rsqrtps */ | |
7655 | case 0xf30f52: /* rsqrtss */ | |
7656 | case 0x0f53: /* rcpps */ | |
7657 | case 0xf30f53: /* rcpss */ | |
7658 | case 0x0f54: /* andps */ | |
7659 | case 0x660f54: /* andpd */ | |
7660 | case 0x0f55: /* andnps */ | |
7661 | case 0x660f55: /* andnpd */ | |
7662 | case 0x0f56: /* orps */ | |
7663 | case 0x660f56: /* orpd */ | |
7664 | case 0x0f57: /* xorps */ | |
7665 | case 0x660f57: /* xorpd */ | |
7666 | case 0x0f58: /* addps */ | |
7667 | case 0x660f58: /* addpd */ | |
7668 | case 0xf20f58: /* addsd */ | |
7669 | case 0xf30f58: /* addss */ | |
7670 | case 0x0f59: /* mulps */ | |
7671 | case 0x660f59: /* mulpd */ | |
7672 | case 0xf20f59: /* mulsd */ | |
7673 | case 0xf30f59: /* mulss */ | |
7674 | case 0x0f5a: /* cvtps2pd */ | |
7675 | case 0x660f5a: /* cvtpd2ps */ | |
7676 | case 0xf20f5a: /* cvtsd2ss */ | |
7677 | case 0xf30f5a: /* cvtss2sd */ | |
7678 | case 0x0f5b: /* cvtdq2ps */ | |
7679 | case 0x660f5b: /* cvtps2dq */ | |
7680 | case 0xf30f5b: /* cvttps2dq */ | |
7681 | case 0x0f5c: /* subps */ | |
7682 | case 0x660f5c: /* subpd */ | |
7683 | case 0xf20f5c: /* subsd */ | |
7684 | case 0xf30f5c: /* subss */ | |
7685 | case 0x0f5d: /* minps */ | |
7686 | case 0x660f5d: /* minpd */ | |
7687 | case 0xf20f5d: /* minsd */ | |
7688 | case 0xf30f5d: /* minss */ | |
7689 | case 0x0f5e: /* divps */ | |
7690 | case 0x660f5e: /* divpd */ | |
7691 | case 0xf20f5e: /* divsd */ | |
7692 | case 0xf30f5e: /* divss */ | |
7693 | case 0x0f5f: /* maxps */ | |
7694 | case 0x660f5f: /* maxpd */ | |
7695 | case 0xf20f5f: /* maxsd */ | |
7696 | case 0xf30f5f: /* maxss */ | |
7697 | case 0x660f60: /* punpcklbw */ | |
7698 | case 0x660f61: /* punpcklwd */ | |
7699 | case 0x660f62: /* punpckldq */ | |
7700 | case 0x660f63: /* packsswb */ | |
7701 | case 0x660f64: /* pcmpgtb */ | |
7702 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 7703 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
7704 | case 0x660f67: /* packuswb */ |
7705 | case 0x660f68: /* punpckhbw */ | |
7706 | case 0x660f69: /* punpckhwd */ | |
7707 | case 0x660f6a: /* punpckhdq */ | |
7708 | case 0x660f6b: /* packssdw */ | |
7709 | case 0x660f6c: /* punpcklqdq */ | |
7710 | case 0x660f6d: /* punpckhqdq */ | |
7711 | case 0x660f6e: /* movd */ | |
7712 | case 0x660f6f: /* movdqa */ | |
7713 | case 0xf30f6f: /* movdqu */ | |
7714 | case 0x660f70: /* pshufd */ | |
7715 | case 0xf20f70: /* pshuflw */ | |
7716 | case 0xf30f70: /* pshufhw */ | |
7717 | case 0x660f74: /* pcmpeqb */ | |
7718 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 7719 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
7720 | case 0x660f7c: /* haddpd */ |
7721 | case 0xf20f7c: /* haddps */ | |
7722 | case 0x660f7d: /* hsubpd */ | |
7723 | case 0xf20f7d: /* hsubps */ | |
7724 | case 0xf30f7e: /* movq */ | |
7725 | case 0x0fc2: /* cmpps */ | |
7726 | case 0x660fc2: /* cmppd */ | |
7727 | case 0xf20fc2: /* cmpsd */ | |
7728 | case 0xf30fc2: /* cmpss */ | |
7729 | case 0x660fc4: /* pinsrw */ | |
7730 | case 0x0fc6: /* shufps */ | |
7731 | case 0x660fc6: /* shufpd */ | |
7732 | case 0x660fd0: /* addsubpd */ | |
7733 | case 0xf20fd0: /* addsubps */ | |
7734 | case 0x660fd1: /* psrlw */ | |
7735 | case 0x660fd2: /* psrld */ | |
7736 | case 0x660fd3: /* psrlq */ | |
7737 | case 0x660fd4: /* paddq */ | |
7738 | case 0x660fd5: /* pmullw */ | |
7739 | case 0xf30fd6: /* movq2dq */ | |
7740 | case 0x660fd8: /* psubusb */ | |
7741 | case 0x660fd9: /* psubusw */ | |
7742 | case 0x660fda: /* pminub */ | |
7743 | case 0x660fdb: /* pand */ | |
7744 | case 0x660fdc: /* paddusb */ | |
7745 | case 0x660fdd: /* paddusw */ | |
7746 | case 0x660fde: /* pmaxub */ | |
7747 | case 0x660fdf: /* pandn */ | |
7748 | case 0x660fe0: /* pavgb */ | |
7749 | case 0x660fe1: /* psraw */ | |
7750 | case 0x660fe2: /* psrad */ | |
7751 | case 0x660fe3: /* pavgw */ | |
7752 | case 0x660fe4: /* pmulhuw */ | |
7753 | case 0x660fe5: /* pmulhw */ | |
7754 | case 0x660fe6: /* cvttpd2dq */ | |
7755 | case 0xf20fe6: /* cvtpd2dq */ | |
7756 | case 0xf30fe6: /* cvtdq2pd */ | |
7757 | case 0x660fe8: /* psubsb */ | |
7758 | case 0x660fe9: /* psubsw */ | |
7759 | case 0x660fea: /* pminsw */ | |
7760 | case 0x660feb: /* por */ | |
7761 | case 0x660fec: /* paddsb */ | |
7762 | case 0x660fed: /* paddsw */ | |
7763 | case 0x660fee: /* pmaxsw */ | |
7764 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7765 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7766 | case 0x660ff1: /* psllw */ |
7767 | case 0x660ff2: /* pslld */ | |
7768 | case 0x660ff3: /* psllq */ | |
7769 | case 0x660ff4: /* pmuludq */ | |
7770 | case 0x660ff5: /* pmaddwd */ | |
7771 | case 0x660ff6: /* psadbw */ | |
7772 | case 0x660ff8: /* psubb */ | |
7773 | case 0x660ff9: /* psubw */ | |
56d2815c | 7774 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7775 | case 0x660ffb: /* psubq */ |
7776 | case 0x660ffc: /* paddb */ | |
7777 | case 0x660ffd: /* paddw */ | |
56d2815c | 7778 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7779 | if (i386_record_modrm (&ir)) |
7780 | return -1; | |
7781 | ir.reg |= rex_r; | |
c131fcee | 7782 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a | 7783 | goto no_support; |
25ea693b MM |
7784 | record_full_arch_list_add_reg (ir.regcache, |
7785 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
a3c4230a | 7786 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
25ea693b | 7787 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7788 | break; |
7789 | ||
7790 | case 0x0f11: /* movups */ | |
7791 | case 0x660f11: /* movupd */ | |
7792 | case 0xf30f11: /* movss */ | |
7793 | case 0xf20f11: /* movsd */ | |
7794 | case 0x0f13: /* movlps */ | |
7795 | case 0x660f13: /* movlpd */ | |
7796 | case 0x0f17: /* movhps */ | |
7797 | case 0x660f17: /* movhpd */ | |
7798 | case 0x0f29: /* movaps */ | |
7799 | case 0x660f29: /* movapd */ | |
7800 | case 0x660f3a14: /* pextrb */ | |
7801 | case 0x660f3a15: /* pextrw */ | |
7802 | case 0x660f3a16: /* pextrd pextrq */ | |
7803 | case 0x660f3a17: /* extractps */ | |
7804 | case 0x660f7f: /* movdqa */ | |
7805 | case 0xf30f7f: /* movdqu */ | |
7806 | if (i386_record_modrm (&ir)) | |
7807 | return -1; | |
7808 | if (ir.mod == 3) | |
7809 | { | |
7810 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7811 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7812 | goto no_support; | |
7813 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7814 | if (!i386_xmm_regnum_p (gdbarch, |
7815 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7816 | goto no_support; |
25ea693b MM |
7817 | record_full_arch_list_add_reg (ir.regcache, |
7818 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7819 | } |
7820 | else | |
7821 | { | |
7822 | switch (opcode) | |
7823 | { | |
7824 | case 0x660f3a14: | |
7825 | ir.ot = OT_BYTE; | |
7826 | break; | |
7827 | case 0x660f3a15: | |
7828 | ir.ot = OT_WORD; | |
7829 | break; | |
7830 | case 0x660f3a16: | |
7831 | ir.ot = OT_LONG; | |
7832 | break; | |
7833 | case 0x660f3a17: | |
7834 | ir.ot = OT_QUAD; | |
7835 | break; | |
7836 | default: | |
7837 | ir.ot = OT_DQUAD; | |
7838 | break; | |
7839 | } | |
7840 | if (i386_record_lea_modrm (&ir)) | |
7841 | return -1; | |
7842 | } | |
7843 | break; | |
7844 | ||
7845 | case 0x0f2b: /* movntps */ | |
7846 | case 0x660f2b: /* movntpd */ | |
7847 | case 0x0fe7: /* movntq */ | |
7848 | case 0x660fe7: /* movntdq */ | |
7849 | if (ir.mod == 3) | |
7850 | goto no_support; | |
7851 | if (opcode == 0x0fe7) | |
7852 | ir.ot = OT_QUAD; | |
7853 | else | |
7854 | ir.ot = OT_DQUAD; | |
7855 | if (i386_record_lea_modrm (&ir)) | |
7856 | return -1; | |
7857 | break; | |
7858 | ||
7859 | case 0xf30f2c: /* cvttss2si */ | |
7860 | case 0xf20f2c: /* cvttsd2si */ | |
7861 | case 0xf30f2d: /* cvtss2si */ | |
7862 | case 0xf20f2d: /* cvtsd2si */ | |
7863 | case 0xf20f38f0: /* crc32 */ | |
7864 | case 0xf20f38f1: /* crc32 */ | |
7865 | case 0x0f50: /* movmskps */ | |
7866 | case 0x660f50: /* movmskpd */ | |
7867 | case 0x0fc5: /* pextrw */ | |
7868 | case 0x660fc5: /* pextrw */ | |
7869 | case 0x0fd7: /* pmovmskb */ | |
7870 | case 0x660fd7: /* pmovmskb */ | |
25ea693b | 7871 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
a3c4230a HZ |
7872 | break; |
7873 | ||
7874 | case 0x0f3800: /* pshufb */ | |
7875 | case 0x0f3801: /* phaddw */ | |
7876 | case 0x0f3802: /* phaddd */ | |
7877 | case 0x0f3803: /* phaddsw */ | |
7878 | case 0x0f3804: /* pmaddubsw */ | |
7879 | case 0x0f3805: /* phsubw */ | |
7880 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7881 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7882 | case 0x0f3808: /* psignb */ |
7883 | case 0x0f3809: /* psignw */ | |
7884 | case 0x0f380a: /* psignd */ | |
7885 | case 0x0f380b: /* pmulhrsw */ | |
7886 | case 0x0f381c: /* pabsb */ | |
7887 | case 0x0f381d: /* pabsw */ | |
7888 | case 0x0f381e: /* pabsd */ | |
7889 | case 0x0f382b: /* packusdw */ | |
7890 | case 0x0f3830: /* pmovzxbw */ | |
7891 | case 0x0f3831: /* pmovzxbd */ | |
7892 | case 0x0f3832: /* pmovzxbq */ | |
7893 | case 0x0f3833: /* pmovzxwd */ | |
7894 | case 0x0f3834: /* pmovzxwq */ | |
7895 | case 0x0f3835: /* pmovzxdq */ | |
7896 | case 0x0f3837: /* pcmpgtq */ | |
7897 | case 0x0f3838: /* pminsb */ | |
7898 | case 0x0f3839: /* pminsd */ | |
7899 | case 0x0f383a: /* pminuw */ | |
7900 | case 0x0f383b: /* pminud */ | |
7901 | case 0x0f383c: /* pmaxsb */ | |
7902 | case 0x0f383d: /* pmaxsd */ | |
7903 | case 0x0f383e: /* pmaxuw */ | |
7904 | case 0x0f383f: /* pmaxud */ | |
7905 | case 0x0f3840: /* pmulld */ | |
7906 | case 0x0f3841: /* phminposuw */ | |
7907 | case 0x0f3a0f: /* palignr */ | |
7908 | case 0x0f60: /* punpcklbw */ | |
7909 | case 0x0f61: /* punpcklwd */ | |
7910 | case 0x0f62: /* punpckldq */ | |
7911 | case 0x0f63: /* packsswb */ | |
7912 | case 0x0f64: /* pcmpgtb */ | |
7913 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7914 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7915 | case 0x0f67: /* packuswb */ |
7916 | case 0x0f68: /* punpckhbw */ | |
7917 | case 0x0f69: /* punpckhwd */ | |
7918 | case 0x0f6a: /* punpckhdq */ | |
7919 | case 0x0f6b: /* packssdw */ | |
7920 | case 0x0f6e: /* movd */ | |
7921 | case 0x0f6f: /* movq */ | |
7922 | case 0x0f70: /* pshufw */ | |
7923 | case 0x0f74: /* pcmpeqb */ | |
7924 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7925 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7926 | case 0x0fc4: /* pinsrw */ |
7927 | case 0x0fd1: /* psrlw */ | |
7928 | case 0x0fd2: /* psrld */ | |
7929 | case 0x0fd3: /* psrlq */ | |
7930 | case 0x0fd4: /* paddq */ | |
7931 | case 0x0fd5: /* pmullw */ | |
7932 | case 0xf20fd6: /* movdq2q */ | |
7933 | case 0x0fd8: /* psubusb */ | |
7934 | case 0x0fd9: /* psubusw */ | |
7935 | case 0x0fda: /* pminub */ | |
7936 | case 0x0fdb: /* pand */ | |
7937 | case 0x0fdc: /* paddusb */ | |
7938 | case 0x0fdd: /* paddusw */ | |
7939 | case 0x0fde: /* pmaxub */ | |
7940 | case 0x0fdf: /* pandn */ | |
7941 | case 0x0fe0: /* pavgb */ | |
7942 | case 0x0fe1: /* psraw */ | |
7943 | case 0x0fe2: /* psrad */ | |
7944 | case 0x0fe3: /* pavgw */ | |
7945 | case 0x0fe4: /* pmulhuw */ | |
7946 | case 0x0fe5: /* pmulhw */ | |
7947 | case 0x0fe8: /* psubsb */ | |
7948 | case 0x0fe9: /* psubsw */ | |
7949 | case 0x0fea: /* pminsw */ | |
7950 | case 0x0feb: /* por */ | |
7951 | case 0x0fec: /* paddsb */ | |
7952 | case 0x0fed: /* paddsw */ | |
7953 | case 0x0fee: /* pmaxsw */ | |
7954 | case 0x0fef: /* pxor */ | |
7955 | case 0x0ff1: /* psllw */ | |
7956 | case 0x0ff2: /* pslld */ | |
7957 | case 0x0ff3: /* psllq */ | |
7958 | case 0x0ff4: /* pmuludq */ | |
7959 | case 0x0ff5: /* pmaddwd */ | |
7960 | case 0x0ff6: /* psadbw */ | |
7961 | case 0x0ff8: /* psubb */ | |
7962 | case 0x0ff9: /* psubw */ | |
56d2815c | 7963 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7964 | case 0x0ffb: /* psubq */ |
7965 | case 0x0ffc: /* paddb */ | |
7966 | case 0x0ffd: /* paddw */ | |
56d2815c | 7967 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7968 | if (i386_record_modrm (&ir)) |
7969 | return -1; | |
7970 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7971 | goto no_support; | |
25ea693b MM |
7972 | record_full_arch_list_add_reg (ir.regcache, |
7973 | I387_MM0_REGNUM (tdep) + ir.reg); | |
a3c4230a HZ |
7974 | break; |
7975 | ||
7976 | case 0x0f71: /* psllw */ | |
7977 | case 0x0f72: /* pslld */ | |
7978 | case 0x0f73: /* psllq */ | |
7979 | if (i386_record_modrm (&ir)) | |
7980 | return -1; | |
7981 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7982 | goto no_support; | |
25ea693b MM |
7983 | record_full_arch_list_add_reg (ir.regcache, |
7984 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7985 | break; |
7986 | ||
7987 | case 0x660f71: /* psllw */ | |
7988 | case 0x660f72: /* pslld */ | |
7989 | case 0x660f73: /* psllq */ | |
7990 | if (i386_record_modrm (&ir)) | |
7991 | return -1; | |
7992 | ir.rm |= ir.rex_b; | |
c131fcee | 7993 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a | 7994 | goto no_support; |
25ea693b MM |
7995 | record_full_arch_list_add_reg (ir.regcache, |
7996 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7997 | break; |
7998 | ||
7999 | case 0x0f7e: /* movd */ | |
8000 | case 0x660f7e: /* movd */ | |
8001 | if (i386_record_modrm (&ir)) | |
8002 | return -1; | |
8003 | if (ir.mod == 3) | |
25ea693b | 8004 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
a3c4230a HZ |
8005 | else |
8006 | { | |
8007 | if (ir.dflag == 2) | |
8008 | ir.ot = OT_QUAD; | |
8009 | else | |
8010 | ir.ot = OT_LONG; | |
8011 | if (i386_record_lea_modrm (&ir)) | |
8012 | return -1; | |
8013 | } | |
8014 | break; | |
8015 | ||
8016 | case 0x0f7f: /* movq */ | |
8017 | if (i386_record_modrm (&ir)) | |
8018 | return -1; | |
8019 | if (ir.mod == 3) | |
8020 | { | |
8021 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
8022 | goto no_support; | |
25ea693b MM |
8023 | record_full_arch_list_add_reg (ir.regcache, |
8024 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
8025 | } |
8026 | else | |
8027 | { | |
8028 | ir.ot = OT_QUAD; | |
8029 | if (i386_record_lea_modrm (&ir)) | |
8030 | return -1; | |
8031 | } | |
8032 | break; | |
8033 | ||
8034 | case 0xf30fb8: /* popcnt */ | |
8035 | if (i386_record_modrm (&ir)) | |
8036 | return -1; | |
25ea693b MM |
8037 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
8038 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
a3c4230a HZ |
8039 | break; |
8040 | ||
8041 | case 0x660fd6: /* movq */ | |
8042 | if (i386_record_modrm (&ir)) | |
8043 | return -1; | |
8044 | if (ir.mod == 3) | |
8045 | { | |
8046 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
8047 | if (!i386_xmm_regnum_p (gdbarch, |
8048 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 8049 | goto no_support; |
25ea693b MM |
8050 | record_full_arch_list_add_reg (ir.regcache, |
8051 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
8052 | } |
8053 | else | |
8054 | { | |
8055 | ir.ot = OT_QUAD; | |
8056 | if (i386_record_lea_modrm (&ir)) | |
8057 | return -1; | |
8058 | } | |
8059 | break; | |
8060 | ||
8061 | case 0x660f3817: /* ptest */ | |
8062 | case 0x0f2e: /* ucomiss */ | |
8063 | case 0x660f2e: /* ucomisd */ | |
8064 | case 0x0f2f: /* comiss */ | |
8065 | case 0x660f2f: /* comisd */ | |
25ea693b | 8066 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
8067 | break; |
8068 | ||
8069 | case 0x0ff7: /* maskmovq */ | |
8070 | regcache_raw_read_unsigned (ir.regcache, | |
8071 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8072 | &addr); | |
25ea693b | 8073 | if (record_full_arch_list_add_mem (addr, 64)) |
a3c4230a HZ |
8074 | return -1; |
8075 | break; | |
8076 | ||
8077 | case 0x660ff7: /* maskmovdqu */ | |
8078 | regcache_raw_read_unsigned (ir.regcache, | |
8079 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8080 | &addr); | |
25ea693b | 8081 | if (record_full_arch_list_add_mem (addr, 128)) |
a3c4230a HZ |
8082 | return -1; |
8083 | break; | |
8084 | ||
8085 | default: | |
8086 | goto no_support; | |
8087 | break; | |
8088 | } | |
8089 | break; | |
7ad10968 HZ |
8090 | |
8091 | default: | |
7ad10968 HZ |
8092 | goto no_support; |
8093 | break; | |
8094 | } | |
8095 | ||
cf648174 | 8096 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
8097 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
8098 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
8099 | return -1; |
8100 | ||
8101 | return 0; | |
8102 | ||
01fe1b41 | 8103 | no_support: |
a3c4230a HZ |
8104 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
8105 | "at address %s.\n"), | |
8106 | (unsigned int) (opcode), | |
8107 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
8108 | return -1; |
8109 | } | |
8110 | ||
cf648174 HZ |
8111 | static const int i386_record_regmap[] = |
8112 | { | |
8113 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
8114 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
8115 | 0, 0, 0, 0, 0, 0, 0, 0, | |
8116 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
8117 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
8118 | }; | |
8119 | ||
7a697b8d | 8120 | /* Check that the given address appears suitable for a fast |
405f8e94 | 8121 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
8122 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
8123 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
8124 | middle of the tracepoint jump. On x86, it may be possible to use |
8125 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
8126 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
8127 | of instruction to replace, and 0 if not, plus an explanatory |
8128 | string. */ | |
8129 | ||
8130 | static int | |
6b940e6a | 8131 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr, |
281d762b | 8132 | std::string *msg) |
7a697b8d SS |
8133 | { |
8134 | int len, jumplen; | |
7a697b8d | 8135 | |
405f8e94 SS |
8136 | /* Ask the target for the minimum instruction length supported. */ |
8137 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
8138 | ||
8139 | if (jumplen < 0) | |
8140 | { | |
8141 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
8142 | operation, assume that fast tracepoints will always be implemented | |
8143 | using 4-byte relative jumps on both x86 and x86-64. */ | |
8144 | jumplen = 5; | |
8145 | } | |
8146 | else if (jumplen == 0) | |
8147 | { | |
8148 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
8149 | returns zero, then the IPA has not loaded yet. In this case, | |
8150 | we optimistically assume that truncated 2-byte relative jumps | |
8151 | will be available on x86, and compensate later if this assumption | |
8152 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
8153 | jumps will always be used. */ | |
8154 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
8155 | } | |
7a697b8d | 8156 | |
7a697b8d | 8157 | /* Check for fit. */ |
be85ce7d | 8158 | len = gdb_insn_length (gdbarch, addr); |
405f8e94 | 8159 | |
7a697b8d SS |
8160 | if (len < jumplen) |
8161 | { | |
8162 | /* Return a bit of target-specific detail to add to the caller's | |
8163 | generic failure message. */ | |
8164 | if (msg) | |
281d762b TT |
8165 | *msg = string_printf (_("; instruction is only %d bytes long, " |
8166 | "need at least %d bytes for the jump"), | |
8167 | len, jumplen); | |
7a697b8d SS |
8168 | return 0; |
8169 | } | |
405f8e94 SS |
8170 | else |
8171 | { | |
8172 | if (msg) | |
281d762b | 8173 | msg->clear (); |
405f8e94 SS |
8174 | return 1; |
8175 | } | |
7a697b8d SS |
8176 | } |
8177 | ||
00d5215e UW |
8178 | /* Return a floating-point format for a floating-point variable of |
8179 | length LEN in bits. If non-NULL, NAME is the name of its type. | |
8180 | If no suitable type is found, return NULL. */ | |
8181 | ||
cb8c24b6 | 8182 | static const struct floatformat ** |
00d5215e UW |
8183 | i386_floatformat_for_type (struct gdbarch *gdbarch, |
8184 | const char *name, int len) | |
8185 | { | |
8186 | if (len == 128 && name) | |
8187 | if (strcmp (name, "__float128") == 0 | |
8188 | || strcmp (name, "_Float128") == 0 | |
34d11c68 AB |
8189 | || strcmp (name, "complex _Float128") == 0 |
8190 | || strcmp (name, "complex(kind=16)") == 0 | |
8191 | || strcmp (name, "real(kind=16)") == 0) | |
00d5215e UW |
8192 | return floatformats_ia64_quad; |
8193 | ||
8194 | return default_floatformat_for_type (gdbarch, name, len); | |
8195 | } | |
8196 | ||
90884b2b L |
8197 | static int |
8198 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
8199 | struct tdesc_arch_data *tdesc_data) | |
8200 | { | |
8201 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 8202 | const struct tdesc_feature *feature_core; |
01f9f808 MS |
8203 | |
8204 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, | |
1163a4b7 | 8205 | *feature_avx512, *feature_pkeys, *feature_segments; |
90884b2b L |
8206 | int i, num_regs, valid_p; |
8207 | ||
8208 | if (! tdesc_has_registers (tdesc)) | |
8209 | return 0; | |
8210 | ||
8211 | /* Get core registers. */ | |
8212 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
8213 | if (feature_core == NULL) |
8214 | return 0; | |
90884b2b L |
8215 | |
8216 | /* Get SSE registers. */ | |
c131fcee | 8217 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 8218 | |
c131fcee L |
8219 | /* Try AVX registers. */ |
8220 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
8221 | ||
1dbcd68c WT |
8222 | /* Try MPX registers. */ |
8223 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
8224 | ||
01f9f808 MS |
8225 | /* Try AVX512 registers. */ |
8226 | feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); | |
8227 | ||
1163a4b7 JB |
8228 | /* Try segment base registers. */ |
8229 | feature_segments = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments"); | |
8230 | ||
51547df6 MS |
8231 | /* Try PKEYS */ |
8232 | feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys"); | |
8233 | ||
90884b2b L |
8234 | valid_p = 1; |
8235 | ||
c131fcee | 8236 | /* The XCR0 bits. */ |
01f9f808 MS |
8237 | if (feature_avx512) |
8238 | { | |
8239 | /* AVX512 register description requires AVX register description. */ | |
8240 | if (!feature_avx) | |
8241 | return 0; | |
8242 | ||
a1fa17ee | 8243 | tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK; |
01f9f808 MS |
8244 | |
8245 | /* It may have been set by OSABI initialization function. */ | |
8246 | if (tdep->k0_regnum < 0) | |
8247 | { | |
8248 | tdep->k_register_names = i386_k_names; | |
8249 | tdep->k0_regnum = I386_K0_REGNUM; | |
8250 | } | |
8251 | ||
8252 | for (i = 0; i < I387_NUM_K_REGS; i++) | |
8253 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8254 | tdep->k0_regnum + i, | |
8255 | i386_k_names[i]); | |
8256 | ||
8257 | if (tdep->num_zmm_regs == 0) | |
8258 | { | |
8259 | tdep->zmmh_register_names = i386_zmmh_names; | |
8260 | tdep->num_zmm_regs = 8; | |
8261 | tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; | |
8262 | } | |
8263 | ||
8264 | for (i = 0; i < tdep->num_zmm_regs; i++) | |
8265 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8266 | tdep->zmm0h_regnum + i, | |
8267 | tdep->zmmh_register_names[i]); | |
8268 | ||
8269 | for (i = 0; i < tdep->num_xmm_avx512_regs; i++) | |
8270 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8271 | tdep->xmm16_regnum + i, | |
8272 | tdep->xmm_avx512_register_names[i]); | |
8273 | ||
8274 | for (i = 0; i < tdep->num_ymm_avx512_regs; i++) | |
8275 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8276 | tdep->ymm16h_regnum + i, | |
8277 | tdep->ymm16h_register_names[i]); | |
8278 | } | |
c131fcee L |
8279 | if (feature_avx) |
8280 | { | |
3a13a53b L |
8281 | /* AVX register description requires SSE register description. */ |
8282 | if (!feature_sse) | |
8283 | return 0; | |
8284 | ||
01f9f808 | 8285 | if (!feature_avx512) |
df7e5265 | 8286 | tdep->xcr0 = X86_XSTATE_AVX_MASK; |
c131fcee L |
8287 | |
8288 | /* It may have been set by OSABI initialization function. */ | |
8289 | if (tdep->num_ymm_regs == 0) | |
8290 | { | |
8291 | tdep->ymmh_register_names = i386_ymmh_names; | |
8292 | tdep->num_ymm_regs = 8; | |
8293 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
8294 | } | |
8295 | ||
8296 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
8297 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
8298 | tdep->ymm0h_regnum + i, | |
8299 | tdep->ymmh_register_names[i]); | |
8300 | } | |
3a13a53b | 8301 | else if (feature_sse) |
df7e5265 | 8302 | tdep->xcr0 = X86_XSTATE_SSE_MASK; |
3a13a53b L |
8303 | else |
8304 | { | |
df7e5265 | 8305 | tdep->xcr0 = X86_XSTATE_X87_MASK; |
3a13a53b L |
8306 | tdep->num_xmm_regs = 0; |
8307 | } | |
c131fcee | 8308 | |
90884b2b L |
8309 | num_regs = tdep->num_core_regs; |
8310 | for (i = 0; i < num_regs; i++) | |
8311 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
8312 | tdep->register_names[i]); | |
8313 | ||
3a13a53b L |
8314 | if (feature_sse) |
8315 | { | |
8316 | /* Need to include %mxcsr, so add one. */ | |
8317 | num_regs += tdep->num_xmm_regs + 1; | |
8318 | for (; i < num_regs; i++) | |
8319 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
8320 | tdep->register_names[i]); | |
8321 | } | |
90884b2b | 8322 | |
1dbcd68c WT |
8323 | if (feature_mpx) |
8324 | { | |
df7e5265 | 8325 | tdep->xcr0 |= X86_XSTATE_MPX_MASK; |
1dbcd68c WT |
8326 | |
8327 | if (tdep->bnd0r_regnum < 0) | |
8328 | { | |
8329 | tdep->mpx_register_names = i386_mpx_names; | |
8330 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
8331 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
8332 | } | |
8333 | ||
8334 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
8335 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
8336 | I387_BND0R_REGNUM (tdep) + i, | |
8337 | tdep->mpx_register_names[i]); | |
8338 | } | |
8339 | ||
1163a4b7 JB |
8340 | if (feature_segments) |
8341 | { | |
8342 | if (tdep->fsbase_regnum < 0) | |
8343 | tdep->fsbase_regnum = I386_FSBASE_REGNUM; | |
8344 | valid_p &= tdesc_numbered_register (feature_segments, tdesc_data, | |
8345 | tdep->fsbase_regnum, "fs_base"); | |
8346 | valid_p &= tdesc_numbered_register (feature_segments, tdesc_data, | |
8347 | tdep->fsbase_regnum + 1, "gs_base"); | |
8348 | } | |
8349 | ||
51547df6 MS |
8350 | if (feature_pkeys) |
8351 | { | |
8352 | tdep->xcr0 |= X86_XSTATE_PKRU; | |
8353 | if (tdep->pkru_regnum < 0) | |
8354 | { | |
8355 | tdep->pkeys_register_names = i386_pkeys_names; | |
8356 | tdep->pkru_regnum = I386_PKRU_REGNUM; | |
8357 | tdep->num_pkeys_regs = 1; | |
8358 | } | |
8359 | ||
8360 | for (i = 0; i < I387_NUM_PKEYS_REGS; i++) | |
8361 | valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data, | |
8362 | I387_PKRU_REGNUM (tdep) + i, | |
8363 | tdep->pkeys_register_names[i]); | |
8364 | } | |
8365 | ||
90884b2b L |
8366 | return valid_p; |
8367 | } | |
8368 | ||
2b4424c3 TT |
8369 | \f |
8370 | ||
8371 | /* Implement the type_align gdbarch function. */ | |
8372 | ||
8373 | static ULONGEST | |
8374 | i386_type_align (struct gdbarch *gdbarch, struct type *type) | |
8375 | { | |
8376 | type = check_typedef (type); | |
8377 | ||
8378 | if (gdbarch_ptr_bit (gdbarch) == 32) | |
8379 | { | |
8380 | if ((TYPE_CODE (type) == TYPE_CODE_INT | |
8381 | || TYPE_CODE (type) == TYPE_CODE_FLT) | |
8382 | && TYPE_LENGTH (type) > 4) | |
8383 | return 4; | |
8384 | ||
8385 | /* Handle x86's funny long double. */ | |
8386 | if (TYPE_CODE (type) == TYPE_CODE_FLT | |
8387 | && gdbarch_long_double_bit (gdbarch) == TYPE_LENGTH (type) * 8) | |
8388 | return 4; | |
8389 | } | |
8390 | ||
5561fc30 | 8391 | return 0; |
2b4424c3 TT |
8392 | } |
8393 | ||
7ad10968 | 8394 | \f |
ad9eb1fd DE |
8395 | /* Note: This is called for both i386 and amd64. */ |
8396 | ||
7ad10968 HZ |
8397 | static struct gdbarch * |
8398 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8399 | { | |
8400 | struct gdbarch_tdep *tdep; | |
8401 | struct gdbarch *gdbarch; | |
90884b2b L |
8402 | struct tdesc_arch_data *tdesc_data; |
8403 | const struct target_desc *tdesc; | |
1ba53b71 | 8404 | int mm0_regnum; |
c131fcee | 8405 | int ymm0_regnum; |
1dbcd68c WT |
8406 | int bnd0_regnum; |
8407 | int num_bnd_cooked; | |
7ad10968 HZ |
8408 | |
8409 | /* If there is already a candidate, use it. */ | |
8410 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
8411 | if (arches != NULL) | |
8412 | return arches->gdbarch; | |
8413 | ||
ad9eb1fd | 8414 | /* Allocate space for the new architecture. Assume i386 for now. */ |
fc270c35 | 8415 | tdep = XCNEW (struct gdbarch_tdep); |
7ad10968 HZ |
8416 | gdbarch = gdbarch_alloc (&info, tdep); |
8417 | ||
8418 | /* General-purpose registers. */ | |
7ad10968 HZ |
8419 | tdep->gregset_reg_offset = NULL; |
8420 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
8421 | tdep->sizeof_gregset = 0; | |
8422 | ||
8423 | /* Floating-point registers. */ | |
7ad10968 | 8424 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
8f0435f7 | 8425 | tdep->fpregset = &i386_fpregset; |
7ad10968 HZ |
8426 | |
8427 | /* The default settings include the FPU registers, the MMX registers | |
8428 | and the SSE registers. This can be overridden for a specific ABI | |
8429 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
8430 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 8431 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
8432 | |
8433 | tdep->st0_regnum = I386_ST0_REGNUM; | |
8434 | ||
7ad10968 HZ |
8435 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
8436 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
8437 | ||
8438 | tdep->jb_pc_offset = -1; | |
8439 | tdep->struct_return = pcc_struct_return; | |
8440 | tdep->sigtramp_start = 0; | |
8441 | tdep->sigtramp_end = 0; | |
8442 | tdep->sigtramp_p = i386_sigtramp_p; | |
8443 | tdep->sigcontext_addr = NULL; | |
8444 | tdep->sc_reg_offset = NULL; | |
8445 | tdep->sc_pc_offset = -1; | |
8446 | tdep->sc_sp_offset = -1; | |
8447 | ||
c131fcee L |
8448 | tdep->xsave_xcr0_offset = -1; |
8449 | ||
cf648174 HZ |
8450 | tdep->record_regmap = i386_record_regmap; |
8451 | ||
2b4424c3 | 8452 | set_gdbarch_type_align (gdbarch, i386_type_align); |
205c306f | 8453 | |
7ad10968 HZ |
8454 | /* The format used for `long double' on almost all i386 targets is |
8455 | the i387 extended floating-point format. In fact, of all targets | |
8456 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
8457 | on having a `long double' that's not `long' at all. */ | |
8458 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
8459 | ||
8460 | /* Although the i387 extended floating-point has only 80 significant | |
8461 | bits, a `long double' actually takes up 96, probably to enforce | |
8462 | alignment. */ | |
8463 | set_gdbarch_long_double_bit (gdbarch, 96); | |
8464 | ||
00d5215e UW |
8465 | /* Support for floating-point data type variants. */ |
8466 | set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type); | |
8467 | ||
7ad10968 HZ |
8468 | /* Register numbers of various important registers. */ |
8469 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
8470 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
8471 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
8472 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
8473 | ||
8474 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
8475 | numbering schemes on the i386: dbx and SVR4. These schemes | |
8476 | differ in how they number %ebp, %esp, %eflags, and the | |
8477 | floating-point registers, and are implemented by the arrays | |
8478 | dbx_register_map[] and svr4_dbx_register_map in | |
8479 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
8480 | gcc/config/i386.c, which it designates as the "default" register | |
8481 | map used in 64bit mode. This last register numbering scheme is | |
8482 | implemented in dbx64_register_map, and is used for AMD64; see | |
8483 | amd64-tdep.c. | |
8484 | ||
8485 | Currently, each GCC i386 target always uses the same register | |
8486 | numbering scheme across all its supported debugging formats | |
8487 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
8488 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
8489 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
8490 | respective config header in a manner independent of the requested | |
8491 | output debugging format. | |
8492 | ||
8493 | This does not match the arrangement below, which presumes that | |
8494 | the SDB and stabs numbering schemes differ from the DWARF and | |
8495 | DWARF 2 ones. The reason for this arrangement is that it is | |
8496 | likely to get the numbering scheme for the target's | |
8497 | default/native debug format right. For targets where GCC is the | |
8498 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
8499 | targets where the native toolchain uses a different numbering | |
8500 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
8501 | the defaults below will have to be overridden, like | |
8502 | i386_elf_init_abi() does. */ | |
8503 | ||
8504 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
8505 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8506 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8507 | ||
8508 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
0fde2c53 | 8509 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum); |
7ad10968 HZ |
8510 | |
8511 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
8512 | be in use on any of the supported i386 targets. */ | |
8513 | ||
8514 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
8515 | ||
8516 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
8517 | ||
8518 | /* Call dummy code. */ | |
a9b8d892 JK |
8519 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8520 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 8521 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 8522 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
8523 | |
8524 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
8525 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
8526 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
8527 | ||
8528 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
8529 | ||
8530 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
8531 | ||
8532 | /* Stack grows downward. */ | |
8533 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8534 | ||
04180708 YQ |
8535 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc); |
8536 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind); | |
8537 | ||
7ad10968 HZ |
8538 | set_gdbarch_decr_pc_after_break (gdbarch, 1); |
8539 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
8540 | ||
8541 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
8542 | ||
7ad10968 HZ |
8543 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
8544 | ||
8545 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
8546 | ||
8547 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
8548 | ||
8549 | /* Add the i386 register groups. */ | |
8550 | i386_add_reggroups (gdbarch); | |
90884b2b | 8551 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 8552 | |
143985b7 AF |
8553 | /* Helper for function argument information. */ |
8554 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
8555 | ||
06da04c6 | 8556 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
8557 | appended to the list first, so that it supercedes the DWARF |
8558 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
8559 | currently fails). */ |
8560 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
8561 | ||
8562 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 8563 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 8564 | CFI info will be used if it is available. */ |
10458914 | 8565 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 8566 | |
acd5c798 | 8567 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 8568 | |
1ba53b71 | 8569 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
8570 | set_gdbarch_pseudo_register_read_value (gdbarch, |
8571 | i386_pseudo_register_read_value); | |
90884b2b | 8572 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
62e5fd57 MK |
8573 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8574 | i386_ax_pseudo_register_collect); | |
90884b2b L |
8575 | |
8576 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
8577 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
8578 | ||
c131fcee L |
8579 | /* Override the normal target description method to make the AVX |
8580 | upper halves anonymous. */ | |
8581 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
8582 | ||
8583 | /* Even though the default ABI only includes general-purpose registers, | |
8584 | floating-point registers and the SSE registers, we have to leave a | |
01f9f808 | 8585 | gap for the upper AVX, MPX and AVX512 registers. */ |
1163a4b7 | 8586 | set_gdbarch_num_regs (gdbarch, I386_NUM_REGS); |
90884b2b | 8587 | |
ac04f72b TT |
8588 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); |
8589 | ||
90884b2b L |
8590 | /* Get the x86 target description from INFO. */ |
8591 | tdesc = info.target_desc; | |
8592 | if (! tdesc_has_registers (tdesc)) | |
1163a4b7 | 8593 | tdesc = i386_target_description (X86_XSTATE_SSE_MASK, false); |
90884b2b L |
8594 | tdep->tdesc = tdesc; |
8595 | ||
8596 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
8597 | tdep->register_names = i386_register_names; | |
8598 | ||
c131fcee L |
8599 | /* No upper YMM registers. */ |
8600 | tdep->ymmh_register_names = NULL; | |
8601 | tdep->ymm0h_regnum = -1; | |
8602 | ||
01f9f808 MS |
8603 | /* No upper ZMM registers. */ |
8604 | tdep->zmmh_register_names = NULL; | |
8605 | tdep->zmm0h_regnum = -1; | |
8606 | ||
8607 | /* No high XMM registers. */ | |
8608 | tdep->xmm_avx512_register_names = NULL; | |
8609 | tdep->xmm16_regnum = -1; | |
8610 | ||
8611 | /* No upper YMM16-31 registers. */ | |
8612 | tdep->ymm16h_register_names = NULL; | |
8613 | tdep->ymm16h_regnum = -1; | |
8614 | ||
1ba53b71 L |
8615 | tdep->num_byte_regs = 8; |
8616 | tdep->num_word_regs = 8; | |
8617 | tdep->num_dword_regs = 0; | |
8618 | tdep->num_mmx_regs = 8; | |
c131fcee | 8619 | tdep->num_ymm_regs = 0; |
1ba53b71 | 8620 | |
1dbcd68c WT |
8621 | /* No MPX registers. */ |
8622 | tdep->bnd0r_regnum = -1; | |
8623 | tdep->bndcfgu_regnum = -1; | |
8624 | ||
01f9f808 MS |
8625 | /* No AVX512 registers. */ |
8626 | tdep->k0_regnum = -1; | |
8627 | tdep->num_zmm_regs = 0; | |
8628 | tdep->num_ymm_avx512_regs = 0; | |
8629 | tdep->num_xmm_avx512_regs = 0; | |
8630 | ||
51547df6 MS |
8631 | /* No PKEYS registers */ |
8632 | tdep->pkru_regnum = -1; | |
8633 | tdep->num_pkeys_regs = 0; | |
8634 | ||
1163a4b7 JB |
8635 | /* No segment base registers. */ |
8636 | tdep->fsbase_regnum = -1; | |
8637 | ||
90884b2b L |
8638 | tdesc_data = tdesc_data_alloc (); |
8639 | ||
dde08ee1 PA |
8640 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
8641 | ||
6710bf39 SS |
8642 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
8643 | ||
c2170eef MM |
8644 | set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); |
8645 | set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); | |
8646 | set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); | |
8647 | ||
ad9eb1fd DE |
8648 | /* Hook in ABI-specific overrides, if they have been registered. |
8649 | Note: If INFO specifies a 64 bit arch, this is where we turn | |
8650 | a 32-bit i386 into a 64-bit amd64. */ | |
0dba2a6c | 8651 | info.tdesc_data = tdesc_data; |
4be87837 | 8652 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 8653 | |
c131fcee L |
8654 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
8655 | { | |
8656 | tdesc_data_cleanup (tdesc_data); | |
8657 | xfree (tdep); | |
8658 | gdbarch_free (gdbarch); | |
8659 | return NULL; | |
8660 | } | |
8661 | ||
1dbcd68c WT |
8662 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
8663 | ||
1ba53b71 L |
8664 | /* Wire in pseudo registers. Number of pseudo registers may be |
8665 | changed. */ | |
8666 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8667 | + tdep->num_word_regs | |
8668 | + tdep->num_dword_regs | |
c131fcee | 8669 | + tdep->num_mmx_regs |
1dbcd68c | 8670 | + tdep->num_ymm_regs |
01f9f808 MS |
8671 | + num_bnd_cooked |
8672 | + tdep->num_ymm_avx512_regs | |
8673 | + tdep->num_zmm_regs)); | |
1ba53b71 | 8674 | |
90884b2b L |
8675 | /* Target description may be changed. */ |
8676 | tdesc = tdep->tdesc; | |
8677 | ||
90884b2b L |
8678 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
8679 | ||
8680 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8681 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8682 | ||
1ba53b71 L |
8683 | /* Make %al the first pseudo-register. */ |
8684 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8685 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8686 | ||
c131fcee | 8687 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8688 | if (tdep->num_dword_regs) |
8689 | { | |
1c6272a6 | 8690 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8691 | tdep->eax_regnum = ymm0_regnum; |
8692 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8693 | } |
8694 | else | |
8695 | tdep->eax_regnum = -1; | |
8696 | ||
c131fcee L |
8697 | mm0_regnum = ymm0_regnum; |
8698 | if (tdep->num_ymm_regs) | |
8699 | { | |
1c6272a6 | 8700 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8701 | tdep->ymm0_regnum = ymm0_regnum; |
8702 | mm0_regnum += tdep->num_ymm_regs; | |
8703 | } | |
8704 | else | |
8705 | tdep->ymm0_regnum = -1; | |
8706 | ||
01f9f808 MS |
8707 | if (tdep->num_ymm_avx512_regs) |
8708 | { | |
8709 | /* Support YMM16-31 pseudo registers if available. */ | |
8710 | tdep->ymm16_regnum = mm0_regnum; | |
8711 | mm0_regnum += tdep->num_ymm_avx512_regs; | |
8712 | } | |
8713 | else | |
8714 | tdep->ymm16_regnum = -1; | |
8715 | ||
8716 | if (tdep->num_zmm_regs) | |
8717 | { | |
8718 | /* Support ZMM pseudo-register if it is available. */ | |
8719 | tdep->zmm0_regnum = mm0_regnum; | |
8720 | mm0_regnum += tdep->num_zmm_regs; | |
8721 | } | |
8722 | else | |
8723 | tdep->zmm0_regnum = -1; | |
8724 | ||
1dbcd68c | 8725 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8726 | if (tdep->num_mmx_regs != 0) |
8727 | { | |
1c6272a6 | 8728 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8729 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8730 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8731 | } |
8732 | else | |
8733 | tdep->mm0_regnum = -1; | |
8734 | ||
1dbcd68c WT |
8735 | if (tdep->bnd0r_regnum > 0) |
8736 | tdep->bnd0_regnum = bnd0_regnum; | |
8737 | else | |
8738 | tdep-> bnd0_regnum = -1; | |
8739 | ||
06da04c6 | 8740 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 8741 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
8742 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
8743 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 8744 | |
8446b36a MK |
8745 | /* If we have a register mapping, enable the generic core file |
8746 | support, unless it has already been enabled. */ | |
8747 | if (tdep->gregset_reg_offset | |
8f0435f7 | 8748 | && !gdbarch_iterate_over_regset_sections_p (gdbarch)) |
490496c3 AA |
8749 | set_gdbarch_iterate_over_regset_sections |
8750 | (gdbarch, i386_iterate_over_regset_sections); | |
8446b36a | 8751 | |
7a697b8d SS |
8752 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8753 | i386_fast_tracepoint_valid_at); | |
8754 | ||
a62cc96e AC |
8755 | return gdbarch; |
8756 | } | |
8757 | ||
8201327c MK |
8758 | \f |
8759 | ||
97de3545 JB |
8760 | /* Return the target description for a specified XSAVE feature mask. */ |
8761 | ||
8762 | const struct target_desc * | |
1163a4b7 | 8763 | i386_target_description (uint64_t xcr0, bool segments) |
97de3545 | 8764 | { |
22916b07 | 8765 | static target_desc *i386_tdescs \ |
1163a4b7 | 8766 | [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {}; |
22916b07 YQ |
8767 | target_desc **tdesc; |
8768 | ||
8769 | tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0] | |
8770 | [(xcr0 & X86_XSTATE_AVX) ? 1 : 0] | |
8771 | [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] | |
8772 | [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] | |
1163a4b7 JB |
8773 | [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0] |
8774 | [segments ? 1 : 0]; | |
22916b07 YQ |
8775 | |
8776 | if (*tdesc == NULL) | |
1163a4b7 | 8777 | *tdesc = i386_create_target_description (xcr0, false, segments); |
22916b07 YQ |
8778 | |
8779 | return *tdesc; | |
97de3545 JB |
8780 | } |
8781 | ||
29c1c244 WT |
8782 | #define MPX_BASE_MASK (~(ULONGEST) 0xfff) |
8783 | ||
8784 | /* Find the bound directory base address. */ | |
8785 | ||
8786 | static unsigned long | |
8787 | i386_mpx_bd_base (void) | |
8788 | { | |
8789 | struct regcache *rcache; | |
8790 | struct gdbarch_tdep *tdep; | |
8791 | ULONGEST ret; | |
8792 | enum register_status regstatus; | |
29c1c244 WT |
8793 | |
8794 | rcache = get_current_regcache (); | |
ac7936df | 8795 | tdep = gdbarch_tdep (rcache->arch ()); |
29c1c244 WT |
8796 | |
8797 | regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret); | |
8798 | ||
8799 | if (regstatus != REG_VALID) | |
8800 | error (_("BNDCFGU register invalid, read status %d."), regstatus); | |
8801 | ||
8802 | return ret & MPX_BASE_MASK; | |
8803 | } | |
8804 | ||
012b3a21 | 8805 | int |
29c1c244 WT |
8806 | i386_mpx_enabled (void) |
8807 | { | |
8808 | const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ()); | |
8809 | const struct target_desc *tdesc = tdep->tdesc; | |
8810 | ||
8811 | return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL); | |
8812 | } | |
8813 | ||
8814 | #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */ | |
8815 | #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */ | |
8816 | #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */ | |
8817 | #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */ | |
8818 | ||
8819 | /* Find the bound table entry given the pointer location and the base | |
8820 | address of the table. */ | |
8821 | ||
8822 | static CORE_ADDR | |
8823 | i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base) | |
8824 | { | |
8825 | CORE_ADDR offset1; | |
8826 | CORE_ADDR offset2; | |
8827 | CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift; | |
8828 | CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift; | |
8829 | CORE_ADDR bd_entry_addr; | |
8830 | CORE_ADDR bt_addr; | |
8831 | CORE_ADDR bd_entry; | |
8832 | struct gdbarch *gdbarch = get_current_arch (); | |
8833 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8834 | ||
8835 | ||
8836 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8837 | { | |
966f0aef | 8838 | mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK; |
29c1c244 WT |
8839 | bd_ptr_r_shift = 20; |
8840 | bd_ptr_l_shift = 3; | |
8841 | bt_select_r_shift = 3; | |
8842 | bt_select_l_shift = 5; | |
966f0aef WT |
8843 | bt_mask = (CORE_ADDR) MPX_BT_MASK; |
8844 | ||
8845 | if ( sizeof (CORE_ADDR) == 4) | |
e00b3c9b WT |
8846 | error (_("bound table examination not supported\ |
8847 | for 64-bit process with 32-bit GDB")); | |
29c1c244 WT |
8848 | } |
8849 | else | |
8850 | { | |
8851 | mpx_bd_mask = MPX_BD_MASK_32; | |
8852 | bd_ptr_r_shift = 12; | |
8853 | bd_ptr_l_shift = 2; | |
8854 | bt_select_r_shift = 2; | |
8855 | bt_select_l_shift = 4; | |
8856 | bt_mask = MPX_BT_MASK_32; | |
8857 | } | |
8858 | ||
8859 | offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift; | |
8860 | bd_entry_addr = bd_base + offset1; | |
8861 | bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type); | |
8862 | ||
8863 | if ((bd_entry & 0x1) == 0) | |
8864 | error (_("Invalid bounds directory entry at %s."), | |
8865 | paddress (get_current_arch (), bd_entry_addr)); | |
8866 | ||
8867 | /* Clearing status bit. */ | |
8868 | bd_entry--; | |
8869 | bt_addr = bd_entry & ~bt_select_r_shift; | |
8870 | offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift; | |
8871 | ||
8872 | return bt_addr + offset2; | |
8873 | } | |
8874 | ||
8875 | /* Print routine for the mpx bounds. */ | |
8876 | ||
8877 | static void | |
8878 | i386_mpx_print_bounds (const CORE_ADDR bt_entry[4]) | |
8879 | { | |
8880 | struct ui_out *uiout = current_uiout; | |
34f8ac9f | 8881 | LONGEST size; |
29c1c244 WT |
8882 | struct gdbarch *gdbarch = get_current_arch (); |
8883 | CORE_ADDR onecompl = ~((CORE_ADDR) 0); | |
8884 | int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0); | |
8885 | ||
8886 | if (bounds_in_map == 1) | |
8887 | { | |
112e8700 SM |
8888 | uiout->text ("Null bounds on map:"); |
8889 | uiout->text (" pointer value = "); | |
8890 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
8891 | uiout->text ("."); | |
8892 | uiout->text ("\n"); | |
29c1c244 WT |
8893 | } |
8894 | else | |
8895 | { | |
112e8700 SM |
8896 | uiout->text ("{lbound = "); |
8897 | uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]); | |
8898 | uiout->text (", ubound = "); | |
29c1c244 WT |
8899 | |
8900 | /* The upper bound is stored in 1's complement. */ | |
112e8700 SM |
8901 | uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]); |
8902 | uiout->text ("}: pointer value = "); | |
8903 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
29c1c244 WT |
8904 | |
8905 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8906 | size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]); | |
8907 | else | |
8908 | size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]); | |
8909 | ||
8910 | /* In case the bounds are 0x0 and 0xffff... the difference will be -1. | |
8911 | -1 represents in this sense full memory access, and there is no need | |
8912 | one to the size. */ | |
8913 | ||
8914 | size = (size > -1 ? size + 1 : size); | |
112e8700 | 8915 | uiout->text (", size = "); |
33eca680 | 8916 | uiout->field_string ("size", plongest (size)); |
29c1c244 | 8917 | |
112e8700 SM |
8918 | uiout->text (", metadata = "); |
8919 | uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]); | |
8920 | uiout->text ("\n"); | |
29c1c244 WT |
8921 | } |
8922 | } | |
8923 | ||
8924 | /* Implement the command "show mpx bound". */ | |
8925 | ||
8926 | static void | |
c4a3e68e | 8927 | i386_mpx_info_bounds (const char *args, int from_tty) |
29c1c244 WT |
8928 | { |
8929 | CORE_ADDR bd_base = 0; | |
8930 | CORE_ADDR addr; | |
8931 | CORE_ADDR bt_entry_addr = 0; | |
8932 | CORE_ADDR bt_entry[4]; | |
8933 | int i; | |
8934 | struct gdbarch *gdbarch = get_current_arch (); | |
8935 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8936 | ||
ae71e7b5 MR |
8937 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8938 | || !i386_mpx_enabled ()) | |
118ca224 | 8939 | { |
bc504a31 | 8940 | printf_unfiltered (_("Intel Memory Protection Extensions not " |
118ca224 PP |
8941 | "supported on this target.\n")); |
8942 | return; | |
8943 | } | |
29c1c244 WT |
8944 | |
8945 | if (args == NULL) | |
118ca224 PP |
8946 | { |
8947 | printf_unfiltered (_("Address of pointer variable expected.\n")); | |
8948 | return; | |
8949 | } | |
29c1c244 WT |
8950 | |
8951 | addr = parse_and_eval_address (args); | |
8952 | ||
8953 | bd_base = i386_mpx_bd_base (); | |
8954 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8955 | ||
8956 | memset (bt_entry, 0, sizeof (bt_entry)); | |
8957 | ||
8958 | for (i = 0; i < 4; i++) | |
8959 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 8960 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
8961 | data_ptr_type); |
8962 | ||
8963 | i386_mpx_print_bounds (bt_entry); | |
8964 | } | |
8965 | ||
8966 | /* Implement the command "set mpx bound". */ | |
8967 | ||
8968 | static void | |
c4a3e68e | 8969 | i386_mpx_set_bounds (const char *args, int from_tty) |
29c1c244 WT |
8970 | { |
8971 | CORE_ADDR bd_base = 0; | |
8972 | CORE_ADDR addr, lower, upper; | |
8973 | CORE_ADDR bt_entry_addr = 0; | |
8974 | CORE_ADDR bt_entry[2]; | |
8975 | const char *input = args; | |
8976 | int i; | |
8977 | struct gdbarch *gdbarch = get_current_arch (); | |
8978 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8979 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8980 | ||
ae71e7b5 MR |
8981 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8982 | || !i386_mpx_enabled ()) | |
bc504a31 | 8983 | error (_("Intel Memory Protection Extensions not supported\ |
29c1c244 WT |
8984 | on this target.")); |
8985 | ||
8986 | if (args == NULL) | |
8987 | error (_("Pointer value expected.")); | |
8988 | ||
8989 | addr = value_as_address (parse_to_comma_and_eval (&input)); | |
8990 | ||
8991 | if (input[0] == ',') | |
8992 | ++input; | |
8993 | if (input[0] == '\0') | |
8994 | error (_("wrong number of arguments: missing lower and upper bound.")); | |
8995 | lower = value_as_address (parse_to_comma_and_eval (&input)); | |
8996 | ||
8997 | if (input[0] == ',') | |
8998 | ++input; | |
8999 | if (input[0] == '\0') | |
9000 | error (_("Wrong number of arguments; Missing upper bound.")); | |
9001 | upper = value_as_address (parse_to_comma_and_eval (&input)); | |
9002 | ||
9003 | bd_base = i386_mpx_bd_base (); | |
9004 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
9005 | for (i = 0; i < 2; i++) | |
9006 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 9007 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
9008 | data_ptr_type); |
9009 | bt_entry[0] = (uint64_t) lower; | |
9010 | bt_entry[1] = ~(uint64_t) upper; | |
9011 | ||
9012 | for (i = 0; i < 2; i++) | |
132874d7 AB |
9013 | write_memory_unsigned_integer (bt_entry_addr |
9014 | + i * TYPE_LENGTH (data_ptr_type), | |
9015 | TYPE_LENGTH (data_ptr_type), byte_order, | |
29c1c244 WT |
9016 | bt_entry[i]); |
9017 | } | |
9018 | ||
9019 | static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist; | |
9020 | ||
6c265988 | 9021 | void _initialize_i386_tdep (); |
c906108c | 9022 | void |
6c265988 | 9023 | _initialize_i386_tdep () |
c906108c | 9024 | { |
a62cc96e AC |
9025 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
9026 | ||
fc338970 | 9027 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
9028 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
9029 | &disassembly_flavor, _("\ | |
9030 | Set the disassembly flavor."), _("\ | |
9031 | Show the disassembly flavor."), _("\ | |
9032 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
9033 | NULL, | |
9034 | NULL, /* FIXME: i18n: */ | |
9035 | &setlist, &showlist); | |
8201327c MK |
9036 | |
9037 | /* Add the variable that controls the convention for returning | |
9038 | structs. */ | |
7ab04401 AC |
9039 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
9040 | &struct_convention, _("\ | |
9041 | Set the convention for returning small structs."), _("\ | |
9042 | Show the convention for returning small structs."), _("\ | |
9043 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
9044 | is \"default\"."), | |
9045 | NULL, | |
9046 | NULL, /* FIXME: i18n: */ | |
9047 | &setlist, &showlist); | |
8201327c | 9048 | |
29c1c244 WT |
9049 | /* Add "mpx" prefix for the set commands. */ |
9050 | ||
0743fc83 | 9051 | add_basic_prefix_cmd ("mpx", class_support, _("\ |
bc504a31 | 9052 | Set Intel Memory Protection Extensions specific variables."), |
0743fc83 TT |
9053 | &mpx_set_cmdlist, "set mpx ", |
9054 | 0 /* allow-unknown */, &setlist); | |
29c1c244 WT |
9055 | |
9056 | /* Add "mpx" prefix for the show commands. */ | |
9057 | ||
0743fc83 | 9058 | add_show_prefix_cmd ("mpx", class_support, _("\ |
bc504a31 | 9059 | Show Intel Memory Protection Extensions specific variables."), |
0743fc83 TT |
9060 | &mpx_show_cmdlist, "show mpx ", |
9061 | 0 /* allow-unknown */, &showlist); | |
29c1c244 WT |
9062 | |
9063 | /* Add "bound" command for the show mpx commands list. */ | |
9064 | ||
9065 | add_cmd ("bound", no_class, i386_mpx_info_bounds, | |
9066 | "Show the memory bounds for a given array/pointer storage\ | |
9067 | in the bound table.", | |
9068 | &mpx_show_cmdlist); | |
9069 | ||
9070 | /* Add "bound" command for the set mpx commands list. */ | |
9071 | ||
9072 | add_cmd ("bound", no_class, i386_mpx_set_bounds, | |
9073 | "Set the memory bounds for a given array/pointer storage\ | |
9074 | in the bound table.", | |
9075 | &mpx_set_cmdlist); | |
9076 | ||
05816f70 | 9077 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 9078 | i386_svr4_init_abi); |
38c968cf | 9079 | |
209bd28e | 9080 | /* Initialize the i386-specific register groups. */ |
38c968cf | 9081 | i386_init_reggroups (); |
90884b2b | 9082 | |
c8d5aac9 L |
9083 | /* Tell remote stub that we support XML target description. */ |
9084 | register_remote_support_xml ("i386"); | |
c906108c | 9085 | } |