Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
7b6bb8da | 5 | 2010, 2011 Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
7a697b8d | 46 | #include "disasm.h" |
c8d5aac9 | 47 | #include "remote.h" |
8fbca658 | 48 | #include "exceptions.h" |
3d261580 | 49 | #include "gdb_assert.h" |
acd5c798 | 50 | #include "gdb_string.h" |
3d261580 | 51 | |
d2a7c97a | 52 | #include "i386-tdep.h" |
61113f8b | 53 | #include "i387-tdep.h" |
c131fcee | 54 | #include "i386-xstate.h" |
d2a7c97a | 55 | |
7ad10968 HZ |
56 | #include "record.h" |
57 | #include <stdint.h> | |
58 | ||
90884b2b | 59 | #include "features/i386/i386.c" |
c131fcee | 60 | #include "features/i386/i386-avx.c" |
3a13a53b | 61 | #include "features/i386/i386-mmx.c" |
90884b2b | 62 | |
c4fc7f1b | 63 | /* Register names. */ |
c40e1eab | 64 | |
90884b2b | 65 | static const char *i386_register_names[] = |
fc633446 MK |
66 | { |
67 | "eax", "ecx", "edx", "ebx", | |
68 | "esp", "ebp", "esi", "edi", | |
69 | "eip", "eflags", "cs", "ss", | |
70 | "ds", "es", "fs", "gs", | |
71 | "st0", "st1", "st2", "st3", | |
72 | "st4", "st5", "st6", "st7", | |
73 | "fctrl", "fstat", "ftag", "fiseg", | |
74 | "fioff", "foseg", "fooff", "fop", | |
75 | "xmm0", "xmm1", "xmm2", "xmm3", | |
76 | "xmm4", "xmm5", "xmm6", "xmm7", | |
77 | "mxcsr" | |
78 | }; | |
79 | ||
c131fcee L |
80 | static const char *i386_ymm_names[] = |
81 | { | |
82 | "ymm0", "ymm1", "ymm2", "ymm3", | |
83 | "ymm4", "ymm5", "ymm6", "ymm7", | |
84 | }; | |
85 | ||
86 | static const char *i386_ymmh_names[] = | |
87 | { | |
88 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
89 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
90 | }; | |
91 | ||
c4fc7f1b | 92 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 93 | |
90884b2b | 94 | static const char *i386_mmx_names[] = |
28fc6740 AC |
95 | { |
96 | "mm0", "mm1", "mm2", "mm3", | |
97 | "mm4", "mm5", "mm6", "mm7" | |
98 | }; | |
c40e1eab | 99 | |
1ba53b71 L |
100 | /* Register names for byte pseudo-registers. */ |
101 | ||
102 | static const char *i386_byte_names[] = | |
103 | { | |
104 | "al", "cl", "dl", "bl", | |
105 | "ah", "ch", "dh", "bh" | |
106 | }; | |
107 | ||
108 | /* Register names for word pseudo-registers. */ | |
109 | ||
110 | static const char *i386_word_names[] = | |
111 | { | |
112 | "ax", "cx", "dx", "bx", | |
9cad29ac | 113 | "", "bp", "si", "di" |
1ba53b71 L |
114 | }; |
115 | ||
116 | /* MMX register? */ | |
c40e1eab | 117 | |
28fc6740 | 118 | static int |
5716833c | 119 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 120 | { |
1ba53b71 L |
121 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
122 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
123 | |
124 | if (mm0_regnum < 0) | |
125 | return 0; | |
126 | ||
1ba53b71 L |
127 | regnum -= mm0_regnum; |
128 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
129 | } | |
130 | ||
131 | /* Byte register? */ | |
132 | ||
133 | int | |
134 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
135 | { | |
136 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
137 | ||
138 | regnum -= tdep->al_regnum; | |
139 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
140 | } | |
141 | ||
142 | /* Word register? */ | |
143 | ||
144 | int | |
145 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
146 | { | |
147 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
148 | ||
149 | regnum -= tdep->ax_regnum; | |
150 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
151 | } | |
152 | ||
153 | /* Dword register? */ | |
154 | ||
155 | int | |
156 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
157 | { | |
158 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
159 | int eax_regnum = tdep->eax_regnum; | |
160 | ||
161 | if (eax_regnum < 0) | |
162 | return 0; | |
163 | ||
164 | regnum -= eax_regnum; | |
165 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
166 | } |
167 | ||
9191d390 | 168 | static int |
c131fcee L |
169 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
170 | { | |
171 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
172 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
173 | ||
174 | if (ymm0h_regnum < 0) | |
175 | return 0; | |
176 | ||
177 | regnum -= ymm0h_regnum; | |
178 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
179 | } | |
180 | ||
181 | /* AVX register? */ | |
182 | ||
183 | int | |
184 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
185 | { | |
186 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
187 | int ymm0_regnum = tdep->ymm0_regnum; | |
188 | ||
189 | if (ymm0_regnum < 0) | |
190 | return 0; | |
191 | ||
192 | regnum -= ymm0_regnum; | |
193 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
194 | } | |
195 | ||
5716833c | 196 | /* SSE register? */ |
23a34459 | 197 | |
c131fcee L |
198 | int |
199 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 200 | { |
5716833c | 201 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 202 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 203 | |
c131fcee | 204 | if (num_xmm_regs == 0) |
5716833c MK |
205 | return 0; |
206 | ||
c131fcee L |
207 | regnum -= I387_XMM0_REGNUM (tdep); |
208 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
209 | } |
210 | ||
5716833c MK |
211 | static int |
212 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 213 | { |
5716833c MK |
214 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
215 | ||
20a6ec49 | 216 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
217 | return 0; |
218 | ||
20a6ec49 | 219 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
220 | } |
221 | ||
5716833c | 222 | /* FP register? */ |
23a34459 AC |
223 | |
224 | int | |
20a6ec49 | 225 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 226 | { |
20a6ec49 MD |
227 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
228 | ||
229 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
230 | return 0; |
231 | ||
20a6ec49 MD |
232 | return (I387_ST0_REGNUM (tdep) <= regnum |
233 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
234 | } |
235 | ||
236 | int | |
20a6ec49 | 237 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 238 | { |
20a6ec49 MD |
239 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
240 | ||
241 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
242 | return 0; |
243 | ||
20a6ec49 MD |
244 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
245 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
246 | } |
247 | ||
c131fcee L |
248 | /* Return the name of register REGNUM, or the empty string if it is |
249 | an anonymous register. */ | |
250 | ||
251 | static const char * | |
252 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
253 | { | |
254 | /* Hide the upper YMM registers. */ | |
255 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
256 | return ""; | |
257 | ||
258 | return tdesc_register_name (gdbarch, regnum); | |
259 | } | |
260 | ||
30b0e2d8 | 261 | /* Return the name of register REGNUM. */ |
fc633446 | 262 | |
1ba53b71 | 263 | const char * |
90884b2b | 264 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 265 | { |
1ba53b71 L |
266 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
267 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
268 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
269 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
270 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
1ba53b71 L |
271 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
272 | return i386_byte_names[regnum - tdep->al_regnum]; | |
273 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
274 | return i386_word_names[regnum - tdep->ax_regnum]; | |
275 | ||
276 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
277 | } |
278 | ||
c4fc7f1b | 279 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
280 | number used by GDB. */ |
281 | ||
8201327c | 282 | static int |
d3f73121 | 283 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 284 | { |
20a6ec49 MD |
285 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
286 | ||
c4fc7f1b MK |
287 | /* This implements what GCC calls the "default" register map |
288 | (dbx_register_map[]). */ | |
289 | ||
85540d8c MK |
290 | if (reg >= 0 && reg <= 7) |
291 | { | |
9872ad24 JB |
292 | /* General-purpose registers. The debug info calls %ebp |
293 | register 4, and %esp register 5. */ | |
294 | if (reg == 4) | |
295 | return 5; | |
296 | else if (reg == 5) | |
297 | return 4; | |
298 | else return reg; | |
85540d8c MK |
299 | } |
300 | else if (reg >= 12 && reg <= 19) | |
301 | { | |
302 | /* Floating-point registers. */ | |
20a6ec49 | 303 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
304 | } |
305 | else if (reg >= 21 && reg <= 28) | |
306 | { | |
307 | /* SSE registers. */ | |
c131fcee L |
308 | int ymm0_regnum = tdep->ymm0_regnum; |
309 | ||
310 | if (ymm0_regnum >= 0 | |
311 | && i386_xmm_regnum_p (gdbarch, reg)) | |
312 | return reg - 21 + ymm0_regnum; | |
313 | else | |
314 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
315 | } |
316 | else if (reg >= 29 && reg <= 36) | |
317 | { | |
318 | /* MMX registers. */ | |
20a6ec49 | 319 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
320 | } |
321 | ||
322 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 323 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
324 | } |
325 | ||
c4fc7f1b MK |
326 | /* Convert SVR4 register number REG to the appropriate register number |
327 | used by GDB. */ | |
85540d8c | 328 | |
8201327c | 329 | static int |
d3f73121 | 330 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 331 | { |
20a6ec49 MD |
332 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
333 | ||
c4fc7f1b MK |
334 | /* This implements the GCC register map that tries to be compatible |
335 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
336 | ||
337 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
338 | numbers the floating point registers differently. */ |
339 | if (reg >= 0 && reg <= 9) | |
340 | { | |
acd5c798 | 341 | /* General-purpose registers. */ |
85540d8c MK |
342 | return reg; |
343 | } | |
344 | else if (reg >= 11 && reg <= 18) | |
345 | { | |
346 | /* Floating-point registers. */ | |
20a6ec49 | 347 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 348 | } |
c6f4c129 | 349 | else if (reg >= 21 && reg <= 36) |
85540d8c | 350 | { |
c4fc7f1b | 351 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 352 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
353 | } |
354 | ||
c6f4c129 JB |
355 | switch (reg) |
356 | { | |
20a6ec49 MD |
357 | case 37: return I387_FCTRL_REGNUM (tdep); |
358 | case 38: return I387_FSTAT_REGNUM (tdep); | |
359 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
360 | case 40: return I386_ES_REGNUM; |
361 | case 41: return I386_CS_REGNUM; | |
362 | case 42: return I386_SS_REGNUM; | |
363 | case 43: return I386_DS_REGNUM; | |
364 | case 44: return I386_FS_REGNUM; | |
365 | case 45: return I386_GS_REGNUM; | |
366 | } | |
367 | ||
85540d8c | 368 | /* This will hopefully provoke a warning. */ |
d3f73121 | 369 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 370 | } |
5716833c | 371 | |
fc338970 | 372 | \f |
917317f4 | 373 | |
fc338970 MK |
374 | /* This is the variable that is set with "set disassembly-flavor", and |
375 | its legitimate values. */ | |
53904c9e AC |
376 | static const char att_flavor[] = "att"; |
377 | static const char intel_flavor[] = "intel"; | |
378 | static const char *valid_flavors[] = | |
c5aa993b | 379 | { |
c906108c SS |
380 | att_flavor, |
381 | intel_flavor, | |
382 | NULL | |
383 | }; | |
53904c9e | 384 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 385 | \f |
c906108c | 386 | |
acd5c798 MK |
387 | /* Use the program counter to determine the contents and size of a |
388 | breakpoint instruction. Return a pointer to a string of bytes that | |
389 | encode a breakpoint instruction, store the length of the string in | |
390 | *LEN and optionally adjust *PC to point to the correct memory | |
391 | location for inserting the breakpoint. | |
c906108c | 392 | |
acd5c798 MK |
393 | On the i386 we have a single breakpoint that fits in a single byte |
394 | and can be inserted anywhere. | |
c906108c | 395 | |
acd5c798 | 396 | This function is 64-bit safe. */ |
63c0089f MK |
397 | |
398 | static const gdb_byte * | |
67d57894 | 399 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 400 | { |
63c0089f MK |
401 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
402 | ||
acd5c798 MK |
403 | *len = sizeof (break_insn); |
404 | return break_insn; | |
c906108c | 405 | } |
237fc4c9 PA |
406 | \f |
407 | /* Displaced instruction handling. */ | |
408 | ||
1903f0e6 DE |
409 | /* Skip the legacy instruction prefixes in INSN. |
410 | Not all prefixes are valid for any particular insn | |
411 | but we needn't care, the insn will fault if it's invalid. | |
412 | The result is a pointer to the first opcode byte, | |
413 | or NULL if we run off the end of the buffer. */ | |
414 | ||
415 | static gdb_byte * | |
416 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
417 | { | |
418 | gdb_byte *end = insn + max_len; | |
419 | ||
420 | while (insn < end) | |
421 | { | |
422 | switch (*insn) | |
423 | { | |
424 | case DATA_PREFIX_OPCODE: | |
425 | case ADDR_PREFIX_OPCODE: | |
426 | case CS_PREFIX_OPCODE: | |
427 | case DS_PREFIX_OPCODE: | |
428 | case ES_PREFIX_OPCODE: | |
429 | case FS_PREFIX_OPCODE: | |
430 | case GS_PREFIX_OPCODE: | |
431 | case SS_PREFIX_OPCODE: | |
432 | case LOCK_PREFIX_OPCODE: | |
433 | case REPE_PREFIX_OPCODE: | |
434 | case REPNE_PREFIX_OPCODE: | |
435 | ++insn; | |
436 | continue; | |
437 | default: | |
438 | return insn; | |
439 | } | |
440 | } | |
441 | ||
442 | return NULL; | |
443 | } | |
237fc4c9 PA |
444 | |
445 | static int | |
1903f0e6 | 446 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 447 | { |
1777feb0 | 448 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
449 | if (insn[0] == 0xea) |
450 | return 1; | |
451 | ||
452 | if (insn[0] == 0xff) | |
453 | { | |
1777feb0 | 454 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
455 | if ((insn[1] & 0x38) == 0x20) |
456 | return 1; | |
457 | ||
1777feb0 | 458 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
459 | if ((insn[1] & 0x38) == 0x28) |
460 | return 1; | |
461 | } | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static int | |
1903f0e6 | 467 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 468 | { |
1777feb0 | 469 | /* call far, absolute. */ |
237fc4c9 PA |
470 | if (insn[0] == 0x9a) |
471 | return 1; | |
472 | ||
473 | if (insn[0] == 0xff) | |
474 | { | |
1777feb0 | 475 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
476 | if ((insn[1] & 0x38) == 0x10) |
477 | return 1; | |
478 | ||
1777feb0 | 479 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
480 | if ((insn[1] & 0x38) == 0x18) |
481 | return 1; | |
482 | } | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | static int | |
1903f0e6 | 488 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
489 | { |
490 | switch (insn[0]) | |
491 | { | |
1777feb0 | 492 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 493 | case 0xc3: /* ret near */ |
1777feb0 | 494 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
495 | case 0xcb: /* ret far */ |
496 | case 0xcf: /* iret */ | |
497 | return 1; | |
498 | ||
499 | default: | |
500 | return 0; | |
501 | } | |
502 | } | |
503 | ||
504 | static int | |
1903f0e6 | 505 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
506 | { |
507 | if (i386_absolute_call_p (insn)) | |
508 | return 1; | |
509 | ||
1777feb0 | 510 | /* call near, relative. */ |
237fc4c9 PA |
511 | if (insn[0] == 0xe8) |
512 | return 1; | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
237fc4c9 PA |
517 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
518 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 519 | |
237fc4c9 | 520 | static int |
b55078be | 521 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 PA |
522 | { |
523 | if (insn[0] == 0xcd) | |
524 | { | |
525 | *lengthp = 2; | |
526 | return 1; | |
527 | } | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
b55078be DE |
532 | /* Some kernels may run one past a syscall insn, so we have to cope. |
533 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
534 | ||
535 | struct displaced_step_closure * | |
536 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
537 | CORE_ADDR from, CORE_ADDR to, | |
538 | struct regcache *regs) | |
539 | { | |
540 | size_t len = gdbarch_max_insn_length (gdbarch); | |
541 | gdb_byte *buf = xmalloc (len); | |
542 | ||
543 | read_memory (from, buf, len); | |
544 | ||
545 | /* GDB may get control back after the insn after the syscall. | |
546 | Presumably this is a kernel bug. | |
547 | If this is a syscall, make sure there's a nop afterwards. */ | |
548 | { | |
549 | int syscall_length; | |
550 | gdb_byte *insn; | |
551 | ||
552 | insn = i386_skip_prefixes (buf, len); | |
553 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
554 | insn[syscall_length] = NOP_OPCODE; | |
555 | } | |
556 | ||
557 | write_memory (to, buf, len); | |
558 | ||
559 | if (debug_displaced) | |
560 | { | |
561 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
562 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
563 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
564 | } | |
565 | ||
566 | return (struct displaced_step_closure *) buf; | |
567 | } | |
568 | ||
237fc4c9 PA |
569 | /* Fix up the state of registers and memory after having single-stepped |
570 | a displaced instruction. */ | |
1903f0e6 | 571 | |
237fc4c9 PA |
572 | void |
573 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
574 | struct displaced_step_closure *closure, | |
575 | CORE_ADDR from, CORE_ADDR to, | |
576 | struct regcache *regs) | |
577 | { | |
e17a4113 UW |
578 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
579 | ||
237fc4c9 PA |
580 | /* The offset we applied to the instruction's address. |
581 | This could well be negative (when viewed as a signed 32-bit | |
582 | value), but ULONGEST won't reflect that, so take care when | |
583 | applying it. */ | |
584 | ULONGEST insn_offset = to - from; | |
585 | ||
586 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
587 | copy of the instruction. */ | |
588 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
589 | /* The start of the insn, needed in case we see some prefixes. */ |
590 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
591 | |
592 | if (debug_displaced) | |
593 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 594 | "displaced: fixup (%s, %s), " |
237fc4c9 | 595 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
596 | paddress (gdbarch, from), paddress (gdbarch, to), |
597 | insn[0], insn[1]); | |
237fc4c9 PA |
598 | |
599 | /* The list of issues to contend with here is taken from | |
600 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
601 | Yay for Free Software! */ | |
602 | ||
603 | /* Relocate the %eip, if necessary. */ | |
604 | ||
1903f0e6 DE |
605 | /* The instruction recognizers we use assume any leading prefixes |
606 | have been skipped. */ | |
607 | { | |
608 | /* This is the size of the buffer in closure. */ | |
609 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
610 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
611 | /* If there are too many prefixes, just ignore the insn. | |
612 | It will fault when run. */ | |
613 | if (opcode != NULL) | |
614 | insn = opcode; | |
615 | } | |
616 | ||
237fc4c9 PA |
617 | /* Except in the case of absolute or indirect jump or call |
618 | instructions, or a return instruction, the new eip is relative to | |
619 | the displaced instruction; make it relative. Well, signal | |
620 | handler returns don't need relocation either, but we use the | |
621 | value of %eip to recognize those; see below. */ | |
622 | if (! i386_absolute_jmp_p (insn) | |
623 | && ! i386_absolute_call_p (insn) | |
624 | && ! i386_ret_p (insn)) | |
625 | { | |
626 | ULONGEST orig_eip; | |
b55078be | 627 | int insn_len; |
237fc4c9 PA |
628 | |
629 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
630 | ||
631 | /* A signal trampoline system call changes the %eip, resuming | |
632 | execution of the main program after the signal handler has | |
633 | returned. That makes them like 'return' instructions; we | |
634 | shouldn't relocate %eip. | |
635 | ||
636 | But most system calls don't, and we do need to relocate %eip. | |
637 | ||
638 | Our heuristic for distinguishing these cases: if stepping | |
639 | over the system call instruction left control directly after | |
640 | the instruction, the we relocate --- control almost certainly | |
641 | doesn't belong in the displaced copy. Otherwise, we assume | |
642 | the instruction has put control where it belongs, and leave | |
643 | it unrelocated. Goodness help us if there are PC-relative | |
644 | system calls. */ | |
645 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
646 | && orig_eip != to + (insn - insn_start) + insn_len |
647 | /* GDB can get control back after the insn after the syscall. | |
648 | Presumably this is a kernel bug. | |
649 | i386_displaced_step_copy_insn ensures its a nop, | |
650 | we add one to the length for it. */ | |
651 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
652 | { |
653 | if (debug_displaced) | |
654 | fprintf_unfiltered (gdb_stdlog, | |
655 | "displaced: syscall changed %%eip; " | |
656 | "not relocating\n"); | |
657 | } | |
658 | else | |
659 | { | |
660 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
661 | ||
1903f0e6 DE |
662 | /* If we just stepped over a breakpoint insn, we don't backup |
663 | the pc on purpose; this is to match behaviour without | |
664 | stepping. */ | |
237fc4c9 PA |
665 | |
666 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
667 | ||
668 | if (debug_displaced) | |
669 | fprintf_unfiltered (gdb_stdlog, | |
670 | "displaced: " | |
5af949e3 UW |
671 | "relocated %%eip from %s to %s\n", |
672 | paddress (gdbarch, orig_eip), | |
673 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
674 | } |
675 | } | |
676 | ||
677 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
678 | pushed value, and should be cleared. We'll leave this for later, | |
679 | since GDB already messes up the TF flag when stepping over a | |
680 | pushfl. */ | |
681 | ||
682 | /* If the instruction was a call, the return address now atop the | |
683 | stack is the address following the copied instruction. We need | |
684 | to make it the address following the original instruction. */ | |
685 | if (i386_call_p (insn)) | |
686 | { | |
687 | ULONGEST esp; | |
688 | ULONGEST retaddr; | |
689 | const ULONGEST retaddr_len = 4; | |
690 | ||
691 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 692 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 693 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 694 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
695 | |
696 | if (debug_displaced) | |
697 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
698 | "displaced: relocated return addr at %s to %s\n", |
699 | paddress (gdbarch, esp), | |
700 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
701 | } |
702 | } | |
dde08ee1 PA |
703 | |
704 | static void | |
705 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
706 | { | |
707 | target_write_memory (*to, buf, len); | |
708 | *to += len; | |
709 | } | |
710 | ||
711 | static void | |
712 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
713 | CORE_ADDR *to, CORE_ADDR oldloc) | |
714 | { | |
715 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
716 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
717 | int offset = 0, rel32, newrel; | |
718 | int insn_length; | |
719 | gdb_byte *insn = buf; | |
720 | ||
721 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
722 | ||
723 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
724 | I386_MAX_INSN_LEN, oldloc); | |
725 | ||
726 | /* Get past the prefixes. */ | |
727 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
728 | ||
729 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
730 | the address pushed being the location where the original call in | |
731 | the user program would return to. */ | |
732 | if (insn[0] == 0xe8) | |
733 | { | |
734 | gdb_byte push_buf[16]; | |
735 | unsigned int ret_addr; | |
736 | ||
737 | /* Where "ret" in the original code will return to. */ | |
738 | ret_addr = oldloc + insn_length; | |
1777feb0 | 739 | push_buf[0] = 0x68; /* pushq $... */ |
dde08ee1 PA |
740 | memcpy (&push_buf[1], &ret_addr, 4); |
741 | /* Push the push. */ | |
742 | append_insns (to, 5, push_buf); | |
743 | ||
744 | /* Convert the relative call to a relative jump. */ | |
745 | insn[0] = 0xe9; | |
746 | ||
747 | /* Adjust the destination offset. */ | |
748 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
749 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
750 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
751 | ||
752 | if (debug_displaced) | |
753 | fprintf_unfiltered (gdb_stdlog, | |
754 | "Adjusted insn rel32=%s at %s to" | |
755 | " rel32=%s at %s\n", | |
756 | hex_string (rel32), paddress (gdbarch, oldloc), | |
757 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
758 | |
759 | /* Write the adjusted jump into its displaced location. */ | |
760 | append_insns (to, 5, insn); | |
761 | return; | |
762 | } | |
763 | ||
764 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
765 | handled above. */ | |
766 | if (insn[0] == 0xe9) | |
767 | offset = 1; | |
768 | /* Adjust conditional jumps. */ | |
769 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
770 | offset = 2; | |
771 | ||
772 | if (offset) | |
773 | { | |
774 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
775 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 776 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
777 | if (debug_displaced) |
778 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
779 | "Adjusted insn rel32=%s at %s to" |
780 | " rel32=%s at %s\n", | |
dde08ee1 PA |
781 | hex_string (rel32), paddress (gdbarch, oldloc), |
782 | hex_string (newrel), paddress (gdbarch, *to)); | |
783 | } | |
784 | ||
785 | /* Write the adjusted instructions into their displaced | |
786 | location. */ | |
787 | append_insns (to, insn_length, buf); | |
788 | } | |
789 | ||
fc338970 | 790 | \f |
acd5c798 MK |
791 | #ifdef I386_REGNO_TO_SYMMETRY |
792 | #error "The Sequent Symmetry is no longer supported." | |
793 | #endif | |
c906108c | 794 | |
acd5c798 MK |
795 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
796 | and %esp "belong" to the calling function. Therefore these | |
797 | registers should be saved if they're going to be modified. */ | |
c906108c | 798 | |
acd5c798 MK |
799 | /* The maximum number of saved registers. This should include all |
800 | registers mentioned above, and %eip. */ | |
a3386186 | 801 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
802 | |
803 | struct i386_frame_cache | |
c906108c | 804 | { |
acd5c798 MK |
805 | /* Base address. */ |
806 | CORE_ADDR base; | |
8fbca658 | 807 | int base_p; |
772562f8 | 808 | LONGEST sp_offset; |
acd5c798 MK |
809 | CORE_ADDR pc; |
810 | ||
fd13a04a AC |
811 | /* Saved registers. */ |
812 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 813 | CORE_ADDR saved_sp; |
e0c62198 | 814 | int saved_sp_reg; |
acd5c798 MK |
815 | int pc_in_eax; |
816 | ||
817 | /* Stack space reserved for local variables. */ | |
818 | long locals; | |
819 | }; | |
820 | ||
821 | /* Allocate and initialize a frame cache. */ | |
822 | ||
823 | static struct i386_frame_cache * | |
fd13a04a | 824 | i386_alloc_frame_cache (void) |
acd5c798 MK |
825 | { |
826 | struct i386_frame_cache *cache; | |
827 | int i; | |
828 | ||
829 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
830 | ||
831 | /* Base address. */ | |
8fbca658 | 832 | cache->base_p = 0; |
acd5c798 MK |
833 | cache->base = 0; |
834 | cache->sp_offset = -4; | |
835 | cache->pc = 0; | |
836 | ||
fd13a04a AC |
837 | /* Saved registers. We initialize these to -1 since zero is a valid |
838 | offset (that's where %ebp is supposed to be stored). */ | |
839 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
840 | cache->saved_regs[i] = -1; | |
acd5c798 | 841 | cache->saved_sp = 0; |
e0c62198 | 842 | cache->saved_sp_reg = -1; |
acd5c798 MK |
843 | cache->pc_in_eax = 0; |
844 | ||
845 | /* Frameless until proven otherwise. */ | |
846 | cache->locals = -1; | |
847 | ||
848 | return cache; | |
849 | } | |
c906108c | 850 | |
acd5c798 MK |
851 | /* If the instruction at PC is a jump, return the address of its |
852 | target. Otherwise, return PC. */ | |
c906108c | 853 | |
acd5c798 | 854 | static CORE_ADDR |
e17a4113 | 855 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 856 | { |
e17a4113 | 857 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 858 | gdb_byte op; |
acd5c798 MK |
859 | long delta = 0; |
860 | int data16 = 0; | |
c906108c | 861 | |
3dcabaa8 MS |
862 | if (target_read_memory (pc, &op, 1)) |
863 | return pc; | |
864 | ||
acd5c798 | 865 | if (op == 0x66) |
c906108c | 866 | { |
c906108c | 867 | data16 = 1; |
e17a4113 | 868 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
869 | } |
870 | ||
acd5c798 | 871 | switch (op) |
c906108c SS |
872 | { |
873 | case 0xe9: | |
fc338970 | 874 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
875 | if (data16) |
876 | { | |
e17a4113 | 877 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 878 | |
fc338970 MK |
879 | /* Include the size of the jmp instruction (including the |
880 | 0x66 prefix). */ | |
acd5c798 | 881 | delta += 4; |
c906108c SS |
882 | } |
883 | else | |
884 | { | |
e17a4113 | 885 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 886 | |
acd5c798 MK |
887 | /* Include the size of the jmp instruction. */ |
888 | delta += 5; | |
c906108c SS |
889 | } |
890 | break; | |
891 | case 0xeb: | |
fc338970 | 892 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 893 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 894 | |
acd5c798 | 895 | delta += data16 + 2; |
c906108c SS |
896 | break; |
897 | } | |
c906108c | 898 | |
acd5c798 MK |
899 | return pc + delta; |
900 | } | |
fc338970 | 901 | |
acd5c798 MK |
902 | /* Check whether PC points at a prologue for a function returning a |
903 | structure or union. If so, it updates CACHE and returns the | |
904 | address of the first instruction after the code sequence that | |
905 | removes the "hidden" argument from the stack or CURRENT_PC, | |
906 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 907 | |
acd5c798 MK |
908 | static CORE_ADDR |
909 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
910 | struct i386_frame_cache *cache) | |
c906108c | 911 | { |
acd5c798 MK |
912 | /* Functions that return a structure or union start with: |
913 | ||
914 | popl %eax 0x58 | |
915 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
916 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
917 | ||
918 | (the System V compiler puts out the second `xchg' instruction, | |
919 | and the assembler doesn't try to optimize it, so the 'sib' form | |
920 | gets generated). This sequence is used to get the address of the | |
921 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
922 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
923 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
924 | gdb_byte buf[4]; | |
925 | gdb_byte op; | |
c906108c | 926 | |
acd5c798 MK |
927 | if (current_pc <= pc) |
928 | return pc; | |
929 | ||
3dcabaa8 MS |
930 | if (target_read_memory (pc, &op, 1)) |
931 | return pc; | |
c906108c | 932 | |
acd5c798 MK |
933 | if (op != 0x58) /* popl %eax */ |
934 | return pc; | |
c906108c | 935 | |
3dcabaa8 MS |
936 | if (target_read_memory (pc + 1, buf, 4)) |
937 | return pc; | |
938 | ||
acd5c798 MK |
939 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
940 | return pc; | |
c906108c | 941 | |
acd5c798 | 942 | if (current_pc == pc) |
c906108c | 943 | { |
acd5c798 MK |
944 | cache->sp_offset += 4; |
945 | return current_pc; | |
c906108c SS |
946 | } |
947 | ||
acd5c798 | 948 | if (current_pc == pc + 1) |
c906108c | 949 | { |
acd5c798 MK |
950 | cache->pc_in_eax = 1; |
951 | return current_pc; | |
952 | } | |
953 | ||
954 | if (buf[1] == proto1[1]) | |
955 | return pc + 4; | |
956 | else | |
957 | return pc + 5; | |
958 | } | |
959 | ||
960 | static CORE_ADDR | |
961 | i386_skip_probe (CORE_ADDR pc) | |
962 | { | |
963 | /* A function may start with | |
fc338970 | 964 | |
acd5c798 MK |
965 | pushl constant |
966 | call _probe | |
967 | addl $4, %esp | |
fc338970 | 968 | |
acd5c798 MK |
969 | followed by |
970 | ||
971 | pushl %ebp | |
fc338970 | 972 | |
acd5c798 | 973 | etc. */ |
63c0089f MK |
974 | gdb_byte buf[8]; |
975 | gdb_byte op; | |
fc338970 | 976 | |
3dcabaa8 MS |
977 | if (target_read_memory (pc, &op, 1)) |
978 | return pc; | |
acd5c798 MK |
979 | |
980 | if (op == 0x68 || op == 0x6a) | |
981 | { | |
982 | int delta; | |
c906108c | 983 | |
acd5c798 MK |
984 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
985 | four-byte operand, depending on the opcode. */ | |
c906108c | 986 | if (op == 0x68) |
acd5c798 | 987 | delta = 5; |
c906108c | 988 | else |
acd5c798 | 989 | delta = 2; |
c906108c | 990 | |
acd5c798 MK |
991 | /* Read the following 8 bytes, which should be `call _probe' (6 |
992 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
993 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 994 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 995 | pc += delta + sizeof (buf); |
c906108c SS |
996 | } |
997 | ||
acd5c798 MK |
998 | return pc; |
999 | } | |
1000 | ||
92dd43fa MK |
1001 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1002 | stack pointer. Check whether PC points to such code, and update | |
1003 | CACHE accordingly. Return the first instruction after the code | |
1004 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1005 | recognize the code, return PC. */ | |
1006 | ||
1007 | static CORE_ADDR | |
1008 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1009 | struct i386_frame_cache *cache) | |
1010 | { | |
e0c62198 L |
1011 | /* There are 2 code sequences to re-align stack before the frame |
1012 | gets set up: | |
1013 | ||
1014 | 1. Use a caller-saved saved register: | |
1015 | ||
1016 | leal 4(%esp), %reg | |
1017 | andl $-XXX, %esp | |
1018 | pushl -4(%reg) | |
1019 | ||
1020 | 2. Use a callee-saved saved register: | |
1021 | ||
1022 | pushl %reg | |
1023 | leal 8(%esp), %reg | |
1024 | andl $-XXX, %esp | |
1025 | pushl -4(%reg) | |
1026 | ||
1027 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1028 | ||
1029 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1030 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1031 | */ | |
1032 | ||
1033 | gdb_byte buf[14]; | |
1034 | int reg; | |
1035 | int offset, offset_and; | |
1036 | static int regnums[8] = { | |
1037 | I386_EAX_REGNUM, /* %eax */ | |
1038 | I386_ECX_REGNUM, /* %ecx */ | |
1039 | I386_EDX_REGNUM, /* %edx */ | |
1040 | I386_EBX_REGNUM, /* %ebx */ | |
1041 | I386_ESP_REGNUM, /* %esp */ | |
1042 | I386_EBP_REGNUM, /* %ebp */ | |
1043 | I386_ESI_REGNUM, /* %esi */ | |
1044 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1045 | }; |
92dd43fa | 1046 | |
e0c62198 L |
1047 | if (target_read_memory (pc, buf, sizeof buf)) |
1048 | return pc; | |
1049 | ||
1050 | /* Check caller-saved saved register. The first instruction has | |
1051 | to be "leal 4(%esp), %reg". */ | |
1052 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1053 | { | |
1054 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1055 | if ((buf[1] & 0xc7) != 0x44) | |
1056 | return pc; | |
1057 | ||
1058 | /* REG has register number. */ | |
1059 | reg = (buf[1] >> 3) & 7; | |
1060 | offset = 4; | |
1061 | } | |
1062 | else | |
1063 | { | |
1064 | /* Check callee-saved saved register. The first instruction | |
1065 | has to be "pushl %reg". */ | |
1066 | if ((buf[0] & 0xf8) != 0x50) | |
1067 | return pc; | |
1068 | ||
1069 | /* Get register. */ | |
1070 | reg = buf[0] & 0x7; | |
1071 | ||
1072 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1073 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1074 | return pc; | |
1075 | ||
1076 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1077 | if ((buf[2] & 0xc7) != 0x44) | |
1078 | return pc; | |
1079 | ||
1080 | /* REG has register number. Registers in pushl and leal have to | |
1081 | be the same. */ | |
1082 | if (reg != ((buf[2] >> 3) & 7)) | |
1083 | return pc; | |
1084 | ||
1085 | offset = 5; | |
1086 | } | |
1087 | ||
1088 | /* Rigister can't be %esp nor %ebp. */ | |
1089 | if (reg == 4 || reg == 5) | |
1090 | return pc; | |
1091 | ||
1092 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1093 | if (buf[offset + 1] != 0xe4 | |
1094 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1095 | return pc; | |
1096 | ||
1097 | offset_and = offset; | |
1098 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1099 | ||
1100 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1101 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1102 | if (buf[offset] != 0xff | |
1103 | || buf[offset + 2] != 0xfc | |
1104 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1105 | return pc; | |
1106 | ||
1107 | /* R/M has register. Registers in leal and pushl have to be the | |
1108 | same. */ | |
1109 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1110 | return pc; |
1111 | ||
e0c62198 L |
1112 | if (current_pc > pc + offset_and) |
1113 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1114 | |
e0c62198 | 1115 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1116 | } |
1117 | ||
37bdc87e | 1118 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1119 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1120 | |
1121 | /* Instruction description. */ | |
1122 | struct i386_insn | |
1123 | { | |
1124 | size_t len; | |
237fc4c9 PA |
1125 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1126 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1127 | }; |
1128 | ||
a3fcb948 | 1129 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1130 | |
a3fcb948 JG |
1131 | static int |
1132 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1133 | { |
63c0089f | 1134 | gdb_byte op; |
37bdc87e | 1135 | |
3dcabaa8 | 1136 | if (target_read_memory (pc, &op, 1)) |
a3fcb948 | 1137 | return 0; |
37bdc87e | 1138 | |
a3fcb948 | 1139 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1140 | { |
a3fcb948 JG |
1141 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1142 | int insn_matched = 1; | |
1143 | size_t i; | |
37bdc87e | 1144 | |
a3fcb948 JG |
1145 | gdb_assert (pattern.len > 1); |
1146 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1147 | |
a3fcb948 JG |
1148 | if (target_read_memory (pc + 1, buf, pattern.len - 1)) |
1149 | return 0; | |
613e8135 | 1150 | |
a3fcb948 JG |
1151 | for (i = 1; i < pattern.len; i++) |
1152 | { | |
1153 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1154 | insn_matched = 0; | |
37bdc87e | 1155 | } |
a3fcb948 JG |
1156 | return insn_matched; |
1157 | } | |
1158 | return 0; | |
1159 | } | |
1160 | ||
1161 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1162 | the first instruction description that matches. Otherwise, return | |
1163 | NULL. */ | |
1164 | ||
1165 | static struct i386_insn * | |
1166 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1167 | { | |
1168 | struct i386_insn *pattern; | |
1169 | ||
1170 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1171 | { | |
1172 | if (i386_match_pattern (pc, *pattern)) | |
1173 | return pattern; | |
37bdc87e MK |
1174 | } |
1175 | ||
1176 | return NULL; | |
1177 | } | |
1178 | ||
a3fcb948 JG |
1179 | /* Return whether PC points inside a sequence of instructions that |
1180 | matches INSN_PATTERNS. */ | |
1181 | ||
1182 | static int | |
1183 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1184 | { | |
1185 | CORE_ADDR current_pc; | |
1186 | int ix, i; | |
1187 | gdb_byte op; | |
1188 | struct i386_insn *insn; | |
1189 | ||
1190 | insn = i386_match_insn (pc, insn_patterns); | |
1191 | if (insn == NULL) | |
1192 | return 0; | |
1193 | ||
8bbdd3f4 | 1194 | current_pc = pc; |
a3fcb948 JG |
1195 | ix = insn - insn_patterns; |
1196 | for (i = ix - 1; i >= 0; i--) | |
1197 | { | |
8bbdd3f4 MK |
1198 | current_pc -= insn_patterns[i].len; |
1199 | ||
a3fcb948 JG |
1200 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1201 | return 0; | |
a3fcb948 JG |
1202 | } |
1203 | ||
1204 | current_pc = pc + insn->len; | |
1205 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1206 | { | |
1207 | if (!i386_match_pattern (current_pc, *insn)) | |
1208 | return 0; | |
1209 | ||
1210 | current_pc += insn->len; | |
1211 | } | |
1212 | ||
1213 | return 1; | |
1214 | } | |
1215 | ||
37bdc87e MK |
1216 | /* Some special instructions that might be migrated by GCC into the |
1217 | part of the prologue that sets up the new stack frame. Because the | |
1218 | stack frame hasn't been setup yet, no registers have been saved | |
1219 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1220 | touched. */ | |
1221 | ||
1222 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1223 | { | |
1777feb0 | 1224 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1225 | |
1226 | ??? Should we handle 16-bit operand-sizes here? */ | |
1227 | ||
1228 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1229 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1230 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1231 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1232 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1233 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1234 | { 5, { 0xb8 }, { 0xfe } }, | |
1235 | /* `movl imm32, %edx' */ | |
1236 | { 5, { 0xba }, { 0xff } }, | |
1237 | ||
1238 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1239 | encoding for `mov m32, %eax'. | |
1240 | ||
1241 | ??? Should we handle SIB adressing here? | |
1242 | ??? Should we handle 16-bit operand-sizes here? */ | |
1243 | ||
1244 | /* `movl m32, %eax' */ | |
1245 | { 5, { 0xa1 }, { 0xff } }, | |
1246 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1247 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1248 | /* `movl m32, %edx' */ | |
1249 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1250 | ||
1251 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1252 | Because of the symmetry, there are actually two ways to encode | |
1253 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1254 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1255 | ||
1256 | /* `subl %eax, %eax' */ | |
1257 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1258 | /* `subl %ecx, %ecx' */ | |
1259 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1260 | /* `subl %edx, %edx' */ | |
1261 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1262 | /* `xorl %eax, %eax' */ | |
1263 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1264 | /* `xorl %ecx, %ecx' */ | |
1265 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1266 | /* `xorl %edx, %edx' */ | |
1267 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1268 | { 0 } | |
1269 | }; | |
1270 | ||
e11481da PM |
1271 | |
1272 | /* Check whether PC points to a no-op instruction. */ | |
1273 | static CORE_ADDR | |
1274 | i386_skip_noop (CORE_ADDR pc) | |
1275 | { | |
1276 | gdb_byte op; | |
1277 | int check = 1; | |
1278 | ||
3dcabaa8 MS |
1279 | if (target_read_memory (pc, &op, 1)) |
1280 | return pc; | |
e11481da PM |
1281 | |
1282 | while (check) | |
1283 | { | |
1284 | check = 0; | |
1285 | /* Ignore `nop' instruction. */ | |
1286 | if (op == 0x90) | |
1287 | { | |
1288 | pc += 1; | |
3dcabaa8 MS |
1289 | if (target_read_memory (pc, &op, 1)) |
1290 | return pc; | |
e11481da PM |
1291 | check = 1; |
1292 | } | |
1293 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1294 | Microsoft system dlls often start with | |
1295 | a `mov %edi,%edi' instruction. | |
1296 | The 5 bytes before the function start are | |
1297 | filled with `nop' instructions. | |
1298 | This pattern can be used for hot-patching: | |
1299 | The `mov %edi, %edi' instruction can be replaced by a | |
1300 | near jump to the location of the 5 `nop' instructions | |
1301 | which can be replaced by a 32-bit jump to anywhere | |
1302 | in the 32-bit address space. */ | |
1303 | ||
1304 | else if (op == 0x8b) | |
1305 | { | |
3dcabaa8 MS |
1306 | if (target_read_memory (pc + 1, &op, 1)) |
1307 | return pc; | |
1308 | ||
e11481da PM |
1309 | if (op == 0xff) |
1310 | { | |
1311 | pc += 2; | |
3dcabaa8 MS |
1312 | if (target_read_memory (pc, &op, 1)) |
1313 | return pc; | |
1314 | ||
e11481da PM |
1315 | check = 1; |
1316 | } | |
1317 | } | |
1318 | } | |
1319 | return pc; | |
1320 | } | |
1321 | ||
acd5c798 MK |
1322 | /* Check whether PC points at a code that sets up a new stack frame. |
1323 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1324 | instruction after the sequence that sets up the frame or LIMIT, |
1325 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1326 | |
1327 | static CORE_ADDR | |
e17a4113 UW |
1328 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1329 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1330 | struct i386_frame_cache *cache) |
1331 | { | |
e17a4113 | 1332 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1333 | struct i386_insn *insn; |
63c0089f | 1334 | gdb_byte op; |
26604a34 | 1335 | int skip = 0; |
acd5c798 | 1336 | |
37bdc87e MK |
1337 | if (limit <= pc) |
1338 | return limit; | |
acd5c798 | 1339 | |
3dcabaa8 MS |
1340 | if (target_read_memory (pc, &op, 1)) |
1341 | return pc; | |
acd5c798 | 1342 | |
c906108c | 1343 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1344 | { |
acd5c798 MK |
1345 | /* Take into account that we've executed the `pushl %ebp' that |
1346 | starts this instruction sequence. */ | |
fd13a04a | 1347 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1348 | cache->sp_offset += 4; |
37bdc87e | 1349 | pc++; |
acd5c798 MK |
1350 | |
1351 | /* If that's all, return now. */ | |
37bdc87e MK |
1352 | if (limit <= pc) |
1353 | return limit; | |
26604a34 | 1354 | |
b4632131 | 1355 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1356 | GCC into the prologue and skip them. At this point in the |
1357 | prologue, code should only touch the scratch registers %eax, | |
1358 | %ecx and %edx, so while the number of posibilities is sheer, | |
1359 | it is limited. | |
5daa5b4e | 1360 | |
26604a34 MK |
1361 | Make sure we only skip these instructions if we later see the |
1362 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1363 | while (pc + skip < limit) |
26604a34 | 1364 | { |
37bdc87e MK |
1365 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1366 | if (insn == NULL) | |
1367 | break; | |
b4632131 | 1368 | |
37bdc87e | 1369 | skip += insn->len; |
26604a34 MK |
1370 | } |
1371 | ||
37bdc87e MK |
1372 | /* If that's all, return now. */ |
1373 | if (limit <= pc + skip) | |
1374 | return limit; | |
1375 | ||
3dcabaa8 MS |
1376 | if (target_read_memory (pc + skip, &op, 1)) |
1377 | return pc + skip; | |
37bdc87e | 1378 | |
26604a34 | 1379 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1380 | switch (op) |
c906108c SS |
1381 | { |
1382 | case 0x8b: | |
e17a4113 UW |
1383 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1384 | != 0xec) | |
37bdc87e | 1385 | return pc; |
c906108c SS |
1386 | break; |
1387 | case 0x89: | |
e17a4113 UW |
1388 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1389 | != 0xe5) | |
37bdc87e | 1390 | return pc; |
c906108c SS |
1391 | break; |
1392 | default: | |
37bdc87e | 1393 | return pc; |
c906108c | 1394 | } |
acd5c798 | 1395 | |
26604a34 MK |
1396 | /* OK, we actually have a frame. We just don't know how large |
1397 | it is yet. Set its size to zero. We'll adjust it if | |
1398 | necessary. We also now commit to skipping the special | |
1399 | instructions mentioned before. */ | |
acd5c798 | 1400 | cache->locals = 0; |
37bdc87e | 1401 | pc += (skip + 2); |
acd5c798 MK |
1402 | |
1403 | /* If that's all, return now. */ | |
37bdc87e MK |
1404 | if (limit <= pc) |
1405 | return limit; | |
acd5c798 | 1406 | |
fc338970 MK |
1407 | /* Check for stack adjustment |
1408 | ||
acd5c798 | 1409 | subl $XXX, %esp |
fc338970 | 1410 | |
fd35795f | 1411 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1412 | reg, so we don't have to worry about a data16 prefix. */ |
3dcabaa8 MS |
1413 | if (target_read_memory (pc, &op, 1)) |
1414 | return pc; | |
c906108c SS |
1415 | if (op == 0x83) |
1416 | { | |
fd35795f | 1417 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1418 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1419 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1420 | return pc; |
acd5c798 | 1421 | |
37bdc87e MK |
1422 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1423 | make sense to be negative). */ | |
e17a4113 | 1424 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1425 | return pc + 3; |
c906108c SS |
1426 | } |
1427 | else if (op == 0x81) | |
1428 | { | |
fd35795f | 1429 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1430 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1431 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1432 | return pc; |
acd5c798 | 1433 | |
fd35795f | 1434 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1435 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1436 | return pc + 6; |
c906108c SS |
1437 | } |
1438 | else | |
1439 | { | |
acd5c798 | 1440 | /* Some instruction other than `subl'. */ |
37bdc87e | 1441 | return pc; |
c906108c SS |
1442 | } |
1443 | } | |
37bdc87e | 1444 | else if (op == 0xc8) /* enter */ |
c906108c | 1445 | { |
e17a4113 | 1446 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1447 | return pc + 4; |
c906108c | 1448 | } |
21d0e8a4 | 1449 | |
acd5c798 | 1450 | return pc; |
21d0e8a4 MK |
1451 | } |
1452 | ||
acd5c798 MK |
1453 | /* Check whether PC points at code that saves registers on the stack. |
1454 | If so, it updates CACHE and returns the address of the first | |
1455 | instruction after the register saves or CURRENT_PC, whichever is | |
1456 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1457 | |
1458 | static CORE_ADDR | |
acd5c798 MK |
1459 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1460 | struct i386_frame_cache *cache) | |
6bff26de | 1461 | { |
99ab4326 | 1462 | CORE_ADDR offset = 0; |
63c0089f | 1463 | gdb_byte op; |
99ab4326 | 1464 | int i; |
c0d1d883 | 1465 | |
99ab4326 MK |
1466 | if (cache->locals > 0) |
1467 | offset -= cache->locals; | |
1468 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1469 | { | |
3dcabaa8 MS |
1470 | if (target_read_memory (pc, &op, 1)) |
1471 | return pc; | |
99ab4326 MK |
1472 | if (op < 0x50 || op > 0x57) |
1473 | break; | |
0d17c81d | 1474 | |
99ab4326 MK |
1475 | offset -= 4; |
1476 | cache->saved_regs[op - 0x50] = offset; | |
1477 | cache->sp_offset += 4; | |
1478 | pc++; | |
6bff26de MK |
1479 | } |
1480 | ||
acd5c798 | 1481 | return pc; |
22797942 AC |
1482 | } |
1483 | ||
acd5c798 MK |
1484 | /* Do a full analysis of the prologue at PC and update CACHE |
1485 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1486 | address where the analysis stopped. | |
ed84f6c1 | 1487 | |
fc338970 MK |
1488 | We handle these cases: |
1489 | ||
1490 | The startup sequence can be at the start of the function, or the | |
1491 | function can start with a branch to startup code at the end. | |
1492 | ||
1493 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1494 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1495 | once used in the System V compiler). | |
1496 | ||
1497 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1498 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1499 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1500 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1501 | |
1502 | Next, the registers used by this function are pushed. With the | |
1503 | System V compiler they will always be in the order: %edi, %esi, | |
1504 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1505 | restore %eax); however, the code below is willing to see the pushes | |
1506 | in any order, and will handle up to 8 of them. | |
1507 | ||
1508 | If the setup sequence is at the end of the function, then the next | |
1509 | instruction will be a branch back to the start. */ | |
c906108c | 1510 | |
acd5c798 | 1511 | static CORE_ADDR |
e17a4113 UW |
1512 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1513 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1514 | struct i386_frame_cache *cache) |
c906108c | 1515 | { |
e11481da | 1516 | pc = i386_skip_noop (pc); |
e17a4113 | 1517 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1518 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1519 | pc = i386_skip_probe (pc); | |
92dd43fa | 1520 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1521 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1522 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1523 | } |
1524 | ||
fc338970 | 1525 | /* Return PC of first real instruction. */ |
c906108c | 1526 | |
3a1e71e3 | 1527 | static CORE_ADDR |
6093d2eb | 1528 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1529 | { |
e17a4113 UW |
1530 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1531 | ||
63c0089f | 1532 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1533 | { |
1534 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1535 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1536 | }; |
acd5c798 MK |
1537 | struct i386_frame_cache cache; |
1538 | CORE_ADDR pc; | |
63c0089f | 1539 | gdb_byte op; |
acd5c798 | 1540 | int i; |
c5aa993b | 1541 | |
acd5c798 | 1542 | cache.locals = -1; |
e17a4113 | 1543 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1544 | if (cache.locals < 0) |
1545 | return start_pc; | |
c5aa993b | 1546 | |
acd5c798 | 1547 | /* Found valid frame setup. */ |
c906108c | 1548 | |
fc338970 MK |
1549 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1550 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1551 | %ebx: |
1552 | ||
fc338970 MK |
1553 | call 0x0 |
1554 | popl %ebx | |
1555 | movl %ebx,x(%ebp) (optional) | |
1556 | addl y,%ebx | |
1557 | ||
c906108c SS |
1558 | This code is with the rest of the prologue (at the end of the |
1559 | function), so we have to skip it to get to the first real | |
1560 | instruction at the start of the function. */ | |
c5aa993b | 1561 | |
c906108c SS |
1562 | for (i = 0; i < 6; i++) |
1563 | { | |
3dcabaa8 MS |
1564 | if (target_read_memory (pc + i, &op, 1)) |
1565 | return pc; | |
1566 | ||
c5aa993b | 1567 | if (pic_pat[i] != op) |
c906108c SS |
1568 | break; |
1569 | } | |
1570 | if (i == 6) | |
1571 | { | |
acd5c798 MK |
1572 | int delta = 6; |
1573 | ||
3dcabaa8 MS |
1574 | if (target_read_memory (pc + delta, &op, 1)) |
1575 | return pc; | |
c906108c | 1576 | |
c5aa993b | 1577 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1578 | { |
e17a4113 | 1579 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1580 | |
fc338970 | 1581 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1582 | delta += 3; |
fc338970 | 1583 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1584 | delta += 6; |
fc338970 | 1585 | else /* Unexpected instruction. */ |
acd5c798 MK |
1586 | delta = 0; |
1587 | ||
3dcabaa8 MS |
1588 | if (target_read_memory (pc + delta, &op, 1)) |
1589 | return pc; | |
c906108c | 1590 | } |
acd5c798 | 1591 | |
c5aa993b | 1592 | /* addl y,%ebx */ |
acd5c798 | 1593 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1594 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1595 | == 0xc3) | |
c906108c | 1596 | { |
acd5c798 | 1597 | pc += delta + 6; |
c906108c SS |
1598 | } |
1599 | } | |
c5aa993b | 1600 | |
e63bbc88 MK |
1601 | /* If the function starts with a branch (to startup code at the end) |
1602 | the last instruction should bring us back to the first | |
1603 | instruction of the real code. */ | |
e17a4113 UW |
1604 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1605 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1606 | |
1607 | return pc; | |
c906108c SS |
1608 | } |
1609 | ||
4309257c PM |
1610 | /* Check that the code pointed to by PC corresponds to a call to |
1611 | __main, skip it if so. Return PC otherwise. */ | |
1612 | ||
1613 | CORE_ADDR | |
1614 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1615 | { | |
e17a4113 | 1616 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1617 | gdb_byte op; |
1618 | ||
3dcabaa8 MS |
1619 | if (target_read_memory (pc, &op, 1)) |
1620 | return pc; | |
4309257c PM |
1621 | if (op == 0xe8) |
1622 | { | |
1623 | gdb_byte buf[4]; | |
1624 | ||
1625 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1626 | { | |
1627 | /* Make sure address is computed correctly as a 32bit | |
1628 | integer even if CORE_ADDR is 64 bit wide. */ | |
1629 | struct minimal_symbol *s; | |
e17a4113 | 1630 | CORE_ADDR call_dest; |
4309257c | 1631 | |
e17a4113 | 1632 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1633 | call_dest = call_dest & 0xffffffffU; |
1634 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1635 | if (s != NULL | |
1636 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1637 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1638 | pc += 5; | |
1639 | } | |
1640 | } | |
1641 | ||
1642 | return pc; | |
1643 | } | |
1644 | ||
acd5c798 | 1645 | /* This function is 64-bit safe. */ |
93924b6b | 1646 | |
acd5c798 MK |
1647 | static CORE_ADDR |
1648 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1649 | { |
63c0089f | 1650 | gdb_byte buf[8]; |
acd5c798 | 1651 | |
875f8d0e | 1652 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1653 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1654 | } |
acd5c798 | 1655 | \f |
93924b6b | 1656 | |
acd5c798 | 1657 | /* Normal frames. */ |
c5aa993b | 1658 | |
8fbca658 PA |
1659 | static void |
1660 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1661 | struct i386_frame_cache *cache) | |
a7769679 | 1662 | { |
e17a4113 UW |
1663 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1664 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1665 | gdb_byte buf[4]; |
acd5c798 MK |
1666 | int i; |
1667 | ||
8fbca658 | 1668 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1669 | |
1670 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1671 | which holds the base address for the current stack frame. | |
1672 | However, for functions that don't need it, the frame pointer is | |
1673 | optional. For these "frameless" functions the frame pointer is | |
1674 | actually the frame pointer of the calling frame. Signal | |
1675 | trampolines are just a special case of a "frameless" function. | |
1676 | They (usually) share their frame pointer with the frame that was | |
1677 | in progress when the signal occurred. */ | |
1678 | ||
10458914 | 1679 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1680 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1681 | if (cache->base == 0) |
8fbca658 | 1682 | return; |
acd5c798 MK |
1683 | |
1684 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1685 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1686 | |
acd5c798 | 1687 | if (cache->pc != 0) |
e17a4113 UW |
1688 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1689 | cache); | |
acd5c798 MK |
1690 | |
1691 | if (cache->locals < 0) | |
1692 | { | |
1693 | /* We didn't find a valid frame, which means that CACHE->base | |
1694 | currently holds the frame pointer for our calling frame. If | |
1695 | we're at the start of a function, or somewhere half-way its | |
1696 | prologue, the function's frame probably hasn't been fully | |
1697 | setup yet. Try to reconstruct the base address for the stack | |
1698 | frame by looking at the stack pointer. For truly "frameless" | |
1699 | functions this might work too. */ | |
1700 | ||
e0c62198 | 1701 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1702 | { |
8fbca658 PA |
1703 | /* Saved stack pointer has been saved. */ |
1704 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
1705 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1706 | ||
92dd43fa MK |
1707 | /* We're halfway aligning the stack. */ |
1708 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1709 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1710 | ||
1711 | /* This will be added back below. */ | |
1712 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1713 | } | |
7618e12b DJ |
1714 | else if (cache->pc != 0 |
1715 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1716 | { |
7618e12b DJ |
1717 | /* We're in a known function, but did not find a frame |
1718 | setup. Assume that the function does not use %ebp. | |
1719 | Alternatively, we may have jumped to an invalid | |
1720 | address; in that case there is definitely no new | |
1721 | frame in %ebp. */ | |
10458914 | 1722 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1723 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1724 | + cache->sp_offset; | |
92dd43fa | 1725 | } |
7618e12b DJ |
1726 | else |
1727 | /* We're in an unknown function. We could not find the start | |
1728 | of the function to analyze the prologue; our best option is | |
1729 | to assume a typical frame layout with the caller's %ebp | |
1730 | saved. */ | |
1731 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1732 | } |
1733 | ||
8fbca658 PA |
1734 | if (cache->saved_sp_reg != -1) |
1735 | { | |
1736 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
1737 | register may be unavailable). */ | |
1738 | if (cache->saved_sp == 0 | |
1739 | && frame_register_read (this_frame, cache->saved_sp_reg, buf)) | |
1740 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1741 | } | |
acd5c798 MK |
1742 | /* Now that we have the base address for the stack frame we can |
1743 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 1744 | else if (cache->saved_sp == 0) |
92dd43fa | 1745 | cache->saved_sp = cache->base + 8; |
a7769679 | 1746 | |
acd5c798 MK |
1747 | /* Adjust all the saved registers such that they contain addresses |
1748 | instead of offsets. */ | |
1749 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1750 | if (cache->saved_regs[i] != -1) |
1751 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 1752 | |
8fbca658 PA |
1753 | cache->base_p = 1; |
1754 | } | |
1755 | ||
1756 | static struct i386_frame_cache * | |
1757 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1758 | { | |
1759 | volatile struct gdb_exception ex; | |
1760 | struct i386_frame_cache *cache; | |
1761 | ||
1762 | if (*this_cache) | |
1763 | return *this_cache; | |
1764 | ||
1765 | cache = i386_alloc_frame_cache (); | |
1766 | *this_cache = cache; | |
1767 | ||
1768 | TRY_CATCH (ex, RETURN_MASK_ERROR) | |
1769 | { | |
1770 | i386_frame_cache_1 (this_frame, cache); | |
1771 | } | |
1772 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1773 | throw_exception (ex); | |
1774 | ||
acd5c798 | 1775 | return cache; |
a7769679 MK |
1776 | } |
1777 | ||
3a1e71e3 | 1778 | static void |
10458914 | 1779 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1780 | struct frame_id *this_id) |
c906108c | 1781 | { |
10458914 | 1782 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1783 | |
1784 | /* This marks the outermost frame. */ | |
1785 | if (cache->base == 0) | |
1786 | return; | |
1787 | ||
3e210248 | 1788 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1789 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1790 | } | |
1791 | ||
8fbca658 PA |
1792 | static enum unwind_stop_reason |
1793 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1794 | void **this_cache) | |
1795 | { | |
1796 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
1797 | ||
1798 | if (!cache->base_p) | |
1799 | return UNWIND_UNAVAILABLE; | |
1800 | ||
1801 | /* This marks the outermost frame. */ | |
1802 | if (cache->base == 0) | |
1803 | return UNWIND_OUTERMOST; | |
1804 | ||
1805 | return UNWIND_NO_REASON; | |
1806 | } | |
1807 | ||
10458914 DJ |
1808 | static struct value * |
1809 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1810 | int regnum) | |
acd5c798 | 1811 | { |
10458914 | 1812 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1813 | |
1814 | gdb_assert (regnum >= 0); | |
1815 | ||
1816 | /* The System V ABI says that: | |
1817 | ||
1818 | "The flags register contains the system flags, such as the | |
1819 | direction flag and the carry flag. The direction flag must be | |
1820 | set to the forward (that is, zero) direction before entry and | |
1821 | upon exit from a function. Other user flags have no specified | |
1822 | role in the standard calling sequence and are not preserved." | |
1823 | ||
1824 | To guarantee the "upon exit" part of that statement we fake a | |
1825 | saved flags register that has its direction flag cleared. | |
1826 | ||
1827 | Note that GCC doesn't seem to rely on the fact that the direction | |
1828 | flag is cleared after a function return; it always explicitly | |
1829 | clears the flag before operations where it matters. | |
1830 | ||
1831 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1832 | right thing to do. The way we fake the flags register here makes | |
1833 | it impossible to change it. */ | |
1834 | ||
1835 | if (regnum == I386_EFLAGS_REGNUM) | |
1836 | { | |
10458914 | 1837 | ULONGEST val; |
c5aa993b | 1838 | |
10458914 DJ |
1839 | val = get_frame_register_unsigned (this_frame, regnum); |
1840 | val &= ~(1 << 10); | |
1841 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1842 | } |
1211c4e4 | 1843 | |
acd5c798 | 1844 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1845 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 1846 | |
fcf250e2 UW |
1847 | if (regnum == I386_ESP_REGNUM |
1848 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
1849 | { |
1850 | /* If the SP has been saved, but we don't know where, then this | |
1851 | means that SAVED_SP_REG register was found unavailable back | |
1852 | when we built the cache. */ | |
fcf250e2 | 1853 | if (cache->saved_sp == 0) |
8fbca658 PA |
1854 | return frame_unwind_got_register (this_frame, regnum, |
1855 | cache->saved_sp_reg); | |
1856 | else | |
1857 | return frame_unwind_got_constant (this_frame, regnum, | |
1858 | cache->saved_sp); | |
1859 | } | |
acd5c798 | 1860 | |
fd13a04a | 1861 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1862 | return frame_unwind_got_memory (this_frame, regnum, |
1863 | cache->saved_regs[regnum]); | |
fd13a04a | 1864 | |
10458914 | 1865 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1866 | } |
1867 | ||
1868 | static const struct frame_unwind i386_frame_unwind = | |
1869 | { | |
1870 | NORMAL_FRAME, | |
8fbca658 | 1871 | i386_frame_unwind_stop_reason, |
acd5c798 | 1872 | i386_frame_this_id, |
10458914 DJ |
1873 | i386_frame_prev_register, |
1874 | NULL, | |
1875 | default_frame_sniffer | |
acd5c798 | 1876 | }; |
06da04c6 MS |
1877 | |
1878 | /* Normal frames, but in a function epilogue. */ | |
1879 | ||
1880 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1881 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1882 | the function's stack frame. */ | |
1883 | ||
1884 | static int | |
1885 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1886 | { | |
1887 | gdb_byte insn; | |
1888 | ||
1889 | if (target_read_memory (pc, &insn, 1)) | |
1890 | return 0; /* Can't read memory at pc. */ | |
1891 | ||
1892 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1893 | return 0; | |
1894 | ||
1895 | return 1; | |
1896 | } | |
1897 | ||
1898 | static int | |
1899 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1900 | struct frame_info *this_frame, | |
1901 | void **this_prologue_cache) | |
1902 | { | |
1903 | if (frame_relative_level (this_frame) == 0) | |
1904 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1905 | get_frame_pc (this_frame)); | |
1906 | else | |
1907 | return 0; | |
1908 | } | |
1909 | ||
1910 | static struct i386_frame_cache * | |
1911 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1912 | { | |
8fbca658 | 1913 | volatile struct gdb_exception ex; |
06da04c6 | 1914 | struct i386_frame_cache *cache; |
0d6c2135 | 1915 | CORE_ADDR sp; |
06da04c6 MS |
1916 | |
1917 | if (*this_cache) | |
1918 | return *this_cache; | |
1919 | ||
1920 | cache = i386_alloc_frame_cache (); | |
1921 | *this_cache = cache; | |
1922 | ||
8fbca658 PA |
1923 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
1924 | { | |
0d6c2135 | 1925 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 1926 | |
0d6c2135 MK |
1927 | /* At this point the stack looks as if we just entered the |
1928 | function, with the return address at the top of the | |
1929 | stack. */ | |
1930 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
1931 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 1932 | cache->saved_sp = cache->base + 8; |
8fbca658 | 1933 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 1934 | |
8fbca658 PA |
1935 | cache->base_p = 1; |
1936 | } | |
1937 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1938 | throw_exception (ex); | |
06da04c6 MS |
1939 | |
1940 | return cache; | |
1941 | } | |
1942 | ||
8fbca658 PA |
1943 | static enum unwind_stop_reason |
1944 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1945 | void **this_cache) | |
1946 | { | |
0d6c2135 MK |
1947 | struct i386_frame_cache *cache = |
1948 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
1949 | |
1950 | if (!cache->base_p) | |
1951 | return UNWIND_UNAVAILABLE; | |
1952 | ||
1953 | return UNWIND_NO_REASON; | |
1954 | } | |
1955 | ||
06da04c6 MS |
1956 | static void |
1957 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1958 | void **this_cache, | |
1959 | struct frame_id *this_id) | |
1960 | { | |
0d6c2135 MK |
1961 | struct i386_frame_cache *cache = |
1962 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 1963 | |
8fbca658 PA |
1964 | if (!cache->base_p) |
1965 | return; | |
1966 | ||
06da04c6 MS |
1967 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1968 | } | |
1969 | ||
0d6c2135 MK |
1970 | static struct value * |
1971 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
1972 | void **this_cache, int regnum) | |
1973 | { | |
1974 | /* Make sure we've initialized the cache. */ | |
1975 | i386_epilogue_frame_cache (this_frame, this_cache); | |
1976 | ||
1977 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
1978 | } | |
1979 | ||
06da04c6 MS |
1980 | static const struct frame_unwind i386_epilogue_frame_unwind = |
1981 | { | |
1982 | NORMAL_FRAME, | |
8fbca658 | 1983 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 1984 | i386_epilogue_frame_this_id, |
0d6c2135 | 1985 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
1986 | NULL, |
1987 | i386_epilogue_frame_sniffer | |
1988 | }; | |
acd5c798 MK |
1989 | \f |
1990 | ||
a3fcb948 JG |
1991 | /* Stack-based trampolines. */ |
1992 | ||
1993 | /* These trampolines are used on cross x86 targets, when taking the | |
1994 | address of a nested function. When executing these trampolines, | |
1995 | no stack frame is set up, so we are in a similar situation as in | |
1996 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
1997 | ||
1998 | /* Static chain passed in register. */ | |
1999 | ||
2000 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2001 | { | |
2002 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2003 | { 5, { 0xb8 }, { 0xfe } }, | |
2004 | ||
2005 | /* `jmp imm32' */ | |
2006 | { 5, { 0xe9 }, { 0xff } }, | |
2007 | ||
2008 | {0} | |
2009 | }; | |
2010 | ||
2011 | /* Static chain passed on stack (when regparm=3). */ | |
2012 | ||
2013 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2014 | { | |
2015 | /* `push imm32' */ | |
2016 | { 5, { 0x68 }, { 0xff } }, | |
2017 | ||
2018 | /* `jmp imm32' */ | |
2019 | { 5, { 0xe9 }, { 0xff } }, | |
2020 | ||
2021 | {0} | |
2022 | }; | |
2023 | ||
2024 | /* Return whether PC points inside a stack trampoline. */ | |
2025 | ||
2026 | static int | |
2027 | i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2028 | { | |
2029 | gdb_byte insn; | |
2030 | char *name; | |
2031 | ||
2032 | /* A stack trampoline is detected if no name is associated | |
2033 | to the current pc and if it points inside a trampoline | |
2034 | sequence. */ | |
2035 | ||
2036 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2037 | if (name) | |
2038 | return 0; | |
2039 | ||
2040 | if (target_read_memory (pc, &insn, 1)) | |
2041 | return 0; | |
2042 | ||
2043 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2044 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2045 | return 0; | |
2046 | ||
2047 | return 1; | |
2048 | } | |
2049 | ||
2050 | static int | |
2051 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2052 | struct frame_info *this_frame, |
2053 | void **this_cache) | |
a3fcb948 JG |
2054 | { |
2055 | if (frame_relative_level (this_frame) == 0) | |
2056 | return i386_in_stack_tramp_p (get_frame_arch (this_frame), | |
2057 | get_frame_pc (this_frame)); | |
2058 | else | |
2059 | return 0; | |
2060 | } | |
2061 | ||
2062 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2063 | { | |
2064 | NORMAL_FRAME, | |
2065 | i386_epilogue_frame_unwind_stop_reason, | |
2066 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2067 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2068 | NULL, |
2069 | i386_stack_tramp_frame_sniffer | |
2070 | }; | |
2071 | \f | |
2072 | ||
acd5c798 MK |
2073 | /* Signal trampolines. */ |
2074 | ||
2075 | static struct i386_frame_cache * | |
10458914 | 2076 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2077 | { |
e17a4113 UW |
2078 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2079 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2080 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2081 | volatile struct gdb_exception ex; |
acd5c798 | 2082 | struct i386_frame_cache *cache; |
acd5c798 | 2083 | CORE_ADDR addr; |
63c0089f | 2084 | gdb_byte buf[4]; |
acd5c798 MK |
2085 | |
2086 | if (*this_cache) | |
2087 | return *this_cache; | |
2088 | ||
fd13a04a | 2089 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2090 | |
8fbca658 | 2091 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
a3386186 | 2092 | { |
8fbca658 PA |
2093 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2094 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2095 | |
8fbca658 PA |
2096 | addr = tdep->sigcontext_addr (this_frame); |
2097 | if (tdep->sc_reg_offset) | |
2098 | { | |
2099 | int i; | |
a3386186 | 2100 | |
8fbca658 PA |
2101 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2102 | ||
2103 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2104 | if (tdep->sc_reg_offset[i] != -1) | |
2105 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2106 | } | |
2107 | else | |
2108 | { | |
2109 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2110 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2111 | } | |
2112 | ||
2113 | cache->base_p = 1; | |
a3386186 | 2114 | } |
8fbca658 PA |
2115 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
2116 | throw_exception (ex); | |
acd5c798 MK |
2117 | |
2118 | *this_cache = cache; | |
2119 | return cache; | |
2120 | } | |
2121 | ||
8fbca658 PA |
2122 | static enum unwind_stop_reason |
2123 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2124 | void **this_cache) | |
2125 | { | |
2126 | struct i386_frame_cache *cache = | |
2127 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2128 | ||
2129 | if (!cache->base_p) | |
2130 | return UNWIND_UNAVAILABLE; | |
2131 | ||
2132 | return UNWIND_NO_REASON; | |
2133 | } | |
2134 | ||
acd5c798 | 2135 | static void |
10458914 | 2136 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2137 | struct frame_id *this_id) |
2138 | { | |
2139 | struct i386_frame_cache *cache = | |
10458914 | 2140 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2141 | |
8fbca658 PA |
2142 | if (!cache->base_p) |
2143 | return; | |
2144 | ||
3e210248 | 2145 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2146 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
2147 | } |
2148 | ||
10458914 DJ |
2149 | static struct value * |
2150 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2151 | void **this_cache, int regnum) | |
acd5c798 MK |
2152 | { |
2153 | /* Make sure we've initialized the cache. */ | |
10458914 | 2154 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2155 | |
10458914 | 2156 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2157 | } |
c0d1d883 | 2158 | |
10458914 DJ |
2159 | static int |
2160 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2161 | struct frame_info *this_frame, | |
2162 | void **this_prologue_cache) | |
acd5c798 | 2163 | { |
10458914 | 2164 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2165 | |
911bc6ee MK |
2166 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2167 | handler. */ | |
2168 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2169 | return 0; |
1c3545ae | 2170 | |
911bc6ee MK |
2171 | if (tdep->sigtramp_p != NULL) |
2172 | { | |
10458914 DJ |
2173 | if (tdep->sigtramp_p (this_frame)) |
2174 | return 1; | |
911bc6ee MK |
2175 | } |
2176 | ||
2177 | if (tdep->sigtramp_start != 0) | |
2178 | { | |
10458914 | 2179 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2180 | |
2181 | gdb_assert (tdep->sigtramp_end != 0); | |
2182 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2183 | return 1; |
911bc6ee | 2184 | } |
acd5c798 | 2185 | |
10458914 | 2186 | return 0; |
acd5c798 | 2187 | } |
10458914 DJ |
2188 | |
2189 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2190 | { | |
2191 | SIGTRAMP_FRAME, | |
8fbca658 | 2192 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2193 | i386_sigtramp_frame_this_id, |
2194 | i386_sigtramp_frame_prev_register, | |
2195 | NULL, | |
2196 | i386_sigtramp_frame_sniffer | |
2197 | }; | |
acd5c798 MK |
2198 | \f |
2199 | ||
2200 | static CORE_ADDR | |
10458914 | 2201 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2202 | { |
10458914 | 2203 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2204 | |
2205 | return cache->base; | |
2206 | } | |
2207 | ||
2208 | static const struct frame_base i386_frame_base = | |
2209 | { | |
2210 | &i386_frame_unwind, | |
2211 | i386_frame_base_address, | |
2212 | i386_frame_base_address, | |
2213 | i386_frame_base_address | |
2214 | }; | |
2215 | ||
acd5c798 | 2216 | static struct frame_id |
10458914 | 2217 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2218 | { |
acd5c798 MK |
2219 | CORE_ADDR fp; |
2220 | ||
10458914 | 2221 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2222 | |
3e210248 | 2223 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2224 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2225 | } |
fc338970 | 2226 | \f |
c906108c | 2227 | |
fc338970 MK |
2228 | /* Figure out where the longjmp will land. Slurp the args out of the |
2229 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2230 | structure from which we extract the address that we will land at. |
28bcfd30 | 2231 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2232 | success. */ |
c906108c | 2233 | |
8201327c | 2234 | static int |
60ade65d | 2235 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2236 | { |
436675d3 | 2237 | gdb_byte buf[4]; |
c906108c | 2238 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2239 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2240 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2241 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2242 | |
8201327c MK |
2243 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2244 | longjmp will land. */ | |
2245 | if (jb_pc_offset == -1) | |
c906108c SS |
2246 | return 0; |
2247 | ||
436675d3 | 2248 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2249 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2250 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2251 | return 0; |
2252 | ||
e17a4113 | 2253 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2254 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2255 | return 0; |
c906108c | 2256 | |
e17a4113 | 2257 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2258 | return 1; |
2259 | } | |
fc338970 | 2260 | \f |
c906108c | 2261 | |
7ccc1c74 JM |
2262 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2263 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2264 | unions containing such types must be 16-byte-aligned; other | |
2265 | arguments are 4-byte-aligned. */ | |
2266 | ||
2267 | static int | |
2268 | i386_16_byte_align_p (struct type *type) | |
2269 | { | |
2270 | type = check_typedef (type); | |
2271 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2272 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2273 | && TYPE_LENGTH (type) == 16) | |
2274 | return 1; | |
2275 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2276 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2277 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2278 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2279 | { | |
2280 | int i; | |
2281 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2282 | { | |
2283 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2284 | return 1; | |
2285 | } | |
2286 | } | |
2287 | return 0; | |
2288 | } | |
2289 | ||
3a1e71e3 | 2290 | static CORE_ADDR |
7d9b040b | 2291 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2292 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2293 | struct value **args, CORE_ADDR sp, int struct_return, | |
2294 | CORE_ADDR struct_addr) | |
22f8ba57 | 2295 | { |
e17a4113 | 2296 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2297 | gdb_byte buf[4]; |
acd5c798 | 2298 | int i; |
7ccc1c74 JM |
2299 | int write_pass; |
2300 | int args_space = 0; | |
acd5c798 | 2301 | |
7ccc1c74 JM |
2302 | /* Determine the total space required for arguments and struct |
2303 | return address in a first pass (allowing for 16-byte-aligned | |
2304 | arguments), then push arguments in a second pass. */ | |
2305 | ||
2306 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2307 | { |
7ccc1c74 JM |
2308 | int args_space_used = 0; |
2309 | int have_16_byte_aligned_arg = 0; | |
2310 | ||
2311 | if (struct_return) | |
2312 | { | |
2313 | if (write_pass) | |
2314 | { | |
2315 | /* Push value address. */ | |
e17a4113 | 2316 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2317 | write_memory (sp, buf, 4); |
2318 | args_space_used += 4; | |
2319 | } | |
2320 | else | |
2321 | args_space += 4; | |
2322 | } | |
2323 | ||
2324 | for (i = 0; i < nargs; i++) | |
2325 | { | |
2326 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2327 | |
7ccc1c74 JM |
2328 | if (write_pass) |
2329 | { | |
2330 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2331 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2332 | |
7ccc1c74 JM |
2333 | write_memory (sp + args_space_used, |
2334 | value_contents_all (args[i]), len); | |
2335 | /* The System V ABI says that: | |
acd5c798 | 2336 | |
7ccc1c74 JM |
2337 | "An argument's size is increased, if necessary, to make it a |
2338 | multiple of [32-bit] words. This may require tail padding, | |
2339 | depending on the size of the argument." | |
22f8ba57 | 2340 | |
7ccc1c74 JM |
2341 | This makes sure the stack stays word-aligned. */ |
2342 | args_space_used += align_up (len, 4); | |
2343 | } | |
2344 | else | |
2345 | { | |
2346 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2347 | { | |
2348 | args_space = align_up (args_space, 16); | |
2349 | have_16_byte_aligned_arg = 1; | |
2350 | } | |
2351 | args_space += align_up (len, 4); | |
2352 | } | |
2353 | } | |
2354 | ||
2355 | if (!write_pass) | |
2356 | { | |
2357 | if (have_16_byte_aligned_arg) | |
2358 | args_space = align_up (args_space, 16); | |
2359 | sp -= args_space; | |
2360 | } | |
22f8ba57 MK |
2361 | } |
2362 | ||
acd5c798 MK |
2363 | /* Store return address. */ |
2364 | sp -= 4; | |
e17a4113 | 2365 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2366 | write_memory (sp, buf, 4); |
2367 | ||
2368 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2369 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2370 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2371 | ||
2372 | /* ...and fake a frame pointer. */ | |
2373 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2374 | ||
3e210248 AC |
2375 | /* MarkK wrote: This "+ 8" is all over the place: |
2376 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2377 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2378 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2379 | definition of the stack address of a frame. Otherwise frame id |
2380 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2381 | stack address *before* the function call as a frame's CFA. On |
2382 | the i386, when %ebp is used as a frame pointer, the offset | |
2383 | between the contents %ebp and the CFA as defined by GCC. */ | |
2384 | return sp + 8; | |
22f8ba57 MK |
2385 | } |
2386 | ||
1a309862 MK |
2387 | /* These registers are used for returning integers (and on some |
2388 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2389 | size and alignment match an integer type). */ |
acd5c798 MK |
2390 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2391 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2392 | |
c5e656c1 MK |
2393 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2394 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2395 | |
3a1e71e3 | 2396 | static void |
c5e656c1 | 2397 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2398 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2399 | { |
c5e656c1 | 2400 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2401 | int len = TYPE_LENGTH (type); |
63c0089f | 2402 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2403 | |
1e8d0a7b | 2404 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2405 | { |
5716833c | 2406 | if (tdep->st0_regnum < 0) |
1a309862 | 2407 | { |
8a3fe4f8 | 2408 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2409 | memset (valbuf, 0, len); |
ef9dff19 | 2410 | return; |
1a309862 MK |
2411 | } |
2412 | ||
c6ba6f0d MK |
2413 | /* Floating-point return values can be found in %st(0). Convert |
2414 | its contents to the desired type. This is probably not | |
2415 | exactly how it would happen on the target itself, but it is | |
2416 | the best we can do. */ | |
acd5c798 | 2417 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2418 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2419 | } |
2420 | else | |
c5aa993b | 2421 | { |
875f8d0e UW |
2422 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2423 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2424 | |
2425 | if (len <= low_size) | |
00f8375e | 2426 | { |
0818c12a | 2427 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2428 | memcpy (valbuf, buf, len); |
2429 | } | |
d4f3574e SS |
2430 | else if (len <= (low_size + high_size)) |
2431 | { | |
0818c12a | 2432 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2433 | memcpy (valbuf, buf, low_size); |
0818c12a | 2434 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2435 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2436 | } |
2437 | else | |
8e65ff28 | 2438 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2439 | _("Cannot extract return value of %d bytes long."), |
2440 | len); | |
c906108c SS |
2441 | } |
2442 | } | |
2443 | ||
c5e656c1 MK |
2444 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2445 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2446 | |
3a1e71e3 | 2447 | static void |
c5e656c1 | 2448 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2449 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2450 | { |
c5e656c1 | 2451 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2452 | int len = TYPE_LENGTH (type); |
2453 | ||
1e8d0a7b | 2454 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2455 | { |
3d7f4f49 | 2456 | ULONGEST fstat; |
63c0089f | 2457 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2458 | |
5716833c | 2459 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2460 | { |
8a3fe4f8 | 2461 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2462 | return; |
2463 | } | |
2464 | ||
635b0cc1 MK |
2465 | /* Returning floating-point values is a bit tricky. Apart from |
2466 | storing the return value in %st(0), we have to simulate the | |
2467 | state of the FPU at function return point. */ | |
2468 | ||
c6ba6f0d MK |
2469 | /* Convert the value found in VALBUF to the extended |
2470 | floating-point format used by the FPU. This is probably | |
2471 | not exactly how it would happen on the target itself, but | |
2472 | it is the best we can do. */ | |
27067745 | 2473 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2474 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2475 | |
635b0cc1 MK |
2476 | /* Set the top of the floating-point register stack to 7. The |
2477 | actual value doesn't really matter, but 7 is what a normal | |
2478 | function return would end up with if the program started out | |
2479 | with a freshly initialized FPU. */ | |
20a6ec49 | 2480 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2481 | fstat |= (7 << 11); |
20a6ec49 | 2482 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2483 | |
635b0cc1 MK |
2484 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2485 | the floating-point register stack to 7, the appropriate value | |
2486 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2487 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2488 | } |
2489 | else | |
2490 | { | |
875f8d0e UW |
2491 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2492 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2493 | |
2494 | if (len <= low_size) | |
3d7f4f49 | 2495 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2496 | else if (len <= (low_size + high_size)) |
2497 | { | |
3d7f4f49 MK |
2498 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2499 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2500 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2501 | } |
2502 | else | |
8e65ff28 | 2503 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2504 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2505 | } |
2506 | } | |
fc338970 | 2507 | \f |
ef9dff19 | 2508 | |
8201327c MK |
2509 | /* This is the variable that is set with "set struct-convention", and |
2510 | its legitimate values. */ | |
2511 | static const char default_struct_convention[] = "default"; | |
2512 | static const char pcc_struct_convention[] = "pcc"; | |
2513 | static const char reg_struct_convention[] = "reg"; | |
2514 | static const char *valid_conventions[] = | |
2515 | { | |
2516 | default_struct_convention, | |
2517 | pcc_struct_convention, | |
2518 | reg_struct_convention, | |
2519 | NULL | |
2520 | }; | |
2521 | static const char *struct_convention = default_struct_convention; | |
2522 | ||
0e4377e1 JB |
2523 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2524 | a union type, or an array type, should be returned in registers | |
2525 | for architecture GDBARCH. */ | |
c5e656c1 | 2526 | |
8201327c | 2527 | static int |
c5e656c1 | 2528 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2529 | { |
c5e656c1 MK |
2530 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2531 | enum type_code code = TYPE_CODE (type); | |
2532 | int len = TYPE_LENGTH (type); | |
8201327c | 2533 | |
0e4377e1 JB |
2534 | gdb_assert (code == TYPE_CODE_STRUCT |
2535 | || code == TYPE_CODE_UNION | |
2536 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2537 | |
2538 | if (struct_convention == pcc_struct_convention | |
2539 | || (struct_convention == default_struct_convention | |
2540 | && tdep->struct_return == pcc_struct_return)) | |
2541 | return 0; | |
2542 | ||
9edde48e MK |
2543 | /* Structures consisting of a single `float', `double' or 'long |
2544 | double' member are returned in %st(0). */ | |
2545 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2546 | { | |
2547 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2548 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2549 | return (len == 4 || len == 8 || len == 12); | |
2550 | } | |
2551 | ||
c5e656c1 MK |
2552 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2553 | } | |
2554 | ||
2555 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2556 | should be returned. If it is supposed to be returned in registers, | |
2557 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2558 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2559 | from WRITEBUF into REGCACHE. */ | |
2560 | ||
2561 | static enum return_value_convention | |
c055b101 CV |
2562 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2563 | struct type *type, struct regcache *regcache, | |
2564 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2565 | { |
2566 | enum type_code code = TYPE_CODE (type); | |
2567 | ||
5daa78cc TJB |
2568 | if (((code == TYPE_CODE_STRUCT |
2569 | || code == TYPE_CODE_UNION | |
2570 | || code == TYPE_CODE_ARRAY) | |
2571 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2572 | /* 128-bit decimal float uses the struct return convention. */ | |
2573 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2574 | { |
2575 | /* The System V ABI says that: | |
2576 | ||
2577 | "A function that returns a structure or union also sets %eax | |
2578 | to the value of the original address of the caller's area | |
2579 | before it returns. Thus when the caller receives control | |
2580 | again, the address of the returned object resides in register | |
2581 | %eax and can be used to access the object." | |
2582 | ||
2583 | So the ABI guarantees that we can always find the return | |
2584 | value just after the function has returned. */ | |
2585 | ||
0e4377e1 JB |
2586 | /* Note that the ABI doesn't mention functions returning arrays, |
2587 | which is something possible in certain languages such as Ada. | |
2588 | In this case, the value is returned as if it was wrapped in | |
2589 | a record, so the convention applied to records also applies | |
2590 | to arrays. */ | |
2591 | ||
31db7b6c MK |
2592 | if (readbuf) |
2593 | { | |
2594 | ULONGEST addr; | |
2595 | ||
2596 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2597 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2598 | } | |
2599 | ||
2600 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2601 | } | |
c5e656c1 MK |
2602 | |
2603 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2604 | `float', `double' or 'long double' member. These structures are |
2605 | returned in %st(0). For these structures, we call ourselves | |
2606 | recursively, changing TYPE into the type of the first member of | |
2607 | the structure. Since that should work for all structures that | |
2608 | have only one member, we don't bother to check the member's type | |
2609 | here. */ | |
c5e656c1 MK |
2610 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2611 | { | |
2612 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2613 | return i386_return_value (gdbarch, func_type, type, regcache, |
2614 | readbuf, writebuf); | |
c5e656c1 MK |
2615 | } |
2616 | ||
2617 | if (readbuf) | |
2618 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2619 | if (writebuf) | |
2620 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2621 | |
c5e656c1 | 2622 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2623 | } |
2624 | \f | |
2625 | ||
27067745 UW |
2626 | struct type * |
2627 | i387_ext_type (struct gdbarch *gdbarch) | |
2628 | { | |
2629 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2630 | ||
2631 | if (!tdep->i387_ext_type) | |
90884b2b L |
2632 | { |
2633 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2634 | gdb_assert (tdep->i387_ext_type != NULL); | |
2635 | } | |
27067745 UW |
2636 | |
2637 | return tdep->i387_ext_type; | |
2638 | } | |
2639 | ||
c131fcee L |
2640 | /* Construct vector type for pseudo YMM registers. We can't use |
2641 | tdesc_find_type since YMM isn't described in target description. */ | |
2642 | ||
2643 | static struct type * | |
2644 | i386_ymm_type (struct gdbarch *gdbarch) | |
2645 | { | |
2646 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2647 | ||
2648 | if (!tdep->i386_ymm_type) | |
2649 | { | |
2650 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2651 | ||
2652 | /* The type we're building is this: */ | |
2653 | #if 0 | |
2654 | union __gdb_builtin_type_vec256i | |
2655 | { | |
2656 | int128_t uint128[2]; | |
2657 | int64_t v2_int64[4]; | |
2658 | int32_t v4_int32[8]; | |
2659 | int16_t v8_int16[16]; | |
2660 | int8_t v16_int8[32]; | |
2661 | double v2_double[4]; | |
2662 | float v4_float[8]; | |
2663 | }; | |
2664 | #endif | |
2665 | ||
2666 | struct type *t; | |
2667 | ||
2668 | t = arch_composite_type (gdbarch, | |
2669 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2670 | append_composite_type_field (t, "v8_float", | |
2671 | init_vector_type (bt->builtin_float, 8)); | |
2672 | append_composite_type_field (t, "v4_double", | |
2673 | init_vector_type (bt->builtin_double, 4)); | |
2674 | append_composite_type_field (t, "v32_int8", | |
2675 | init_vector_type (bt->builtin_int8, 32)); | |
2676 | append_composite_type_field (t, "v16_int16", | |
2677 | init_vector_type (bt->builtin_int16, 16)); | |
2678 | append_composite_type_field (t, "v8_int32", | |
2679 | init_vector_type (bt->builtin_int32, 8)); | |
2680 | append_composite_type_field (t, "v4_int64", | |
2681 | init_vector_type (bt->builtin_int64, 4)); | |
2682 | append_composite_type_field (t, "v2_int128", | |
2683 | init_vector_type (bt->builtin_int128, 2)); | |
2684 | ||
2685 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 2686 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
2687 | tdep->i386_ymm_type = t; |
2688 | } | |
2689 | ||
2690 | return tdep->i386_ymm_type; | |
2691 | } | |
2692 | ||
794ac428 | 2693 | /* Construct vector type for MMX registers. */ |
90884b2b | 2694 | static struct type * |
794ac428 UW |
2695 | i386_mmx_type (struct gdbarch *gdbarch) |
2696 | { | |
2697 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2698 | ||
2699 | if (!tdep->i386_mmx_type) | |
2700 | { | |
df4df182 UW |
2701 | const struct builtin_type *bt = builtin_type (gdbarch); |
2702 | ||
794ac428 UW |
2703 | /* The type we're building is this: */ |
2704 | #if 0 | |
2705 | union __gdb_builtin_type_vec64i | |
2706 | { | |
2707 | int64_t uint64; | |
2708 | int32_t v2_int32[2]; | |
2709 | int16_t v4_int16[4]; | |
2710 | int8_t v8_int8[8]; | |
2711 | }; | |
2712 | #endif | |
2713 | ||
2714 | struct type *t; | |
2715 | ||
e9bb382b UW |
2716 | t = arch_composite_type (gdbarch, |
2717 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2718 | |
2719 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2720 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2721 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2722 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2723 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2724 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2725 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2726 | |
876cecd0 | 2727 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2728 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2729 | tdep->i386_mmx_type = t; | |
2730 | } | |
2731 | ||
2732 | return tdep->i386_mmx_type; | |
2733 | } | |
2734 | ||
d7a0d72c | 2735 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 2736 | register REGNUM. */ |
d7a0d72c | 2737 | |
3a1e71e3 | 2738 | static struct type * |
90884b2b | 2739 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2740 | { |
1ba53b71 L |
2741 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2742 | return i386_mmx_type (gdbarch); | |
c131fcee L |
2743 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
2744 | return i386_ymm_type (gdbarch); | |
1ba53b71 L |
2745 | else |
2746 | { | |
2747 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2748 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2749 | return bt->builtin_int8; | |
2750 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2751 | return bt->builtin_int16; | |
2752 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2753 | return bt->builtin_int32; | |
2754 | } | |
2755 | ||
2756 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2757 | } |
2758 | ||
28fc6740 | 2759 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2760 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2761 | |
2762 | static int | |
c86c27af | 2763 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2764 | { |
5716833c MK |
2765 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2766 | int mmxreg, fpreg; | |
28fc6740 AC |
2767 | ULONGEST fstat; |
2768 | int tos; | |
c86c27af | 2769 | |
5716833c | 2770 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2771 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2772 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2773 | fpreg = (mmxreg + tos) % 8; |
2774 | ||
20a6ec49 | 2775 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2776 | } |
2777 | ||
05d1431c | 2778 | enum register_status |
28fc6740 | 2779 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2780 | int regnum, gdb_byte *buf) |
28fc6740 | 2781 | { |
1ba53b71 | 2782 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 2783 | enum register_status status; |
1ba53b71 | 2784 | |
5716833c | 2785 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2786 | { |
c86c27af MK |
2787 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2788 | ||
28fc6740 | 2789 | /* Extract (always little endian). */ |
05d1431c PA |
2790 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
2791 | if (status != REG_VALID) | |
2792 | return status; | |
1ba53b71 | 2793 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2794 | } |
2795 | else | |
1ba53b71 L |
2796 | { |
2797 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2798 | ||
c131fcee L |
2799 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2800 | { | |
2801 | regnum -= tdep->ymm0_regnum; | |
2802 | ||
1777feb0 | 2803 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
2804 | status = regcache_raw_read (regcache, |
2805 | I387_XMM0_REGNUM (tdep) + regnum, | |
2806 | raw_buf); | |
2807 | if (status != REG_VALID) | |
2808 | return status; | |
c131fcee L |
2809 | memcpy (buf, raw_buf, 16); |
2810 | /* Read upper 128bits. */ | |
05d1431c PA |
2811 | status = regcache_raw_read (regcache, |
2812 | tdep->ymm0h_regnum + regnum, | |
2813 | raw_buf); | |
2814 | if (status != REG_VALID) | |
2815 | return status; | |
c131fcee L |
2816 | memcpy (buf + 16, raw_buf, 16); |
2817 | } | |
2818 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2819 | { |
2820 | int gpnum = regnum - tdep->ax_regnum; | |
2821 | ||
2822 | /* Extract (always little endian). */ | |
05d1431c PA |
2823 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
2824 | if (status != REG_VALID) | |
2825 | return status; | |
1ba53b71 L |
2826 | memcpy (buf, raw_buf, 2); |
2827 | } | |
2828 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2829 | { | |
2830 | /* Check byte pseudo registers last since this function will | |
2831 | be called from amd64_pseudo_register_read, which handles | |
2832 | byte pseudo registers differently. */ | |
2833 | int gpnum = regnum - tdep->al_regnum; | |
2834 | ||
2835 | /* Extract (always little endian). We read both lower and | |
2836 | upper registers. */ | |
05d1431c PA |
2837 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
2838 | if (status != REG_VALID) | |
2839 | return status; | |
1ba53b71 L |
2840 | if (gpnum >= 4) |
2841 | memcpy (buf, raw_buf + 1, 1); | |
2842 | else | |
2843 | memcpy (buf, raw_buf, 1); | |
2844 | } | |
2845 | else | |
2846 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2847 | } | |
05d1431c PA |
2848 | |
2849 | return REG_VALID; | |
28fc6740 AC |
2850 | } |
2851 | ||
1ba53b71 | 2852 | void |
28fc6740 | 2853 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2854 | int regnum, const gdb_byte *buf) |
28fc6740 | 2855 | { |
1ba53b71 L |
2856 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2857 | ||
5716833c | 2858 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2859 | { |
c86c27af MK |
2860 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2861 | ||
28fc6740 | 2862 | /* Read ... */ |
1ba53b71 | 2863 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 2864 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 2865 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 2866 | /* ... Write. */ |
1ba53b71 | 2867 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
2868 | } |
2869 | else | |
1ba53b71 L |
2870 | { |
2871 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2872 | ||
c131fcee L |
2873 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2874 | { | |
2875 | regnum -= tdep->ymm0_regnum; | |
2876 | ||
2877 | /* ... Write lower 128bits. */ | |
2878 | regcache_raw_write (regcache, | |
2879 | I387_XMM0_REGNUM (tdep) + regnum, | |
2880 | buf); | |
2881 | /* ... Write upper 128bits. */ | |
2882 | regcache_raw_write (regcache, | |
2883 | tdep->ymm0h_regnum + regnum, | |
2884 | buf + 16); | |
2885 | } | |
2886 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2887 | { |
2888 | int gpnum = regnum - tdep->ax_regnum; | |
2889 | ||
2890 | /* Read ... */ | |
2891 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2892 | /* ... Modify ... (always little endian). */ | |
2893 | memcpy (raw_buf, buf, 2); | |
2894 | /* ... Write. */ | |
2895 | regcache_raw_write (regcache, gpnum, raw_buf); | |
2896 | } | |
2897 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2898 | { | |
2899 | /* Check byte pseudo registers last since this function will | |
2900 | be called from amd64_pseudo_register_read, which handles | |
2901 | byte pseudo registers differently. */ | |
2902 | int gpnum = regnum - tdep->al_regnum; | |
2903 | ||
2904 | /* Read ... We read both lower and upper registers. */ | |
2905 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2906 | /* ... Modify ... (always little endian). */ | |
2907 | if (gpnum >= 4) | |
2908 | memcpy (raw_buf + 1, buf, 1); | |
2909 | else | |
2910 | memcpy (raw_buf, buf, 1); | |
2911 | /* ... Write. */ | |
2912 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
2913 | } | |
2914 | else | |
2915 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2916 | } | |
28fc6740 | 2917 | } |
ff2e87ac AC |
2918 | \f |
2919 | ||
ff2e87ac AC |
2920 | /* Return the register number of the register allocated by GCC after |
2921 | REGNUM, or -1 if there is no such register. */ | |
2922 | ||
2923 | static int | |
2924 | i386_next_regnum (int regnum) | |
2925 | { | |
2926 | /* GCC allocates the registers in the order: | |
2927 | ||
2928 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2929 | ||
2930 | Since storing a variable in %esp doesn't make any sense we return | |
2931 | -1 for %ebp and for %esp itself. */ | |
2932 | static int next_regnum[] = | |
2933 | { | |
2934 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2935 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2936 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2937 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2938 | -1, -1, /* Slots for %esp and %ebp. */ | |
2939 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2940 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2941 | }; | |
2942 | ||
de5b9bb9 | 2943 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2944 | return next_regnum[regnum]; |
28fc6740 | 2945 | |
ff2e87ac AC |
2946 | return -1; |
2947 | } | |
2948 | ||
2949 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2950 | needs any special handling. */ | |
d7a0d72c | 2951 | |
3a1e71e3 | 2952 | static int |
1777feb0 MS |
2953 | i386_convert_register_p (struct gdbarch *gdbarch, |
2954 | int regnum, struct type *type) | |
d7a0d72c | 2955 | { |
de5b9bb9 MK |
2956 | int len = TYPE_LENGTH (type); |
2957 | ||
ff2e87ac AC |
2958 | /* Values may be spread across multiple registers. Most debugging |
2959 | formats aren't expressive enough to specify the locations, so | |
2960 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2961 | have a length that is a multiple of the word size, since GCC |
2962 | doesn't seem to put any other types into registers. */ | |
2963 | if (len > 4 && len % 4 == 0) | |
2964 | { | |
2965 | int last_regnum = regnum; | |
2966 | ||
2967 | while (len > 4) | |
2968 | { | |
2969 | last_regnum = i386_next_regnum (last_regnum); | |
2970 | len -= 4; | |
2971 | } | |
2972 | ||
2973 | if (last_regnum != -1) | |
2974 | return 1; | |
2975 | } | |
ff2e87ac | 2976 | |
0abe36f5 | 2977 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2978 | } |
2979 | ||
ff2e87ac AC |
2980 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2981 | return its contents in TO. */ | |
ac27f131 | 2982 | |
8dccd430 | 2983 | static int |
ff2e87ac | 2984 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
2985 | struct type *type, gdb_byte *to, |
2986 | int *optimizedp, int *unavailablep) | |
ac27f131 | 2987 | { |
20a6ec49 | 2988 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2989 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2990 | |
20a6ec49 | 2991 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
2992 | return i387_register_to_value (frame, regnum, type, to, |
2993 | optimizedp, unavailablep); | |
ff2e87ac | 2994 | |
fd35795f | 2995 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2996 | |
2997 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2998 | |
de5b9bb9 MK |
2999 | while (len > 0) |
3000 | { | |
3001 | gdb_assert (regnum != -1); | |
20a6ec49 | 3002 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3003 | |
8dccd430 PA |
3004 | if (!get_frame_register_bytes (frame, regnum, 0, |
3005 | register_size (gdbarch, regnum), | |
3006 | to, optimizedp, unavailablep)) | |
3007 | return 0; | |
3008 | ||
de5b9bb9 MK |
3009 | regnum = i386_next_regnum (regnum); |
3010 | len -= 4; | |
42835c2b | 3011 | to += 4; |
de5b9bb9 | 3012 | } |
8dccd430 PA |
3013 | |
3014 | *optimizedp = *unavailablep = 0; | |
3015 | return 1; | |
ac27f131 MK |
3016 | } |
3017 | ||
ff2e87ac AC |
3018 | /* Write the contents FROM of a value of type TYPE into register |
3019 | REGNUM in frame FRAME. */ | |
ac27f131 | 3020 | |
3a1e71e3 | 3021 | static void |
ff2e87ac | 3022 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3023 | struct type *type, const gdb_byte *from) |
ac27f131 | 3024 | { |
de5b9bb9 | 3025 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3026 | |
20a6ec49 | 3027 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3028 | { |
d532c08f MK |
3029 | i387_value_to_register (frame, regnum, type, from); |
3030 | return; | |
3031 | } | |
3d261580 | 3032 | |
fd35795f | 3033 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3034 | |
3035 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3036 | |
de5b9bb9 MK |
3037 | while (len > 0) |
3038 | { | |
3039 | gdb_assert (regnum != -1); | |
875f8d0e | 3040 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3041 | |
42835c2b | 3042 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3043 | regnum = i386_next_regnum (regnum); |
3044 | len -= 4; | |
42835c2b | 3045 | from += 4; |
de5b9bb9 | 3046 | } |
ac27f131 | 3047 | } |
ff2e87ac | 3048 | \f |
7fdafb5a MK |
3049 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3050 | in the general-purpose register set REGSET to register cache | |
3051 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3052 | |
20187ed5 | 3053 | void |
473f17b0 MK |
3054 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3055 | int regnum, const void *gregs, size_t len) | |
3056 | { | |
9ea75c57 | 3057 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 3058 | const gdb_byte *regs = gregs; |
473f17b0 MK |
3059 | int i; |
3060 | ||
3061 | gdb_assert (len == tdep->sizeof_gregset); | |
3062 | ||
3063 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3064 | { | |
3065 | if ((regnum == i || regnum == -1) | |
3066 | && tdep->gregset_reg_offset[i] != -1) | |
3067 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3068 | } | |
3069 | } | |
3070 | ||
7fdafb5a MK |
3071 | /* Collect register REGNUM from the register cache REGCACHE and store |
3072 | it in the buffer specified by GREGS and LEN as described by the | |
3073 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3074 | all registers in REGSET. */ | |
3075 | ||
3076 | void | |
3077 | i386_collect_gregset (const struct regset *regset, | |
3078 | const struct regcache *regcache, | |
3079 | int regnum, void *gregs, size_t len) | |
3080 | { | |
3081 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 3082 | gdb_byte *regs = gregs; |
7fdafb5a MK |
3083 | int i; |
3084 | ||
3085 | gdb_assert (len == tdep->sizeof_gregset); | |
3086 | ||
3087 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3088 | { | |
3089 | if ((regnum == i || regnum == -1) | |
3090 | && tdep->gregset_reg_offset[i] != -1) | |
3091 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3092 | } | |
3093 | } | |
3094 | ||
3095 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3096 | in the floating-point register set REGSET to register cache | |
3097 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3098 | |
3099 | static void | |
3100 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3101 | int regnum, const void *fpregs, size_t len) | |
3102 | { | |
9ea75c57 | 3103 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 3104 | |
66a72d25 MK |
3105 | if (len == I387_SIZEOF_FXSAVE) |
3106 | { | |
3107 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3108 | return; | |
3109 | } | |
3110 | ||
473f17b0 MK |
3111 | gdb_assert (len == tdep->sizeof_fpregset); |
3112 | i387_supply_fsave (regcache, regnum, fpregs); | |
3113 | } | |
8446b36a | 3114 | |
2f305df1 MK |
3115 | /* Collect register REGNUM from the register cache REGCACHE and store |
3116 | it in the buffer specified by FPREGS and LEN as described by the | |
3117 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3118 | all registers in REGSET. */ | |
7fdafb5a MK |
3119 | |
3120 | static void | |
3121 | i386_collect_fpregset (const struct regset *regset, | |
3122 | const struct regcache *regcache, | |
3123 | int regnum, void *fpregs, size_t len) | |
3124 | { | |
3125 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
3126 | ||
3127 | if (len == I387_SIZEOF_FXSAVE) | |
3128 | { | |
3129 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3130 | return; | |
3131 | } | |
3132 | ||
3133 | gdb_assert (len == tdep->sizeof_fpregset); | |
3134 | i387_collect_fsave (regcache, regnum, fpregs); | |
3135 | } | |
3136 | ||
c131fcee L |
3137 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
3138 | ||
3139 | static void | |
3140 | i386_supply_xstateregset (const struct regset *regset, | |
3141 | struct regcache *regcache, int regnum, | |
3142 | const void *xstateregs, size_t len) | |
3143 | { | |
c131fcee L |
3144 | i387_supply_xsave (regcache, regnum, xstateregs); |
3145 | } | |
3146 | ||
3147 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
3148 | ||
3149 | static void | |
3150 | i386_collect_xstateregset (const struct regset *regset, | |
3151 | const struct regcache *regcache, | |
3152 | int regnum, void *xstateregs, size_t len) | |
3153 | { | |
c131fcee L |
3154 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
3155 | } | |
3156 | ||
8446b36a MK |
3157 | /* Return the appropriate register set for the core section identified |
3158 | by SECT_NAME and SECT_SIZE. */ | |
3159 | ||
3160 | const struct regset * | |
3161 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
3162 | const char *sect_name, size_t sect_size) | |
3163 | { | |
3164 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3165 | ||
3166 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
3167 | { | |
3168 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
3169 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
3170 | i386_collect_gregset); | |
8446b36a MK |
3171 | return tdep->gregset; |
3172 | } | |
3173 | ||
66a72d25 MK |
3174 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
3175 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
3176 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
3177 | { |
3178 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
3179 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
3180 | i386_collect_fpregset); | |
8446b36a MK |
3181 | return tdep->fpregset; |
3182 | } | |
3183 | ||
c131fcee L |
3184 | if (strcmp (sect_name, ".reg-xstate") == 0) |
3185 | { | |
3186 | if (tdep->xstateregset == NULL) | |
3187 | tdep->xstateregset = regset_alloc (gdbarch, | |
3188 | i386_supply_xstateregset, | |
3189 | i386_collect_xstateregset); | |
3190 | ||
3191 | return tdep->xstateregset; | |
3192 | } | |
3193 | ||
8446b36a MK |
3194 | return NULL; |
3195 | } | |
473f17b0 | 3196 | \f |
fc338970 | 3197 | |
fc338970 | 3198 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3199 | |
3200 | CORE_ADDR | |
e17a4113 UW |
3201 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3202 | CORE_ADDR pc, char *name) | |
c906108c | 3203 | { |
e17a4113 UW |
3204 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3205 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3206 | ||
3207 | /* jmp *(dest) */ | |
3208 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3209 | { |
e17a4113 UW |
3210 | unsigned long indirect = |
3211 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3212 | struct minimal_symbol *indsym = |
fc338970 | 3213 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 3214 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3215 | |
c5aa993b | 3216 | if (symname) |
c906108c | 3217 | { |
c5aa993b JM |
3218 | if (strncmp (symname, "__imp_", 6) == 0 |
3219 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
3220 | return name ? 1 : |
3221 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3222 | } |
3223 | } | |
fc338970 | 3224 | return 0; /* Not a trampoline. */ |
c906108c | 3225 | } |
fc338970 MK |
3226 | \f |
3227 | ||
10458914 DJ |
3228 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3229 | routine. */ | |
8201327c | 3230 | |
4bd207ef | 3231 | int |
10458914 | 3232 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3233 | { |
10458914 | 3234 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
3235 | char *name; |
3236 | ||
3237 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3238 | return (name && strcmp ("_sigtramp", name) == 0); |
3239 | } | |
3240 | \f | |
3241 | ||
fc338970 MK |
3242 | /* We have two flavours of disassembly. The machinery on this page |
3243 | deals with switching between those. */ | |
c906108c SS |
3244 | |
3245 | static int | |
a89aa300 | 3246 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3247 | { |
5e3397bb MK |
3248 | gdb_assert (disassembly_flavor == att_flavor |
3249 | || disassembly_flavor == intel_flavor); | |
3250 | ||
3251 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3252 | constified, cast to prevent a compiler warning. */ | |
3253 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3254 | |
3255 | return print_insn_i386 (pc, info); | |
7a292a7a | 3256 | } |
fc338970 | 3257 | \f |
3ce1502b | 3258 | |
8201327c MK |
3259 | /* There are a few i386 architecture variants that differ only |
3260 | slightly from the generic i386 target. For now, we don't give them | |
3261 | their own source file, but include them here. As a consequence, | |
3262 | they'll always be included. */ | |
3ce1502b | 3263 | |
8201327c | 3264 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3265 | |
10458914 DJ |
3266 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3267 | routine. */ | |
911bc6ee | 3268 | |
8201327c | 3269 | static int |
10458914 | 3270 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3271 | { |
10458914 | 3272 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
3273 | char *name; |
3274 | ||
acd5c798 MK |
3275 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
3276 | currently unknown. */ | |
911bc6ee | 3277 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
3278 | return (name && (strcmp ("_sigreturn", name) == 0 |
3279 | || strcmp ("_sigacthandler", name) == 0 | |
3280 | || strcmp ("sigvechandler", name) == 0)); | |
3281 | } | |
d2a7c97a | 3282 | |
10458914 DJ |
3283 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3284 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3285 | |
3a1e71e3 | 3286 | static CORE_ADDR |
10458914 | 3287 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3288 | { |
e17a4113 UW |
3289 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3290 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3291 | gdb_byte buf[4]; |
acd5c798 | 3292 | CORE_ADDR sp; |
3ce1502b | 3293 | |
10458914 | 3294 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3295 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3296 | |
e17a4113 | 3297 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c MK |
3298 | } |
3299 | \f | |
3ce1502b | 3300 | |
8201327c | 3301 | /* Generic ELF. */ |
d2a7c97a | 3302 | |
8201327c MK |
3303 | void |
3304 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3305 | { | |
c4fc7f1b MK |
3306 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
3307 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 3308 | } |
3ce1502b | 3309 | |
8201327c | 3310 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3311 | |
8201327c MK |
3312 | void |
3313 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3314 | { | |
3315 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 3316 | |
8201327c MK |
3317 | /* System V Release 4 uses ELF. */ |
3318 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 3319 | |
dfe01d39 | 3320 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
3321 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
3322 | ||
911bc6ee | 3323 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 3324 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
3325 | tdep->sc_pc_offset = 36 + 14 * 4; |
3326 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 3327 | |
8201327c | 3328 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
3329 | } |
3330 | ||
8201327c | 3331 | /* DJGPP. */ |
3ce1502b | 3332 | |
3a1e71e3 | 3333 | static void |
8201327c | 3334 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 3335 | { |
8201327c | 3336 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 3337 | |
911bc6ee MK |
3338 | /* DJGPP doesn't have any special frames for signal handlers. */ |
3339 | tdep->sigtramp_p = NULL; | |
3ce1502b | 3340 | |
8201327c | 3341 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
3342 | |
3343 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
3344 | if (! tdesc_has_registers (info.target_desc)) |
3345 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
3346 | |
3347 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
3348 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
3349 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
3350 | set_gdbarch_sdb_reg_to_regnum. */ | |
3351 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3352 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
3353 | |
3354 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 3355 | } |
8201327c | 3356 | \f |
2acceee2 | 3357 | |
38c968cf AC |
3358 | /* i386 register groups. In addition to the normal groups, add "mmx" |
3359 | and "sse". */ | |
3360 | ||
3361 | static struct reggroup *i386_sse_reggroup; | |
3362 | static struct reggroup *i386_mmx_reggroup; | |
3363 | ||
3364 | static void | |
3365 | i386_init_reggroups (void) | |
3366 | { | |
3367 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
3368 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
3369 | } | |
3370 | ||
3371 | static void | |
3372 | i386_add_reggroups (struct gdbarch *gdbarch) | |
3373 | { | |
3374 | reggroup_add (gdbarch, i386_sse_reggroup); | |
3375 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
3376 | reggroup_add (gdbarch, general_reggroup); | |
3377 | reggroup_add (gdbarch, float_reggroup); | |
3378 | reggroup_add (gdbarch, all_reggroup); | |
3379 | reggroup_add (gdbarch, save_reggroup); | |
3380 | reggroup_add (gdbarch, restore_reggroup); | |
3381 | reggroup_add (gdbarch, vector_reggroup); | |
3382 | reggroup_add (gdbarch, system_reggroup); | |
3383 | } | |
3384 | ||
3385 | int | |
3386 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
3387 | struct reggroup *group) | |
3388 | { | |
c131fcee L |
3389 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3390 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
3391 | ymm_regnum_p, ymmh_regnum_p; | |
acd5c798 | 3392 | |
1ba53b71 L |
3393 | /* Don't include pseudo registers, except for MMX, in any register |
3394 | groups. */ | |
c131fcee | 3395 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3396 | return 0; |
3397 | ||
c131fcee | 3398 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3399 | return 0; |
3400 | ||
c131fcee | 3401 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3402 | return 0; |
3403 | ||
3404 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
3405 | if (group == i386_mmx_reggroup) |
3406 | return mmx_regnum_p; | |
1ba53b71 | 3407 | |
c131fcee L |
3408 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
3409 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); | |
38c968cf | 3410 | if (group == i386_sse_reggroup) |
c131fcee L |
3411 | return xmm_regnum_p || mxcsr_regnum_p; |
3412 | ||
3413 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
38c968cf | 3414 | if (group == vector_reggroup) |
c131fcee L |
3415 | return (mmx_regnum_p |
3416 | || ymm_regnum_p | |
3417 | || mxcsr_regnum_p | |
3418 | || (xmm_regnum_p | |
3419 | && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) | |
3420 | == I386_XSTATE_SSE_MASK))); | |
1ba53b71 L |
3421 | |
3422 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
3423 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
3424 | if (group == float_reggroup) |
3425 | return fp_regnum_p; | |
1ba53b71 | 3426 | |
c131fcee L |
3427 | /* For "info reg all", don't include upper YMM registers nor XMM |
3428 | registers when AVX is supported. */ | |
3429 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
3430 | if (group == all_reggroup | |
3431 | && ((xmm_regnum_p | |
3432 | && (tdep->xcr0 & I386_XSTATE_AVX)) | |
3433 | || ymmh_regnum_p)) | |
3434 | return 0; | |
3435 | ||
38c968cf | 3436 | if (group == general_reggroup) |
1ba53b71 L |
3437 | return (!fp_regnum_p |
3438 | && !mmx_regnum_p | |
c131fcee L |
3439 | && !mxcsr_regnum_p |
3440 | && !xmm_regnum_p | |
3441 | && !ymm_regnum_p | |
3442 | && !ymmh_regnum_p); | |
acd5c798 | 3443 | |
38c968cf AC |
3444 | return default_register_reggroup_p (gdbarch, regnum, group); |
3445 | } | |
38c968cf | 3446 | \f |
acd5c798 | 3447 | |
f837910f MK |
3448 | /* Get the ARGIth function argument for the current function. */ |
3449 | ||
42c466d7 | 3450 | static CORE_ADDR |
143985b7 AF |
3451 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
3452 | struct type *type) | |
3453 | { | |
e17a4113 UW |
3454 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3455 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f837910f | 3456 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 3457 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
3458 | } |
3459 | ||
514f746b AR |
3460 | static void |
3461 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
3462 | { | |
3463 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
3464 | ||
3465 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
3466 | adjust the PC in the regcache. */ | |
3467 | current_pc += 1; | |
3468 | regcache_write_pc (regcache, current_pc); | |
3469 | } | |
3470 | ||
3471 | ||
7ad10968 HZ |
3472 | #define PREFIX_REPZ 0x01 |
3473 | #define PREFIX_REPNZ 0x02 | |
3474 | #define PREFIX_LOCK 0x04 | |
3475 | #define PREFIX_DATA 0x08 | |
3476 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 3477 | |
7ad10968 HZ |
3478 | /* operand size */ |
3479 | enum | |
3480 | { | |
3481 | OT_BYTE = 0, | |
3482 | OT_WORD, | |
3483 | OT_LONG, | |
cf648174 | 3484 | OT_QUAD, |
a3c4230a | 3485 | OT_DQUAD, |
7ad10968 | 3486 | }; |
473f17b0 | 3487 | |
7ad10968 HZ |
3488 | /* i386 arith/logic operations */ |
3489 | enum | |
3490 | { | |
3491 | OP_ADDL, | |
3492 | OP_ORL, | |
3493 | OP_ADCL, | |
3494 | OP_SBBL, | |
3495 | OP_ANDL, | |
3496 | OP_SUBL, | |
3497 | OP_XORL, | |
3498 | OP_CMPL, | |
3499 | }; | |
5716833c | 3500 | |
7ad10968 HZ |
3501 | struct i386_record_s |
3502 | { | |
cf648174 | 3503 | struct gdbarch *gdbarch; |
7ad10968 | 3504 | struct regcache *regcache; |
df61f520 | 3505 | CORE_ADDR orig_addr; |
7ad10968 HZ |
3506 | CORE_ADDR addr; |
3507 | int aflag; | |
3508 | int dflag; | |
3509 | int override; | |
3510 | uint8_t modrm; | |
3511 | uint8_t mod, reg, rm; | |
3512 | int ot; | |
cf648174 HZ |
3513 | uint8_t rex_x; |
3514 | uint8_t rex_b; | |
3515 | int rip_offset; | |
3516 | int popl_esp_hack; | |
3517 | const int *regmap; | |
7ad10968 | 3518 | }; |
5716833c | 3519 | |
7ad10968 | 3520 | /* Parse "modrm" part in current memory address that irp->addr point to |
1777feb0 | 3521 | Return -1 if something wrong. */ |
5716833c | 3522 | |
7ad10968 HZ |
3523 | static int |
3524 | i386_record_modrm (struct i386_record_s *irp) | |
3525 | { | |
cf648174 | 3526 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 3527 | |
7ad10968 HZ |
3528 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
3529 | { | |
3530 | if (record_debug) | |
3531 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3532 | "addr %s len = 1.\n"), |
3533 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3534 | return -1; |
3535 | } | |
3536 | irp->addr++; | |
3537 | irp->mod = (irp->modrm >> 6) & 3; | |
3538 | irp->reg = (irp->modrm >> 3) & 7; | |
3539 | irp->rm = irp->modrm & 7; | |
5716833c | 3540 | |
7ad10968 HZ |
3541 | return 0; |
3542 | } | |
d2a7c97a | 3543 | |
7ad10968 HZ |
3544 | /* Get the memory address that current instruction write to and set it to |
3545 | the argument "addr". | |
1777feb0 | 3546 | Return -1 if something wrong. */ |
8201327c | 3547 | |
7ad10968 | 3548 | static int |
cf648174 | 3549 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 3550 | { |
cf648174 | 3551 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
3552 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3553 | gdb_byte buf[4]; | |
3554 | ULONGEST offset64; | |
21d0e8a4 | 3555 | |
7ad10968 HZ |
3556 | *addr = 0; |
3557 | if (irp->aflag) | |
3558 | { | |
3559 | /* 32 bits */ | |
3560 | int havesib = 0; | |
3561 | uint8_t scale = 0; | |
648d0c8b | 3562 | uint8_t byte; |
7ad10968 HZ |
3563 | uint8_t index = 0; |
3564 | uint8_t base = irp->rm; | |
896fb97d | 3565 | |
7ad10968 HZ |
3566 | if (base == 4) |
3567 | { | |
3568 | havesib = 1; | |
648d0c8b | 3569 | if (target_read_memory (irp->addr, &byte, 1)) |
7ad10968 HZ |
3570 | { |
3571 | if (record_debug) | |
3572 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3573 | "at addr %s len = 1.\n"), |
3574 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3575 | return -1; |
3576 | } | |
3577 | irp->addr++; | |
648d0c8b MS |
3578 | scale = (byte >> 6) & 3; |
3579 | index = ((byte >> 3) & 7) | irp->rex_x; | |
3580 | base = (byte & 7); | |
7ad10968 | 3581 | } |
cf648174 | 3582 | base |= irp->rex_b; |
21d0e8a4 | 3583 | |
7ad10968 HZ |
3584 | switch (irp->mod) |
3585 | { | |
3586 | case 0: | |
3587 | if ((base & 7) == 5) | |
3588 | { | |
3589 | base = 0xff; | |
60a1502a | 3590 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3591 | { |
3592 | if (record_debug) | |
3593 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3594 | "memory at addr %s len = 4.\n"), |
3595 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3596 | return -1; |
3597 | } | |
3598 | irp->addr += 4; | |
60a1502a | 3599 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
3600 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
3601 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 3602 | } |
7ad10968 HZ |
3603 | break; |
3604 | case 1: | |
60a1502a | 3605 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3606 | { |
3607 | if (record_debug) | |
3608 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3609 | "at addr %s len = 1.\n"), |
3610 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3611 | return -1; |
3612 | } | |
3613 | irp->addr++; | |
60a1502a | 3614 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3615 | break; |
3616 | case 2: | |
60a1502a | 3617 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3618 | { |
3619 | if (record_debug) | |
3620 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3621 | "at addr %s len = 4.\n"), |
3622 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3623 | return -1; |
3624 | } | |
60a1502a | 3625 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
3626 | irp->addr += 4; |
3627 | break; | |
3628 | } | |
356a6b3e | 3629 | |
60a1502a | 3630 | offset64 = 0; |
7ad10968 | 3631 | if (base != 0xff) |
cf648174 HZ |
3632 | { |
3633 | if (base == 4 && irp->popl_esp_hack) | |
3634 | *addr += irp->popl_esp_hack; | |
3635 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 3636 | &offset64); |
7ad10968 | 3637 | } |
cf648174 HZ |
3638 | if (irp->aflag == 2) |
3639 | { | |
60a1502a | 3640 | *addr += offset64; |
cf648174 HZ |
3641 | } |
3642 | else | |
60a1502a | 3643 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 3644 | |
7ad10968 HZ |
3645 | if (havesib && (index != 4 || scale != 0)) |
3646 | { | |
cf648174 | 3647 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 3648 | &offset64); |
cf648174 | 3649 | if (irp->aflag == 2) |
60a1502a | 3650 | *addr += offset64 << scale; |
cf648174 | 3651 | else |
60a1502a | 3652 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 HZ |
3653 | } |
3654 | } | |
3655 | else | |
3656 | { | |
3657 | /* 16 bits */ | |
3658 | switch (irp->mod) | |
3659 | { | |
3660 | case 0: | |
3661 | if (irp->rm == 6) | |
3662 | { | |
60a1502a | 3663 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3664 | { |
3665 | if (record_debug) | |
3666 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3667 | "memory at addr %s len = 2.\n"), |
3668 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3669 | return -1; |
3670 | } | |
3671 | irp->addr += 2; | |
60a1502a | 3672 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3673 | irp->rm = 0; |
3674 | goto no_rm; | |
3675 | } | |
7ad10968 HZ |
3676 | break; |
3677 | case 1: | |
60a1502a | 3678 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3679 | { |
3680 | if (record_debug) | |
3681 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3682 | "at addr %s len = 1.\n"), |
3683 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3684 | return -1; |
3685 | } | |
3686 | irp->addr++; | |
60a1502a | 3687 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3688 | break; |
3689 | case 2: | |
60a1502a | 3690 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3691 | { |
3692 | if (record_debug) | |
3693 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3694 | "at addr %s len = 2.\n"), |
3695 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3696 | return -1; |
3697 | } | |
3698 | irp->addr += 2; | |
60a1502a | 3699 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3700 | break; |
3701 | } | |
c4fc7f1b | 3702 | |
7ad10968 HZ |
3703 | switch (irp->rm) |
3704 | { | |
3705 | case 0: | |
cf648174 HZ |
3706 | regcache_raw_read_unsigned (irp->regcache, |
3707 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3708 | &offset64); |
3709 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3710 | regcache_raw_read_unsigned (irp->regcache, |
3711 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3712 | &offset64); |
3713 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3714 | break; |
3715 | case 1: | |
cf648174 HZ |
3716 | regcache_raw_read_unsigned (irp->regcache, |
3717 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3718 | &offset64); |
3719 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3720 | regcache_raw_read_unsigned (irp->regcache, |
3721 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3722 | &offset64); |
3723 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3724 | break; |
3725 | case 2: | |
cf648174 HZ |
3726 | regcache_raw_read_unsigned (irp->regcache, |
3727 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3728 | &offset64); |
3729 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3730 | regcache_raw_read_unsigned (irp->regcache, |
3731 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3732 | &offset64); |
3733 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3734 | break; |
3735 | case 3: | |
cf648174 HZ |
3736 | regcache_raw_read_unsigned (irp->regcache, |
3737 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3738 | &offset64); |
3739 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3740 | regcache_raw_read_unsigned (irp->regcache, |
3741 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3742 | &offset64); |
3743 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3744 | break; |
3745 | case 4: | |
cf648174 HZ |
3746 | regcache_raw_read_unsigned (irp->regcache, |
3747 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3748 | &offset64); |
3749 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3750 | break; |
3751 | case 5: | |
cf648174 HZ |
3752 | regcache_raw_read_unsigned (irp->regcache, |
3753 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3754 | &offset64); |
3755 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3756 | break; |
3757 | case 6: | |
cf648174 HZ |
3758 | regcache_raw_read_unsigned (irp->regcache, |
3759 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3760 | &offset64); |
3761 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3762 | break; |
3763 | case 7: | |
cf648174 HZ |
3764 | regcache_raw_read_unsigned (irp->regcache, |
3765 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3766 | &offset64); |
3767 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3768 | break; |
3769 | } | |
3770 | *addr &= 0xffff; | |
3771 | } | |
c4fc7f1b | 3772 | |
01fe1b41 | 3773 | no_rm: |
7ad10968 HZ |
3774 | return 0; |
3775 | } | |
c4fc7f1b | 3776 | |
7ad10968 HZ |
3777 | /* Record the value of the memory that willbe changed in current instruction |
3778 | to "record_arch_list". | |
1777feb0 | 3779 | Return -1 if something wrong. */ |
356a6b3e | 3780 | |
7ad10968 HZ |
3781 | static int |
3782 | i386_record_lea_modrm (struct i386_record_s *irp) | |
3783 | { | |
cf648174 HZ |
3784 | struct gdbarch *gdbarch = irp->gdbarch; |
3785 | uint64_t addr; | |
356a6b3e | 3786 | |
d7877f7e | 3787 | if (irp->override >= 0) |
7ad10968 | 3788 | { |
bb08c432 HZ |
3789 | if (record_memory_query) |
3790 | { | |
3791 | int q; | |
3792 | ||
3793 | target_terminal_ours (); | |
3794 | q = yquery (_("\ | |
3795 | Process record ignores the memory change of instruction at address %s\n\ | |
3796 | because it can't get the value of the segment register.\n\ | |
3797 | Do you want to stop the program?"), | |
3798 | paddress (gdbarch, irp->orig_addr)); | |
3799 | target_terminal_inferior (); | |
3800 | if (q) | |
3801 | return -1; | |
3802 | } | |
3803 | ||
7ad10968 HZ |
3804 | return 0; |
3805 | } | |
61113f8b | 3806 | |
7ad10968 HZ |
3807 | if (i386_record_lea_modrm_addr (irp, &addr)) |
3808 | return -1; | |
96297dab | 3809 | |
7ad10968 HZ |
3810 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
3811 | return -1; | |
a62cc96e | 3812 | |
7ad10968 HZ |
3813 | return 0; |
3814 | } | |
b6197528 | 3815 | |
cf648174 | 3816 | /* Record the push operation to "record_arch_list". |
1777feb0 | 3817 | Return -1 if something wrong. */ |
cf648174 HZ |
3818 | |
3819 | static int | |
3820 | i386_record_push (struct i386_record_s *irp, int size) | |
3821 | { | |
648d0c8b | 3822 | ULONGEST addr; |
cf648174 HZ |
3823 | |
3824 | if (record_arch_list_add_reg (irp->regcache, | |
3825 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
3826 | return -1; | |
3827 | regcache_raw_read_unsigned (irp->regcache, | |
3828 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b MS |
3829 | &addr); |
3830 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) | |
cf648174 HZ |
3831 | return -1; |
3832 | ||
3833 | return 0; | |
3834 | } | |
3835 | ||
0289bdd7 MS |
3836 | |
3837 | /* Defines contents to record. */ | |
3838 | #define I386_SAVE_FPU_REGS 0xfffd | |
3839 | #define I386_SAVE_FPU_ENV 0xfffe | |
3840 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
3841 | ||
1777feb0 MS |
3842 | /* Record the value of floating point registers which will be changed |
3843 | by the current instruction to "record_arch_list". Return -1 if | |
3844 | something is wrong. */ | |
0289bdd7 MS |
3845 | |
3846 | static int i386_record_floats (struct gdbarch *gdbarch, | |
3847 | struct i386_record_s *ir, | |
3848 | uint32_t iregnum) | |
3849 | { | |
3850 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3851 | int i; | |
3852 | ||
3853 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
3854 | happen. Currently we store st0-st7 registers, but we need not store all | |
3855 | registers all the time, in future we use ftag register and record only | |
3856 | those who are not marked as an empty. */ | |
3857 | ||
3858 | if (I386_SAVE_FPU_REGS == iregnum) | |
3859 | { | |
3860 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
3861 | { | |
3862 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3863 | return -1; | |
3864 | } | |
3865 | } | |
3866 | else if (I386_SAVE_FPU_ENV == iregnum) | |
3867 | { | |
3868 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3869 | { | |
3870 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3871 | return -1; | |
3872 | } | |
3873 | } | |
3874 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
3875 | { | |
3876 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3877 | { | |
3878 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3879 | return -1; | |
3880 | } | |
3881 | } | |
3882 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
3883 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
3884 | { | |
3885 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
3886 | return -1; | |
3887 | } | |
3888 | else | |
3889 | { | |
3890 | /* Parameter error. */ | |
3891 | return -1; | |
3892 | } | |
3893 | if(I386_SAVE_FPU_ENV != iregnum) | |
3894 | { | |
3895 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3896 | { | |
3897 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3898 | return -1; | |
3899 | } | |
3900 | } | |
3901 | return 0; | |
3902 | } | |
3903 | ||
7ad10968 HZ |
3904 | /* Parse the current instruction and record the values of the registers and |
3905 | memory that will be changed in current instruction to "record_arch_list". | |
1777feb0 | 3906 | Return -1 if something wrong. */ |
8201327c | 3907 | |
cf648174 HZ |
3908 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
3909 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
3910 | ||
a6b808b4 | 3911 | int |
7ad10968 | 3912 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 3913 | CORE_ADDR input_addr) |
7ad10968 | 3914 | { |
60a1502a | 3915 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 3916 | int prefixes = 0; |
580879fc | 3917 | int regnum = 0; |
425b824a MS |
3918 | uint32_t opcode; |
3919 | uint8_t opcode8; | |
648d0c8b | 3920 | ULONGEST addr; |
60a1502a | 3921 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 3922 | struct i386_record_s ir; |
0289bdd7 | 3923 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
3924 | int rex = 0; |
3925 | uint8_t rex_w = -1; | |
3926 | uint8_t rex_r = 0; | |
7ad10968 | 3927 | |
8408d274 | 3928 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 3929 | ir.regcache = regcache; |
648d0c8b MS |
3930 | ir.addr = input_addr; |
3931 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
3932 | ir.aflag = 1; |
3933 | ir.dflag = 1; | |
cf648174 HZ |
3934 | ir.override = -1; |
3935 | ir.popl_esp_hack = 0; | |
a3c4230a | 3936 | ir.regmap = tdep->record_regmap; |
cf648174 | 3937 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
3938 | |
3939 | if (record_debug > 1) | |
3940 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
3941 | "addr = %s\n", |
3942 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3943 | |
3944 | /* prefixes */ | |
3945 | while (1) | |
3946 | { | |
425b824a | 3947 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
3948 | { |
3949 | if (record_debug) | |
3950 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3951 | "addr %s len = 1.\n"), |
3952 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3953 | return -1; |
3954 | } | |
3955 | ir.addr++; | |
425b824a | 3956 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 3957 | { |
01fe1b41 | 3958 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
3959 | prefixes |= PREFIX_REPZ; |
3960 | break; | |
01fe1b41 | 3961 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
3962 | prefixes |= PREFIX_REPNZ; |
3963 | break; | |
01fe1b41 | 3964 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
3965 | prefixes |= PREFIX_LOCK; |
3966 | break; | |
01fe1b41 | 3967 | case CS_PREFIX_OPCODE: |
cf648174 | 3968 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 3969 | break; |
01fe1b41 | 3970 | case SS_PREFIX_OPCODE: |
cf648174 | 3971 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 3972 | break; |
01fe1b41 | 3973 | case DS_PREFIX_OPCODE: |
cf648174 | 3974 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 3975 | break; |
01fe1b41 | 3976 | case ES_PREFIX_OPCODE: |
cf648174 | 3977 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 3978 | break; |
01fe1b41 | 3979 | case FS_PREFIX_OPCODE: |
cf648174 | 3980 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 3981 | break; |
01fe1b41 | 3982 | case GS_PREFIX_OPCODE: |
cf648174 | 3983 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 3984 | break; |
01fe1b41 | 3985 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
3986 | prefixes |= PREFIX_DATA; |
3987 | break; | |
01fe1b41 | 3988 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
3989 | prefixes |= PREFIX_ADDR; |
3990 | break; | |
d691bec7 MS |
3991 | case 0x40: /* i386 inc %eax */ |
3992 | case 0x41: /* i386 inc %ecx */ | |
3993 | case 0x42: /* i386 inc %edx */ | |
3994 | case 0x43: /* i386 inc %ebx */ | |
3995 | case 0x44: /* i386 inc %esp */ | |
3996 | case 0x45: /* i386 inc %ebp */ | |
3997 | case 0x46: /* i386 inc %esi */ | |
3998 | case 0x47: /* i386 inc %edi */ | |
3999 | case 0x48: /* i386 dec %eax */ | |
4000 | case 0x49: /* i386 dec %ecx */ | |
4001 | case 0x4a: /* i386 dec %edx */ | |
4002 | case 0x4b: /* i386 dec %ebx */ | |
4003 | case 0x4c: /* i386 dec %esp */ | |
4004 | case 0x4d: /* i386 dec %ebp */ | |
4005 | case 0x4e: /* i386 dec %esi */ | |
4006 | case 0x4f: /* i386 dec %edi */ | |
4007 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
4008 | { |
4009 | /* REX */ | |
4010 | rex = 1; | |
425b824a MS |
4011 | rex_w = (opcode8 >> 3) & 1; |
4012 | rex_r = (opcode8 & 0x4) << 1; | |
4013 | ir.rex_x = (opcode8 & 0x2) << 2; | |
4014 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 4015 | } |
d691bec7 MS |
4016 | else /* 32 bit target */ |
4017 | goto out_prefixes; | |
cf648174 | 4018 | break; |
7ad10968 HZ |
4019 | default: |
4020 | goto out_prefixes; | |
4021 | break; | |
4022 | } | |
4023 | } | |
01fe1b41 | 4024 | out_prefixes: |
cf648174 HZ |
4025 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
4026 | { | |
4027 | ir.dflag = 2; | |
4028 | } | |
4029 | else | |
4030 | { | |
4031 | if (prefixes & PREFIX_DATA) | |
4032 | ir.dflag ^= 1; | |
4033 | } | |
7ad10968 HZ |
4034 | if (prefixes & PREFIX_ADDR) |
4035 | ir.aflag ^= 1; | |
cf648174 HZ |
4036 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4037 | ir.aflag = 2; | |
7ad10968 | 4038 | |
1777feb0 | 4039 | /* Now check op code. */ |
425b824a | 4040 | opcode = (uint32_t) opcode8; |
01fe1b41 | 4041 | reswitch: |
7ad10968 HZ |
4042 | switch (opcode) |
4043 | { | |
4044 | case 0x0f: | |
425b824a | 4045 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
4046 | { |
4047 | if (record_debug) | |
4048 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
4049 | "addr %s len = 1.\n"), |
4050 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4051 | return -1; |
4052 | } | |
4053 | ir.addr++; | |
a3c4230a | 4054 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
4055 | goto reswitch; |
4056 | break; | |
93924b6b | 4057 | |
a38bba38 | 4058 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
4059 | case 0x01: |
4060 | case 0x02: | |
4061 | case 0x03: | |
4062 | case 0x04: | |
4063 | case 0x05: | |
4064 | case 0x08: | |
4065 | case 0x09: | |
4066 | case 0x0a: | |
4067 | case 0x0b: | |
4068 | case 0x0c: | |
4069 | case 0x0d: | |
4070 | case 0x10: | |
4071 | case 0x11: | |
4072 | case 0x12: | |
4073 | case 0x13: | |
4074 | case 0x14: | |
4075 | case 0x15: | |
4076 | case 0x18: | |
4077 | case 0x19: | |
4078 | case 0x1a: | |
4079 | case 0x1b: | |
4080 | case 0x1c: | |
4081 | case 0x1d: | |
4082 | case 0x20: | |
4083 | case 0x21: | |
4084 | case 0x22: | |
4085 | case 0x23: | |
4086 | case 0x24: | |
4087 | case 0x25: | |
4088 | case 0x28: | |
4089 | case 0x29: | |
4090 | case 0x2a: | |
4091 | case 0x2b: | |
4092 | case 0x2c: | |
4093 | case 0x2d: | |
4094 | case 0x30: | |
4095 | case 0x31: | |
4096 | case 0x32: | |
4097 | case 0x33: | |
4098 | case 0x34: | |
4099 | case 0x35: | |
4100 | case 0x38: | |
4101 | case 0x39: | |
4102 | case 0x3a: | |
4103 | case 0x3b: | |
4104 | case 0x3c: | |
4105 | case 0x3d: | |
4106 | if (((opcode >> 3) & 7) != OP_CMPL) | |
4107 | { | |
4108 | if ((opcode & 1) == 0) | |
4109 | ir.ot = OT_BYTE; | |
4110 | else | |
4111 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 4112 | |
7ad10968 HZ |
4113 | switch ((opcode >> 1) & 3) |
4114 | { | |
a38bba38 | 4115 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
4116 | if (i386_record_modrm (&ir)) |
4117 | return -1; | |
4118 | if (ir.mod != 3) | |
4119 | { | |
4120 | if (i386_record_lea_modrm (&ir)) | |
4121 | return -1; | |
4122 | } | |
4123 | else | |
4124 | { | |
cf648174 HZ |
4125 | ir.rm |= ir.rex_b; |
4126 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4127 | ir.rm &= 0x3; |
cf648174 | 4128 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4129 | } |
4130 | break; | |
a38bba38 | 4131 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
4132 | if (i386_record_modrm (&ir)) |
4133 | return -1; | |
cf648174 HZ |
4134 | ir.reg |= rex_r; |
4135 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4136 | ir.reg &= 0x3; |
cf648174 | 4137 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4138 | break; |
a38bba38 | 4139 | case 2: /* OP A, Iv */ |
cf648174 | 4140 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4141 | break; |
4142 | } | |
4143 | } | |
cf648174 | 4144 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4145 | break; |
42fdc8df | 4146 | |
a38bba38 | 4147 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
4148 | case 0x81: |
4149 | case 0x82: | |
4150 | case 0x83: | |
4151 | if (i386_record_modrm (&ir)) | |
4152 | return -1; | |
8201327c | 4153 | |
7ad10968 HZ |
4154 | if (ir.reg != OP_CMPL) |
4155 | { | |
4156 | if ((opcode & 1) == 0) | |
4157 | ir.ot = OT_BYTE; | |
4158 | else | |
4159 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 4160 | |
7ad10968 HZ |
4161 | if (ir.mod != 3) |
4162 | { | |
cf648174 HZ |
4163 | if (opcode == 0x83) |
4164 | ir.rip_offset = 1; | |
4165 | else | |
4166 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4167 | if (i386_record_lea_modrm (&ir)) |
4168 | return -1; | |
4169 | } | |
4170 | else | |
cf648174 | 4171 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 4172 | } |
cf648174 | 4173 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4174 | break; |
5e3397bb | 4175 | |
a38bba38 | 4176 | case 0x40: /* inc */ |
7ad10968 HZ |
4177 | case 0x41: |
4178 | case 0x42: | |
4179 | case 0x43: | |
4180 | case 0x44: | |
4181 | case 0x45: | |
4182 | case 0x46: | |
4183 | case 0x47: | |
a38bba38 MS |
4184 | |
4185 | case 0x48: /* dec */ | |
7ad10968 HZ |
4186 | case 0x49: |
4187 | case 0x4a: | |
4188 | case 0x4b: | |
4189 | case 0x4c: | |
4190 | case 0x4d: | |
4191 | case 0x4e: | |
4192 | case 0x4f: | |
a38bba38 | 4193 | |
cf648174 HZ |
4194 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
4195 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 4196 | break; |
acd5c798 | 4197 | |
a38bba38 | 4198 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
4199 | case 0xf7: |
4200 | if ((opcode & 1) == 0) | |
4201 | ir.ot = OT_BYTE; | |
4202 | else | |
4203 | ir.ot = ir.dflag + OT_WORD; | |
4204 | if (i386_record_modrm (&ir)) | |
4205 | return -1; | |
acd5c798 | 4206 | |
cf648174 HZ |
4207 | if (ir.mod != 3 && ir.reg == 0) |
4208 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4209 | ||
7ad10968 HZ |
4210 | switch (ir.reg) |
4211 | { | |
a38bba38 | 4212 | case 0: /* test */ |
cf648174 | 4213 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4214 | break; |
a38bba38 MS |
4215 | case 2: /* not */ |
4216 | case 3: /* neg */ | |
7ad10968 HZ |
4217 | if (ir.mod != 3) |
4218 | { | |
4219 | if (i386_record_lea_modrm (&ir)) | |
4220 | return -1; | |
4221 | } | |
4222 | else | |
4223 | { | |
cf648174 HZ |
4224 | ir.rm |= ir.rex_b; |
4225 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4226 | ir.rm &= 0x3; |
cf648174 | 4227 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4228 | } |
a38bba38 | 4229 | if (ir.reg == 3) /* neg */ |
cf648174 | 4230 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4231 | break; |
a38bba38 MS |
4232 | case 4: /* mul */ |
4233 | case 5: /* imul */ | |
4234 | case 6: /* div */ | |
4235 | case 7: /* idiv */ | |
cf648174 | 4236 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 4237 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
4238 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
4239 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4240 | break; |
4241 | default: | |
4242 | ir.addr -= 2; | |
4243 | opcode = opcode << 8 | ir.modrm; | |
4244 | goto no_support; | |
4245 | break; | |
4246 | } | |
4247 | break; | |
4248 | ||
a38bba38 MS |
4249 | case 0xfe: /* GRP4 */ |
4250 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
4251 | if (i386_record_modrm (&ir)) |
4252 | return -1; | |
4253 | if (ir.reg >= 2 && opcode == 0xfe) | |
4254 | { | |
4255 | ir.addr -= 2; | |
4256 | opcode = opcode << 8 | ir.modrm; | |
4257 | goto no_support; | |
4258 | } | |
7ad10968 HZ |
4259 | switch (ir.reg) |
4260 | { | |
a38bba38 MS |
4261 | case 0: /* inc */ |
4262 | case 1: /* dec */ | |
cf648174 HZ |
4263 | if ((opcode & 1) == 0) |
4264 | ir.ot = OT_BYTE; | |
4265 | else | |
4266 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4267 | if (ir.mod != 3) |
4268 | { | |
4269 | if (i386_record_lea_modrm (&ir)) | |
4270 | return -1; | |
4271 | } | |
4272 | else | |
4273 | { | |
cf648174 HZ |
4274 | ir.rm |= ir.rex_b; |
4275 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4276 | ir.rm &= 0x3; |
cf648174 | 4277 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4278 | } |
cf648174 | 4279 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4280 | break; |
a38bba38 | 4281 | case 2: /* call */ |
cf648174 HZ |
4282 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4283 | ir.dflag = 2; | |
4284 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4285 | return -1; |
cf648174 | 4286 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4287 | break; |
a38bba38 | 4288 | case 3: /* lcall */ |
cf648174 HZ |
4289 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4290 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4291 | return -1; |
cf648174 | 4292 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4293 | break; |
a38bba38 MS |
4294 | case 4: /* jmp */ |
4295 | case 5: /* ljmp */ | |
cf648174 HZ |
4296 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4297 | break; | |
a38bba38 | 4298 | case 6: /* push */ |
cf648174 HZ |
4299 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4300 | ir.dflag = 2; | |
4301 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4302 | return -1; | |
7ad10968 HZ |
4303 | break; |
4304 | default: | |
4305 | ir.addr -= 2; | |
4306 | opcode = opcode << 8 | ir.modrm; | |
4307 | goto no_support; | |
4308 | break; | |
4309 | } | |
4310 | break; | |
4311 | ||
a38bba38 | 4312 | case 0x84: /* test */ |
7ad10968 HZ |
4313 | case 0x85: |
4314 | case 0xa8: | |
4315 | case 0xa9: | |
cf648174 | 4316 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4317 | break; |
4318 | ||
a38bba38 | 4319 | case 0x98: /* CWDE/CBW */ |
cf648174 | 4320 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4321 | break; |
4322 | ||
a38bba38 | 4323 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
4324 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4325 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4326 | break; |
4327 | ||
a38bba38 | 4328 | case 0x0faf: /* imul */ |
7ad10968 HZ |
4329 | case 0x69: |
4330 | case 0x6b: | |
4331 | ir.ot = ir.dflag + OT_WORD; | |
4332 | if (i386_record_modrm (&ir)) | |
4333 | return -1; | |
cf648174 HZ |
4334 | if (opcode == 0x69) |
4335 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4336 | else if (opcode == 0x6b) | |
4337 | ir.rip_offset = 1; | |
4338 | ir.reg |= rex_r; | |
4339 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4340 | ir.reg &= 0x3; |
cf648174 HZ |
4341 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4342 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4343 | break; |
4344 | ||
a38bba38 | 4345 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
4346 | case 0x0fc1: |
4347 | if ((opcode & 1) == 0) | |
4348 | ir.ot = OT_BYTE; | |
4349 | else | |
4350 | ir.ot = ir.dflag + OT_WORD; | |
4351 | if (i386_record_modrm (&ir)) | |
4352 | return -1; | |
cf648174 | 4353 | ir.reg |= rex_r; |
7ad10968 HZ |
4354 | if (ir.mod == 3) |
4355 | { | |
cf648174 | 4356 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4357 | ir.reg &= 0x3; |
cf648174 HZ |
4358 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4359 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4360 | ir.rm &= 0x3; |
cf648174 | 4361 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4362 | } |
4363 | else | |
4364 | { | |
4365 | if (i386_record_lea_modrm (&ir)) | |
4366 | return -1; | |
cf648174 | 4367 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4368 | ir.reg &= 0x3; |
cf648174 | 4369 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4370 | } |
cf648174 | 4371 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4372 | break; |
4373 | ||
a38bba38 | 4374 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
4375 | case 0x0fb1: |
4376 | if ((opcode & 1) == 0) | |
4377 | ir.ot = OT_BYTE; | |
4378 | else | |
4379 | ir.ot = ir.dflag + OT_WORD; | |
4380 | if (i386_record_modrm (&ir)) | |
4381 | return -1; | |
4382 | if (ir.mod == 3) | |
4383 | { | |
cf648174 HZ |
4384 | ir.reg |= rex_r; |
4385 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
4386 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4387 | ir.reg &= 0x3; |
cf648174 | 4388 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4389 | } |
4390 | else | |
4391 | { | |
cf648174 | 4392 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4393 | if (i386_record_lea_modrm (&ir)) |
4394 | return -1; | |
4395 | } | |
cf648174 | 4396 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4397 | break; |
4398 | ||
a38bba38 | 4399 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
4400 | if (i386_record_modrm (&ir)) |
4401 | return -1; | |
4402 | if (ir.mod == 3) | |
4403 | { | |
4404 | ir.addr -= 2; | |
4405 | opcode = opcode << 8 | ir.modrm; | |
4406 | goto no_support; | |
4407 | } | |
cf648174 HZ |
4408 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4409 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4410 | if (i386_record_lea_modrm (&ir)) |
4411 | return -1; | |
cf648174 | 4412 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4413 | break; |
4414 | ||
a38bba38 | 4415 | case 0x50: /* push */ |
7ad10968 HZ |
4416 | case 0x51: |
4417 | case 0x52: | |
4418 | case 0x53: | |
4419 | case 0x54: | |
4420 | case 0x55: | |
4421 | case 0x56: | |
4422 | case 0x57: | |
4423 | case 0x68: | |
4424 | case 0x6a: | |
cf648174 HZ |
4425 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4426 | ir.dflag = 2; | |
4427 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4428 | return -1; | |
4429 | break; | |
4430 | ||
a38bba38 MS |
4431 | case 0x06: /* push es */ |
4432 | case 0x0e: /* push cs */ | |
4433 | case 0x16: /* push ss */ | |
4434 | case 0x1e: /* push ds */ | |
cf648174 HZ |
4435 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4436 | { | |
4437 | ir.addr -= 1; | |
4438 | goto no_support; | |
4439 | } | |
4440 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4441 | return -1; | |
4442 | break; | |
4443 | ||
a38bba38 MS |
4444 | case 0x0fa0: /* push fs */ |
4445 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
4446 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4447 | { | |
4448 | ir.addr -= 2; | |
4449 | goto no_support; | |
4450 | } | |
4451 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4452 | return -1; |
cf648174 HZ |
4453 | break; |
4454 | ||
a38bba38 | 4455 | case 0x60: /* pusha */ |
cf648174 HZ |
4456 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4457 | { | |
4458 | ir.addr -= 1; | |
4459 | goto no_support; | |
4460 | } | |
4461 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
4462 | return -1; |
4463 | break; | |
4464 | ||
a38bba38 | 4465 | case 0x58: /* pop */ |
7ad10968 HZ |
4466 | case 0x59: |
4467 | case 0x5a: | |
4468 | case 0x5b: | |
4469 | case 0x5c: | |
4470 | case 0x5d: | |
4471 | case 0x5e: | |
4472 | case 0x5f: | |
cf648174 HZ |
4473 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4474 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
4475 | break; |
4476 | ||
a38bba38 | 4477 | case 0x61: /* popa */ |
cf648174 HZ |
4478 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4479 | { | |
4480 | ir.addr -= 1; | |
4481 | goto no_support; | |
7ad10968 | 4482 | } |
425b824a MS |
4483 | for (regnum = X86_RECORD_REAX_REGNUM; |
4484 | regnum <= X86_RECORD_REDI_REGNUM; | |
4485 | regnum++) | |
4486 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); | |
7ad10968 HZ |
4487 | break; |
4488 | ||
a38bba38 | 4489 | case 0x8f: /* pop */ |
cf648174 HZ |
4490 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4491 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
4492 | else | |
4493 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4494 | if (i386_record_modrm (&ir)) |
4495 | return -1; | |
4496 | if (ir.mod == 3) | |
cf648174 | 4497 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
4498 | else |
4499 | { | |
cf648174 | 4500 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
4501 | if (i386_record_lea_modrm (&ir)) |
4502 | return -1; | |
4503 | } | |
cf648174 | 4504 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
4505 | break; |
4506 | ||
a38bba38 | 4507 | case 0xc8: /* enter */ |
cf648174 HZ |
4508 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
4509 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4510 | ir.dflag = 2; | |
4511 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
4512 | return -1; |
4513 | break; | |
4514 | ||
a38bba38 | 4515 | case 0xc9: /* leave */ |
cf648174 HZ |
4516 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4517 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
4518 | break; |
4519 | ||
a38bba38 | 4520 | case 0x07: /* pop es */ |
cf648174 HZ |
4521 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4522 | { | |
4523 | ir.addr -= 1; | |
4524 | goto no_support; | |
4525 | } | |
4526 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4527 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
4528 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4529 | break; |
4530 | ||
a38bba38 | 4531 | case 0x17: /* pop ss */ |
cf648174 HZ |
4532 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4533 | { | |
4534 | ir.addr -= 1; | |
4535 | goto no_support; | |
4536 | } | |
4537 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4538 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
4539 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4540 | break; |
4541 | ||
a38bba38 | 4542 | case 0x1f: /* pop ds */ |
cf648174 HZ |
4543 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4544 | { | |
4545 | ir.addr -= 1; | |
4546 | goto no_support; | |
4547 | } | |
4548 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4549 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
4550 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4551 | break; |
4552 | ||
a38bba38 | 4553 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
4554 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4555 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
4556 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4557 | break; |
4558 | ||
a38bba38 | 4559 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
4560 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4561 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
4562 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4563 | break; |
4564 | ||
a38bba38 | 4565 | case 0x88: /* mov */ |
7ad10968 HZ |
4566 | case 0x89: |
4567 | case 0xc6: | |
4568 | case 0xc7: | |
4569 | if ((opcode & 1) == 0) | |
4570 | ir.ot = OT_BYTE; | |
4571 | else | |
4572 | ir.ot = ir.dflag + OT_WORD; | |
4573 | ||
4574 | if (i386_record_modrm (&ir)) | |
4575 | return -1; | |
4576 | ||
4577 | if (ir.mod != 3) | |
4578 | { | |
cf648174 HZ |
4579 | if (opcode == 0xc6 || opcode == 0xc7) |
4580 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4581 | if (i386_record_lea_modrm (&ir)) |
4582 | return -1; | |
4583 | } | |
4584 | else | |
4585 | { | |
cf648174 HZ |
4586 | if (opcode == 0xc6 || opcode == 0xc7) |
4587 | ir.rm |= ir.rex_b; | |
4588 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4589 | ir.rm &= 0x3; |
cf648174 | 4590 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4591 | } |
7ad10968 | 4592 | break; |
cf648174 | 4593 | |
a38bba38 | 4594 | case 0x8a: /* mov */ |
7ad10968 HZ |
4595 | case 0x8b: |
4596 | if ((opcode & 1) == 0) | |
4597 | ir.ot = OT_BYTE; | |
4598 | else | |
4599 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4600 | if (i386_record_modrm (&ir)) |
4601 | return -1; | |
cf648174 HZ |
4602 | ir.reg |= rex_r; |
4603 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4604 | ir.reg &= 0x3; |
cf648174 HZ |
4605 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4606 | break; | |
7ad10968 | 4607 | |
a38bba38 | 4608 | case 0x8c: /* mov seg */ |
cf648174 | 4609 | if (i386_record_modrm (&ir)) |
7ad10968 | 4610 | return -1; |
cf648174 HZ |
4611 | if (ir.reg > 5) |
4612 | { | |
4613 | ir.addr -= 2; | |
4614 | opcode = opcode << 8 | ir.modrm; | |
4615 | goto no_support; | |
4616 | } | |
4617 | ||
4618 | if (ir.mod == 3) | |
4619 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
4620 | else | |
4621 | { | |
4622 | ir.ot = OT_WORD; | |
4623 | if (i386_record_lea_modrm (&ir)) | |
4624 | return -1; | |
4625 | } | |
7ad10968 HZ |
4626 | break; |
4627 | ||
a38bba38 | 4628 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
4629 | if (i386_record_modrm (&ir)) |
4630 | return -1; | |
7ad10968 HZ |
4631 | switch (ir.reg) |
4632 | { | |
4633 | case 0: | |
425b824a | 4634 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
4635 | break; |
4636 | case 2: | |
425b824a | 4637 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
4638 | break; |
4639 | case 3: | |
425b824a | 4640 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
4641 | break; |
4642 | case 4: | |
425b824a | 4643 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
4644 | break; |
4645 | case 5: | |
425b824a | 4646 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4647 | break; |
4648 | default: | |
4649 | ir.addr -= 2; | |
4650 | opcode = opcode << 8 | ir.modrm; | |
4651 | goto no_support; | |
4652 | break; | |
4653 | } | |
425b824a | 4654 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 | 4655 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4656 | break; |
4657 | ||
a38bba38 MS |
4658 | case 0x0fb6: /* movzbS */ |
4659 | case 0x0fb7: /* movzwS */ | |
4660 | case 0x0fbe: /* movsbS */ | |
4661 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
4662 | if (i386_record_modrm (&ir)) |
4663 | return -1; | |
cf648174 | 4664 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
4665 | break; |
4666 | ||
a38bba38 | 4667 | case 0x8d: /* lea */ |
7ad10968 HZ |
4668 | if (i386_record_modrm (&ir)) |
4669 | return -1; | |
4670 | if (ir.mod == 3) | |
4671 | { | |
4672 | ir.addr -= 2; | |
4673 | opcode = opcode << 8 | ir.modrm; | |
4674 | goto no_support; | |
4675 | } | |
7ad10968 | 4676 | ir.ot = ir.dflag; |
cf648174 HZ |
4677 | ir.reg |= rex_r; |
4678 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4679 | ir.reg &= 0x3; |
cf648174 | 4680 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4681 | break; |
4682 | ||
a38bba38 | 4683 | case 0xa0: /* mov EAX */ |
7ad10968 | 4684 | case 0xa1: |
a38bba38 MS |
4685 | |
4686 | case 0xd7: /* xlat */ | |
cf648174 | 4687 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4688 | break; |
4689 | ||
a38bba38 | 4690 | case 0xa2: /* mov EAX */ |
7ad10968 | 4691 | case 0xa3: |
d7877f7e | 4692 | if (ir.override >= 0) |
cf648174 | 4693 | { |
bb08c432 HZ |
4694 | if (record_memory_query) |
4695 | { | |
4696 | int q; | |
4697 | ||
4698 | target_terminal_ours (); | |
4699 | q = yquery (_("\ | |
4700 | Process record ignores the memory change of instruction at address %s\n\ | |
4701 | because it can't get the value of the segment register.\n\ | |
4702 | Do you want to stop the program?"), | |
4703 | paddress (gdbarch, ir.orig_addr)); | |
4704 | target_terminal_inferior (); | |
4705 | if (q) | |
4706 | return -1; | |
4707 | } | |
cf648174 HZ |
4708 | } |
4709 | else | |
4710 | { | |
4711 | if ((opcode & 1) == 0) | |
4712 | ir.ot = OT_BYTE; | |
4713 | else | |
4714 | ir.ot = ir.dflag + OT_WORD; | |
4715 | if (ir.aflag == 2) | |
4716 | { | |
60a1502a | 4717 | if (target_read_memory (ir.addr, buf, 8)) |
cf648174 HZ |
4718 | { |
4719 | if (record_debug) | |
4720 | printf_unfiltered (_("Process record: error reading " | |
4721 | "memory at addr 0x%s len = 8.\n"), | |
4722 | paddress (gdbarch, ir.addr)); | |
4723 | return -1; | |
4724 | } | |
4725 | ir.addr += 8; | |
60a1502a | 4726 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
4727 | } |
4728 | else if (ir.aflag) | |
4729 | { | |
60a1502a | 4730 | if (target_read_memory (ir.addr, buf, 4)) |
cf648174 HZ |
4731 | { |
4732 | if (record_debug) | |
4733 | printf_unfiltered (_("Process record: error reading " | |
4734 | "memory at addr 0x%s len = 4.\n"), | |
4735 | paddress (gdbarch, ir.addr)); | |
4736 | return -1; | |
4737 | } | |
4738 | ir.addr += 4; | |
60a1502a | 4739 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
4740 | } |
4741 | else | |
4742 | { | |
60a1502a | 4743 | if (target_read_memory (ir.addr, buf, 2)) |
cf648174 HZ |
4744 | { |
4745 | if (record_debug) | |
4746 | printf_unfiltered (_("Process record: error reading " | |
4747 | "memory at addr 0x%s len = 2.\n"), | |
4748 | paddress (gdbarch, ir.addr)); | |
4749 | return -1; | |
4750 | } | |
4751 | ir.addr += 2; | |
60a1502a | 4752 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 4753 | } |
648d0c8b | 4754 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
4755 | return -1; |
4756 | } | |
7ad10968 HZ |
4757 | break; |
4758 | ||
a38bba38 | 4759 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
4760 | case 0xb1: |
4761 | case 0xb2: | |
4762 | case 0xb3: | |
4763 | case 0xb4: | |
4764 | case 0xb5: | |
4765 | case 0xb6: | |
4766 | case 0xb7: | |
cf648174 HZ |
4767 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
4768 | ? ((opcode & 0x7) | ir.rex_b) | |
4769 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
4770 | break; |
4771 | ||
a38bba38 | 4772 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
4773 | case 0xb9: |
4774 | case 0xba: | |
4775 | case 0xbb: | |
4776 | case 0xbc: | |
4777 | case 0xbd: | |
4778 | case 0xbe: | |
4779 | case 0xbf: | |
cf648174 | 4780 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
4781 | break; |
4782 | ||
a38bba38 | 4783 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
4784 | case 0x92: |
4785 | case 0x93: | |
4786 | case 0x94: | |
4787 | case 0x95: | |
4788 | case 0x96: | |
4789 | case 0x97: | |
cf648174 HZ |
4790 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4791 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
4792 | break; |
4793 | ||
a38bba38 | 4794 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
4795 | case 0x87: |
4796 | if ((opcode & 1) == 0) | |
4797 | ir.ot = OT_BYTE; | |
4798 | else | |
4799 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4800 | if (i386_record_modrm (&ir)) |
4801 | return -1; | |
7ad10968 HZ |
4802 | if (ir.mod == 3) |
4803 | { | |
86839d38 | 4804 | ir.rm |= ir.rex_b; |
cf648174 HZ |
4805 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
4806 | ir.rm &= 0x3; | |
4807 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
4808 | } |
4809 | else | |
4810 | { | |
4811 | if (i386_record_lea_modrm (&ir)) | |
4812 | return -1; | |
4813 | } | |
cf648174 HZ |
4814 | ir.reg |= rex_r; |
4815 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4816 | ir.reg &= 0x3; |
cf648174 | 4817 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4818 | break; |
4819 | ||
a38bba38 MS |
4820 | case 0xc4: /* les Gv */ |
4821 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
4822 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4823 | { | |
4824 | ir.addr -= 1; | |
4825 | goto no_support; | |
4826 | } | |
d3f323f3 | 4827 | /* FALLTHROUGH */ |
a38bba38 MS |
4828 | case 0x0fb2: /* lss Gv */ |
4829 | case 0x0fb4: /* lfs Gv */ | |
4830 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
4831 | if (i386_record_modrm (&ir)) |
4832 | return -1; | |
4833 | if (ir.mod == 3) | |
4834 | { | |
4835 | if (opcode > 0xff) | |
4836 | ir.addr -= 3; | |
4837 | else | |
4838 | ir.addr -= 2; | |
4839 | opcode = opcode << 8 | ir.modrm; | |
4840 | goto no_support; | |
4841 | } | |
7ad10968 HZ |
4842 | switch (opcode) |
4843 | { | |
a38bba38 | 4844 | case 0xc4: /* les Gv */ |
425b824a | 4845 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 4846 | break; |
a38bba38 | 4847 | case 0xc5: /* lds Gv */ |
425b824a | 4848 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 4849 | break; |
a38bba38 | 4850 | case 0x0fb2: /* lss Gv */ |
425b824a | 4851 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 4852 | break; |
a38bba38 | 4853 | case 0x0fb4: /* lfs Gv */ |
425b824a | 4854 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 4855 | break; |
a38bba38 | 4856 | case 0x0fb5: /* lgs Gv */ |
425b824a | 4857 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4858 | break; |
4859 | } | |
425b824a | 4860 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 HZ |
4861 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
4862 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4863 | break; |
4864 | ||
a38bba38 | 4865 | case 0xc0: /* shifts */ |
7ad10968 HZ |
4866 | case 0xc1: |
4867 | case 0xd0: | |
4868 | case 0xd1: | |
4869 | case 0xd2: | |
4870 | case 0xd3: | |
4871 | if ((opcode & 1) == 0) | |
4872 | ir.ot = OT_BYTE; | |
4873 | else | |
4874 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4875 | if (i386_record_modrm (&ir)) |
4876 | return -1; | |
7ad10968 HZ |
4877 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
4878 | { | |
4879 | if (i386_record_lea_modrm (&ir)) | |
4880 | return -1; | |
4881 | } | |
4882 | else | |
4883 | { | |
cf648174 HZ |
4884 | ir.rm |= ir.rex_b; |
4885 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4886 | ir.rm &= 0x3; |
cf648174 | 4887 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4888 | } |
cf648174 | 4889 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4890 | break; |
4891 | ||
4892 | case 0x0fa4: | |
4893 | case 0x0fa5: | |
4894 | case 0x0fac: | |
4895 | case 0x0fad: | |
4896 | if (i386_record_modrm (&ir)) | |
4897 | return -1; | |
4898 | if (ir.mod == 3) | |
4899 | { | |
4900 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4901 | return -1; | |
4902 | } | |
4903 | else | |
4904 | { | |
4905 | if (i386_record_lea_modrm (&ir)) | |
4906 | return -1; | |
4907 | } | |
4908 | break; | |
4909 | ||
a38bba38 | 4910 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
4911 | case 0xd9: |
4912 | case 0xda: | |
4913 | case 0xdb: | |
4914 | case 0xdc: | |
4915 | case 0xdd: | |
4916 | case 0xde: | |
4917 | case 0xdf: | |
4918 | if (i386_record_modrm (&ir)) | |
4919 | return -1; | |
4920 | ir.reg |= ((opcode & 7) << 3); | |
4921 | if (ir.mod != 3) | |
4922 | { | |
1777feb0 | 4923 | /* Memory. */ |
955db0c0 | 4924 | uint64_t addr64; |
7ad10968 | 4925 | |
955db0c0 | 4926 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
4927 | return -1; |
4928 | switch (ir.reg) | |
4929 | { | |
7ad10968 | 4930 | case 0x02: |
0289bdd7 MS |
4931 | case 0x12: |
4932 | case 0x22: | |
4933 | case 0x32: | |
4934 | /* For fcom, ficom nothing to do. */ | |
4935 | break; | |
7ad10968 | 4936 | case 0x03: |
0289bdd7 MS |
4937 | case 0x13: |
4938 | case 0x23: | |
4939 | case 0x33: | |
4940 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
4941 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4942 | return -1; | |
4943 | break; | |
4944 | case 0x00: | |
4945 | case 0x01: | |
7ad10968 HZ |
4946 | case 0x04: |
4947 | case 0x05: | |
4948 | case 0x06: | |
4949 | case 0x07: | |
4950 | case 0x10: | |
4951 | case 0x11: | |
7ad10968 HZ |
4952 | case 0x14: |
4953 | case 0x15: | |
4954 | case 0x16: | |
4955 | case 0x17: | |
4956 | case 0x20: | |
4957 | case 0x21: | |
7ad10968 HZ |
4958 | case 0x24: |
4959 | case 0x25: | |
4960 | case 0x26: | |
4961 | case 0x27: | |
4962 | case 0x30: | |
4963 | case 0x31: | |
7ad10968 HZ |
4964 | case 0x34: |
4965 | case 0x35: | |
4966 | case 0x36: | |
4967 | case 0x37: | |
0289bdd7 MS |
4968 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
4969 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
4970 | of code, always affects st(0) register. */ | |
4971 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4972 | return -1; | |
7ad10968 HZ |
4973 | break; |
4974 | case 0x08: | |
4975 | case 0x0a: | |
4976 | case 0x0b: | |
4977 | case 0x18: | |
4978 | case 0x19: | |
4979 | case 0x1a: | |
4980 | case 0x1b: | |
0289bdd7 | 4981 | case 0x1d: |
7ad10968 HZ |
4982 | case 0x28: |
4983 | case 0x29: | |
4984 | case 0x2a: | |
4985 | case 0x2b: | |
4986 | case 0x38: | |
4987 | case 0x39: | |
4988 | case 0x3a: | |
4989 | case 0x3b: | |
0289bdd7 MS |
4990 | case 0x3c: |
4991 | case 0x3d: | |
7ad10968 HZ |
4992 | switch (ir.reg & 7) |
4993 | { | |
4994 | case 0: | |
0289bdd7 MS |
4995 | /* Handling fld, fild. */ |
4996 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4997 | return -1; | |
7ad10968 HZ |
4998 | break; |
4999 | case 1: | |
5000 | switch (ir.reg >> 4) | |
5001 | { | |
5002 | case 0: | |
955db0c0 | 5003 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
5004 | return -1; |
5005 | break; | |
5006 | case 2: | |
955db0c0 | 5007 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
5008 | return -1; |
5009 | break; | |
5010 | case 3: | |
0289bdd7 | 5011 | break; |
7ad10968 | 5012 | default: |
955db0c0 | 5013 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5014 | return -1; |
5015 | break; | |
5016 | } | |
5017 | break; | |
5018 | default: | |
5019 | switch (ir.reg >> 4) | |
5020 | { | |
5021 | case 0: | |
955db0c0 | 5022 | if (record_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
5023 | return -1; |
5024 | if (3 == (ir.reg & 7)) | |
5025 | { | |
5026 | /* For fstp m32fp. */ | |
5027 | if (i386_record_floats (gdbarch, &ir, | |
5028 | I386_SAVE_FPU_REGS)) | |
5029 | return -1; | |
5030 | } | |
5031 | break; | |
7ad10968 | 5032 | case 1: |
955db0c0 | 5033 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 | 5034 | return -1; |
0289bdd7 MS |
5035 | if ((3 == (ir.reg & 7)) |
5036 | || (5 == (ir.reg & 7)) | |
5037 | || (7 == (ir.reg & 7))) | |
5038 | { | |
5039 | /* For fstp insn. */ | |
5040 | if (i386_record_floats (gdbarch, &ir, | |
5041 | I386_SAVE_FPU_REGS)) | |
5042 | return -1; | |
5043 | } | |
7ad10968 HZ |
5044 | break; |
5045 | case 2: | |
955db0c0 | 5046 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5047 | return -1; |
0289bdd7 MS |
5048 | if (3 == (ir.reg & 7)) |
5049 | { | |
5050 | /* For fstp m64fp. */ | |
5051 | if (i386_record_floats (gdbarch, &ir, | |
5052 | I386_SAVE_FPU_REGS)) | |
5053 | return -1; | |
5054 | } | |
7ad10968 HZ |
5055 | break; |
5056 | case 3: | |
0289bdd7 MS |
5057 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
5058 | { | |
5059 | /* For fistp, fbld, fild, fbstp. */ | |
5060 | if (i386_record_floats (gdbarch, &ir, | |
5061 | I386_SAVE_FPU_REGS)) | |
5062 | return -1; | |
5063 | } | |
5064 | /* Fall through */ | |
7ad10968 | 5065 | default: |
955db0c0 | 5066 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5067 | return -1; |
5068 | break; | |
5069 | } | |
5070 | break; | |
5071 | } | |
5072 | break; | |
5073 | case 0x0c: | |
0289bdd7 MS |
5074 | /* Insn fldenv. */ |
5075 | if (i386_record_floats (gdbarch, &ir, | |
5076 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5077 | return -1; | |
5078 | break; | |
7ad10968 | 5079 | case 0x0d: |
0289bdd7 MS |
5080 | /* Insn fldcw. */ |
5081 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
5082 | return -1; | |
5083 | break; | |
7ad10968 | 5084 | case 0x2c: |
0289bdd7 MS |
5085 | /* Insn frstor. */ |
5086 | if (i386_record_floats (gdbarch, &ir, | |
5087 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5088 | return -1; | |
7ad10968 HZ |
5089 | break; |
5090 | case 0x0e: | |
5091 | if (ir.dflag) | |
5092 | { | |
955db0c0 | 5093 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
5094 | return -1; |
5095 | } | |
5096 | else | |
5097 | { | |
955db0c0 | 5098 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
5099 | return -1; |
5100 | } | |
5101 | break; | |
5102 | case 0x0f: | |
5103 | case 0x2f: | |
955db0c0 | 5104 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5105 | return -1; |
0289bdd7 MS |
5106 | /* Insn fstp, fbstp. */ |
5107 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5108 | return -1; | |
7ad10968 HZ |
5109 | break; |
5110 | case 0x1f: | |
5111 | case 0x3e: | |
955db0c0 | 5112 | if (record_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
5113 | return -1; |
5114 | break; | |
5115 | case 0x2e: | |
5116 | if (ir.dflag) | |
5117 | { | |
955db0c0 | 5118 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 | 5119 | return -1; |
955db0c0 | 5120 | addr64 += 28; |
7ad10968 HZ |
5121 | } |
5122 | else | |
5123 | { | |
955db0c0 | 5124 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 | 5125 | return -1; |
955db0c0 | 5126 | addr64 += 14; |
7ad10968 | 5127 | } |
955db0c0 | 5128 | if (record_arch_list_add_mem (addr64, 80)) |
7ad10968 | 5129 | return -1; |
0289bdd7 MS |
5130 | /* Insn fsave. */ |
5131 | if (i386_record_floats (gdbarch, &ir, | |
5132 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5133 | return -1; | |
7ad10968 HZ |
5134 | break; |
5135 | case 0x3f: | |
955db0c0 | 5136 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5137 | return -1; |
0289bdd7 MS |
5138 | /* Insn fistp. */ |
5139 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5140 | return -1; | |
7ad10968 HZ |
5141 | break; |
5142 | default: | |
5143 | ir.addr -= 2; | |
5144 | opcode = opcode << 8 | ir.modrm; | |
5145 | goto no_support; | |
5146 | break; | |
5147 | } | |
5148 | } | |
0289bdd7 MS |
5149 | /* Opcode is an extension of modR/M byte. */ |
5150 | else | |
5151 | { | |
5152 | switch (opcode) | |
5153 | { | |
5154 | case 0xd8: | |
5155 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5156 | return -1; | |
5157 | break; | |
5158 | case 0xd9: | |
5159 | if (0x0c == (ir.modrm >> 4)) | |
5160 | { | |
5161 | if ((ir.modrm & 0x0f) <= 7) | |
5162 | { | |
5163 | if (i386_record_floats (gdbarch, &ir, | |
5164 | I386_SAVE_FPU_REGS)) | |
5165 | return -1; | |
5166 | } | |
5167 | else | |
5168 | { | |
5169 | if (i386_record_floats (gdbarch, &ir, | |
5170 | I387_ST0_REGNUM (tdep))) | |
5171 | return -1; | |
5172 | /* If only st(0) is changing, then we have already | |
5173 | recorded. */ | |
5174 | if ((ir.modrm & 0x0f) - 0x08) | |
5175 | { | |
5176 | if (i386_record_floats (gdbarch, &ir, | |
5177 | I387_ST0_REGNUM (tdep) + | |
5178 | ((ir.modrm & 0x0f) - 0x08))) | |
5179 | return -1; | |
5180 | } | |
5181 | } | |
5182 | } | |
5183 | else | |
5184 | { | |
5185 | switch (ir.modrm) | |
5186 | { | |
5187 | case 0xe0: | |
5188 | case 0xe1: | |
5189 | case 0xf0: | |
5190 | case 0xf5: | |
5191 | case 0xf8: | |
5192 | case 0xfa: | |
5193 | case 0xfc: | |
5194 | case 0xfe: | |
5195 | case 0xff: | |
5196 | if (i386_record_floats (gdbarch, &ir, | |
5197 | I387_ST0_REGNUM (tdep))) | |
5198 | return -1; | |
5199 | break; | |
5200 | case 0xf1: | |
5201 | case 0xf2: | |
5202 | case 0xf3: | |
5203 | case 0xf4: | |
5204 | case 0xf6: | |
5205 | case 0xf7: | |
5206 | case 0xe8: | |
5207 | case 0xe9: | |
5208 | case 0xea: | |
5209 | case 0xeb: | |
5210 | case 0xec: | |
5211 | case 0xed: | |
5212 | case 0xee: | |
5213 | case 0xf9: | |
5214 | case 0xfb: | |
5215 | if (i386_record_floats (gdbarch, &ir, | |
5216 | I386_SAVE_FPU_REGS)) | |
5217 | return -1; | |
5218 | break; | |
5219 | case 0xfd: | |
5220 | if (i386_record_floats (gdbarch, &ir, | |
5221 | I387_ST0_REGNUM (tdep))) | |
5222 | return -1; | |
5223 | if (i386_record_floats (gdbarch, &ir, | |
5224 | I387_ST0_REGNUM (tdep) + 1)) | |
5225 | return -1; | |
5226 | break; | |
5227 | } | |
5228 | } | |
5229 | break; | |
5230 | case 0xda: | |
5231 | if (0xe9 == ir.modrm) | |
5232 | { | |
5233 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5234 | return -1; | |
5235 | } | |
5236 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5237 | { | |
5238 | if (i386_record_floats (gdbarch, &ir, | |
5239 | I387_ST0_REGNUM (tdep))) | |
5240 | return -1; | |
5241 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5242 | { | |
5243 | if (i386_record_floats (gdbarch, &ir, | |
5244 | I387_ST0_REGNUM (tdep) + | |
5245 | (ir.modrm & 0x0f))) | |
5246 | return -1; | |
5247 | } | |
5248 | else if ((ir.modrm & 0x0f) - 0x08) | |
5249 | { | |
5250 | if (i386_record_floats (gdbarch, &ir, | |
5251 | I387_ST0_REGNUM (tdep) + | |
5252 | ((ir.modrm & 0x0f) - 0x08))) | |
5253 | return -1; | |
5254 | } | |
5255 | } | |
5256 | break; | |
5257 | case 0xdb: | |
5258 | if (0xe3 == ir.modrm) | |
5259 | { | |
5260 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
5261 | return -1; | |
5262 | } | |
5263 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5264 | { | |
5265 | if (i386_record_floats (gdbarch, &ir, | |
5266 | I387_ST0_REGNUM (tdep))) | |
5267 | return -1; | |
5268 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5269 | { | |
5270 | if (i386_record_floats (gdbarch, &ir, | |
5271 | I387_ST0_REGNUM (tdep) + | |
5272 | (ir.modrm & 0x0f))) | |
5273 | return -1; | |
5274 | } | |
5275 | else if ((ir.modrm & 0x0f) - 0x08) | |
5276 | { | |
5277 | if (i386_record_floats (gdbarch, &ir, | |
5278 | I387_ST0_REGNUM (tdep) + | |
5279 | ((ir.modrm & 0x0f) - 0x08))) | |
5280 | return -1; | |
5281 | } | |
5282 | } | |
5283 | break; | |
5284 | case 0xdc: | |
5285 | if ((0x0c == ir.modrm >> 4) | |
5286 | || (0x0d == ir.modrm >> 4) | |
5287 | || (0x0f == ir.modrm >> 4)) | |
5288 | { | |
5289 | if ((ir.modrm & 0x0f) <= 7) | |
5290 | { | |
5291 | if (i386_record_floats (gdbarch, &ir, | |
5292 | I387_ST0_REGNUM (tdep) + | |
5293 | (ir.modrm & 0x0f))) | |
5294 | return -1; | |
5295 | } | |
5296 | else | |
5297 | { | |
5298 | if (i386_record_floats (gdbarch, &ir, | |
5299 | I387_ST0_REGNUM (tdep) + | |
5300 | ((ir.modrm & 0x0f) - 0x08))) | |
5301 | return -1; | |
5302 | } | |
5303 | } | |
5304 | break; | |
5305 | case 0xdd: | |
5306 | if (0x0c == ir.modrm >> 4) | |
5307 | { | |
5308 | if (i386_record_floats (gdbarch, &ir, | |
5309 | I387_FTAG_REGNUM (tdep))) | |
5310 | return -1; | |
5311 | } | |
5312 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5313 | { | |
5314 | if ((ir.modrm & 0x0f) <= 7) | |
5315 | { | |
5316 | if (i386_record_floats (gdbarch, &ir, | |
5317 | I387_ST0_REGNUM (tdep) + | |
5318 | (ir.modrm & 0x0f))) | |
5319 | return -1; | |
5320 | } | |
5321 | else | |
5322 | { | |
5323 | if (i386_record_floats (gdbarch, &ir, | |
5324 | I386_SAVE_FPU_REGS)) | |
5325 | return -1; | |
5326 | } | |
5327 | } | |
5328 | break; | |
5329 | case 0xde: | |
5330 | if ((0x0c == ir.modrm >> 4) | |
5331 | || (0x0e == ir.modrm >> 4) | |
5332 | || (0x0f == ir.modrm >> 4) | |
5333 | || (0xd9 == ir.modrm)) | |
5334 | { | |
5335 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5336 | return -1; | |
5337 | } | |
5338 | break; | |
5339 | case 0xdf: | |
5340 | if (0xe0 == ir.modrm) | |
5341 | { | |
5342 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
5343 | return -1; | |
5344 | } | |
5345 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5346 | { | |
5347 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5348 | return -1; | |
5349 | } | |
5350 | break; | |
5351 | } | |
5352 | } | |
7ad10968 | 5353 | break; |
7ad10968 | 5354 | /* string ops */ |
a38bba38 | 5355 | case 0xa4: /* movsS */ |
7ad10968 | 5356 | case 0xa5: |
a38bba38 | 5357 | case 0xaa: /* stosS */ |
7ad10968 | 5358 | case 0xab: |
a38bba38 | 5359 | case 0x6c: /* insS */ |
7ad10968 | 5360 | case 0x6d: |
cf648174 | 5361 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 5362 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
5363 | &addr); |
5364 | if (addr) | |
cf648174 | 5365 | { |
77d7dc92 HZ |
5366 | ULONGEST es, ds; |
5367 | ||
5368 | if ((opcode & 1) == 0) | |
5369 | ir.ot = OT_BYTE; | |
5370 | else | |
5371 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
5372 | regcache_raw_read_unsigned (ir.regcache, |
5373 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 5374 | &addr); |
77d7dc92 | 5375 | |
d7877f7e HZ |
5376 | regcache_raw_read_unsigned (ir.regcache, |
5377 | ir.regmap[X86_RECORD_ES_REGNUM], | |
5378 | &es); | |
5379 | regcache_raw_read_unsigned (ir.regcache, | |
5380 | ir.regmap[X86_RECORD_DS_REGNUM], | |
5381 | &ds); | |
5382 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
5383 | { |
5384 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
bb08c432 HZ |
5385 | if (record_memory_query) |
5386 | { | |
5387 | int q; | |
5388 | ||
5389 | target_terminal_ours (); | |
5390 | q = yquery (_("\ | |
5391 | Process record ignores the memory change of instruction at address %s\n\ | |
5392 | because it can't get the value of the segment register.\n\ | |
5393 | Do you want to stop the program?"), | |
5394 | paddress (gdbarch, ir.orig_addr)); | |
5395 | target_terminal_inferior (); | |
5396 | if (q) | |
5397 | return -1; | |
5398 | } | |
df61f520 HZ |
5399 | } |
5400 | else | |
5401 | { | |
648d0c8b | 5402 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 5403 | return -1; |
77d7dc92 HZ |
5404 | } |
5405 | ||
5406 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5407 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
5408 | if (opcode == 0xa4 || opcode == 0xa5) |
5409 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5410 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5411 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5412 | } | |
cf648174 | 5413 | break; |
7ad10968 | 5414 | |
a38bba38 | 5415 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
5416 | case 0xa7: |
5417 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5418 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5419 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5420 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5421 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5422 | break; |
5423 | ||
a38bba38 | 5424 | case 0xac: /* lodsS */ |
7ad10968 | 5425 | case 0xad: |
cf648174 HZ |
5426 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5427 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5428 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5429 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5430 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5431 | break; |
5432 | ||
a38bba38 | 5433 | case 0xae: /* scasS */ |
7ad10968 | 5434 | case 0xaf: |
cf648174 | 5435 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 5436 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5437 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5438 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5439 | break; |
5440 | ||
a38bba38 | 5441 | case 0x6e: /* outsS */ |
cf648174 HZ |
5442 | case 0x6f: |
5443 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5444 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5445 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5446 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5447 | break; |
5448 | ||
a38bba38 | 5449 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
5450 | case 0xe5: |
5451 | case 0xec: | |
5452 | case 0xed: | |
cf648174 HZ |
5453 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5454 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5455 | break; |
5456 | ||
5457 | case 0xe6: | |
5458 | case 0xe7: | |
5459 | case 0xee: | |
5460 | case 0xef: | |
5461 | break; | |
5462 | ||
5463 | /* control */ | |
a38bba38 MS |
5464 | case 0xc2: /* ret im */ |
5465 | case 0xc3: /* ret */ | |
cf648174 HZ |
5466 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5467 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5468 | break; | |
5469 | ||
a38bba38 MS |
5470 | case 0xca: /* lret im */ |
5471 | case 0xcb: /* lret */ | |
5472 | case 0xcf: /* iret */ | |
cf648174 HZ |
5473 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
5474 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
5475 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5476 | break; |
5477 | ||
a38bba38 | 5478 | case 0xe8: /* call im */ |
cf648174 HZ |
5479 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5480 | ir.dflag = 2; | |
5481 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5482 | return -1; | |
7ad10968 HZ |
5483 | break; |
5484 | ||
a38bba38 | 5485 | case 0x9a: /* lcall im */ |
cf648174 HZ |
5486 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5487 | { | |
5488 | ir.addr -= 1; | |
5489 | goto no_support; | |
5490 | } | |
5491 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
5492 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5493 | return -1; | |
7ad10968 HZ |
5494 | break; |
5495 | ||
a38bba38 MS |
5496 | case 0xe9: /* jmp im */ |
5497 | case 0xea: /* ljmp im */ | |
5498 | case 0xeb: /* jmp Jb */ | |
5499 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
5500 | case 0x71: |
5501 | case 0x72: | |
5502 | case 0x73: | |
5503 | case 0x74: | |
5504 | case 0x75: | |
5505 | case 0x76: | |
5506 | case 0x77: | |
5507 | case 0x78: | |
5508 | case 0x79: | |
5509 | case 0x7a: | |
5510 | case 0x7b: | |
5511 | case 0x7c: | |
5512 | case 0x7d: | |
5513 | case 0x7e: | |
5514 | case 0x7f: | |
a38bba38 | 5515 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
5516 | case 0x0f81: |
5517 | case 0x0f82: | |
5518 | case 0x0f83: | |
5519 | case 0x0f84: | |
5520 | case 0x0f85: | |
5521 | case 0x0f86: | |
5522 | case 0x0f87: | |
5523 | case 0x0f88: | |
5524 | case 0x0f89: | |
5525 | case 0x0f8a: | |
5526 | case 0x0f8b: | |
5527 | case 0x0f8c: | |
5528 | case 0x0f8d: | |
5529 | case 0x0f8e: | |
5530 | case 0x0f8f: | |
5531 | break; | |
5532 | ||
a38bba38 | 5533 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
5534 | case 0x0f91: |
5535 | case 0x0f92: | |
5536 | case 0x0f93: | |
5537 | case 0x0f94: | |
5538 | case 0x0f95: | |
5539 | case 0x0f96: | |
5540 | case 0x0f97: | |
5541 | case 0x0f98: | |
5542 | case 0x0f99: | |
5543 | case 0x0f9a: | |
5544 | case 0x0f9b: | |
5545 | case 0x0f9c: | |
5546 | case 0x0f9d: | |
5547 | case 0x0f9e: | |
5548 | case 0x0f9f: | |
cf648174 | 5549 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5550 | ir.ot = OT_BYTE; |
5551 | if (i386_record_modrm (&ir)) | |
5552 | return -1; | |
5553 | if (ir.mod == 3) | |
cf648174 HZ |
5554 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
5555 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
5556 | else |
5557 | { | |
5558 | if (i386_record_lea_modrm (&ir)) | |
5559 | return -1; | |
5560 | } | |
5561 | break; | |
5562 | ||
a38bba38 | 5563 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
5564 | case 0x0f41: |
5565 | case 0x0f42: | |
5566 | case 0x0f43: | |
5567 | case 0x0f44: | |
5568 | case 0x0f45: | |
5569 | case 0x0f46: | |
5570 | case 0x0f47: | |
5571 | case 0x0f48: | |
5572 | case 0x0f49: | |
5573 | case 0x0f4a: | |
5574 | case 0x0f4b: | |
5575 | case 0x0f4c: | |
5576 | case 0x0f4d: | |
5577 | case 0x0f4e: | |
5578 | case 0x0f4f: | |
5579 | if (i386_record_modrm (&ir)) | |
5580 | return -1; | |
cf648174 | 5581 | ir.reg |= rex_r; |
7ad10968 HZ |
5582 | if (ir.dflag == OT_BYTE) |
5583 | ir.reg &= 0x3; | |
cf648174 | 5584 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5585 | break; |
5586 | ||
5587 | /* flags */ | |
a38bba38 | 5588 | case 0x9c: /* pushf */ |
cf648174 HZ |
5589 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5590 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
5591 | ir.dflag = 2; | |
5592 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5593 | return -1; | |
7ad10968 HZ |
5594 | break; |
5595 | ||
a38bba38 | 5596 | case 0x9d: /* popf */ |
cf648174 HZ |
5597 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5598 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5599 | break; |
5600 | ||
a38bba38 | 5601 | case 0x9e: /* sahf */ |
cf648174 HZ |
5602 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5603 | { | |
5604 | ir.addr -= 1; | |
5605 | goto no_support; | |
5606 | } | |
d3f323f3 | 5607 | /* FALLTHROUGH */ |
a38bba38 MS |
5608 | case 0xf5: /* cmc */ |
5609 | case 0xf8: /* clc */ | |
5610 | case 0xf9: /* stc */ | |
5611 | case 0xfc: /* cld */ | |
5612 | case 0xfd: /* std */ | |
cf648174 | 5613 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5614 | break; |
5615 | ||
a38bba38 | 5616 | case 0x9f: /* lahf */ |
cf648174 HZ |
5617 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5618 | { | |
5619 | ir.addr -= 1; | |
5620 | goto no_support; | |
5621 | } | |
5622 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5623 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5624 | break; |
5625 | ||
5626 | /* bit operations */ | |
a38bba38 | 5627 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
5628 | ir.ot = ir.dflag + OT_WORD; |
5629 | if (i386_record_modrm (&ir)) | |
5630 | return -1; | |
5631 | if (ir.reg < 4) | |
5632 | { | |
cf648174 | 5633 | ir.addr -= 2; |
7ad10968 HZ |
5634 | opcode = opcode << 8 | ir.modrm; |
5635 | goto no_support; | |
5636 | } | |
cf648174 | 5637 | if (ir.reg != 4) |
7ad10968 | 5638 | { |
cf648174 HZ |
5639 | if (ir.mod == 3) |
5640 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
5641 | else |
5642 | { | |
cf648174 | 5643 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
5644 | return -1; |
5645 | } | |
5646 | } | |
cf648174 | 5647 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5648 | break; |
5649 | ||
a38bba38 | 5650 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
5651 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5652 | break; | |
5653 | ||
a38bba38 MS |
5654 | case 0x0fab: /* bts */ |
5655 | case 0x0fb3: /* btr */ | |
5656 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
5657 | ir.ot = ir.dflag + OT_WORD; |
5658 | if (i386_record_modrm (&ir)) | |
5659 | return -1; | |
5660 | if (ir.mod == 3) | |
5661 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
5662 | else | |
5663 | { | |
955db0c0 MS |
5664 | uint64_t addr64; |
5665 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
5666 | return -1; |
5667 | regcache_raw_read_unsigned (ir.regcache, | |
5668 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 5669 | &addr); |
cf648174 HZ |
5670 | switch (ir.dflag) |
5671 | { | |
5672 | case 0: | |
648d0c8b | 5673 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
5674 | break; |
5675 | case 1: | |
648d0c8b | 5676 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
5677 | break; |
5678 | case 2: | |
648d0c8b | 5679 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
5680 | break; |
5681 | } | |
955db0c0 | 5682 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
5683 | return -1; |
5684 | if (i386_record_lea_modrm (&ir)) | |
5685 | return -1; | |
5686 | } | |
5687 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5688 | break; |
5689 | ||
a38bba38 MS |
5690 | case 0x0fbc: /* bsf */ |
5691 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
5692 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5693 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5694 | break; |
5695 | ||
5696 | /* bcd */ | |
a38bba38 MS |
5697 | case 0x27: /* daa */ |
5698 | case 0x2f: /* das */ | |
5699 | case 0x37: /* aaa */ | |
5700 | case 0x3f: /* aas */ | |
5701 | case 0xd4: /* aam */ | |
5702 | case 0xd5: /* aad */ | |
cf648174 HZ |
5703 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5704 | { | |
5705 | ir.addr -= 1; | |
5706 | goto no_support; | |
5707 | } | |
5708 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5709 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5710 | break; |
5711 | ||
5712 | /* misc */ | |
a38bba38 | 5713 | case 0x90: /* nop */ |
7ad10968 HZ |
5714 | if (prefixes & PREFIX_LOCK) |
5715 | { | |
5716 | ir.addr -= 1; | |
5717 | goto no_support; | |
5718 | } | |
5719 | break; | |
5720 | ||
a38bba38 | 5721 | case 0x9b: /* fwait */ |
425b824a | 5722 | if (target_read_memory (ir.addr, &opcode8, 1)) |
0289bdd7 MS |
5723 | { |
5724 | if (record_debug) | |
5725 | printf_unfiltered (_("Process record: error reading memory at " | |
5726 | "addr 0x%s len = 1.\n"), | |
5727 | paddress (gdbarch, ir.addr)); | |
5728 | return -1; | |
5729 | } | |
425b824a | 5730 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
5731 | ir.addr++; |
5732 | goto reswitch; | |
7ad10968 HZ |
5733 | break; |
5734 | ||
7ad10968 | 5735 | /* XXX */ |
a38bba38 | 5736 | case 0xcc: /* int3 */ |
a3c4230a | 5737 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
5738 | "int3.\n")); |
5739 | ir.addr -= 1; | |
5740 | goto no_support; | |
5741 | break; | |
5742 | ||
7ad10968 | 5743 | /* XXX */ |
a38bba38 | 5744 | case 0xcd: /* int */ |
7ad10968 HZ |
5745 | { |
5746 | int ret; | |
425b824a MS |
5747 | uint8_t interrupt; |
5748 | if (target_read_memory (ir.addr, &interrupt, 1)) | |
7ad10968 HZ |
5749 | { |
5750 | if (record_debug) | |
5751 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
5752 | "at addr %s len = 1.\n"), |
5753 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5754 | return -1; |
5755 | } | |
5756 | ir.addr++; | |
425b824a | 5757 | if (interrupt != 0x80 |
a3c4230a | 5758 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 5759 | { |
a3c4230a | 5760 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 5761 | "instruction int 0x%02x.\n"), |
425b824a | 5762 | interrupt); |
7ad10968 HZ |
5763 | ir.addr -= 2; |
5764 | goto no_support; | |
5765 | } | |
a3c4230a | 5766 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
5767 | if (ret) |
5768 | return ret; | |
5769 | } | |
5770 | break; | |
5771 | ||
7ad10968 | 5772 | /* XXX */ |
a38bba38 | 5773 | case 0xce: /* into */ |
a3c4230a | 5774 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5775 | "instruction into.\n")); |
5776 | ir.addr -= 1; | |
5777 | goto no_support; | |
5778 | break; | |
5779 | ||
a38bba38 MS |
5780 | case 0xfa: /* cli */ |
5781 | case 0xfb: /* sti */ | |
7ad10968 HZ |
5782 | break; |
5783 | ||
a38bba38 | 5784 | case 0x62: /* bound */ |
a3c4230a | 5785 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5786 | "instruction bound.\n")); |
5787 | ir.addr -= 1; | |
5788 | goto no_support; | |
5789 | break; | |
5790 | ||
a38bba38 | 5791 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
5792 | case 0x0fc9: |
5793 | case 0x0fca: | |
5794 | case 0x0fcb: | |
5795 | case 0x0fcc: | |
5796 | case 0x0fcd: | |
5797 | case 0x0fce: | |
5798 | case 0x0fcf: | |
cf648174 | 5799 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
5800 | break; |
5801 | ||
a38bba38 | 5802 | case 0xd6: /* salc */ |
cf648174 HZ |
5803 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5804 | { | |
5805 | ir.addr -= 1; | |
5806 | goto no_support; | |
5807 | } | |
5808 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5809 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5810 | break; |
5811 | ||
a38bba38 MS |
5812 | case 0xe0: /* loopnz */ |
5813 | case 0xe1: /* loopz */ | |
5814 | case 0xe2: /* loop */ | |
5815 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
5816 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5817 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5818 | break; |
5819 | ||
a38bba38 | 5820 | case 0x0f30: /* wrmsr */ |
a3c4230a | 5821 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5822 | "instruction wrmsr.\n")); |
5823 | ir.addr -= 2; | |
5824 | goto no_support; | |
5825 | break; | |
5826 | ||
a38bba38 | 5827 | case 0x0f32: /* rdmsr */ |
a3c4230a | 5828 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5829 | "instruction rdmsr.\n")); |
5830 | ir.addr -= 2; | |
5831 | goto no_support; | |
5832 | break; | |
5833 | ||
a38bba38 | 5834 | case 0x0f31: /* rdtsc */ |
f8c4f480 HZ |
5835 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5836 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5837 | break; |
5838 | ||
a38bba38 | 5839 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
5840 | { |
5841 | int ret; | |
cf648174 HZ |
5842 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5843 | { | |
5844 | ir.addr -= 2; | |
5845 | goto no_support; | |
5846 | } | |
a3c4230a | 5847 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 5848 | { |
a3c4230a | 5849 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5850 | "instruction sysenter.\n")); |
5851 | ir.addr -= 2; | |
5852 | goto no_support; | |
5853 | } | |
a3c4230a | 5854 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
5855 | if (ret) |
5856 | return ret; | |
5857 | } | |
5858 | break; | |
5859 | ||
a38bba38 | 5860 | case 0x0f35: /* sysexit */ |
a3c4230a | 5861 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5862 | "instruction sysexit.\n")); |
5863 | ir.addr -= 2; | |
5864 | goto no_support; | |
5865 | break; | |
5866 | ||
a38bba38 | 5867 | case 0x0f05: /* syscall */ |
cf648174 HZ |
5868 | { |
5869 | int ret; | |
a3c4230a | 5870 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 5871 | { |
a3c4230a | 5872 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
5873 | "instruction syscall.\n")); |
5874 | ir.addr -= 2; | |
5875 | goto no_support; | |
5876 | } | |
a3c4230a | 5877 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
5878 | if (ret) |
5879 | return ret; | |
5880 | } | |
5881 | break; | |
5882 | ||
a38bba38 | 5883 | case 0x0f07: /* sysret */ |
a3c4230a | 5884 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
5885 | "instruction sysret.\n")); |
5886 | ir.addr -= 2; | |
5887 | goto no_support; | |
5888 | break; | |
5889 | ||
a38bba38 | 5890 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
5891 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5892 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5893 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5894 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
5895 | break; |
5896 | ||
a38bba38 | 5897 | case 0xf4: /* hlt */ |
a3c4230a | 5898 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5899 | "instruction hlt.\n")); |
5900 | ir.addr -= 1; | |
5901 | goto no_support; | |
5902 | break; | |
5903 | ||
5904 | case 0x0f00: | |
5905 | if (i386_record_modrm (&ir)) | |
5906 | return -1; | |
5907 | switch (ir.reg) | |
5908 | { | |
a38bba38 MS |
5909 | case 0: /* sldt */ |
5910 | case 1: /* str */ | |
7ad10968 | 5911 | if (ir.mod == 3) |
cf648174 | 5912 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5913 | else |
5914 | { | |
5915 | ir.ot = OT_WORD; | |
5916 | if (i386_record_lea_modrm (&ir)) | |
5917 | return -1; | |
5918 | } | |
5919 | break; | |
a38bba38 MS |
5920 | case 2: /* lldt */ |
5921 | case 3: /* ltr */ | |
7ad10968 | 5922 | break; |
a38bba38 MS |
5923 | case 4: /* verr */ |
5924 | case 5: /* verw */ | |
cf648174 | 5925 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5926 | break; |
5927 | default: | |
5928 | ir.addr -= 3; | |
5929 | opcode = opcode << 8 | ir.modrm; | |
5930 | goto no_support; | |
5931 | break; | |
5932 | } | |
5933 | break; | |
5934 | ||
5935 | case 0x0f01: | |
5936 | if (i386_record_modrm (&ir)) | |
5937 | return -1; | |
5938 | switch (ir.reg) | |
5939 | { | |
a38bba38 | 5940 | case 0: /* sgdt */ |
7ad10968 | 5941 | { |
955db0c0 | 5942 | uint64_t addr64; |
7ad10968 HZ |
5943 | |
5944 | if (ir.mod == 3) | |
5945 | { | |
5946 | ir.addr -= 3; | |
5947 | opcode = opcode << 8 | ir.modrm; | |
5948 | goto no_support; | |
5949 | } | |
d7877f7e | 5950 | if (ir.override >= 0) |
7ad10968 | 5951 | { |
bb08c432 HZ |
5952 | if (record_memory_query) |
5953 | { | |
5954 | int q; | |
5955 | ||
5956 | target_terminal_ours (); | |
5957 | q = yquery (_("\ | |
5958 | Process record ignores the memory change of instruction at address %s\n\ | |
5959 | because it can't get the value of the segment register.\n\ | |
5960 | Do you want to stop the program?"), | |
5961 | paddress (gdbarch, ir.orig_addr)); | |
5962 | target_terminal_inferior (); | |
5963 | if (q) | |
5964 | return -1; | |
5965 | } | |
7ad10968 HZ |
5966 | } |
5967 | else | |
5968 | { | |
955db0c0 | 5969 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 5970 | return -1; |
955db0c0 | 5971 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5972 | return -1; |
955db0c0 | 5973 | addr64 += 2; |
cf648174 HZ |
5974 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5975 | { | |
955db0c0 | 5976 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
5977 | return -1; |
5978 | } | |
5979 | else | |
5980 | { | |
955db0c0 | 5981 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
5982 | return -1; |
5983 | } | |
7ad10968 HZ |
5984 | } |
5985 | } | |
5986 | break; | |
5987 | case 1: | |
5988 | if (ir.mod == 3) | |
5989 | { | |
5990 | switch (ir.rm) | |
5991 | { | |
a38bba38 | 5992 | case 0: /* monitor */ |
7ad10968 | 5993 | break; |
a38bba38 | 5994 | case 1: /* mwait */ |
cf648174 | 5995 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5996 | break; |
5997 | default: | |
5998 | ir.addr -= 3; | |
5999 | opcode = opcode << 8 | ir.modrm; | |
6000 | goto no_support; | |
6001 | break; | |
6002 | } | |
6003 | } | |
6004 | else | |
6005 | { | |
6006 | /* sidt */ | |
d7877f7e | 6007 | if (ir.override >= 0) |
7ad10968 | 6008 | { |
bb08c432 HZ |
6009 | if (record_memory_query) |
6010 | { | |
6011 | int q; | |
6012 | ||
6013 | target_terminal_ours (); | |
6014 | q = yquery (_("\ | |
6015 | Process record ignores the memory change of instruction at address %s\n\ | |
6016 | because it can't get the value of the segment register.\n\ | |
6017 | Do you want to stop the program?"), | |
6018 | paddress (gdbarch, ir.orig_addr)); | |
6019 | target_terminal_inferior (); | |
6020 | if (q) | |
6021 | return -1; | |
6022 | } | |
7ad10968 HZ |
6023 | } |
6024 | else | |
6025 | { | |
955db0c0 | 6026 | uint64_t addr64; |
7ad10968 | 6027 | |
955db0c0 | 6028 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6029 | return -1; |
955db0c0 | 6030 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6031 | return -1; |
955db0c0 | 6032 | addr64 += 2; |
cf648174 HZ |
6033 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6034 | { | |
955db0c0 | 6035 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6036 | return -1; |
6037 | } | |
6038 | else | |
6039 | { | |
955db0c0 | 6040 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6041 | return -1; |
6042 | } | |
7ad10968 HZ |
6043 | } |
6044 | } | |
6045 | break; | |
a38bba38 | 6046 | case 2: /* lgdt */ |
3800e645 MS |
6047 | if (ir.mod == 3) |
6048 | { | |
6049 | /* xgetbv */ | |
6050 | if (ir.rm == 0) | |
6051 | { | |
6052 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6053 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6054 | break; | |
6055 | } | |
6056 | /* xsetbv */ | |
6057 | else if (ir.rm == 1) | |
6058 | break; | |
6059 | } | |
a38bba38 | 6060 | case 3: /* lidt */ |
7ad10968 HZ |
6061 | if (ir.mod == 3) |
6062 | { | |
6063 | ir.addr -= 3; | |
6064 | opcode = opcode << 8 | ir.modrm; | |
6065 | goto no_support; | |
6066 | } | |
6067 | break; | |
a38bba38 | 6068 | case 4: /* smsw */ |
7ad10968 HZ |
6069 | if (ir.mod == 3) |
6070 | { | |
cf648174 | 6071 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
6072 | return -1; |
6073 | } | |
6074 | else | |
6075 | { | |
6076 | ir.ot = OT_WORD; | |
6077 | if (i386_record_lea_modrm (&ir)) | |
6078 | return -1; | |
6079 | } | |
cf648174 | 6080 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6081 | break; |
a38bba38 | 6082 | case 6: /* lmsw */ |
cf648174 HZ |
6083 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6084 | break; | |
a38bba38 | 6085 | case 7: /* invlpg */ |
cf648174 HZ |
6086 | if (ir.mod == 3) |
6087 | { | |
6088 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
6089 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
6090 | else | |
6091 | { | |
6092 | ir.addr -= 3; | |
6093 | opcode = opcode << 8 | ir.modrm; | |
6094 | goto no_support; | |
6095 | } | |
6096 | } | |
6097 | else | |
6098 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6099 | break; | |
6100 | default: | |
6101 | ir.addr -= 3; | |
6102 | opcode = opcode << 8 | ir.modrm; | |
6103 | goto no_support; | |
7ad10968 HZ |
6104 | break; |
6105 | } | |
6106 | break; | |
6107 | ||
a38bba38 MS |
6108 | case 0x0f08: /* invd */ |
6109 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
6110 | break; |
6111 | ||
a38bba38 | 6112 | case 0x63: /* arpl */ |
7ad10968 HZ |
6113 | if (i386_record_modrm (&ir)) |
6114 | return -1; | |
cf648174 HZ |
6115 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
6116 | { | |
6117 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
6118 | ? (ir.reg | rex_r) : ir.rm); | |
6119 | } | |
7ad10968 | 6120 | else |
cf648174 HZ |
6121 | { |
6122 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
6123 | if (i386_record_lea_modrm (&ir)) | |
6124 | return -1; | |
6125 | } | |
6126 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
6127 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6128 | break; |
6129 | ||
a38bba38 MS |
6130 | case 0x0f02: /* lar */ |
6131 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
6132 | if (i386_record_modrm (&ir)) |
6133 | return -1; | |
cf648174 HZ |
6134 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6135 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6136 | break; |
6137 | ||
6138 | case 0x0f18: | |
cf648174 HZ |
6139 | if (i386_record_modrm (&ir)) |
6140 | return -1; | |
6141 | if (ir.mod == 3 && ir.reg == 3) | |
6142 | { | |
6143 | ir.addr -= 3; | |
6144 | opcode = opcode << 8 | ir.modrm; | |
6145 | goto no_support; | |
6146 | } | |
7ad10968 HZ |
6147 | break; |
6148 | ||
7ad10968 HZ |
6149 | case 0x0f19: |
6150 | case 0x0f1a: | |
6151 | case 0x0f1b: | |
6152 | case 0x0f1c: | |
6153 | case 0x0f1d: | |
6154 | case 0x0f1e: | |
6155 | case 0x0f1f: | |
a38bba38 | 6156 | /* nop (multi byte) */ |
7ad10968 HZ |
6157 | break; |
6158 | ||
a38bba38 MS |
6159 | case 0x0f20: /* mov reg, crN */ |
6160 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
6161 | if (i386_record_modrm (&ir)) |
6162 | return -1; | |
6163 | if ((ir.modrm & 0xc0) != 0xc0) | |
6164 | { | |
cf648174 | 6165 | ir.addr -= 3; |
7ad10968 HZ |
6166 | opcode = opcode << 8 | ir.modrm; |
6167 | goto no_support; | |
6168 | } | |
6169 | switch (ir.reg) | |
6170 | { | |
6171 | case 0: | |
6172 | case 2: | |
6173 | case 3: | |
6174 | case 4: | |
6175 | case 8: | |
6176 | if (opcode & 2) | |
cf648174 | 6177 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6178 | else |
cf648174 | 6179 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6180 | break; |
6181 | default: | |
cf648174 | 6182 | ir.addr -= 3; |
7ad10968 HZ |
6183 | opcode = opcode << 8 | ir.modrm; |
6184 | goto no_support; | |
6185 | break; | |
6186 | } | |
6187 | break; | |
6188 | ||
a38bba38 MS |
6189 | case 0x0f21: /* mov reg, drN */ |
6190 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
6191 | if (i386_record_modrm (&ir)) |
6192 | return -1; | |
6193 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
6194 | || ir.reg == 5 || ir.reg >= 8) | |
6195 | { | |
cf648174 | 6196 | ir.addr -= 3; |
7ad10968 HZ |
6197 | opcode = opcode << 8 | ir.modrm; |
6198 | goto no_support; | |
6199 | } | |
6200 | if (opcode & 2) | |
cf648174 | 6201 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6202 | else |
cf648174 | 6203 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6204 | break; |
6205 | ||
a38bba38 | 6206 | case 0x0f06: /* clts */ |
cf648174 | 6207 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6208 | break; |
6209 | ||
a3c4230a HZ |
6210 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
6211 | ||
6212 | case 0x0f0d: /* 3DNow! prefetch */ | |
6213 | break; | |
6214 | ||
6215 | case 0x0f0e: /* 3DNow! femms */ | |
6216 | case 0x0f77: /* emms */ | |
6217 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
6218 | goto no_support; | |
6219 | record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); | |
6220 | break; | |
6221 | ||
6222 | case 0x0f0f: /* 3DNow! data */ | |
6223 | if (i386_record_modrm (&ir)) | |
6224 | return -1; | |
6225 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
6226 | { | |
6227 | printf_unfiltered (_("Process record: error reading memory at " | |
6228 | "addr %s len = 1.\n"), | |
6229 | paddress (gdbarch, ir.addr)); | |
6230 | return -1; | |
6231 | } | |
6232 | ir.addr++; | |
6233 | switch (opcode8) | |
6234 | { | |
6235 | case 0x0c: /* 3DNow! pi2fw */ | |
6236 | case 0x0d: /* 3DNow! pi2fd */ | |
6237 | case 0x1c: /* 3DNow! pf2iw */ | |
6238 | case 0x1d: /* 3DNow! pf2id */ | |
6239 | case 0x8a: /* 3DNow! pfnacc */ | |
6240 | case 0x8e: /* 3DNow! pfpnacc */ | |
6241 | case 0x90: /* 3DNow! pfcmpge */ | |
6242 | case 0x94: /* 3DNow! pfmin */ | |
6243 | case 0x96: /* 3DNow! pfrcp */ | |
6244 | case 0x97: /* 3DNow! pfrsqrt */ | |
6245 | case 0x9a: /* 3DNow! pfsub */ | |
6246 | case 0x9e: /* 3DNow! pfadd */ | |
6247 | case 0xa0: /* 3DNow! pfcmpgt */ | |
6248 | case 0xa4: /* 3DNow! pfmax */ | |
6249 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
6250 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
6251 | case 0xaa: /* 3DNow! pfsubr */ | |
6252 | case 0xae: /* 3DNow! pfacc */ | |
6253 | case 0xb0: /* 3DNow! pfcmpeq */ | |
6254 | case 0xb4: /* 3DNow! pfmul */ | |
6255 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
6256 | case 0xb7: /* 3DNow! pmulhrw */ | |
6257 | case 0xbb: /* 3DNow! pswapd */ | |
6258 | case 0xbf: /* 3DNow! pavgusb */ | |
6259 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6260 | goto no_support_3dnow_data; | |
6261 | record_arch_list_add_reg (ir.regcache, ir.reg); | |
6262 | break; | |
6263 | ||
6264 | default: | |
6265 | no_support_3dnow_data: | |
6266 | opcode = (opcode << 8) | opcode8; | |
6267 | goto no_support; | |
6268 | break; | |
6269 | } | |
6270 | break; | |
6271 | ||
6272 | case 0x0faa: /* rsm */ | |
6273 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6274 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6275 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6276 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6277 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
6278 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6279 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
6280 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6281 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6282 | break; | |
6283 | ||
6284 | case 0x0fae: | |
6285 | if (i386_record_modrm (&ir)) | |
6286 | return -1; | |
6287 | switch(ir.reg) | |
6288 | { | |
6289 | case 0: /* fxsave */ | |
6290 | { | |
6291 | uint64_t tmpu64; | |
6292 | ||
6293 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6294 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) | |
6295 | return -1; | |
6296 | if (record_arch_list_add_mem (tmpu64, 512)) | |
6297 | return -1; | |
6298 | } | |
6299 | break; | |
6300 | ||
6301 | case 1: /* fxrstor */ | |
6302 | { | |
6303 | int i; | |
6304 | ||
6305 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6306 | ||
6307 | for (i = I387_MM0_REGNUM (tdep); | |
6308 | i386_mmx_regnum_p (gdbarch, i); i++) | |
6309 | record_arch_list_add_reg (ir.regcache, i); | |
6310 | ||
6311 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 6312 | i386_xmm_regnum_p (gdbarch, i); i++) |
a3c4230a HZ |
6313 | record_arch_list_add_reg (ir.regcache, i); |
6314 | ||
6315 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6316 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6317 | ||
6318 | for (i = I387_ST0_REGNUM (tdep); | |
6319 | i386_fp_regnum_p (gdbarch, i); i++) | |
6320 | record_arch_list_add_reg (ir.regcache, i); | |
6321 | ||
6322 | for (i = I387_FCTRL_REGNUM (tdep); | |
6323 | i386_fpc_regnum_p (gdbarch, i); i++) | |
6324 | record_arch_list_add_reg (ir.regcache, i); | |
6325 | } | |
6326 | break; | |
6327 | ||
6328 | case 2: /* ldmxcsr */ | |
6329 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6330 | goto no_support; | |
6331 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6332 | break; | |
6333 | ||
6334 | case 3: /* stmxcsr */ | |
6335 | ir.ot = OT_LONG; | |
6336 | if (i386_record_lea_modrm (&ir)) | |
6337 | return -1; | |
6338 | break; | |
6339 | ||
6340 | case 5: /* lfence */ | |
6341 | case 6: /* mfence */ | |
6342 | case 7: /* sfence clflush */ | |
6343 | break; | |
6344 | ||
6345 | default: | |
6346 | opcode = (opcode << 8) | ir.modrm; | |
6347 | goto no_support; | |
6348 | break; | |
6349 | } | |
6350 | break; | |
6351 | ||
6352 | case 0x0fc3: /* movnti */ | |
6353 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
6354 | if (i386_record_modrm (&ir)) | |
6355 | return -1; | |
6356 | if (ir.mod == 3) | |
6357 | goto no_support; | |
6358 | ir.reg |= rex_r; | |
6359 | if (i386_record_lea_modrm (&ir)) | |
6360 | return -1; | |
6361 | break; | |
6362 | ||
6363 | /* Add prefix to opcode. */ | |
6364 | case 0x0f10: | |
6365 | case 0x0f11: | |
6366 | case 0x0f12: | |
6367 | case 0x0f13: | |
6368 | case 0x0f14: | |
6369 | case 0x0f15: | |
6370 | case 0x0f16: | |
6371 | case 0x0f17: | |
6372 | case 0x0f28: | |
6373 | case 0x0f29: | |
6374 | case 0x0f2a: | |
6375 | case 0x0f2b: | |
6376 | case 0x0f2c: | |
6377 | case 0x0f2d: | |
6378 | case 0x0f2e: | |
6379 | case 0x0f2f: | |
6380 | case 0x0f38: | |
6381 | case 0x0f39: | |
6382 | case 0x0f3a: | |
6383 | case 0x0f50: | |
6384 | case 0x0f51: | |
6385 | case 0x0f52: | |
6386 | case 0x0f53: | |
6387 | case 0x0f54: | |
6388 | case 0x0f55: | |
6389 | case 0x0f56: | |
6390 | case 0x0f57: | |
6391 | case 0x0f58: | |
6392 | case 0x0f59: | |
6393 | case 0x0f5a: | |
6394 | case 0x0f5b: | |
6395 | case 0x0f5c: | |
6396 | case 0x0f5d: | |
6397 | case 0x0f5e: | |
6398 | case 0x0f5f: | |
6399 | case 0x0f60: | |
6400 | case 0x0f61: | |
6401 | case 0x0f62: | |
6402 | case 0x0f63: | |
6403 | case 0x0f64: | |
6404 | case 0x0f65: | |
6405 | case 0x0f66: | |
6406 | case 0x0f67: | |
6407 | case 0x0f68: | |
6408 | case 0x0f69: | |
6409 | case 0x0f6a: | |
6410 | case 0x0f6b: | |
6411 | case 0x0f6c: | |
6412 | case 0x0f6d: | |
6413 | case 0x0f6e: | |
6414 | case 0x0f6f: | |
6415 | case 0x0f70: | |
6416 | case 0x0f71: | |
6417 | case 0x0f72: | |
6418 | case 0x0f73: | |
6419 | case 0x0f74: | |
6420 | case 0x0f75: | |
6421 | case 0x0f76: | |
6422 | case 0x0f7c: | |
6423 | case 0x0f7d: | |
6424 | case 0x0f7e: | |
6425 | case 0x0f7f: | |
6426 | case 0x0fb8: | |
6427 | case 0x0fc2: | |
6428 | case 0x0fc4: | |
6429 | case 0x0fc5: | |
6430 | case 0x0fc6: | |
6431 | case 0x0fd0: | |
6432 | case 0x0fd1: | |
6433 | case 0x0fd2: | |
6434 | case 0x0fd3: | |
6435 | case 0x0fd4: | |
6436 | case 0x0fd5: | |
6437 | case 0x0fd6: | |
6438 | case 0x0fd7: | |
6439 | case 0x0fd8: | |
6440 | case 0x0fd9: | |
6441 | case 0x0fda: | |
6442 | case 0x0fdb: | |
6443 | case 0x0fdc: | |
6444 | case 0x0fdd: | |
6445 | case 0x0fde: | |
6446 | case 0x0fdf: | |
6447 | case 0x0fe0: | |
6448 | case 0x0fe1: | |
6449 | case 0x0fe2: | |
6450 | case 0x0fe3: | |
6451 | case 0x0fe4: | |
6452 | case 0x0fe5: | |
6453 | case 0x0fe6: | |
6454 | case 0x0fe7: | |
6455 | case 0x0fe8: | |
6456 | case 0x0fe9: | |
6457 | case 0x0fea: | |
6458 | case 0x0feb: | |
6459 | case 0x0fec: | |
6460 | case 0x0fed: | |
6461 | case 0x0fee: | |
6462 | case 0x0fef: | |
6463 | case 0x0ff0: | |
6464 | case 0x0ff1: | |
6465 | case 0x0ff2: | |
6466 | case 0x0ff3: | |
6467 | case 0x0ff4: | |
6468 | case 0x0ff5: | |
6469 | case 0x0ff6: | |
6470 | case 0x0ff7: | |
6471 | case 0x0ff8: | |
6472 | case 0x0ff9: | |
6473 | case 0x0ffa: | |
6474 | case 0x0ffb: | |
6475 | case 0x0ffc: | |
6476 | case 0x0ffd: | |
6477 | case 0x0ffe: | |
6478 | switch (prefixes) | |
6479 | { | |
6480 | case PREFIX_REPNZ: | |
6481 | opcode |= 0xf20000; | |
6482 | break; | |
6483 | case PREFIX_DATA: | |
6484 | opcode |= 0x660000; | |
6485 | break; | |
6486 | case PREFIX_REPZ: | |
6487 | opcode |= 0xf30000; | |
6488 | break; | |
6489 | } | |
6490 | reswitch_prefix_add: | |
6491 | switch (opcode) | |
6492 | { | |
6493 | case 0x0f38: | |
6494 | case 0x660f38: | |
6495 | case 0xf20f38: | |
6496 | case 0x0f3a: | |
6497 | case 0x660f3a: | |
6498 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
6499 | { | |
6500 | printf_unfiltered (_("Process record: error reading memory at " | |
6501 | "addr %s len = 1.\n"), | |
6502 | paddress (gdbarch, ir.addr)); | |
6503 | return -1; | |
6504 | } | |
6505 | ir.addr++; | |
6506 | opcode = (uint32_t) opcode8 | opcode << 8; | |
6507 | goto reswitch_prefix_add; | |
6508 | break; | |
6509 | ||
6510 | case 0x0f10: /* movups */ | |
6511 | case 0x660f10: /* movupd */ | |
6512 | case 0xf30f10: /* movss */ | |
6513 | case 0xf20f10: /* movsd */ | |
6514 | case 0x0f12: /* movlps */ | |
6515 | case 0x660f12: /* movlpd */ | |
6516 | case 0xf30f12: /* movsldup */ | |
6517 | case 0xf20f12: /* movddup */ | |
6518 | case 0x0f14: /* unpcklps */ | |
6519 | case 0x660f14: /* unpcklpd */ | |
6520 | case 0x0f15: /* unpckhps */ | |
6521 | case 0x660f15: /* unpckhpd */ | |
6522 | case 0x0f16: /* movhps */ | |
6523 | case 0x660f16: /* movhpd */ | |
6524 | case 0xf30f16: /* movshdup */ | |
6525 | case 0x0f28: /* movaps */ | |
6526 | case 0x660f28: /* movapd */ | |
6527 | case 0x0f2a: /* cvtpi2ps */ | |
6528 | case 0x660f2a: /* cvtpi2pd */ | |
6529 | case 0xf30f2a: /* cvtsi2ss */ | |
6530 | case 0xf20f2a: /* cvtsi2sd */ | |
6531 | case 0x0f2c: /* cvttps2pi */ | |
6532 | case 0x660f2c: /* cvttpd2pi */ | |
6533 | case 0x0f2d: /* cvtps2pi */ | |
6534 | case 0x660f2d: /* cvtpd2pi */ | |
6535 | case 0x660f3800: /* pshufb */ | |
6536 | case 0x660f3801: /* phaddw */ | |
6537 | case 0x660f3802: /* phaddd */ | |
6538 | case 0x660f3803: /* phaddsw */ | |
6539 | case 0x660f3804: /* pmaddubsw */ | |
6540 | case 0x660f3805: /* phsubw */ | |
6541 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 6542 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
6543 | case 0x660f3808: /* psignb */ |
6544 | case 0x660f3809: /* psignw */ | |
6545 | case 0x660f380a: /* psignd */ | |
6546 | case 0x660f380b: /* pmulhrsw */ | |
6547 | case 0x660f3810: /* pblendvb */ | |
6548 | case 0x660f3814: /* blendvps */ | |
6549 | case 0x660f3815: /* blendvpd */ | |
6550 | case 0x660f381c: /* pabsb */ | |
6551 | case 0x660f381d: /* pabsw */ | |
6552 | case 0x660f381e: /* pabsd */ | |
6553 | case 0x660f3820: /* pmovsxbw */ | |
6554 | case 0x660f3821: /* pmovsxbd */ | |
6555 | case 0x660f3822: /* pmovsxbq */ | |
6556 | case 0x660f3823: /* pmovsxwd */ | |
6557 | case 0x660f3824: /* pmovsxwq */ | |
6558 | case 0x660f3825: /* pmovsxdq */ | |
6559 | case 0x660f3828: /* pmuldq */ | |
6560 | case 0x660f3829: /* pcmpeqq */ | |
6561 | case 0x660f382a: /* movntdqa */ | |
6562 | case 0x660f3a08: /* roundps */ | |
6563 | case 0x660f3a09: /* roundpd */ | |
6564 | case 0x660f3a0a: /* roundss */ | |
6565 | case 0x660f3a0b: /* roundsd */ | |
6566 | case 0x660f3a0c: /* blendps */ | |
6567 | case 0x660f3a0d: /* blendpd */ | |
6568 | case 0x660f3a0e: /* pblendw */ | |
6569 | case 0x660f3a0f: /* palignr */ | |
6570 | case 0x660f3a20: /* pinsrb */ | |
6571 | case 0x660f3a21: /* insertps */ | |
6572 | case 0x660f3a22: /* pinsrd pinsrq */ | |
6573 | case 0x660f3a40: /* dpps */ | |
6574 | case 0x660f3a41: /* dppd */ | |
6575 | case 0x660f3a42: /* mpsadbw */ | |
6576 | case 0x660f3a60: /* pcmpestrm */ | |
6577 | case 0x660f3a61: /* pcmpestri */ | |
6578 | case 0x660f3a62: /* pcmpistrm */ | |
6579 | case 0x660f3a63: /* pcmpistri */ | |
6580 | case 0x0f51: /* sqrtps */ | |
6581 | case 0x660f51: /* sqrtpd */ | |
6582 | case 0xf20f51: /* sqrtsd */ | |
6583 | case 0xf30f51: /* sqrtss */ | |
6584 | case 0x0f52: /* rsqrtps */ | |
6585 | case 0xf30f52: /* rsqrtss */ | |
6586 | case 0x0f53: /* rcpps */ | |
6587 | case 0xf30f53: /* rcpss */ | |
6588 | case 0x0f54: /* andps */ | |
6589 | case 0x660f54: /* andpd */ | |
6590 | case 0x0f55: /* andnps */ | |
6591 | case 0x660f55: /* andnpd */ | |
6592 | case 0x0f56: /* orps */ | |
6593 | case 0x660f56: /* orpd */ | |
6594 | case 0x0f57: /* xorps */ | |
6595 | case 0x660f57: /* xorpd */ | |
6596 | case 0x0f58: /* addps */ | |
6597 | case 0x660f58: /* addpd */ | |
6598 | case 0xf20f58: /* addsd */ | |
6599 | case 0xf30f58: /* addss */ | |
6600 | case 0x0f59: /* mulps */ | |
6601 | case 0x660f59: /* mulpd */ | |
6602 | case 0xf20f59: /* mulsd */ | |
6603 | case 0xf30f59: /* mulss */ | |
6604 | case 0x0f5a: /* cvtps2pd */ | |
6605 | case 0x660f5a: /* cvtpd2ps */ | |
6606 | case 0xf20f5a: /* cvtsd2ss */ | |
6607 | case 0xf30f5a: /* cvtss2sd */ | |
6608 | case 0x0f5b: /* cvtdq2ps */ | |
6609 | case 0x660f5b: /* cvtps2dq */ | |
6610 | case 0xf30f5b: /* cvttps2dq */ | |
6611 | case 0x0f5c: /* subps */ | |
6612 | case 0x660f5c: /* subpd */ | |
6613 | case 0xf20f5c: /* subsd */ | |
6614 | case 0xf30f5c: /* subss */ | |
6615 | case 0x0f5d: /* minps */ | |
6616 | case 0x660f5d: /* minpd */ | |
6617 | case 0xf20f5d: /* minsd */ | |
6618 | case 0xf30f5d: /* minss */ | |
6619 | case 0x0f5e: /* divps */ | |
6620 | case 0x660f5e: /* divpd */ | |
6621 | case 0xf20f5e: /* divsd */ | |
6622 | case 0xf30f5e: /* divss */ | |
6623 | case 0x0f5f: /* maxps */ | |
6624 | case 0x660f5f: /* maxpd */ | |
6625 | case 0xf20f5f: /* maxsd */ | |
6626 | case 0xf30f5f: /* maxss */ | |
6627 | case 0x660f60: /* punpcklbw */ | |
6628 | case 0x660f61: /* punpcklwd */ | |
6629 | case 0x660f62: /* punpckldq */ | |
6630 | case 0x660f63: /* packsswb */ | |
6631 | case 0x660f64: /* pcmpgtb */ | |
6632 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 6633 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
6634 | case 0x660f67: /* packuswb */ |
6635 | case 0x660f68: /* punpckhbw */ | |
6636 | case 0x660f69: /* punpckhwd */ | |
6637 | case 0x660f6a: /* punpckhdq */ | |
6638 | case 0x660f6b: /* packssdw */ | |
6639 | case 0x660f6c: /* punpcklqdq */ | |
6640 | case 0x660f6d: /* punpckhqdq */ | |
6641 | case 0x660f6e: /* movd */ | |
6642 | case 0x660f6f: /* movdqa */ | |
6643 | case 0xf30f6f: /* movdqu */ | |
6644 | case 0x660f70: /* pshufd */ | |
6645 | case 0xf20f70: /* pshuflw */ | |
6646 | case 0xf30f70: /* pshufhw */ | |
6647 | case 0x660f74: /* pcmpeqb */ | |
6648 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 6649 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
6650 | case 0x660f7c: /* haddpd */ |
6651 | case 0xf20f7c: /* haddps */ | |
6652 | case 0x660f7d: /* hsubpd */ | |
6653 | case 0xf20f7d: /* hsubps */ | |
6654 | case 0xf30f7e: /* movq */ | |
6655 | case 0x0fc2: /* cmpps */ | |
6656 | case 0x660fc2: /* cmppd */ | |
6657 | case 0xf20fc2: /* cmpsd */ | |
6658 | case 0xf30fc2: /* cmpss */ | |
6659 | case 0x660fc4: /* pinsrw */ | |
6660 | case 0x0fc6: /* shufps */ | |
6661 | case 0x660fc6: /* shufpd */ | |
6662 | case 0x660fd0: /* addsubpd */ | |
6663 | case 0xf20fd0: /* addsubps */ | |
6664 | case 0x660fd1: /* psrlw */ | |
6665 | case 0x660fd2: /* psrld */ | |
6666 | case 0x660fd3: /* psrlq */ | |
6667 | case 0x660fd4: /* paddq */ | |
6668 | case 0x660fd5: /* pmullw */ | |
6669 | case 0xf30fd6: /* movq2dq */ | |
6670 | case 0x660fd8: /* psubusb */ | |
6671 | case 0x660fd9: /* psubusw */ | |
6672 | case 0x660fda: /* pminub */ | |
6673 | case 0x660fdb: /* pand */ | |
6674 | case 0x660fdc: /* paddusb */ | |
6675 | case 0x660fdd: /* paddusw */ | |
6676 | case 0x660fde: /* pmaxub */ | |
6677 | case 0x660fdf: /* pandn */ | |
6678 | case 0x660fe0: /* pavgb */ | |
6679 | case 0x660fe1: /* psraw */ | |
6680 | case 0x660fe2: /* psrad */ | |
6681 | case 0x660fe3: /* pavgw */ | |
6682 | case 0x660fe4: /* pmulhuw */ | |
6683 | case 0x660fe5: /* pmulhw */ | |
6684 | case 0x660fe6: /* cvttpd2dq */ | |
6685 | case 0xf20fe6: /* cvtpd2dq */ | |
6686 | case 0xf30fe6: /* cvtdq2pd */ | |
6687 | case 0x660fe8: /* psubsb */ | |
6688 | case 0x660fe9: /* psubsw */ | |
6689 | case 0x660fea: /* pminsw */ | |
6690 | case 0x660feb: /* por */ | |
6691 | case 0x660fec: /* paddsb */ | |
6692 | case 0x660fed: /* paddsw */ | |
6693 | case 0x660fee: /* pmaxsw */ | |
6694 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 6695 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
6696 | case 0x660ff1: /* psllw */ |
6697 | case 0x660ff2: /* pslld */ | |
6698 | case 0x660ff3: /* psllq */ | |
6699 | case 0x660ff4: /* pmuludq */ | |
6700 | case 0x660ff5: /* pmaddwd */ | |
6701 | case 0x660ff6: /* psadbw */ | |
6702 | case 0x660ff8: /* psubb */ | |
6703 | case 0x660ff9: /* psubw */ | |
56d2815c | 6704 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
6705 | case 0x660ffb: /* psubq */ |
6706 | case 0x660ffc: /* paddb */ | |
6707 | case 0x660ffd: /* paddw */ | |
56d2815c | 6708 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
6709 | if (i386_record_modrm (&ir)) |
6710 | return -1; | |
6711 | ir.reg |= rex_r; | |
c131fcee | 6712 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a HZ |
6713 | goto no_support; |
6714 | record_arch_list_add_reg (ir.regcache, | |
6715 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
6716 | if ((opcode & 0xfffffffc) == 0x660f3a60) | |
6717 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6718 | break; | |
6719 | ||
6720 | case 0x0f11: /* movups */ | |
6721 | case 0x660f11: /* movupd */ | |
6722 | case 0xf30f11: /* movss */ | |
6723 | case 0xf20f11: /* movsd */ | |
6724 | case 0x0f13: /* movlps */ | |
6725 | case 0x660f13: /* movlpd */ | |
6726 | case 0x0f17: /* movhps */ | |
6727 | case 0x660f17: /* movhpd */ | |
6728 | case 0x0f29: /* movaps */ | |
6729 | case 0x660f29: /* movapd */ | |
6730 | case 0x660f3a14: /* pextrb */ | |
6731 | case 0x660f3a15: /* pextrw */ | |
6732 | case 0x660f3a16: /* pextrd pextrq */ | |
6733 | case 0x660f3a17: /* extractps */ | |
6734 | case 0x660f7f: /* movdqa */ | |
6735 | case 0xf30f7f: /* movdqu */ | |
6736 | if (i386_record_modrm (&ir)) | |
6737 | return -1; | |
6738 | if (ir.mod == 3) | |
6739 | { | |
6740 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
6741 | || opcode == 0x0f17 || opcode == 0x660f17) | |
6742 | goto no_support; | |
6743 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
6744 | if (!i386_xmm_regnum_p (gdbarch, |
6745 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
6746 | goto no_support; |
6747 | record_arch_list_add_reg (ir.regcache, | |
6748 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6749 | } | |
6750 | else | |
6751 | { | |
6752 | switch (opcode) | |
6753 | { | |
6754 | case 0x660f3a14: | |
6755 | ir.ot = OT_BYTE; | |
6756 | break; | |
6757 | case 0x660f3a15: | |
6758 | ir.ot = OT_WORD; | |
6759 | break; | |
6760 | case 0x660f3a16: | |
6761 | ir.ot = OT_LONG; | |
6762 | break; | |
6763 | case 0x660f3a17: | |
6764 | ir.ot = OT_QUAD; | |
6765 | break; | |
6766 | default: | |
6767 | ir.ot = OT_DQUAD; | |
6768 | break; | |
6769 | } | |
6770 | if (i386_record_lea_modrm (&ir)) | |
6771 | return -1; | |
6772 | } | |
6773 | break; | |
6774 | ||
6775 | case 0x0f2b: /* movntps */ | |
6776 | case 0x660f2b: /* movntpd */ | |
6777 | case 0x0fe7: /* movntq */ | |
6778 | case 0x660fe7: /* movntdq */ | |
6779 | if (ir.mod == 3) | |
6780 | goto no_support; | |
6781 | if (opcode == 0x0fe7) | |
6782 | ir.ot = OT_QUAD; | |
6783 | else | |
6784 | ir.ot = OT_DQUAD; | |
6785 | if (i386_record_lea_modrm (&ir)) | |
6786 | return -1; | |
6787 | break; | |
6788 | ||
6789 | case 0xf30f2c: /* cvttss2si */ | |
6790 | case 0xf20f2c: /* cvttsd2si */ | |
6791 | case 0xf30f2d: /* cvtss2si */ | |
6792 | case 0xf20f2d: /* cvtsd2si */ | |
6793 | case 0xf20f38f0: /* crc32 */ | |
6794 | case 0xf20f38f1: /* crc32 */ | |
6795 | case 0x0f50: /* movmskps */ | |
6796 | case 0x660f50: /* movmskpd */ | |
6797 | case 0x0fc5: /* pextrw */ | |
6798 | case 0x660fc5: /* pextrw */ | |
6799 | case 0x0fd7: /* pmovmskb */ | |
6800 | case 0x660fd7: /* pmovmskb */ | |
6801 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
6802 | break; | |
6803 | ||
6804 | case 0x0f3800: /* pshufb */ | |
6805 | case 0x0f3801: /* phaddw */ | |
6806 | case 0x0f3802: /* phaddd */ | |
6807 | case 0x0f3803: /* phaddsw */ | |
6808 | case 0x0f3804: /* pmaddubsw */ | |
6809 | case 0x0f3805: /* phsubw */ | |
6810 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 6811 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
6812 | case 0x0f3808: /* psignb */ |
6813 | case 0x0f3809: /* psignw */ | |
6814 | case 0x0f380a: /* psignd */ | |
6815 | case 0x0f380b: /* pmulhrsw */ | |
6816 | case 0x0f381c: /* pabsb */ | |
6817 | case 0x0f381d: /* pabsw */ | |
6818 | case 0x0f381e: /* pabsd */ | |
6819 | case 0x0f382b: /* packusdw */ | |
6820 | case 0x0f3830: /* pmovzxbw */ | |
6821 | case 0x0f3831: /* pmovzxbd */ | |
6822 | case 0x0f3832: /* pmovzxbq */ | |
6823 | case 0x0f3833: /* pmovzxwd */ | |
6824 | case 0x0f3834: /* pmovzxwq */ | |
6825 | case 0x0f3835: /* pmovzxdq */ | |
6826 | case 0x0f3837: /* pcmpgtq */ | |
6827 | case 0x0f3838: /* pminsb */ | |
6828 | case 0x0f3839: /* pminsd */ | |
6829 | case 0x0f383a: /* pminuw */ | |
6830 | case 0x0f383b: /* pminud */ | |
6831 | case 0x0f383c: /* pmaxsb */ | |
6832 | case 0x0f383d: /* pmaxsd */ | |
6833 | case 0x0f383e: /* pmaxuw */ | |
6834 | case 0x0f383f: /* pmaxud */ | |
6835 | case 0x0f3840: /* pmulld */ | |
6836 | case 0x0f3841: /* phminposuw */ | |
6837 | case 0x0f3a0f: /* palignr */ | |
6838 | case 0x0f60: /* punpcklbw */ | |
6839 | case 0x0f61: /* punpcklwd */ | |
6840 | case 0x0f62: /* punpckldq */ | |
6841 | case 0x0f63: /* packsswb */ | |
6842 | case 0x0f64: /* pcmpgtb */ | |
6843 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 6844 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
6845 | case 0x0f67: /* packuswb */ |
6846 | case 0x0f68: /* punpckhbw */ | |
6847 | case 0x0f69: /* punpckhwd */ | |
6848 | case 0x0f6a: /* punpckhdq */ | |
6849 | case 0x0f6b: /* packssdw */ | |
6850 | case 0x0f6e: /* movd */ | |
6851 | case 0x0f6f: /* movq */ | |
6852 | case 0x0f70: /* pshufw */ | |
6853 | case 0x0f74: /* pcmpeqb */ | |
6854 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 6855 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
6856 | case 0x0fc4: /* pinsrw */ |
6857 | case 0x0fd1: /* psrlw */ | |
6858 | case 0x0fd2: /* psrld */ | |
6859 | case 0x0fd3: /* psrlq */ | |
6860 | case 0x0fd4: /* paddq */ | |
6861 | case 0x0fd5: /* pmullw */ | |
6862 | case 0xf20fd6: /* movdq2q */ | |
6863 | case 0x0fd8: /* psubusb */ | |
6864 | case 0x0fd9: /* psubusw */ | |
6865 | case 0x0fda: /* pminub */ | |
6866 | case 0x0fdb: /* pand */ | |
6867 | case 0x0fdc: /* paddusb */ | |
6868 | case 0x0fdd: /* paddusw */ | |
6869 | case 0x0fde: /* pmaxub */ | |
6870 | case 0x0fdf: /* pandn */ | |
6871 | case 0x0fe0: /* pavgb */ | |
6872 | case 0x0fe1: /* psraw */ | |
6873 | case 0x0fe2: /* psrad */ | |
6874 | case 0x0fe3: /* pavgw */ | |
6875 | case 0x0fe4: /* pmulhuw */ | |
6876 | case 0x0fe5: /* pmulhw */ | |
6877 | case 0x0fe8: /* psubsb */ | |
6878 | case 0x0fe9: /* psubsw */ | |
6879 | case 0x0fea: /* pminsw */ | |
6880 | case 0x0feb: /* por */ | |
6881 | case 0x0fec: /* paddsb */ | |
6882 | case 0x0fed: /* paddsw */ | |
6883 | case 0x0fee: /* pmaxsw */ | |
6884 | case 0x0fef: /* pxor */ | |
6885 | case 0x0ff1: /* psllw */ | |
6886 | case 0x0ff2: /* pslld */ | |
6887 | case 0x0ff3: /* psllq */ | |
6888 | case 0x0ff4: /* pmuludq */ | |
6889 | case 0x0ff5: /* pmaddwd */ | |
6890 | case 0x0ff6: /* psadbw */ | |
6891 | case 0x0ff8: /* psubb */ | |
6892 | case 0x0ff9: /* psubw */ | |
56d2815c | 6893 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
6894 | case 0x0ffb: /* psubq */ |
6895 | case 0x0ffc: /* paddb */ | |
6896 | case 0x0ffd: /* paddw */ | |
56d2815c | 6897 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
6898 | if (i386_record_modrm (&ir)) |
6899 | return -1; | |
6900 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6901 | goto no_support; | |
6902 | record_arch_list_add_reg (ir.regcache, | |
6903 | I387_MM0_REGNUM (tdep) + ir.reg); | |
6904 | break; | |
6905 | ||
6906 | case 0x0f71: /* psllw */ | |
6907 | case 0x0f72: /* pslld */ | |
6908 | case 0x0f73: /* psllq */ | |
6909 | if (i386_record_modrm (&ir)) | |
6910 | return -1; | |
6911 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
6912 | goto no_support; | |
6913 | record_arch_list_add_reg (ir.regcache, | |
6914 | I387_MM0_REGNUM (tdep) + ir.rm); | |
6915 | break; | |
6916 | ||
6917 | case 0x660f71: /* psllw */ | |
6918 | case 0x660f72: /* pslld */ | |
6919 | case 0x660f73: /* psllq */ | |
6920 | if (i386_record_modrm (&ir)) | |
6921 | return -1; | |
6922 | ir.rm |= ir.rex_b; | |
c131fcee | 6923 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a HZ |
6924 | goto no_support; |
6925 | record_arch_list_add_reg (ir.regcache, | |
6926 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6927 | break; | |
6928 | ||
6929 | case 0x0f7e: /* movd */ | |
6930 | case 0x660f7e: /* movd */ | |
6931 | if (i386_record_modrm (&ir)) | |
6932 | return -1; | |
6933 | if (ir.mod == 3) | |
6934 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
6935 | else | |
6936 | { | |
6937 | if (ir.dflag == 2) | |
6938 | ir.ot = OT_QUAD; | |
6939 | else | |
6940 | ir.ot = OT_LONG; | |
6941 | if (i386_record_lea_modrm (&ir)) | |
6942 | return -1; | |
6943 | } | |
6944 | break; | |
6945 | ||
6946 | case 0x0f7f: /* movq */ | |
6947 | if (i386_record_modrm (&ir)) | |
6948 | return -1; | |
6949 | if (ir.mod == 3) | |
6950 | { | |
6951 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
6952 | goto no_support; | |
6953 | record_arch_list_add_reg (ir.regcache, | |
6954 | I387_MM0_REGNUM (tdep) + ir.rm); | |
6955 | } | |
6956 | else | |
6957 | { | |
6958 | ir.ot = OT_QUAD; | |
6959 | if (i386_record_lea_modrm (&ir)) | |
6960 | return -1; | |
6961 | } | |
6962 | break; | |
6963 | ||
6964 | case 0xf30fb8: /* popcnt */ | |
6965 | if (i386_record_modrm (&ir)) | |
6966 | return -1; | |
6967 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); | |
6968 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6969 | break; | |
6970 | ||
6971 | case 0x660fd6: /* movq */ | |
6972 | if (i386_record_modrm (&ir)) | |
6973 | return -1; | |
6974 | if (ir.mod == 3) | |
6975 | { | |
6976 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
6977 | if (!i386_xmm_regnum_p (gdbarch, |
6978 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
6979 | goto no_support; |
6980 | record_arch_list_add_reg (ir.regcache, | |
6981 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6982 | } | |
6983 | else | |
6984 | { | |
6985 | ir.ot = OT_QUAD; | |
6986 | if (i386_record_lea_modrm (&ir)) | |
6987 | return -1; | |
6988 | } | |
6989 | break; | |
6990 | ||
6991 | case 0x660f3817: /* ptest */ | |
6992 | case 0x0f2e: /* ucomiss */ | |
6993 | case 0x660f2e: /* ucomisd */ | |
6994 | case 0x0f2f: /* comiss */ | |
6995 | case 0x660f2f: /* comisd */ | |
6996 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6997 | break; | |
6998 | ||
6999 | case 0x0ff7: /* maskmovq */ | |
7000 | regcache_raw_read_unsigned (ir.regcache, | |
7001 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7002 | &addr); | |
7003 | if (record_arch_list_add_mem (addr, 64)) | |
7004 | return -1; | |
7005 | break; | |
7006 | ||
7007 | case 0x660ff7: /* maskmovdqu */ | |
7008 | regcache_raw_read_unsigned (ir.regcache, | |
7009 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7010 | &addr); | |
7011 | if (record_arch_list_add_mem (addr, 128)) | |
7012 | return -1; | |
7013 | break; | |
7014 | ||
7015 | default: | |
7016 | goto no_support; | |
7017 | break; | |
7018 | } | |
7019 | break; | |
7ad10968 HZ |
7020 | |
7021 | default: | |
7ad10968 HZ |
7022 | goto no_support; |
7023 | break; | |
7024 | } | |
7025 | ||
cf648174 HZ |
7026 | /* In the future, maybe still need to deal with need_dasm. */ |
7027 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
7028 | if (record_arch_list_add_end ()) |
7029 | return -1; | |
7030 | ||
7031 | return 0; | |
7032 | ||
01fe1b41 | 7033 | no_support: |
a3c4230a HZ |
7034 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
7035 | "at address %s.\n"), | |
7036 | (unsigned int) (opcode), | |
7037 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
7038 | return -1; |
7039 | } | |
7040 | ||
cf648174 HZ |
7041 | static const int i386_record_regmap[] = |
7042 | { | |
7043 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
7044 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
7045 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7046 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
7047 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
7048 | }; | |
7049 | ||
7a697b8d SS |
7050 | /* Check that the given address appears suitable for a fast |
7051 | tracepoint, which on x86 means that we need an instruction of at | |
7052 | least 5 bytes, so that we can overwrite it with a 4-byte-offset | |
7053 | jump and not have to worry about program jumps to an address in the | |
7054 | middle of the tracepoint jump. Returns 1 if OK, and writes a size | |
7055 | of instruction to replace, and 0 if not, plus an explanatory | |
7056 | string. */ | |
7057 | ||
7058 | static int | |
7059 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
7060 | CORE_ADDR addr, int *isize, char **msg) | |
7061 | { | |
7062 | int len, jumplen; | |
7063 | static struct ui_file *gdb_null = NULL; | |
7064 | ||
7065 | /* This is based on the target agent using a 4-byte relative jump. | |
7066 | Alternate future possibilities include 8-byte offset for x86-84, | |
7067 | or 3-byte jumps if the program has trampoline space close by. */ | |
7068 | jumplen = 5; | |
7069 | ||
7070 | /* Dummy file descriptor for the disassembler. */ | |
7071 | if (!gdb_null) | |
7072 | gdb_null = ui_file_new (); | |
7073 | ||
7074 | /* Check for fit. */ | |
7075 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
7076 | if (len < jumplen) | |
7077 | { | |
7078 | /* Return a bit of target-specific detail to add to the caller's | |
7079 | generic failure message. */ | |
7080 | if (msg) | |
1777feb0 MS |
7081 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
7082 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
7083 | len, jumplen); |
7084 | return 0; | |
7085 | } | |
7086 | ||
7087 | if (isize) | |
7088 | *isize = len; | |
7089 | if (msg) | |
7090 | *msg = NULL; | |
7091 | return 1; | |
7092 | } | |
7093 | ||
90884b2b L |
7094 | static int |
7095 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
7096 | struct tdesc_arch_data *tdesc_data) | |
7097 | { | |
7098 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee L |
7099 | const struct tdesc_feature *feature_core; |
7100 | const struct tdesc_feature *feature_sse, *feature_avx; | |
90884b2b L |
7101 | int i, num_regs, valid_p; |
7102 | ||
7103 | if (! tdesc_has_registers (tdesc)) | |
7104 | return 0; | |
7105 | ||
7106 | /* Get core registers. */ | |
7107 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
7108 | if (feature_core == NULL) |
7109 | return 0; | |
90884b2b L |
7110 | |
7111 | /* Get SSE registers. */ | |
c131fcee | 7112 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 7113 | |
c131fcee L |
7114 | /* Try AVX registers. */ |
7115 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
7116 | ||
90884b2b L |
7117 | valid_p = 1; |
7118 | ||
c131fcee L |
7119 | /* The XCR0 bits. */ |
7120 | if (feature_avx) | |
7121 | { | |
3a13a53b L |
7122 | /* AVX register description requires SSE register description. */ |
7123 | if (!feature_sse) | |
7124 | return 0; | |
7125 | ||
c131fcee L |
7126 | tdep->xcr0 = I386_XSTATE_AVX_MASK; |
7127 | ||
7128 | /* It may have been set by OSABI initialization function. */ | |
7129 | if (tdep->num_ymm_regs == 0) | |
7130 | { | |
7131 | tdep->ymmh_register_names = i386_ymmh_names; | |
7132 | tdep->num_ymm_regs = 8; | |
7133 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
7134 | } | |
7135 | ||
7136 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
7137 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
7138 | tdep->ymm0h_regnum + i, | |
7139 | tdep->ymmh_register_names[i]); | |
7140 | } | |
3a13a53b | 7141 | else if (feature_sse) |
c131fcee | 7142 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
3a13a53b L |
7143 | else |
7144 | { | |
7145 | tdep->xcr0 = I386_XSTATE_X87_MASK; | |
7146 | tdep->num_xmm_regs = 0; | |
7147 | } | |
c131fcee | 7148 | |
90884b2b L |
7149 | num_regs = tdep->num_core_regs; |
7150 | for (i = 0; i < num_regs; i++) | |
7151 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
7152 | tdep->register_names[i]); | |
7153 | ||
3a13a53b L |
7154 | if (feature_sse) |
7155 | { | |
7156 | /* Need to include %mxcsr, so add one. */ | |
7157 | num_regs += tdep->num_xmm_regs + 1; | |
7158 | for (; i < num_regs; i++) | |
7159 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
7160 | tdep->register_names[i]); | |
7161 | } | |
90884b2b L |
7162 | |
7163 | return valid_p; | |
7164 | } | |
7165 | ||
7ad10968 HZ |
7166 | \f |
7167 | static struct gdbarch * | |
7168 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
7169 | { | |
7170 | struct gdbarch_tdep *tdep; | |
7171 | struct gdbarch *gdbarch; | |
90884b2b L |
7172 | struct tdesc_arch_data *tdesc_data; |
7173 | const struct target_desc *tdesc; | |
1ba53b71 | 7174 | int mm0_regnum; |
c131fcee | 7175 | int ymm0_regnum; |
7ad10968 HZ |
7176 | |
7177 | /* If there is already a candidate, use it. */ | |
7178 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
7179 | if (arches != NULL) | |
7180 | return arches->gdbarch; | |
7181 | ||
7182 | /* Allocate space for the new architecture. */ | |
7183 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
7184 | gdbarch = gdbarch_alloc (&info, tdep); | |
7185 | ||
7186 | /* General-purpose registers. */ | |
7187 | tdep->gregset = NULL; | |
7188 | tdep->gregset_reg_offset = NULL; | |
7189 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
7190 | tdep->sizeof_gregset = 0; | |
7191 | ||
7192 | /* Floating-point registers. */ | |
7193 | tdep->fpregset = NULL; | |
7194 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
7195 | ||
c131fcee L |
7196 | tdep->xstateregset = NULL; |
7197 | ||
7ad10968 HZ |
7198 | /* The default settings include the FPU registers, the MMX registers |
7199 | and the SSE registers. This can be overridden for a specific ABI | |
7200 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
7201 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 7202 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
7203 | |
7204 | tdep->st0_regnum = I386_ST0_REGNUM; | |
7205 | ||
7ad10968 HZ |
7206 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
7207 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
7208 | ||
7209 | tdep->jb_pc_offset = -1; | |
7210 | tdep->struct_return = pcc_struct_return; | |
7211 | tdep->sigtramp_start = 0; | |
7212 | tdep->sigtramp_end = 0; | |
7213 | tdep->sigtramp_p = i386_sigtramp_p; | |
7214 | tdep->sigcontext_addr = NULL; | |
7215 | tdep->sc_reg_offset = NULL; | |
7216 | tdep->sc_pc_offset = -1; | |
7217 | tdep->sc_sp_offset = -1; | |
7218 | ||
c131fcee L |
7219 | tdep->xsave_xcr0_offset = -1; |
7220 | ||
cf648174 HZ |
7221 | tdep->record_regmap = i386_record_regmap; |
7222 | ||
7ad10968 HZ |
7223 | /* The format used for `long double' on almost all i386 targets is |
7224 | the i387 extended floating-point format. In fact, of all targets | |
7225 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
7226 | on having a `long double' that's not `long' at all. */ | |
7227 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
7228 | ||
7229 | /* Although the i387 extended floating-point has only 80 significant | |
7230 | bits, a `long double' actually takes up 96, probably to enforce | |
7231 | alignment. */ | |
7232 | set_gdbarch_long_double_bit (gdbarch, 96); | |
7233 | ||
7ad10968 HZ |
7234 | /* Register numbers of various important registers. */ |
7235 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
7236 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
7237 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
7238 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
7239 | ||
7240 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
7241 | numbering schemes on the i386: dbx and SVR4. These schemes | |
7242 | differ in how they number %ebp, %esp, %eflags, and the | |
7243 | floating-point registers, and are implemented by the arrays | |
7244 | dbx_register_map[] and svr4_dbx_register_map in | |
7245 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
7246 | gcc/config/i386.c, which it designates as the "default" register | |
7247 | map used in 64bit mode. This last register numbering scheme is | |
7248 | implemented in dbx64_register_map, and is used for AMD64; see | |
7249 | amd64-tdep.c. | |
7250 | ||
7251 | Currently, each GCC i386 target always uses the same register | |
7252 | numbering scheme across all its supported debugging formats | |
7253 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
7254 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
7255 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
7256 | respective config header in a manner independent of the requested | |
7257 | output debugging format. | |
7258 | ||
7259 | This does not match the arrangement below, which presumes that | |
7260 | the SDB and stabs numbering schemes differ from the DWARF and | |
7261 | DWARF 2 ones. The reason for this arrangement is that it is | |
7262 | likely to get the numbering scheme for the target's | |
7263 | default/native debug format right. For targets where GCC is the | |
7264 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
7265 | targets where the native toolchain uses a different numbering | |
7266 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
7267 | the defaults below will have to be overridden, like | |
7268 | i386_elf_init_abi() does. */ | |
7269 | ||
7270 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
7271 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7272 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7273 | ||
7274 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
7275 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
7276 | ||
7277 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
7278 | be in use on any of the supported i386 targets. */ | |
7279 | ||
7280 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
7281 | ||
7282 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
7283 | ||
7284 | /* Call dummy code. */ | |
7285 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
7286 | ||
7287 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
7288 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
7289 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
7290 | ||
7291 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
7292 | ||
7293 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
7294 | ||
7295 | /* Stack grows downward. */ | |
7296 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7297 | ||
7298 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
7299 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
7300 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
7301 | ||
7302 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
7303 | ||
7ad10968 HZ |
7304 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
7305 | ||
7306 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
7307 | ||
7308 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
7309 | ||
7310 | /* Add the i386 register groups. */ | |
7311 | i386_add_reggroups (gdbarch); | |
90884b2b | 7312 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 7313 | |
143985b7 AF |
7314 | /* Helper for function argument information. */ |
7315 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
7316 | ||
06da04c6 | 7317 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
7318 | appended to the list first, so that it supercedes the DWARF |
7319 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
7320 | currently fails). */ |
7321 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
7322 | ||
7323 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 7324 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 7325 | CFI info will be used if it is available. */ |
10458914 | 7326 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 7327 | |
acd5c798 | 7328 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 7329 | |
1ba53b71 | 7330 | /* Pseudo registers may be changed by amd64_init_abi. */ |
90884b2b L |
7331 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); |
7332 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
7333 | ||
7334 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
7335 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
7336 | ||
c131fcee L |
7337 | /* Override the normal target description method to make the AVX |
7338 | upper halves anonymous. */ | |
7339 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
7340 | ||
7341 | /* Even though the default ABI only includes general-purpose registers, | |
7342 | floating-point registers and the SSE registers, we have to leave a | |
7343 | gap for the upper AVX registers. */ | |
7344 | set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); | |
90884b2b L |
7345 | |
7346 | /* Get the x86 target description from INFO. */ | |
7347 | tdesc = info.target_desc; | |
7348 | if (! tdesc_has_registers (tdesc)) | |
7349 | tdesc = tdesc_i386; | |
7350 | tdep->tdesc = tdesc; | |
7351 | ||
7352 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
7353 | tdep->register_names = i386_register_names; | |
7354 | ||
c131fcee L |
7355 | /* No upper YMM registers. */ |
7356 | tdep->ymmh_register_names = NULL; | |
7357 | tdep->ymm0h_regnum = -1; | |
7358 | ||
1ba53b71 L |
7359 | tdep->num_byte_regs = 8; |
7360 | tdep->num_word_regs = 8; | |
7361 | tdep->num_dword_regs = 0; | |
7362 | tdep->num_mmx_regs = 8; | |
c131fcee | 7363 | tdep->num_ymm_regs = 0; |
1ba53b71 | 7364 | |
90884b2b L |
7365 | tdesc_data = tdesc_data_alloc (); |
7366 | ||
dde08ee1 PA |
7367 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
7368 | ||
3ce1502b | 7369 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 7370 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 7371 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 7372 | |
c131fcee L |
7373 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
7374 | { | |
7375 | tdesc_data_cleanup (tdesc_data); | |
7376 | xfree (tdep); | |
7377 | gdbarch_free (gdbarch); | |
7378 | return NULL; | |
7379 | } | |
7380 | ||
1ba53b71 L |
7381 | /* Wire in pseudo registers. Number of pseudo registers may be |
7382 | changed. */ | |
7383 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
7384 | + tdep->num_word_regs | |
7385 | + tdep->num_dword_regs | |
c131fcee L |
7386 | + tdep->num_mmx_regs |
7387 | + tdep->num_ymm_regs)); | |
1ba53b71 | 7388 | |
90884b2b L |
7389 | /* Target description may be changed. */ |
7390 | tdesc = tdep->tdesc; | |
7391 | ||
90884b2b L |
7392 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
7393 | ||
7394 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
7395 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
7396 | ||
1ba53b71 L |
7397 | /* Make %al the first pseudo-register. */ |
7398 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
7399 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
7400 | ||
c131fcee | 7401 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
7402 | if (tdep->num_dword_regs) |
7403 | { | |
1c6272a6 | 7404 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
7405 | tdep->eax_regnum = ymm0_regnum; |
7406 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
7407 | } |
7408 | else | |
7409 | tdep->eax_regnum = -1; | |
7410 | ||
c131fcee L |
7411 | mm0_regnum = ymm0_regnum; |
7412 | if (tdep->num_ymm_regs) | |
7413 | { | |
1c6272a6 | 7414 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
7415 | tdep->ymm0_regnum = ymm0_regnum; |
7416 | mm0_regnum += tdep->num_ymm_regs; | |
7417 | } | |
7418 | else | |
7419 | tdep->ymm0_regnum = -1; | |
7420 | ||
1ba53b71 L |
7421 | if (tdep->num_mmx_regs != 0) |
7422 | { | |
1c6272a6 | 7423 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 L |
7424 | tdep->mm0_regnum = mm0_regnum; |
7425 | } | |
7426 | else | |
7427 | tdep->mm0_regnum = -1; | |
7428 | ||
06da04c6 | 7429 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 7430 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
7431 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
7432 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 7433 | |
8446b36a MK |
7434 | /* If we have a register mapping, enable the generic core file |
7435 | support, unless it has already been enabled. */ | |
7436 | if (tdep->gregset_reg_offset | |
7437 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
7438 | set_gdbarch_regset_from_core_section (gdbarch, | |
7439 | i386_regset_from_core_section); | |
7440 | ||
514f746b AR |
7441 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
7442 | i386_skip_permanent_breakpoint); | |
7443 | ||
7a697b8d SS |
7444 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
7445 | i386_fast_tracepoint_valid_at); | |
7446 | ||
a62cc96e AC |
7447 | return gdbarch; |
7448 | } | |
7449 | ||
8201327c MK |
7450 | static enum gdb_osabi |
7451 | i386_coff_osabi_sniffer (bfd *abfd) | |
7452 | { | |
762c5349 MK |
7453 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
7454 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
7455 | return GDB_OSABI_GO32; |
7456 | ||
7457 | return GDB_OSABI_UNKNOWN; | |
7458 | } | |
8201327c MK |
7459 | \f |
7460 | ||
28e9e0f0 MK |
7461 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
7462 | void _initialize_i386_tdep (void); | |
7463 | ||
c906108c | 7464 | void |
fba45db2 | 7465 | _initialize_i386_tdep (void) |
c906108c | 7466 | { |
a62cc96e AC |
7467 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
7468 | ||
fc338970 | 7469 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
7470 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
7471 | &disassembly_flavor, _("\ | |
7472 | Set the disassembly flavor."), _("\ | |
7473 | Show the disassembly flavor."), _("\ | |
7474 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
7475 | NULL, | |
7476 | NULL, /* FIXME: i18n: */ | |
7477 | &setlist, &showlist); | |
8201327c MK |
7478 | |
7479 | /* Add the variable that controls the convention for returning | |
7480 | structs. */ | |
7ab04401 AC |
7481 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
7482 | &struct_convention, _("\ | |
7483 | Set the convention for returning small structs."), _("\ | |
7484 | Show the convention for returning small structs."), _("\ | |
7485 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
7486 | is \"default\"."), | |
7487 | NULL, | |
7488 | NULL, /* FIXME: i18n: */ | |
7489 | &setlist, &showlist); | |
8201327c MK |
7490 | |
7491 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
7492 | i386_coff_osabi_sniffer); | |
8201327c | 7493 | |
05816f70 | 7494 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 7495 | i386_svr4_init_abi); |
05816f70 | 7496 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 7497 | i386_go32_init_abi); |
38c968cf | 7498 | |
209bd28e | 7499 | /* Initialize the i386-specific register groups. */ |
38c968cf | 7500 | i386_init_reggroups (); |
90884b2b L |
7501 | |
7502 | /* Initialize the standard target descriptions. */ | |
7503 | initialize_tdesc_i386 (); | |
3a13a53b | 7504 | initialize_tdesc_i386_mmx (); |
c131fcee | 7505 | initialize_tdesc_i386_avx (); |
c8d5aac9 L |
7506 | |
7507 | /* Tell remote stub that we support XML target description. */ | |
7508 | register_remote_support_xml ("i386"); | |
c906108c | 7509 | } |