Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
3666a048 | 3 | Copyright (C) 1988-2021 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
82ca8957 | 25 | #include "dwarf2/frame.h" |
c906108c | 26 | #include "frame.h" |
acd5c798 MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
c906108c | 29 | #include "inferior.h" |
45741a9c | 30 | #include "infrun.h" |
acd5c798 | 31 | #include "gdbcmd.h" |
c906108c | 32 | #include "gdbcore.h" |
e6bb342a | 33 | #include "gdbtypes.h" |
dfe01d39 | 34 | #include "objfiles.h" |
acd5c798 MK |
35 | #include "osabi.h" |
36 | #include "regcache.h" | |
37 | #include "reggroups.h" | |
473f17b0 | 38 | #include "regset.h" |
c0d1d883 | 39 | #include "symfile.h" |
c906108c | 40 | #include "symtab.h" |
acd5c798 | 41 | #include "target.h" |
3b2ca824 | 42 | #include "target-float.h" |
fd0407d6 | 43 | #include "value.h" |
a89aa300 | 44 | #include "dis-asm.h" |
7a697b8d | 45 | #include "disasm.h" |
c8d5aac9 | 46 | #include "remote.h" |
d2a7c97a | 47 | #include "i386-tdep.h" |
61113f8b | 48 | #include "i387-tdep.h" |
268a13a5 | 49 | #include "gdbsupport/x86-xstate.h" |
1d509aa6 | 50 | #include "x86-tdep.h" |
4c5e7a93 | 51 | #include "expop.h" |
d2a7c97a | 52 | |
7ad10968 | 53 | #include "record.h" |
d02ed0bb | 54 | #include "record-full.h" |
22916b07 YQ |
55 | #include "target-descriptions.h" |
56 | #include "arch/i386.h" | |
90884b2b | 57 | |
6710bf39 SS |
58 | #include "ax.h" |
59 | #include "ax-gdb.h" | |
60 | ||
55aa24fb SDJ |
61 | #include "stap-probe.h" |
62 | #include "user-regs.h" | |
63 | #include "cli/cli-utils.h" | |
64 | #include "expression.h" | |
65 | #include "parser-defs.h" | |
66 | #include <ctype.h> | |
325fac50 | 67 | #include <algorithm> |
7d7571f0 | 68 | #include <unordered_set> |
c2fd7fae | 69 | #include "producer.h" |
55aa24fb | 70 | |
c4fc7f1b | 71 | /* Register names. */ |
c40e1eab | 72 | |
27087b7f | 73 | static const char * const i386_register_names[] = |
fc633446 MK |
74 | { |
75 | "eax", "ecx", "edx", "ebx", | |
76 | "esp", "ebp", "esi", "edi", | |
77 | "eip", "eflags", "cs", "ss", | |
78 | "ds", "es", "fs", "gs", | |
79 | "st0", "st1", "st2", "st3", | |
80 | "st4", "st5", "st6", "st7", | |
81 | "fctrl", "fstat", "ftag", "fiseg", | |
82 | "fioff", "foseg", "fooff", "fop", | |
83 | "xmm0", "xmm1", "xmm2", "xmm3", | |
84 | "xmm4", "xmm5", "xmm6", "xmm7", | |
85 | "mxcsr" | |
86 | }; | |
87 | ||
27087b7f | 88 | static const char * const i386_zmm_names[] = |
01f9f808 MS |
89 | { |
90 | "zmm0", "zmm1", "zmm2", "zmm3", | |
91 | "zmm4", "zmm5", "zmm6", "zmm7" | |
92 | }; | |
93 | ||
27087b7f | 94 | static const char * const i386_zmmh_names[] = |
01f9f808 MS |
95 | { |
96 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
97 | "zmm4h", "zmm5h", "zmm6h", "zmm7h" | |
98 | }; | |
99 | ||
27087b7f | 100 | static const char * const i386_k_names[] = |
01f9f808 MS |
101 | { |
102 | "k0", "k1", "k2", "k3", | |
103 | "k4", "k5", "k6", "k7" | |
104 | }; | |
105 | ||
27087b7f | 106 | static const char * const i386_ymm_names[] = |
c131fcee L |
107 | { |
108 | "ymm0", "ymm1", "ymm2", "ymm3", | |
109 | "ymm4", "ymm5", "ymm6", "ymm7", | |
110 | }; | |
111 | ||
27087b7f | 112 | static const char * const i386_ymmh_names[] = |
c131fcee L |
113 | { |
114 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
115 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
116 | }; | |
117 | ||
27087b7f | 118 | static const char * const i386_mpx_names[] = |
1dbcd68c WT |
119 | { |
120 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
121 | }; | |
122 | ||
27087b7f | 123 | static const char * const i386_pkeys_names[] = |
51547df6 MS |
124 | { |
125 | "pkru" | |
126 | }; | |
127 | ||
1dbcd68c WT |
128 | /* Register names for MPX pseudo-registers. */ |
129 | ||
27087b7f | 130 | static const char * const i386_bnd_names[] = |
1dbcd68c WT |
131 | { |
132 | "bnd0", "bnd1", "bnd2", "bnd3" | |
133 | }; | |
134 | ||
c4fc7f1b | 135 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 136 | |
27087b7f | 137 | static const char * const i386_mmx_names[] = |
28fc6740 AC |
138 | { |
139 | "mm0", "mm1", "mm2", "mm3", | |
140 | "mm4", "mm5", "mm6", "mm7" | |
141 | }; | |
c40e1eab | 142 | |
1ba53b71 L |
143 | /* Register names for byte pseudo-registers. */ |
144 | ||
27087b7f | 145 | static const char * const i386_byte_names[] = |
1ba53b71 L |
146 | { |
147 | "al", "cl", "dl", "bl", | |
148 | "ah", "ch", "dh", "bh" | |
149 | }; | |
150 | ||
151 | /* Register names for word pseudo-registers. */ | |
152 | ||
27087b7f | 153 | static const char * const i386_word_names[] = |
1ba53b71 L |
154 | { |
155 | "ax", "cx", "dx", "bx", | |
9cad29ac | 156 | "", "bp", "si", "di" |
1ba53b71 L |
157 | }; |
158 | ||
01f9f808 MS |
159 | /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have |
160 | 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, | |
161 | we have 16 upper ZMM regs that have to be handled differently. */ | |
162 | ||
163 | const int num_lower_zmm_regs = 16; | |
164 | ||
1ba53b71 | 165 | /* MMX register? */ |
c40e1eab | 166 | |
28fc6740 | 167 | static int |
5716833c | 168 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 169 | { |
1ba53b71 L |
170 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
171 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
172 | |
173 | if (mm0_regnum < 0) | |
174 | return 0; | |
175 | ||
1ba53b71 L |
176 | regnum -= mm0_regnum; |
177 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
178 | } | |
179 | ||
180 | /* Byte register? */ | |
181 | ||
182 | int | |
183 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
184 | { | |
185 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
186 | ||
187 | regnum -= tdep->al_regnum; | |
188 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
189 | } | |
190 | ||
191 | /* Word register? */ | |
192 | ||
193 | int | |
194 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
195 | { | |
196 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
197 | ||
198 | regnum -= tdep->ax_regnum; | |
199 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
200 | } | |
201 | ||
202 | /* Dword register? */ | |
203 | ||
204 | int | |
205 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
206 | { | |
207 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
208 | int eax_regnum = tdep->eax_regnum; | |
209 | ||
210 | if (eax_regnum < 0) | |
211 | return 0; | |
212 | ||
213 | regnum -= eax_regnum; | |
214 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
215 | } |
216 | ||
01f9f808 MS |
217 | /* AVX512 register? */ |
218 | ||
219 | int | |
220 | i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
221 | { | |
222 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
223 | int zmm0h_regnum = tdep->zmm0h_regnum; | |
224 | ||
225 | if (zmm0h_regnum < 0) | |
226 | return 0; | |
227 | ||
228 | regnum -= zmm0h_regnum; | |
229 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
230 | } | |
231 | ||
232 | int | |
233 | i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
234 | { | |
235 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236 | int zmm0_regnum = tdep->zmm0_regnum; | |
237 | ||
238 | if (zmm0_regnum < 0) | |
239 | return 0; | |
240 | ||
241 | regnum -= zmm0_regnum; | |
242 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
243 | } | |
244 | ||
245 | int | |
246 | i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) | |
247 | { | |
248 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
249 | int k0_regnum = tdep->k0_regnum; | |
250 | ||
251 | if (k0_regnum < 0) | |
252 | return 0; | |
253 | ||
254 | regnum -= k0_regnum; | |
255 | return regnum >= 0 && regnum < I387_NUM_K_REGS; | |
256 | } | |
257 | ||
9191d390 | 258 | static int |
c131fcee L |
259 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
260 | { | |
261 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
262 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
263 | ||
264 | if (ymm0h_regnum < 0) | |
265 | return 0; | |
266 | ||
267 | regnum -= ymm0h_regnum; | |
268 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
269 | } | |
270 | ||
271 | /* AVX register? */ | |
272 | ||
273 | int | |
274 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
275 | { | |
276 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
277 | int ymm0_regnum = tdep->ymm0_regnum; | |
278 | ||
279 | if (ymm0_regnum < 0) | |
280 | return 0; | |
281 | ||
282 | regnum -= ymm0_regnum; | |
283 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
284 | } | |
285 | ||
01f9f808 MS |
286 | static int |
287 | i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
288 | { | |
289 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
290 | int ymm16h_regnum = tdep->ymm16h_regnum; | |
291 | ||
292 | if (ymm16h_regnum < 0) | |
293 | return 0; | |
294 | ||
295 | regnum -= ymm16h_regnum; | |
296 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
297 | } | |
298 | ||
299 | int | |
300 | i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
301 | { | |
302 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
303 | int ymm16_regnum = tdep->ymm16_regnum; | |
304 | ||
305 | if (ymm16_regnum < 0) | |
306 | return 0; | |
307 | ||
308 | regnum -= ymm16_regnum; | |
309 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
310 | } | |
311 | ||
1dbcd68c WT |
312 | /* BND register? */ |
313 | ||
314 | int | |
315 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
316 | { | |
317 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
318 | int bnd0_regnum = tdep->bnd0_regnum; | |
319 | ||
320 | if (bnd0_regnum < 0) | |
321 | return 0; | |
322 | ||
323 | regnum -= bnd0_regnum; | |
324 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
325 | } | |
326 | ||
5716833c | 327 | /* SSE register? */ |
23a34459 | 328 | |
c131fcee L |
329 | int |
330 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 331 | { |
5716833c | 332 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 333 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 334 | |
c131fcee | 335 | if (num_xmm_regs == 0) |
5716833c MK |
336 | return 0; |
337 | ||
c131fcee L |
338 | regnum -= I387_XMM0_REGNUM (tdep); |
339 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
340 | } |
341 | ||
01f9f808 MS |
342 | /* XMM_512 register? */ |
343 | ||
344 | int | |
345 | i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
346 | { | |
347 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
348 | int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); | |
349 | ||
350 | if (num_xmm_avx512_regs == 0) | |
351 | return 0; | |
352 | ||
353 | regnum -= I387_XMM16_REGNUM (tdep); | |
354 | return regnum >= 0 && regnum < num_xmm_avx512_regs; | |
355 | } | |
356 | ||
5716833c MK |
357 | static int |
358 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 359 | { |
5716833c MK |
360 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
361 | ||
20a6ec49 | 362 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
363 | return 0; |
364 | ||
20a6ec49 | 365 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
366 | } |
367 | ||
5716833c | 368 | /* FP register? */ |
23a34459 AC |
369 | |
370 | int | |
20a6ec49 | 371 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 372 | { |
20a6ec49 MD |
373 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
374 | ||
375 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
376 | return 0; |
377 | ||
20a6ec49 MD |
378 | return (I387_ST0_REGNUM (tdep) <= regnum |
379 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
380 | } |
381 | ||
382 | int | |
20a6ec49 | 383 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 384 | { |
20a6ec49 MD |
385 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386 | ||
387 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
388 | return 0; |
389 | ||
20a6ec49 MD |
390 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
391 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
392 | } |
393 | ||
1dbcd68c WT |
394 | /* BNDr (raw) register? */ |
395 | ||
396 | static int | |
397 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
398 | { | |
399 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
400 | ||
401 | if (I387_BND0R_REGNUM (tdep) < 0) | |
402 | return 0; | |
403 | ||
404 | regnum -= tdep->bnd0r_regnum; | |
405 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
406 | } | |
407 | ||
408 | /* BND control register? */ | |
409 | ||
410 | static int | |
411 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
412 | { | |
413 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
414 | ||
415 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
416 | return 0; | |
417 | ||
418 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
419 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
420 | } | |
421 | ||
51547df6 MS |
422 | /* PKRU register? */ |
423 | ||
424 | bool | |
425 | i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum) | |
426 | { | |
427 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
428 | int pkru_regnum = tdep->pkru_regnum; | |
429 | ||
430 | if (pkru_regnum < 0) | |
431 | return false; | |
432 | ||
433 | regnum -= pkru_regnum; | |
434 | return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS; | |
435 | } | |
436 | ||
c131fcee L |
437 | /* Return the name of register REGNUM, or the empty string if it is |
438 | an anonymous register. */ | |
439 | ||
440 | static const char * | |
441 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
442 | { | |
443 | /* Hide the upper YMM registers. */ | |
444 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
445 | return ""; | |
446 | ||
01f9f808 MS |
447 | /* Hide the upper YMM16-31 registers. */ |
448 | if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) | |
449 | return ""; | |
450 | ||
451 | /* Hide the upper ZMM registers. */ | |
452 | if (i386_zmmh_regnum_p (gdbarch, regnum)) | |
453 | return ""; | |
454 | ||
c131fcee L |
455 | return tdesc_register_name (gdbarch, regnum); |
456 | } | |
457 | ||
30b0e2d8 | 458 | /* Return the name of register REGNUM. */ |
fc633446 | 459 | |
1ba53b71 | 460 | const char * |
90884b2b | 461 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 462 | { |
1ba53b71 | 463 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dbcd68c WT |
464 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
465 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
466 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
467 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
468 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
469 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
470 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
471 | return i386_zmm_names[regnum - tdep->zmm0_regnum]; | |
1ba53b71 L |
472 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
473 | return i386_byte_names[regnum - tdep->al_regnum]; | |
474 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
475 | return i386_word_names[regnum - tdep->ax_regnum]; | |
476 | ||
477 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
478 | } |
479 | ||
c4fc7f1b | 480 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
481 | number used by GDB. */ |
482 | ||
8201327c | 483 | static int |
d3f73121 | 484 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 485 | { |
20a6ec49 MD |
486 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
487 | ||
c4fc7f1b MK |
488 | /* This implements what GCC calls the "default" register map |
489 | (dbx_register_map[]). */ | |
490 | ||
85540d8c MK |
491 | if (reg >= 0 && reg <= 7) |
492 | { | |
9872ad24 | 493 | /* General-purpose registers. The debug info calls %ebp |
dda83cd7 | 494 | register 4, and %esp register 5. */ |
9872ad24 | 495 | if (reg == 4) |
dda83cd7 | 496 | return 5; |
9872ad24 | 497 | else if (reg == 5) |
dda83cd7 | 498 | return 4; |
9872ad24 | 499 | else return reg; |
85540d8c MK |
500 | } |
501 | else if (reg >= 12 && reg <= 19) | |
502 | { | |
503 | /* Floating-point registers. */ | |
20a6ec49 | 504 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
505 | } |
506 | else if (reg >= 21 && reg <= 28) | |
507 | { | |
508 | /* SSE registers. */ | |
c131fcee L |
509 | int ymm0_regnum = tdep->ymm0_regnum; |
510 | ||
511 | if (ymm0_regnum >= 0 | |
512 | && i386_xmm_regnum_p (gdbarch, reg)) | |
513 | return reg - 21 + ymm0_regnum; | |
514 | else | |
515 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
516 | } |
517 | else if (reg >= 29 && reg <= 36) | |
518 | { | |
519 | /* MMX registers. */ | |
20a6ec49 | 520 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
521 | } |
522 | ||
523 | /* This will hopefully provoke a warning. */ | |
f6efe3f8 | 524 | return gdbarch_num_cooked_regs (gdbarch); |
85540d8c MK |
525 | } |
526 | ||
0fde2c53 | 527 | /* Convert SVR4 DWARF register number REG to the appropriate register number |
c4fc7f1b | 528 | used by GDB. */ |
85540d8c | 529 | |
8201327c | 530 | static int |
0fde2c53 | 531 | i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 532 | { |
20a6ec49 MD |
533 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
534 | ||
c4fc7f1b MK |
535 | /* This implements the GCC register map that tries to be compatible |
536 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
537 | ||
538 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
539 | numbers the floating point registers differently. */ |
540 | if (reg >= 0 && reg <= 9) | |
541 | { | |
acd5c798 | 542 | /* General-purpose registers. */ |
85540d8c MK |
543 | return reg; |
544 | } | |
545 | else if (reg >= 11 && reg <= 18) | |
546 | { | |
547 | /* Floating-point registers. */ | |
20a6ec49 | 548 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 549 | } |
c6f4c129 | 550 | else if (reg >= 21 && reg <= 36) |
85540d8c | 551 | { |
c4fc7f1b | 552 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 553 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
554 | } |
555 | ||
c6f4c129 JB |
556 | switch (reg) |
557 | { | |
20a6ec49 MD |
558 | case 37: return I387_FCTRL_REGNUM (tdep); |
559 | case 38: return I387_FSTAT_REGNUM (tdep); | |
560 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
561 | case 40: return I386_ES_REGNUM; |
562 | case 41: return I386_CS_REGNUM; | |
563 | case 42: return I386_SS_REGNUM; | |
564 | case 43: return I386_DS_REGNUM; | |
565 | case 44: return I386_FS_REGNUM; | |
566 | case 45: return I386_GS_REGNUM; | |
567 | } | |
568 | ||
0fde2c53 DE |
569 | return -1; |
570 | } | |
571 | ||
572 | /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return | |
573 | num_regs + num_pseudo_regs for other debug formats. */ | |
574 | ||
8f10c932 | 575 | int |
0fde2c53 DE |
576 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
577 | { | |
578 | int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg); | |
579 | ||
580 | if (regnum == -1) | |
f6efe3f8 | 581 | return gdbarch_num_cooked_regs (gdbarch); |
0fde2c53 | 582 | return regnum; |
85540d8c | 583 | } |
5716833c | 584 | |
fc338970 | 585 | \f |
917317f4 | 586 | |
fc338970 MK |
587 | /* This is the variable that is set with "set disassembly-flavor", and |
588 | its legitimate values. */ | |
53904c9e AC |
589 | static const char att_flavor[] = "att"; |
590 | static const char intel_flavor[] = "intel"; | |
40478521 | 591 | static const char *const valid_flavors[] = |
c5aa993b | 592 | { |
c906108c SS |
593 | att_flavor, |
594 | intel_flavor, | |
595 | NULL | |
596 | }; | |
53904c9e | 597 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 598 | \f |
c906108c | 599 | |
acd5c798 MK |
600 | /* Use the program counter to determine the contents and size of a |
601 | breakpoint instruction. Return a pointer to a string of bytes that | |
602 | encode a breakpoint instruction, store the length of the string in | |
603 | *LEN and optionally adjust *PC to point to the correct memory | |
604 | location for inserting the breakpoint. | |
c906108c | 605 | |
acd5c798 MK |
606 | On the i386 we have a single breakpoint that fits in a single byte |
607 | and can be inserted anywhere. | |
c906108c | 608 | |
acd5c798 | 609 | This function is 64-bit safe. */ |
63c0089f | 610 | |
04180708 YQ |
611 | constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */ |
612 | ||
613 | typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint; | |
63c0089f | 614 | |
237fc4c9 PA |
615 | \f |
616 | /* Displaced instruction handling. */ | |
617 | ||
1903f0e6 DE |
618 | /* Skip the legacy instruction prefixes in INSN. |
619 | Not all prefixes are valid for any particular insn | |
620 | but we needn't care, the insn will fault if it's invalid. | |
621 | The result is a pointer to the first opcode byte, | |
622 | or NULL if we run off the end of the buffer. */ | |
623 | ||
624 | static gdb_byte * | |
625 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
626 | { | |
627 | gdb_byte *end = insn + max_len; | |
628 | ||
629 | while (insn < end) | |
630 | { | |
631 | switch (*insn) | |
632 | { | |
633 | case DATA_PREFIX_OPCODE: | |
634 | case ADDR_PREFIX_OPCODE: | |
635 | case CS_PREFIX_OPCODE: | |
636 | case DS_PREFIX_OPCODE: | |
637 | case ES_PREFIX_OPCODE: | |
638 | case FS_PREFIX_OPCODE: | |
639 | case GS_PREFIX_OPCODE: | |
640 | case SS_PREFIX_OPCODE: | |
641 | case LOCK_PREFIX_OPCODE: | |
642 | case REPE_PREFIX_OPCODE: | |
643 | case REPNE_PREFIX_OPCODE: | |
644 | ++insn; | |
645 | continue; | |
646 | default: | |
647 | return insn; | |
648 | } | |
649 | } | |
650 | ||
651 | return NULL; | |
652 | } | |
237fc4c9 PA |
653 | |
654 | static int | |
1903f0e6 | 655 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 656 | { |
1777feb0 | 657 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
658 | if (insn[0] == 0xea) |
659 | return 1; | |
660 | ||
661 | if (insn[0] == 0xff) | |
662 | { | |
1777feb0 | 663 | /* jump near, absolute indirect (/4). */ |
237fc4c9 | 664 | if ((insn[1] & 0x38) == 0x20) |
dda83cd7 | 665 | return 1; |
237fc4c9 | 666 | |
1777feb0 | 667 | /* jump far, absolute indirect (/5). */ |
237fc4c9 | 668 | if ((insn[1] & 0x38) == 0x28) |
dda83cd7 | 669 | return 1; |
237fc4c9 PA |
670 | } |
671 | ||
672 | return 0; | |
673 | } | |
674 | ||
c2170eef MM |
675 | /* Return non-zero if INSN is a jump, zero otherwise. */ |
676 | ||
677 | static int | |
678 | i386_jmp_p (const gdb_byte *insn) | |
679 | { | |
680 | /* jump short, relative. */ | |
681 | if (insn[0] == 0xeb) | |
682 | return 1; | |
683 | ||
684 | /* jump near, relative. */ | |
685 | if (insn[0] == 0xe9) | |
686 | return 1; | |
687 | ||
688 | return i386_absolute_jmp_p (insn); | |
689 | } | |
690 | ||
237fc4c9 | 691 | static int |
1903f0e6 | 692 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 693 | { |
1777feb0 | 694 | /* call far, absolute. */ |
237fc4c9 PA |
695 | if (insn[0] == 0x9a) |
696 | return 1; | |
697 | ||
698 | if (insn[0] == 0xff) | |
699 | { | |
1777feb0 | 700 | /* Call near, absolute indirect (/2). */ |
237fc4c9 | 701 | if ((insn[1] & 0x38) == 0x10) |
dda83cd7 | 702 | return 1; |
237fc4c9 | 703 | |
1777feb0 | 704 | /* Call far, absolute indirect (/3). */ |
237fc4c9 | 705 | if ((insn[1] & 0x38) == 0x18) |
dda83cd7 | 706 | return 1; |
237fc4c9 PA |
707 | } |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
712 | static int | |
1903f0e6 | 713 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
714 | { |
715 | switch (insn[0]) | |
716 | { | |
1777feb0 | 717 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 718 | case 0xc3: /* ret near */ |
1777feb0 | 719 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
720 | case 0xcb: /* ret far */ |
721 | case 0xcf: /* iret */ | |
722 | return 1; | |
723 | ||
724 | default: | |
725 | return 0; | |
726 | } | |
727 | } | |
728 | ||
729 | static int | |
1903f0e6 | 730 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
731 | { |
732 | if (i386_absolute_call_p (insn)) | |
733 | return 1; | |
734 | ||
1777feb0 | 735 | /* call near, relative. */ |
237fc4c9 PA |
736 | if (insn[0] == 0xe8) |
737 | return 1; | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
237fc4c9 PA |
742 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
743 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 744 | |
237fc4c9 | 745 | static int |
b55078be | 746 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 747 | { |
9a7f938f JK |
748 | /* Is it 'int $0x80'? */ |
749 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
750 | /* Or is it 'sysenter'? */ | |
751 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
752 | /* Or is it 'syscall'? */ | |
753 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
754 | { |
755 | *lengthp = 2; | |
756 | return 1; | |
757 | } | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
c2170eef MM |
762 | /* The gdbarch insn_is_call method. */ |
763 | ||
764 | static int | |
765 | i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
766 | { | |
767 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
768 | ||
769 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
770 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
771 | ||
772 | return i386_call_p (insn); | |
773 | } | |
774 | ||
775 | /* The gdbarch insn_is_ret method. */ | |
776 | ||
777 | static int | |
778 | i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
779 | { | |
780 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
781 | ||
782 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
783 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
784 | ||
785 | return i386_ret_p (insn); | |
786 | } | |
787 | ||
788 | /* The gdbarch insn_is_jump method. */ | |
789 | ||
790 | static int | |
791 | i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
792 | { | |
793 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
794 | ||
795 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
796 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
797 | ||
798 | return i386_jmp_p (insn); | |
799 | } | |
800 | ||
c2508e90 | 801 | /* Some kernels may run one past a syscall insn, so we have to cope. */ |
b55078be | 802 | |
1152d984 | 803 | displaced_step_copy_insn_closure_up |
b55078be DE |
804 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, |
805 | CORE_ADDR from, CORE_ADDR to, | |
806 | struct regcache *regs) | |
807 | { | |
808 | size_t len = gdbarch_max_insn_length (gdbarch); | |
1152d984 SM |
809 | std::unique_ptr<i386_displaced_step_copy_insn_closure> closure |
810 | (new i386_displaced_step_copy_insn_closure (len)); | |
cfba9872 | 811 | gdb_byte *buf = closure->buf.data (); |
b55078be DE |
812 | |
813 | read_memory (from, buf, len); | |
814 | ||
815 | /* GDB may get control back after the insn after the syscall. | |
816 | Presumably this is a kernel bug. | |
817 | If this is a syscall, make sure there's a nop afterwards. */ | |
818 | { | |
819 | int syscall_length; | |
820 | gdb_byte *insn; | |
821 | ||
822 | insn = i386_skip_prefixes (buf, len); | |
823 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
824 | insn[syscall_length] = NOP_OPCODE; | |
825 | } | |
826 | ||
827 | write_memory (to, buf, len); | |
828 | ||
136821d9 | 829 | displaced_debug_printf ("%s->%s: %s", |
dda83cd7 | 830 | paddress (gdbarch, from), paddress (gdbarch, to), |
136821d9 | 831 | displaced_step_dump_bytes (buf, len).c_str ()); |
b55078be | 832 | |
6d0cf446 | 833 | /* This is a work around for a problem with g++ 4.8. */ |
1152d984 | 834 | return displaced_step_copy_insn_closure_up (closure.release ()); |
b55078be DE |
835 | } |
836 | ||
237fc4c9 PA |
837 | /* Fix up the state of registers and memory after having single-stepped |
838 | a displaced instruction. */ | |
1903f0e6 | 839 | |
237fc4c9 PA |
840 | void |
841 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 842 | struct displaced_step_copy_insn_closure *closure_, |
dda83cd7 SM |
843 | CORE_ADDR from, CORE_ADDR to, |
844 | struct regcache *regs) | |
237fc4c9 | 845 | { |
e17a4113 UW |
846 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
847 | ||
237fc4c9 PA |
848 | /* The offset we applied to the instruction's address. |
849 | This could well be negative (when viewed as a signed 32-bit | |
850 | value), but ULONGEST won't reflect that, so take care when | |
851 | applying it. */ | |
852 | ULONGEST insn_offset = to - from; | |
853 | ||
1152d984 SM |
854 | i386_displaced_step_copy_insn_closure *closure |
855 | = (i386_displaced_step_copy_insn_closure *) closure_; | |
cfba9872 | 856 | gdb_byte *insn = closure->buf.data (); |
1903f0e6 DE |
857 | /* The start of the insn, needed in case we see some prefixes. */ |
858 | gdb_byte *insn_start = insn; | |
237fc4c9 | 859 | |
136821d9 SM |
860 | displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...", |
861 | paddress (gdbarch, from), paddress (gdbarch, to), | |
862 | insn[0], insn[1]); | |
237fc4c9 PA |
863 | |
864 | /* The list of issues to contend with here is taken from | |
865 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
866 | Yay for Free Software! */ | |
867 | ||
868 | /* Relocate the %eip, if necessary. */ | |
869 | ||
1903f0e6 DE |
870 | /* The instruction recognizers we use assume any leading prefixes |
871 | have been skipped. */ | |
872 | { | |
873 | /* This is the size of the buffer in closure. */ | |
874 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
875 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
876 | /* If there are too many prefixes, just ignore the insn. | |
877 | It will fault when run. */ | |
878 | if (opcode != NULL) | |
879 | insn = opcode; | |
880 | } | |
881 | ||
237fc4c9 PA |
882 | /* Except in the case of absolute or indirect jump or call |
883 | instructions, or a return instruction, the new eip is relative to | |
884 | the displaced instruction; make it relative. Well, signal | |
885 | handler returns don't need relocation either, but we use the | |
886 | value of %eip to recognize those; see below. */ | |
887 | if (! i386_absolute_jmp_p (insn) | |
888 | && ! i386_absolute_call_p (insn) | |
889 | && ! i386_ret_p (insn)) | |
890 | { | |
891 | ULONGEST orig_eip; | |
b55078be | 892 | int insn_len; |
237fc4c9 PA |
893 | |
894 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
895 | ||
896 | /* A signal trampoline system call changes the %eip, resuming | |
dda83cd7 SM |
897 | execution of the main program after the signal handler has |
898 | returned. That makes them like 'return' instructions; we | |
899 | shouldn't relocate %eip. | |
900 | ||
901 | But most system calls don't, and we do need to relocate %eip. | |
902 | ||
903 | Our heuristic for distinguishing these cases: if stepping | |
904 | over the system call instruction left control directly after | |
905 | the instruction, the we relocate --- control almost certainly | |
906 | doesn't belong in the displaced copy. Otherwise, we assume | |
907 | the instruction has put control where it belongs, and leave | |
908 | it unrelocated. Goodness help us if there are PC-relative | |
909 | system calls. */ | |
237fc4c9 | 910 | if (i386_syscall_p (insn, &insn_len) |
dda83cd7 | 911 | && orig_eip != to + (insn - insn_start) + insn_len |
b55078be DE |
912 | /* GDB can get control back after the insn after the syscall. |
913 | Presumably this is a kernel bug. | |
914 | i386_displaced_step_copy_insn ensures its a nop, | |
915 | we add one to the length for it. */ | |
136821d9 SM |
916 | && orig_eip != to + (insn - insn_start) + insn_len + 1) |
917 | displaced_debug_printf ("syscall changed %%eip; not relocating"); | |
237fc4c9 | 918 | else |
dda83cd7 SM |
919 | { |
920 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
237fc4c9 | 921 | |
1903f0e6 DE |
922 | /* If we just stepped over a breakpoint insn, we don't backup |
923 | the pc on purpose; this is to match behaviour without | |
924 | stepping. */ | |
237fc4c9 | 925 | |
dda83cd7 | 926 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); |
237fc4c9 | 927 | |
136821d9 SM |
928 | displaced_debug_printf ("relocated %%eip from %s to %s", |
929 | paddress (gdbarch, orig_eip), | |
930 | paddress (gdbarch, eip)); | |
dda83cd7 | 931 | } |
237fc4c9 PA |
932 | } |
933 | ||
934 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
935 | pushed value, and should be cleared. We'll leave this for later, | |
936 | since GDB already messes up the TF flag when stepping over a | |
937 | pushfl. */ | |
938 | ||
939 | /* If the instruction was a call, the return address now atop the | |
940 | stack is the address following the copied instruction. We need | |
941 | to make it the address following the original instruction. */ | |
942 | if (i386_call_p (insn)) | |
943 | { | |
944 | ULONGEST esp; | |
945 | ULONGEST retaddr; | |
946 | const ULONGEST retaddr_len = 4; | |
947 | ||
948 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 949 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 950 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 951 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 | 952 | |
136821d9 SM |
953 | displaced_debug_printf ("relocated return addr at %s to %s", |
954 | paddress (gdbarch, esp), | |
955 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
956 | } |
957 | } | |
dde08ee1 PA |
958 | |
959 | static void | |
960 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
961 | { | |
962 | target_write_memory (*to, buf, len); | |
963 | *to += len; | |
964 | } | |
965 | ||
966 | static void | |
967 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
968 | CORE_ADDR *to, CORE_ADDR oldloc) | |
969 | { | |
970 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
971 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
972 | int offset = 0, rel32, newrel; | |
973 | int insn_length; | |
974 | gdb_byte *insn = buf; | |
975 | ||
976 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
977 | ||
978 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
979 | I386_MAX_INSN_LEN, oldloc); | |
980 | ||
981 | /* Get past the prefixes. */ | |
982 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
983 | ||
984 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
985 | the address pushed being the location where the original call in | |
986 | the user program would return to. */ | |
987 | if (insn[0] == 0xe8) | |
988 | { | |
989 | gdb_byte push_buf[16]; | |
990 | unsigned int ret_addr; | |
991 | ||
992 | /* Where "ret" in the original code will return to. */ | |
993 | ret_addr = oldloc + insn_length; | |
1777feb0 | 994 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 995 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
996 | /* Push the push. */ |
997 | append_insns (to, 5, push_buf); | |
998 | ||
999 | /* Convert the relative call to a relative jump. */ | |
1000 | insn[0] = 0xe9; | |
1001 | ||
1002 | /* Adjust the destination offset. */ | |
1003 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
1004 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
1005 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
1006 | ||
136821d9 SM |
1007 | displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s", |
1008 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1009 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1010 | |
1011 | /* Write the adjusted jump into its displaced location. */ | |
1012 | append_insns (to, 5, insn); | |
1013 | return; | |
1014 | } | |
1015 | ||
1016 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
1017 | handled above. */ | |
1018 | if (insn[0] == 0xe9) | |
1019 | offset = 1; | |
1020 | /* Adjust conditional jumps. */ | |
1021 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1022 | offset = 2; | |
1023 | ||
1024 | if (offset) | |
1025 | { | |
1026 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1027 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1028 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
136821d9 SM |
1029 | displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s", |
1030 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1031 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1032 | } |
1033 | ||
1034 | /* Write the adjusted instructions into their displaced | |
1035 | location. */ | |
1036 | append_insns (to, insn_length, buf); | |
1037 | } | |
1038 | ||
fc338970 | 1039 | \f |
acd5c798 MK |
1040 | #ifdef I386_REGNO_TO_SYMMETRY |
1041 | #error "The Sequent Symmetry is no longer supported." | |
1042 | #endif | |
c906108c | 1043 | |
acd5c798 MK |
1044 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
1045 | and %esp "belong" to the calling function. Therefore these | |
1046 | registers should be saved if they're going to be modified. */ | |
c906108c | 1047 | |
acd5c798 MK |
1048 | /* The maximum number of saved registers. This should include all |
1049 | registers mentioned above, and %eip. */ | |
a3386186 | 1050 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
1051 | |
1052 | struct i386_frame_cache | |
c906108c | 1053 | { |
acd5c798 MK |
1054 | /* Base address. */ |
1055 | CORE_ADDR base; | |
8fbca658 | 1056 | int base_p; |
772562f8 | 1057 | LONGEST sp_offset; |
acd5c798 MK |
1058 | CORE_ADDR pc; |
1059 | ||
fd13a04a AC |
1060 | /* Saved registers. */ |
1061 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 1062 | CORE_ADDR saved_sp; |
e0c62198 | 1063 | int saved_sp_reg; |
acd5c798 MK |
1064 | int pc_in_eax; |
1065 | ||
1066 | /* Stack space reserved for local variables. */ | |
1067 | long locals; | |
1068 | }; | |
1069 | ||
1070 | /* Allocate and initialize a frame cache. */ | |
1071 | ||
1072 | static struct i386_frame_cache * | |
fd13a04a | 1073 | i386_alloc_frame_cache (void) |
acd5c798 MK |
1074 | { |
1075 | struct i386_frame_cache *cache; | |
1076 | int i; | |
1077 | ||
1078 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
1079 | ||
1080 | /* Base address. */ | |
8fbca658 | 1081 | cache->base_p = 0; |
acd5c798 MK |
1082 | cache->base = 0; |
1083 | cache->sp_offset = -4; | |
1084 | cache->pc = 0; | |
1085 | ||
fd13a04a AC |
1086 | /* Saved registers. We initialize these to -1 since zero is a valid |
1087 | offset (that's where %ebp is supposed to be stored). */ | |
1088 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
1089 | cache->saved_regs[i] = -1; | |
acd5c798 | 1090 | cache->saved_sp = 0; |
e0c62198 | 1091 | cache->saved_sp_reg = -1; |
acd5c798 MK |
1092 | cache->pc_in_eax = 0; |
1093 | ||
1094 | /* Frameless until proven otherwise. */ | |
1095 | cache->locals = -1; | |
1096 | ||
1097 | return cache; | |
1098 | } | |
c906108c | 1099 | |
acd5c798 MK |
1100 | /* If the instruction at PC is a jump, return the address of its |
1101 | target. Otherwise, return PC. */ | |
c906108c | 1102 | |
acd5c798 | 1103 | static CORE_ADDR |
e17a4113 | 1104 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 1105 | { |
e17a4113 | 1106 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1107 | gdb_byte op; |
acd5c798 MK |
1108 | long delta = 0; |
1109 | int data16 = 0; | |
c906108c | 1110 | |
0865b04a | 1111 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1112 | return pc; |
1113 | ||
acd5c798 | 1114 | if (op == 0x66) |
c906108c | 1115 | { |
c906108c | 1116 | data16 = 1; |
0865b04a YQ |
1117 | |
1118 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
1119 | } |
1120 | ||
acd5c798 | 1121 | switch (op) |
c906108c SS |
1122 | { |
1123 | case 0xe9: | |
fc338970 | 1124 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
1125 | if (data16) |
1126 | { | |
e17a4113 | 1127 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 1128 | |
fc338970 | 1129 | /* Include the size of the jmp instruction (including the |
dda83cd7 | 1130 | 0x66 prefix). */ |
acd5c798 | 1131 | delta += 4; |
c906108c SS |
1132 | } |
1133 | else | |
1134 | { | |
e17a4113 | 1135 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 1136 | |
acd5c798 MK |
1137 | /* Include the size of the jmp instruction. */ |
1138 | delta += 5; | |
c906108c SS |
1139 | } |
1140 | break; | |
1141 | case 0xeb: | |
fc338970 | 1142 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 1143 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 1144 | |
acd5c798 | 1145 | delta += data16 + 2; |
c906108c SS |
1146 | break; |
1147 | } | |
c906108c | 1148 | |
acd5c798 MK |
1149 | return pc + delta; |
1150 | } | |
fc338970 | 1151 | |
acd5c798 MK |
1152 | /* Check whether PC points at a prologue for a function returning a |
1153 | structure or union. If so, it updates CACHE and returns the | |
1154 | address of the first instruction after the code sequence that | |
1155 | removes the "hidden" argument from the stack or CURRENT_PC, | |
1156 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 1157 | |
acd5c798 MK |
1158 | static CORE_ADDR |
1159 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
1160 | struct i386_frame_cache *cache) | |
c906108c | 1161 | { |
acd5c798 MK |
1162 | /* Functions that return a structure or union start with: |
1163 | ||
dda83cd7 SM |
1164 | popl %eax 0x58 |
1165 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
acd5c798 MK |
1166 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 |
1167 | ||
1168 | (the System V compiler puts out the second `xchg' instruction, | |
1169 | and the assembler doesn't try to optimize it, so the 'sib' form | |
1170 | gets generated). This sequence is used to get the address of the | |
1171 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
1172 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
1173 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
1174 | gdb_byte buf[4]; | |
1175 | gdb_byte op; | |
c906108c | 1176 | |
acd5c798 MK |
1177 | if (current_pc <= pc) |
1178 | return pc; | |
1179 | ||
0865b04a | 1180 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1181 | return pc; |
c906108c | 1182 | |
acd5c798 MK |
1183 | if (op != 0x58) /* popl %eax */ |
1184 | return pc; | |
c906108c | 1185 | |
0865b04a | 1186 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1187 | return pc; |
1188 | ||
acd5c798 MK |
1189 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1190 | return pc; | |
c906108c | 1191 | |
acd5c798 | 1192 | if (current_pc == pc) |
c906108c | 1193 | { |
acd5c798 MK |
1194 | cache->sp_offset += 4; |
1195 | return current_pc; | |
c906108c SS |
1196 | } |
1197 | ||
acd5c798 | 1198 | if (current_pc == pc + 1) |
c906108c | 1199 | { |
acd5c798 MK |
1200 | cache->pc_in_eax = 1; |
1201 | return current_pc; | |
1202 | } | |
1203 | ||
1204 | if (buf[1] == proto1[1]) | |
1205 | return pc + 4; | |
1206 | else | |
1207 | return pc + 5; | |
1208 | } | |
1209 | ||
1210 | static CORE_ADDR | |
1211 | i386_skip_probe (CORE_ADDR pc) | |
1212 | { | |
1213 | /* A function may start with | |
fc338970 | 1214 | |
dda83cd7 SM |
1215 | pushl constant |
1216 | call _probe | |
acd5c798 | 1217 | addl $4, %esp |
fc338970 | 1218 | |
acd5c798 MK |
1219 | followed by |
1220 | ||
dda83cd7 | 1221 | pushl %ebp |
fc338970 | 1222 | |
acd5c798 | 1223 | etc. */ |
63c0089f MK |
1224 | gdb_byte buf[8]; |
1225 | gdb_byte op; | |
fc338970 | 1226 | |
0865b04a | 1227 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1228 | return pc; |
acd5c798 MK |
1229 | |
1230 | if (op == 0x68 || op == 0x6a) | |
1231 | { | |
1232 | int delta; | |
c906108c | 1233 | |
acd5c798 MK |
1234 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1235 | four-byte operand, depending on the opcode. */ | |
c906108c | 1236 | if (op == 0x68) |
acd5c798 | 1237 | delta = 5; |
c906108c | 1238 | else |
acd5c798 | 1239 | delta = 2; |
c906108c | 1240 | |
acd5c798 MK |
1241 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1242 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1243 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1244 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1245 | pc += delta + sizeof (buf); |
c906108c SS |
1246 | } |
1247 | ||
acd5c798 MK |
1248 | return pc; |
1249 | } | |
1250 | ||
92dd43fa MK |
1251 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1252 | stack pointer. Check whether PC points to such code, and update | |
1253 | CACHE accordingly. Return the first instruction after the code | |
1254 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1255 | recognize the code, return PC. */ | |
1256 | ||
1257 | static CORE_ADDR | |
1258 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1259 | struct i386_frame_cache *cache) | |
1260 | { | |
e0c62198 L |
1261 | /* There are 2 code sequences to re-align stack before the frame |
1262 | gets set up: | |
1263 | ||
1264 | 1. Use a caller-saved saved register: | |
1265 | ||
1266 | leal 4(%esp), %reg | |
1267 | andl $-XXX, %esp | |
1268 | pushl -4(%reg) | |
1269 | ||
1270 | 2. Use a callee-saved saved register: | |
1271 | ||
1272 | pushl %reg | |
1273 | leal 8(%esp), %reg | |
1274 | andl $-XXX, %esp | |
1275 | pushl -4(%reg) | |
1276 | ||
1277 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1278 | ||
24b21115 SM |
1279 | 0x83 0xe4 0xf0 andl $-16, %esp |
1280 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
e0c62198 L |
1281 | */ |
1282 | ||
1283 | gdb_byte buf[14]; | |
1284 | int reg; | |
1285 | int offset, offset_and; | |
1286 | static int regnums[8] = { | |
1287 | I386_EAX_REGNUM, /* %eax */ | |
1288 | I386_ECX_REGNUM, /* %ecx */ | |
1289 | I386_EDX_REGNUM, /* %edx */ | |
1290 | I386_EBX_REGNUM, /* %ebx */ | |
1291 | I386_ESP_REGNUM, /* %esp */ | |
1292 | I386_EBP_REGNUM, /* %ebp */ | |
1293 | I386_ESI_REGNUM, /* %esi */ | |
1294 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1295 | }; |
92dd43fa | 1296 | |
0865b04a | 1297 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1298 | return pc; |
1299 | ||
1300 | /* Check caller-saved saved register. The first instruction has | |
1301 | to be "leal 4(%esp), %reg". */ | |
1302 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1303 | { | |
1304 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1305 | if ((buf[1] & 0xc7) != 0x44) | |
1306 | return pc; | |
1307 | ||
1308 | /* REG has register number. */ | |
1309 | reg = (buf[1] >> 3) & 7; | |
1310 | offset = 4; | |
1311 | } | |
1312 | else | |
1313 | { | |
1314 | /* Check callee-saved saved register. The first instruction | |
1315 | has to be "pushl %reg". */ | |
1316 | if ((buf[0] & 0xf8) != 0x50) | |
1317 | return pc; | |
1318 | ||
1319 | /* Get register. */ | |
1320 | reg = buf[0] & 0x7; | |
1321 | ||
1322 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1323 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1324 | return pc; | |
1325 | ||
1326 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1327 | if ((buf[2] & 0xc7) != 0x44) | |
1328 | return pc; | |
1329 | ||
1330 | /* REG has register number. Registers in pushl and leal have to | |
1331 | be the same. */ | |
1332 | if (reg != ((buf[2] >> 3) & 7)) | |
1333 | return pc; | |
1334 | ||
1335 | offset = 5; | |
1336 | } | |
1337 | ||
1338 | /* Rigister can't be %esp nor %ebp. */ | |
1339 | if (reg == 4 || reg == 5) | |
1340 | return pc; | |
1341 | ||
1342 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1343 | if (buf[offset + 1] != 0xe4 | |
1344 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1345 | return pc; | |
1346 | ||
1347 | offset_and = offset; | |
1348 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1349 | ||
1350 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1351 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1352 | if (buf[offset] != 0xff | |
1353 | || buf[offset + 2] != 0xfc | |
1354 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1355 | return pc; | |
1356 | ||
1357 | /* R/M has register. Registers in leal and pushl have to be the | |
1358 | same. */ | |
1359 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1360 | return pc; |
1361 | ||
e0c62198 L |
1362 | if (current_pc > pc + offset_and) |
1363 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1364 | |
325fac50 | 1365 | return std::min (pc + offset + 3, current_pc); |
92dd43fa MK |
1366 | } |
1367 | ||
37bdc87e | 1368 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1369 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1370 | |
1371 | /* Instruction description. */ | |
1372 | struct i386_insn | |
1373 | { | |
1374 | size_t len; | |
237fc4c9 PA |
1375 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1376 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1377 | }; |
1378 | ||
a3fcb948 | 1379 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1380 | |
a3fcb948 JG |
1381 | static int |
1382 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1383 | { |
63c0089f | 1384 | gdb_byte op; |
37bdc87e | 1385 | |
0865b04a | 1386 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1387 | return 0; |
37bdc87e | 1388 | |
a3fcb948 | 1389 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1390 | { |
a3fcb948 JG |
1391 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1392 | int insn_matched = 1; | |
1393 | size_t i; | |
37bdc87e | 1394 | |
a3fcb948 JG |
1395 | gdb_assert (pattern.len > 1); |
1396 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1397 | |
0865b04a | 1398 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1399 | return 0; |
613e8135 | 1400 | |
a3fcb948 JG |
1401 | for (i = 1; i < pattern.len; i++) |
1402 | { | |
1403 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1404 | insn_matched = 0; | |
37bdc87e | 1405 | } |
a3fcb948 JG |
1406 | return insn_matched; |
1407 | } | |
1408 | return 0; | |
1409 | } | |
1410 | ||
1411 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1412 | the first instruction description that matches. Otherwise, return | |
1413 | NULL. */ | |
1414 | ||
1415 | static struct i386_insn * | |
1416 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1417 | { | |
1418 | struct i386_insn *pattern; | |
1419 | ||
1420 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1421 | { | |
1422 | if (i386_match_pattern (pc, *pattern)) | |
1423 | return pattern; | |
37bdc87e MK |
1424 | } |
1425 | ||
1426 | return NULL; | |
1427 | } | |
1428 | ||
a3fcb948 JG |
1429 | /* Return whether PC points inside a sequence of instructions that |
1430 | matches INSN_PATTERNS. */ | |
1431 | ||
1432 | static int | |
1433 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1434 | { | |
1435 | CORE_ADDR current_pc; | |
1436 | int ix, i; | |
a3fcb948 JG |
1437 | struct i386_insn *insn; |
1438 | ||
1439 | insn = i386_match_insn (pc, insn_patterns); | |
1440 | if (insn == NULL) | |
1441 | return 0; | |
1442 | ||
8bbdd3f4 | 1443 | current_pc = pc; |
a3fcb948 JG |
1444 | ix = insn - insn_patterns; |
1445 | for (i = ix - 1; i >= 0; i--) | |
1446 | { | |
8bbdd3f4 MK |
1447 | current_pc -= insn_patterns[i].len; |
1448 | ||
a3fcb948 JG |
1449 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1450 | return 0; | |
a3fcb948 JG |
1451 | } |
1452 | ||
1453 | current_pc = pc + insn->len; | |
1454 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1455 | { | |
1456 | if (!i386_match_pattern (current_pc, *insn)) | |
1457 | return 0; | |
1458 | ||
1459 | current_pc += insn->len; | |
1460 | } | |
1461 | ||
1462 | return 1; | |
1463 | } | |
1464 | ||
37bdc87e MK |
1465 | /* Some special instructions that might be migrated by GCC into the |
1466 | part of the prologue that sets up the new stack frame. Because the | |
1467 | stack frame hasn't been setup yet, no registers have been saved | |
1468 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1469 | touched. */ | |
1470 | ||
6bd434d6 | 1471 | static i386_insn i386_frame_setup_skip_insns[] = |
37bdc87e | 1472 | { |
1777feb0 | 1473 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1474 | |
1475 | ??? Should we handle 16-bit operand-sizes here? */ | |
1476 | ||
1477 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1478 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1479 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1480 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1481 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1482 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1483 | { 5, { 0xb8 }, { 0xfe } }, | |
1484 | /* `movl imm32, %edx' */ | |
1485 | { 5, { 0xba }, { 0xff } }, | |
1486 | ||
1487 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1488 | encoding for `mov m32, %eax'. | |
1489 | ||
85102364 | 1490 | ??? Should we handle SIB addressing here? |
37bdc87e MK |
1491 | ??? Should we handle 16-bit operand-sizes here? */ |
1492 | ||
1493 | /* `movl m32, %eax' */ | |
1494 | { 5, { 0xa1 }, { 0xff } }, | |
1495 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1496 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1497 | /* `movl m32, %edx' */ | |
1498 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1499 | ||
1500 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1501 | Because of the symmetry, there are actually two ways to encode | |
1502 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1503 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1504 | ||
1505 | /* `subl %eax, %eax' */ | |
1506 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1507 | /* `subl %ecx, %ecx' */ | |
1508 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1509 | /* `subl %edx, %edx' */ | |
1510 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1511 | /* `xorl %eax, %eax' */ | |
1512 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1513 | /* `xorl %ecx, %ecx' */ | |
1514 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1515 | /* `xorl %edx, %edx' */ | |
1516 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1517 | { 0 } | |
1518 | }; | |
1519 | ||
14f9473c VC |
1520 | /* Check whether PC points to an endbr32 instruction. */ |
1521 | static CORE_ADDR | |
1522 | i386_skip_endbr (CORE_ADDR pc) | |
1523 | { | |
1524 | static const gdb_byte endbr32[] = { 0xf3, 0x0f, 0x1e, 0xfb }; | |
1525 | ||
1526 | gdb_byte buf[sizeof (endbr32)]; | |
1527 | ||
1528 | /* Stop there if we can't read the code */ | |
1529 | if (target_read_code (pc, buf, sizeof (endbr32))) | |
1530 | return pc; | |
1531 | ||
1532 | /* If the instruction isn't an endbr32, stop */ | |
1533 | if (memcmp (buf, endbr32, sizeof (endbr32)) != 0) | |
1534 | return pc; | |
1535 | ||
1536 | return pc + sizeof (endbr32); | |
1537 | } | |
e11481da PM |
1538 | |
1539 | /* Check whether PC points to a no-op instruction. */ | |
1540 | static CORE_ADDR | |
1541 | i386_skip_noop (CORE_ADDR pc) | |
1542 | { | |
1543 | gdb_byte op; | |
1544 | int check = 1; | |
1545 | ||
0865b04a | 1546 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1547 | return pc; |
e11481da PM |
1548 | |
1549 | while (check) | |
1550 | { | |
1551 | check = 0; | |
1552 | /* Ignore `nop' instruction. */ | |
1553 | if (op == 0x90) | |
1554 | { | |
1555 | pc += 1; | |
0865b04a | 1556 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1557 | return pc; |
e11481da PM |
1558 | check = 1; |
1559 | } | |
1560 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1561 | Microsoft system dlls often start with | |
1562 | a `mov %edi,%edi' instruction. | |
1563 | The 5 bytes before the function start are | |
1564 | filled with `nop' instructions. | |
1565 | This pattern can be used for hot-patching: | |
1566 | The `mov %edi, %edi' instruction can be replaced by a | |
1567 | near jump to the location of the 5 `nop' instructions | |
1568 | which can be replaced by a 32-bit jump to anywhere | |
1569 | in the 32-bit address space. */ | |
1570 | ||
1571 | else if (op == 0x8b) | |
1572 | { | |
0865b04a | 1573 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1574 | return pc; |
1575 | ||
e11481da PM |
1576 | if (op == 0xff) |
1577 | { | |
1578 | pc += 2; | |
0865b04a | 1579 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1580 | return pc; |
1581 | ||
e11481da PM |
1582 | check = 1; |
1583 | } | |
1584 | } | |
1585 | } | |
1586 | return pc; | |
1587 | } | |
1588 | ||
acd5c798 MK |
1589 | /* Check whether PC points at a code that sets up a new stack frame. |
1590 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1591 | instruction after the sequence that sets up the frame or LIMIT, |
1592 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1593 | |
1594 | static CORE_ADDR | |
e17a4113 UW |
1595 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1596 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1597 | struct i386_frame_cache *cache) |
1598 | { | |
e17a4113 | 1599 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1600 | struct i386_insn *insn; |
63c0089f | 1601 | gdb_byte op; |
26604a34 | 1602 | int skip = 0; |
acd5c798 | 1603 | |
37bdc87e MK |
1604 | if (limit <= pc) |
1605 | return limit; | |
acd5c798 | 1606 | |
0865b04a | 1607 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1608 | return pc; |
acd5c798 | 1609 | |
c906108c | 1610 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1611 | { |
acd5c798 MK |
1612 | /* Take into account that we've executed the `pushl %ebp' that |
1613 | starts this instruction sequence. */ | |
fd13a04a | 1614 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1615 | cache->sp_offset += 4; |
37bdc87e | 1616 | pc++; |
acd5c798 MK |
1617 | |
1618 | /* If that's all, return now. */ | |
37bdc87e MK |
1619 | if (limit <= pc) |
1620 | return limit; | |
26604a34 | 1621 | |
b4632131 | 1622 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1623 | GCC into the prologue and skip them. At this point in the |
1624 | prologue, code should only touch the scratch registers %eax, | |
30baf67b | 1625 | %ecx and %edx, so while the number of possibilities is sheer, |
37bdc87e | 1626 | it is limited. |
5daa5b4e | 1627 | |
26604a34 MK |
1628 | Make sure we only skip these instructions if we later see the |
1629 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1630 | while (pc + skip < limit) |
26604a34 | 1631 | { |
37bdc87e MK |
1632 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1633 | if (insn == NULL) | |
1634 | break; | |
b4632131 | 1635 | |
37bdc87e | 1636 | skip += insn->len; |
26604a34 MK |
1637 | } |
1638 | ||
37bdc87e MK |
1639 | /* If that's all, return now. */ |
1640 | if (limit <= pc + skip) | |
1641 | return limit; | |
1642 | ||
0865b04a | 1643 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1644 | return pc + skip; |
37bdc87e | 1645 | |
30f8135b YQ |
1646 | /* The i386 prologue looks like |
1647 | ||
1648 | push %ebp | |
1649 | mov %esp,%ebp | |
1650 | sub $0x10,%esp | |
1651 | ||
1652 | and a different prologue can be generated for atom. | |
1653 | ||
1654 | push %ebp | |
1655 | lea (%esp),%ebp | |
1656 | lea -0x10(%esp),%esp | |
1657 | ||
1658 | We handle both of them here. */ | |
1659 | ||
acd5c798 | 1660 | switch (op) |
c906108c | 1661 | { |
30f8135b | 1662 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1663 | case 0x8b: |
0865b04a | 1664 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1665 | != 0xec) |
37bdc87e | 1666 | return pc; |
30f8135b | 1667 | pc += (skip + 2); |
c906108c SS |
1668 | break; |
1669 | case 0x89: | |
0865b04a | 1670 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1671 | != 0xe5) |
37bdc87e | 1672 | return pc; |
30f8135b YQ |
1673 | pc += (skip + 2); |
1674 | break; | |
1675 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1676 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1677 | != 0x242c) |
1678 | return pc; | |
1679 | pc += (skip + 3); | |
c906108c SS |
1680 | break; |
1681 | default: | |
37bdc87e | 1682 | return pc; |
c906108c | 1683 | } |
acd5c798 | 1684 | |
26604a34 MK |
1685 | /* OK, we actually have a frame. We just don't know how large |
1686 | it is yet. Set its size to zero. We'll adjust it if | |
1687 | necessary. We also now commit to skipping the special | |
1688 | instructions mentioned before. */ | |
acd5c798 MK |
1689 | cache->locals = 0; |
1690 | ||
1691 | /* If that's all, return now. */ | |
37bdc87e MK |
1692 | if (limit <= pc) |
1693 | return limit; | |
acd5c798 | 1694 | |
fc338970 MK |
1695 | /* Check for stack adjustment |
1696 | ||
acd5c798 | 1697 | subl $XXX, %esp |
30f8135b YQ |
1698 | or |
1699 | lea -XXX(%esp),%esp | |
fc338970 | 1700 | |
fd35795f | 1701 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1702 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1703 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1704 | return pc; |
c906108c SS |
1705 | if (op == 0x83) |
1706 | { | |
fd35795f | 1707 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1708 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1709 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1710 | return pc; |
acd5c798 | 1711 | |
37bdc87e MK |
1712 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1713 | make sense to be negative). */ | |
0865b04a | 1714 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1715 | return pc + 3; |
c906108c SS |
1716 | } |
1717 | else if (op == 0x81) | |
1718 | { | |
fd35795f | 1719 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1720 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1721 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1722 | return pc; |
acd5c798 | 1723 | |
fd35795f | 1724 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1725 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1726 | return pc + 6; |
c906108c | 1727 | } |
30f8135b YQ |
1728 | else if (op == 0x8d) |
1729 | { | |
1730 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1731 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1732 | return pc; |
1733 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1734 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1735 | return pc + 4; |
1736 | } | |
c906108c SS |
1737 | else |
1738 | { | |
30f8135b | 1739 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1740 | return pc; |
c906108c SS |
1741 | } |
1742 | } | |
37bdc87e | 1743 | else if (op == 0xc8) /* enter */ |
c906108c | 1744 | { |
0865b04a | 1745 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1746 | return pc + 4; |
c906108c | 1747 | } |
21d0e8a4 | 1748 | |
acd5c798 | 1749 | return pc; |
21d0e8a4 MK |
1750 | } |
1751 | ||
acd5c798 MK |
1752 | /* Check whether PC points at code that saves registers on the stack. |
1753 | If so, it updates CACHE and returns the address of the first | |
1754 | instruction after the register saves or CURRENT_PC, whichever is | |
1755 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1756 | |
1757 | static CORE_ADDR | |
acd5c798 MK |
1758 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1759 | struct i386_frame_cache *cache) | |
6bff26de | 1760 | { |
99ab4326 | 1761 | CORE_ADDR offset = 0; |
63c0089f | 1762 | gdb_byte op; |
99ab4326 | 1763 | int i; |
c0d1d883 | 1764 | |
99ab4326 MK |
1765 | if (cache->locals > 0) |
1766 | offset -= cache->locals; | |
1767 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1768 | { | |
0865b04a | 1769 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1770 | return pc; |
99ab4326 MK |
1771 | if (op < 0x50 || op > 0x57) |
1772 | break; | |
0d17c81d | 1773 | |
99ab4326 MK |
1774 | offset -= 4; |
1775 | cache->saved_regs[op - 0x50] = offset; | |
1776 | cache->sp_offset += 4; | |
1777 | pc++; | |
6bff26de MK |
1778 | } |
1779 | ||
acd5c798 | 1780 | return pc; |
22797942 AC |
1781 | } |
1782 | ||
acd5c798 MK |
1783 | /* Do a full analysis of the prologue at PC and update CACHE |
1784 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1785 | address where the analysis stopped. | |
ed84f6c1 | 1786 | |
fc338970 MK |
1787 | We handle these cases: |
1788 | ||
1789 | The startup sequence can be at the start of the function, or the | |
1790 | function can start with a branch to startup code at the end. | |
1791 | ||
1792 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1793 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1794 | once used in the System V compiler). | |
1795 | ||
1796 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1797 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1798 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1799 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1800 | |
1801 | Next, the registers used by this function are pushed. With the | |
1802 | System V compiler they will always be in the order: %edi, %esi, | |
1803 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1804 | restore %eax); however, the code below is willing to see the pushes | |
1805 | in any order, and will handle up to 8 of them. | |
1806 | ||
1807 | If the setup sequence is at the end of the function, then the next | |
1808 | instruction will be a branch back to the start. */ | |
c906108c | 1809 | |
acd5c798 | 1810 | static CORE_ADDR |
e17a4113 UW |
1811 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1812 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1813 | struct i386_frame_cache *cache) |
c906108c | 1814 | { |
14f9473c | 1815 | pc = i386_skip_endbr (pc); |
e11481da | 1816 | pc = i386_skip_noop (pc); |
e17a4113 | 1817 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1818 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1819 | pc = i386_skip_probe (pc); | |
92dd43fa | 1820 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1821 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1822 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1823 | } |
1824 | ||
fc338970 | 1825 | /* Return PC of first real instruction. */ |
c906108c | 1826 | |
3a1e71e3 | 1827 | static CORE_ADDR |
6093d2eb | 1828 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1829 | { |
e17a4113 UW |
1830 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1831 | ||
63c0089f | 1832 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1833 | { |
1834 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1835 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1836 | }; |
acd5c798 MK |
1837 | struct i386_frame_cache cache; |
1838 | CORE_ADDR pc; | |
63c0089f | 1839 | gdb_byte op; |
acd5c798 | 1840 | int i; |
56bf0743 | 1841 | CORE_ADDR func_addr; |
4e879fc2 | 1842 | |
56bf0743 KB |
1843 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1844 | { | |
1845 | CORE_ADDR post_prologue_pc | |
1846 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1847 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
56bf0743 | 1848 | |
c2fd7fae | 1849 | /* LLVM backend (Clang/Flang) always emits a line note before the |
16e311ab FW |
1850 | prologue and another one after. We trust clang and newer Intel |
1851 | compilers to emit usable line notes. */ | |
56bf0743 | 1852 | if (post_prologue_pc |
43f3e411 DE |
1853 | && (cust != NULL |
1854 | && COMPUNIT_PRODUCER (cust) != NULL | |
16e311ab FW |
1855 | && (producer_is_llvm (COMPUNIT_PRODUCER (cust)) |
1856 | || producer_is_icc_ge_19 (COMPUNIT_PRODUCER (cust))))) | |
1857 | return std::max (start_pc, post_prologue_pc); | |
56bf0743 KB |
1858 | } |
1859 | ||
e0f33b1f | 1860 | cache.locals = -1; |
e17a4113 | 1861 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1862 | if (cache.locals < 0) |
1863 | return start_pc; | |
c5aa993b | 1864 | |
acd5c798 | 1865 | /* Found valid frame setup. */ |
c906108c | 1866 | |
fc338970 MK |
1867 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1868 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1869 | %ebx: |
1870 | ||
dda83cd7 | 1871 | call 0x0 |
fc338970 | 1872 | popl %ebx |
dda83cd7 SM |
1873 | movl %ebx,x(%ebp) (optional) |
1874 | addl y,%ebx | |
fc338970 | 1875 | |
c906108c SS |
1876 | This code is with the rest of the prologue (at the end of the |
1877 | function), so we have to skip it to get to the first real | |
1878 | instruction at the start of the function. */ | |
c5aa993b | 1879 | |
c906108c SS |
1880 | for (i = 0; i < 6; i++) |
1881 | { | |
0865b04a | 1882 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1883 | return pc; |
1884 | ||
c5aa993b | 1885 | if (pic_pat[i] != op) |
c906108c SS |
1886 | break; |
1887 | } | |
1888 | if (i == 6) | |
1889 | { | |
acd5c798 MK |
1890 | int delta = 6; |
1891 | ||
0865b04a | 1892 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1893 | return pc; |
c906108c | 1894 | |
c5aa993b | 1895 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1896 | { |
0865b04a | 1897 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1898 | |
fc338970 | 1899 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1900 | delta += 3; |
fc338970 | 1901 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1902 | delta += 6; |
fc338970 | 1903 | else /* Unexpected instruction. */ |
acd5c798 MK |
1904 | delta = 0; |
1905 | ||
dda83cd7 | 1906 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1907 | return pc; |
c906108c | 1908 | } |
acd5c798 | 1909 | |
c5aa993b | 1910 | /* addl y,%ebx */ |
acd5c798 | 1911 | if (delta > 0 && op == 0x81 |
0865b04a | 1912 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1913 | == 0xc3) |
c906108c | 1914 | { |
acd5c798 | 1915 | pc += delta + 6; |
c906108c SS |
1916 | } |
1917 | } | |
c5aa993b | 1918 | |
e63bbc88 MK |
1919 | /* If the function starts with a branch (to startup code at the end) |
1920 | the last instruction should bring us back to the first | |
1921 | instruction of the real code. */ | |
e17a4113 UW |
1922 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1923 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1924 | |
1925 | return pc; | |
c906108c SS |
1926 | } |
1927 | ||
4309257c PM |
1928 | /* Check that the code pointed to by PC corresponds to a call to |
1929 | __main, skip it if so. Return PC otherwise. */ | |
1930 | ||
1931 | CORE_ADDR | |
1932 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1933 | { | |
e17a4113 | 1934 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1935 | gdb_byte op; |
1936 | ||
0865b04a | 1937 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1938 | return pc; |
4309257c PM |
1939 | if (op == 0xe8) |
1940 | { | |
1941 | gdb_byte buf[4]; | |
1942 | ||
0865b04a | 1943 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
24b21115 | 1944 | { |
4309257c PM |
1945 | /* Make sure address is computed correctly as a 32bit |
1946 | integer even if CORE_ADDR is 64 bit wide. */ | |
24b21115 SM |
1947 | struct bound_minimal_symbol s; |
1948 | CORE_ADDR call_dest; | |
4309257c | 1949 | |
e17a4113 | 1950 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c | 1951 | call_dest = call_dest & 0xffffffffU; |
24b21115 SM |
1952 | s = lookup_minimal_symbol_by_pc (call_dest); |
1953 | if (s.minsym != NULL | |
1954 | && s.minsym->linkage_name () != NULL | |
1955 | && strcmp (s.minsym->linkage_name (), "__main") == 0) | |
1956 | pc += 5; | |
1957 | } | |
4309257c PM |
1958 | } |
1959 | ||
1960 | return pc; | |
1961 | } | |
1962 | ||
acd5c798 | 1963 | /* This function is 64-bit safe. */ |
93924b6b | 1964 | |
acd5c798 MK |
1965 | static CORE_ADDR |
1966 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1967 | { |
63c0089f | 1968 | gdb_byte buf[8]; |
acd5c798 | 1969 | |
875f8d0e | 1970 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1971 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1972 | } |
acd5c798 | 1973 | \f |
93924b6b | 1974 | |
acd5c798 | 1975 | /* Normal frames. */ |
c5aa993b | 1976 | |
8fbca658 PA |
1977 | static void |
1978 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1979 | struct i386_frame_cache *cache) | |
a7769679 | 1980 | { |
e17a4113 UW |
1981 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1982 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1983 | gdb_byte buf[4]; |
acd5c798 MK |
1984 | int i; |
1985 | ||
8fbca658 | 1986 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1987 | |
1988 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1989 | which holds the base address for the current stack frame. | |
1990 | However, for functions that don't need it, the frame pointer is | |
1991 | optional. For these "frameless" functions the frame pointer is | |
1992 | actually the frame pointer of the calling frame. Signal | |
1993 | trampolines are just a special case of a "frameless" function. | |
1994 | They (usually) share their frame pointer with the frame that was | |
1995 | in progress when the signal occurred. */ | |
1996 | ||
10458914 | 1997 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1998 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1999 | if (cache->base == 0) |
620fa63a PA |
2000 | { |
2001 | cache->base_p = 1; | |
2002 | return; | |
2003 | } | |
acd5c798 MK |
2004 | |
2005 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 2006 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 2007 | |
acd5c798 | 2008 | if (cache->pc != 0) |
e17a4113 UW |
2009 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
2010 | cache); | |
acd5c798 MK |
2011 | |
2012 | if (cache->locals < 0) | |
2013 | { | |
2014 | /* We didn't find a valid frame, which means that CACHE->base | |
2015 | currently holds the frame pointer for our calling frame. If | |
2016 | we're at the start of a function, or somewhere half-way its | |
2017 | prologue, the function's frame probably hasn't been fully | |
2018 | setup yet. Try to reconstruct the base address for the stack | |
2019 | frame by looking at the stack pointer. For truly "frameless" | |
2020 | functions this might work too. */ | |
2021 | ||
e0c62198 | 2022 | if (cache->saved_sp_reg != -1) |
92dd43fa | 2023 | { |
8fbca658 PA |
2024 | /* Saved stack pointer has been saved. */ |
2025 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2026 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
2027 | ||
92dd43fa MK |
2028 | /* We're halfway aligning the stack. */ |
2029 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
2030 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
2031 | ||
2032 | /* This will be added back below. */ | |
2033 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
2034 | } | |
7618e12b | 2035 | else if (cache->pc != 0 |
0865b04a | 2036 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 2037 | { |
7618e12b DJ |
2038 | /* We're in a known function, but did not find a frame |
2039 | setup. Assume that the function does not use %ebp. | |
2040 | Alternatively, we may have jumped to an invalid | |
2041 | address; in that case there is definitely no new | |
2042 | frame in %ebp. */ | |
10458914 | 2043 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
2044 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
2045 | + cache->sp_offset; | |
92dd43fa | 2046 | } |
7618e12b DJ |
2047 | else |
2048 | /* We're in an unknown function. We could not find the start | |
2049 | of the function to analyze the prologue; our best option is | |
2050 | to assume a typical frame layout with the caller's %ebp | |
2051 | saved. */ | |
2052 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
2053 | } |
2054 | ||
8fbca658 PA |
2055 | if (cache->saved_sp_reg != -1) |
2056 | { | |
2057 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
2058 | register may be unavailable). */ | |
2059 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
2060 | && deprecated_frame_register_read (this_frame, |
2061 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
2062 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
2063 | } | |
acd5c798 MK |
2064 | /* Now that we have the base address for the stack frame we can |
2065 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 2066 | else if (cache->saved_sp == 0) |
92dd43fa | 2067 | cache->saved_sp = cache->base + 8; |
a7769679 | 2068 | |
acd5c798 MK |
2069 | /* Adjust all the saved registers such that they contain addresses |
2070 | instead of offsets. */ | |
2071 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
2072 | if (cache->saved_regs[i] != -1) |
2073 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 2074 | |
8fbca658 PA |
2075 | cache->base_p = 1; |
2076 | } | |
2077 | ||
2078 | static struct i386_frame_cache * | |
2079 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2080 | { | |
8fbca658 PA |
2081 | struct i386_frame_cache *cache; |
2082 | ||
2083 | if (*this_cache) | |
9a3c8263 | 2084 | return (struct i386_frame_cache *) *this_cache; |
8fbca658 PA |
2085 | |
2086 | cache = i386_alloc_frame_cache (); | |
2087 | *this_cache = cache; | |
2088 | ||
a70b8144 | 2089 | try |
8fbca658 PA |
2090 | { |
2091 | i386_frame_cache_1 (this_frame, cache); | |
2092 | } | |
230d2906 | 2093 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2094 | { |
2095 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2096 | throw; |
7556d4a4 | 2097 | } |
8fbca658 | 2098 | |
acd5c798 | 2099 | return cache; |
a7769679 MK |
2100 | } |
2101 | ||
3a1e71e3 | 2102 | static void |
10458914 | 2103 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 2104 | struct frame_id *this_id) |
c906108c | 2105 | { |
10458914 | 2106 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 2107 | |
5ce0145d PA |
2108 | if (!cache->base_p) |
2109 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
2110 | else if (cache->base == 0) | |
2111 | { | |
2112 | /* This marks the outermost frame. */ | |
2113 | } | |
2114 | else | |
2115 | { | |
2116 | /* See the end of i386_push_dummy_call. */ | |
2117 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
2118 | } | |
acd5c798 MK |
2119 | } |
2120 | ||
8fbca658 PA |
2121 | static enum unwind_stop_reason |
2122 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2123 | void **this_cache) | |
2124 | { | |
2125 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
2126 | ||
2127 | if (!cache->base_p) | |
2128 | return UNWIND_UNAVAILABLE; | |
2129 | ||
2130 | /* This marks the outermost frame. */ | |
2131 | if (cache->base == 0) | |
2132 | return UNWIND_OUTERMOST; | |
2133 | ||
2134 | return UNWIND_NO_REASON; | |
2135 | } | |
2136 | ||
10458914 DJ |
2137 | static struct value * |
2138 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2139 | int regnum) | |
acd5c798 | 2140 | { |
10458914 | 2141 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2142 | |
2143 | gdb_assert (regnum >= 0); | |
2144 | ||
2145 | /* The System V ABI says that: | |
2146 | ||
2147 | "The flags register contains the system flags, such as the | |
2148 | direction flag and the carry flag. The direction flag must be | |
2149 | set to the forward (that is, zero) direction before entry and | |
2150 | upon exit from a function. Other user flags have no specified | |
2151 | role in the standard calling sequence and are not preserved." | |
2152 | ||
2153 | To guarantee the "upon exit" part of that statement we fake a | |
2154 | saved flags register that has its direction flag cleared. | |
2155 | ||
2156 | Note that GCC doesn't seem to rely on the fact that the direction | |
2157 | flag is cleared after a function return; it always explicitly | |
2158 | clears the flag before operations where it matters. | |
2159 | ||
2160 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
2161 | right thing to do. The way we fake the flags register here makes | |
2162 | it impossible to change it. */ | |
2163 | ||
2164 | if (regnum == I386_EFLAGS_REGNUM) | |
2165 | { | |
10458914 | 2166 | ULONGEST val; |
c5aa993b | 2167 | |
10458914 DJ |
2168 | val = get_frame_register_unsigned (this_frame, regnum); |
2169 | val &= ~(1 << 10); | |
2170 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 2171 | } |
1211c4e4 | 2172 | |
acd5c798 | 2173 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 2174 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 2175 | |
fcf250e2 UW |
2176 | if (regnum == I386_ESP_REGNUM |
2177 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
2178 | { |
2179 | /* If the SP has been saved, but we don't know where, then this | |
2180 | means that SAVED_SP_REG register was found unavailable back | |
2181 | when we built the cache. */ | |
fcf250e2 | 2182 | if (cache->saved_sp == 0) |
8fbca658 PA |
2183 | return frame_unwind_got_register (this_frame, regnum, |
2184 | cache->saved_sp_reg); | |
2185 | else | |
2186 | return frame_unwind_got_constant (this_frame, regnum, | |
2187 | cache->saved_sp); | |
2188 | } | |
acd5c798 | 2189 | |
fd13a04a | 2190 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2191 | return frame_unwind_got_memory (this_frame, regnum, |
2192 | cache->saved_regs[regnum]); | |
fd13a04a | 2193 | |
10458914 | 2194 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
2195 | } |
2196 | ||
2197 | static const struct frame_unwind i386_frame_unwind = | |
2198 | { | |
a154d838 | 2199 | "i386 prologue", |
acd5c798 | 2200 | NORMAL_FRAME, |
8fbca658 | 2201 | i386_frame_unwind_stop_reason, |
acd5c798 | 2202 | i386_frame_this_id, |
10458914 DJ |
2203 | i386_frame_prev_register, |
2204 | NULL, | |
2205 | default_frame_sniffer | |
acd5c798 | 2206 | }; |
06da04c6 MS |
2207 | |
2208 | /* Normal frames, but in a function epilogue. */ | |
2209 | ||
c9cf6e20 MG |
2210 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2211 | ||
2212 | The epilogue is defined here as the 'ret' instruction, which will | |
06da04c6 MS |
2213 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
2214 | the function's stack frame. */ | |
2215 | ||
2216 | static int | |
c9cf6e20 | 2217 | i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
06da04c6 MS |
2218 | { |
2219 | gdb_byte insn; | |
43f3e411 | 2220 | struct compunit_symtab *cust; |
e0d00bc7 | 2221 | |
43f3e411 DE |
2222 | cust = find_pc_compunit_symtab (pc); |
2223 | if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) | |
e0d00bc7 | 2224 | return 0; |
06da04c6 MS |
2225 | |
2226 | if (target_read_memory (pc, &insn, 1)) | |
2227 | return 0; /* Can't read memory at pc. */ | |
2228 | ||
2229 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2230 | return 0; | |
2231 | ||
2232 | return 1; | |
2233 | } | |
2234 | ||
2235 | static int | |
2236 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2237 | struct frame_info *this_frame, | |
2238 | void **this_prologue_cache) | |
2239 | { | |
2240 | if (frame_relative_level (this_frame) == 0) | |
c9cf6e20 MG |
2241 | return i386_stack_frame_destroyed_p (get_frame_arch (this_frame), |
2242 | get_frame_pc (this_frame)); | |
06da04c6 MS |
2243 | else |
2244 | return 0; | |
2245 | } | |
2246 | ||
2247 | static struct i386_frame_cache * | |
2248 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2249 | { | |
06da04c6 | 2250 | struct i386_frame_cache *cache; |
0d6c2135 | 2251 | CORE_ADDR sp; |
06da04c6 MS |
2252 | |
2253 | if (*this_cache) | |
9a3c8263 | 2254 | return (struct i386_frame_cache *) *this_cache; |
06da04c6 MS |
2255 | |
2256 | cache = i386_alloc_frame_cache (); | |
2257 | *this_cache = cache; | |
2258 | ||
a70b8144 | 2259 | try |
8fbca658 | 2260 | { |
0d6c2135 | 2261 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2262 | |
0d6c2135 MK |
2263 | /* At this point the stack looks as if we just entered the |
2264 | function, with the return address at the top of the | |
2265 | stack. */ | |
2266 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2267 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2268 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2269 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2270 | |
8fbca658 PA |
2271 | cache->base_p = 1; |
2272 | } | |
230d2906 | 2273 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2274 | { |
2275 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2276 | throw; |
7556d4a4 | 2277 | } |
06da04c6 MS |
2278 | |
2279 | return cache; | |
2280 | } | |
2281 | ||
8fbca658 PA |
2282 | static enum unwind_stop_reason |
2283 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2284 | void **this_cache) | |
2285 | { | |
0d6c2135 MK |
2286 | struct i386_frame_cache *cache = |
2287 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2288 | |
2289 | if (!cache->base_p) | |
2290 | return UNWIND_UNAVAILABLE; | |
2291 | ||
2292 | return UNWIND_NO_REASON; | |
2293 | } | |
2294 | ||
06da04c6 MS |
2295 | static void |
2296 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2297 | void **this_cache, | |
2298 | struct frame_id *this_id) | |
2299 | { | |
0d6c2135 MK |
2300 | struct i386_frame_cache *cache = |
2301 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2302 | |
8fbca658 | 2303 | if (!cache->base_p) |
5ce0145d PA |
2304 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2305 | else | |
2306 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2307 | } |
2308 | ||
0d6c2135 MK |
2309 | static struct value * |
2310 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2311 | void **this_cache, int regnum) | |
2312 | { | |
2313 | /* Make sure we've initialized the cache. */ | |
2314 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2315 | ||
2316 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2317 | } | |
2318 | ||
06da04c6 MS |
2319 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2320 | { | |
a154d838 | 2321 | "i386 epilogue", |
06da04c6 | 2322 | NORMAL_FRAME, |
8fbca658 | 2323 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2324 | i386_epilogue_frame_this_id, |
0d6c2135 | 2325 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2326 | NULL, |
2327 | i386_epilogue_frame_sniffer | |
2328 | }; | |
acd5c798 MK |
2329 | \f |
2330 | ||
a3fcb948 JG |
2331 | /* Stack-based trampolines. */ |
2332 | ||
2333 | /* These trampolines are used on cross x86 targets, when taking the | |
2334 | address of a nested function. When executing these trampolines, | |
2335 | no stack frame is set up, so we are in a similar situation as in | |
2336 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2337 | ||
2338 | /* Static chain passed in register. */ | |
2339 | ||
6bd434d6 | 2340 | static i386_insn i386_tramp_chain_in_reg_insns[] = |
a3fcb948 JG |
2341 | { |
2342 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2343 | { 5, { 0xb8 }, { 0xfe } }, | |
2344 | ||
2345 | /* `jmp imm32' */ | |
2346 | { 5, { 0xe9 }, { 0xff } }, | |
2347 | ||
2348 | {0} | |
2349 | }; | |
2350 | ||
2351 | /* Static chain passed on stack (when regparm=3). */ | |
2352 | ||
6bd434d6 | 2353 | static i386_insn i386_tramp_chain_on_stack_insns[] = |
a3fcb948 JG |
2354 | { |
2355 | /* `push imm32' */ | |
2356 | { 5, { 0x68 }, { 0xff } }, | |
2357 | ||
2358 | /* `jmp imm32' */ | |
2359 | { 5, { 0xe9 }, { 0xff } }, | |
2360 | ||
2361 | {0} | |
2362 | }; | |
2363 | ||
2364 | /* Return whether PC points inside a stack trampoline. */ | |
2365 | ||
2366 | static int | |
6df81a63 | 2367 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2368 | { |
2369 | gdb_byte insn; | |
2c02bd72 | 2370 | const char *name; |
a3fcb948 JG |
2371 | |
2372 | /* A stack trampoline is detected if no name is associated | |
2373 | to the current pc and if it points inside a trampoline | |
2374 | sequence. */ | |
2375 | ||
2376 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2377 | if (name) | |
2378 | return 0; | |
2379 | ||
2380 | if (target_read_memory (pc, &insn, 1)) | |
2381 | return 0; | |
2382 | ||
2383 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2384 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2385 | return 0; | |
2386 | ||
2387 | return 1; | |
2388 | } | |
2389 | ||
2390 | static int | |
2391 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2392 | struct frame_info *this_frame, |
2393 | void **this_cache) | |
a3fcb948 JG |
2394 | { |
2395 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2396 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2397 | else |
2398 | return 0; | |
2399 | } | |
2400 | ||
2401 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2402 | { | |
a154d838 | 2403 | "i386 stack tramp", |
a3fcb948 JG |
2404 | NORMAL_FRAME, |
2405 | i386_epilogue_frame_unwind_stop_reason, | |
2406 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2407 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2408 | NULL, |
2409 | i386_stack_tramp_frame_sniffer | |
2410 | }; | |
2411 | \f | |
6710bf39 SS |
2412 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2413 | ||
2414 | static void | |
2415 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2416 | struct agent_expr *ax, struct axs_value *value, | |
2417 | CORE_ADDR scope) | |
2418 | { | |
2419 | /* The following sequence assumes the traditional use of the base | |
2420 | register. */ | |
2421 | ax_reg (ax, I386_EBP_REGNUM); | |
2422 | ax_const_l (ax, 4); | |
2423 | ax_simple (ax, aop_add); | |
2424 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2425 | value->kind = axs_lvalue_memory; | |
2426 | } | |
2427 | \f | |
a3fcb948 | 2428 | |
acd5c798 MK |
2429 | /* Signal trampolines. */ |
2430 | ||
2431 | static struct i386_frame_cache * | |
10458914 | 2432 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2433 | { |
e17a4113 UW |
2434 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2435 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2436 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 2437 | struct i386_frame_cache *cache; |
acd5c798 | 2438 | CORE_ADDR addr; |
63c0089f | 2439 | gdb_byte buf[4]; |
acd5c798 MK |
2440 | |
2441 | if (*this_cache) | |
9a3c8263 | 2442 | return (struct i386_frame_cache *) *this_cache; |
acd5c798 | 2443 | |
fd13a04a | 2444 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2445 | |
a70b8144 | 2446 | try |
a3386186 | 2447 | { |
8fbca658 PA |
2448 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2449 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2450 | |
8fbca658 PA |
2451 | addr = tdep->sigcontext_addr (this_frame); |
2452 | if (tdep->sc_reg_offset) | |
2453 | { | |
2454 | int i; | |
a3386186 | 2455 | |
8fbca658 PA |
2456 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2457 | ||
2458 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2459 | if (tdep->sc_reg_offset[i] != -1) | |
2460 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2461 | } | |
2462 | else | |
2463 | { | |
2464 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2465 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2466 | } | |
2467 | ||
2468 | cache->base_p = 1; | |
a3386186 | 2469 | } |
230d2906 | 2470 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2471 | { |
2472 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2473 | throw; |
7556d4a4 | 2474 | } |
acd5c798 MK |
2475 | |
2476 | *this_cache = cache; | |
2477 | return cache; | |
2478 | } | |
2479 | ||
8fbca658 PA |
2480 | static enum unwind_stop_reason |
2481 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2482 | void **this_cache) | |
2483 | { | |
2484 | struct i386_frame_cache *cache = | |
2485 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2486 | ||
2487 | if (!cache->base_p) | |
2488 | return UNWIND_UNAVAILABLE; | |
2489 | ||
2490 | return UNWIND_NO_REASON; | |
2491 | } | |
2492 | ||
acd5c798 | 2493 | static void |
10458914 | 2494 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2495 | struct frame_id *this_id) |
2496 | { | |
2497 | struct i386_frame_cache *cache = | |
10458914 | 2498 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2499 | |
8fbca658 | 2500 | if (!cache->base_p) |
5ce0145d PA |
2501 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2502 | else | |
2503 | { | |
2504 | /* See the end of i386_push_dummy_call. */ | |
2505 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2506 | } | |
acd5c798 MK |
2507 | } |
2508 | ||
10458914 DJ |
2509 | static struct value * |
2510 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2511 | void **this_cache, int regnum) | |
acd5c798 MK |
2512 | { |
2513 | /* Make sure we've initialized the cache. */ | |
10458914 | 2514 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2515 | |
10458914 | 2516 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2517 | } |
c0d1d883 | 2518 | |
10458914 DJ |
2519 | static int |
2520 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2521 | struct frame_info *this_frame, | |
2522 | void **this_prologue_cache) | |
acd5c798 | 2523 | { |
10458914 | 2524 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2525 | |
911bc6ee MK |
2526 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2527 | handler. */ | |
2528 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2529 | return 0; |
1c3545ae | 2530 | |
911bc6ee MK |
2531 | if (tdep->sigtramp_p != NULL) |
2532 | { | |
10458914 DJ |
2533 | if (tdep->sigtramp_p (this_frame)) |
2534 | return 1; | |
911bc6ee MK |
2535 | } |
2536 | ||
2537 | if (tdep->sigtramp_start != 0) | |
2538 | { | |
10458914 | 2539 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2540 | |
2541 | gdb_assert (tdep->sigtramp_end != 0); | |
2542 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2543 | return 1; |
911bc6ee | 2544 | } |
acd5c798 | 2545 | |
10458914 | 2546 | return 0; |
acd5c798 | 2547 | } |
10458914 DJ |
2548 | |
2549 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2550 | { | |
a154d838 | 2551 | "i386 sigtramp", |
10458914 | 2552 | SIGTRAMP_FRAME, |
8fbca658 | 2553 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2554 | i386_sigtramp_frame_this_id, |
2555 | i386_sigtramp_frame_prev_register, | |
2556 | NULL, | |
2557 | i386_sigtramp_frame_sniffer | |
2558 | }; | |
acd5c798 MK |
2559 | \f |
2560 | ||
2561 | static CORE_ADDR | |
10458914 | 2562 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2563 | { |
10458914 | 2564 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2565 | |
2566 | return cache->base; | |
2567 | } | |
2568 | ||
2569 | static const struct frame_base i386_frame_base = | |
2570 | { | |
2571 | &i386_frame_unwind, | |
2572 | i386_frame_base_address, | |
2573 | i386_frame_base_address, | |
2574 | i386_frame_base_address | |
2575 | }; | |
2576 | ||
acd5c798 | 2577 | static struct frame_id |
10458914 | 2578 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2579 | { |
acd5c798 MK |
2580 | CORE_ADDR fp; |
2581 | ||
10458914 | 2582 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2583 | |
3e210248 | 2584 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2585 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2586 | } |
e04e5beb JM |
2587 | |
2588 | /* _Decimal128 function return values need 16-byte alignment on the | |
2589 | stack. */ | |
2590 | ||
2591 | static CORE_ADDR | |
2592 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2593 | { | |
2594 | return sp & -(CORE_ADDR)16; | |
2595 | } | |
fc338970 | 2596 | \f |
c906108c | 2597 | |
fc338970 MK |
2598 | /* Figure out where the longjmp will land. Slurp the args out of the |
2599 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2600 | structure from which we extract the address that we will land at. |
28bcfd30 | 2601 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2602 | success. */ |
c906108c | 2603 | |
8201327c | 2604 | static int |
60ade65d | 2605 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2606 | { |
436675d3 | 2607 | gdb_byte buf[4]; |
c906108c | 2608 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2609 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2610 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2611 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2612 | |
8201327c MK |
2613 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2614 | longjmp will land. */ | |
2615 | if (jb_pc_offset == -1) | |
c906108c SS |
2616 | return 0; |
2617 | ||
436675d3 | 2618 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2619 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2620 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2621 | return 0; |
2622 | ||
e17a4113 | 2623 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2624 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2625 | return 0; |
c906108c | 2626 | |
e17a4113 | 2627 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2628 | return 1; |
2629 | } | |
fc338970 | 2630 | \f |
c906108c | 2631 | |
7ccc1c74 JM |
2632 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2633 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2634 | unions containing such types must be 16-byte-aligned; other | |
2635 | arguments are 4-byte-aligned. */ | |
2636 | ||
2637 | static int | |
2638 | i386_16_byte_align_p (struct type *type) | |
2639 | { | |
2640 | type = check_typedef (type); | |
78134374 | 2641 | if ((type->code () == TYPE_CODE_DECFLOAT |
bd63c870 | 2642 | || (type->code () == TYPE_CODE_ARRAY && type->is_vector ())) |
7ccc1c74 JM |
2643 | && TYPE_LENGTH (type) == 16) |
2644 | return 1; | |
78134374 | 2645 | if (type->code () == TYPE_CODE_ARRAY) |
7ccc1c74 | 2646 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); |
78134374 SM |
2647 | if (type->code () == TYPE_CODE_STRUCT |
2648 | || type->code () == TYPE_CODE_UNION) | |
7ccc1c74 JM |
2649 | { |
2650 | int i; | |
1f704f76 | 2651 | for (i = 0; i < type->num_fields (); i++) |
7ccc1c74 | 2652 | { |
b6a6aa07 TV |
2653 | if (field_is_static (&type->field (i))) |
2654 | continue; | |
940da03e | 2655 | if (i386_16_byte_align_p (type->field (i).type ())) |
7ccc1c74 JM |
2656 | return 1; |
2657 | } | |
2658 | } | |
2659 | return 0; | |
2660 | } | |
2661 | ||
a9b8d892 JK |
2662 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2663 | ||
2664 | static CORE_ADDR | |
2665 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2666 | struct value **args, int nargs, struct type *value_type, | |
2667 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2668 | struct regcache *regcache) | |
2669 | { | |
2670 | /* Use 0xcc breakpoint - 1 byte. */ | |
2671 | *bp_addr = sp - 1; | |
2672 | *real_pc = funaddr; | |
2673 | ||
2674 | /* Keep the stack aligned. */ | |
2675 | return sp - 16; | |
2676 | } | |
2677 | ||
627c7fb8 HD |
2678 | /* The "push_dummy_call" gdbarch method, optionally with the thiscall |
2679 | calling convention. */ | |
2680 | ||
2681 | CORE_ADDR | |
2682 | i386_thiscall_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
2683 | struct regcache *regcache, CORE_ADDR bp_addr, | |
2684 | int nargs, struct value **args, CORE_ADDR sp, | |
2685 | function_call_return_method return_method, | |
2686 | CORE_ADDR struct_addr, bool thiscall) | |
22f8ba57 | 2687 | { |
e17a4113 | 2688 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2689 | gdb_byte buf[4]; |
acd5c798 | 2690 | int i; |
7ccc1c74 JM |
2691 | int write_pass; |
2692 | int args_space = 0; | |
acd5c798 | 2693 | |
4a612d6f WT |
2694 | /* BND registers can be in arbitrary values at the moment of the |
2695 | inferior call. This can cause boundary violations that are not | |
2696 | due to a real bug or even desired by the user. The best to be done | |
2697 | is set the BND registers to allow access to the whole memory, INIT | |
2698 | state, before pushing the inferior call. */ | |
2699 | i387_reset_bnd_regs (gdbarch, regcache); | |
2700 | ||
7ccc1c74 JM |
2701 | /* Determine the total space required for arguments and struct |
2702 | return address in a first pass (allowing for 16-byte-aligned | |
2703 | arguments), then push arguments in a second pass. */ | |
2704 | ||
2705 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2706 | { |
7ccc1c74 | 2707 | int args_space_used = 0; |
7ccc1c74 | 2708 | |
cf84fa6b | 2709 | if (return_method == return_method_struct) |
7ccc1c74 JM |
2710 | { |
2711 | if (write_pass) | |
2712 | { | |
2713 | /* Push value address. */ | |
e17a4113 | 2714 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2715 | write_memory (sp, buf, 4); |
2716 | args_space_used += 4; | |
2717 | } | |
2718 | else | |
2719 | args_space += 4; | |
2720 | } | |
2721 | ||
627c7fb8 | 2722 | for (i = thiscall ? 1 : 0; i < nargs; i++) |
7ccc1c74 JM |
2723 | { |
2724 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2725 | |
7ccc1c74 JM |
2726 | if (write_pass) |
2727 | { | |
2728 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2729 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2730 | |
7ccc1c74 JM |
2731 | write_memory (sp + args_space_used, |
2732 | value_contents_all (args[i]), len); | |
2733 | /* The System V ABI says that: | |
acd5c798 | 2734 | |
7ccc1c74 JM |
2735 | "An argument's size is increased, if necessary, to make it a |
2736 | multiple of [32-bit] words. This may require tail padding, | |
2737 | depending on the size of the argument." | |
22f8ba57 | 2738 | |
7ccc1c74 JM |
2739 | This makes sure the stack stays word-aligned. */ |
2740 | args_space_used += align_up (len, 4); | |
2741 | } | |
2742 | else | |
2743 | { | |
2744 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2745 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2746 | args_space += align_up (len, 4); |
2747 | } | |
2748 | } | |
2749 | ||
2750 | if (!write_pass) | |
2751 | { | |
7ccc1c74 | 2752 | sp -= args_space; |
284c5a60 MK |
2753 | |
2754 | /* The original System V ABI only requires word alignment, | |
2755 | but modern incarnations need 16-byte alignment in order | |
2756 | to support SSE. Since wasting a few bytes here isn't | |
2757 | harmful we unconditionally enforce 16-byte alignment. */ | |
2758 | sp &= ~0xf; | |
7ccc1c74 | 2759 | } |
22f8ba57 MK |
2760 | } |
2761 | ||
acd5c798 MK |
2762 | /* Store return address. */ |
2763 | sp -= 4; | |
e17a4113 | 2764 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2765 | write_memory (sp, buf, 4); |
2766 | ||
2767 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2768 | store_unsigned_integer (buf, 4, byte_order, sp); |
b66f5587 | 2769 | regcache->cooked_write (I386_ESP_REGNUM, buf); |
acd5c798 MK |
2770 | |
2771 | /* ...and fake a frame pointer. */ | |
b66f5587 | 2772 | regcache->cooked_write (I386_EBP_REGNUM, buf); |
acd5c798 | 2773 | |
627c7fb8 HD |
2774 | /* The 'this' pointer needs to be in ECX. */ |
2775 | if (thiscall) | |
2776 | regcache->cooked_write (I386_ECX_REGNUM, value_contents_all (args[0])); | |
2777 | ||
3e210248 AC |
2778 | /* MarkK wrote: This "+ 8" is all over the place: |
2779 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2780 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2781 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2782 | definition of the stack address of a frame. Otherwise frame id |
2783 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2784 | stack address *before* the function call as a frame's CFA. On |
2785 | the i386, when %ebp is used as a frame pointer, the offset | |
2786 | between the contents %ebp and the CFA as defined by GCC. */ | |
2787 | return sp + 8; | |
22f8ba57 MK |
2788 | } |
2789 | ||
627c7fb8 HD |
2790 | /* Implement the "push_dummy_call" gdbarch method. */ |
2791 | ||
2792 | static CORE_ADDR | |
2793 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
2794 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2795 | struct value **args, CORE_ADDR sp, | |
2796 | function_call_return_method return_method, | |
2797 | CORE_ADDR struct_addr) | |
2798 | { | |
2799 | return i386_thiscall_push_dummy_call (gdbarch, function, regcache, bp_addr, | |
2800 | nargs, args, sp, return_method, | |
2801 | struct_addr, false); | |
2802 | } | |
2803 | ||
1a309862 MK |
2804 | /* These registers are used for returning integers (and on some |
2805 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2806 | size and alignment match an integer type). */ |
acd5c798 MK |
2807 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2808 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2809 | |
c5e656c1 MK |
2810 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2811 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2812 | |
3a1e71e3 | 2813 | static void |
c5e656c1 | 2814 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2815 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2816 | { |
c5e656c1 | 2817 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2818 | int len = TYPE_LENGTH (type); |
63c0089f | 2819 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2820 | |
78134374 | 2821 | if (type->code () == TYPE_CODE_FLT) |
c906108c | 2822 | { |
5716833c | 2823 | if (tdep->st0_regnum < 0) |
1a309862 | 2824 | { |
8a3fe4f8 | 2825 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2826 | memset (valbuf, 0, len); |
ef9dff19 | 2827 | return; |
1a309862 MK |
2828 | } |
2829 | ||
c6ba6f0d MK |
2830 | /* Floating-point return values can be found in %st(0). Convert |
2831 | its contents to the desired type. This is probably not | |
2832 | exactly how it would happen on the target itself, but it is | |
2833 | the best we can do. */ | |
0b883586 | 2834 | regcache->raw_read (I386_ST0_REGNUM, buf); |
3b2ca824 | 2835 | target_float_convert (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2836 | } |
2837 | else | |
c5aa993b | 2838 | { |
875f8d0e UW |
2839 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2840 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2841 | |
2842 | if (len <= low_size) | |
00f8375e | 2843 | { |
0b883586 | 2844 | regcache->raw_read (LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2845 | memcpy (valbuf, buf, len); |
2846 | } | |
d4f3574e SS |
2847 | else if (len <= (low_size + high_size)) |
2848 | { | |
0b883586 | 2849 | regcache->raw_read (LOW_RETURN_REGNUM, buf); |
00f8375e | 2850 | memcpy (valbuf, buf, low_size); |
0b883586 | 2851 | regcache->raw_read (HIGH_RETURN_REGNUM, buf); |
63c0089f | 2852 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2853 | } |
2854 | else | |
8e65ff28 | 2855 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2856 | _("Cannot extract return value of %d bytes long."), |
2857 | len); | |
c906108c SS |
2858 | } |
2859 | } | |
2860 | ||
c5e656c1 MK |
2861 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2862 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2863 | |
3a1e71e3 | 2864 | static void |
c5e656c1 | 2865 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2866 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2867 | { |
c5e656c1 | 2868 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2869 | int len = TYPE_LENGTH (type); |
2870 | ||
78134374 | 2871 | if (type->code () == TYPE_CODE_FLT) |
ef9dff19 | 2872 | { |
3d7f4f49 | 2873 | ULONGEST fstat; |
63c0089f | 2874 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2875 | |
5716833c | 2876 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2877 | { |
8a3fe4f8 | 2878 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2879 | return; |
2880 | } | |
2881 | ||
635b0cc1 | 2882 | /* Returning floating-point values is a bit tricky. Apart from |
dda83cd7 SM |
2883 | storing the return value in %st(0), we have to simulate the |
2884 | state of the FPU at function return point. */ | |
635b0cc1 | 2885 | |
c6ba6f0d MK |
2886 | /* Convert the value found in VALBUF to the extended |
2887 | floating-point format used by the FPU. This is probably | |
2888 | not exactly how it would happen on the target itself, but | |
2889 | it is the best we can do. */ | |
3b2ca824 | 2890 | target_float_convert (valbuf, type, buf, i387_ext_type (gdbarch)); |
10eaee5f | 2891 | regcache->raw_write (I386_ST0_REGNUM, buf); |
ccb945b8 | 2892 | |
635b0cc1 | 2893 | /* Set the top of the floating-point register stack to 7. The |
dda83cd7 SM |
2894 | actual value doesn't really matter, but 7 is what a normal |
2895 | function return would end up with if the program started out | |
2896 | with a freshly initialized FPU. */ | |
20a6ec49 | 2897 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2898 | fstat |= (7 << 11); |
20a6ec49 | 2899 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2900 | |
635b0cc1 | 2901 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
dda83cd7 SM |
2902 | the floating-point register stack to 7, the appropriate value |
2903 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2904 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2905 | } |
2906 | else | |
2907 | { | |
875f8d0e UW |
2908 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2909 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2910 | |
2911 | if (len <= low_size) | |
4f0420fd | 2912 | regcache->raw_write_part (LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2913 | else if (len <= (low_size + high_size)) |
2914 | { | |
10eaee5f | 2915 | regcache->raw_write (LOW_RETURN_REGNUM, valbuf); |
4f0420fd SM |
2916 | regcache->raw_write_part (HIGH_RETURN_REGNUM, 0, len - low_size, |
2917 | valbuf + low_size); | |
ef9dff19 MK |
2918 | } |
2919 | else | |
8e65ff28 | 2920 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2921 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2922 | } |
2923 | } | |
fc338970 | 2924 | \f |
ef9dff19 | 2925 | |
8201327c MK |
2926 | /* This is the variable that is set with "set struct-convention", and |
2927 | its legitimate values. */ | |
2928 | static const char default_struct_convention[] = "default"; | |
2929 | static const char pcc_struct_convention[] = "pcc"; | |
2930 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2931 | static const char *const valid_conventions[] = |
8201327c MK |
2932 | { |
2933 | default_struct_convention, | |
2934 | pcc_struct_convention, | |
2935 | reg_struct_convention, | |
2936 | NULL | |
2937 | }; | |
2938 | static const char *struct_convention = default_struct_convention; | |
2939 | ||
0e4377e1 JB |
2940 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2941 | a union type, or an array type, should be returned in registers | |
2942 | for architecture GDBARCH. */ | |
c5e656c1 | 2943 | |
8201327c | 2944 | static int |
c5e656c1 | 2945 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2946 | { |
c5e656c1 | 2947 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
78134374 | 2948 | enum type_code code = type->code (); |
c5e656c1 | 2949 | int len = TYPE_LENGTH (type); |
8201327c | 2950 | |
0e4377e1 | 2951 | gdb_assert (code == TYPE_CODE_STRUCT |
dda83cd7 SM |
2952 | || code == TYPE_CODE_UNION |
2953 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2954 | |
2955 | if (struct_convention == pcc_struct_convention | |
2956 | || (struct_convention == default_struct_convention | |
2957 | && tdep->struct_return == pcc_struct_return)) | |
2958 | return 0; | |
2959 | ||
9edde48e MK |
2960 | /* Structures consisting of a single `float', `double' or 'long |
2961 | double' member are returned in %st(0). */ | |
1f704f76 | 2962 | if (code == TYPE_CODE_STRUCT && type->num_fields () == 1) |
9edde48e | 2963 | { |
940da03e | 2964 | type = check_typedef (type->field (0).type ()); |
78134374 | 2965 | if (type->code () == TYPE_CODE_FLT) |
9edde48e MK |
2966 | return (len == 4 || len == 8 || len == 12); |
2967 | } | |
2968 | ||
c5e656c1 MK |
2969 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2970 | } | |
2971 | ||
2972 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2973 | should be returned. If it is supposed to be returned in registers, | |
2974 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2975 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2976 | from WRITEBUF into REGCACHE. */ | |
2977 | ||
2978 | static enum return_value_convention | |
6a3a010b | 2979 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2980 | struct type *type, struct regcache *regcache, |
2981 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 | 2982 | { |
78134374 | 2983 | enum type_code code = type->code (); |
c5e656c1 | 2984 | |
5daa78cc TJB |
2985 | if (((code == TYPE_CODE_STRUCT |
2986 | || code == TYPE_CODE_UNION | |
2987 | || code == TYPE_CODE_ARRAY) | |
2988 | && !i386_reg_struct_return_p (gdbarch, type)) | |
405feb71 | 2989 | /* Complex double and long double uses the struct return convention. */ |
2445fd7b MK |
2990 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) |
2991 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2992 | /* 128-bit decimal float uses the struct return convention. */ |
2993 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2994 | { |
2995 | /* The System V ABI says that: | |
2996 | ||
2997 | "A function that returns a structure or union also sets %eax | |
2998 | to the value of the original address of the caller's area | |
2999 | before it returns. Thus when the caller receives control | |
3000 | again, the address of the returned object resides in register | |
3001 | %eax and can be used to access the object." | |
3002 | ||
3003 | So the ABI guarantees that we can always find the return | |
3004 | value just after the function has returned. */ | |
3005 | ||
0e4377e1 | 3006 | /* Note that the ABI doesn't mention functions returning arrays, |
dda83cd7 SM |
3007 | which is something possible in certain languages such as Ada. |
3008 | In this case, the value is returned as if it was wrapped in | |
3009 | a record, so the convention applied to records also applies | |
3010 | to arrays. */ | |
0e4377e1 | 3011 | |
31db7b6c MK |
3012 | if (readbuf) |
3013 | { | |
3014 | ULONGEST addr; | |
3015 | ||
3016 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
3017 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
3018 | } | |
3019 | ||
3020 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
3021 | } | |
c5e656c1 MK |
3022 | |
3023 | /* This special case is for structures consisting of a single | |
9edde48e MK |
3024 | `float', `double' or 'long double' member. These structures are |
3025 | returned in %st(0). For these structures, we call ourselves | |
3026 | recursively, changing TYPE into the type of the first member of | |
3027 | the structure. Since that should work for all structures that | |
3028 | have only one member, we don't bother to check the member's type | |
3029 | here. */ | |
1f704f76 | 3030 | if (code == TYPE_CODE_STRUCT && type->num_fields () == 1) |
c5e656c1 | 3031 | { |
940da03e | 3032 | type = check_typedef (type->field (0).type ()); |
6a3a010b | 3033 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 3034 | readbuf, writebuf); |
c5e656c1 MK |
3035 | } |
3036 | ||
3037 | if (readbuf) | |
3038 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
3039 | if (writebuf) | |
3040 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 3041 | |
c5e656c1 | 3042 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
3043 | } |
3044 | \f | |
3045 | ||
27067745 UW |
3046 | struct type * |
3047 | i387_ext_type (struct gdbarch *gdbarch) | |
3048 | { | |
3049 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3050 | ||
3051 | if (!tdep->i387_ext_type) | |
90884b2b L |
3052 | { |
3053 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
3054 | gdb_assert (tdep->i387_ext_type != NULL); | |
3055 | } | |
27067745 UW |
3056 | |
3057 | return tdep->i387_ext_type; | |
3058 | } | |
3059 | ||
1dbcd68c WT |
3060 | /* Construct type for pseudo BND registers. We can't use |
3061 | tdesc_find_type since a complement of one value has to be used | |
3062 | to describe the upper bound. */ | |
3063 | ||
3064 | static struct type * | |
3065 | i386_bnd_type (struct gdbarch *gdbarch) | |
3066 | { | |
3067 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3068 | ||
3069 | ||
3070 | if (!tdep->i386_bnd_type) | |
3071 | { | |
870f88f7 | 3072 | struct type *t; |
1dbcd68c WT |
3073 | const struct builtin_type *bt = builtin_type (gdbarch); |
3074 | ||
3075 | /* The type we're building is described bellow: */ | |
3076 | #if 0 | |
3077 | struct __bound128 | |
3078 | { | |
3079 | void *lbound; | |
3080 | void *ubound; /* One complement of raw ubound field. */ | |
3081 | }; | |
3082 | #endif | |
3083 | ||
3084 | t = arch_composite_type (gdbarch, | |
3085 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
3086 | ||
3087 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
3088 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
3089 | ||
d0e39ea2 | 3090 | t->set_name ("builtin_type_bound128"); |
1dbcd68c WT |
3091 | tdep->i386_bnd_type = t; |
3092 | } | |
3093 | ||
3094 | return tdep->i386_bnd_type; | |
3095 | } | |
3096 | ||
01f9f808 MS |
3097 | /* Construct vector type for pseudo ZMM registers. We can't use |
3098 | tdesc_find_type since ZMM isn't described in target description. */ | |
3099 | ||
3100 | static struct type * | |
3101 | i386_zmm_type (struct gdbarch *gdbarch) | |
3102 | { | |
3103 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3104 | ||
3105 | if (!tdep->i386_zmm_type) | |
3106 | { | |
3107 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3108 | ||
3109 | /* The type we're building is this: */ | |
3110 | #if 0 | |
3111 | union __gdb_builtin_type_vec512i | |
3112 | { | |
1347d111 FW |
3113 | int128_t v4_int128[4]; |
3114 | int64_t v8_int64[8]; | |
3115 | int32_t v16_int32[16]; | |
3116 | int16_t v32_int16[32]; | |
3117 | int8_t v64_int8[64]; | |
3118 | double v8_double[8]; | |
3119 | float v16_float[16]; | |
2a67f09d | 3120 | bfloat16_t v32_bfloat16[32]; |
01f9f808 MS |
3121 | }; |
3122 | #endif | |
3123 | ||
3124 | struct type *t; | |
3125 | ||
3126 | t = arch_composite_type (gdbarch, | |
3127 | "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); | |
2a67f09d FW |
3128 | append_composite_type_field (t, "v32_bfloat16", |
3129 | init_vector_type (bt->builtin_bfloat16, 32)); | |
01f9f808 MS |
3130 | append_composite_type_field (t, "v16_float", |
3131 | init_vector_type (bt->builtin_float, 16)); | |
3132 | append_composite_type_field (t, "v8_double", | |
3133 | init_vector_type (bt->builtin_double, 8)); | |
3134 | append_composite_type_field (t, "v64_int8", | |
3135 | init_vector_type (bt->builtin_int8, 64)); | |
3136 | append_composite_type_field (t, "v32_int16", | |
3137 | init_vector_type (bt->builtin_int16, 32)); | |
3138 | append_composite_type_field (t, "v16_int32", | |
3139 | init_vector_type (bt->builtin_int32, 16)); | |
3140 | append_composite_type_field (t, "v8_int64", | |
3141 | init_vector_type (bt->builtin_int64, 8)); | |
3142 | append_composite_type_field (t, "v4_int128", | |
3143 | init_vector_type (bt->builtin_int128, 4)); | |
3144 | ||
2062087b | 3145 | t->set_is_vector (true); |
d0e39ea2 | 3146 | t->set_name ("builtin_type_vec512i"); |
01f9f808 MS |
3147 | tdep->i386_zmm_type = t; |
3148 | } | |
3149 | ||
3150 | return tdep->i386_zmm_type; | |
3151 | } | |
3152 | ||
c131fcee L |
3153 | /* Construct vector type for pseudo YMM registers. We can't use |
3154 | tdesc_find_type since YMM isn't described in target description. */ | |
3155 | ||
3156 | static struct type * | |
3157 | i386_ymm_type (struct gdbarch *gdbarch) | |
3158 | { | |
3159 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3160 | ||
3161 | if (!tdep->i386_ymm_type) | |
3162 | { | |
3163 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3164 | ||
3165 | /* The type we're building is this: */ | |
3166 | #if 0 | |
3167 | union __gdb_builtin_type_vec256i | |
3168 | { | |
dda83cd7 SM |
3169 | int128_t v2_int128[2]; |
3170 | int64_t v4_int64[4]; | |
3171 | int32_t v8_int32[8]; | |
3172 | int16_t v16_int16[16]; | |
3173 | int8_t v32_int8[32]; | |
3174 | double v4_double[4]; | |
3175 | float v8_float[8]; | |
3176 | bfloat16_t v16_bfloat16[16]; | |
c131fcee L |
3177 | }; |
3178 | #endif | |
3179 | ||
3180 | struct type *t; | |
3181 | ||
3182 | t = arch_composite_type (gdbarch, | |
3183 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2a67f09d FW |
3184 | append_composite_type_field (t, "v16_bfloat16", |
3185 | init_vector_type (bt->builtin_bfloat16, 16)); | |
c131fcee L |
3186 | append_composite_type_field (t, "v8_float", |
3187 | init_vector_type (bt->builtin_float, 8)); | |
3188 | append_composite_type_field (t, "v4_double", | |
3189 | init_vector_type (bt->builtin_double, 4)); | |
3190 | append_composite_type_field (t, "v32_int8", | |
3191 | init_vector_type (bt->builtin_int8, 32)); | |
3192 | append_composite_type_field (t, "v16_int16", | |
3193 | init_vector_type (bt->builtin_int16, 16)); | |
3194 | append_composite_type_field (t, "v8_int32", | |
3195 | init_vector_type (bt->builtin_int32, 8)); | |
3196 | append_composite_type_field (t, "v4_int64", | |
3197 | init_vector_type (bt->builtin_int64, 4)); | |
3198 | append_composite_type_field (t, "v2_int128", | |
3199 | init_vector_type (bt->builtin_int128, 2)); | |
3200 | ||
2062087b | 3201 | t->set_is_vector (true); |
d0e39ea2 | 3202 | t->set_name ("builtin_type_vec256i"); |
c131fcee L |
3203 | tdep->i386_ymm_type = t; |
3204 | } | |
3205 | ||
3206 | return tdep->i386_ymm_type; | |
3207 | } | |
3208 | ||
794ac428 | 3209 | /* Construct vector type for MMX registers. */ |
90884b2b | 3210 | static struct type * |
794ac428 UW |
3211 | i386_mmx_type (struct gdbarch *gdbarch) |
3212 | { | |
3213 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3214 | ||
3215 | if (!tdep->i386_mmx_type) | |
3216 | { | |
df4df182 UW |
3217 | const struct builtin_type *bt = builtin_type (gdbarch); |
3218 | ||
794ac428 UW |
3219 | /* The type we're building is this: */ |
3220 | #if 0 | |
3221 | union __gdb_builtin_type_vec64i | |
3222 | { | |
dda83cd7 SM |
3223 | int64_t uint64; |
3224 | int32_t v2_int32[2]; | |
3225 | int16_t v4_int16[4]; | |
3226 | int8_t v8_int8[8]; | |
794ac428 UW |
3227 | }; |
3228 | #endif | |
3229 | ||
3230 | struct type *t; | |
3231 | ||
e9bb382b UW |
3232 | t = arch_composite_type (gdbarch, |
3233 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
3234 | |
3235 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 3236 | append_composite_type_field (t, "v2_int32", |
df4df182 | 3237 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 3238 | append_composite_type_field (t, "v4_int16", |
df4df182 | 3239 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 3240 | append_composite_type_field (t, "v8_int8", |
df4df182 | 3241 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 3242 | |
2062087b | 3243 | t->set_is_vector (true); |
d0e39ea2 | 3244 | t->set_name ("builtin_type_vec64i"); |
794ac428 UW |
3245 | tdep->i386_mmx_type = t; |
3246 | } | |
3247 | ||
3248 | return tdep->i386_mmx_type; | |
3249 | } | |
3250 | ||
d7a0d72c | 3251 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 3252 | register REGNUM. */ |
d7a0d72c | 3253 | |
fff4548b | 3254 | struct type * |
90884b2b | 3255 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 3256 | { |
1dbcd68c WT |
3257 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3258 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
3259 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
3260 | return i386_mmx_type (gdbarch); | |
c131fcee L |
3261 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
3262 | return i386_ymm_type (gdbarch); | |
01f9f808 MS |
3263 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3264 | return i386_ymm_type (gdbarch); | |
3265 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3266 | return i386_zmm_type (gdbarch); | |
1ba53b71 L |
3267 | else |
3268 | { | |
3269 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3270 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
3271 | return bt->builtin_int8; | |
3272 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3273 | return bt->builtin_int16; | |
3274 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
3275 | return bt->builtin_int32; | |
01f9f808 MS |
3276 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3277 | return bt->builtin_int64; | |
1ba53b71 L |
3278 | } |
3279 | ||
3280 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
3281 | } |
3282 | ||
28fc6740 | 3283 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 3284 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
3285 | |
3286 | static int | |
849d0ba8 | 3287 | i386_mmx_regnum_to_fp_regnum (readable_regcache *regcache, int regnum) |
28fc6740 | 3288 | { |
ac7936df | 3289 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
5716833c | 3290 | int mmxreg, fpreg; |
28fc6740 AC |
3291 | ULONGEST fstat; |
3292 | int tos; | |
c86c27af | 3293 | |
5716833c | 3294 | mmxreg = regnum - tdep->mm0_regnum; |
03f50fc8 | 3295 | regcache->raw_read (I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 3296 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
3297 | fpreg = (mmxreg + tos) % 8; |
3298 | ||
20a6ec49 | 3299 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
3300 | } |
3301 | ||
3543a589 TT |
3302 | /* A helper function for us by i386_pseudo_register_read_value and |
3303 | amd64_pseudo_register_read_value. It does all the work but reads | |
3304 | the data into an already-allocated value. */ | |
3305 | ||
3306 | void | |
3307 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
849d0ba8 | 3308 | readable_regcache *regcache, |
3543a589 TT |
3309 | int regnum, |
3310 | struct value *result_value) | |
28fc6740 | 3311 | { |
975c21ab | 3312 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
05d1431c | 3313 | enum register_status status; |
3543a589 | 3314 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 3315 | |
5716833c | 3316 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3317 | { |
c86c27af MK |
3318 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3319 | ||
28fc6740 | 3320 | /* Extract (always little endian). */ |
03f50fc8 | 3321 | status = regcache->raw_read (fpnum, raw_buf); |
05d1431c | 3322 | if (status != REG_VALID) |
3543a589 TT |
3323 | mark_value_bytes_unavailable (result_value, 0, |
3324 | TYPE_LENGTH (value_type (result_value))); | |
3325 | else | |
3326 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3327 | } |
3328 | else | |
1ba53b71 L |
3329 | { |
3330 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dbcd68c WT |
3331 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3332 | { | |
3333 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3334 | |
1dbcd68c | 3335 | /* Extract (always little endian). Read lower 128bits. */ |
03f50fc8 YQ |
3336 | status = regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum, |
3337 | raw_buf); | |
1dbcd68c WT |
3338 | if (status != REG_VALID) |
3339 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3340 | else | |
3341 | { | |
3342 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3343 | LONGEST upper, lower; | |
3344 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3345 | ||
3346 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3347 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3348 | upper = ~upper; | |
3349 | ||
3350 | memcpy (buf, &lower, size); | |
3351 | memcpy (buf + size, &upper, size); | |
3352 | } | |
3353 | } | |
01f9f808 MS |
3354 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3355 | { | |
3356 | regnum -= tdep->k0_regnum; | |
3357 | ||
3358 | /* Extract (always little endian). */ | |
03f50fc8 | 3359 | status = regcache->raw_read (tdep->k0_regnum + regnum, raw_buf); |
01f9f808 MS |
3360 | if (status != REG_VALID) |
3361 | mark_value_bytes_unavailable (result_value, 0, 8); | |
3362 | else | |
3363 | memcpy (buf, raw_buf, 8); | |
3364 | } | |
3365 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3366 | { | |
3367 | regnum -= tdep->zmm0_regnum; | |
3368 | ||
3369 | if (regnum < num_lower_zmm_regs) | |
3370 | { | |
3371 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3372 | status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum, |
3373 | raw_buf); | |
01f9f808 MS |
3374 | if (status != REG_VALID) |
3375 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3376 | else | |
3377 | memcpy (buf, raw_buf, 16); | |
3378 | ||
3379 | /* Extract (always little endian). Read upper 128bits. */ | |
03f50fc8 YQ |
3380 | status = regcache->raw_read (tdep->ymm0h_regnum + regnum, |
3381 | raw_buf); | |
01f9f808 MS |
3382 | if (status != REG_VALID) |
3383 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3384 | else | |
3385 | memcpy (buf + 16, raw_buf, 16); | |
3386 | } | |
3387 | else | |
3388 | { | |
3389 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3390 | status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum |
3391 | - num_lower_zmm_regs, | |
3392 | raw_buf); | |
01f9f808 MS |
3393 | if (status != REG_VALID) |
3394 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3395 | else | |
3396 | memcpy (buf, raw_buf, 16); | |
3397 | ||
3398 | /* Extract (always little endian). Read upper 128bits. */ | |
03f50fc8 YQ |
3399 | status = regcache->raw_read (I387_YMM16H_REGNUM (tdep) + regnum |
3400 | - num_lower_zmm_regs, | |
3401 | raw_buf); | |
01f9f808 MS |
3402 | if (status != REG_VALID) |
3403 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3404 | else | |
3405 | memcpy (buf + 16, raw_buf, 16); | |
3406 | } | |
3407 | ||
3408 | /* Read upper 256bits. */ | |
03f50fc8 YQ |
3409 | status = regcache->raw_read (tdep->zmm0h_regnum + regnum, |
3410 | raw_buf); | |
01f9f808 MS |
3411 | if (status != REG_VALID) |
3412 | mark_value_bytes_unavailable (result_value, 32, 32); | |
3413 | else | |
3414 | memcpy (buf + 32, raw_buf, 32); | |
3415 | } | |
1dbcd68c | 3416 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3417 | { |
3418 | regnum -= tdep->ymm0_regnum; | |
3419 | ||
1777feb0 | 3420 | /* Extract (always little endian). Read lower 128bits. */ |
03f50fc8 YQ |
3421 | status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum, |
3422 | raw_buf); | |
05d1431c | 3423 | if (status != REG_VALID) |
3543a589 TT |
3424 | mark_value_bytes_unavailable (result_value, 0, 16); |
3425 | else | |
3426 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3427 | /* Read upper 128bits. */ |
03f50fc8 YQ |
3428 | status = regcache->raw_read (tdep->ymm0h_regnum + regnum, |
3429 | raw_buf); | |
05d1431c | 3430 | if (status != REG_VALID) |
3543a589 TT |
3431 | mark_value_bytes_unavailable (result_value, 16, 32); |
3432 | else | |
3433 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee | 3434 | } |
01f9f808 MS |
3435 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3436 | { | |
3437 | regnum -= tdep->ymm16_regnum; | |
3438 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3439 | status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum, |
3440 | raw_buf); | |
01f9f808 MS |
3441 | if (status != REG_VALID) |
3442 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3443 | else | |
3444 | memcpy (buf, raw_buf, 16); | |
3445 | /* Read upper 128bits. */ | |
03f50fc8 YQ |
3446 | status = regcache->raw_read (tdep->ymm16h_regnum + regnum, |
3447 | raw_buf); | |
01f9f808 MS |
3448 | if (status != REG_VALID) |
3449 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3450 | else | |
3451 | memcpy (buf + 16, raw_buf, 16); | |
3452 | } | |
c131fcee | 3453 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3454 | { |
3455 | int gpnum = regnum - tdep->ax_regnum; | |
3456 | ||
3457 | /* Extract (always little endian). */ | |
03f50fc8 | 3458 | status = regcache->raw_read (gpnum, raw_buf); |
05d1431c | 3459 | if (status != REG_VALID) |
3543a589 TT |
3460 | mark_value_bytes_unavailable (result_value, 0, |
3461 | TYPE_LENGTH (value_type (result_value))); | |
3462 | else | |
3463 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3464 | } |
3465 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3466 | { | |
1ba53b71 L |
3467 | int gpnum = regnum - tdep->al_regnum; |
3468 | ||
3469 | /* Extract (always little endian). We read both lower and | |
3470 | upper registers. */ | |
03f50fc8 | 3471 | status = regcache->raw_read (gpnum % 4, raw_buf); |
05d1431c | 3472 | if (status != REG_VALID) |
3543a589 TT |
3473 | mark_value_bytes_unavailable (result_value, 0, |
3474 | TYPE_LENGTH (value_type (result_value))); | |
3475 | else if (gpnum >= 4) | |
1ba53b71 L |
3476 | memcpy (buf, raw_buf + 1, 1); |
3477 | else | |
3478 | memcpy (buf, raw_buf, 1); | |
3479 | } | |
3480 | else | |
3481 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3482 | } | |
3543a589 TT |
3483 | } |
3484 | ||
3485 | static struct value * | |
3486 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
849d0ba8 | 3487 | readable_regcache *regcache, |
3543a589 TT |
3488 | int regnum) |
3489 | { | |
3490 | struct value *result; | |
3491 | ||
3492 | result = allocate_value (register_type (gdbarch, regnum)); | |
3493 | VALUE_LVAL (result) = lval_register; | |
3494 | VALUE_REGNUM (result) = regnum; | |
3495 | ||
3496 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3497 | |
3543a589 | 3498 | return result; |
28fc6740 AC |
3499 | } |
3500 | ||
1ba53b71 | 3501 | void |
28fc6740 | 3502 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3503 | int regnum, const gdb_byte *buf) |
28fc6740 | 3504 | { |
975c21ab | 3505 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
1ba53b71 | 3506 | |
5716833c | 3507 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3508 | { |
c86c27af MK |
3509 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3510 | ||
28fc6740 | 3511 | /* Read ... */ |
0b883586 | 3512 | regcache->raw_read (fpnum, raw_buf); |
28fc6740 | 3513 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3514 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3515 | /* ... Write. */ |
10eaee5f | 3516 | regcache->raw_write (fpnum, raw_buf); |
28fc6740 AC |
3517 | } |
3518 | else | |
1ba53b71 L |
3519 | { |
3520 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3521 | ||
1dbcd68c WT |
3522 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3523 | { | |
3524 | ULONGEST upper, lower; | |
3525 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3526 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3527 | ||
3528 | /* New values from input value. */ | |
3529 | regnum -= tdep->bnd0_regnum; | |
3530 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3531 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3532 | ||
3533 | /* Fetching register buffer. */ | |
0b883586 SM |
3534 | regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum, |
3535 | raw_buf); | |
1dbcd68c WT |
3536 | |
3537 | upper = ~upper; | |
3538 | ||
3539 | /* Set register bits. */ | |
3540 | memcpy (raw_buf, &lower, 8); | |
3541 | memcpy (raw_buf + 8, &upper, 8); | |
3542 | ||
10eaee5f | 3543 | regcache->raw_write (I387_BND0R_REGNUM (tdep) + regnum, raw_buf); |
1dbcd68c | 3544 | } |
01f9f808 MS |
3545 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3546 | { | |
3547 | regnum -= tdep->k0_regnum; | |
3548 | ||
10eaee5f | 3549 | regcache->raw_write (tdep->k0_regnum + regnum, buf); |
01f9f808 MS |
3550 | } |
3551 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3552 | { | |
3553 | regnum -= tdep->zmm0_regnum; | |
3554 | ||
3555 | if (regnum < num_lower_zmm_regs) | |
3556 | { | |
3557 | /* Write lower 128bits. */ | |
10eaee5f | 3558 | regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf); |
01f9f808 | 3559 | /* Write upper 128bits. */ |
10eaee5f | 3560 | regcache->raw_write (I387_YMM0_REGNUM (tdep) + regnum, buf + 16); |
01f9f808 MS |
3561 | } |
3562 | else | |
3563 | { | |
3564 | /* Write lower 128bits. */ | |
10eaee5f SM |
3565 | regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum |
3566 | - num_lower_zmm_regs, buf); | |
01f9f808 | 3567 | /* Write upper 128bits. */ |
10eaee5f SM |
3568 | regcache->raw_write (I387_YMM16H_REGNUM (tdep) + regnum |
3569 | - num_lower_zmm_regs, buf + 16); | |
01f9f808 MS |
3570 | } |
3571 | /* Write upper 256bits. */ | |
10eaee5f | 3572 | regcache->raw_write (tdep->zmm0h_regnum + regnum, buf + 32); |
01f9f808 | 3573 | } |
1dbcd68c | 3574 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3575 | { |
3576 | regnum -= tdep->ymm0_regnum; | |
3577 | ||
3578 | /* ... Write lower 128bits. */ | |
10eaee5f | 3579 | regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf); |
c131fcee | 3580 | /* ... Write upper 128bits. */ |
10eaee5f | 3581 | regcache->raw_write (tdep->ymm0h_regnum + regnum, buf + 16); |
c131fcee | 3582 | } |
01f9f808 MS |
3583 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3584 | { | |
3585 | regnum -= tdep->ymm16_regnum; | |
3586 | ||
3587 | /* ... Write lower 128bits. */ | |
10eaee5f | 3588 | regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum, buf); |
01f9f808 | 3589 | /* ... Write upper 128bits. */ |
10eaee5f | 3590 | regcache->raw_write (tdep->ymm16h_regnum + regnum, buf + 16); |
01f9f808 | 3591 | } |
c131fcee | 3592 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3593 | { |
3594 | int gpnum = regnum - tdep->ax_regnum; | |
3595 | ||
3596 | /* Read ... */ | |
0b883586 | 3597 | regcache->raw_read (gpnum, raw_buf); |
1ba53b71 L |
3598 | /* ... Modify ... (always little endian). */ |
3599 | memcpy (raw_buf, buf, 2); | |
3600 | /* ... Write. */ | |
10eaee5f | 3601 | regcache->raw_write (gpnum, raw_buf); |
1ba53b71 L |
3602 | } |
3603 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3604 | { | |
1ba53b71 L |
3605 | int gpnum = regnum - tdep->al_regnum; |
3606 | ||
3607 | /* Read ... We read both lower and upper registers. */ | |
0b883586 | 3608 | regcache->raw_read (gpnum % 4, raw_buf); |
1ba53b71 L |
3609 | /* ... Modify ... (always little endian). */ |
3610 | if (gpnum >= 4) | |
3611 | memcpy (raw_buf + 1, buf, 1); | |
3612 | else | |
3613 | memcpy (raw_buf, buf, 1); | |
3614 | /* ... Write. */ | |
10eaee5f | 3615 | regcache->raw_write (gpnum % 4, raw_buf); |
1ba53b71 L |
3616 | } |
3617 | else | |
3618 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3619 | } | |
28fc6740 | 3620 | } |
62e5fd57 MK |
3621 | |
3622 | /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ | |
3623 | ||
3624 | int | |
3625 | i386_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3626 | struct agent_expr *ax, int regnum) | |
3627 | { | |
3628 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3629 | ||
3630 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
3631 | { | |
3632 | /* MMX to FPU register mapping depends on current TOS. Let's just | |
3633 | not care and collect everything... */ | |
3634 | int i; | |
3635 | ||
3636 | ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep)); | |
3637 | for (i = 0; i < 8; i++) | |
3638 | ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i); | |
3639 | return 0; | |
3640 | } | |
3641 | else if (i386_bnd_regnum_p (gdbarch, regnum)) | |
3642 | { | |
3643 | regnum -= tdep->bnd0_regnum; | |
3644 | ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum); | |
3645 | return 0; | |
3646 | } | |
3647 | else if (i386_k_regnum_p (gdbarch, regnum)) | |
3648 | { | |
3649 | regnum -= tdep->k0_regnum; | |
3650 | ax_reg_mask (ax, tdep->k0_regnum + regnum); | |
3651 | return 0; | |
3652 | } | |
3653 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3654 | { | |
3655 | regnum -= tdep->zmm0_regnum; | |
3656 | if (regnum < num_lower_zmm_regs) | |
3657 | { | |
3658 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3659 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3660 | } | |
3661 | else | |
3662 | { | |
3663 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum | |
3664 | - num_lower_zmm_regs); | |
3665 | ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum | |
3666 | - num_lower_zmm_regs); | |
3667 | } | |
3668 | ax_reg_mask (ax, tdep->zmm0h_regnum + regnum); | |
3669 | return 0; | |
3670 | } | |
3671 | else if (i386_ymm_regnum_p (gdbarch, regnum)) | |
3672 | { | |
3673 | regnum -= tdep->ymm0_regnum; | |
3674 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3675 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3676 | return 0; | |
3677 | } | |
3678 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) | |
3679 | { | |
3680 | regnum -= tdep->ymm16_regnum; | |
3681 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum); | |
3682 | ax_reg_mask (ax, tdep->ymm16h_regnum + regnum); | |
3683 | return 0; | |
3684 | } | |
3685 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3686 | { | |
3687 | int gpnum = regnum - tdep->ax_regnum; | |
3688 | ||
3689 | ax_reg_mask (ax, gpnum); | |
3690 | return 0; | |
3691 | } | |
3692 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3693 | { | |
3694 | int gpnum = regnum - tdep->al_regnum; | |
3695 | ||
3696 | ax_reg_mask (ax, gpnum % 4); | |
3697 | return 0; | |
3698 | } | |
3699 | else | |
3700 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3701 | return 1; | |
3702 | } | |
ff2e87ac AC |
3703 | \f |
3704 | ||
ff2e87ac AC |
3705 | /* Return the register number of the register allocated by GCC after |
3706 | REGNUM, or -1 if there is no such register. */ | |
3707 | ||
3708 | static int | |
3709 | i386_next_regnum (int regnum) | |
3710 | { | |
3711 | /* GCC allocates the registers in the order: | |
3712 | ||
3713 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3714 | ||
3715 | Since storing a variable in %esp doesn't make any sense we return | |
3716 | -1 for %ebp and for %esp itself. */ | |
3717 | static int next_regnum[] = | |
3718 | { | |
3719 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3720 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3721 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3722 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3723 | -1, -1, /* Slots for %esp and %ebp. */ | |
3724 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3725 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3726 | }; | |
3727 | ||
de5b9bb9 | 3728 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3729 | return next_regnum[regnum]; |
28fc6740 | 3730 | |
ff2e87ac AC |
3731 | return -1; |
3732 | } | |
3733 | ||
3734 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3735 | needs any special handling. */ | |
d7a0d72c | 3736 | |
3a1e71e3 | 3737 | static int |
1777feb0 MS |
3738 | i386_convert_register_p (struct gdbarch *gdbarch, |
3739 | int regnum, struct type *type) | |
d7a0d72c | 3740 | { |
de5b9bb9 MK |
3741 | int len = TYPE_LENGTH (type); |
3742 | ||
ff2e87ac AC |
3743 | /* Values may be spread across multiple registers. Most debugging |
3744 | formats aren't expressive enough to specify the locations, so | |
3745 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3746 | have a length that is a multiple of the word size, since GCC |
3747 | doesn't seem to put any other types into registers. */ | |
3748 | if (len > 4 && len % 4 == 0) | |
3749 | { | |
3750 | int last_regnum = regnum; | |
3751 | ||
3752 | while (len > 4) | |
3753 | { | |
3754 | last_regnum = i386_next_regnum (last_regnum); | |
3755 | len -= 4; | |
3756 | } | |
3757 | ||
3758 | if (last_regnum != -1) | |
3759 | return 1; | |
3760 | } | |
ff2e87ac | 3761 | |
0abe36f5 | 3762 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3763 | } |
3764 | ||
ff2e87ac AC |
3765 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3766 | return its contents in TO. */ | |
ac27f131 | 3767 | |
8dccd430 | 3768 | static int |
ff2e87ac | 3769 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3770 | struct type *type, gdb_byte *to, |
3771 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3772 | { |
20a6ec49 | 3773 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3774 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3775 | |
20a6ec49 | 3776 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3777 | return i387_register_to_value (frame, regnum, type, to, |
3778 | optimizedp, unavailablep); | |
ff2e87ac | 3779 | |
fd35795f | 3780 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3781 | |
3782 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3783 | |
de5b9bb9 MK |
3784 | while (len > 0) |
3785 | { | |
3786 | gdb_assert (regnum != -1); | |
20a6ec49 | 3787 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3788 | |
8dccd430 | 3789 | if (!get_frame_register_bytes (frame, regnum, 0, |
bdec2917 LM |
3790 | gdb::make_array_view (to, |
3791 | register_size (gdbarch, | |
3792 | regnum)), | |
3793 | optimizedp, unavailablep)) | |
8dccd430 PA |
3794 | return 0; |
3795 | ||
de5b9bb9 MK |
3796 | regnum = i386_next_regnum (regnum); |
3797 | len -= 4; | |
42835c2b | 3798 | to += 4; |
de5b9bb9 | 3799 | } |
8dccd430 PA |
3800 | |
3801 | *optimizedp = *unavailablep = 0; | |
3802 | return 1; | |
ac27f131 MK |
3803 | } |
3804 | ||
ff2e87ac AC |
3805 | /* Write the contents FROM of a value of type TYPE into register |
3806 | REGNUM in frame FRAME. */ | |
ac27f131 | 3807 | |
3a1e71e3 | 3808 | static void |
ff2e87ac | 3809 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3810 | struct type *type, const gdb_byte *from) |
ac27f131 | 3811 | { |
de5b9bb9 | 3812 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3813 | |
20a6ec49 | 3814 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3815 | { |
d532c08f MK |
3816 | i387_value_to_register (frame, regnum, type, from); |
3817 | return; | |
3818 | } | |
3d261580 | 3819 | |
fd35795f | 3820 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3821 | |
3822 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3823 | |
de5b9bb9 MK |
3824 | while (len > 0) |
3825 | { | |
3826 | gdb_assert (regnum != -1); | |
875f8d0e | 3827 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3828 | |
42835c2b | 3829 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3830 | regnum = i386_next_regnum (regnum); |
3831 | len -= 4; | |
42835c2b | 3832 | from += 4; |
de5b9bb9 | 3833 | } |
ac27f131 | 3834 | } |
ff2e87ac | 3835 | \f |
7fdafb5a MK |
3836 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3837 | in the general-purpose register set REGSET to register cache | |
3838 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3839 | |
20187ed5 | 3840 | void |
473f17b0 MK |
3841 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3842 | int regnum, const void *gregs, size_t len) | |
3843 | { | |
ac7936df | 3844 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3845 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9a3c8263 | 3846 | const gdb_byte *regs = (const gdb_byte *) gregs; |
473f17b0 MK |
3847 | int i; |
3848 | ||
1528345d | 3849 | gdb_assert (len >= tdep->sizeof_gregset); |
473f17b0 MK |
3850 | |
3851 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3852 | { | |
3853 | if ((regnum == i || regnum == -1) | |
3854 | && tdep->gregset_reg_offset[i] != -1) | |
73e1c03f | 3855 | regcache->raw_supply (i, regs + tdep->gregset_reg_offset[i]); |
473f17b0 MK |
3856 | } |
3857 | } | |
3858 | ||
7fdafb5a MK |
3859 | /* Collect register REGNUM from the register cache REGCACHE and store |
3860 | it in the buffer specified by GREGS and LEN as described by the | |
3861 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3862 | all registers in REGSET. */ | |
3863 | ||
ecc37a5a | 3864 | static void |
7fdafb5a MK |
3865 | i386_collect_gregset (const struct regset *regset, |
3866 | const struct regcache *regcache, | |
3867 | int regnum, void *gregs, size_t len) | |
3868 | { | |
ac7936df | 3869 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3870 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9a3c8263 | 3871 | gdb_byte *regs = (gdb_byte *) gregs; |
7fdafb5a MK |
3872 | int i; |
3873 | ||
1528345d | 3874 | gdb_assert (len >= tdep->sizeof_gregset); |
7fdafb5a MK |
3875 | |
3876 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3877 | { | |
3878 | if ((regnum == i || regnum == -1) | |
3879 | && tdep->gregset_reg_offset[i] != -1) | |
34a79281 | 3880 | regcache->raw_collect (i, regs + tdep->gregset_reg_offset[i]); |
7fdafb5a MK |
3881 | } |
3882 | } | |
3883 | ||
3884 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3885 | in the floating-point register set REGSET to register cache | |
3886 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3887 | |
3888 | static void | |
3889 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3890 | int regnum, const void *fpregs, size_t len) | |
3891 | { | |
ac7936df | 3892 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3893 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
473f17b0 | 3894 | |
66a72d25 MK |
3895 | if (len == I387_SIZEOF_FXSAVE) |
3896 | { | |
3897 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3898 | return; | |
3899 | } | |
3900 | ||
1528345d | 3901 | gdb_assert (len >= tdep->sizeof_fpregset); |
473f17b0 MK |
3902 | i387_supply_fsave (regcache, regnum, fpregs); |
3903 | } | |
8446b36a | 3904 | |
2f305df1 MK |
3905 | /* Collect register REGNUM from the register cache REGCACHE and store |
3906 | it in the buffer specified by FPREGS and LEN as described by the | |
3907 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3908 | all registers in REGSET. */ | |
7fdafb5a MK |
3909 | |
3910 | static void | |
3911 | i386_collect_fpregset (const struct regset *regset, | |
3912 | const struct regcache *regcache, | |
3913 | int regnum, void *fpregs, size_t len) | |
3914 | { | |
ac7936df | 3915 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3916 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7fdafb5a MK |
3917 | |
3918 | if (len == I387_SIZEOF_FXSAVE) | |
3919 | { | |
3920 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3921 | return; | |
3922 | } | |
3923 | ||
1528345d | 3924 | gdb_assert (len >= tdep->sizeof_fpregset); |
7fdafb5a MK |
3925 | i387_collect_fsave (regcache, regnum, fpregs); |
3926 | } | |
3927 | ||
ecc37a5a AA |
3928 | /* Register set definitions. */ |
3929 | ||
3930 | const struct regset i386_gregset = | |
3931 | { | |
3932 | NULL, i386_supply_gregset, i386_collect_gregset | |
3933 | }; | |
3934 | ||
8f0435f7 | 3935 | const struct regset i386_fpregset = |
ecc37a5a AA |
3936 | { |
3937 | NULL, i386_supply_fpregset, i386_collect_fpregset | |
3938 | }; | |
3939 | ||
490496c3 | 3940 | /* Default iterator over core file register note sections. */ |
8446b36a | 3941 | |
490496c3 AA |
3942 | void |
3943 | i386_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
3944 | iterate_over_regset_sections_cb *cb, | |
3945 | void *cb_data, | |
3946 | const struct regcache *regcache) | |
8446b36a MK |
3947 | { |
3948 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3949 | ||
a616bb94 AH |
3950 | cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, &i386_gregset, NULL, |
3951 | cb_data); | |
490496c3 | 3952 | if (tdep->sizeof_fpregset) |
a616bb94 AH |
3953 | cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, |
3954 | NULL, cb_data); | |
8446b36a | 3955 | } |
473f17b0 | 3956 | \f |
fc338970 | 3957 | |
fc338970 | 3958 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3959 | |
3960 | CORE_ADDR | |
e17a4113 UW |
3961 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3962 | CORE_ADDR pc, char *name) | |
c906108c | 3963 | { |
e17a4113 UW |
3964 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3965 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3966 | ||
3967 | /* jmp *(dest) */ | |
3968 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3969 | { |
e17a4113 UW |
3970 | unsigned long indirect = |
3971 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3972 | struct minimal_symbol *indsym = |
7cbd4a93 | 3973 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
c9d95fa3 | 3974 | const char *symname = indsym ? indsym->linkage_name () : 0; |
c906108c | 3975 | |
c5aa993b | 3976 | if (symname) |
c906108c | 3977 | { |
61012eef GB |
3978 | if (startswith (symname, "__imp_") |
3979 | || startswith (symname, "_imp_")) | |
e17a4113 UW |
3980 | return name ? 1 : |
3981 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3982 | } |
3983 | } | |
fc338970 | 3984 | return 0; /* Not a trampoline. */ |
c906108c | 3985 | } |
fc338970 MK |
3986 | \f |
3987 | ||
10458914 DJ |
3988 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3989 | routine. */ | |
8201327c | 3990 | |
4bd207ef | 3991 | int |
10458914 | 3992 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3993 | { |
10458914 | 3994 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3995 | const char *name; |
911bc6ee MK |
3996 | |
3997 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3998 | return (name && strcmp ("_sigtramp", name) == 0); |
3999 | } | |
4000 | \f | |
4001 | ||
fc338970 MK |
4002 | /* We have two flavours of disassembly. The machinery on this page |
4003 | deals with switching between those. */ | |
c906108c SS |
4004 | |
4005 | static int | |
a89aa300 | 4006 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 4007 | { |
5e3397bb MK |
4008 | gdb_assert (disassembly_flavor == att_flavor |
4009 | || disassembly_flavor == intel_flavor); | |
4010 | ||
f995bbe8 | 4011 | info->disassembler_options = disassembly_flavor; |
5e3397bb | 4012 | |
6394c606 | 4013 | return default_print_insn (pc, info); |
7a292a7a | 4014 | } |
fc338970 | 4015 | \f |
3ce1502b | 4016 | |
8201327c MK |
4017 | /* There are a few i386 architecture variants that differ only |
4018 | slightly from the generic i386 target. For now, we don't give them | |
4019 | their own source file, but include them here. As a consequence, | |
4020 | they'll always be included. */ | |
3ce1502b | 4021 | |
8201327c | 4022 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4023 | |
10458914 DJ |
4024 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
4025 | routine. */ | |
911bc6ee | 4026 | |
8201327c | 4027 | static int |
10458914 | 4028 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 4029 | { |
10458914 | 4030 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 4031 | const char *name; |
911bc6ee | 4032 | |
05b4bd79 | 4033 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 4034 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 4035 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
4036 | || strcmp ("sigvechandler", name) == 0)); |
4037 | } | |
d2a7c97a | 4038 | |
10458914 DJ |
4039 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
4040 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 4041 | |
3a1e71e3 | 4042 | static CORE_ADDR |
10458914 | 4043 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 4044 | { |
e17a4113 UW |
4045 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
4046 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 4047 | gdb_byte buf[4]; |
acd5c798 | 4048 | CORE_ADDR sp; |
3ce1502b | 4049 | |
10458914 | 4050 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 4051 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 4052 | |
e17a4113 | 4053 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 4054 | } |
55aa24fb SDJ |
4055 | |
4056 | \f | |
4057 | ||
4058 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
4059 | gdbarch.h. */ | |
4060 | ||
4061 | int | |
4062 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
4063 | { | |
4064 | return (*s == '$' /* Literal number. */ | |
4065 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
4066 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
4067 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
4068 | } | |
4069 | ||
5acfdbae SDJ |
4070 | /* Helper function for i386_stap_parse_special_token. |
4071 | ||
4072 | This function parses operands of the form `-8+3+1(%rbp)', which | |
4073 | must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. | |
4074 | ||
af2d9bee | 4075 | Return true if the operand was parsed successfully, false |
5acfdbae SDJ |
4076 | otherwise. */ |
4077 | ||
4c5e7a93 | 4078 | static expr::operation_up |
5acfdbae SDJ |
4079 | i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, |
4080 | struct stap_parse_info *p) | |
4081 | { | |
4082 | const char *s = p->arg; | |
4083 | ||
4084 | if (isdigit (*s) || *s == '-' || *s == '+') | |
4085 | { | |
af2d9bee | 4086 | bool got_minus[3]; |
5acfdbae SDJ |
4087 | int i; |
4088 | long displacements[3]; | |
4089 | const char *start; | |
5acfdbae | 4090 | int len; |
5acfdbae SDJ |
4091 | char *endp; |
4092 | ||
af2d9bee | 4093 | got_minus[0] = false; |
5acfdbae SDJ |
4094 | if (*s == '+') |
4095 | ++s; | |
4096 | else if (*s == '-') | |
4097 | { | |
4098 | ++s; | |
af2d9bee | 4099 | got_minus[0] = true; |
5acfdbae SDJ |
4100 | } |
4101 | ||
d7b30f67 | 4102 | if (!isdigit ((unsigned char) *s)) |
4c5e7a93 | 4103 | return {}; |
d7b30f67 | 4104 | |
5acfdbae SDJ |
4105 | displacements[0] = strtol (s, &endp, 10); |
4106 | s = endp; | |
4107 | ||
4108 | if (*s != '+' && *s != '-') | |
4109 | { | |
4110 | /* We are not dealing with a triplet. */ | |
4c5e7a93 | 4111 | return {}; |
5acfdbae SDJ |
4112 | } |
4113 | ||
af2d9bee | 4114 | got_minus[1] = false; |
5acfdbae SDJ |
4115 | if (*s == '+') |
4116 | ++s; | |
4117 | else | |
4118 | { | |
4119 | ++s; | |
af2d9bee | 4120 | got_minus[1] = true; |
5acfdbae SDJ |
4121 | } |
4122 | ||
d7b30f67 | 4123 | if (!isdigit ((unsigned char) *s)) |
4c5e7a93 | 4124 | return {}; |
d7b30f67 | 4125 | |
5acfdbae SDJ |
4126 | displacements[1] = strtol (s, &endp, 10); |
4127 | s = endp; | |
4128 | ||
4129 | if (*s != '+' && *s != '-') | |
4130 | { | |
4131 | /* We are not dealing with a triplet. */ | |
4c5e7a93 | 4132 | return {}; |
5acfdbae SDJ |
4133 | } |
4134 | ||
af2d9bee | 4135 | got_minus[2] = false; |
5acfdbae SDJ |
4136 | if (*s == '+') |
4137 | ++s; | |
4138 | else | |
4139 | { | |
4140 | ++s; | |
af2d9bee | 4141 | got_minus[2] = true; |
5acfdbae SDJ |
4142 | } |
4143 | ||
d7b30f67 | 4144 | if (!isdigit ((unsigned char) *s)) |
4c5e7a93 | 4145 | return {}; |
d7b30f67 | 4146 | |
5acfdbae SDJ |
4147 | displacements[2] = strtol (s, &endp, 10); |
4148 | s = endp; | |
4149 | ||
4150 | if (*s != '(' || s[1] != '%') | |
4c5e7a93 | 4151 | return {}; |
5acfdbae SDJ |
4152 | |
4153 | s += 2; | |
4154 | start = s; | |
4155 | ||
4156 | while (isalnum (*s)) | |
4157 | ++s; | |
4158 | ||
4159 | if (*s++ != ')') | |
4c5e7a93 | 4160 | return {}; |
5acfdbae | 4161 | |
d7b30f67 | 4162 | len = s - start - 1; |
4c5e7a93 | 4163 | std::string regname (start, len); |
5acfdbae | 4164 | |
4c5e7a93 | 4165 | if (user_reg_map_name_to_regnum (gdbarch, regname.c_str (), len) == -1) |
5acfdbae | 4166 | error (_("Invalid register name `%s' on expression `%s'."), |
4c5e7a93 | 4167 | regname.c_str (), p->saved_arg); |
5acfdbae | 4168 | |
4c5e7a93 | 4169 | LONGEST value = 0; |
5acfdbae SDJ |
4170 | for (i = 0; i < 3; i++) |
4171 | { | |
4c5e7a93 | 4172 | LONGEST this_val = displacements[i]; |
5acfdbae | 4173 | if (got_minus[i]) |
4c5e7a93 TT |
4174 | this_val = -this_val; |
4175 | value += this_val; | |
5acfdbae SDJ |
4176 | } |
4177 | ||
4c5e7a93 | 4178 | p->arg = s; |
5acfdbae | 4179 | |
4c5e7a93 | 4180 | using namespace expr; |
5acfdbae | 4181 | |
4c5e7a93 TT |
4182 | struct type *long_type = builtin_type (gdbarch)->builtin_long; |
4183 | operation_up offset | |
4184 | = make_operation<long_const_operation> (long_type, value); | |
5acfdbae | 4185 | |
4c5e7a93 TT |
4186 | operation_up reg |
4187 | = make_operation<register_operation> (std::move (regname)); | |
4188 | struct type *void_ptr = builtin_type (gdbarch)->builtin_data_ptr; | |
4189 | reg = make_operation<unop_cast_operation> (std::move (reg), void_ptr); | |
5acfdbae | 4190 | |
4c5e7a93 TT |
4191 | operation_up sum |
4192 | = make_operation<add_operation> (std::move (reg), std::move (offset)); | |
4193 | struct type *arg_ptr_type = lookup_pointer_type (p->arg_type); | |
4194 | sum = make_operation<unop_cast_operation> (std::move (sum), | |
4195 | arg_ptr_type); | |
4196 | return make_operation<unop_ind_operation> (std::move (sum)); | |
5acfdbae SDJ |
4197 | } |
4198 | ||
4c5e7a93 | 4199 | return {}; |
5acfdbae SDJ |
4200 | } |
4201 | ||
4202 | /* Helper function for i386_stap_parse_special_token. | |
4203 | ||
4204 | This function parses operands of the form `register base + | |
4205 | (register index * size) + offset', as represented in | |
4206 | `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4207 | ||
af2d9bee | 4208 | Return true if the operand was parsed successfully, false |
5acfdbae SDJ |
4209 | otherwise. */ |
4210 | ||
4c5e7a93 | 4211 | static expr::operation_up |
5acfdbae SDJ |
4212 | i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, |
4213 | struct stap_parse_info *p) | |
4214 | { | |
4215 | const char *s = p->arg; | |
4216 | ||
4217 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
4218 | { | |
af2d9bee | 4219 | bool offset_minus = false; |
5acfdbae | 4220 | long offset = 0; |
af2d9bee | 4221 | bool size_minus = false; |
5acfdbae SDJ |
4222 | long size = 0; |
4223 | const char *start; | |
5acfdbae | 4224 | int len_base; |
5acfdbae | 4225 | int len_index; |
5acfdbae SDJ |
4226 | |
4227 | if (*s == '+') | |
4228 | ++s; | |
4229 | else if (*s == '-') | |
4230 | { | |
4231 | ++s; | |
af2d9bee | 4232 | offset_minus = true; |
5acfdbae SDJ |
4233 | } |
4234 | ||
4235 | if (offset_minus && !isdigit (*s)) | |
4c5e7a93 | 4236 | return {}; |
5acfdbae SDJ |
4237 | |
4238 | if (isdigit (*s)) | |
4239 | { | |
4240 | char *endp; | |
4241 | ||
4242 | offset = strtol (s, &endp, 10); | |
4243 | s = endp; | |
4244 | } | |
4245 | ||
4246 | if (*s != '(' || s[1] != '%') | |
4c5e7a93 | 4247 | return {}; |
5acfdbae SDJ |
4248 | |
4249 | s += 2; | |
4250 | start = s; | |
4251 | ||
4252 | while (isalnum (*s)) | |
4253 | ++s; | |
4254 | ||
4255 | if (*s != ',' || s[1] != '%') | |
4c5e7a93 | 4256 | return {}; |
5acfdbae SDJ |
4257 | |
4258 | len_base = s - start; | |
4c5e7a93 | 4259 | std::string base (start, len_base); |
5acfdbae | 4260 | |
4c5e7a93 | 4261 | if (user_reg_map_name_to_regnum (gdbarch, base.c_str (), len_base) == -1) |
5acfdbae | 4262 | error (_("Invalid register name `%s' on expression `%s'."), |
4c5e7a93 | 4263 | base.c_str (), p->saved_arg); |
5acfdbae SDJ |
4264 | |
4265 | s += 2; | |
4266 | start = s; | |
4267 | ||
4268 | while (isalnum (*s)) | |
4269 | ++s; | |
4270 | ||
4271 | len_index = s - start; | |
4c5e7a93 | 4272 | std::string index (start, len_index); |
5acfdbae | 4273 | |
4c5e7a93 TT |
4274 | if (user_reg_map_name_to_regnum (gdbarch, index.c_str (), |
4275 | len_index) == -1) | |
5acfdbae | 4276 | error (_("Invalid register name `%s' on expression `%s'."), |
4c5e7a93 | 4277 | index.c_str (), p->saved_arg); |
5acfdbae SDJ |
4278 | |
4279 | if (*s != ',' && *s != ')') | |
4c5e7a93 | 4280 | return {}; |
5acfdbae SDJ |
4281 | |
4282 | if (*s == ',') | |
4283 | { | |
4284 | char *endp; | |
4285 | ||
4286 | ++s; | |
4287 | if (*s == '+') | |
4288 | ++s; | |
4289 | else if (*s == '-') | |
4290 | { | |
4291 | ++s; | |
af2d9bee | 4292 | size_minus = true; |
5acfdbae SDJ |
4293 | } |
4294 | ||
4295 | size = strtol (s, &endp, 10); | |
4296 | s = endp; | |
4297 | ||
4298 | if (*s != ')') | |
4c5e7a93 | 4299 | return {}; |
5acfdbae SDJ |
4300 | } |
4301 | ||
4302 | ++s; | |
4c5e7a93 TT |
4303 | p->arg = s; |
4304 | ||
4305 | using namespace expr; | |
4306 | ||
4307 | struct type *long_type = builtin_type (gdbarch)->builtin_long; | |
4308 | operation_up reg = make_operation<register_operation> (std::move (base)); | |
5acfdbae | 4309 | |
4c5e7a93 | 4310 | if (offset != 0) |
5acfdbae | 4311 | { |
5acfdbae | 4312 | if (offset_minus) |
4c5e7a93 TT |
4313 | offset = -offset; |
4314 | operation_up value | |
4315 | = make_operation<long_const_operation> (long_type, offset); | |
4316 | reg = make_operation<add_operation> (std::move (reg), | |
4317 | std::move (value)); | |
5acfdbae SDJ |
4318 | } |
4319 | ||
4c5e7a93 TT |
4320 | operation_up ind_reg |
4321 | = make_operation<register_operation> (std::move (index)); | |
5acfdbae | 4322 | |
4c5e7a93 | 4323 | if (size != 0) |
5acfdbae | 4324 | { |
5acfdbae | 4325 | if (size_minus) |
4c5e7a93 TT |
4326 | size = -size; |
4327 | operation_up value | |
4328 | = make_operation<long_const_operation> (long_type, size); | |
4329 | ind_reg = make_operation<mul_operation> (std::move (ind_reg), | |
4330 | std::move (value)); | |
5acfdbae SDJ |
4331 | } |
4332 | ||
4c5e7a93 TT |
4333 | operation_up sum |
4334 | = make_operation<add_operation> (std::move (reg), | |
4335 | std::move (ind_reg)); | |
5acfdbae | 4336 | |
4c5e7a93 TT |
4337 | struct type *arg_ptr_type = lookup_pointer_type (p->arg_type); |
4338 | sum = make_operation<unop_cast_operation> (std::move (sum), | |
4339 | arg_ptr_type); | |
4340 | return make_operation<unop_ind_operation> (std::move (sum)); | |
5acfdbae SDJ |
4341 | } |
4342 | ||
4c5e7a93 | 4343 | return {}; |
5acfdbae SDJ |
4344 | } |
4345 | ||
55aa24fb SDJ |
4346 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in |
4347 | gdbarch.h. */ | |
4348 | ||
4c5e7a93 | 4349 | expr::operation_up |
55aa24fb SDJ |
4350 | i386_stap_parse_special_token (struct gdbarch *gdbarch, |
4351 | struct stap_parse_info *p) | |
4352 | { | |
55aa24fb SDJ |
4353 | /* The special tokens to be parsed here are: |
4354 | ||
4355 | - `register base + (register index * size) + offset', as represented | |
4356 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4357 | ||
4358 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
4359 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
4360 | ||
4c5e7a93 TT |
4361 | expr::operation_up result |
4362 | = i386_stap_parse_special_token_triplet (gdbarch, p); | |
55aa24fb | 4363 | |
4c5e7a93 TT |
4364 | if (result == nullptr) |
4365 | result = i386_stap_parse_special_token_three_arg_disp (gdbarch, p); | |
55aa24fb | 4366 | |
4c5e7a93 | 4367 | return result; |
55aa24fb SDJ |
4368 | } |
4369 | ||
7d7571f0 SDJ |
4370 | /* Implementation of 'gdbarch_stap_adjust_register', as defined in |
4371 | gdbarch.h. */ | |
4372 | ||
6b78c3f8 | 4373 | static std::string |
7d7571f0 | 4374 | i386_stap_adjust_register (struct gdbarch *gdbarch, struct stap_parse_info *p, |
6b78c3f8 | 4375 | const std::string ®name, int regnum) |
7d7571f0 SDJ |
4376 | { |
4377 | static const std::unordered_set<std::string> reg_assoc | |
4378 | = { "ax", "bx", "cx", "dx", | |
4379 | "si", "di", "bp", "sp" }; | |
4380 | ||
6b78c3f8 AB |
4381 | /* If we are dealing with a register whose size is less than the size |
4382 | specified by the "[-]N@" prefix, and it is one of the registers that | |
4383 | we know has an extended variant available, then use the extended | |
4384 | version of the register instead. */ | |
4385 | if (register_size (gdbarch, regnum) < TYPE_LENGTH (p->arg_type) | |
4386 | && reg_assoc.find (regname) != reg_assoc.end ()) | |
4387 | return "e" + regname; | |
7d7571f0 | 4388 | |
6b78c3f8 AB |
4389 | /* Otherwise, just use the requested register. */ |
4390 | return regname; | |
7d7571f0 SDJ |
4391 | } |
4392 | ||
8201327c | 4393 | \f |
3ce1502b | 4394 | |
ac04f72b TT |
4395 | /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always |
4396 | also supplies -m64 or -m32 by gdbarch_gcc_target_options. */ | |
4397 | ||
4398 | static const char * | |
4399 | i386_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
4400 | { | |
4401 | return "(x86_64|i.86)"; | |
4402 | } | |
4403 | ||
4404 | \f | |
4405 | ||
1d509aa6 MM |
4406 | /* Implement the "in_indirect_branch_thunk" gdbarch function. */ |
4407 | ||
4408 | static bool | |
4409 | i386_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4410 | { | |
4411 | return x86_in_indirect_branch_thunk (pc, i386_register_names, | |
4412 | I386_EAX_REGNUM, I386_EIP_REGNUM); | |
4413 | } | |
4414 | ||
8201327c | 4415 | /* Generic ELF. */ |
d2a7c97a | 4416 | |
8201327c MK |
4417 | void |
4418 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4419 | { | |
05c0465e SDJ |
4420 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
4421 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
4422 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
4423 | NULL }; | |
4424 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
4425 | NULL }; | |
4426 | ||
c4fc7f1b MK |
4427 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
4428 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
4429 | |
4430 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
4431 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
4432 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
4433 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
4434 | stap_register_indirection_prefixes); | |
4435 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
4436 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
4437 | set_gdbarch_stap_is_single_operand (gdbarch, |
4438 | i386_stap_is_single_operand); | |
4439 | set_gdbarch_stap_parse_special_token (gdbarch, | |
4440 | i386_stap_parse_special_token); | |
7d7571f0 SDJ |
4441 | set_gdbarch_stap_adjust_register (gdbarch, |
4442 | i386_stap_adjust_register); | |
1d509aa6 MM |
4443 | |
4444 | set_gdbarch_in_indirect_branch_thunk (gdbarch, | |
4445 | i386_in_indirect_branch_thunk); | |
8201327c | 4446 | } |
3ce1502b | 4447 | |
8201327c | 4448 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4449 | |
8201327c MK |
4450 | void |
4451 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4452 | { | |
4453 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 4454 | |
8201327c MK |
4455 | /* System V Release 4 uses ELF. */ |
4456 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 4457 | |
dfe01d39 | 4458 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
4459 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
4460 | ||
911bc6ee | 4461 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 4462 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
4463 | tdep->sc_pc_offset = 36 + 14 * 4; |
4464 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 4465 | |
8201327c | 4466 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
4467 | } |
4468 | ||
8201327c | 4469 | \f |
2acceee2 | 4470 | |
38c968cf AC |
4471 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4472 | and "sse". */ | |
4473 | ||
4474 | static struct reggroup *i386_sse_reggroup; | |
4475 | static struct reggroup *i386_mmx_reggroup; | |
4476 | ||
4477 | static void | |
4478 | i386_init_reggroups (void) | |
4479 | { | |
4480 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4481 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4482 | } | |
4483 | ||
4484 | static void | |
4485 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4486 | { | |
4487 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4488 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
4489 | reggroup_add (gdbarch, general_reggroup); | |
4490 | reggroup_add (gdbarch, float_reggroup); | |
4491 | reggroup_add (gdbarch, all_reggroup); | |
4492 | reggroup_add (gdbarch, save_reggroup); | |
4493 | reggroup_add (gdbarch, restore_reggroup); | |
4494 | reggroup_add (gdbarch, vector_reggroup); | |
4495 | reggroup_add (gdbarch, system_reggroup); | |
4496 | } | |
4497 | ||
4498 | int | |
4499 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
4500 | struct reggroup *group) | |
4501 | { | |
c131fcee L |
4502 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4503 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
01f9f808 | 4504 | ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, |
798a7429 SM |
4505 | bndr_regnum_p, bnd_regnum_p, zmm_regnum_p, zmmh_regnum_p, |
4506 | mpx_ctrl_regnum_p, xmm_avx512_regnum_p, | |
51547df6 | 4507 | avx512_p, avx_p, sse_p, pkru_regnum_p; |
acd5c798 | 4508 | |
1ba53b71 L |
4509 | /* Don't include pseudo registers, except for MMX, in any register |
4510 | groups. */ | |
c131fcee | 4511 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4512 | return 0; |
4513 | ||
c131fcee | 4514 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4515 | return 0; |
4516 | ||
c131fcee | 4517 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4518 | return 0; |
4519 | ||
4520 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4521 | if (group == i386_mmx_reggroup) |
4522 | return mmx_regnum_p; | |
1ba53b71 | 4523 | |
51547df6 | 4524 | pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum); |
c131fcee | 4525 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
01f9f808 | 4526 | xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); |
c131fcee | 4527 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
38c968cf | 4528 | if (group == i386_sse_reggroup) |
01f9f808 | 4529 | return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; |
c131fcee L |
4530 | |
4531 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4532 | ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); |
4533 | zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); | |
4534 | ||
22049425 MS |
4535 | avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
4536 | == X86_XSTATE_AVX_AVX512_MASK); | |
4537 | avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) | |
df7e5265 | 4538 | == X86_XSTATE_AVX_MASK) && !avx512_p; |
22049425 | 4539 | sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
df7e5265 | 4540 | == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; |
01f9f808 | 4541 | |
38c968cf | 4542 | if (group == vector_reggroup) |
c131fcee | 4543 | return (mmx_regnum_p |
01f9f808 MS |
4544 | || (zmm_regnum_p && avx512_p) |
4545 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) | |
4546 | || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) | |
4547 | || mxcsr_regnum_p); | |
1ba53b71 L |
4548 | |
4549 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4550 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4551 | if (group == float_reggroup) |
4552 | return fp_regnum_p; | |
1ba53b71 | 4553 | |
c131fcee L |
4554 | /* For "info reg all", don't include upper YMM registers nor XMM |
4555 | registers when AVX is supported. */ | |
4556 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4557 | ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); |
4558 | zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); | |
c131fcee | 4559 | if (group == all_reggroup |
01f9f808 MS |
4560 | && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) |
4561 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) | |
4562 | || ymmh_regnum_p | |
4563 | || ymmh_avx512_regnum_p | |
4564 | || zmmh_regnum_p)) | |
c131fcee L |
4565 | return 0; |
4566 | ||
1dbcd68c WT |
4567 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4568 | if (group == all_reggroup | |
df7e5265 | 4569 | && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4570 | return bnd_regnum_p; |
4571 | ||
4572 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4573 | if (group == all_reggroup | |
df7e5265 | 4574 | && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4575 | return 0; |
4576 | ||
4577 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4578 | if (group == all_reggroup | |
df7e5265 | 4579 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4580 | return mpx_ctrl_regnum_p; |
4581 | ||
38c968cf | 4582 | if (group == general_reggroup) |
1ba53b71 L |
4583 | return (!fp_regnum_p |
4584 | && !mmx_regnum_p | |
c131fcee L |
4585 | && !mxcsr_regnum_p |
4586 | && !xmm_regnum_p | |
01f9f808 | 4587 | && !xmm_avx512_regnum_p |
c131fcee | 4588 | && !ymm_regnum_p |
1dbcd68c | 4589 | && !ymmh_regnum_p |
01f9f808 MS |
4590 | && !ymm_avx512_regnum_p |
4591 | && !ymmh_avx512_regnum_p | |
1dbcd68c WT |
4592 | && !bndr_regnum_p |
4593 | && !bnd_regnum_p | |
01f9f808 MS |
4594 | && !mpx_ctrl_regnum_p |
4595 | && !zmm_regnum_p | |
51547df6 MS |
4596 | && !zmmh_regnum_p |
4597 | && !pkru_regnum_p); | |
acd5c798 | 4598 | |
38c968cf AC |
4599 | return default_register_reggroup_p (gdbarch, regnum, group); |
4600 | } | |
38c968cf | 4601 | \f |
acd5c798 | 4602 | |
f837910f MK |
4603 | /* Get the ARGIth function argument for the current function. */ |
4604 | ||
42c466d7 | 4605 | static CORE_ADDR |
143985b7 AF |
4606 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
4607 | struct type *type) | |
4608 | { | |
e17a4113 UW |
4609 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4610 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4611 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4612 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4613 | } |
4614 | ||
7ad10968 HZ |
4615 | #define PREFIX_REPZ 0x01 |
4616 | #define PREFIX_REPNZ 0x02 | |
4617 | #define PREFIX_LOCK 0x04 | |
4618 | #define PREFIX_DATA 0x08 | |
4619 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4620 | |
7ad10968 HZ |
4621 | /* operand size */ |
4622 | enum | |
4623 | { | |
4624 | OT_BYTE = 0, | |
4625 | OT_WORD, | |
4626 | OT_LONG, | |
cf648174 | 4627 | OT_QUAD, |
a3c4230a | 4628 | OT_DQUAD, |
7ad10968 | 4629 | }; |
473f17b0 | 4630 | |
7ad10968 HZ |
4631 | /* i386 arith/logic operations */ |
4632 | enum | |
4633 | { | |
4634 | OP_ADDL, | |
4635 | OP_ORL, | |
4636 | OP_ADCL, | |
4637 | OP_SBBL, | |
4638 | OP_ANDL, | |
4639 | OP_SUBL, | |
4640 | OP_XORL, | |
4641 | OP_CMPL, | |
4642 | }; | |
5716833c | 4643 | |
7ad10968 HZ |
4644 | struct i386_record_s |
4645 | { | |
cf648174 | 4646 | struct gdbarch *gdbarch; |
7ad10968 | 4647 | struct regcache *regcache; |
df61f520 | 4648 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4649 | CORE_ADDR addr; |
4650 | int aflag; | |
4651 | int dflag; | |
4652 | int override; | |
4653 | uint8_t modrm; | |
4654 | uint8_t mod, reg, rm; | |
4655 | int ot; | |
cf648174 HZ |
4656 | uint8_t rex_x; |
4657 | uint8_t rex_b; | |
4658 | int rip_offset; | |
4659 | int popl_esp_hack; | |
4660 | const int *regmap; | |
7ad10968 | 4661 | }; |
5716833c | 4662 | |
99c1624c PA |
4663 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4664 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4665 | |
7ad10968 HZ |
4666 | static int |
4667 | i386_record_modrm (struct i386_record_s *irp) | |
4668 | { | |
cf648174 | 4669 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4670 | |
4ffa4fc7 PA |
4671 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4672 | return -1; | |
4673 | ||
7ad10968 HZ |
4674 | irp->addr++; |
4675 | irp->mod = (irp->modrm >> 6) & 3; | |
4676 | irp->reg = (irp->modrm >> 3) & 7; | |
4677 | irp->rm = irp->modrm & 7; | |
5716833c | 4678 | |
7ad10968 HZ |
4679 | return 0; |
4680 | } | |
d2a7c97a | 4681 | |
99c1624c PA |
4682 | /* Extract the memory address that the current instruction writes to, |
4683 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4684 | |
7ad10968 | 4685 | static int |
cf648174 | 4686 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4687 | { |
cf648174 | 4688 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4689 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4690 | gdb_byte buf[4]; | |
4691 | ULONGEST offset64; | |
21d0e8a4 | 4692 | |
7ad10968 | 4693 | *addr = 0; |
1e87984a | 4694 | if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4695 | { |
1e87984a | 4696 | /* 32/64 bits */ |
7ad10968 HZ |
4697 | int havesib = 0; |
4698 | uint8_t scale = 0; | |
648d0c8b | 4699 | uint8_t byte; |
7ad10968 HZ |
4700 | uint8_t index = 0; |
4701 | uint8_t base = irp->rm; | |
896fb97d | 4702 | |
7ad10968 HZ |
4703 | if (base == 4) |
4704 | { | |
4705 | havesib = 1; | |
4ffa4fc7 PA |
4706 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4707 | return -1; | |
7ad10968 | 4708 | irp->addr++; |
648d0c8b MS |
4709 | scale = (byte >> 6) & 3; |
4710 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4711 | base = (byte & 7); | |
7ad10968 | 4712 | } |
cf648174 | 4713 | base |= irp->rex_b; |
21d0e8a4 | 4714 | |
7ad10968 HZ |
4715 | switch (irp->mod) |
4716 | { | |
4717 | case 0: | |
4718 | if ((base & 7) == 5) | |
4719 | { | |
4720 | base = 0xff; | |
4ffa4fc7 PA |
4721 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4722 | return -1; | |
7ad10968 | 4723 | irp->addr += 4; |
60a1502a | 4724 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4725 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4726 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4727 | } |
7ad10968 HZ |
4728 | break; |
4729 | case 1: | |
4ffa4fc7 PA |
4730 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4731 | return -1; | |
7ad10968 | 4732 | irp->addr++; |
60a1502a | 4733 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4734 | break; |
4735 | case 2: | |
4ffa4fc7 PA |
4736 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4737 | return -1; | |
60a1502a | 4738 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4739 | irp->addr += 4; |
4740 | break; | |
4741 | } | |
356a6b3e | 4742 | |
60a1502a | 4743 | offset64 = 0; |
7ad10968 | 4744 | if (base != 0xff) |
dda83cd7 | 4745 | { |
cf648174 HZ |
4746 | if (base == 4 && irp->popl_esp_hack) |
4747 | *addr += irp->popl_esp_hack; | |
4748 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
dda83cd7 | 4749 | &offset64); |
7ad10968 | 4750 | } |
cf648174 | 4751 | if (irp->aflag == 2) |
dda83cd7 | 4752 | { |
60a1502a | 4753 | *addr += offset64; |
dda83cd7 | 4754 | } |
cf648174 | 4755 | else |
dda83cd7 | 4756 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4757 | |
7ad10968 HZ |
4758 | if (havesib && (index != 4 || scale != 0)) |
4759 | { | |
cf648174 | 4760 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
dda83cd7 | 4761 | &offset64); |
cf648174 | 4762 | if (irp->aflag == 2) |
60a1502a | 4763 | *addr += offset64 << scale; |
cf648174 | 4764 | else |
60a1502a | 4765 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 | 4766 | } |
e85596e0 L |
4767 | |
4768 | if (!irp->aflag) | |
4769 | { | |
4770 | /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend | |
4771 | address from 32-bit to 64-bit. */ | |
4772 | *addr = (uint32_t) *addr; | |
4773 | } | |
7ad10968 HZ |
4774 | } |
4775 | else | |
4776 | { | |
4777 | /* 16 bits */ | |
4778 | switch (irp->mod) | |
4779 | { | |
4780 | case 0: | |
4781 | if (irp->rm == 6) | |
4782 | { | |
4ffa4fc7 PA |
4783 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4784 | return -1; | |
7ad10968 | 4785 | irp->addr += 2; |
60a1502a | 4786 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4787 | irp->rm = 0; |
4788 | goto no_rm; | |
4789 | } | |
7ad10968 HZ |
4790 | break; |
4791 | case 1: | |
4ffa4fc7 PA |
4792 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4793 | return -1; | |
7ad10968 | 4794 | irp->addr++; |
60a1502a | 4795 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4796 | break; |
4797 | case 2: | |
4ffa4fc7 PA |
4798 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4799 | return -1; | |
7ad10968 | 4800 | irp->addr += 2; |
60a1502a | 4801 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4802 | break; |
4803 | } | |
c4fc7f1b | 4804 | |
7ad10968 HZ |
4805 | switch (irp->rm) |
4806 | { | |
4807 | case 0: | |
cf648174 HZ |
4808 | regcache_raw_read_unsigned (irp->regcache, |
4809 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
dda83cd7 | 4810 | &offset64); |
60a1502a | 4811 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4812 | regcache_raw_read_unsigned (irp->regcache, |
4813 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
dda83cd7 | 4814 | &offset64); |
60a1502a | 4815 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4816 | break; |
4817 | case 1: | |
cf648174 HZ |
4818 | regcache_raw_read_unsigned (irp->regcache, |
4819 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
dda83cd7 | 4820 | &offset64); |
60a1502a | 4821 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4822 | regcache_raw_read_unsigned (irp->regcache, |
4823 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
dda83cd7 | 4824 | &offset64); |
60a1502a | 4825 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4826 | break; |
4827 | case 2: | |
cf648174 HZ |
4828 | regcache_raw_read_unsigned (irp->regcache, |
4829 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
dda83cd7 | 4830 | &offset64); |
60a1502a | 4831 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4832 | regcache_raw_read_unsigned (irp->regcache, |
4833 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
dda83cd7 | 4834 | &offset64); |
60a1502a | 4835 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4836 | break; |
4837 | case 3: | |
cf648174 HZ |
4838 | regcache_raw_read_unsigned (irp->regcache, |
4839 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
dda83cd7 | 4840 | &offset64); |
60a1502a | 4841 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4842 | regcache_raw_read_unsigned (irp->regcache, |
4843 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
dda83cd7 | 4844 | &offset64); |
60a1502a | 4845 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4846 | break; |
4847 | case 4: | |
cf648174 HZ |
4848 | regcache_raw_read_unsigned (irp->regcache, |
4849 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
dda83cd7 | 4850 | &offset64); |
60a1502a | 4851 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4852 | break; |
4853 | case 5: | |
cf648174 HZ |
4854 | regcache_raw_read_unsigned (irp->regcache, |
4855 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
dda83cd7 | 4856 | &offset64); |
60a1502a | 4857 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4858 | break; |
4859 | case 6: | |
cf648174 HZ |
4860 | regcache_raw_read_unsigned (irp->regcache, |
4861 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
dda83cd7 | 4862 | &offset64); |
60a1502a | 4863 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4864 | break; |
4865 | case 7: | |
cf648174 HZ |
4866 | regcache_raw_read_unsigned (irp->regcache, |
4867 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
dda83cd7 | 4868 | &offset64); |
60a1502a | 4869 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4870 | break; |
4871 | } | |
4872 | *addr &= 0xffff; | |
4873 | } | |
c4fc7f1b | 4874 | |
01fe1b41 | 4875 | no_rm: |
7ad10968 HZ |
4876 | return 0; |
4877 | } | |
c4fc7f1b | 4878 | |
99c1624c PA |
4879 | /* Record the address and contents of the memory that will be changed |
4880 | by the current instruction. Return -1 if something goes wrong, 0 | |
4881 | otherwise. */ | |
356a6b3e | 4882 | |
7ad10968 HZ |
4883 | static int |
4884 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4885 | { | |
cf648174 HZ |
4886 | struct gdbarch *gdbarch = irp->gdbarch; |
4887 | uint64_t addr; | |
356a6b3e | 4888 | |
d7877f7e | 4889 | if (irp->override >= 0) |
7ad10968 | 4890 | { |
25ea693b | 4891 | if (record_full_memory_query) |
dda83cd7 SM |
4892 | { |
4893 | if (yquery (_("\ | |
bb08c432 HZ |
4894 | Process record ignores the memory change of instruction at address %s\n\ |
4895 | because it can't get the value of the segment register.\n\ | |
4896 | Do you want to stop the program?"), | |
dda83cd7 | 4897 | paddress (gdbarch, irp->orig_addr))) |
651ce16a | 4898 | return -1; |
dda83cd7 | 4899 | } |
bb08c432 | 4900 | |
7ad10968 HZ |
4901 | return 0; |
4902 | } | |
61113f8b | 4903 | |
7ad10968 HZ |
4904 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4905 | return -1; | |
96297dab | 4906 | |
25ea693b | 4907 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4908 | return -1; |
a62cc96e | 4909 | |
7ad10968 HZ |
4910 | return 0; |
4911 | } | |
b6197528 | 4912 | |
99c1624c PA |
4913 | /* Record the effects of a push operation. Return -1 if something |
4914 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4915 | |
4916 | static int | |
4917 | i386_record_push (struct i386_record_s *irp, int size) | |
4918 | { | |
648d0c8b | 4919 | ULONGEST addr; |
cf648174 | 4920 | |
25ea693b MM |
4921 | if (record_full_arch_list_add_reg (irp->regcache, |
4922 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4923 | return -1; |
4924 | regcache_raw_read_unsigned (irp->regcache, | |
4925 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4926 | &addr); |
25ea693b | 4927 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4928 | return -1; |
4929 | ||
4930 | return 0; | |
4931 | } | |
4932 | ||
0289bdd7 MS |
4933 | |
4934 | /* Defines contents to record. */ | |
4935 | #define I386_SAVE_FPU_REGS 0xfffd | |
4936 | #define I386_SAVE_FPU_ENV 0xfffe | |
4937 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4938 | ||
99c1624c PA |
4939 | /* Record the values of the floating point registers which will be |
4940 | changed by the current instruction. Returns -1 if something is | |
4941 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4942 | |
4943 | static int i386_record_floats (struct gdbarch *gdbarch, | |
dda83cd7 SM |
4944 | struct i386_record_s *ir, |
4945 | uint32_t iregnum) | |
0289bdd7 MS |
4946 | { |
4947 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4948 | int i; | |
4949 | ||
4950 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4951 | happen. Currently we store st0-st7 registers, but we need not store all | |
4952 | registers all the time, in future we use ftag register and record only | |
4953 | those who are not marked as an empty. */ | |
4954 | ||
4955 | if (I386_SAVE_FPU_REGS == iregnum) | |
4956 | { | |
4957 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
dda83cd7 SM |
4958 | { |
4959 | if (record_full_arch_list_add_reg (ir->regcache, i)) | |
4960 | return -1; | |
4961 | } | |
0289bdd7 MS |
4962 | } |
4963 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4964 | { | |
4965 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4966 | { | |
25ea693b | 4967 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
dda83cd7 | 4968 | return -1; |
0289bdd7 MS |
4969 | } |
4970 | } | |
4971 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4972 | { | |
4973 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
dda83cd7 SM |
4974 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
4975 | return -1; | |
0289bdd7 MS |
4976 | } |
4977 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
dda83cd7 | 4978 | (iregnum <= I387_FOP_REGNUM (tdep))) |
0289bdd7 | 4979 | { |
25ea693b | 4980 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
dda83cd7 | 4981 | return -1; |
0289bdd7 MS |
4982 | } |
4983 | else | |
4984 | { | |
4985 | /* Parameter error. */ | |
4986 | return -1; | |
4987 | } | |
4988 | if(I386_SAVE_FPU_ENV != iregnum) | |
4989 | { | |
4990 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4991 | { | |
25ea693b | 4992 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
dda83cd7 | 4993 | return -1; |
0289bdd7 MS |
4994 | } |
4995 | } | |
4996 | return 0; | |
4997 | } | |
4998 | ||
99c1624c PA |
4999 | /* Parse the current instruction, and record the values of the |
5000 | registers and memory that will be changed by the current | |
5001 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 5002 | |
25ea693b MM |
5003 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
5004 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 5005 | |
a6b808b4 | 5006 | int |
7ad10968 | 5007 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 5008 | CORE_ADDR input_addr) |
7ad10968 | 5009 | { |
60a1502a | 5010 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 5011 | int prefixes = 0; |
580879fc | 5012 | int regnum = 0; |
425b824a | 5013 | uint32_t opcode; |
f4644a3f | 5014 | uint8_t opcode8; |
648d0c8b | 5015 | ULONGEST addr; |
975c21ab | 5016 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
7ad10968 | 5017 | struct i386_record_s ir; |
0289bdd7 | 5018 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
5019 | uint8_t rex_w = -1; |
5020 | uint8_t rex_r = 0; | |
7ad10968 | 5021 | |
8408d274 | 5022 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 5023 | ir.regcache = regcache; |
648d0c8b MS |
5024 | ir.addr = input_addr; |
5025 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
5026 | ir.aflag = 1; |
5027 | ir.dflag = 1; | |
cf648174 HZ |
5028 | ir.override = -1; |
5029 | ir.popl_esp_hack = 0; | |
a3c4230a | 5030 | ir.regmap = tdep->record_regmap; |
cf648174 | 5031 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
5032 | |
5033 | if (record_debug > 1) | |
5034 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
dda83cd7 | 5035 | "addr = %s\n", |
5af949e3 | 5036 | paddress (gdbarch, ir.addr)); |
7ad10968 HZ |
5037 | |
5038 | /* prefixes */ | |
5039 | while (1) | |
5040 | { | |
4ffa4fc7 PA |
5041 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5042 | return -1; | |
7ad10968 | 5043 | ir.addr++; |
425b824a | 5044 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 5045 | { |
01fe1b41 | 5046 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
5047 | prefixes |= PREFIX_REPZ; |
5048 | break; | |
01fe1b41 | 5049 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
5050 | prefixes |= PREFIX_REPNZ; |
5051 | break; | |
01fe1b41 | 5052 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
5053 | prefixes |= PREFIX_LOCK; |
5054 | break; | |
01fe1b41 | 5055 | case CS_PREFIX_OPCODE: |
cf648174 | 5056 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 5057 | break; |
01fe1b41 | 5058 | case SS_PREFIX_OPCODE: |
cf648174 | 5059 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 5060 | break; |
01fe1b41 | 5061 | case DS_PREFIX_OPCODE: |
cf648174 | 5062 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 5063 | break; |
01fe1b41 | 5064 | case ES_PREFIX_OPCODE: |
cf648174 | 5065 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 5066 | break; |
01fe1b41 | 5067 | case FS_PREFIX_OPCODE: |
cf648174 | 5068 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 5069 | break; |
01fe1b41 | 5070 | case GS_PREFIX_OPCODE: |
cf648174 | 5071 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 5072 | break; |
01fe1b41 | 5073 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
5074 | prefixes |= PREFIX_DATA; |
5075 | break; | |
01fe1b41 | 5076 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
5077 | prefixes |= PREFIX_ADDR; |
5078 | break; | |
dda83cd7 SM |
5079 | case 0x40: /* i386 inc %eax */ |
5080 | case 0x41: /* i386 inc %ecx */ | |
5081 | case 0x42: /* i386 inc %edx */ | |
5082 | case 0x43: /* i386 inc %ebx */ | |
5083 | case 0x44: /* i386 inc %esp */ | |
5084 | case 0x45: /* i386 inc %ebp */ | |
5085 | case 0x46: /* i386 inc %esi */ | |
5086 | case 0x47: /* i386 inc %edi */ | |
5087 | case 0x48: /* i386 dec %eax */ | |
5088 | case 0x49: /* i386 dec %ecx */ | |
5089 | case 0x4a: /* i386 dec %edx */ | |
5090 | case 0x4b: /* i386 dec %ebx */ | |
5091 | case 0x4c: /* i386 dec %esp */ | |
5092 | case 0x4d: /* i386 dec %ebp */ | |
5093 | case 0x4e: /* i386 dec %esi */ | |
5094 | case 0x4f: /* i386 dec %edi */ | |
5095 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
5096 | { | |
5097 | /* REX */ | |
5098 | rex_w = (opcode8 >> 3) & 1; | |
5099 | rex_r = (opcode8 & 0x4) << 1; | |
5100 | ir.rex_x = (opcode8 & 0x2) << 2; | |
5101 | ir.rex_b = (opcode8 & 0x1) << 3; | |
5102 | } | |
d691bec7 MS |
5103 | else /* 32 bit target */ |
5104 | goto out_prefixes; | |
dda83cd7 | 5105 | break; |
7ad10968 HZ |
5106 | default: |
5107 | goto out_prefixes; | |
5108 | break; | |
5109 | } | |
5110 | } | |
01fe1b41 | 5111 | out_prefixes: |
cf648174 HZ |
5112 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
5113 | { | |
5114 | ir.dflag = 2; | |
5115 | } | |
5116 | else | |
5117 | { | |
5118 | if (prefixes & PREFIX_DATA) | |
dda83cd7 | 5119 | ir.dflag ^= 1; |
cf648174 | 5120 | } |
7ad10968 HZ |
5121 | if (prefixes & PREFIX_ADDR) |
5122 | ir.aflag ^= 1; | |
cf648174 HZ |
5123 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5124 | ir.aflag = 2; | |
7ad10968 | 5125 | |
1777feb0 | 5126 | /* Now check op code. */ |
425b824a | 5127 | opcode = (uint32_t) opcode8; |
01fe1b41 | 5128 | reswitch: |
7ad10968 HZ |
5129 | switch (opcode) |
5130 | { | |
5131 | case 0x0f: | |
4ffa4fc7 PA |
5132 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5133 | return -1; | |
7ad10968 | 5134 | ir.addr++; |
a3c4230a | 5135 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
5136 | goto reswitch; |
5137 | break; | |
93924b6b | 5138 | |
a38bba38 | 5139 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
5140 | case 0x01: |
5141 | case 0x02: | |
5142 | case 0x03: | |
5143 | case 0x04: | |
5144 | case 0x05: | |
5145 | case 0x08: | |
5146 | case 0x09: | |
5147 | case 0x0a: | |
5148 | case 0x0b: | |
5149 | case 0x0c: | |
5150 | case 0x0d: | |
5151 | case 0x10: | |
5152 | case 0x11: | |
5153 | case 0x12: | |
5154 | case 0x13: | |
5155 | case 0x14: | |
5156 | case 0x15: | |
5157 | case 0x18: | |
5158 | case 0x19: | |
5159 | case 0x1a: | |
5160 | case 0x1b: | |
5161 | case 0x1c: | |
5162 | case 0x1d: | |
5163 | case 0x20: | |
5164 | case 0x21: | |
5165 | case 0x22: | |
5166 | case 0x23: | |
5167 | case 0x24: | |
5168 | case 0x25: | |
5169 | case 0x28: | |
5170 | case 0x29: | |
5171 | case 0x2a: | |
5172 | case 0x2b: | |
5173 | case 0x2c: | |
5174 | case 0x2d: | |
5175 | case 0x30: | |
5176 | case 0x31: | |
5177 | case 0x32: | |
5178 | case 0x33: | |
5179 | case 0x34: | |
5180 | case 0x35: | |
5181 | case 0x38: | |
5182 | case 0x39: | |
5183 | case 0x3a: | |
5184 | case 0x3b: | |
5185 | case 0x3c: | |
5186 | case 0x3d: | |
5187 | if (((opcode >> 3) & 7) != OP_CMPL) | |
5188 | { | |
5189 | if ((opcode & 1) == 0) | |
5190 | ir.ot = OT_BYTE; | |
5191 | else | |
5192 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 5193 | |
7ad10968 HZ |
5194 | switch ((opcode >> 1) & 3) |
5195 | { | |
a38bba38 | 5196 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
5197 | if (i386_record_modrm (&ir)) |
5198 | return -1; | |
5199 | if (ir.mod != 3) | |
5200 | { | |
5201 | if (i386_record_lea_modrm (&ir)) | |
5202 | return -1; | |
5203 | } | |
5204 | else | |
5205 | { | |
dda83cd7 | 5206 | ir.rm |= ir.rex_b; |
cf648174 | 5207 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5208 | ir.rm &= 0x3; |
25ea693b | 5209 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5210 | } |
5211 | break; | |
a38bba38 | 5212 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
5213 | if (i386_record_modrm (&ir)) |
5214 | return -1; | |
dda83cd7 | 5215 | ir.reg |= rex_r; |
cf648174 | 5216 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5217 | ir.reg &= 0x3; |
25ea693b | 5218 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5219 | break; |
a38bba38 | 5220 | case 2: /* OP A, Iv */ |
25ea693b | 5221 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5222 | break; |
5223 | } | |
5224 | } | |
25ea693b | 5225 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5226 | break; |
42fdc8df | 5227 | |
a38bba38 | 5228 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
5229 | case 0x81: |
5230 | case 0x82: | |
5231 | case 0x83: | |
5232 | if (i386_record_modrm (&ir)) | |
5233 | return -1; | |
8201327c | 5234 | |
7ad10968 HZ |
5235 | if (ir.reg != OP_CMPL) |
5236 | { | |
5237 | if ((opcode & 1) == 0) | |
5238 | ir.ot = OT_BYTE; | |
5239 | else | |
5240 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 5241 | |
7ad10968 HZ |
5242 | if (ir.mod != 3) |
5243 | { | |
dda83cd7 SM |
5244 | if (opcode == 0x83) |
5245 | ir.rip_offset = 1; | |
5246 | else | |
5247 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5248 | if (i386_record_lea_modrm (&ir)) |
5249 | return -1; | |
5250 | } | |
5251 | else | |
25ea693b | 5252 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 5253 | } |
25ea693b | 5254 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5255 | break; |
5e3397bb | 5256 | |
a38bba38 | 5257 | case 0x40: /* inc */ |
7ad10968 HZ |
5258 | case 0x41: |
5259 | case 0x42: | |
5260 | case 0x43: | |
5261 | case 0x44: | |
5262 | case 0x45: | |
5263 | case 0x46: | |
5264 | case 0x47: | |
a38bba38 MS |
5265 | |
5266 | case 0x48: /* dec */ | |
7ad10968 HZ |
5267 | case 0x49: |
5268 | case 0x4a: | |
5269 | case 0x4b: | |
5270 | case 0x4c: | |
5271 | case 0x4d: | |
5272 | case 0x4e: | |
5273 | case 0x4f: | |
a38bba38 | 5274 | |
25ea693b MM |
5275 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
5276 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 5277 | break; |
acd5c798 | 5278 | |
a38bba38 | 5279 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
5280 | case 0xf7: |
5281 | if ((opcode & 1) == 0) | |
5282 | ir.ot = OT_BYTE; | |
5283 | else | |
5284 | ir.ot = ir.dflag + OT_WORD; | |
5285 | if (i386_record_modrm (&ir)) | |
5286 | return -1; | |
acd5c798 | 5287 | |
cf648174 | 5288 | if (ir.mod != 3 && ir.reg == 0) |
dda83cd7 | 5289 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
cf648174 | 5290 | |
7ad10968 HZ |
5291 | switch (ir.reg) |
5292 | { | |
a38bba38 | 5293 | case 0: /* test */ |
25ea693b | 5294 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5295 | break; |
a38bba38 MS |
5296 | case 2: /* not */ |
5297 | case 3: /* neg */ | |
7ad10968 HZ |
5298 | if (ir.mod != 3) |
5299 | { | |
5300 | if (i386_record_lea_modrm (&ir)) | |
5301 | return -1; | |
5302 | } | |
5303 | else | |
5304 | { | |
dda83cd7 | 5305 | ir.rm |= ir.rex_b; |
cf648174 | 5306 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5307 | ir.rm &= 0x3; |
25ea693b | 5308 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5309 | } |
a38bba38 | 5310 | if (ir.reg == 3) /* neg */ |
25ea693b | 5311 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5312 | break; |
a38bba38 MS |
5313 | case 4: /* mul */ |
5314 | case 5: /* imul */ | |
5315 | case 6: /* div */ | |
5316 | case 7: /* idiv */ | |
25ea693b | 5317 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 5318 | if (ir.ot != OT_BYTE) |
25ea693b MM |
5319 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
5320 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5321 | break; |
5322 | default: | |
5323 | ir.addr -= 2; | |
5324 | opcode = opcode << 8 | ir.modrm; | |
5325 | goto no_support; | |
5326 | break; | |
5327 | } | |
5328 | break; | |
5329 | ||
a38bba38 MS |
5330 | case 0xfe: /* GRP4 */ |
5331 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
5332 | if (i386_record_modrm (&ir)) |
5333 | return -1; | |
5334 | if (ir.reg >= 2 && opcode == 0xfe) | |
5335 | { | |
5336 | ir.addr -= 2; | |
5337 | opcode = opcode << 8 | ir.modrm; | |
5338 | goto no_support; | |
5339 | } | |
7ad10968 HZ |
5340 | switch (ir.reg) |
5341 | { | |
a38bba38 MS |
5342 | case 0: /* inc */ |
5343 | case 1: /* dec */ | |
dda83cd7 | 5344 | if ((opcode & 1) == 0) |
cf648174 | 5345 | ir.ot = OT_BYTE; |
dda83cd7 | 5346 | else |
cf648174 | 5347 | ir.ot = ir.dflag + OT_WORD; |
7ad10968 HZ |
5348 | if (ir.mod != 3) |
5349 | { | |
5350 | if (i386_record_lea_modrm (&ir)) | |
5351 | return -1; | |
5352 | } | |
5353 | else | |
5354 | { | |
cf648174 HZ |
5355 | ir.rm |= ir.rex_b; |
5356 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5357 | ir.rm &= 0x3; |
25ea693b | 5358 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5359 | } |
25ea693b | 5360 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5361 | break; |
a38bba38 | 5362 | case 2: /* call */ |
dda83cd7 SM |
5363 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5364 | ir.dflag = 2; | |
cf648174 | 5365 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5366 | return -1; |
25ea693b | 5367 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5368 | break; |
a38bba38 | 5369 | case 3: /* lcall */ |
25ea693b | 5370 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 5371 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5372 | return -1; |
25ea693b | 5373 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5374 | break; |
a38bba38 MS |
5375 | case 4: /* jmp */ |
5376 | case 5: /* ljmp */ | |
25ea693b | 5377 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 5378 | break; |
a38bba38 | 5379 | case 6: /* push */ |
dda83cd7 SM |
5380 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5381 | ir.dflag = 2; | |
cf648174 HZ |
5382 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
5383 | return -1; | |
7ad10968 HZ |
5384 | break; |
5385 | default: | |
5386 | ir.addr -= 2; | |
5387 | opcode = opcode << 8 | ir.modrm; | |
5388 | goto no_support; | |
5389 | break; | |
5390 | } | |
5391 | break; | |
5392 | ||
a38bba38 | 5393 | case 0x84: /* test */ |
7ad10968 HZ |
5394 | case 0x85: |
5395 | case 0xa8: | |
5396 | case 0xa9: | |
25ea693b | 5397 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5398 | break; |
5399 | ||
a38bba38 | 5400 | case 0x98: /* CWDE/CBW */ |
25ea693b | 5401 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5402 | break; |
5403 | ||
a38bba38 | 5404 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
5405 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5406 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5407 | break; |
5408 | ||
a38bba38 | 5409 | case 0x0faf: /* imul */ |
7ad10968 HZ |
5410 | case 0x69: |
5411 | case 0x6b: | |
5412 | ir.ot = ir.dflag + OT_WORD; | |
5413 | if (i386_record_modrm (&ir)) | |
5414 | return -1; | |
cf648174 | 5415 | if (opcode == 0x69) |
dda83cd7 | 5416 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
cf648174 | 5417 | else if (opcode == 0x6b) |
dda83cd7 | 5418 | ir.rip_offset = 1; |
cf648174 HZ |
5419 | ir.reg |= rex_r; |
5420 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5421 | ir.reg &= 0x3; |
25ea693b MM |
5422 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
5423 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5424 | break; |
5425 | ||
a38bba38 | 5426 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
5427 | case 0x0fc1: |
5428 | if ((opcode & 1) == 0) | |
5429 | ir.ot = OT_BYTE; | |
5430 | else | |
5431 | ir.ot = ir.dflag + OT_WORD; | |
5432 | if (i386_record_modrm (&ir)) | |
5433 | return -1; | |
cf648174 | 5434 | ir.reg |= rex_r; |
7ad10968 HZ |
5435 | if (ir.mod == 3) |
5436 | { | |
cf648174 | 5437 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5438 | ir.reg &= 0x3; |
25ea693b | 5439 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5440 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5441 | ir.rm &= 0x3; |
25ea693b | 5442 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5443 | } |
5444 | else | |
5445 | { | |
5446 | if (i386_record_lea_modrm (&ir)) | |
5447 | return -1; | |
cf648174 | 5448 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5449 | ir.reg &= 0x3; |
25ea693b | 5450 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5451 | } |
25ea693b | 5452 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5453 | break; |
5454 | ||
a38bba38 | 5455 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
5456 | case 0x0fb1: |
5457 | if ((opcode & 1) == 0) | |
5458 | ir.ot = OT_BYTE; | |
5459 | else | |
5460 | ir.ot = ir.dflag + OT_WORD; | |
5461 | if (i386_record_modrm (&ir)) | |
5462 | return -1; | |
5463 | if (ir.mod == 3) | |
5464 | { | |
dda83cd7 | 5465 | ir.reg |= rex_r; |
25ea693b | 5466 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 5467 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5468 | ir.reg &= 0x3; |
25ea693b | 5469 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5470 | } |
5471 | else | |
5472 | { | |
25ea693b | 5473 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5474 | if (i386_record_lea_modrm (&ir)) |
5475 | return -1; | |
5476 | } | |
25ea693b | 5477 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5478 | break; |
5479 | ||
20b477a7 | 5480 | case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */ |
7ad10968 HZ |
5481 | if (i386_record_modrm (&ir)) |
5482 | return -1; | |
5483 | if (ir.mod == 3) | |
5484 | { | |
20b477a7 LM |
5485 | /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as |
5486 | an extended opcode. rdrand has bits 110 (/6) and rdseed | |
5487 | has bits 111 (/7). */ | |
5488 | if (ir.reg == 6 || ir.reg == 7) | |
5489 | { | |
5490 | /* The storage register is described by the 3 R/M bits, but the | |
5491 | REX.B prefix may be used to give access to registers | |
5492 | R8~R15. In this case ir.rex_b + R/M will give us the register | |
5493 | in the range R8~R15. | |
5494 | ||
5495 | REX.W may also be used to access 64-bit registers, but we | |
5496 | already record entire registers and not just partial bits | |
5497 | of them. */ | |
5498 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm); | |
5499 | /* These instructions also set conditional bits. */ | |
5500 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5501 | break; | |
5502 | } | |
5503 | else | |
5504 | { | |
5505 | /* We don't handle this particular instruction yet. */ | |
5506 | ir.addr -= 2; | |
5507 | opcode = opcode << 8 | ir.modrm; | |
5508 | goto no_support; | |
5509 | } | |
7ad10968 | 5510 | } |
25ea693b MM |
5511 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5512 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5513 | if (i386_record_lea_modrm (&ir)) |
5514 | return -1; | |
25ea693b | 5515 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5516 | break; |
5517 | ||
a38bba38 | 5518 | case 0x50: /* push */ |
7ad10968 HZ |
5519 | case 0x51: |
5520 | case 0x52: | |
5521 | case 0x53: | |
5522 | case 0x54: | |
5523 | case 0x55: | |
5524 | case 0x56: | |
5525 | case 0x57: | |
5526 | case 0x68: | |
5527 | case 0x6a: | |
cf648174 | 5528 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 5529 | ir.dflag = 2; |
cf648174 HZ |
5530 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
5531 | return -1; | |
5532 | break; | |
5533 | ||
a38bba38 MS |
5534 | case 0x06: /* push es */ |
5535 | case 0x0e: /* push cs */ | |
5536 | case 0x16: /* push ss */ | |
5537 | case 0x1e: /* push ds */ | |
cf648174 | 5538 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5539 | { |
cf648174 HZ |
5540 | ir.addr -= 1; |
5541 | goto no_support; | |
5542 | } | |
5543 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5544 | return -1; | |
5545 | break; | |
5546 | ||
a38bba38 MS |
5547 | case 0x0fa0: /* push fs */ |
5548 | case 0x0fa8: /* push gs */ | |
cf648174 | 5549 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5550 | { |
cf648174 HZ |
5551 | ir.addr -= 2; |
5552 | goto no_support; | |
5553 | } | |
5554 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5555 | return -1; |
cf648174 HZ |
5556 | break; |
5557 | ||
a38bba38 | 5558 | case 0x60: /* pusha */ |
cf648174 | 5559 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5560 | { |
cf648174 HZ |
5561 | ir.addr -= 1; |
5562 | goto no_support; | |
5563 | } | |
5564 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5565 | return -1; |
5566 | break; | |
5567 | ||
a38bba38 | 5568 | case 0x58: /* pop */ |
7ad10968 HZ |
5569 | case 0x59: |
5570 | case 0x5a: | |
5571 | case 0x5b: | |
5572 | case 0x5c: | |
5573 | case 0x5d: | |
5574 | case 0x5e: | |
5575 | case 0x5f: | |
25ea693b MM |
5576 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5577 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5578 | break; |
5579 | ||
a38bba38 | 5580 | case 0x61: /* popa */ |
cf648174 | 5581 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5582 | { |
cf648174 HZ |
5583 | ir.addr -= 1; |
5584 | goto no_support; | |
7ad10968 | 5585 | } |
425b824a MS |
5586 | for (regnum = X86_RECORD_REAX_REGNUM; |
5587 | regnum <= X86_RECORD_REDI_REGNUM; | |
5588 | regnum++) | |
25ea693b | 5589 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5590 | break; |
5591 | ||
a38bba38 | 5592 | case 0x8f: /* pop */ |
cf648174 HZ |
5593 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5594 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5595 | else | |
dda83cd7 | 5596 | ir.ot = ir.dflag + OT_WORD; |
7ad10968 HZ |
5597 | if (i386_record_modrm (&ir)) |
5598 | return -1; | |
5599 | if (ir.mod == 3) | |
25ea693b | 5600 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5601 | else |
5602 | { | |
dda83cd7 | 5603 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5604 | if (i386_record_lea_modrm (&ir)) |
5605 | return -1; | |
5606 | } | |
25ea693b | 5607 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5608 | break; |
5609 | ||
a38bba38 | 5610 | case 0xc8: /* enter */ |
25ea693b | 5611 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 | 5612 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 5613 | ir.dflag = 2; |
cf648174 | 5614 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 HZ |
5615 | return -1; |
5616 | break; | |
5617 | ||
a38bba38 | 5618 | case 0xc9: /* leave */ |
25ea693b MM |
5619 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5620 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5621 | break; |
5622 | ||
a38bba38 | 5623 | case 0x07: /* pop es */ |
cf648174 | 5624 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5625 | { |
cf648174 HZ |
5626 | ir.addr -= 1; |
5627 | goto no_support; | |
5628 | } | |
25ea693b MM |
5629 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5630 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5631 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5632 | break; |
5633 | ||
a38bba38 | 5634 | case 0x17: /* pop ss */ |
cf648174 | 5635 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5636 | { |
cf648174 HZ |
5637 | ir.addr -= 1; |
5638 | goto no_support; | |
5639 | } | |
25ea693b MM |
5640 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5641 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5642 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5643 | break; |
5644 | ||
a38bba38 | 5645 | case 0x1f: /* pop ds */ |
cf648174 | 5646 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5647 | { |
cf648174 HZ |
5648 | ir.addr -= 1; |
5649 | goto no_support; | |
5650 | } | |
25ea693b MM |
5651 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5652 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5653 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5654 | break; |
5655 | ||
a38bba38 | 5656 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5657 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5658 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5659 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5660 | break; |
5661 | ||
a38bba38 | 5662 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5663 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5664 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5665 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5666 | break; |
5667 | ||
a38bba38 | 5668 | case 0x88: /* mov */ |
7ad10968 HZ |
5669 | case 0x89: |
5670 | case 0xc6: | |
5671 | case 0xc7: | |
5672 | if ((opcode & 1) == 0) | |
5673 | ir.ot = OT_BYTE; | |
5674 | else | |
5675 | ir.ot = ir.dflag + OT_WORD; | |
5676 | ||
5677 | if (i386_record_modrm (&ir)) | |
5678 | return -1; | |
5679 | ||
5680 | if (ir.mod != 3) | |
5681 | { | |
dda83cd7 | 5682 | if (opcode == 0xc6 || opcode == 0xc7) |
cf648174 | 5683 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
7ad10968 HZ |
5684 | if (i386_record_lea_modrm (&ir)) |
5685 | return -1; | |
5686 | } | |
5687 | else | |
5688 | { | |
dda83cd7 | 5689 | if (opcode == 0xc6 || opcode == 0xc7) |
cf648174 HZ |
5690 | ir.rm |= ir.rex_b; |
5691 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5692 | ir.rm &= 0x3; |
25ea693b | 5693 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5694 | } |
7ad10968 | 5695 | break; |
cf648174 | 5696 | |
a38bba38 | 5697 | case 0x8a: /* mov */ |
7ad10968 HZ |
5698 | case 0x8b: |
5699 | if ((opcode & 1) == 0) | |
5700 | ir.ot = OT_BYTE; | |
5701 | else | |
5702 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5703 | if (i386_record_modrm (&ir)) |
5704 | return -1; | |
cf648174 HZ |
5705 | ir.reg |= rex_r; |
5706 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5707 | ir.reg &= 0x3; |
25ea693b | 5708 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5709 | break; |
7ad10968 | 5710 | |
a38bba38 | 5711 | case 0x8c: /* mov seg */ |
cf648174 | 5712 | if (i386_record_modrm (&ir)) |
7ad10968 | 5713 | return -1; |
cf648174 HZ |
5714 | if (ir.reg > 5) |
5715 | { | |
5716 | ir.addr -= 2; | |
5717 | opcode = opcode << 8 | ir.modrm; | |
5718 | goto no_support; | |
5719 | } | |
5720 | ||
5721 | if (ir.mod == 3) | |
25ea693b | 5722 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5723 | else |
5724 | { | |
5725 | ir.ot = OT_WORD; | |
5726 | if (i386_record_lea_modrm (&ir)) | |
5727 | return -1; | |
5728 | } | |
7ad10968 HZ |
5729 | break; |
5730 | ||
a38bba38 | 5731 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5732 | if (i386_record_modrm (&ir)) |
5733 | return -1; | |
7ad10968 HZ |
5734 | switch (ir.reg) |
5735 | { | |
5736 | case 0: | |
425b824a | 5737 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5738 | break; |
5739 | case 2: | |
425b824a | 5740 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5741 | break; |
5742 | case 3: | |
425b824a | 5743 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5744 | break; |
5745 | case 4: | |
425b824a | 5746 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5747 | break; |
5748 | case 5: | |
425b824a | 5749 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5750 | break; |
5751 | default: | |
5752 | ir.addr -= 2; | |
5753 | opcode = opcode << 8 | ir.modrm; | |
5754 | goto no_support; | |
5755 | break; | |
5756 | } | |
25ea693b MM |
5757 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5758 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5759 | break; |
5760 | ||
a38bba38 MS |
5761 | case 0x0fb6: /* movzbS */ |
5762 | case 0x0fb7: /* movzwS */ | |
5763 | case 0x0fbe: /* movsbS */ | |
5764 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5765 | if (i386_record_modrm (&ir)) |
5766 | return -1; | |
25ea693b | 5767 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5768 | break; |
5769 | ||
a38bba38 | 5770 | case 0x8d: /* lea */ |
7ad10968 HZ |
5771 | if (i386_record_modrm (&ir)) |
5772 | return -1; | |
5773 | if (ir.mod == 3) | |
5774 | { | |
5775 | ir.addr -= 2; | |
5776 | opcode = opcode << 8 | ir.modrm; | |
5777 | goto no_support; | |
5778 | } | |
7ad10968 | 5779 | ir.ot = ir.dflag; |
cf648174 HZ |
5780 | ir.reg |= rex_r; |
5781 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5782 | ir.reg &= 0x3; |
25ea693b | 5783 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5784 | break; |
5785 | ||
a38bba38 | 5786 | case 0xa0: /* mov EAX */ |
7ad10968 | 5787 | case 0xa1: |
a38bba38 MS |
5788 | |
5789 | case 0xd7: /* xlat */ | |
25ea693b | 5790 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5791 | break; |
5792 | ||
a38bba38 | 5793 | case 0xa2: /* mov EAX */ |
7ad10968 | 5794 | case 0xa3: |
d7877f7e | 5795 | if (ir.override >= 0) |
dda83cd7 SM |
5796 | { |
5797 | if (record_full_memory_query) | |
5798 | { | |
5799 | if (yquery (_("\ | |
bb08c432 HZ |
5800 | Process record ignores the memory change of instruction at address %s\n\ |
5801 | because it can't get the value of the segment register.\n\ | |
5802 | Do you want to stop the program?"), | |
dda83cd7 SM |
5803 | paddress (gdbarch, ir.orig_addr))) |
5804 | return -1; | |
5805 | } | |
cf648174 HZ |
5806 | } |
5807 | else | |
5808 | { | |
dda83cd7 | 5809 | if ((opcode & 1) == 0) |
cf648174 HZ |
5810 | ir.ot = OT_BYTE; |
5811 | else | |
5812 | ir.ot = ir.dflag + OT_WORD; | |
5813 | if (ir.aflag == 2) | |
5814 | { | |
dda83cd7 | 5815 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
4ffa4fc7 | 5816 | return -1; |
cf648174 | 5817 | ir.addr += 8; |
60a1502a | 5818 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 | 5819 | } |
dda83cd7 | 5820 | else if (ir.aflag) |
cf648174 | 5821 | { |
dda83cd7 | 5822 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
4ffa4fc7 | 5823 | return -1; |
cf648174 | 5824 | ir.addr += 4; |
dda83cd7 | 5825 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 | 5826 | } |
dda83cd7 | 5827 | else |
cf648174 | 5828 | { |
dda83cd7 | 5829 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
4ffa4fc7 | 5830 | return -1; |
cf648174 | 5831 | ir.addr += 2; |
dda83cd7 | 5832 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5833 | } |
25ea693b | 5834 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 | 5835 | return -1; |
dda83cd7 | 5836 | } |
7ad10968 HZ |
5837 | break; |
5838 | ||
a38bba38 | 5839 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5840 | case 0xb1: |
5841 | case 0xb2: | |
5842 | case 0xb3: | |
5843 | case 0xb4: | |
5844 | case 0xb5: | |
5845 | case 0xb6: | |
5846 | case 0xb7: | |
25ea693b MM |
5847 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5848 | ? ((opcode & 0x7) | ir.rex_b) | |
5849 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5850 | break; |
5851 | ||
a38bba38 | 5852 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5853 | case 0xb9: |
5854 | case 0xba: | |
5855 | case 0xbb: | |
5856 | case 0xbc: | |
5857 | case 0xbd: | |
5858 | case 0xbe: | |
5859 | case 0xbf: | |
25ea693b | 5860 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5861 | break; |
5862 | ||
a38bba38 | 5863 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5864 | case 0x92: |
5865 | case 0x93: | |
5866 | case 0x94: | |
5867 | case 0x95: | |
5868 | case 0x96: | |
5869 | case 0x97: | |
25ea693b MM |
5870 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5871 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5872 | break; |
5873 | ||
a38bba38 | 5874 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5875 | case 0x87: |
5876 | if ((opcode & 1) == 0) | |
5877 | ir.ot = OT_BYTE; | |
5878 | else | |
5879 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5880 | if (i386_record_modrm (&ir)) |
5881 | return -1; | |
7ad10968 HZ |
5882 | if (ir.mod == 3) |
5883 | { | |
86839d38 | 5884 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5885 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5886 | ir.rm &= 0x3; | |
25ea693b | 5887 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5888 | } |
5889 | else | |
5890 | { | |
5891 | if (i386_record_lea_modrm (&ir)) | |
5892 | return -1; | |
5893 | } | |
cf648174 HZ |
5894 | ir.reg |= rex_r; |
5895 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5896 | ir.reg &= 0x3; |
25ea693b | 5897 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5898 | break; |
5899 | ||
a38bba38 MS |
5900 | case 0xc4: /* les Gv */ |
5901 | case 0xc5: /* lds Gv */ | |
cf648174 | 5902 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5903 | { |
cf648174 HZ |
5904 | ir.addr -= 1; |
5905 | goto no_support; | |
5906 | } | |
d3f323f3 | 5907 | /* FALLTHROUGH */ |
a38bba38 MS |
5908 | case 0x0fb2: /* lss Gv */ |
5909 | case 0x0fb4: /* lfs Gv */ | |
5910 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5911 | if (i386_record_modrm (&ir)) |
5912 | return -1; | |
5913 | if (ir.mod == 3) | |
5914 | { | |
5915 | if (opcode > 0xff) | |
5916 | ir.addr -= 3; | |
5917 | else | |
5918 | ir.addr -= 2; | |
5919 | opcode = opcode << 8 | ir.modrm; | |
5920 | goto no_support; | |
5921 | } | |
7ad10968 HZ |
5922 | switch (opcode) |
5923 | { | |
a38bba38 | 5924 | case 0xc4: /* les Gv */ |
425b824a | 5925 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5926 | break; |
a38bba38 | 5927 | case 0xc5: /* lds Gv */ |
425b824a | 5928 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5929 | break; |
a38bba38 | 5930 | case 0x0fb2: /* lss Gv */ |
425b824a | 5931 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5932 | break; |
a38bba38 | 5933 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5934 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5935 | break; |
a38bba38 | 5936 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5937 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5938 | break; |
5939 | } | |
25ea693b MM |
5940 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5941 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5942 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5943 | break; |
5944 | ||
a38bba38 | 5945 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5946 | case 0xc1: |
5947 | case 0xd0: | |
5948 | case 0xd1: | |
5949 | case 0xd2: | |
5950 | case 0xd3: | |
5951 | if ((opcode & 1) == 0) | |
5952 | ir.ot = OT_BYTE; | |
5953 | else | |
5954 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5955 | if (i386_record_modrm (&ir)) |
5956 | return -1; | |
7ad10968 HZ |
5957 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5958 | { | |
5959 | if (i386_record_lea_modrm (&ir)) | |
5960 | return -1; | |
5961 | } | |
5962 | else | |
5963 | { | |
cf648174 HZ |
5964 | ir.rm |= ir.rex_b; |
5965 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5966 | ir.rm &= 0x3; |
25ea693b | 5967 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5968 | } |
25ea693b | 5969 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5970 | break; |
5971 | ||
5972 | case 0x0fa4: | |
5973 | case 0x0fa5: | |
5974 | case 0x0fac: | |
5975 | case 0x0fad: | |
5976 | if (i386_record_modrm (&ir)) | |
5977 | return -1; | |
5978 | if (ir.mod == 3) | |
5979 | { | |
25ea693b | 5980 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
5981 | return -1; |
5982 | } | |
5983 | else | |
5984 | { | |
5985 | if (i386_record_lea_modrm (&ir)) | |
5986 | return -1; | |
5987 | } | |
5988 | break; | |
5989 | ||
a38bba38 | 5990 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
5991 | case 0xd9: |
5992 | case 0xda: | |
5993 | case 0xdb: | |
5994 | case 0xdc: | |
5995 | case 0xdd: | |
5996 | case 0xde: | |
5997 | case 0xdf: | |
5998 | if (i386_record_modrm (&ir)) | |
5999 | return -1; | |
6000 | ir.reg |= ((opcode & 7) << 3); | |
6001 | if (ir.mod != 3) | |
6002 | { | |
1777feb0 | 6003 | /* Memory. */ |
955db0c0 | 6004 | uint64_t addr64; |
7ad10968 | 6005 | |
955db0c0 | 6006 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
6007 | return -1; |
6008 | switch (ir.reg) | |
6009 | { | |
7ad10968 | 6010 | case 0x02: |
dda83cd7 SM |
6011 | case 0x12: |
6012 | case 0x22: | |
6013 | case 0x32: | |
0289bdd7 | 6014 | /* For fcom, ficom nothing to do. */ |
dda83cd7 | 6015 | break; |
7ad10968 | 6016 | case 0x03: |
dda83cd7 SM |
6017 | case 0x13: |
6018 | case 0x23: | |
6019 | case 0x33: | |
0289bdd7 | 6020 | /* For fcomp, ficomp pop FPU stack, store all. */ |
dda83cd7 SM |
6021 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6022 | return -1; | |
6023 | break; | |
6024 | case 0x00: | |
6025 | case 0x01: | |
7ad10968 HZ |
6026 | case 0x04: |
6027 | case 0x05: | |
6028 | case 0x06: | |
6029 | case 0x07: | |
6030 | case 0x10: | |
6031 | case 0x11: | |
7ad10968 HZ |
6032 | case 0x14: |
6033 | case 0x15: | |
6034 | case 0x16: | |
6035 | case 0x17: | |
6036 | case 0x20: | |
6037 | case 0x21: | |
7ad10968 HZ |
6038 | case 0x24: |
6039 | case 0x25: | |
6040 | case 0x26: | |
6041 | case 0x27: | |
6042 | case 0x30: | |
6043 | case 0x31: | |
7ad10968 HZ |
6044 | case 0x34: |
6045 | case 0x35: | |
6046 | case 0x36: | |
6047 | case 0x37: | |
dda83cd7 SM |
6048 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
6049 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
6050 | of code, always affects st(0) register. */ | |
6051 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6052 | return -1; | |
7ad10968 HZ |
6053 | break; |
6054 | case 0x08: | |
6055 | case 0x0a: | |
6056 | case 0x0b: | |
6057 | case 0x18: | |
6058 | case 0x19: | |
6059 | case 0x1a: | |
6060 | case 0x1b: | |
dda83cd7 | 6061 | case 0x1d: |
7ad10968 HZ |
6062 | case 0x28: |
6063 | case 0x29: | |
6064 | case 0x2a: | |
6065 | case 0x2b: | |
6066 | case 0x38: | |
6067 | case 0x39: | |
6068 | case 0x3a: | |
6069 | case 0x3b: | |
dda83cd7 SM |
6070 | case 0x3c: |
6071 | case 0x3d: | |
7ad10968 HZ |
6072 | switch (ir.reg & 7) |
6073 | { | |
6074 | case 0: | |
0289bdd7 MS |
6075 | /* Handling fld, fild. */ |
6076 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6077 | return -1; | |
7ad10968 HZ |
6078 | break; |
6079 | case 1: | |
6080 | switch (ir.reg >> 4) | |
6081 | { | |
6082 | case 0: | |
25ea693b | 6083 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
6084 | return -1; |
6085 | break; | |
6086 | case 2: | |
25ea693b | 6087 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
6088 | return -1; |
6089 | break; | |
6090 | case 3: | |
0289bdd7 | 6091 | break; |
7ad10968 | 6092 | default: |
25ea693b | 6093 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6094 | return -1; |
6095 | break; | |
6096 | } | |
6097 | break; | |
6098 | default: | |
6099 | switch (ir.reg >> 4) | |
6100 | { | |
6101 | case 0: | |
25ea693b | 6102 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
6103 | return -1; |
6104 | if (3 == (ir.reg & 7)) | |
6105 | { | |
6106 | /* For fstp m32fp. */ | |
6107 | if (i386_record_floats (gdbarch, &ir, | |
6108 | I386_SAVE_FPU_REGS)) | |
6109 | return -1; | |
6110 | } | |
6111 | break; | |
7ad10968 | 6112 | case 1: |
25ea693b | 6113 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 6114 | return -1; |
0289bdd7 MS |
6115 | if ((3 == (ir.reg & 7)) |
6116 | || (5 == (ir.reg & 7)) | |
6117 | || (7 == (ir.reg & 7))) | |
6118 | { | |
6119 | /* For fstp insn. */ | |
6120 | if (i386_record_floats (gdbarch, &ir, | |
6121 | I386_SAVE_FPU_REGS)) | |
6122 | return -1; | |
6123 | } | |
7ad10968 HZ |
6124 | break; |
6125 | case 2: | |
25ea693b | 6126 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6127 | return -1; |
0289bdd7 MS |
6128 | if (3 == (ir.reg & 7)) |
6129 | { | |
6130 | /* For fstp m64fp. */ | |
6131 | if (i386_record_floats (gdbarch, &ir, | |
6132 | I386_SAVE_FPU_REGS)) | |
6133 | return -1; | |
6134 | } | |
7ad10968 HZ |
6135 | break; |
6136 | case 3: | |
0289bdd7 MS |
6137 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
6138 | { | |
6139 | /* For fistp, fbld, fild, fbstp. */ | |
6140 | if (i386_record_floats (gdbarch, &ir, | |
6141 | I386_SAVE_FPU_REGS)) | |
6142 | return -1; | |
6143 | } | |
6144 | /* Fall through */ | |
7ad10968 | 6145 | default: |
25ea693b | 6146 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6147 | return -1; |
6148 | break; | |
6149 | } | |
6150 | break; | |
6151 | } | |
6152 | break; | |
6153 | case 0x0c: | |
dda83cd7 SM |
6154 | /* Insn fldenv. */ |
6155 | if (i386_record_floats (gdbarch, &ir, | |
6156 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6157 | return -1; | |
6158 | break; | |
7ad10968 | 6159 | case 0x0d: |
dda83cd7 SM |
6160 | /* Insn fldcw. */ |
6161 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
6162 | return -1; | |
6163 | break; | |
7ad10968 | 6164 | case 0x2c: |
dda83cd7 SM |
6165 | /* Insn frstor. */ |
6166 | if (i386_record_floats (gdbarch, &ir, | |
6167 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6168 | return -1; | |
7ad10968 HZ |
6169 | break; |
6170 | case 0x0e: | |
6171 | if (ir.dflag) | |
6172 | { | |
25ea693b | 6173 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
6174 | return -1; |
6175 | } | |
6176 | else | |
6177 | { | |
25ea693b | 6178 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
6179 | return -1; |
6180 | } | |
6181 | break; | |
6182 | case 0x0f: | |
6183 | case 0x2f: | |
25ea693b | 6184 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6185 | return -1; |
dda83cd7 SM |
6186 | /* Insn fstp, fbstp. */ |
6187 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6188 | return -1; | |
7ad10968 HZ |
6189 | break; |
6190 | case 0x1f: | |
6191 | case 0x3e: | |
25ea693b | 6192 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
6193 | return -1; |
6194 | break; | |
6195 | case 0x2e: | |
6196 | if (ir.dflag) | |
6197 | { | |
25ea693b | 6198 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 6199 | return -1; |
955db0c0 | 6200 | addr64 += 28; |
7ad10968 HZ |
6201 | } |
6202 | else | |
6203 | { | |
25ea693b | 6204 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 6205 | return -1; |
955db0c0 | 6206 | addr64 += 14; |
7ad10968 | 6207 | } |
25ea693b | 6208 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 6209 | return -1; |
0289bdd7 MS |
6210 | /* Insn fsave. */ |
6211 | if (i386_record_floats (gdbarch, &ir, | |
6212 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6213 | return -1; | |
7ad10968 HZ |
6214 | break; |
6215 | case 0x3f: | |
25ea693b | 6216 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6217 | return -1; |
0289bdd7 MS |
6218 | /* Insn fistp. */ |
6219 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6220 | return -1; | |
7ad10968 HZ |
6221 | break; |
6222 | default: | |
6223 | ir.addr -= 2; | |
6224 | opcode = opcode << 8 | ir.modrm; | |
6225 | goto no_support; | |
6226 | break; | |
6227 | } | |
6228 | } | |
0289bdd7 MS |
6229 | /* Opcode is an extension of modR/M byte. */ |
6230 | else | |
dda83cd7 | 6231 | { |
0289bdd7 MS |
6232 | switch (opcode) |
6233 | { | |
6234 | case 0xd8: | |
6235 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6236 | return -1; | |
6237 | break; | |
6238 | case 0xd9: | |
6239 | if (0x0c == (ir.modrm >> 4)) | |
6240 | { | |
6241 | if ((ir.modrm & 0x0f) <= 7) | |
6242 | { | |
6243 | if (i386_record_floats (gdbarch, &ir, | |
6244 | I386_SAVE_FPU_REGS)) | |
6245 | return -1; | |
6246 | } | |
dda83cd7 | 6247 | else |
0289bdd7 MS |
6248 | { |
6249 | if (i386_record_floats (gdbarch, &ir, | |
6250 | I387_ST0_REGNUM (tdep))) | |
6251 | return -1; | |
6252 | /* If only st(0) is changing, then we have already | |
6253 | recorded. */ | |
6254 | if ((ir.modrm & 0x0f) - 0x08) | |
6255 | { | |
6256 | if (i386_record_floats (gdbarch, &ir, | |
6257 | I387_ST0_REGNUM (tdep) + | |
6258 | ((ir.modrm & 0x0f) - 0x08))) | |
6259 | return -1; | |
6260 | } | |
6261 | } | |
6262 | } | |
dda83cd7 SM |
6263 | else |
6264 | { | |
0289bdd7 MS |
6265 | switch (ir.modrm) |
6266 | { | |
6267 | case 0xe0: | |
6268 | case 0xe1: | |
6269 | case 0xf0: | |
6270 | case 0xf5: | |
6271 | case 0xf8: | |
6272 | case 0xfa: | |
6273 | case 0xfc: | |
6274 | case 0xfe: | |
6275 | case 0xff: | |
6276 | if (i386_record_floats (gdbarch, &ir, | |
6277 | I387_ST0_REGNUM (tdep))) | |
6278 | return -1; | |
6279 | break; | |
6280 | case 0xf1: | |
6281 | case 0xf2: | |
6282 | case 0xf3: | |
6283 | case 0xf4: | |
6284 | case 0xf6: | |
6285 | case 0xf7: | |
6286 | case 0xe8: | |
6287 | case 0xe9: | |
6288 | case 0xea: | |
6289 | case 0xeb: | |
6290 | case 0xec: | |
6291 | case 0xed: | |
6292 | case 0xee: | |
6293 | case 0xf9: | |
6294 | case 0xfb: | |
6295 | if (i386_record_floats (gdbarch, &ir, | |
6296 | I386_SAVE_FPU_REGS)) | |
6297 | return -1; | |
6298 | break; | |
6299 | case 0xfd: | |
6300 | if (i386_record_floats (gdbarch, &ir, | |
6301 | I387_ST0_REGNUM (tdep))) | |
6302 | return -1; | |
6303 | if (i386_record_floats (gdbarch, &ir, | |
6304 | I387_ST0_REGNUM (tdep) + 1)) | |
6305 | return -1; | |
6306 | break; | |
6307 | } | |
6308 | } | |
dda83cd7 SM |
6309 | break; |
6310 | case 0xda: | |
6311 | if (0xe9 == ir.modrm) | |
6312 | { | |
0289bdd7 MS |
6313 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6314 | return -1; | |
dda83cd7 SM |
6315 | } |
6316 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6317 | { | |
0289bdd7 MS |
6318 | if (i386_record_floats (gdbarch, &ir, |
6319 | I387_ST0_REGNUM (tdep))) | |
6320 | return -1; | |
6321 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6322 | { | |
6323 | if (i386_record_floats (gdbarch, &ir, | |
6324 | I387_ST0_REGNUM (tdep) + | |
6325 | (ir.modrm & 0x0f))) | |
6326 | return -1; | |
6327 | } | |
6328 | else if ((ir.modrm & 0x0f) - 0x08) | |
6329 | { | |
6330 | if (i386_record_floats (gdbarch, &ir, | |
6331 | I387_ST0_REGNUM (tdep) + | |
6332 | ((ir.modrm & 0x0f) - 0x08))) | |
6333 | return -1; | |
6334 | } | |
dda83cd7 SM |
6335 | } |
6336 | break; | |
6337 | case 0xdb: | |
6338 | if (0xe3 == ir.modrm) | |
6339 | { | |
0289bdd7 MS |
6340 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) |
6341 | return -1; | |
dda83cd7 SM |
6342 | } |
6343 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6344 | { | |
0289bdd7 MS |
6345 | if (i386_record_floats (gdbarch, &ir, |
6346 | I387_ST0_REGNUM (tdep))) | |
6347 | return -1; | |
6348 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6349 | { | |
6350 | if (i386_record_floats (gdbarch, &ir, | |
6351 | I387_ST0_REGNUM (tdep) + | |
6352 | (ir.modrm & 0x0f))) | |
6353 | return -1; | |
6354 | } | |
6355 | else if ((ir.modrm & 0x0f) - 0x08) | |
6356 | { | |
6357 | if (i386_record_floats (gdbarch, &ir, | |
6358 | I387_ST0_REGNUM (tdep) + | |
6359 | ((ir.modrm & 0x0f) - 0x08))) | |
6360 | return -1; | |
6361 | } | |
dda83cd7 SM |
6362 | } |
6363 | break; | |
6364 | case 0xdc: | |
6365 | if ((0x0c == ir.modrm >> 4) | |
0289bdd7 MS |
6366 | || (0x0d == ir.modrm >> 4) |
6367 | || (0x0f == ir.modrm >> 4)) | |
dda83cd7 | 6368 | { |
0289bdd7 MS |
6369 | if ((ir.modrm & 0x0f) <= 7) |
6370 | { | |
6371 | if (i386_record_floats (gdbarch, &ir, | |
6372 | I387_ST0_REGNUM (tdep) + | |
6373 | (ir.modrm & 0x0f))) | |
6374 | return -1; | |
6375 | } | |
6376 | else | |
6377 | { | |
6378 | if (i386_record_floats (gdbarch, &ir, | |
6379 | I387_ST0_REGNUM (tdep) + | |
6380 | ((ir.modrm & 0x0f) - 0x08))) | |
6381 | return -1; | |
6382 | } | |
dda83cd7 | 6383 | } |
0289bdd7 | 6384 | break; |
dda83cd7 SM |
6385 | case 0xdd: |
6386 | if (0x0c == ir.modrm >> 4) | |
6387 | { | |
6388 | if (i386_record_floats (gdbarch, &ir, | |
6389 | I387_FTAG_REGNUM (tdep))) | |
6390 | return -1; | |
6391 | } | |
6392 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6393 | { | |
6394 | if ((ir.modrm & 0x0f) <= 7) | |
6395 | { | |
0289bdd7 MS |
6396 | if (i386_record_floats (gdbarch, &ir, |
6397 | I387_ST0_REGNUM (tdep) + | |
6398 | (ir.modrm & 0x0f))) | |
6399 | return -1; | |
dda83cd7 SM |
6400 | } |
6401 | else | |
6402 | { | |
6403 | if (i386_record_floats (gdbarch, &ir, | |
0289bdd7 | 6404 | I386_SAVE_FPU_REGS)) |
dda83cd7 SM |
6405 | return -1; |
6406 | } | |
6407 | } | |
6408 | break; | |
6409 | case 0xde: | |
6410 | if ((0x0c == ir.modrm >> 4) | |
0289bdd7 MS |
6411 | || (0x0e == ir.modrm >> 4) |
6412 | || (0x0f == ir.modrm >> 4) | |
6413 | || (0xd9 == ir.modrm)) | |
dda83cd7 | 6414 | { |
0289bdd7 MS |
6415 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6416 | return -1; | |
dda83cd7 SM |
6417 | } |
6418 | break; | |
6419 | case 0xdf: | |
6420 | if (0xe0 == ir.modrm) | |
6421 | { | |
25ea693b MM |
6422 | if (record_full_arch_list_add_reg (ir.regcache, |
6423 | I386_EAX_REGNUM)) | |
0289bdd7 | 6424 | return -1; |
dda83cd7 SM |
6425 | } |
6426 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6427 | { | |
0289bdd7 MS |
6428 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6429 | return -1; | |
dda83cd7 SM |
6430 | } |
6431 | break; | |
0289bdd7 MS |
6432 | } |
6433 | } | |
7ad10968 | 6434 | break; |
7ad10968 | 6435 | /* string ops */ |
a38bba38 | 6436 | case 0xa4: /* movsS */ |
7ad10968 | 6437 | case 0xa5: |
a38bba38 | 6438 | case 0xaa: /* stosS */ |
7ad10968 | 6439 | case 0xab: |
a38bba38 | 6440 | case 0x6c: /* insS */ |
7ad10968 | 6441 | case 0x6d: |
cf648174 | 6442 | regcache_raw_read_unsigned (ir.regcache, |
dda83cd7 SM |
6443 | ir.regmap[X86_RECORD_RECX_REGNUM], |
6444 | &addr); | |
648d0c8b | 6445 | if (addr) |
dda83cd7 SM |
6446 | { |
6447 | ULONGEST es, ds; | |
77d7dc92 | 6448 | |
dda83cd7 | 6449 | if ((opcode & 1) == 0) |
77d7dc92 | 6450 | ir.ot = OT_BYTE; |
dda83cd7 | 6451 | else |
77d7dc92 | 6452 | ir.ot = ir.dflag + OT_WORD; |
dda83cd7 SM |
6453 | regcache_raw_read_unsigned (ir.regcache, |
6454 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
6455 | &addr); | |
6456 | ||
6457 | regcache_raw_read_unsigned (ir.regcache, | |
6458 | ir.regmap[X86_RECORD_ES_REGNUM], | |
6459 | &es); | |
6460 | regcache_raw_read_unsigned (ir.regcache, | |
6461 | ir.regmap[X86_RECORD_DS_REGNUM], | |
6462 | &ds); | |
6463 | if (ir.aflag && (es != ds)) | |
6464 | { | |
6465 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
6466 | if (record_full_memory_query) | |
6467 | { | |
6468 | if (yquery (_("\ | |
bb08c432 HZ |
6469 | Process record ignores the memory change of instruction at address %s\n\ |
6470 | because it can't get the value of the segment register.\n\ | |
6471 | Do you want to stop the program?"), | |
dda83cd7 SM |
6472 | paddress (gdbarch, ir.orig_addr))) |
6473 | return -1; | |
6474 | } | |
6475 | } | |
6476 | else | |
6477 | { | |
6478 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) | |
6479 | return -1; | |
6480 | } | |
6481 | ||
6482 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
6483 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6484 | if (opcode == 0xa4 || opcode == 0xa5) | |
6485 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6486 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6487 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 6488 | } |
cf648174 | 6489 | break; |
7ad10968 | 6490 | |
a38bba38 | 6491 | case 0xa6: /* cmpsS */ |
cf648174 | 6492 | case 0xa7: |
25ea693b MM |
6493 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6494 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6495 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6496 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6497 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6498 | break; |
6499 | ||
a38bba38 | 6500 | case 0xac: /* lodsS */ |
7ad10968 | 6501 | case 0xad: |
25ea693b MM |
6502 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6503 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6504 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6505 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6506 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6507 | break; |
6508 | ||
a38bba38 | 6509 | case 0xae: /* scasS */ |
7ad10968 | 6510 | case 0xaf: |
25ea693b | 6511 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6512 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6513 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6514 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6515 | break; |
6516 | ||
a38bba38 | 6517 | case 0x6e: /* outsS */ |
cf648174 | 6518 | case 0x6f: |
25ea693b | 6519 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6520 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6521 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6522 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6523 | break; |
6524 | ||
a38bba38 | 6525 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6526 | case 0xe5: |
6527 | case 0xec: | |
6528 | case 0xed: | |
25ea693b MM |
6529 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6530 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6531 | break; |
6532 | ||
6533 | case 0xe6: | |
6534 | case 0xe7: | |
6535 | case 0xee: | |
6536 | case 0xef: | |
6537 | break; | |
6538 | ||
6539 | /* control */ | |
a38bba38 MS |
6540 | case 0xc2: /* ret im */ |
6541 | case 0xc3: /* ret */ | |
25ea693b MM |
6542 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6543 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6544 | break; |
6545 | ||
a38bba38 MS |
6546 | case 0xca: /* lret im */ |
6547 | case 0xcb: /* lret */ | |
6548 | case 0xcf: /* iret */ | |
25ea693b MM |
6549 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6550 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6551 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6552 | break; |
6553 | ||
a38bba38 | 6554 | case 0xe8: /* call im */ |
cf648174 | 6555 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 6556 | ir.dflag = 2; |
cf648174 | 6557 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
dda83cd7 | 6558 | return -1; |
7ad10968 HZ |
6559 | break; |
6560 | ||
a38bba38 | 6561 | case 0x9a: /* lcall im */ |
cf648174 | 6562 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6563 | { |
6564 | ir.addr -= 1; | |
6565 | goto no_support; | |
6566 | } | |
25ea693b | 6567 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 6568 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
dda83cd7 | 6569 | return -1; |
7ad10968 HZ |
6570 | break; |
6571 | ||
a38bba38 MS |
6572 | case 0xe9: /* jmp im */ |
6573 | case 0xea: /* ljmp im */ | |
6574 | case 0xeb: /* jmp Jb */ | |
6575 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6576 | case 0x71: |
6577 | case 0x72: | |
6578 | case 0x73: | |
6579 | case 0x74: | |
6580 | case 0x75: | |
6581 | case 0x76: | |
6582 | case 0x77: | |
6583 | case 0x78: | |
6584 | case 0x79: | |
6585 | case 0x7a: | |
6586 | case 0x7b: | |
6587 | case 0x7c: | |
6588 | case 0x7d: | |
6589 | case 0x7e: | |
6590 | case 0x7f: | |
a38bba38 | 6591 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6592 | case 0x0f81: |
6593 | case 0x0f82: | |
6594 | case 0x0f83: | |
6595 | case 0x0f84: | |
6596 | case 0x0f85: | |
6597 | case 0x0f86: | |
6598 | case 0x0f87: | |
6599 | case 0x0f88: | |
6600 | case 0x0f89: | |
6601 | case 0x0f8a: | |
6602 | case 0x0f8b: | |
6603 | case 0x0f8c: | |
6604 | case 0x0f8d: | |
6605 | case 0x0f8e: | |
6606 | case 0x0f8f: | |
6607 | break; | |
6608 | ||
a38bba38 | 6609 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6610 | case 0x0f91: |
6611 | case 0x0f92: | |
6612 | case 0x0f93: | |
6613 | case 0x0f94: | |
6614 | case 0x0f95: | |
6615 | case 0x0f96: | |
6616 | case 0x0f97: | |
6617 | case 0x0f98: | |
6618 | case 0x0f99: | |
6619 | case 0x0f9a: | |
6620 | case 0x0f9b: | |
6621 | case 0x0f9c: | |
6622 | case 0x0f9d: | |
6623 | case 0x0f9e: | |
6624 | case 0x0f9f: | |
25ea693b | 6625 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6626 | ir.ot = OT_BYTE; |
6627 | if (i386_record_modrm (&ir)) | |
6628 | return -1; | |
6629 | if (ir.mod == 3) | |
dda83cd7 | 6630 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
25ea693b | 6631 | : (ir.rm & 0x3)); |
7ad10968 HZ |
6632 | else |
6633 | { | |
6634 | if (i386_record_lea_modrm (&ir)) | |
6635 | return -1; | |
6636 | } | |
6637 | break; | |
6638 | ||
a38bba38 | 6639 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6640 | case 0x0f41: |
6641 | case 0x0f42: | |
6642 | case 0x0f43: | |
6643 | case 0x0f44: | |
6644 | case 0x0f45: | |
6645 | case 0x0f46: | |
6646 | case 0x0f47: | |
6647 | case 0x0f48: | |
6648 | case 0x0f49: | |
6649 | case 0x0f4a: | |
6650 | case 0x0f4b: | |
6651 | case 0x0f4c: | |
6652 | case 0x0f4d: | |
6653 | case 0x0f4e: | |
6654 | case 0x0f4f: | |
6655 | if (i386_record_modrm (&ir)) | |
6656 | return -1; | |
cf648174 | 6657 | ir.reg |= rex_r; |
7ad10968 HZ |
6658 | if (ir.dflag == OT_BYTE) |
6659 | ir.reg &= 0x3; | |
25ea693b | 6660 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6661 | break; |
6662 | ||
6663 | /* flags */ | |
a38bba38 | 6664 | case 0x9c: /* pushf */ |
25ea693b | 6665 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 6666 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 6667 | ir.dflag = 2; |
cf648174 | 6668 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
dda83cd7 | 6669 | return -1; |
7ad10968 HZ |
6670 | break; |
6671 | ||
a38bba38 | 6672 | case 0x9d: /* popf */ |
25ea693b MM |
6673 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6674 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6675 | break; |
6676 | ||
a38bba38 | 6677 | case 0x9e: /* sahf */ |
cf648174 | 6678 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6679 | { |
6680 | ir.addr -= 1; | |
6681 | goto no_support; | |
6682 | } | |
d3f323f3 | 6683 | /* FALLTHROUGH */ |
a38bba38 MS |
6684 | case 0xf5: /* cmc */ |
6685 | case 0xf8: /* clc */ | |
6686 | case 0xf9: /* stc */ | |
6687 | case 0xfc: /* cld */ | |
6688 | case 0xfd: /* std */ | |
25ea693b | 6689 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6690 | break; |
6691 | ||
a38bba38 | 6692 | case 0x9f: /* lahf */ |
cf648174 | 6693 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6694 | { |
6695 | ir.addr -= 1; | |
6696 | goto no_support; | |
6697 | } | |
25ea693b MM |
6698 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6699 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6700 | break; |
6701 | ||
6702 | /* bit operations */ | |
a38bba38 | 6703 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6704 | ir.ot = ir.dflag + OT_WORD; |
6705 | if (i386_record_modrm (&ir)) | |
6706 | return -1; | |
6707 | if (ir.reg < 4) | |
6708 | { | |
cf648174 | 6709 | ir.addr -= 2; |
7ad10968 HZ |
6710 | opcode = opcode << 8 | ir.modrm; |
6711 | goto no_support; | |
6712 | } | |
cf648174 | 6713 | if (ir.reg != 4) |
7ad10968 | 6714 | { |
dda83cd7 SM |
6715 | if (ir.mod == 3) |
6716 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
6717 | else |
6718 | { | |
cf648174 | 6719 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6720 | return -1; |
6721 | } | |
6722 | } | |
25ea693b | 6723 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6724 | break; |
6725 | ||
a38bba38 | 6726 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6727 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6728 | break; |
6729 | ||
a38bba38 MS |
6730 | case 0x0fab: /* bts */ |
6731 | case 0x0fb3: /* btr */ | |
6732 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6733 | ir.ot = ir.dflag + OT_WORD; |
6734 | if (i386_record_modrm (&ir)) | |
dda83cd7 | 6735 | return -1; |
cf648174 | 6736 | if (ir.mod == 3) |
dda83cd7 | 6737 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 | 6738 | else |
dda83cd7 SM |
6739 | { |
6740 | uint64_t addr64; | |
6741 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
6742 | return -1; | |
6743 | regcache_raw_read_unsigned (ir.regcache, | |
6744 | ir.regmap[ir.reg | rex_r], | |
6745 | &addr); | |
6746 | switch (ir.dflag) | |
6747 | { | |
6748 | case 0: | |
6749 | addr64 += ((int16_t) addr >> 4) << 4; | |
6750 | break; | |
6751 | case 1: | |
6752 | addr64 += ((int32_t) addr >> 5) << 5; | |
6753 | break; | |
6754 | case 2: | |
6755 | addr64 += ((int64_t) addr >> 6) << 6; | |
6756 | break; | |
6757 | } | |
6758 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) | |
6759 | return -1; | |
6760 | if (i386_record_lea_modrm (&ir)) | |
6761 | return -1; | |
6762 | } | |
25ea693b | 6763 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6764 | break; |
6765 | ||
a38bba38 MS |
6766 | case 0x0fbc: /* bsf */ |
6767 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6768 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6769 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6770 | break; |
6771 | ||
6772 | /* bcd */ | |
a38bba38 MS |
6773 | case 0x27: /* daa */ |
6774 | case 0x2f: /* das */ | |
6775 | case 0x37: /* aaa */ | |
6776 | case 0x3f: /* aas */ | |
6777 | case 0xd4: /* aam */ | |
6778 | case 0xd5: /* aad */ | |
cf648174 | 6779 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6780 | { |
6781 | ir.addr -= 1; | |
6782 | goto no_support; | |
6783 | } | |
25ea693b MM |
6784 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6785 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6786 | break; |
6787 | ||
6788 | /* misc */ | |
a38bba38 | 6789 | case 0x90: /* nop */ |
7ad10968 HZ |
6790 | if (prefixes & PREFIX_LOCK) |
6791 | { | |
6792 | ir.addr -= 1; | |
6793 | goto no_support; | |
6794 | } | |
6795 | break; | |
6796 | ||
a38bba38 | 6797 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6798 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6799 | return -1; | |
425b824a | 6800 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6801 | ir.addr++; |
6802 | goto reswitch; | |
7ad10968 HZ |
6803 | break; |
6804 | ||
7ad10968 | 6805 | /* XXX */ |
a38bba38 | 6806 | case 0xcc: /* int3 */ |
a3c4230a | 6807 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6808 | "int3.\n")); |
6809 | ir.addr -= 1; | |
6810 | goto no_support; | |
6811 | break; | |
6812 | ||
7ad10968 | 6813 | /* XXX */ |
a38bba38 | 6814 | case 0xcd: /* int */ |
7ad10968 HZ |
6815 | { |
6816 | int ret; | |
425b824a | 6817 | uint8_t interrupt; |
4ffa4fc7 PA |
6818 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6819 | return -1; | |
7ad10968 | 6820 | ir.addr++; |
425b824a | 6821 | if (interrupt != 0x80 |
a3c4230a | 6822 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6823 | { |
a3c4230a | 6824 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6825 | "instruction int 0x%02x.\n"), |
425b824a | 6826 | interrupt); |
7ad10968 HZ |
6827 | ir.addr -= 2; |
6828 | goto no_support; | |
6829 | } | |
a3c4230a | 6830 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6831 | if (ret) |
6832 | return ret; | |
6833 | } | |
6834 | break; | |
6835 | ||
7ad10968 | 6836 | /* XXX */ |
a38bba38 | 6837 | case 0xce: /* into */ |
a3c4230a | 6838 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6839 | "instruction into.\n")); |
6840 | ir.addr -= 1; | |
6841 | goto no_support; | |
6842 | break; | |
6843 | ||
a38bba38 MS |
6844 | case 0xfa: /* cli */ |
6845 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6846 | break; |
6847 | ||
a38bba38 | 6848 | case 0x62: /* bound */ |
a3c4230a | 6849 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6850 | "instruction bound.\n")); |
6851 | ir.addr -= 1; | |
6852 | goto no_support; | |
6853 | break; | |
6854 | ||
a38bba38 | 6855 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6856 | case 0x0fc9: |
6857 | case 0x0fca: | |
6858 | case 0x0fcb: | |
6859 | case 0x0fcc: | |
6860 | case 0x0fcd: | |
6861 | case 0x0fce: | |
6862 | case 0x0fcf: | |
25ea693b | 6863 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6864 | break; |
6865 | ||
a38bba38 | 6866 | case 0xd6: /* salc */ |
cf648174 | 6867 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6868 | { |
6869 | ir.addr -= 1; | |
6870 | goto no_support; | |
6871 | } | |
25ea693b MM |
6872 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6873 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6874 | break; |
6875 | ||
a38bba38 MS |
6876 | case 0xe0: /* loopnz */ |
6877 | case 0xe1: /* loopz */ | |
6878 | case 0xe2: /* loop */ | |
6879 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6880 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6881 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6882 | break; |
6883 | ||
a38bba38 | 6884 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6885 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6886 | "instruction wrmsr.\n")); |
6887 | ir.addr -= 2; | |
6888 | goto no_support; | |
6889 | break; | |
6890 | ||
a38bba38 | 6891 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6892 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6893 | "instruction rdmsr.\n")); |
6894 | ir.addr -= 2; | |
6895 | goto no_support; | |
6896 | break; | |
6897 | ||
a38bba38 | 6898 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6899 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6900 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6901 | break; |
6902 | ||
a38bba38 | 6903 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6904 | { |
6905 | int ret; | |
dda83cd7 SM |
6906 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6907 | { | |
6908 | ir.addr -= 2; | |
6909 | goto no_support; | |
6910 | } | |
a3c4230a | 6911 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6912 | { |
a3c4230a | 6913 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6914 | "instruction sysenter.\n")); |
6915 | ir.addr -= 2; | |
6916 | goto no_support; | |
6917 | } | |
a3c4230a | 6918 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6919 | if (ret) |
6920 | return ret; | |
6921 | } | |
6922 | break; | |
6923 | ||
a38bba38 | 6924 | case 0x0f35: /* sysexit */ |
a3c4230a | 6925 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6926 | "instruction sysexit.\n")); |
6927 | ir.addr -= 2; | |
6928 | goto no_support; | |
6929 | break; | |
6930 | ||
a38bba38 | 6931 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6932 | { |
6933 | int ret; | |
a3c4230a | 6934 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6935 | { |
a3c4230a | 6936 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6937 | "instruction syscall.\n")); |
6938 | ir.addr -= 2; | |
6939 | goto no_support; | |
6940 | } | |
a3c4230a | 6941 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6942 | if (ret) |
6943 | return ret; | |
6944 | } | |
6945 | break; | |
6946 | ||
a38bba38 | 6947 | case 0x0f07: /* sysret */ |
a3c4230a | 6948 | printf_unfiltered (_("Process record does not support " |
dda83cd7 | 6949 | "instruction sysret.\n")); |
cf648174 HZ |
6950 | ir.addr -= 2; |
6951 | goto no_support; | |
6952 | break; | |
6953 | ||
a38bba38 | 6954 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
6955 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6956 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6957 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6958 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6959 | break; |
6960 | ||
a38bba38 | 6961 | case 0xf4: /* hlt */ |
a3c4230a | 6962 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6963 | "instruction hlt.\n")); |
6964 | ir.addr -= 1; | |
6965 | goto no_support; | |
6966 | break; | |
6967 | ||
6968 | case 0x0f00: | |
6969 | if (i386_record_modrm (&ir)) | |
6970 | return -1; | |
6971 | switch (ir.reg) | |
6972 | { | |
a38bba38 MS |
6973 | case 0: /* sldt */ |
6974 | case 1: /* str */ | |
7ad10968 | 6975 | if (ir.mod == 3) |
dda83cd7 | 6976 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6977 | else |
6978 | { | |
6979 | ir.ot = OT_WORD; | |
6980 | if (i386_record_lea_modrm (&ir)) | |
6981 | return -1; | |
6982 | } | |
6983 | break; | |
a38bba38 MS |
6984 | case 2: /* lldt */ |
6985 | case 3: /* ltr */ | |
7ad10968 | 6986 | break; |
a38bba38 MS |
6987 | case 4: /* verr */ |
6988 | case 5: /* verw */ | |
dda83cd7 | 6989 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6990 | break; |
6991 | default: | |
6992 | ir.addr -= 3; | |
6993 | opcode = opcode << 8 | ir.modrm; | |
6994 | goto no_support; | |
6995 | break; | |
6996 | } | |
6997 | break; | |
6998 | ||
6999 | case 0x0f01: | |
7000 | if (i386_record_modrm (&ir)) | |
7001 | return -1; | |
7002 | switch (ir.reg) | |
7003 | { | |
a38bba38 | 7004 | case 0: /* sgdt */ |
7ad10968 | 7005 | { |
955db0c0 | 7006 | uint64_t addr64; |
7ad10968 HZ |
7007 | |
7008 | if (ir.mod == 3) | |
7009 | { | |
7010 | ir.addr -= 3; | |
7011 | opcode = opcode << 8 | ir.modrm; | |
7012 | goto no_support; | |
7013 | } | |
d7877f7e | 7014 | if (ir.override >= 0) |
7ad10968 | 7015 | { |
dda83cd7 SM |
7016 | if (record_full_memory_query) |
7017 | { | |
7018 | if (yquery (_("\ | |
bb08c432 HZ |
7019 | Process record ignores the memory change of instruction at address %s\n\ |
7020 | because it can't get the value of the segment register.\n\ | |
7021 | Do you want to stop the program?"), | |
dda83cd7 | 7022 | paddress (gdbarch, ir.orig_addr))) |
651ce16a | 7023 | return -1; |
dda83cd7 | 7024 | } |
7ad10968 HZ |
7025 | } |
7026 | else | |
7027 | { | |
955db0c0 | 7028 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7029 | return -1; |
25ea693b | 7030 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7031 | return -1; |
955db0c0 | 7032 | addr64 += 2; |
dda83cd7 SM |
7033 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7034 | { | |
7035 | if (record_full_arch_list_add_mem (addr64, 8)) | |
cf648174 | 7036 | return -1; |
dda83cd7 SM |
7037 | } |
7038 | else | |
7039 | { | |
7040 | if (record_full_arch_list_add_mem (addr64, 4)) | |
cf648174 | 7041 | return -1; |
dda83cd7 | 7042 | } |
7ad10968 HZ |
7043 | } |
7044 | } | |
7045 | break; | |
7046 | case 1: | |
7047 | if (ir.mod == 3) | |
7048 | { | |
7049 | switch (ir.rm) | |
7050 | { | |
a38bba38 | 7051 | case 0: /* monitor */ |
7ad10968 | 7052 | break; |
a38bba38 | 7053 | case 1: /* mwait */ |
25ea693b | 7054 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7055 | break; |
7056 | default: | |
7057 | ir.addr -= 3; | |
7058 | opcode = opcode << 8 | ir.modrm; | |
7059 | goto no_support; | |
7060 | break; | |
7061 | } | |
7062 | } | |
7063 | else | |
7064 | { | |
7065 | /* sidt */ | |
d7877f7e | 7066 | if (ir.override >= 0) |
7ad10968 | 7067 | { |
dda83cd7 SM |
7068 | if (record_full_memory_query) |
7069 | { | |
7070 | if (yquery (_("\ | |
bb08c432 HZ |
7071 | Process record ignores the memory change of instruction at address %s\n\ |
7072 | because it can't get the value of the segment register.\n\ | |
7073 | Do you want to stop the program?"), | |
dda83cd7 SM |
7074 | paddress (gdbarch, ir.orig_addr))) |
7075 | return -1; | |
7076 | } | |
7ad10968 HZ |
7077 | } |
7078 | else | |
7079 | { | |
955db0c0 | 7080 | uint64_t addr64; |
7ad10968 | 7081 | |
955db0c0 | 7082 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7083 | return -1; |
25ea693b | 7084 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7085 | return -1; |
955db0c0 | 7086 | addr64 += 2; |
dda83cd7 SM |
7087 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7088 | { | |
7089 | if (record_full_arch_list_add_mem (addr64, 8)) | |
7090 | return -1; | |
7091 | } | |
7092 | else | |
7093 | { | |
7094 | if (record_full_arch_list_add_mem (addr64, 4)) | |
7095 | return -1; | |
7096 | } | |
7ad10968 HZ |
7097 | } |
7098 | } | |
7099 | break; | |
a38bba38 | 7100 | case 2: /* lgdt */ |
3800e645 MS |
7101 | if (ir.mod == 3) |
7102 | { | |
7103 | /* xgetbv */ | |
7104 | if (ir.rm == 0) | |
7105 | { | |
25ea693b MM |
7106 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7107 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
7108 | break; |
7109 | } | |
7110 | /* xsetbv */ | |
7111 | else if (ir.rm == 1) | |
7112 | break; | |
7113 | } | |
da0e1563 | 7114 | /* Fall through. */ |
a38bba38 | 7115 | case 3: /* lidt */ |
7ad10968 HZ |
7116 | if (ir.mod == 3) |
7117 | { | |
7118 | ir.addr -= 3; | |
7119 | opcode = opcode << 8 | ir.modrm; | |
7120 | goto no_support; | |
7121 | } | |
7122 | break; | |
a38bba38 | 7123 | case 4: /* smsw */ |
7ad10968 HZ |
7124 | if (ir.mod == 3) |
7125 | { | |
25ea693b | 7126 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
7127 | return -1; |
7128 | } | |
7129 | else | |
7130 | { | |
7131 | ir.ot = OT_WORD; | |
7132 | if (i386_record_lea_modrm (&ir)) | |
7133 | return -1; | |
7134 | } | |
25ea693b | 7135 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7136 | break; |
a38bba38 | 7137 | case 6: /* lmsw */ |
25ea693b | 7138 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 7139 | break; |
a38bba38 | 7140 | case 7: /* invlpg */ |
cf648174 HZ |
7141 | if (ir.mod == 3) |
7142 | { | |
7143 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
dda83cd7 | 7144 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 | 7145 | else |
dda83cd7 SM |
7146 | { |
7147 | ir.addr -= 3; | |
7148 | opcode = opcode << 8 | ir.modrm; | |
7149 | goto no_support; | |
7150 | } | |
cf648174 HZ |
7151 | } |
7152 | else | |
25ea693b | 7153 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
7154 | break; |
7155 | default: | |
7156 | ir.addr -= 3; | |
7157 | opcode = opcode << 8 | ir.modrm; | |
7158 | goto no_support; | |
7ad10968 HZ |
7159 | break; |
7160 | } | |
7161 | break; | |
7162 | ||
a38bba38 MS |
7163 | case 0x0f08: /* invd */ |
7164 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
7165 | break; |
7166 | ||
a38bba38 | 7167 | case 0x63: /* arpl */ |
7ad10968 HZ |
7168 | if (i386_record_modrm (&ir)) |
7169 | return -1; | |
cf648174 | 7170 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
7171 | { |
7172 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
25ea693b | 7173 | ? (ir.reg | rex_r) : ir.rm); |
dda83cd7 | 7174 | } |
7ad10968 | 7175 | else |
dda83cd7 SM |
7176 | { |
7177 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
7178 | if (i386_record_lea_modrm (&ir)) | |
7179 | return -1; | |
7180 | } | |
cf648174 | 7181 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 7182 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7183 | break; |
7184 | ||
a38bba38 MS |
7185 | case 0x0f02: /* lar */ |
7186 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
7187 | if (i386_record_modrm (&ir)) |
7188 | return -1; | |
25ea693b MM |
7189 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7190 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
7191 | break; |
7192 | ||
7193 | case 0x0f18: | |
cf648174 HZ |
7194 | if (i386_record_modrm (&ir)) |
7195 | return -1; | |
7196 | if (ir.mod == 3 && ir.reg == 3) | |
dda83cd7 | 7197 | { |
cf648174 HZ |
7198 | ir.addr -= 3; |
7199 | opcode = opcode << 8 | ir.modrm; | |
7200 | goto no_support; | |
7201 | } | |
7ad10968 HZ |
7202 | break; |
7203 | ||
7ad10968 HZ |
7204 | case 0x0f19: |
7205 | case 0x0f1a: | |
7206 | case 0x0f1b: | |
7207 | case 0x0f1c: | |
7208 | case 0x0f1d: | |
7209 | case 0x0f1e: | |
7210 | case 0x0f1f: | |
a38bba38 | 7211 | /* nop (multi byte) */ |
7ad10968 HZ |
7212 | break; |
7213 | ||
a38bba38 MS |
7214 | case 0x0f20: /* mov reg, crN */ |
7215 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
7216 | if (i386_record_modrm (&ir)) |
7217 | return -1; | |
7218 | if ((ir.modrm & 0xc0) != 0xc0) | |
7219 | { | |
cf648174 | 7220 | ir.addr -= 3; |
7ad10968 HZ |
7221 | opcode = opcode << 8 | ir.modrm; |
7222 | goto no_support; | |
7223 | } | |
7224 | switch (ir.reg) | |
7225 | { | |
7226 | case 0: | |
7227 | case 2: | |
7228 | case 3: | |
7229 | case 4: | |
7230 | case 8: | |
7231 | if (opcode & 2) | |
25ea693b | 7232 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7233 | else |
dda83cd7 | 7234 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7235 | break; |
7236 | default: | |
cf648174 | 7237 | ir.addr -= 3; |
7ad10968 HZ |
7238 | opcode = opcode << 8 | ir.modrm; |
7239 | goto no_support; | |
7240 | break; | |
7241 | } | |
7242 | break; | |
7243 | ||
a38bba38 MS |
7244 | case 0x0f21: /* mov reg, drN */ |
7245 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
7246 | if (i386_record_modrm (&ir)) |
7247 | return -1; | |
7248 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
7249 | || ir.reg == 5 || ir.reg >= 8) | |
7250 | { | |
cf648174 | 7251 | ir.addr -= 3; |
7ad10968 HZ |
7252 | opcode = opcode << 8 | ir.modrm; |
7253 | goto no_support; | |
7254 | } | |
7255 | if (opcode & 2) | |
dda83cd7 | 7256 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7257 | else |
25ea693b | 7258 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7259 | break; |
7260 | ||
a38bba38 | 7261 | case 0x0f06: /* clts */ |
25ea693b | 7262 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7263 | break; |
7264 | ||
a3c4230a HZ |
7265 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
7266 | ||
7267 | case 0x0f0d: /* 3DNow! prefetch */ | |
7268 | break; | |
7269 | ||
7270 | case 0x0f0e: /* 3DNow! femms */ | |
7271 | case 0x0f77: /* emms */ | |
7272 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
dda83cd7 | 7273 | goto no_support; |
25ea693b | 7274 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
7275 | break; |
7276 | ||
7277 | case 0x0f0f: /* 3DNow! data */ | |
7278 | if (i386_record_modrm (&ir)) | |
7279 | return -1; | |
4ffa4fc7 PA |
7280 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7281 | return -1; | |
a3c4230a HZ |
7282 | ir.addr++; |
7283 | switch (opcode8) | |
dda83cd7 SM |
7284 | { |
7285 | case 0x0c: /* 3DNow! pi2fw */ | |
7286 | case 0x0d: /* 3DNow! pi2fd */ | |
7287 | case 0x1c: /* 3DNow! pf2iw */ | |
7288 | case 0x1d: /* 3DNow! pf2id */ | |
7289 | case 0x8a: /* 3DNow! pfnacc */ | |
7290 | case 0x8e: /* 3DNow! pfpnacc */ | |
7291 | case 0x90: /* 3DNow! pfcmpge */ | |
7292 | case 0x94: /* 3DNow! pfmin */ | |
7293 | case 0x96: /* 3DNow! pfrcp */ | |
7294 | case 0x97: /* 3DNow! pfrsqrt */ | |
7295 | case 0x9a: /* 3DNow! pfsub */ | |
7296 | case 0x9e: /* 3DNow! pfadd */ | |
7297 | case 0xa0: /* 3DNow! pfcmpgt */ | |
7298 | case 0xa4: /* 3DNow! pfmax */ | |
7299 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
7300 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
7301 | case 0xaa: /* 3DNow! pfsubr */ | |
7302 | case 0xae: /* 3DNow! pfacc */ | |
7303 | case 0xb0: /* 3DNow! pfcmpeq */ | |
7304 | case 0xb4: /* 3DNow! pfmul */ | |
7305 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
7306 | case 0xb7: /* 3DNow! pmulhrw */ | |
7307 | case 0xbb: /* 3DNow! pswapd */ | |
7308 | case 0xbf: /* 3DNow! pavgusb */ | |
7309 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7310 | goto no_support_3dnow_data; | |
7311 | record_full_arch_list_add_reg (ir.regcache, ir.reg); | |
7312 | break; | |
7313 | ||
7314 | default: | |
a3c4230a | 7315 | no_support_3dnow_data: |
dda83cd7 SM |
7316 | opcode = (opcode << 8) | opcode8; |
7317 | goto no_support; | |
7318 | break; | |
7319 | } | |
a3c4230a HZ |
7320 | break; |
7321 | ||
7322 | case 0x0faa: /* rsm */ | |
25ea693b MM |
7323 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7324 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7325 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7326 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7327 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7328 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
7329 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7330 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7331 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
7332 | break; |
7333 | ||
7334 | case 0x0fae: | |
7335 | if (i386_record_modrm (&ir)) | |
7336 | return -1; | |
7337 | switch(ir.reg) | |
dda83cd7 SM |
7338 | { |
7339 | case 0: /* fxsave */ | |
7340 | { | |
7341 | uint64_t tmpu64; | |
a3c4230a | 7342 | |
dda83cd7 | 7343 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7344 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7345 | return -1; | |
dda83cd7 SM |
7346 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
7347 | return -1; | |
7348 | } | |
7349 | break; | |
a3c4230a | 7350 | |
dda83cd7 SM |
7351 | case 1: /* fxrstor */ |
7352 | { | |
7353 | int i; | |
a3c4230a | 7354 | |
dda83cd7 | 7355 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a | 7356 | |
dda83cd7 SM |
7357 | for (i = I387_MM0_REGNUM (tdep); |
7358 | i386_mmx_regnum_p (gdbarch, i); i++) | |
7359 | record_full_arch_list_add_reg (ir.regcache, i); | |
a3c4230a | 7360 | |
dda83cd7 SM |
7361 | for (i = I387_XMM0_REGNUM (tdep); |
7362 | i386_xmm_regnum_p (gdbarch, i); i++) | |
7363 | record_full_arch_list_add_reg (ir.regcache, i); | |
a3c4230a | 7364 | |
dda83cd7 SM |
7365 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) |
7366 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7367 | I387_MXCSR_REGNUM(tdep)); |
a3c4230a | 7368 | |
dda83cd7 SM |
7369 | for (i = I387_ST0_REGNUM (tdep); |
7370 | i386_fp_regnum_p (gdbarch, i); i++) | |
7371 | record_full_arch_list_add_reg (ir.regcache, i); | |
7372 | ||
7373 | for (i = I387_FCTRL_REGNUM (tdep); | |
7374 | i386_fpc_regnum_p (gdbarch, i); i++) | |
7375 | record_full_arch_list_add_reg (ir.regcache, i); | |
7376 | } | |
7377 | break; | |
7378 | ||
7379 | case 2: /* ldmxcsr */ | |
7380 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
7381 | goto no_support; | |
7382 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
7383 | break; | |
7384 | ||
7385 | case 3: /* stmxcsr */ | |
7386 | ir.ot = OT_LONG; | |
7387 | if (i386_record_lea_modrm (&ir)) | |
7388 | return -1; | |
7389 | break; | |
7390 | ||
7391 | case 5: /* lfence */ | |
7392 | case 6: /* mfence */ | |
7393 | case 7: /* sfence clflush */ | |
7394 | break; | |
7395 | ||
7396 | default: | |
7397 | opcode = (opcode << 8) | ir.modrm; | |
7398 | goto no_support; | |
7399 | break; | |
7400 | } | |
a3c4230a HZ |
7401 | break; |
7402 | ||
7403 | case 0x0fc3: /* movnti */ | |
7404 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
7405 | if (i386_record_modrm (&ir)) | |
7406 | return -1; | |
7407 | if (ir.mod == 3) | |
dda83cd7 | 7408 | goto no_support; |
a3c4230a HZ |
7409 | ir.reg |= rex_r; |
7410 | if (i386_record_lea_modrm (&ir)) | |
dda83cd7 | 7411 | return -1; |
a3c4230a HZ |
7412 | break; |
7413 | ||
7414 | /* Add prefix to opcode. */ | |
7415 | case 0x0f10: | |
7416 | case 0x0f11: | |
7417 | case 0x0f12: | |
7418 | case 0x0f13: | |
7419 | case 0x0f14: | |
7420 | case 0x0f15: | |
7421 | case 0x0f16: | |
7422 | case 0x0f17: | |
7423 | case 0x0f28: | |
7424 | case 0x0f29: | |
7425 | case 0x0f2a: | |
7426 | case 0x0f2b: | |
7427 | case 0x0f2c: | |
7428 | case 0x0f2d: | |
7429 | case 0x0f2e: | |
7430 | case 0x0f2f: | |
7431 | case 0x0f38: | |
7432 | case 0x0f39: | |
7433 | case 0x0f3a: | |
7434 | case 0x0f50: | |
7435 | case 0x0f51: | |
7436 | case 0x0f52: | |
7437 | case 0x0f53: | |
7438 | case 0x0f54: | |
7439 | case 0x0f55: | |
7440 | case 0x0f56: | |
7441 | case 0x0f57: | |
7442 | case 0x0f58: | |
7443 | case 0x0f59: | |
7444 | case 0x0f5a: | |
7445 | case 0x0f5b: | |
7446 | case 0x0f5c: | |
7447 | case 0x0f5d: | |
7448 | case 0x0f5e: | |
7449 | case 0x0f5f: | |
7450 | case 0x0f60: | |
7451 | case 0x0f61: | |
7452 | case 0x0f62: | |
7453 | case 0x0f63: | |
7454 | case 0x0f64: | |
7455 | case 0x0f65: | |
7456 | case 0x0f66: | |
7457 | case 0x0f67: | |
7458 | case 0x0f68: | |
7459 | case 0x0f69: | |
7460 | case 0x0f6a: | |
7461 | case 0x0f6b: | |
7462 | case 0x0f6c: | |
7463 | case 0x0f6d: | |
7464 | case 0x0f6e: | |
7465 | case 0x0f6f: | |
7466 | case 0x0f70: | |
7467 | case 0x0f71: | |
7468 | case 0x0f72: | |
7469 | case 0x0f73: | |
7470 | case 0x0f74: | |
7471 | case 0x0f75: | |
7472 | case 0x0f76: | |
7473 | case 0x0f7c: | |
7474 | case 0x0f7d: | |
7475 | case 0x0f7e: | |
7476 | case 0x0f7f: | |
7477 | case 0x0fb8: | |
7478 | case 0x0fc2: | |
7479 | case 0x0fc4: | |
7480 | case 0x0fc5: | |
7481 | case 0x0fc6: | |
7482 | case 0x0fd0: | |
7483 | case 0x0fd1: | |
7484 | case 0x0fd2: | |
7485 | case 0x0fd3: | |
7486 | case 0x0fd4: | |
7487 | case 0x0fd5: | |
7488 | case 0x0fd6: | |
7489 | case 0x0fd7: | |
7490 | case 0x0fd8: | |
7491 | case 0x0fd9: | |
7492 | case 0x0fda: | |
7493 | case 0x0fdb: | |
7494 | case 0x0fdc: | |
7495 | case 0x0fdd: | |
7496 | case 0x0fde: | |
7497 | case 0x0fdf: | |
7498 | case 0x0fe0: | |
7499 | case 0x0fe1: | |
7500 | case 0x0fe2: | |
7501 | case 0x0fe3: | |
7502 | case 0x0fe4: | |
7503 | case 0x0fe5: | |
7504 | case 0x0fe6: | |
7505 | case 0x0fe7: | |
7506 | case 0x0fe8: | |
7507 | case 0x0fe9: | |
7508 | case 0x0fea: | |
7509 | case 0x0feb: | |
7510 | case 0x0fec: | |
7511 | case 0x0fed: | |
7512 | case 0x0fee: | |
7513 | case 0x0fef: | |
7514 | case 0x0ff0: | |
7515 | case 0x0ff1: | |
7516 | case 0x0ff2: | |
7517 | case 0x0ff3: | |
7518 | case 0x0ff4: | |
7519 | case 0x0ff5: | |
7520 | case 0x0ff6: | |
7521 | case 0x0ff7: | |
7522 | case 0x0ff8: | |
7523 | case 0x0ff9: | |
7524 | case 0x0ffa: | |
7525 | case 0x0ffb: | |
7526 | case 0x0ffc: | |
7527 | case 0x0ffd: | |
7528 | case 0x0ffe: | |
f9fda3f5 L |
7529 | /* Mask out PREFIX_ADDR. */ |
7530 | switch ((prefixes & ~PREFIX_ADDR)) | |
dda83cd7 SM |
7531 | { |
7532 | case PREFIX_REPNZ: | |
7533 | opcode |= 0xf20000; | |
7534 | break; | |
7535 | case PREFIX_DATA: | |
7536 | opcode |= 0x660000; | |
7537 | break; | |
7538 | case PREFIX_REPZ: | |
7539 | opcode |= 0xf30000; | |
7540 | break; | |
7541 | } | |
a3c4230a HZ |
7542 | reswitch_prefix_add: |
7543 | switch (opcode) | |
dda83cd7 SM |
7544 | { |
7545 | case 0x0f38: | |
7546 | case 0x660f38: | |
7547 | case 0xf20f38: | |
7548 | case 0x0f3a: | |
7549 | case 0x660f3a: | |
7550 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) | |
4ffa4fc7 | 7551 | return -1; |
dda83cd7 SM |
7552 | ir.addr++; |
7553 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7554 | goto reswitch_prefix_add; | |
7555 | break; | |
7556 | ||
7557 | case 0x0f10: /* movups */ | |
7558 | case 0x660f10: /* movupd */ | |
7559 | case 0xf30f10: /* movss */ | |
7560 | case 0xf20f10: /* movsd */ | |
7561 | case 0x0f12: /* movlps */ | |
7562 | case 0x660f12: /* movlpd */ | |
7563 | case 0xf30f12: /* movsldup */ | |
7564 | case 0xf20f12: /* movddup */ | |
7565 | case 0x0f14: /* unpcklps */ | |
7566 | case 0x660f14: /* unpcklpd */ | |
7567 | case 0x0f15: /* unpckhps */ | |
7568 | case 0x660f15: /* unpckhpd */ | |
7569 | case 0x0f16: /* movhps */ | |
7570 | case 0x660f16: /* movhpd */ | |
7571 | case 0xf30f16: /* movshdup */ | |
7572 | case 0x0f28: /* movaps */ | |
7573 | case 0x660f28: /* movapd */ | |
7574 | case 0x0f2a: /* cvtpi2ps */ | |
7575 | case 0x660f2a: /* cvtpi2pd */ | |
7576 | case 0xf30f2a: /* cvtsi2ss */ | |
7577 | case 0xf20f2a: /* cvtsi2sd */ | |
7578 | case 0x0f2c: /* cvttps2pi */ | |
7579 | case 0x660f2c: /* cvttpd2pi */ | |
7580 | case 0x0f2d: /* cvtps2pi */ | |
7581 | case 0x660f2d: /* cvtpd2pi */ | |
7582 | case 0x660f3800: /* pshufb */ | |
7583 | case 0x660f3801: /* phaddw */ | |
7584 | case 0x660f3802: /* phaddd */ | |
7585 | case 0x660f3803: /* phaddsw */ | |
7586 | case 0x660f3804: /* pmaddubsw */ | |
7587 | case 0x660f3805: /* phsubw */ | |
7588 | case 0x660f3806: /* phsubd */ | |
7589 | case 0x660f3807: /* phsubsw */ | |
7590 | case 0x660f3808: /* psignb */ | |
7591 | case 0x660f3809: /* psignw */ | |
7592 | case 0x660f380a: /* psignd */ | |
7593 | case 0x660f380b: /* pmulhrsw */ | |
7594 | case 0x660f3810: /* pblendvb */ | |
7595 | case 0x660f3814: /* blendvps */ | |
7596 | case 0x660f3815: /* blendvpd */ | |
7597 | case 0x660f381c: /* pabsb */ | |
7598 | case 0x660f381d: /* pabsw */ | |
7599 | case 0x660f381e: /* pabsd */ | |
7600 | case 0x660f3820: /* pmovsxbw */ | |
7601 | case 0x660f3821: /* pmovsxbd */ | |
7602 | case 0x660f3822: /* pmovsxbq */ | |
7603 | case 0x660f3823: /* pmovsxwd */ | |
7604 | case 0x660f3824: /* pmovsxwq */ | |
7605 | case 0x660f3825: /* pmovsxdq */ | |
7606 | case 0x660f3828: /* pmuldq */ | |
7607 | case 0x660f3829: /* pcmpeqq */ | |
7608 | case 0x660f382a: /* movntdqa */ | |
7609 | case 0x660f3a08: /* roundps */ | |
7610 | case 0x660f3a09: /* roundpd */ | |
7611 | case 0x660f3a0a: /* roundss */ | |
7612 | case 0x660f3a0b: /* roundsd */ | |
7613 | case 0x660f3a0c: /* blendps */ | |
7614 | case 0x660f3a0d: /* blendpd */ | |
7615 | case 0x660f3a0e: /* pblendw */ | |
7616 | case 0x660f3a0f: /* palignr */ | |
7617 | case 0x660f3a20: /* pinsrb */ | |
7618 | case 0x660f3a21: /* insertps */ | |
7619 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7620 | case 0x660f3a40: /* dpps */ | |
7621 | case 0x660f3a41: /* dppd */ | |
7622 | case 0x660f3a42: /* mpsadbw */ | |
7623 | case 0x660f3a60: /* pcmpestrm */ | |
7624 | case 0x660f3a61: /* pcmpestri */ | |
7625 | case 0x660f3a62: /* pcmpistrm */ | |
7626 | case 0x660f3a63: /* pcmpistri */ | |
7627 | case 0x0f51: /* sqrtps */ | |
7628 | case 0x660f51: /* sqrtpd */ | |
7629 | case 0xf20f51: /* sqrtsd */ | |
7630 | case 0xf30f51: /* sqrtss */ | |
7631 | case 0x0f52: /* rsqrtps */ | |
7632 | case 0xf30f52: /* rsqrtss */ | |
7633 | case 0x0f53: /* rcpps */ | |
7634 | case 0xf30f53: /* rcpss */ | |
7635 | case 0x0f54: /* andps */ | |
7636 | case 0x660f54: /* andpd */ | |
7637 | case 0x0f55: /* andnps */ | |
7638 | case 0x660f55: /* andnpd */ | |
7639 | case 0x0f56: /* orps */ | |
7640 | case 0x660f56: /* orpd */ | |
7641 | case 0x0f57: /* xorps */ | |
7642 | case 0x660f57: /* xorpd */ | |
7643 | case 0x0f58: /* addps */ | |
7644 | case 0x660f58: /* addpd */ | |
7645 | case 0xf20f58: /* addsd */ | |
7646 | case 0xf30f58: /* addss */ | |
7647 | case 0x0f59: /* mulps */ | |
7648 | case 0x660f59: /* mulpd */ | |
7649 | case 0xf20f59: /* mulsd */ | |
7650 | case 0xf30f59: /* mulss */ | |
7651 | case 0x0f5a: /* cvtps2pd */ | |
7652 | case 0x660f5a: /* cvtpd2ps */ | |
7653 | case 0xf20f5a: /* cvtsd2ss */ | |
7654 | case 0xf30f5a: /* cvtss2sd */ | |
7655 | case 0x0f5b: /* cvtdq2ps */ | |
7656 | case 0x660f5b: /* cvtps2dq */ | |
7657 | case 0xf30f5b: /* cvttps2dq */ | |
7658 | case 0x0f5c: /* subps */ | |
7659 | case 0x660f5c: /* subpd */ | |
7660 | case 0xf20f5c: /* subsd */ | |
7661 | case 0xf30f5c: /* subss */ | |
7662 | case 0x0f5d: /* minps */ | |
7663 | case 0x660f5d: /* minpd */ | |
7664 | case 0xf20f5d: /* minsd */ | |
7665 | case 0xf30f5d: /* minss */ | |
7666 | case 0x0f5e: /* divps */ | |
7667 | case 0x660f5e: /* divpd */ | |
7668 | case 0xf20f5e: /* divsd */ | |
7669 | case 0xf30f5e: /* divss */ | |
7670 | case 0x0f5f: /* maxps */ | |
7671 | case 0x660f5f: /* maxpd */ | |
7672 | case 0xf20f5f: /* maxsd */ | |
7673 | case 0xf30f5f: /* maxss */ | |
7674 | case 0x660f60: /* punpcklbw */ | |
7675 | case 0x660f61: /* punpcklwd */ | |
7676 | case 0x660f62: /* punpckldq */ | |
7677 | case 0x660f63: /* packsswb */ | |
7678 | case 0x660f64: /* pcmpgtb */ | |
7679 | case 0x660f65: /* pcmpgtw */ | |
7680 | case 0x660f66: /* pcmpgtd */ | |
7681 | case 0x660f67: /* packuswb */ | |
7682 | case 0x660f68: /* punpckhbw */ | |
7683 | case 0x660f69: /* punpckhwd */ | |
7684 | case 0x660f6a: /* punpckhdq */ | |
7685 | case 0x660f6b: /* packssdw */ | |
7686 | case 0x660f6c: /* punpcklqdq */ | |
7687 | case 0x660f6d: /* punpckhqdq */ | |
7688 | case 0x660f6e: /* movd */ | |
7689 | case 0x660f6f: /* movdqa */ | |
7690 | case 0xf30f6f: /* movdqu */ | |
7691 | case 0x660f70: /* pshufd */ | |
7692 | case 0xf20f70: /* pshuflw */ | |
7693 | case 0xf30f70: /* pshufhw */ | |
7694 | case 0x660f74: /* pcmpeqb */ | |
7695 | case 0x660f75: /* pcmpeqw */ | |
7696 | case 0x660f76: /* pcmpeqd */ | |
7697 | case 0x660f7c: /* haddpd */ | |
7698 | case 0xf20f7c: /* haddps */ | |
7699 | case 0x660f7d: /* hsubpd */ | |
7700 | case 0xf20f7d: /* hsubps */ | |
7701 | case 0xf30f7e: /* movq */ | |
7702 | case 0x0fc2: /* cmpps */ | |
7703 | case 0x660fc2: /* cmppd */ | |
7704 | case 0xf20fc2: /* cmpsd */ | |
7705 | case 0xf30fc2: /* cmpss */ | |
7706 | case 0x660fc4: /* pinsrw */ | |
7707 | case 0x0fc6: /* shufps */ | |
7708 | case 0x660fc6: /* shufpd */ | |
7709 | case 0x660fd0: /* addsubpd */ | |
7710 | case 0xf20fd0: /* addsubps */ | |
7711 | case 0x660fd1: /* psrlw */ | |
7712 | case 0x660fd2: /* psrld */ | |
7713 | case 0x660fd3: /* psrlq */ | |
7714 | case 0x660fd4: /* paddq */ | |
7715 | case 0x660fd5: /* pmullw */ | |
7716 | case 0xf30fd6: /* movq2dq */ | |
7717 | case 0x660fd8: /* psubusb */ | |
7718 | case 0x660fd9: /* psubusw */ | |
7719 | case 0x660fda: /* pminub */ | |
7720 | case 0x660fdb: /* pand */ | |
7721 | case 0x660fdc: /* paddusb */ | |
7722 | case 0x660fdd: /* paddusw */ | |
7723 | case 0x660fde: /* pmaxub */ | |
7724 | case 0x660fdf: /* pandn */ | |
7725 | case 0x660fe0: /* pavgb */ | |
7726 | case 0x660fe1: /* psraw */ | |
7727 | case 0x660fe2: /* psrad */ | |
7728 | case 0x660fe3: /* pavgw */ | |
7729 | case 0x660fe4: /* pmulhuw */ | |
7730 | case 0x660fe5: /* pmulhw */ | |
7731 | case 0x660fe6: /* cvttpd2dq */ | |
7732 | case 0xf20fe6: /* cvtpd2dq */ | |
7733 | case 0xf30fe6: /* cvtdq2pd */ | |
7734 | case 0x660fe8: /* psubsb */ | |
7735 | case 0x660fe9: /* psubsw */ | |
7736 | case 0x660fea: /* pminsw */ | |
7737 | case 0x660feb: /* por */ | |
7738 | case 0x660fec: /* paddsb */ | |
7739 | case 0x660fed: /* paddsw */ | |
7740 | case 0x660fee: /* pmaxsw */ | |
7741 | case 0x660fef: /* pxor */ | |
7742 | case 0xf20ff0: /* lddqu */ | |
7743 | case 0x660ff1: /* psllw */ | |
7744 | case 0x660ff2: /* pslld */ | |
7745 | case 0x660ff3: /* psllq */ | |
7746 | case 0x660ff4: /* pmuludq */ | |
7747 | case 0x660ff5: /* pmaddwd */ | |
7748 | case 0x660ff6: /* psadbw */ | |
7749 | case 0x660ff8: /* psubb */ | |
7750 | case 0x660ff9: /* psubw */ | |
7751 | case 0x660ffa: /* psubd */ | |
7752 | case 0x660ffb: /* psubq */ | |
7753 | case 0x660ffc: /* paddb */ | |
7754 | case 0x660ffd: /* paddw */ | |
7755 | case 0x660ffe: /* paddd */ | |
7756 | if (i386_record_modrm (&ir)) | |
a3c4230a | 7757 | return -1; |
dda83cd7 SM |
7758 | ir.reg |= rex_r; |
7759 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) | |
7760 | goto no_support; | |
7761 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7762 | I387_XMM0_REGNUM (tdep) + ir.reg); |
dda83cd7 SM |
7763 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
7764 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7765 | break; | |
7766 | ||
7767 | case 0x0f11: /* movups */ | |
7768 | case 0x660f11: /* movupd */ | |
7769 | case 0xf30f11: /* movss */ | |
7770 | case 0xf20f11: /* movsd */ | |
7771 | case 0x0f13: /* movlps */ | |
7772 | case 0x660f13: /* movlpd */ | |
7773 | case 0x0f17: /* movhps */ | |
7774 | case 0x660f17: /* movhpd */ | |
7775 | case 0x0f29: /* movaps */ | |
7776 | case 0x660f29: /* movapd */ | |
7777 | case 0x660f3a14: /* pextrb */ | |
7778 | case 0x660f3a15: /* pextrw */ | |
7779 | case 0x660f3a16: /* pextrd pextrq */ | |
7780 | case 0x660f3a17: /* extractps */ | |
7781 | case 0x660f7f: /* movdqa */ | |
7782 | case 0xf30f7f: /* movdqu */ | |
7783 | if (i386_record_modrm (&ir)) | |
a3c4230a | 7784 | return -1; |
dda83cd7 SM |
7785 | if (ir.mod == 3) |
7786 | { | |
7787 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7788 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7789 | goto no_support; | |
7790 | ir.rm |= ir.rex_b; | |
7791 | if (!i386_xmm_regnum_p (gdbarch, | |
1777feb0 | 7792 | I387_XMM0_REGNUM (tdep) + ir.rm)) |
dda83cd7 SM |
7793 | goto no_support; |
7794 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7795 | I387_XMM0_REGNUM (tdep) + ir.rm); |
dda83cd7 SM |
7796 | } |
7797 | else | |
7798 | { | |
7799 | switch (opcode) | |
7800 | { | |
7801 | case 0x660f3a14: | |
7802 | ir.ot = OT_BYTE; | |
7803 | break; | |
7804 | case 0x660f3a15: | |
7805 | ir.ot = OT_WORD; | |
7806 | break; | |
7807 | case 0x660f3a16: | |
7808 | ir.ot = OT_LONG; | |
7809 | break; | |
7810 | case 0x660f3a17: | |
7811 | ir.ot = OT_QUAD; | |
7812 | break; | |
7813 | default: | |
7814 | ir.ot = OT_DQUAD; | |
7815 | break; | |
7816 | } | |
7817 | if (i386_record_lea_modrm (&ir)) | |
7818 | return -1; | |
7819 | } | |
7820 | break; | |
7821 | ||
7822 | case 0x0f2b: /* movntps */ | |
7823 | case 0x660f2b: /* movntpd */ | |
7824 | case 0x0fe7: /* movntq */ | |
7825 | case 0x660fe7: /* movntdq */ | |
7826 | if (ir.mod == 3) | |
7827 | goto no_support; | |
7828 | if (opcode == 0x0fe7) | |
7829 | ir.ot = OT_QUAD; | |
7830 | else | |
7831 | ir.ot = OT_DQUAD; | |
7832 | if (i386_record_lea_modrm (&ir)) | |
a3c4230a | 7833 | return -1; |
dda83cd7 SM |
7834 | break; |
7835 | ||
7836 | case 0xf30f2c: /* cvttss2si */ | |
7837 | case 0xf20f2c: /* cvttsd2si */ | |
7838 | case 0xf30f2d: /* cvtss2si */ | |
7839 | case 0xf20f2d: /* cvtsd2si */ | |
7840 | case 0xf20f38f0: /* crc32 */ | |
7841 | case 0xf20f38f1: /* crc32 */ | |
7842 | case 0x0f50: /* movmskps */ | |
7843 | case 0x660f50: /* movmskpd */ | |
7844 | case 0x0fc5: /* pextrw */ | |
7845 | case 0x660fc5: /* pextrw */ | |
7846 | case 0x0fd7: /* pmovmskb */ | |
7847 | case 0x660fd7: /* pmovmskb */ | |
7848 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
7849 | break; | |
7850 | ||
7851 | case 0x0f3800: /* pshufb */ | |
7852 | case 0x0f3801: /* phaddw */ | |
7853 | case 0x0f3802: /* phaddd */ | |
7854 | case 0x0f3803: /* phaddsw */ | |
7855 | case 0x0f3804: /* pmaddubsw */ | |
7856 | case 0x0f3805: /* phsubw */ | |
7857 | case 0x0f3806: /* phsubd */ | |
7858 | case 0x0f3807: /* phsubsw */ | |
7859 | case 0x0f3808: /* psignb */ | |
7860 | case 0x0f3809: /* psignw */ | |
7861 | case 0x0f380a: /* psignd */ | |
7862 | case 0x0f380b: /* pmulhrsw */ | |
7863 | case 0x0f381c: /* pabsb */ | |
7864 | case 0x0f381d: /* pabsw */ | |
7865 | case 0x0f381e: /* pabsd */ | |
7866 | case 0x0f382b: /* packusdw */ | |
7867 | case 0x0f3830: /* pmovzxbw */ | |
7868 | case 0x0f3831: /* pmovzxbd */ | |
7869 | case 0x0f3832: /* pmovzxbq */ | |
7870 | case 0x0f3833: /* pmovzxwd */ | |
7871 | case 0x0f3834: /* pmovzxwq */ | |
7872 | case 0x0f3835: /* pmovzxdq */ | |
7873 | case 0x0f3837: /* pcmpgtq */ | |
7874 | case 0x0f3838: /* pminsb */ | |
7875 | case 0x0f3839: /* pminsd */ | |
7876 | case 0x0f383a: /* pminuw */ | |
7877 | case 0x0f383b: /* pminud */ | |
7878 | case 0x0f383c: /* pmaxsb */ | |
7879 | case 0x0f383d: /* pmaxsd */ | |
7880 | case 0x0f383e: /* pmaxuw */ | |
7881 | case 0x0f383f: /* pmaxud */ | |
7882 | case 0x0f3840: /* pmulld */ | |
7883 | case 0x0f3841: /* phminposuw */ | |
7884 | case 0x0f3a0f: /* palignr */ | |
7885 | case 0x0f60: /* punpcklbw */ | |
7886 | case 0x0f61: /* punpcklwd */ | |
7887 | case 0x0f62: /* punpckldq */ | |
7888 | case 0x0f63: /* packsswb */ | |
7889 | case 0x0f64: /* pcmpgtb */ | |
7890 | case 0x0f65: /* pcmpgtw */ | |
7891 | case 0x0f66: /* pcmpgtd */ | |
7892 | case 0x0f67: /* packuswb */ | |
7893 | case 0x0f68: /* punpckhbw */ | |
7894 | case 0x0f69: /* punpckhwd */ | |
7895 | case 0x0f6a: /* punpckhdq */ | |
7896 | case 0x0f6b: /* packssdw */ | |
7897 | case 0x0f6e: /* movd */ | |
7898 | case 0x0f6f: /* movq */ | |
7899 | case 0x0f70: /* pshufw */ | |
7900 | case 0x0f74: /* pcmpeqb */ | |
7901 | case 0x0f75: /* pcmpeqw */ | |
7902 | case 0x0f76: /* pcmpeqd */ | |
7903 | case 0x0fc4: /* pinsrw */ | |
7904 | case 0x0fd1: /* psrlw */ | |
7905 | case 0x0fd2: /* psrld */ | |
7906 | case 0x0fd3: /* psrlq */ | |
7907 | case 0x0fd4: /* paddq */ | |
7908 | case 0x0fd5: /* pmullw */ | |
7909 | case 0xf20fd6: /* movdq2q */ | |
7910 | case 0x0fd8: /* psubusb */ | |
7911 | case 0x0fd9: /* psubusw */ | |
7912 | case 0x0fda: /* pminub */ | |
7913 | case 0x0fdb: /* pand */ | |
7914 | case 0x0fdc: /* paddusb */ | |
7915 | case 0x0fdd: /* paddusw */ | |
7916 | case 0x0fde: /* pmaxub */ | |
7917 | case 0x0fdf: /* pandn */ | |
7918 | case 0x0fe0: /* pavgb */ | |
7919 | case 0x0fe1: /* psraw */ | |
7920 | case 0x0fe2: /* psrad */ | |
7921 | case 0x0fe3: /* pavgw */ | |
7922 | case 0x0fe4: /* pmulhuw */ | |
7923 | case 0x0fe5: /* pmulhw */ | |
7924 | case 0x0fe8: /* psubsb */ | |
7925 | case 0x0fe9: /* psubsw */ | |
7926 | case 0x0fea: /* pminsw */ | |
7927 | case 0x0feb: /* por */ | |
7928 | case 0x0fec: /* paddsb */ | |
7929 | case 0x0fed: /* paddsw */ | |
7930 | case 0x0fee: /* pmaxsw */ | |
7931 | case 0x0fef: /* pxor */ | |
7932 | case 0x0ff1: /* psllw */ | |
7933 | case 0x0ff2: /* pslld */ | |
7934 | case 0x0ff3: /* psllq */ | |
7935 | case 0x0ff4: /* pmuludq */ | |
7936 | case 0x0ff5: /* pmaddwd */ | |
7937 | case 0x0ff6: /* psadbw */ | |
7938 | case 0x0ff8: /* psubb */ | |
7939 | case 0x0ff9: /* psubw */ | |
7940 | case 0x0ffa: /* psubd */ | |
7941 | case 0x0ffb: /* psubq */ | |
7942 | case 0x0ffc: /* paddb */ | |
7943 | case 0x0ffd: /* paddw */ | |
7944 | case 0x0ffe: /* paddd */ | |
7945 | if (i386_record_modrm (&ir)) | |
7946 | return -1; | |
7947 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7948 | goto no_support; | |
7949 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7950 | I387_MM0_REGNUM (tdep) + ir.reg); |
dda83cd7 | 7951 | break; |
a3c4230a | 7952 | |
dda83cd7 SM |
7953 | case 0x0f71: /* psllw */ |
7954 | case 0x0f72: /* pslld */ | |
7955 | case 0x0f73: /* psllq */ | |
7956 | if (i386_record_modrm (&ir)) | |
a3c4230a | 7957 | return -1; |
dda83cd7 SM |
7958 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) |
7959 | goto no_support; | |
7960 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7961 | I387_MM0_REGNUM (tdep) + ir.rm); |
dda83cd7 | 7962 | break; |
a3c4230a | 7963 | |
dda83cd7 SM |
7964 | case 0x660f71: /* psllw */ |
7965 | case 0x660f72: /* pslld */ | |
7966 | case 0x660f73: /* psllq */ | |
7967 | if (i386_record_modrm (&ir)) | |
a3c4230a | 7968 | return -1; |
dda83cd7 SM |
7969 | ir.rm |= ir.rex_b; |
7970 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) | |
7971 | goto no_support; | |
7972 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7973 | I387_XMM0_REGNUM (tdep) + ir.rm); |
dda83cd7 | 7974 | break; |
a3c4230a | 7975 | |
dda83cd7 SM |
7976 | case 0x0f7e: /* movd */ |
7977 | case 0x660f7e: /* movd */ | |
7978 | if (i386_record_modrm (&ir)) | |
a3c4230a | 7979 | return -1; |
dda83cd7 SM |
7980 | if (ir.mod == 3) |
7981 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7982 | else | |
7983 | { | |
7984 | if (ir.dflag == 2) | |
7985 | ir.ot = OT_QUAD; | |
7986 | else | |
7987 | ir.ot = OT_LONG; | |
7988 | if (i386_record_lea_modrm (&ir)) | |
7989 | return -1; | |
7990 | } | |
7991 | break; | |
7992 | ||
7993 | case 0x0f7f: /* movq */ | |
7994 | if (i386_record_modrm (&ir)) | |
a3c4230a | 7995 | return -1; |
dda83cd7 SM |
7996 | if (ir.mod == 3) |
7997 | { | |
7998 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7999 | goto no_support; | |
8000 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8001 | I387_MM0_REGNUM (tdep) + ir.rm); |
dda83cd7 SM |
8002 | } |
8003 | else | |
8004 | { | |
8005 | ir.ot = OT_QUAD; | |
8006 | if (i386_record_lea_modrm (&ir)) | |
8007 | return -1; | |
8008 | } | |
8009 | break; | |
8010 | ||
8011 | case 0xf30fb8: /* popcnt */ | |
8012 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8013 | return -1; |
dda83cd7 SM |
8014 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
8015 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
8016 | break; | |
a3c4230a | 8017 | |
dda83cd7 SM |
8018 | case 0x660fd6: /* movq */ |
8019 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8020 | return -1; |
dda83cd7 SM |
8021 | if (ir.mod == 3) |
8022 | { | |
8023 | ir.rm |= ir.rex_b; | |
8024 | if (!i386_xmm_regnum_p (gdbarch, | |
1777feb0 | 8025 | I387_XMM0_REGNUM (tdep) + ir.rm)) |
dda83cd7 SM |
8026 | goto no_support; |
8027 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8028 | I387_XMM0_REGNUM (tdep) + ir.rm); |
dda83cd7 SM |
8029 | } |
8030 | else | |
8031 | { | |
8032 | ir.ot = OT_QUAD; | |
8033 | if (i386_record_lea_modrm (&ir)) | |
8034 | return -1; | |
8035 | } | |
8036 | break; | |
8037 | ||
8038 | case 0x660f3817: /* ptest */ | |
8039 | case 0x0f2e: /* ucomiss */ | |
8040 | case 0x660f2e: /* ucomisd */ | |
8041 | case 0x0f2f: /* comiss */ | |
8042 | case 0x660f2f: /* comisd */ | |
8043 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
8044 | break; | |
8045 | ||
8046 | case 0x0ff7: /* maskmovq */ | |
8047 | regcache_raw_read_unsigned (ir.regcache, | |
8048 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8049 | &addr); | |
8050 | if (record_full_arch_list_add_mem (addr, 64)) | |
8051 | return -1; | |
8052 | break; | |
8053 | ||
8054 | case 0x660ff7: /* maskmovdqu */ | |
8055 | regcache_raw_read_unsigned (ir.regcache, | |
8056 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8057 | &addr); | |
8058 | if (record_full_arch_list_add_mem (addr, 128)) | |
8059 | return -1; | |
8060 | break; | |
8061 | ||
8062 | default: | |
8063 | goto no_support; | |
8064 | break; | |
8065 | } | |
a3c4230a | 8066 | break; |
7ad10968 HZ |
8067 | |
8068 | default: | |
7ad10968 HZ |
8069 | goto no_support; |
8070 | break; | |
8071 | } | |
8072 | ||
cf648174 | 8073 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
8074 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
8075 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
8076 | return -1; |
8077 | ||
8078 | return 0; | |
8079 | ||
01fe1b41 | 8080 | no_support: |
a3c4230a | 8081 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
dda83cd7 SM |
8082 | "at address %s.\n"), |
8083 | (unsigned int) (opcode), | |
8084 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
8085 | return -1; |
8086 | } | |
8087 | ||
cf648174 HZ |
8088 | static const int i386_record_regmap[] = |
8089 | { | |
8090 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
8091 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
8092 | 0, 0, 0, 0, 0, 0, 0, 0, | |
8093 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
8094 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
8095 | }; | |
8096 | ||
7a697b8d | 8097 | /* Check that the given address appears suitable for a fast |
405f8e94 | 8098 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
8099 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
8100 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
8101 | middle of the tracepoint jump. On x86, it may be possible to use |
8102 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
8103 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
8104 | of instruction to replace, and 0 if not, plus an explanatory |
8105 | string. */ | |
8106 | ||
8107 | static int | |
6b940e6a | 8108 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr, |
281d762b | 8109 | std::string *msg) |
7a697b8d SS |
8110 | { |
8111 | int len, jumplen; | |
7a697b8d | 8112 | |
405f8e94 SS |
8113 | /* Ask the target for the minimum instruction length supported. */ |
8114 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
8115 | ||
8116 | if (jumplen < 0) | |
8117 | { | |
8118 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
8119 | operation, assume that fast tracepoints will always be implemented | |
8120 | using 4-byte relative jumps on both x86 and x86-64. */ | |
8121 | jumplen = 5; | |
8122 | } | |
8123 | else if (jumplen == 0) | |
8124 | { | |
8125 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
8126 | returns zero, then the IPA has not loaded yet. In this case, | |
8127 | we optimistically assume that truncated 2-byte relative jumps | |
8128 | will be available on x86, and compensate later if this assumption | |
8129 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
8130 | jumps will always be used. */ | |
8131 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
8132 | } | |
7a697b8d | 8133 | |
7a697b8d | 8134 | /* Check for fit. */ |
be85ce7d | 8135 | len = gdb_insn_length (gdbarch, addr); |
405f8e94 | 8136 | |
7a697b8d SS |
8137 | if (len < jumplen) |
8138 | { | |
8139 | /* Return a bit of target-specific detail to add to the caller's | |
8140 | generic failure message. */ | |
8141 | if (msg) | |
281d762b TT |
8142 | *msg = string_printf (_("; instruction is only %d bytes long, " |
8143 | "need at least %d bytes for the jump"), | |
8144 | len, jumplen); | |
7a697b8d SS |
8145 | return 0; |
8146 | } | |
405f8e94 SS |
8147 | else |
8148 | { | |
8149 | if (msg) | |
281d762b | 8150 | msg->clear (); |
405f8e94 SS |
8151 | return 1; |
8152 | } | |
7a697b8d SS |
8153 | } |
8154 | ||
00d5215e UW |
8155 | /* Return a floating-point format for a floating-point variable of |
8156 | length LEN in bits. If non-NULL, NAME is the name of its type. | |
8157 | If no suitable type is found, return NULL. */ | |
8158 | ||
cb8c24b6 | 8159 | static const struct floatformat ** |
00d5215e UW |
8160 | i386_floatformat_for_type (struct gdbarch *gdbarch, |
8161 | const char *name, int len) | |
8162 | { | |
8163 | if (len == 128 && name) | |
8164 | if (strcmp (name, "__float128") == 0 | |
8165 | || strcmp (name, "_Float128") == 0 | |
34d11c68 AB |
8166 | || strcmp (name, "complex _Float128") == 0 |
8167 | || strcmp (name, "complex(kind=16)") == 0 | |
8d624a9d FW |
8168 | || strcmp (name, "complex*32") == 0 |
8169 | || strcmp (name, "COMPLEX*32") == 0 | |
e56798df AKS |
8170 | || strcmp (name, "quad complex") == 0 |
8171 | || strcmp (name, "real(kind=16)") == 0 | |
8d624a9d FW |
8172 | || strcmp (name, "real*16") == 0 |
8173 | || strcmp (name, "REAL*16") == 0) | |
00d5215e UW |
8174 | return floatformats_ia64_quad; |
8175 | ||
8176 | return default_floatformat_for_type (gdbarch, name, len); | |
8177 | } | |
8178 | ||
90884b2b L |
8179 | static int |
8180 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
8181 | struct tdesc_arch_data *tdesc_data) | |
8182 | { | |
8183 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 8184 | const struct tdesc_feature *feature_core; |
01f9f808 MS |
8185 | |
8186 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, | |
1163a4b7 | 8187 | *feature_avx512, *feature_pkeys, *feature_segments; |
90884b2b L |
8188 | int i, num_regs, valid_p; |
8189 | ||
8190 | if (! tdesc_has_registers (tdesc)) | |
8191 | return 0; | |
8192 | ||
8193 | /* Get core registers. */ | |
8194 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
8195 | if (feature_core == NULL) |
8196 | return 0; | |
90884b2b L |
8197 | |
8198 | /* Get SSE registers. */ | |
c131fcee | 8199 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 8200 | |
c131fcee L |
8201 | /* Try AVX registers. */ |
8202 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
8203 | ||
1dbcd68c WT |
8204 | /* Try MPX registers. */ |
8205 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
8206 | ||
01f9f808 MS |
8207 | /* Try AVX512 registers. */ |
8208 | feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); | |
8209 | ||
1163a4b7 JB |
8210 | /* Try segment base registers. */ |
8211 | feature_segments = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments"); | |
8212 | ||
51547df6 MS |
8213 | /* Try PKEYS */ |
8214 | feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys"); | |
8215 | ||
90884b2b L |
8216 | valid_p = 1; |
8217 | ||
c131fcee | 8218 | /* The XCR0 bits. */ |
01f9f808 MS |
8219 | if (feature_avx512) |
8220 | { | |
8221 | /* AVX512 register description requires AVX register description. */ | |
8222 | if (!feature_avx) | |
8223 | return 0; | |
8224 | ||
a1fa17ee | 8225 | tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK; |
01f9f808 MS |
8226 | |
8227 | /* It may have been set by OSABI initialization function. */ | |
8228 | if (tdep->k0_regnum < 0) | |
8229 | { | |
8230 | tdep->k_register_names = i386_k_names; | |
8231 | tdep->k0_regnum = I386_K0_REGNUM; | |
8232 | } | |
8233 | ||
8234 | for (i = 0; i < I387_NUM_K_REGS; i++) | |
8235 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8236 | tdep->k0_regnum + i, | |
8237 | i386_k_names[i]); | |
8238 | ||
8239 | if (tdep->num_zmm_regs == 0) | |
8240 | { | |
8241 | tdep->zmmh_register_names = i386_zmmh_names; | |
8242 | tdep->num_zmm_regs = 8; | |
8243 | tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; | |
8244 | } | |
8245 | ||
8246 | for (i = 0; i < tdep->num_zmm_regs; i++) | |
8247 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8248 | tdep->zmm0h_regnum + i, | |
8249 | tdep->zmmh_register_names[i]); | |
8250 | ||
8251 | for (i = 0; i < tdep->num_xmm_avx512_regs; i++) | |
8252 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8253 | tdep->xmm16_regnum + i, | |
8254 | tdep->xmm_avx512_register_names[i]); | |
8255 | ||
8256 | for (i = 0; i < tdep->num_ymm_avx512_regs; i++) | |
8257 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8258 | tdep->ymm16h_regnum + i, | |
8259 | tdep->ymm16h_register_names[i]); | |
8260 | } | |
c131fcee L |
8261 | if (feature_avx) |
8262 | { | |
3a13a53b L |
8263 | /* AVX register description requires SSE register description. */ |
8264 | if (!feature_sse) | |
8265 | return 0; | |
8266 | ||
01f9f808 | 8267 | if (!feature_avx512) |
df7e5265 | 8268 | tdep->xcr0 = X86_XSTATE_AVX_MASK; |
c131fcee L |
8269 | |
8270 | /* It may have been set by OSABI initialization function. */ | |
8271 | if (tdep->num_ymm_regs == 0) | |
8272 | { | |
8273 | tdep->ymmh_register_names = i386_ymmh_names; | |
8274 | tdep->num_ymm_regs = 8; | |
8275 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
8276 | } | |
8277 | ||
8278 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
8279 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
8280 | tdep->ymm0h_regnum + i, | |
8281 | tdep->ymmh_register_names[i]); | |
8282 | } | |
3a13a53b | 8283 | else if (feature_sse) |
df7e5265 | 8284 | tdep->xcr0 = X86_XSTATE_SSE_MASK; |
3a13a53b L |
8285 | else |
8286 | { | |
df7e5265 | 8287 | tdep->xcr0 = X86_XSTATE_X87_MASK; |
3a13a53b L |
8288 | tdep->num_xmm_regs = 0; |
8289 | } | |
c131fcee | 8290 | |
90884b2b L |
8291 | num_regs = tdep->num_core_regs; |
8292 | for (i = 0; i < num_regs; i++) | |
8293 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
8294 | tdep->register_names[i]); | |
8295 | ||
3a13a53b L |
8296 | if (feature_sse) |
8297 | { | |
8298 | /* Need to include %mxcsr, so add one. */ | |
8299 | num_regs += tdep->num_xmm_regs + 1; | |
8300 | for (; i < num_regs; i++) | |
8301 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
8302 | tdep->register_names[i]); | |
8303 | } | |
90884b2b | 8304 | |
1dbcd68c WT |
8305 | if (feature_mpx) |
8306 | { | |
df7e5265 | 8307 | tdep->xcr0 |= X86_XSTATE_MPX_MASK; |
1dbcd68c WT |
8308 | |
8309 | if (tdep->bnd0r_regnum < 0) | |
8310 | { | |
8311 | tdep->mpx_register_names = i386_mpx_names; | |
8312 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
8313 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
8314 | } | |
8315 | ||
8316 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
8317 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
8318 | I387_BND0R_REGNUM (tdep) + i, | |
8319 | tdep->mpx_register_names[i]); | |
8320 | } | |
8321 | ||
1163a4b7 JB |
8322 | if (feature_segments) |
8323 | { | |
8324 | if (tdep->fsbase_regnum < 0) | |
8325 | tdep->fsbase_regnum = I386_FSBASE_REGNUM; | |
8326 | valid_p &= tdesc_numbered_register (feature_segments, tdesc_data, | |
8327 | tdep->fsbase_regnum, "fs_base"); | |
8328 | valid_p &= tdesc_numbered_register (feature_segments, tdesc_data, | |
8329 | tdep->fsbase_regnum + 1, "gs_base"); | |
8330 | } | |
8331 | ||
51547df6 MS |
8332 | if (feature_pkeys) |
8333 | { | |
8334 | tdep->xcr0 |= X86_XSTATE_PKRU; | |
8335 | if (tdep->pkru_regnum < 0) | |
8336 | { | |
8337 | tdep->pkeys_register_names = i386_pkeys_names; | |
8338 | tdep->pkru_regnum = I386_PKRU_REGNUM; | |
8339 | tdep->num_pkeys_regs = 1; | |
8340 | } | |
8341 | ||
8342 | for (i = 0; i < I387_NUM_PKEYS_REGS; i++) | |
8343 | valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data, | |
8344 | I387_PKRU_REGNUM (tdep) + i, | |
8345 | tdep->pkeys_register_names[i]); | |
8346 | } | |
8347 | ||
90884b2b L |
8348 | return valid_p; |
8349 | } | |
8350 | ||
2b4424c3 TT |
8351 | \f |
8352 | ||
8353 | /* Implement the type_align gdbarch function. */ | |
8354 | ||
8355 | static ULONGEST | |
8356 | i386_type_align (struct gdbarch *gdbarch, struct type *type) | |
8357 | { | |
8358 | type = check_typedef (type); | |
8359 | ||
8360 | if (gdbarch_ptr_bit (gdbarch) == 32) | |
8361 | { | |
78134374 SM |
8362 | if ((type->code () == TYPE_CODE_INT |
8363 | || type->code () == TYPE_CODE_FLT) | |
2b4424c3 TT |
8364 | && TYPE_LENGTH (type) > 4) |
8365 | return 4; | |
8366 | ||
8367 | /* Handle x86's funny long double. */ | |
78134374 | 8368 | if (type->code () == TYPE_CODE_FLT |
2b4424c3 TT |
8369 | && gdbarch_long_double_bit (gdbarch) == TYPE_LENGTH (type) * 8) |
8370 | return 4; | |
8371 | } | |
8372 | ||
5561fc30 | 8373 | return 0; |
2b4424c3 TT |
8374 | } |
8375 | ||
7ad10968 | 8376 | \f |
ad9eb1fd DE |
8377 | /* Note: This is called for both i386 and amd64. */ |
8378 | ||
7ad10968 HZ |
8379 | static struct gdbarch * |
8380 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8381 | { | |
8382 | struct gdbarch_tdep *tdep; | |
8383 | struct gdbarch *gdbarch; | |
90884b2b | 8384 | const struct target_desc *tdesc; |
1ba53b71 | 8385 | int mm0_regnum; |
c131fcee | 8386 | int ymm0_regnum; |
1dbcd68c WT |
8387 | int bnd0_regnum; |
8388 | int num_bnd_cooked; | |
7ad10968 HZ |
8389 | |
8390 | /* If there is already a candidate, use it. */ | |
8391 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
8392 | if (arches != NULL) | |
8393 | return arches->gdbarch; | |
8394 | ||
ad9eb1fd | 8395 | /* Allocate space for the new architecture. Assume i386 for now. */ |
fc270c35 | 8396 | tdep = XCNEW (struct gdbarch_tdep); |
7ad10968 HZ |
8397 | gdbarch = gdbarch_alloc (&info, tdep); |
8398 | ||
8399 | /* General-purpose registers. */ | |
7ad10968 HZ |
8400 | tdep->gregset_reg_offset = NULL; |
8401 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
8402 | tdep->sizeof_gregset = 0; | |
8403 | ||
8404 | /* Floating-point registers. */ | |
7ad10968 | 8405 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
8f0435f7 | 8406 | tdep->fpregset = &i386_fpregset; |
7ad10968 HZ |
8407 | |
8408 | /* The default settings include the FPU registers, the MMX registers | |
8409 | and the SSE registers. This can be overridden for a specific ABI | |
8410 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
8411 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 8412 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
8413 | |
8414 | tdep->st0_regnum = I386_ST0_REGNUM; | |
8415 | ||
7ad10968 HZ |
8416 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
8417 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
8418 | ||
8419 | tdep->jb_pc_offset = -1; | |
8420 | tdep->struct_return = pcc_struct_return; | |
8421 | tdep->sigtramp_start = 0; | |
8422 | tdep->sigtramp_end = 0; | |
8423 | tdep->sigtramp_p = i386_sigtramp_p; | |
8424 | tdep->sigcontext_addr = NULL; | |
8425 | tdep->sc_reg_offset = NULL; | |
8426 | tdep->sc_pc_offset = -1; | |
8427 | tdep->sc_sp_offset = -1; | |
8428 | ||
c131fcee L |
8429 | tdep->xsave_xcr0_offset = -1; |
8430 | ||
cf648174 HZ |
8431 | tdep->record_regmap = i386_record_regmap; |
8432 | ||
2b4424c3 | 8433 | set_gdbarch_type_align (gdbarch, i386_type_align); |
205c306f | 8434 | |
7ad10968 HZ |
8435 | /* The format used for `long double' on almost all i386 targets is |
8436 | the i387 extended floating-point format. In fact, of all targets | |
8437 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
8438 | on having a `long double' that's not `long' at all. */ | |
8439 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
8440 | ||
8441 | /* Although the i387 extended floating-point has only 80 significant | |
8442 | bits, a `long double' actually takes up 96, probably to enforce | |
8443 | alignment. */ | |
8444 | set_gdbarch_long_double_bit (gdbarch, 96); | |
8445 | ||
2a67f09d FW |
8446 | /* Support of bfloat16 format. */ |
8447 | set_gdbarch_bfloat16_format (gdbarch, floatformats_bfloat16); | |
8448 | ||
00d5215e UW |
8449 | /* Support for floating-point data type variants. */ |
8450 | set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type); | |
8451 | ||
7ad10968 HZ |
8452 | /* Register numbers of various important registers. */ |
8453 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
8454 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
8455 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
8456 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
8457 | ||
8458 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
8459 | numbering schemes on the i386: dbx and SVR4. These schemes | |
8460 | differ in how they number %ebp, %esp, %eflags, and the | |
8461 | floating-point registers, and are implemented by the arrays | |
8462 | dbx_register_map[] and svr4_dbx_register_map in | |
8463 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
8464 | gcc/config/i386.c, which it designates as the "default" register | |
8465 | map used in 64bit mode. This last register numbering scheme is | |
8466 | implemented in dbx64_register_map, and is used for AMD64; see | |
8467 | amd64-tdep.c. | |
8468 | ||
8469 | Currently, each GCC i386 target always uses the same register | |
8470 | numbering scheme across all its supported debugging formats | |
8471 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
8472 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
8473 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
8474 | respective config header in a manner independent of the requested | |
8475 | output debugging format. | |
8476 | ||
8477 | This does not match the arrangement below, which presumes that | |
8478 | the SDB and stabs numbering schemes differ from the DWARF and | |
8479 | DWARF 2 ones. The reason for this arrangement is that it is | |
8480 | likely to get the numbering scheme for the target's | |
8481 | default/native debug format right. For targets where GCC is the | |
8482 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
8483 | targets where the native toolchain uses a different numbering | |
8484 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
8485 | the defaults below will have to be overridden, like | |
8486 | i386_elf_init_abi() does. */ | |
8487 | ||
8488 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
8489 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8490 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8491 | ||
8492 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
0fde2c53 | 8493 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum); |
7ad10968 HZ |
8494 | |
8495 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
8496 | be in use on any of the supported i386 targets. */ | |
8497 | ||
8498 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
8499 | ||
8500 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
8501 | ||
8502 | /* Call dummy code. */ | |
a9b8d892 JK |
8503 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8504 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 8505 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 8506 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
8507 | |
8508 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
8509 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
8510 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
8511 | ||
8512 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
8513 | ||
8514 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
8515 | ||
8516 | /* Stack grows downward. */ | |
8517 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8518 | ||
04180708 YQ |
8519 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc); |
8520 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind); | |
8521 | ||
7ad10968 HZ |
8522 | set_gdbarch_decr_pc_after_break (gdbarch, 1); |
8523 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
8524 | ||
8525 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
8526 | ||
7ad10968 HZ |
8527 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
8528 | ||
8529 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
8530 | ||
8531 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
8532 | ||
8533 | /* Add the i386 register groups. */ | |
8534 | i386_add_reggroups (gdbarch); | |
90884b2b | 8535 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 8536 | |
143985b7 AF |
8537 | /* Helper for function argument information. */ |
8538 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
8539 | ||
06da04c6 | 8540 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
8541 | appended to the list first, so that it supercedes the DWARF |
8542 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
8543 | currently fails). */ |
8544 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
8545 | ||
8546 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 8547 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 8548 | CFI info will be used if it is available. */ |
10458914 | 8549 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 8550 | |
acd5c798 | 8551 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 8552 | |
1ba53b71 | 8553 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
8554 | set_gdbarch_pseudo_register_read_value (gdbarch, |
8555 | i386_pseudo_register_read_value); | |
90884b2b | 8556 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
62e5fd57 MK |
8557 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8558 | i386_ax_pseudo_register_collect); | |
90884b2b L |
8559 | |
8560 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
8561 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
8562 | ||
c131fcee L |
8563 | /* Override the normal target description method to make the AVX |
8564 | upper halves anonymous. */ | |
8565 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
8566 | ||
8567 | /* Even though the default ABI only includes general-purpose registers, | |
8568 | floating-point registers and the SSE registers, we have to leave a | |
01f9f808 | 8569 | gap for the upper AVX, MPX and AVX512 registers. */ |
1163a4b7 | 8570 | set_gdbarch_num_regs (gdbarch, I386_NUM_REGS); |
90884b2b | 8571 | |
ac04f72b TT |
8572 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); |
8573 | ||
90884b2b L |
8574 | /* Get the x86 target description from INFO. */ |
8575 | tdesc = info.target_desc; | |
8576 | if (! tdesc_has_registers (tdesc)) | |
1163a4b7 | 8577 | tdesc = i386_target_description (X86_XSTATE_SSE_MASK, false); |
90884b2b L |
8578 | tdep->tdesc = tdesc; |
8579 | ||
8580 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
8581 | tdep->register_names = i386_register_names; | |
8582 | ||
c131fcee L |
8583 | /* No upper YMM registers. */ |
8584 | tdep->ymmh_register_names = NULL; | |
8585 | tdep->ymm0h_regnum = -1; | |
8586 | ||
01f9f808 MS |
8587 | /* No upper ZMM registers. */ |
8588 | tdep->zmmh_register_names = NULL; | |
8589 | tdep->zmm0h_regnum = -1; | |
8590 | ||
8591 | /* No high XMM registers. */ | |
8592 | tdep->xmm_avx512_register_names = NULL; | |
8593 | tdep->xmm16_regnum = -1; | |
8594 | ||
8595 | /* No upper YMM16-31 registers. */ | |
8596 | tdep->ymm16h_register_names = NULL; | |
8597 | tdep->ymm16h_regnum = -1; | |
8598 | ||
1ba53b71 L |
8599 | tdep->num_byte_regs = 8; |
8600 | tdep->num_word_regs = 8; | |
8601 | tdep->num_dword_regs = 0; | |
8602 | tdep->num_mmx_regs = 8; | |
c131fcee | 8603 | tdep->num_ymm_regs = 0; |
1ba53b71 | 8604 | |
1dbcd68c WT |
8605 | /* No MPX registers. */ |
8606 | tdep->bnd0r_regnum = -1; | |
8607 | tdep->bndcfgu_regnum = -1; | |
8608 | ||
01f9f808 MS |
8609 | /* No AVX512 registers. */ |
8610 | tdep->k0_regnum = -1; | |
8611 | tdep->num_zmm_regs = 0; | |
8612 | tdep->num_ymm_avx512_regs = 0; | |
8613 | tdep->num_xmm_avx512_regs = 0; | |
8614 | ||
51547df6 MS |
8615 | /* No PKEYS registers */ |
8616 | tdep->pkru_regnum = -1; | |
8617 | tdep->num_pkeys_regs = 0; | |
8618 | ||
1163a4b7 JB |
8619 | /* No segment base registers. */ |
8620 | tdep->fsbase_regnum = -1; | |
8621 | ||
c1e1314d | 8622 | tdesc_arch_data_up tdesc_data = tdesc_data_alloc (); |
90884b2b | 8623 | |
dde08ee1 PA |
8624 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
8625 | ||
6710bf39 SS |
8626 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
8627 | ||
c2170eef MM |
8628 | set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); |
8629 | set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); | |
8630 | set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); | |
8631 | ||
ad9eb1fd DE |
8632 | /* Hook in ABI-specific overrides, if they have been registered. |
8633 | Note: If INFO specifies a 64 bit arch, this is where we turn | |
8634 | a 32-bit i386 into a 64-bit amd64. */ | |
c1e1314d | 8635 | info.tdesc_data = tdesc_data.get (); |
4be87837 | 8636 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 8637 | |
c1e1314d | 8638 | if (!i386_validate_tdesc_p (tdep, tdesc_data.get ())) |
c131fcee | 8639 | { |
c131fcee L |
8640 | xfree (tdep); |
8641 | gdbarch_free (gdbarch); | |
8642 | return NULL; | |
8643 | } | |
8644 | ||
1dbcd68c WT |
8645 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
8646 | ||
1ba53b71 L |
8647 | /* Wire in pseudo registers. Number of pseudo registers may be |
8648 | changed. */ | |
8649 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8650 | + tdep->num_word_regs | |
8651 | + tdep->num_dword_regs | |
c131fcee | 8652 | + tdep->num_mmx_regs |
1dbcd68c | 8653 | + tdep->num_ymm_regs |
01f9f808 MS |
8654 | + num_bnd_cooked |
8655 | + tdep->num_ymm_avx512_regs | |
8656 | + tdep->num_zmm_regs)); | |
1ba53b71 | 8657 | |
90884b2b L |
8658 | /* Target description may be changed. */ |
8659 | tdesc = tdep->tdesc; | |
8660 | ||
c1e1314d | 8661 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); |
90884b2b L |
8662 | |
8663 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8664 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8665 | ||
1ba53b71 L |
8666 | /* Make %al the first pseudo-register. */ |
8667 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8668 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8669 | ||
c131fcee | 8670 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8671 | if (tdep->num_dword_regs) |
8672 | { | |
1c6272a6 | 8673 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8674 | tdep->eax_regnum = ymm0_regnum; |
8675 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8676 | } |
8677 | else | |
8678 | tdep->eax_regnum = -1; | |
8679 | ||
c131fcee L |
8680 | mm0_regnum = ymm0_regnum; |
8681 | if (tdep->num_ymm_regs) | |
8682 | { | |
1c6272a6 | 8683 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8684 | tdep->ymm0_regnum = ymm0_regnum; |
8685 | mm0_regnum += tdep->num_ymm_regs; | |
8686 | } | |
8687 | else | |
8688 | tdep->ymm0_regnum = -1; | |
8689 | ||
01f9f808 MS |
8690 | if (tdep->num_ymm_avx512_regs) |
8691 | { | |
8692 | /* Support YMM16-31 pseudo registers if available. */ | |
8693 | tdep->ymm16_regnum = mm0_regnum; | |
8694 | mm0_regnum += tdep->num_ymm_avx512_regs; | |
8695 | } | |
8696 | else | |
8697 | tdep->ymm16_regnum = -1; | |
8698 | ||
8699 | if (tdep->num_zmm_regs) | |
8700 | { | |
8701 | /* Support ZMM pseudo-register if it is available. */ | |
8702 | tdep->zmm0_regnum = mm0_regnum; | |
8703 | mm0_regnum += tdep->num_zmm_regs; | |
8704 | } | |
8705 | else | |
8706 | tdep->zmm0_regnum = -1; | |
8707 | ||
1dbcd68c | 8708 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8709 | if (tdep->num_mmx_regs != 0) |
8710 | { | |
1c6272a6 | 8711 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8712 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8713 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8714 | } |
8715 | else | |
8716 | tdep->mm0_regnum = -1; | |
8717 | ||
1dbcd68c WT |
8718 | if (tdep->bnd0r_regnum > 0) |
8719 | tdep->bnd0_regnum = bnd0_regnum; | |
8720 | else | |
8721 | tdep-> bnd0_regnum = -1; | |
8722 | ||
06da04c6 | 8723 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 8724 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
8725 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
8726 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 8727 | |
8446b36a MK |
8728 | /* If we have a register mapping, enable the generic core file |
8729 | support, unless it has already been enabled. */ | |
8730 | if (tdep->gregset_reg_offset | |
8f0435f7 | 8731 | && !gdbarch_iterate_over_regset_sections_p (gdbarch)) |
490496c3 AA |
8732 | set_gdbarch_iterate_over_regset_sections |
8733 | (gdbarch, i386_iterate_over_regset_sections); | |
8446b36a | 8734 | |
7a697b8d SS |
8735 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8736 | i386_fast_tracepoint_valid_at); | |
8737 | ||
a62cc96e AC |
8738 | return gdbarch; |
8739 | } | |
8740 | ||
8201327c MK |
8741 | \f |
8742 | ||
97de3545 JB |
8743 | /* Return the target description for a specified XSAVE feature mask. */ |
8744 | ||
8745 | const struct target_desc * | |
1163a4b7 | 8746 | i386_target_description (uint64_t xcr0, bool segments) |
97de3545 | 8747 | { |
22916b07 | 8748 | static target_desc *i386_tdescs \ |
1163a4b7 | 8749 | [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {}; |
22916b07 YQ |
8750 | target_desc **tdesc; |
8751 | ||
8752 | tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0] | |
8753 | [(xcr0 & X86_XSTATE_AVX) ? 1 : 0] | |
8754 | [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] | |
8755 | [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] | |
1163a4b7 JB |
8756 | [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0] |
8757 | [segments ? 1 : 0]; | |
22916b07 YQ |
8758 | |
8759 | if (*tdesc == NULL) | |
1163a4b7 | 8760 | *tdesc = i386_create_target_description (xcr0, false, segments); |
22916b07 YQ |
8761 | |
8762 | return *tdesc; | |
97de3545 JB |
8763 | } |
8764 | ||
29c1c244 WT |
8765 | #define MPX_BASE_MASK (~(ULONGEST) 0xfff) |
8766 | ||
8767 | /* Find the bound directory base address. */ | |
8768 | ||
8769 | static unsigned long | |
8770 | i386_mpx_bd_base (void) | |
8771 | { | |
8772 | struct regcache *rcache; | |
8773 | struct gdbarch_tdep *tdep; | |
8774 | ULONGEST ret; | |
8775 | enum register_status regstatus; | |
29c1c244 WT |
8776 | |
8777 | rcache = get_current_regcache (); | |
ac7936df | 8778 | tdep = gdbarch_tdep (rcache->arch ()); |
29c1c244 WT |
8779 | |
8780 | regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret); | |
8781 | ||
8782 | if (regstatus != REG_VALID) | |
8783 | error (_("BNDCFGU register invalid, read status %d."), regstatus); | |
8784 | ||
8785 | return ret & MPX_BASE_MASK; | |
8786 | } | |
8787 | ||
012b3a21 | 8788 | int |
29c1c244 WT |
8789 | i386_mpx_enabled (void) |
8790 | { | |
8791 | const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ()); | |
8792 | const struct target_desc *tdesc = tdep->tdesc; | |
8793 | ||
8794 | return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL); | |
8795 | } | |
8796 | ||
8797 | #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */ | |
8798 | #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */ | |
8799 | #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */ | |
8800 | #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */ | |
8801 | ||
8802 | /* Find the bound table entry given the pointer location and the base | |
8803 | address of the table. */ | |
8804 | ||
8805 | static CORE_ADDR | |
8806 | i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base) | |
8807 | { | |
8808 | CORE_ADDR offset1; | |
8809 | CORE_ADDR offset2; | |
8810 | CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift; | |
8811 | CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift; | |
8812 | CORE_ADDR bd_entry_addr; | |
8813 | CORE_ADDR bt_addr; | |
8814 | CORE_ADDR bd_entry; | |
8815 | struct gdbarch *gdbarch = get_current_arch (); | |
8816 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8817 | ||
8818 | ||
8819 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8820 | { | |
966f0aef | 8821 | mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK; |
29c1c244 WT |
8822 | bd_ptr_r_shift = 20; |
8823 | bd_ptr_l_shift = 3; | |
8824 | bt_select_r_shift = 3; | |
8825 | bt_select_l_shift = 5; | |
966f0aef WT |
8826 | bt_mask = (CORE_ADDR) MPX_BT_MASK; |
8827 | ||
8828 | if ( sizeof (CORE_ADDR) == 4) | |
e00b3c9b WT |
8829 | error (_("bound table examination not supported\ |
8830 | for 64-bit process with 32-bit GDB")); | |
29c1c244 WT |
8831 | } |
8832 | else | |
8833 | { | |
8834 | mpx_bd_mask = MPX_BD_MASK_32; | |
8835 | bd_ptr_r_shift = 12; | |
8836 | bd_ptr_l_shift = 2; | |
8837 | bt_select_r_shift = 2; | |
8838 | bt_select_l_shift = 4; | |
8839 | bt_mask = MPX_BT_MASK_32; | |
8840 | } | |
8841 | ||
8842 | offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift; | |
8843 | bd_entry_addr = bd_base + offset1; | |
8844 | bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type); | |
8845 | ||
8846 | if ((bd_entry & 0x1) == 0) | |
8847 | error (_("Invalid bounds directory entry at %s."), | |
8848 | paddress (get_current_arch (), bd_entry_addr)); | |
8849 | ||
8850 | /* Clearing status bit. */ | |
8851 | bd_entry--; | |
8852 | bt_addr = bd_entry & ~bt_select_r_shift; | |
8853 | offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift; | |
8854 | ||
8855 | return bt_addr + offset2; | |
8856 | } | |
8857 | ||
8858 | /* Print routine for the mpx bounds. */ | |
8859 | ||
8860 | static void | |
8861 | i386_mpx_print_bounds (const CORE_ADDR bt_entry[4]) | |
8862 | { | |
8863 | struct ui_out *uiout = current_uiout; | |
34f8ac9f | 8864 | LONGEST size; |
29c1c244 WT |
8865 | struct gdbarch *gdbarch = get_current_arch (); |
8866 | CORE_ADDR onecompl = ~((CORE_ADDR) 0); | |
8867 | int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0); | |
8868 | ||
8869 | if (bounds_in_map == 1) | |
8870 | { | |
112e8700 SM |
8871 | uiout->text ("Null bounds on map:"); |
8872 | uiout->text (" pointer value = "); | |
8873 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
8874 | uiout->text ("."); | |
8875 | uiout->text ("\n"); | |
29c1c244 WT |
8876 | } |
8877 | else | |
8878 | { | |
112e8700 SM |
8879 | uiout->text ("{lbound = "); |
8880 | uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]); | |
8881 | uiout->text (", ubound = "); | |
29c1c244 WT |
8882 | |
8883 | /* The upper bound is stored in 1's complement. */ | |
112e8700 SM |
8884 | uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]); |
8885 | uiout->text ("}: pointer value = "); | |
8886 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
29c1c244 WT |
8887 | |
8888 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8889 | size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]); | |
8890 | else | |
8891 | size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]); | |
8892 | ||
8893 | /* In case the bounds are 0x0 and 0xffff... the difference will be -1. | |
8894 | -1 represents in this sense full memory access, and there is no need | |
8895 | one to the size. */ | |
8896 | ||
8897 | size = (size > -1 ? size + 1 : size); | |
112e8700 | 8898 | uiout->text (", size = "); |
33eca680 | 8899 | uiout->field_string ("size", plongest (size)); |
29c1c244 | 8900 | |
112e8700 SM |
8901 | uiout->text (", metadata = "); |
8902 | uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]); | |
8903 | uiout->text ("\n"); | |
29c1c244 WT |
8904 | } |
8905 | } | |
8906 | ||
8907 | /* Implement the command "show mpx bound". */ | |
8908 | ||
8909 | static void | |
c4a3e68e | 8910 | i386_mpx_info_bounds (const char *args, int from_tty) |
29c1c244 WT |
8911 | { |
8912 | CORE_ADDR bd_base = 0; | |
8913 | CORE_ADDR addr; | |
8914 | CORE_ADDR bt_entry_addr = 0; | |
8915 | CORE_ADDR bt_entry[4]; | |
8916 | int i; | |
8917 | struct gdbarch *gdbarch = get_current_arch (); | |
8918 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8919 | ||
ae71e7b5 MR |
8920 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8921 | || !i386_mpx_enabled ()) | |
118ca224 | 8922 | { |
bc504a31 | 8923 | printf_unfiltered (_("Intel Memory Protection Extensions not " |
118ca224 PP |
8924 | "supported on this target.\n")); |
8925 | return; | |
8926 | } | |
29c1c244 WT |
8927 | |
8928 | if (args == NULL) | |
118ca224 PP |
8929 | { |
8930 | printf_unfiltered (_("Address of pointer variable expected.\n")); | |
8931 | return; | |
8932 | } | |
29c1c244 WT |
8933 | |
8934 | addr = parse_and_eval_address (args); | |
8935 | ||
8936 | bd_base = i386_mpx_bd_base (); | |
8937 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8938 | ||
8939 | memset (bt_entry, 0, sizeof (bt_entry)); | |
8940 | ||
8941 | for (i = 0; i < 4; i++) | |
8942 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 8943 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
8944 | data_ptr_type); |
8945 | ||
8946 | i386_mpx_print_bounds (bt_entry); | |
8947 | } | |
8948 | ||
8949 | /* Implement the command "set mpx bound". */ | |
8950 | ||
8951 | static void | |
c4a3e68e | 8952 | i386_mpx_set_bounds (const char *args, int from_tty) |
29c1c244 WT |
8953 | { |
8954 | CORE_ADDR bd_base = 0; | |
8955 | CORE_ADDR addr, lower, upper; | |
8956 | CORE_ADDR bt_entry_addr = 0; | |
8957 | CORE_ADDR bt_entry[2]; | |
8958 | const char *input = args; | |
8959 | int i; | |
8960 | struct gdbarch *gdbarch = get_current_arch (); | |
8961 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8962 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8963 | ||
ae71e7b5 MR |
8964 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8965 | || !i386_mpx_enabled ()) | |
bc504a31 | 8966 | error (_("Intel Memory Protection Extensions not supported\ |
29c1c244 WT |
8967 | on this target.")); |
8968 | ||
8969 | if (args == NULL) | |
8970 | error (_("Pointer value expected.")); | |
8971 | ||
8972 | addr = value_as_address (parse_to_comma_and_eval (&input)); | |
8973 | ||
8974 | if (input[0] == ',') | |
8975 | ++input; | |
8976 | if (input[0] == '\0') | |
8977 | error (_("wrong number of arguments: missing lower and upper bound.")); | |
8978 | lower = value_as_address (parse_to_comma_and_eval (&input)); | |
8979 | ||
8980 | if (input[0] == ',') | |
8981 | ++input; | |
8982 | if (input[0] == '\0') | |
8983 | error (_("Wrong number of arguments; Missing upper bound.")); | |
8984 | upper = value_as_address (parse_to_comma_and_eval (&input)); | |
8985 | ||
8986 | bd_base = i386_mpx_bd_base (); | |
8987 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8988 | for (i = 0; i < 2; i++) | |
8989 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 8990 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
8991 | data_ptr_type); |
8992 | bt_entry[0] = (uint64_t) lower; | |
8993 | bt_entry[1] = ~(uint64_t) upper; | |
8994 | ||
8995 | for (i = 0; i < 2; i++) | |
132874d7 AB |
8996 | write_memory_unsigned_integer (bt_entry_addr |
8997 | + i * TYPE_LENGTH (data_ptr_type), | |
8998 | TYPE_LENGTH (data_ptr_type), byte_order, | |
29c1c244 WT |
8999 | bt_entry[i]); |
9000 | } | |
9001 | ||
9002 | static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist; | |
9003 | ||
6c265988 | 9004 | void _initialize_i386_tdep (); |
c906108c | 9005 | void |
6c265988 | 9006 | _initialize_i386_tdep () |
c906108c | 9007 | { |
a62cc96e AC |
9008 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
9009 | ||
fc338970 | 9010 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
9011 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
9012 | &disassembly_flavor, _("\ | |
9013 | Set the disassembly flavor."), _("\ | |
9014 | Show the disassembly flavor."), _("\ | |
9015 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
9016 | NULL, | |
9017 | NULL, /* FIXME: i18n: */ | |
9018 | &setlist, &showlist); | |
8201327c MK |
9019 | |
9020 | /* Add the variable that controls the convention for returning | |
9021 | structs. */ | |
7ab04401 AC |
9022 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
9023 | &struct_convention, _("\ | |
9024 | Set the convention for returning small structs."), _("\ | |
9025 | Show the convention for returning small structs."), _("\ | |
9026 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
9027 | is \"default\"."), | |
9028 | NULL, | |
9029 | NULL, /* FIXME: i18n: */ | |
9030 | &setlist, &showlist); | |
8201327c | 9031 | |
29c1c244 WT |
9032 | /* Add "mpx" prefix for the set commands. */ |
9033 | ||
0743fc83 | 9034 | add_basic_prefix_cmd ("mpx", class_support, _("\ |
bc504a31 | 9035 | Set Intel Memory Protection Extensions specific variables."), |
2f822da5 | 9036 | &mpx_set_cmdlist, |
0743fc83 | 9037 | 0 /* allow-unknown */, &setlist); |
29c1c244 WT |
9038 | |
9039 | /* Add "mpx" prefix for the show commands. */ | |
9040 | ||
0743fc83 | 9041 | add_show_prefix_cmd ("mpx", class_support, _("\ |
bc504a31 | 9042 | Show Intel Memory Protection Extensions specific variables."), |
2f822da5 | 9043 | &mpx_show_cmdlist, |
0743fc83 | 9044 | 0 /* allow-unknown */, &showlist); |
29c1c244 WT |
9045 | |
9046 | /* Add "bound" command for the show mpx commands list. */ | |
9047 | ||
9048 | add_cmd ("bound", no_class, i386_mpx_info_bounds, | |
9049 | "Show the memory bounds for a given array/pointer storage\ | |
9050 | in the bound table.", | |
9051 | &mpx_show_cmdlist); | |
9052 | ||
9053 | /* Add "bound" command for the set mpx commands list. */ | |
9054 | ||
9055 | add_cmd ("bound", no_class, i386_mpx_set_bounds, | |
9056 | "Set the memory bounds for a given array/pointer storage\ | |
9057 | in the bound table.", | |
9058 | &mpx_set_cmdlist); | |
9059 | ||
05816f70 | 9060 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 9061 | i386_svr4_init_abi); |
38c968cf | 9062 | |
209bd28e | 9063 | /* Initialize the i386-specific register groups. */ |
38c968cf | 9064 | i386_init_reggroups (); |
90884b2b | 9065 | |
c8d5aac9 L |
9066 | /* Tell remote stub that we support XML target description. */ |
9067 | register_remote_support_xml ("i386"); | |
c906108c | 9068 | } |