Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
28e7fd62 | 3 | Copyright (C) 1988-2013 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
acd5c798 | 31 | #include "gdbcmd.h" |
c906108c | 32 | #include "gdbcore.h" |
e6bb342a | 33 | #include "gdbtypes.h" |
dfe01d39 | 34 | #include "objfiles.h" |
acd5c798 MK |
35 | #include "osabi.h" |
36 | #include "regcache.h" | |
37 | #include "reggroups.h" | |
473f17b0 | 38 | #include "regset.h" |
c0d1d883 | 39 | #include "symfile.h" |
c906108c | 40 | #include "symtab.h" |
acd5c798 | 41 | #include "target.h" |
fd0407d6 | 42 | #include "value.h" |
a89aa300 | 43 | #include "dis-asm.h" |
7a697b8d | 44 | #include "disasm.h" |
c8d5aac9 | 45 | #include "remote.h" |
8fbca658 | 46 | #include "exceptions.h" |
3d261580 | 47 | #include "gdb_assert.h" |
0e9f083f | 48 | #include <string.h> |
3d261580 | 49 | |
d2a7c97a | 50 | #include "i386-tdep.h" |
61113f8b | 51 | #include "i387-tdep.h" |
c131fcee | 52 | #include "i386-xstate.h" |
d2a7c97a | 53 | |
7ad10968 | 54 | #include "record.h" |
d02ed0bb | 55 | #include "record-full.h" |
7ad10968 HZ |
56 | #include <stdint.h> |
57 | ||
90884b2b | 58 | #include "features/i386/i386.c" |
c131fcee | 59 | #include "features/i386/i386-avx.c" |
1dbcd68c | 60 | #include "features/i386/i386-mpx.c" |
3a13a53b | 61 | #include "features/i386/i386-mmx.c" |
90884b2b | 62 | |
6710bf39 SS |
63 | #include "ax.h" |
64 | #include "ax-gdb.h" | |
65 | ||
55aa24fb SDJ |
66 | #include "stap-probe.h" |
67 | #include "user-regs.h" | |
68 | #include "cli/cli-utils.h" | |
69 | #include "expression.h" | |
70 | #include "parser-defs.h" | |
71 | #include <ctype.h> | |
72 | ||
c4fc7f1b | 73 | /* Register names. */ |
c40e1eab | 74 | |
90884b2b | 75 | static const char *i386_register_names[] = |
fc633446 MK |
76 | { |
77 | "eax", "ecx", "edx", "ebx", | |
78 | "esp", "ebp", "esi", "edi", | |
79 | "eip", "eflags", "cs", "ss", | |
80 | "ds", "es", "fs", "gs", | |
81 | "st0", "st1", "st2", "st3", | |
82 | "st4", "st5", "st6", "st7", | |
83 | "fctrl", "fstat", "ftag", "fiseg", | |
84 | "fioff", "foseg", "fooff", "fop", | |
85 | "xmm0", "xmm1", "xmm2", "xmm3", | |
86 | "xmm4", "xmm5", "xmm6", "xmm7", | |
87 | "mxcsr" | |
88 | }; | |
89 | ||
c131fcee L |
90 | static const char *i386_ymm_names[] = |
91 | { | |
92 | "ymm0", "ymm1", "ymm2", "ymm3", | |
93 | "ymm4", "ymm5", "ymm6", "ymm7", | |
94 | }; | |
95 | ||
96 | static const char *i386_ymmh_names[] = | |
97 | { | |
98 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
99 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
100 | }; | |
101 | ||
1dbcd68c WT |
102 | static const char *i386_mpx_names[] = |
103 | { | |
104 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
105 | }; | |
106 | ||
107 | /* Register names for MPX pseudo-registers. */ | |
108 | ||
109 | static const char *i386_bnd_names[] = | |
110 | { | |
111 | "bnd0", "bnd1", "bnd2", "bnd3" | |
112 | }; | |
113 | ||
c4fc7f1b | 114 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 115 | |
90884b2b | 116 | static const char *i386_mmx_names[] = |
28fc6740 AC |
117 | { |
118 | "mm0", "mm1", "mm2", "mm3", | |
119 | "mm4", "mm5", "mm6", "mm7" | |
120 | }; | |
c40e1eab | 121 | |
1ba53b71 L |
122 | /* Register names for byte pseudo-registers. */ |
123 | ||
124 | static const char *i386_byte_names[] = | |
125 | { | |
126 | "al", "cl", "dl", "bl", | |
127 | "ah", "ch", "dh", "bh" | |
128 | }; | |
129 | ||
130 | /* Register names for word pseudo-registers. */ | |
131 | ||
132 | static const char *i386_word_names[] = | |
133 | { | |
134 | "ax", "cx", "dx", "bx", | |
9cad29ac | 135 | "", "bp", "si", "di" |
1ba53b71 L |
136 | }; |
137 | ||
138 | /* MMX register? */ | |
c40e1eab | 139 | |
28fc6740 | 140 | static int |
5716833c | 141 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 142 | { |
1ba53b71 L |
143 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
144 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
145 | |
146 | if (mm0_regnum < 0) | |
147 | return 0; | |
148 | ||
1ba53b71 L |
149 | regnum -= mm0_regnum; |
150 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
151 | } | |
152 | ||
153 | /* Byte register? */ | |
154 | ||
155 | int | |
156 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
157 | { | |
158 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
159 | ||
160 | regnum -= tdep->al_regnum; | |
161 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
162 | } | |
163 | ||
164 | /* Word register? */ | |
165 | ||
166 | int | |
167 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
168 | { | |
169 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
170 | ||
171 | regnum -= tdep->ax_regnum; | |
172 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
173 | } | |
174 | ||
175 | /* Dword register? */ | |
176 | ||
177 | int | |
178 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
179 | { | |
180 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
181 | int eax_regnum = tdep->eax_regnum; | |
182 | ||
183 | if (eax_regnum < 0) | |
184 | return 0; | |
185 | ||
186 | regnum -= eax_regnum; | |
187 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
188 | } |
189 | ||
9191d390 | 190 | static int |
c131fcee L |
191 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
192 | { | |
193 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
194 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
195 | ||
196 | if (ymm0h_regnum < 0) | |
197 | return 0; | |
198 | ||
199 | regnum -= ymm0h_regnum; | |
200 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
201 | } | |
202 | ||
203 | /* AVX register? */ | |
204 | ||
205 | int | |
206 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
207 | { | |
208 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
209 | int ymm0_regnum = tdep->ymm0_regnum; | |
210 | ||
211 | if (ymm0_regnum < 0) | |
212 | return 0; | |
213 | ||
214 | regnum -= ymm0_regnum; | |
215 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
216 | } | |
217 | ||
1dbcd68c WT |
218 | /* BND register? */ |
219 | ||
220 | int | |
221 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
222 | { | |
223 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
224 | int bnd0_regnum = tdep->bnd0_regnum; | |
225 | ||
226 | if (bnd0_regnum < 0) | |
227 | return 0; | |
228 | ||
229 | regnum -= bnd0_regnum; | |
230 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
231 | } | |
232 | ||
5716833c | 233 | /* SSE register? */ |
23a34459 | 234 | |
c131fcee L |
235 | int |
236 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 237 | { |
5716833c | 238 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 239 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 240 | |
c131fcee | 241 | if (num_xmm_regs == 0) |
5716833c MK |
242 | return 0; |
243 | ||
c131fcee L |
244 | regnum -= I387_XMM0_REGNUM (tdep); |
245 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
246 | } |
247 | ||
5716833c MK |
248 | static int |
249 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 250 | { |
5716833c MK |
251 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
252 | ||
20a6ec49 | 253 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
254 | return 0; |
255 | ||
20a6ec49 | 256 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
257 | } |
258 | ||
5716833c | 259 | /* FP register? */ |
23a34459 AC |
260 | |
261 | int | |
20a6ec49 | 262 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 263 | { |
20a6ec49 MD |
264 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
265 | ||
266 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
267 | return 0; |
268 | ||
20a6ec49 MD |
269 | return (I387_ST0_REGNUM (tdep) <= regnum |
270 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
271 | } |
272 | ||
273 | int | |
20a6ec49 | 274 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 275 | { |
20a6ec49 MD |
276 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
277 | ||
278 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
279 | return 0; |
280 | ||
20a6ec49 MD |
281 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
282 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
283 | } |
284 | ||
1dbcd68c WT |
285 | /* BNDr (raw) register? */ |
286 | ||
287 | static int | |
288 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
289 | { | |
290 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
291 | ||
292 | if (I387_BND0R_REGNUM (tdep) < 0) | |
293 | return 0; | |
294 | ||
295 | regnum -= tdep->bnd0r_regnum; | |
296 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
297 | } | |
298 | ||
299 | /* BND control register? */ | |
300 | ||
301 | static int | |
302 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
303 | { | |
304 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
305 | ||
306 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
307 | return 0; | |
308 | ||
309 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
310 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
311 | } | |
312 | ||
c131fcee L |
313 | /* Return the name of register REGNUM, or the empty string if it is |
314 | an anonymous register. */ | |
315 | ||
316 | static const char * | |
317 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
318 | { | |
319 | /* Hide the upper YMM registers. */ | |
320 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
321 | return ""; | |
322 | ||
323 | return tdesc_register_name (gdbarch, regnum); | |
324 | } | |
325 | ||
30b0e2d8 | 326 | /* Return the name of register REGNUM. */ |
fc633446 | 327 | |
1ba53b71 | 328 | const char * |
90884b2b | 329 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 330 | { |
1ba53b71 | 331 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dbcd68c WT |
332 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
333 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
334 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
335 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
336 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
337 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
1ba53b71 L |
338 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
339 | return i386_byte_names[regnum - tdep->al_regnum]; | |
340 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
341 | return i386_word_names[regnum - tdep->ax_regnum]; | |
342 | ||
343 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
344 | } |
345 | ||
c4fc7f1b | 346 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
347 | number used by GDB. */ |
348 | ||
8201327c | 349 | static int |
d3f73121 | 350 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 351 | { |
20a6ec49 MD |
352 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
353 | ||
c4fc7f1b MK |
354 | /* This implements what GCC calls the "default" register map |
355 | (dbx_register_map[]). */ | |
356 | ||
85540d8c MK |
357 | if (reg >= 0 && reg <= 7) |
358 | { | |
9872ad24 JB |
359 | /* General-purpose registers. The debug info calls %ebp |
360 | register 4, and %esp register 5. */ | |
361 | if (reg == 4) | |
362 | return 5; | |
363 | else if (reg == 5) | |
364 | return 4; | |
365 | else return reg; | |
85540d8c MK |
366 | } |
367 | else if (reg >= 12 && reg <= 19) | |
368 | { | |
369 | /* Floating-point registers. */ | |
20a6ec49 | 370 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
371 | } |
372 | else if (reg >= 21 && reg <= 28) | |
373 | { | |
374 | /* SSE registers. */ | |
c131fcee L |
375 | int ymm0_regnum = tdep->ymm0_regnum; |
376 | ||
377 | if (ymm0_regnum >= 0 | |
378 | && i386_xmm_regnum_p (gdbarch, reg)) | |
379 | return reg - 21 + ymm0_regnum; | |
380 | else | |
381 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
382 | } |
383 | else if (reg >= 29 && reg <= 36) | |
384 | { | |
385 | /* MMX registers. */ | |
20a6ec49 | 386 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
387 | } |
388 | ||
389 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 390 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
391 | } |
392 | ||
c4fc7f1b MK |
393 | /* Convert SVR4 register number REG to the appropriate register number |
394 | used by GDB. */ | |
85540d8c | 395 | |
8201327c | 396 | static int |
d3f73121 | 397 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 398 | { |
20a6ec49 MD |
399 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
400 | ||
c4fc7f1b MK |
401 | /* This implements the GCC register map that tries to be compatible |
402 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
403 | ||
404 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
405 | numbers the floating point registers differently. */ |
406 | if (reg >= 0 && reg <= 9) | |
407 | { | |
acd5c798 | 408 | /* General-purpose registers. */ |
85540d8c MK |
409 | return reg; |
410 | } | |
411 | else if (reg >= 11 && reg <= 18) | |
412 | { | |
413 | /* Floating-point registers. */ | |
20a6ec49 | 414 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 415 | } |
c6f4c129 | 416 | else if (reg >= 21 && reg <= 36) |
85540d8c | 417 | { |
c4fc7f1b | 418 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 419 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
420 | } |
421 | ||
c6f4c129 JB |
422 | switch (reg) |
423 | { | |
20a6ec49 MD |
424 | case 37: return I387_FCTRL_REGNUM (tdep); |
425 | case 38: return I387_FSTAT_REGNUM (tdep); | |
426 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
427 | case 40: return I386_ES_REGNUM; |
428 | case 41: return I386_CS_REGNUM; | |
429 | case 42: return I386_SS_REGNUM; | |
430 | case 43: return I386_DS_REGNUM; | |
431 | case 44: return I386_FS_REGNUM; | |
432 | case 45: return I386_GS_REGNUM; | |
433 | } | |
434 | ||
85540d8c | 435 | /* This will hopefully provoke a warning. */ |
d3f73121 | 436 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 437 | } |
5716833c | 438 | |
fc338970 | 439 | \f |
917317f4 | 440 | |
fc338970 MK |
441 | /* This is the variable that is set with "set disassembly-flavor", and |
442 | its legitimate values. */ | |
53904c9e AC |
443 | static const char att_flavor[] = "att"; |
444 | static const char intel_flavor[] = "intel"; | |
40478521 | 445 | static const char *const valid_flavors[] = |
c5aa993b | 446 | { |
c906108c SS |
447 | att_flavor, |
448 | intel_flavor, | |
449 | NULL | |
450 | }; | |
53904c9e | 451 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 452 | \f |
c906108c | 453 | |
acd5c798 MK |
454 | /* Use the program counter to determine the contents and size of a |
455 | breakpoint instruction. Return a pointer to a string of bytes that | |
456 | encode a breakpoint instruction, store the length of the string in | |
457 | *LEN and optionally adjust *PC to point to the correct memory | |
458 | location for inserting the breakpoint. | |
c906108c | 459 | |
acd5c798 MK |
460 | On the i386 we have a single breakpoint that fits in a single byte |
461 | and can be inserted anywhere. | |
c906108c | 462 | |
acd5c798 | 463 | This function is 64-bit safe. */ |
63c0089f MK |
464 | |
465 | static const gdb_byte * | |
67d57894 | 466 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 467 | { |
63c0089f MK |
468 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
469 | ||
acd5c798 MK |
470 | *len = sizeof (break_insn); |
471 | return break_insn; | |
c906108c | 472 | } |
237fc4c9 PA |
473 | \f |
474 | /* Displaced instruction handling. */ | |
475 | ||
1903f0e6 DE |
476 | /* Skip the legacy instruction prefixes in INSN. |
477 | Not all prefixes are valid for any particular insn | |
478 | but we needn't care, the insn will fault if it's invalid. | |
479 | The result is a pointer to the first opcode byte, | |
480 | or NULL if we run off the end of the buffer. */ | |
481 | ||
482 | static gdb_byte * | |
483 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
484 | { | |
485 | gdb_byte *end = insn + max_len; | |
486 | ||
487 | while (insn < end) | |
488 | { | |
489 | switch (*insn) | |
490 | { | |
491 | case DATA_PREFIX_OPCODE: | |
492 | case ADDR_PREFIX_OPCODE: | |
493 | case CS_PREFIX_OPCODE: | |
494 | case DS_PREFIX_OPCODE: | |
495 | case ES_PREFIX_OPCODE: | |
496 | case FS_PREFIX_OPCODE: | |
497 | case GS_PREFIX_OPCODE: | |
498 | case SS_PREFIX_OPCODE: | |
499 | case LOCK_PREFIX_OPCODE: | |
500 | case REPE_PREFIX_OPCODE: | |
501 | case REPNE_PREFIX_OPCODE: | |
502 | ++insn; | |
503 | continue; | |
504 | default: | |
505 | return insn; | |
506 | } | |
507 | } | |
508 | ||
509 | return NULL; | |
510 | } | |
237fc4c9 PA |
511 | |
512 | static int | |
1903f0e6 | 513 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 514 | { |
1777feb0 | 515 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
516 | if (insn[0] == 0xea) |
517 | return 1; | |
518 | ||
519 | if (insn[0] == 0xff) | |
520 | { | |
1777feb0 | 521 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
522 | if ((insn[1] & 0x38) == 0x20) |
523 | return 1; | |
524 | ||
1777feb0 | 525 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
526 | if ((insn[1] & 0x38) == 0x28) |
527 | return 1; | |
528 | } | |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
533 | static int | |
1903f0e6 | 534 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 535 | { |
1777feb0 | 536 | /* call far, absolute. */ |
237fc4c9 PA |
537 | if (insn[0] == 0x9a) |
538 | return 1; | |
539 | ||
540 | if (insn[0] == 0xff) | |
541 | { | |
1777feb0 | 542 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
543 | if ((insn[1] & 0x38) == 0x10) |
544 | return 1; | |
545 | ||
1777feb0 | 546 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
547 | if ((insn[1] & 0x38) == 0x18) |
548 | return 1; | |
549 | } | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | static int | |
1903f0e6 | 555 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
556 | { |
557 | switch (insn[0]) | |
558 | { | |
1777feb0 | 559 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 560 | case 0xc3: /* ret near */ |
1777feb0 | 561 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
562 | case 0xcb: /* ret far */ |
563 | case 0xcf: /* iret */ | |
564 | return 1; | |
565 | ||
566 | default: | |
567 | return 0; | |
568 | } | |
569 | } | |
570 | ||
571 | static int | |
1903f0e6 | 572 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
573 | { |
574 | if (i386_absolute_call_p (insn)) | |
575 | return 1; | |
576 | ||
1777feb0 | 577 | /* call near, relative. */ |
237fc4c9 PA |
578 | if (insn[0] == 0xe8) |
579 | return 1; | |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
237fc4c9 PA |
584 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
585 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 586 | |
237fc4c9 | 587 | static int |
b55078be | 588 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 589 | { |
9a7f938f JK |
590 | /* Is it 'int $0x80'? */ |
591 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
592 | /* Or is it 'sysenter'? */ | |
593 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
594 | /* Or is it 'syscall'? */ | |
595 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
596 | { |
597 | *lengthp = 2; | |
598 | return 1; | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
b55078be DE |
604 | /* Some kernels may run one past a syscall insn, so we have to cope. |
605 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
606 | ||
607 | struct displaced_step_closure * | |
608 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
609 | CORE_ADDR from, CORE_ADDR to, | |
610 | struct regcache *regs) | |
611 | { | |
612 | size_t len = gdbarch_max_insn_length (gdbarch); | |
613 | gdb_byte *buf = xmalloc (len); | |
614 | ||
615 | read_memory (from, buf, len); | |
616 | ||
617 | /* GDB may get control back after the insn after the syscall. | |
618 | Presumably this is a kernel bug. | |
619 | If this is a syscall, make sure there's a nop afterwards. */ | |
620 | { | |
621 | int syscall_length; | |
622 | gdb_byte *insn; | |
623 | ||
624 | insn = i386_skip_prefixes (buf, len); | |
625 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
626 | insn[syscall_length] = NOP_OPCODE; | |
627 | } | |
628 | ||
629 | write_memory (to, buf, len); | |
630 | ||
631 | if (debug_displaced) | |
632 | { | |
633 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
634 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
635 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
636 | } | |
637 | ||
638 | return (struct displaced_step_closure *) buf; | |
639 | } | |
640 | ||
237fc4c9 PA |
641 | /* Fix up the state of registers and memory after having single-stepped |
642 | a displaced instruction. */ | |
1903f0e6 | 643 | |
237fc4c9 PA |
644 | void |
645 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
646 | struct displaced_step_closure *closure, | |
647 | CORE_ADDR from, CORE_ADDR to, | |
648 | struct regcache *regs) | |
649 | { | |
e17a4113 UW |
650 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
651 | ||
237fc4c9 PA |
652 | /* The offset we applied to the instruction's address. |
653 | This could well be negative (when viewed as a signed 32-bit | |
654 | value), but ULONGEST won't reflect that, so take care when | |
655 | applying it. */ | |
656 | ULONGEST insn_offset = to - from; | |
657 | ||
658 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
659 | copy of the instruction. */ | |
660 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
661 | /* The start of the insn, needed in case we see some prefixes. */ |
662 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
663 | |
664 | if (debug_displaced) | |
665 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 666 | "displaced: fixup (%s, %s), " |
237fc4c9 | 667 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
668 | paddress (gdbarch, from), paddress (gdbarch, to), |
669 | insn[0], insn[1]); | |
237fc4c9 PA |
670 | |
671 | /* The list of issues to contend with here is taken from | |
672 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
673 | Yay for Free Software! */ | |
674 | ||
675 | /* Relocate the %eip, if necessary. */ | |
676 | ||
1903f0e6 DE |
677 | /* The instruction recognizers we use assume any leading prefixes |
678 | have been skipped. */ | |
679 | { | |
680 | /* This is the size of the buffer in closure. */ | |
681 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
682 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
683 | /* If there are too many prefixes, just ignore the insn. | |
684 | It will fault when run. */ | |
685 | if (opcode != NULL) | |
686 | insn = opcode; | |
687 | } | |
688 | ||
237fc4c9 PA |
689 | /* Except in the case of absolute or indirect jump or call |
690 | instructions, or a return instruction, the new eip is relative to | |
691 | the displaced instruction; make it relative. Well, signal | |
692 | handler returns don't need relocation either, but we use the | |
693 | value of %eip to recognize those; see below. */ | |
694 | if (! i386_absolute_jmp_p (insn) | |
695 | && ! i386_absolute_call_p (insn) | |
696 | && ! i386_ret_p (insn)) | |
697 | { | |
698 | ULONGEST orig_eip; | |
b55078be | 699 | int insn_len; |
237fc4c9 PA |
700 | |
701 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
702 | ||
703 | /* A signal trampoline system call changes the %eip, resuming | |
704 | execution of the main program after the signal handler has | |
705 | returned. That makes them like 'return' instructions; we | |
706 | shouldn't relocate %eip. | |
707 | ||
708 | But most system calls don't, and we do need to relocate %eip. | |
709 | ||
710 | Our heuristic for distinguishing these cases: if stepping | |
711 | over the system call instruction left control directly after | |
712 | the instruction, the we relocate --- control almost certainly | |
713 | doesn't belong in the displaced copy. Otherwise, we assume | |
714 | the instruction has put control where it belongs, and leave | |
715 | it unrelocated. Goodness help us if there are PC-relative | |
716 | system calls. */ | |
717 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
718 | && orig_eip != to + (insn - insn_start) + insn_len |
719 | /* GDB can get control back after the insn after the syscall. | |
720 | Presumably this is a kernel bug. | |
721 | i386_displaced_step_copy_insn ensures its a nop, | |
722 | we add one to the length for it. */ | |
723 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
724 | { |
725 | if (debug_displaced) | |
726 | fprintf_unfiltered (gdb_stdlog, | |
727 | "displaced: syscall changed %%eip; " | |
728 | "not relocating\n"); | |
729 | } | |
730 | else | |
731 | { | |
732 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
733 | ||
1903f0e6 DE |
734 | /* If we just stepped over a breakpoint insn, we don't backup |
735 | the pc on purpose; this is to match behaviour without | |
736 | stepping. */ | |
237fc4c9 PA |
737 | |
738 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
739 | ||
740 | if (debug_displaced) | |
741 | fprintf_unfiltered (gdb_stdlog, | |
742 | "displaced: " | |
5af949e3 UW |
743 | "relocated %%eip from %s to %s\n", |
744 | paddress (gdbarch, orig_eip), | |
745 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
746 | } |
747 | } | |
748 | ||
749 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
750 | pushed value, and should be cleared. We'll leave this for later, | |
751 | since GDB already messes up the TF flag when stepping over a | |
752 | pushfl. */ | |
753 | ||
754 | /* If the instruction was a call, the return address now atop the | |
755 | stack is the address following the copied instruction. We need | |
756 | to make it the address following the original instruction. */ | |
757 | if (i386_call_p (insn)) | |
758 | { | |
759 | ULONGEST esp; | |
760 | ULONGEST retaddr; | |
761 | const ULONGEST retaddr_len = 4; | |
762 | ||
763 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 764 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 765 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 766 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
767 | |
768 | if (debug_displaced) | |
769 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
770 | "displaced: relocated return addr at %s to %s\n", |
771 | paddress (gdbarch, esp), | |
772 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
773 | } |
774 | } | |
dde08ee1 PA |
775 | |
776 | static void | |
777 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
778 | { | |
779 | target_write_memory (*to, buf, len); | |
780 | *to += len; | |
781 | } | |
782 | ||
783 | static void | |
784 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
785 | CORE_ADDR *to, CORE_ADDR oldloc) | |
786 | { | |
787 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
788 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
789 | int offset = 0, rel32, newrel; | |
790 | int insn_length; | |
791 | gdb_byte *insn = buf; | |
792 | ||
793 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
794 | ||
795 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
796 | I386_MAX_INSN_LEN, oldloc); | |
797 | ||
798 | /* Get past the prefixes. */ | |
799 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
800 | ||
801 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
802 | the address pushed being the location where the original call in | |
803 | the user program would return to. */ | |
804 | if (insn[0] == 0xe8) | |
805 | { | |
806 | gdb_byte push_buf[16]; | |
807 | unsigned int ret_addr; | |
808 | ||
809 | /* Where "ret" in the original code will return to. */ | |
810 | ret_addr = oldloc + insn_length; | |
1777feb0 | 811 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 812 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
813 | /* Push the push. */ |
814 | append_insns (to, 5, push_buf); | |
815 | ||
816 | /* Convert the relative call to a relative jump. */ | |
817 | insn[0] = 0xe9; | |
818 | ||
819 | /* Adjust the destination offset. */ | |
820 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
821 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
822 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
823 | ||
824 | if (debug_displaced) | |
825 | fprintf_unfiltered (gdb_stdlog, | |
826 | "Adjusted insn rel32=%s at %s to" | |
827 | " rel32=%s at %s\n", | |
828 | hex_string (rel32), paddress (gdbarch, oldloc), | |
829 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
830 | |
831 | /* Write the adjusted jump into its displaced location. */ | |
832 | append_insns (to, 5, insn); | |
833 | return; | |
834 | } | |
835 | ||
836 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
837 | handled above. */ | |
838 | if (insn[0] == 0xe9) | |
839 | offset = 1; | |
840 | /* Adjust conditional jumps. */ | |
841 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
842 | offset = 2; | |
843 | ||
844 | if (offset) | |
845 | { | |
846 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
847 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 848 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
849 | if (debug_displaced) |
850 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
851 | "Adjusted insn rel32=%s at %s to" |
852 | " rel32=%s at %s\n", | |
dde08ee1 PA |
853 | hex_string (rel32), paddress (gdbarch, oldloc), |
854 | hex_string (newrel), paddress (gdbarch, *to)); | |
855 | } | |
856 | ||
857 | /* Write the adjusted instructions into their displaced | |
858 | location. */ | |
859 | append_insns (to, insn_length, buf); | |
860 | } | |
861 | ||
fc338970 | 862 | \f |
acd5c798 MK |
863 | #ifdef I386_REGNO_TO_SYMMETRY |
864 | #error "The Sequent Symmetry is no longer supported." | |
865 | #endif | |
c906108c | 866 | |
acd5c798 MK |
867 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
868 | and %esp "belong" to the calling function. Therefore these | |
869 | registers should be saved if they're going to be modified. */ | |
c906108c | 870 | |
acd5c798 MK |
871 | /* The maximum number of saved registers. This should include all |
872 | registers mentioned above, and %eip. */ | |
a3386186 | 873 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
874 | |
875 | struct i386_frame_cache | |
c906108c | 876 | { |
acd5c798 MK |
877 | /* Base address. */ |
878 | CORE_ADDR base; | |
8fbca658 | 879 | int base_p; |
772562f8 | 880 | LONGEST sp_offset; |
acd5c798 MK |
881 | CORE_ADDR pc; |
882 | ||
fd13a04a AC |
883 | /* Saved registers. */ |
884 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 885 | CORE_ADDR saved_sp; |
e0c62198 | 886 | int saved_sp_reg; |
acd5c798 MK |
887 | int pc_in_eax; |
888 | ||
889 | /* Stack space reserved for local variables. */ | |
890 | long locals; | |
891 | }; | |
892 | ||
893 | /* Allocate and initialize a frame cache. */ | |
894 | ||
895 | static struct i386_frame_cache * | |
fd13a04a | 896 | i386_alloc_frame_cache (void) |
acd5c798 MK |
897 | { |
898 | struct i386_frame_cache *cache; | |
899 | int i; | |
900 | ||
901 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
902 | ||
903 | /* Base address. */ | |
8fbca658 | 904 | cache->base_p = 0; |
acd5c798 MK |
905 | cache->base = 0; |
906 | cache->sp_offset = -4; | |
907 | cache->pc = 0; | |
908 | ||
fd13a04a AC |
909 | /* Saved registers. We initialize these to -1 since zero is a valid |
910 | offset (that's where %ebp is supposed to be stored). */ | |
911 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
912 | cache->saved_regs[i] = -1; | |
acd5c798 | 913 | cache->saved_sp = 0; |
e0c62198 | 914 | cache->saved_sp_reg = -1; |
acd5c798 MK |
915 | cache->pc_in_eax = 0; |
916 | ||
917 | /* Frameless until proven otherwise. */ | |
918 | cache->locals = -1; | |
919 | ||
920 | return cache; | |
921 | } | |
c906108c | 922 | |
acd5c798 MK |
923 | /* If the instruction at PC is a jump, return the address of its |
924 | target. Otherwise, return PC. */ | |
c906108c | 925 | |
acd5c798 | 926 | static CORE_ADDR |
e17a4113 | 927 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 928 | { |
e17a4113 | 929 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 930 | gdb_byte op; |
acd5c798 MK |
931 | long delta = 0; |
932 | int data16 = 0; | |
c906108c | 933 | |
0865b04a | 934 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
935 | return pc; |
936 | ||
acd5c798 | 937 | if (op == 0x66) |
c906108c | 938 | { |
c906108c | 939 | data16 = 1; |
0865b04a YQ |
940 | |
941 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
942 | } |
943 | ||
acd5c798 | 944 | switch (op) |
c906108c SS |
945 | { |
946 | case 0xe9: | |
fc338970 | 947 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
948 | if (data16) |
949 | { | |
e17a4113 | 950 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 951 | |
fc338970 MK |
952 | /* Include the size of the jmp instruction (including the |
953 | 0x66 prefix). */ | |
acd5c798 | 954 | delta += 4; |
c906108c SS |
955 | } |
956 | else | |
957 | { | |
e17a4113 | 958 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 959 | |
acd5c798 MK |
960 | /* Include the size of the jmp instruction. */ |
961 | delta += 5; | |
c906108c SS |
962 | } |
963 | break; | |
964 | case 0xeb: | |
fc338970 | 965 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 966 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 967 | |
acd5c798 | 968 | delta += data16 + 2; |
c906108c SS |
969 | break; |
970 | } | |
c906108c | 971 | |
acd5c798 MK |
972 | return pc + delta; |
973 | } | |
fc338970 | 974 | |
acd5c798 MK |
975 | /* Check whether PC points at a prologue for a function returning a |
976 | structure or union. If so, it updates CACHE and returns the | |
977 | address of the first instruction after the code sequence that | |
978 | removes the "hidden" argument from the stack or CURRENT_PC, | |
979 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 980 | |
acd5c798 MK |
981 | static CORE_ADDR |
982 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
983 | struct i386_frame_cache *cache) | |
c906108c | 984 | { |
acd5c798 MK |
985 | /* Functions that return a structure or union start with: |
986 | ||
987 | popl %eax 0x58 | |
988 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
989 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
990 | ||
991 | (the System V compiler puts out the second `xchg' instruction, | |
992 | and the assembler doesn't try to optimize it, so the 'sib' form | |
993 | gets generated). This sequence is used to get the address of the | |
994 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
995 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
996 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
997 | gdb_byte buf[4]; | |
998 | gdb_byte op; | |
c906108c | 999 | |
acd5c798 MK |
1000 | if (current_pc <= pc) |
1001 | return pc; | |
1002 | ||
0865b04a | 1003 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1004 | return pc; |
c906108c | 1005 | |
acd5c798 MK |
1006 | if (op != 0x58) /* popl %eax */ |
1007 | return pc; | |
c906108c | 1008 | |
0865b04a | 1009 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1010 | return pc; |
1011 | ||
acd5c798 MK |
1012 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1013 | return pc; | |
c906108c | 1014 | |
acd5c798 | 1015 | if (current_pc == pc) |
c906108c | 1016 | { |
acd5c798 MK |
1017 | cache->sp_offset += 4; |
1018 | return current_pc; | |
c906108c SS |
1019 | } |
1020 | ||
acd5c798 | 1021 | if (current_pc == pc + 1) |
c906108c | 1022 | { |
acd5c798 MK |
1023 | cache->pc_in_eax = 1; |
1024 | return current_pc; | |
1025 | } | |
1026 | ||
1027 | if (buf[1] == proto1[1]) | |
1028 | return pc + 4; | |
1029 | else | |
1030 | return pc + 5; | |
1031 | } | |
1032 | ||
1033 | static CORE_ADDR | |
1034 | i386_skip_probe (CORE_ADDR pc) | |
1035 | { | |
1036 | /* A function may start with | |
fc338970 | 1037 | |
acd5c798 MK |
1038 | pushl constant |
1039 | call _probe | |
1040 | addl $4, %esp | |
fc338970 | 1041 | |
acd5c798 MK |
1042 | followed by |
1043 | ||
1044 | pushl %ebp | |
fc338970 | 1045 | |
acd5c798 | 1046 | etc. */ |
63c0089f MK |
1047 | gdb_byte buf[8]; |
1048 | gdb_byte op; | |
fc338970 | 1049 | |
0865b04a | 1050 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1051 | return pc; |
acd5c798 MK |
1052 | |
1053 | if (op == 0x68 || op == 0x6a) | |
1054 | { | |
1055 | int delta; | |
c906108c | 1056 | |
acd5c798 MK |
1057 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1058 | four-byte operand, depending on the opcode. */ | |
c906108c | 1059 | if (op == 0x68) |
acd5c798 | 1060 | delta = 5; |
c906108c | 1061 | else |
acd5c798 | 1062 | delta = 2; |
c906108c | 1063 | |
acd5c798 MK |
1064 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1065 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1066 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1067 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1068 | pc += delta + sizeof (buf); |
c906108c SS |
1069 | } |
1070 | ||
acd5c798 MK |
1071 | return pc; |
1072 | } | |
1073 | ||
92dd43fa MK |
1074 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1075 | stack pointer. Check whether PC points to such code, and update | |
1076 | CACHE accordingly. Return the first instruction after the code | |
1077 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1078 | recognize the code, return PC. */ | |
1079 | ||
1080 | static CORE_ADDR | |
1081 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1082 | struct i386_frame_cache *cache) | |
1083 | { | |
e0c62198 L |
1084 | /* There are 2 code sequences to re-align stack before the frame |
1085 | gets set up: | |
1086 | ||
1087 | 1. Use a caller-saved saved register: | |
1088 | ||
1089 | leal 4(%esp), %reg | |
1090 | andl $-XXX, %esp | |
1091 | pushl -4(%reg) | |
1092 | ||
1093 | 2. Use a callee-saved saved register: | |
1094 | ||
1095 | pushl %reg | |
1096 | leal 8(%esp), %reg | |
1097 | andl $-XXX, %esp | |
1098 | pushl -4(%reg) | |
1099 | ||
1100 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1101 | ||
1102 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1103 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1104 | */ | |
1105 | ||
1106 | gdb_byte buf[14]; | |
1107 | int reg; | |
1108 | int offset, offset_and; | |
1109 | static int regnums[8] = { | |
1110 | I386_EAX_REGNUM, /* %eax */ | |
1111 | I386_ECX_REGNUM, /* %ecx */ | |
1112 | I386_EDX_REGNUM, /* %edx */ | |
1113 | I386_EBX_REGNUM, /* %ebx */ | |
1114 | I386_ESP_REGNUM, /* %esp */ | |
1115 | I386_EBP_REGNUM, /* %ebp */ | |
1116 | I386_ESI_REGNUM, /* %esi */ | |
1117 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1118 | }; |
92dd43fa | 1119 | |
0865b04a | 1120 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1121 | return pc; |
1122 | ||
1123 | /* Check caller-saved saved register. The first instruction has | |
1124 | to be "leal 4(%esp), %reg". */ | |
1125 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1126 | { | |
1127 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1128 | if ((buf[1] & 0xc7) != 0x44) | |
1129 | return pc; | |
1130 | ||
1131 | /* REG has register number. */ | |
1132 | reg = (buf[1] >> 3) & 7; | |
1133 | offset = 4; | |
1134 | } | |
1135 | else | |
1136 | { | |
1137 | /* Check callee-saved saved register. The first instruction | |
1138 | has to be "pushl %reg". */ | |
1139 | if ((buf[0] & 0xf8) != 0x50) | |
1140 | return pc; | |
1141 | ||
1142 | /* Get register. */ | |
1143 | reg = buf[0] & 0x7; | |
1144 | ||
1145 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1146 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1147 | return pc; | |
1148 | ||
1149 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1150 | if ((buf[2] & 0xc7) != 0x44) | |
1151 | return pc; | |
1152 | ||
1153 | /* REG has register number. Registers in pushl and leal have to | |
1154 | be the same. */ | |
1155 | if (reg != ((buf[2] >> 3) & 7)) | |
1156 | return pc; | |
1157 | ||
1158 | offset = 5; | |
1159 | } | |
1160 | ||
1161 | /* Rigister can't be %esp nor %ebp. */ | |
1162 | if (reg == 4 || reg == 5) | |
1163 | return pc; | |
1164 | ||
1165 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1166 | if (buf[offset + 1] != 0xe4 | |
1167 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1168 | return pc; | |
1169 | ||
1170 | offset_and = offset; | |
1171 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1172 | ||
1173 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1174 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1175 | if (buf[offset] != 0xff | |
1176 | || buf[offset + 2] != 0xfc | |
1177 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1178 | return pc; | |
1179 | ||
1180 | /* R/M has register. Registers in leal and pushl have to be the | |
1181 | same. */ | |
1182 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1183 | return pc; |
1184 | ||
e0c62198 L |
1185 | if (current_pc > pc + offset_and) |
1186 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1187 | |
e0c62198 | 1188 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1189 | } |
1190 | ||
37bdc87e | 1191 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1192 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1193 | |
1194 | /* Instruction description. */ | |
1195 | struct i386_insn | |
1196 | { | |
1197 | size_t len; | |
237fc4c9 PA |
1198 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1199 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1200 | }; |
1201 | ||
a3fcb948 | 1202 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1203 | |
a3fcb948 JG |
1204 | static int |
1205 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1206 | { |
63c0089f | 1207 | gdb_byte op; |
37bdc87e | 1208 | |
0865b04a | 1209 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1210 | return 0; |
37bdc87e | 1211 | |
a3fcb948 | 1212 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1213 | { |
a3fcb948 JG |
1214 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1215 | int insn_matched = 1; | |
1216 | size_t i; | |
37bdc87e | 1217 | |
a3fcb948 JG |
1218 | gdb_assert (pattern.len > 1); |
1219 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1220 | |
0865b04a | 1221 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1222 | return 0; |
613e8135 | 1223 | |
a3fcb948 JG |
1224 | for (i = 1; i < pattern.len; i++) |
1225 | { | |
1226 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1227 | insn_matched = 0; | |
37bdc87e | 1228 | } |
a3fcb948 JG |
1229 | return insn_matched; |
1230 | } | |
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1235 | the first instruction description that matches. Otherwise, return | |
1236 | NULL. */ | |
1237 | ||
1238 | static struct i386_insn * | |
1239 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1240 | { | |
1241 | struct i386_insn *pattern; | |
1242 | ||
1243 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1244 | { | |
1245 | if (i386_match_pattern (pc, *pattern)) | |
1246 | return pattern; | |
37bdc87e MK |
1247 | } |
1248 | ||
1249 | return NULL; | |
1250 | } | |
1251 | ||
a3fcb948 JG |
1252 | /* Return whether PC points inside a sequence of instructions that |
1253 | matches INSN_PATTERNS. */ | |
1254 | ||
1255 | static int | |
1256 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1257 | { | |
1258 | CORE_ADDR current_pc; | |
1259 | int ix, i; | |
a3fcb948 JG |
1260 | struct i386_insn *insn; |
1261 | ||
1262 | insn = i386_match_insn (pc, insn_patterns); | |
1263 | if (insn == NULL) | |
1264 | return 0; | |
1265 | ||
8bbdd3f4 | 1266 | current_pc = pc; |
a3fcb948 JG |
1267 | ix = insn - insn_patterns; |
1268 | for (i = ix - 1; i >= 0; i--) | |
1269 | { | |
8bbdd3f4 MK |
1270 | current_pc -= insn_patterns[i].len; |
1271 | ||
a3fcb948 JG |
1272 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1273 | return 0; | |
a3fcb948 JG |
1274 | } |
1275 | ||
1276 | current_pc = pc + insn->len; | |
1277 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1278 | { | |
1279 | if (!i386_match_pattern (current_pc, *insn)) | |
1280 | return 0; | |
1281 | ||
1282 | current_pc += insn->len; | |
1283 | } | |
1284 | ||
1285 | return 1; | |
1286 | } | |
1287 | ||
37bdc87e MK |
1288 | /* Some special instructions that might be migrated by GCC into the |
1289 | part of the prologue that sets up the new stack frame. Because the | |
1290 | stack frame hasn't been setup yet, no registers have been saved | |
1291 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1292 | touched. */ | |
1293 | ||
1294 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1295 | { | |
1777feb0 | 1296 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1297 | |
1298 | ??? Should we handle 16-bit operand-sizes here? */ | |
1299 | ||
1300 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1301 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1302 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1303 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1304 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1305 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1306 | { 5, { 0xb8 }, { 0xfe } }, | |
1307 | /* `movl imm32, %edx' */ | |
1308 | { 5, { 0xba }, { 0xff } }, | |
1309 | ||
1310 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1311 | encoding for `mov m32, %eax'. | |
1312 | ||
1313 | ??? Should we handle SIB adressing here? | |
1314 | ??? Should we handle 16-bit operand-sizes here? */ | |
1315 | ||
1316 | /* `movl m32, %eax' */ | |
1317 | { 5, { 0xa1 }, { 0xff } }, | |
1318 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1319 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1320 | /* `movl m32, %edx' */ | |
1321 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1322 | ||
1323 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1324 | Because of the symmetry, there are actually two ways to encode | |
1325 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1326 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1327 | ||
1328 | /* `subl %eax, %eax' */ | |
1329 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1330 | /* `subl %ecx, %ecx' */ | |
1331 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1332 | /* `subl %edx, %edx' */ | |
1333 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1334 | /* `xorl %eax, %eax' */ | |
1335 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1336 | /* `xorl %ecx, %ecx' */ | |
1337 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1338 | /* `xorl %edx, %edx' */ | |
1339 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1340 | { 0 } | |
1341 | }; | |
1342 | ||
e11481da PM |
1343 | |
1344 | /* Check whether PC points to a no-op instruction. */ | |
1345 | static CORE_ADDR | |
1346 | i386_skip_noop (CORE_ADDR pc) | |
1347 | { | |
1348 | gdb_byte op; | |
1349 | int check = 1; | |
1350 | ||
0865b04a | 1351 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1352 | return pc; |
e11481da PM |
1353 | |
1354 | while (check) | |
1355 | { | |
1356 | check = 0; | |
1357 | /* Ignore `nop' instruction. */ | |
1358 | if (op == 0x90) | |
1359 | { | |
1360 | pc += 1; | |
0865b04a | 1361 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1362 | return pc; |
e11481da PM |
1363 | check = 1; |
1364 | } | |
1365 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1366 | Microsoft system dlls often start with | |
1367 | a `mov %edi,%edi' instruction. | |
1368 | The 5 bytes before the function start are | |
1369 | filled with `nop' instructions. | |
1370 | This pattern can be used for hot-patching: | |
1371 | The `mov %edi, %edi' instruction can be replaced by a | |
1372 | near jump to the location of the 5 `nop' instructions | |
1373 | which can be replaced by a 32-bit jump to anywhere | |
1374 | in the 32-bit address space. */ | |
1375 | ||
1376 | else if (op == 0x8b) | |
1377 | { | |
0865b04a | 1378 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1379 | return pc; |
1380 | ||
e11481da PM |
1381 | if (op == 0xff) |
1382 | { | |
1383 | pc += 2; | |
0865b04a | 1384 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1385 | return pc; |
1386 | ||
e11481da PM |
1387 | check = 1; |
1388 | } | |
1389 | } | |
1390 | } | |
1391 | return pc; | |
1392 | } | |
1393 | ||
acd5c798 MK |
1394 | /* Check whether PC points at a code that sets up a new stack frame. |
1395 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1396 | instruction after the sequence that sets up the frame or LIMIT, |
1397 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1398 | |
1399 | static CORE_ADDR | |
e17a4113 UW |
1400 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1401 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1402 | struct i386_frame_cache *cache) |
1403 | { | |
e17a4113 | 1404 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1405 | struct i386_insn *insn; |
63c0089f | 1406 | gdb_byte op; |
26604a34 | 1407 | int skip = 0; |
acd5c798 | 1408 | |
37bdc87e MK |
1409 | if (limit <= pc) |
1410 | return limit; | |
acd5c798 | 1411 | |
0865b04a | 1412 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1413 | return pc; |
acd5c798 | 1414 | |
c906108c | 1415 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1416 | { |
acd5c798 MK |
1417 | /* Take into account that we've executed the `pushl %ebp' that |
1418 | starts this instruction sequence. */ | |
fd13a04a | 1419 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1420 | cache->sp_offset += 4; |
37bdc87e | 1421 | pc++; |
acd5c798 MK |
1422 | |
1423 | /* If that's all, return now. */ | |
37bdc87e MK |
1424 | if (limit <= pc) |
1425 | return limit; | |
26604a34 | 1426 | |
b4632131 | 1427 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1428 | GCC into the prologue and skip them. At this point in the |
1429 | prologue, code should only touch the scratch registers %eax, | |
1430 | %ecx and %edx, so while the number of posibilities is sheer, | |
1431 | it is limited. | |
5daa5b4e | 1432 | |
26604a34 MK |
1433 | Make sure we only skip these instructions if we later see the |
1434 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1435 | while (pc + skip < limit) |
26604a34 | 1436 | { |
37bdc87e MK |
1437 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1438 | if (insn == NULL) | |
1439 | break; | |
b4632131 | 1440 | |
37bdc87e | 1441 | skip += insn->len; |
26604a34 MK |
1442 | } |
1443 | ||
37bdc87e MK |
1444 | /* If that's all, return now. */ |
1445 | if (limit <= pc + skip) | |
1446 | return limit; | |
1447 | ||
0865b04a | 1448 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1449 | return pc + skip; |
37bdc87e | 1450 | |
30f8135b YQ |
1451 | /* The i386 prologue looks like |
1452 | ||
1453 | push %ebp | |
1454 | mov %esp,%ebp | |
1455 | sub $0x10,%esp | |
1456 | ||
1457 | and a different prologue can be generated for atom. | |
1458 | ||
1459 | push %ebp | |
1460 | lea (%esp),%ebp | |
1461 | lea -0x10(%esp),%esp | |
1462 | ||
1463 | We handle both of them here. */ | |
1464 | ||
acd5c798 | 1465 | switch (op) |
c906108c | 1466 | { |
30f8135b | 1467 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1468 | case 0x8b: |
0865b04a | 1469 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1470 | != 0xec) |
37bdc87e | 1471 | return pc; |
30f8135b | 1472 | pc += (skip + 2); |
c906108c SS |
1473 | break; |
1474 | case 0x89: | |
0865b04a | 1475 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1476 | != 0xe5) |
37bdc87e | 1477 | return pc; |
30f8135b YQ |
1478 | pc += (skip + 2); |
1479 | break; | |
1480 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1481 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1482 | != 0x242c) |
1483 | return pc; | |
1484 | pc += (skip + 3); | |
c906108c SS |
1485 | break; |
1486 | default: | |
37bdc87e | 1487 | return pc; |
c906108c | 1488 | } |
acd5c798 | 1489 | |
26604a34 MK |
1490 | /* OK, we actually have a frame. We just don't know how large |
1491 | it is yet. Set its size to zero. We'll adjust it if | |
1492 | necessary. We also now commit to skipping the special | |
1493 | instructions mentioned before. */ | |
acd5c798 MK |
1494 | cache->locals = 0; |
1495 | ||
1496 | /* If that's all, return now. */ | |
37bdc87e MK |
1497 | if (limit <= pc) |
1498 | return limit; | |
acd5c798 | 1499 | |
fc338970 MK |
1500 | /* Check for stack adjustment |
1501 | ||
acd5c798 | 1502 | subl $XXX, %esp |
30f8135b YQ |
1503 | or |
1504 | lea -XXX(%esp),%esp | |
fc338970 | 1505 | |
fd35795f | 1506 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1507 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1508 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1509 | return pc; |
c906108c SS |
1510 | if (op == 0x83) |
1511 | { | |
fd35795f | 1512 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1513 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1514 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1515 | return pc; |
acd5c798 | 1516 | |
37bdc87e MK |
1517 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1518 | make sense to be negative). */ | |
0865b04a | 1519 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1520 | return pc + 3; |
c906108c SS |
1521 | } |
1522 | else if (op == 0x81) | |
1523 | { | |
fd35795f | 1524 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1525 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1526 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1527 | return pc; |
acd5c798 | 1528 | |
fd35795f | 1529 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1530 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1531 | return pc + 6; |
c906108c | 1532 | } |
30f8135b YQ |
1533 | else if (op == 0x8d) |
1534 | { | |
1535 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1536 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1537 | return pc; |
1538 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1539 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1540 | return pc + 4; |
1541 | } | |
c906108c SS |
1542 | else |
1543 | { | |
30f8135b | 1544 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1545 | return pc; |
c906108c SS |
1546 | } |
1547 | } | |
37bdc87e | 1548 | else if (op == 0xc8) /* enter */ |
c906108c | 1549 | { |
0865b04a | 1550 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1551 | return pc + 4; |
c906108c | 1552 | } |
21d0e8a4 | 1553 | |
acd5c798 | 1554 | return pc; |
21d0e8a4 MK |
1555 | } |
1556 | ||
acd5c798 MK |
1557 | /* Check whether PC points at code that saves registers on the stack. |
1558 | If so, it updates CACHE and returns the address of the first | |
1559 | instruction after the register saves or CURRENT_PC, whichever is | |
1560 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1561 | |
1562 | static CORE_ADDR | |
acd5c798 MK |
1563 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1564 | struct i386_frame_cache *cache) | |
6bff26de | 1565 | { |
99ab4326 | 1566 | CORE_ADDR offset = 0; |
63c0089f | 1567 | gdb_byte op; |
99ab4326 | 1568 | int i; |
c0d1d883 | 1569 | |
99ab4326 MK |
1570 | if (cache->locals > 0) |
1571 | offset -= cache->locals; | |
1572 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1573 | { | |
0865b04a | 1574 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1575 | return pc; |
99ab4326 MK |
1576 | if (op < 0x50 || op > 0x57) |
1577 | break; | |
0d17c81d | 1578 | |
99ab4326 MK |
1579 | offset -= 4; |
1580 | cache->saved_regs[op - 0x50] = offset; | |
1581 | cache->sp_offset += 4; | |
1582 | pc++; | |
6bff26de MK |
1583 | } |
1584 | ||
acd5c798 | 1585 | return pc; |
22797942 AC |
1586 | } |
1587 | ||
acd5c798 MK |
1588 | /* Do a full analysis of the prologue at PC and update CACHE |
1589 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1590 | address where the analysis stopped. | |
ed84f6c1 | 1591 | |
fc338970 MK |
1592 | We handle these cases: |
1593 | ||
1594 | The startup sequence can be at the start of the function, or the | |
1595 | function can start with a branch to startup code at the end. | |
1596 | ||
1597 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1598 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1599 | once used in the System V compiler). | |
1600 | ||
1601 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1602 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1603 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1604 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1605 | |
1606 | Next, the registers used by this function are pushed. With the | |
1607 | System V compiler they will always be in the order: %edi, %esi, | |
1608 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1609 | restore %eax); however, the code below is willing to see the pushes | |
1610 | in any order, and will handle up to 8 of them. | |
1611 | ||
1612 | If the setup sequence is at the end of the function, then the next | |
1613 | instruction will be a branch back to the start. */ | |
c906108c | 1614 | |
acd5c798 | 1615 | static CORE_ADDR |
e17a4113 UW |
1616 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1617 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1618 | struct i386_frame_cache *cache) |
c906108c | 1619 | { |
e11481da | 1620 | pc = i386_skip_noop (pc); |
e17a4113 | 1621 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1622 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1623 | pc = i386_skip_probe (pc); | |
92dd43fa | 1624 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1625 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1626 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1627 | } |
1628 | ||
fc338970 | 1629 | /* Return PC of first real instruction. */ |
c906108c | 1630 | |
3a1e71e3 | 1631 | static CORE_ADDR |
6093d2eb | 1632 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1633 | { |
e17a4113 UW |
1634 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1635 | ||
63c0089f | 1636 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1637 | { |
1638 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1639 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1640 | }; |
acd5c798 MK |
1641 | struct i386_frame_cache cache; |
1642 | CORE_ADDR pc; | |
63c0089f | 1643 | gdb_byte op; |
acd5c798 | 1644 | int i; |
56bf0743 | 1645 | CORE_ADDR func_addr; |
4e879fc2 | 1646 | |
56bf0743 KB |
1647 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1648 | { | |
1649 | CORE_ADDR post_prologue_pc | |
1650 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1651 | struct symtab *s = find_pc_symtab (func_addr); | |
1652 | ||
1653 | /* Clang always emits a line note before the prologue and another | |
1654 | one after. We trust clang to emit usable line notes. */ | |
1655 | if (post_prologue_pc | |
1656 | && (s != NULL | |
1657 | && s->producer != NULL | |
1658 | && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0)) | |
1659 | return max (start_pc, post_prologue_pc); | |
1660 | } | |
1661 | ||
e0f33b1f | 1662 | cache.locals = -1; |
e17a4113 | 1663 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1664 | if (cache.locals < 0) |
1665 | return start_pc; | |
c5aa993b | 1666 | |
acd5c798 | 1667 | /* Found valid frame setup. */ |
c906108c | 1668 | |
fc338970 MK |
1669 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1670 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1671 | %ebx: |
1672 | ||
fc338970 MK |
1673 | call 0x0 |
1674 | popl %ebx | |
1675 | movl %ebx,x(%ebp) (optional) | |
1676 | addl y,%ebx | |
1677 | ||
c906108c SS |
1678 | This code is with the rest of the prologue (at the end of the |
1679 | function), so we have to skip it to get to the first real | |
1680 | instruction at the start of the function. */ | |
c5aa993b | 1681 | |
c906108c SS |
1682 | for (i = 0; i < 6; i++) |
1683 | { | |
0865b04a | 1684 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1685 | return pc; |
1686 | ||
c5aa993b | 1687 | if (pic_pat[i] != op) |
c906108c SS |
1688 | break; |
1689 | } | |
1690 | if (i == 6) | |
1691 | { | |
acd5c798 MK |
1692 | int delta = 6; |
1693 | ||
0865b04a | 1694 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1695 | return pc; |
c906108c | 1696 | |
c5aa993b | 1697 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1698 | { |
0865b04a | 1699 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1700 | |
fc338970 | 1701 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1702 | delta += 3; |
fc338970 | 1703 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1704 | delta += 6; |
fc338970 | 1705 | else /* Unexpected instruction. */ |
acd5c798 MK |
1706 | delta = 0; |
1707 | ||
0865b04a | 1708 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1709 | return pc; |
c906108c | 1710 | } |
acd5c798 | 1711 | |
c5aa993b | 1712 | /* addl y,%ebx */ |
acd5c798 | 1713 | if (delta > 0 && op == 0x81 |
0865b04a | 1714 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1715 | == 0xc3) |
c906108c | 1716 | { |
acd5c798 | 1717 | pc += delta + 6; |
c906108c SS |
1718 | } |
1719 | } | |
c5aa993b | 1720 | |
e63bbc88 MK |
1721 | /* If the function starts with a branch (to startup code at the end) |
1722 | the last instruction should bring us back to the first | |
1723 | instruction of the real code. */ | |
e17a4113 UW |
1724 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1725 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1726 | |
1727 | return pc; | |
c906108c SS |
1728 | } |
1729 | ||
4309257c PM |
1730 | /* Check that the code pointed to by PC corresponds to a call to |
1731 | __main, skip it if so. Return PC otherwise. */ | |
1732 | ||
1733 | CORE_ADDR | |
1734 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1735 | { | |
e17a4113 | 1736 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1737 | gdb_byte op; |
1738 | ||
0865b04a | 1739 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1740 | return pc; |
4309257c PM |
1741 | if (op == 0xe8) |
1742 | { | |
1743 | gdb_byte buf[4]; | |
1744 | ||
0865b04a | 1745 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
4309257c PM |
1746 | { |
1747 | /* Make sure address is computed correctly as a 32bit | |
1748 | integer even if CORE_ADDR is 64 bit wide. */ | |
7cbd4a93 | 1749 | struct bound_minimal_symbol s; |
e17a4113 | 1750 | CORE_ADDR call_dest; |
4309257c | 1751 | |
e17a4113 | 1752 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1753 | call_dest = call_dest & 0xffffffffU; |
1754 | s = lookup_minimal_symbol_by_pc (call_dest); | |
7cbd4a93 TT |
1755 | if (s.minsym != NULL |
1756 | && SYMBOL_LINKAGE_NAME (s.minsym) != NULL | |
1757 | && strcmp (SYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0) | |
4309257c PM |
1758 | pc += 5; |
1759 | } | |
1760 | } | |
1761 | ||
1762 | return pc; | |
1763 | } | |
1764 | ||
acd5c798 | 1765 | /* This function is 64-bit safe. */ |
93924b6b | 1766 | |
acd5c798 MK |
1767 | static CORE_ADDR |
1768 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1769 | { |
63c0089f | 1770 | gdb_byte buf[8]; |
acd5c798 | 1771 | |
875f8d0e | 1772 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1773 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1774 | } |
acd5c798 | 1775 | \f |
93924b6b | 1776 | |
acd5c798 | 1777 | /* Normal frames. */ |
c5aa993b | 1778 | |
8fbca658 PA |
1779 | static void |
1780 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1781 | struct i386_frame_cache *cache) | |
a7769679 | 1782 | { |
e17a4113 UW |
1783 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1784 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1785 | gdb_byte buf[4]; |
acd5c798 MK |
1786 | int i; |
1787 | ||
8fbca658 | 1788 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1789 | |
1790 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1791 | which holds the base address for the current stack frame. | |
1792 | However, for functions that don't need it, the frame pointer is | |
1793 | optional. For these "frameless" functions the frame pointer is | |
1794 | actually the frame pointer of the calling frame. Signal | |
1795 | trampolines are just a special case of a "frameless" function. | |
1796 | They (usually) share their frame pointer with the frame that was | |
1797 | in progress when the signal occurred. */ | |
1798 | ||
10458914 | 1799 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1800 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1801 | if (cache->base == 0) |
620fa63a PA |
1802 | { |
1803 | cache->base_p = 1; | |
1804 | return; | |
1805 | } | |
acd5c798 MK |
1806 | |
1807 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1808 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1809 | |
acd5c798 | 1810 | if (cache->pc != 0) |
e17a4113 UW |
1811 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1812 | cache); | |
acd5c798 MK |
1813 | |
1814 | if (cache->locals < 0) | |
1815 | { | |
1816 | /* We didn't find a valid frame, which means that CACHE->base | |
1817 | currently holds the frame pointer for our calling frame. If | |
1818 | we're at the start of a function, or somewhere half-way its | |
1819 | prologue, the function's frame probably hasn't been fully | |
1820 | setup yet. Try to reconstruct the base address for the stack | |
1821 | frame by looking at the stack pointer. For truly "frameless" | |
1822 | functions this might work too. */ | |
1823 | ||
e0c62198 | 1824 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1825 | { |
8fbca658 PA |
1826 | /* Saved stack pointer has been saved. */ |
1827 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
1828 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1829 | ||
92dd43fa MK |
1830 | /* We're halfway aligning the stack. */ |
1831 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1832 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1833 | ||
1834 | /* This will be added back below. */ | |
1835 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1836 | } | |
7618e12b | 1837 | else if (cache->pc != 0 |
0865b04a | 1838 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 1839 | { |
7618e12b DJ |
1840 | /* We're in a known function, but did not find a frame |
1841 | setup. Assume that the function does not use %ebp. | |
1842 | Alternatively, we may have jumped to an invalid | |
1843 | address; in that case there is definitely no new | |
1844 | frame in %ebp. */ | |
10458914 | 1845 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1846 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1847 | + cache->sp_offset; | |
92dd43fa | 1848 | } |
7618e12b DJ |
1849 | else |
1850 | /* We're in an unknown function. We could not find the start | |
1851 | of the function to analyze the prologue; our best option is | |
1852 | to assume a typical frame layout with the caller's %ebp | |
1853 | saved. */ | |
1854 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1855 | } |
1856 | ||
8fbca658 PA |
1857 | if (cache->saved_sp_reg != -1) |
1858 | { | |
1859 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
1860 | register may be unavailable). */ | |
1861 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
1862 | && deprecated_frame_register_read (this_frame, |
1863 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
1864 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
1865 | } | |
acd5c798 MK |
1866 | /* Now that we have the base address for the stack frame we can |
1867 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 1868 | else if (cache->saved_sp == 0) |
92dd43fa | 1869 | cache->saved_sp = cache->base + 8; |
a7769679 | 1870 | |
acd5c798 MK |
1871 | /* Adjust all the saved registers such that they contain addresses |
1872 | instead of offsets. */ | |
1873 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1874 | if (cache->saved_regs[i] != -1) |
1875 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 1876 | |
8fbca658 PA |
1877 | cache->base_p = 1; |
1878 | } | |
1879 | ||
1880 | static struct i386_frame_cache * | |
1881 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1882 | { | |
1883 | volatile struct gdb_exception ex; | |
1884 | struct i386_frame_cache *cache; | |
1885 | ||
1886 | if (*this_cache) | |
1887 | return *this_cache; | |
1888 | ||
1889 | cache = i386_alloc_frame_cache (); | |
1890 | *this_cache = cache; | |
1891 | ||
1892 | TRY_CATCH (ex, RETURN_MASK_ERROR) | |
1893 | { | |
1894 | i386_frame_cache_1 (this_frame, cache); | |
1895 | } | |
1896 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1897 | throw_exception (ex); | |
1898 | ||
acd5c798 | 1899 | return cache; |
a7769679 MK |
1900 | } |
1901 | ||
3a1e71e3 | 1902 | static void |
10458914 | 1903 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1904 | struct frame_id *this_id) |
c906108c | 1905 | { |
10458914 | 1906 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 1907 | |
5ce0145d PA |
1908 | if (!cache->base_p) |
1909 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
1910 | else if (cache->base == 0) | |
1911 | { | |
1912 | /* This marks the outermost frame. */ | |
1913 | } | |
1914 | else | |
1915 | { | |
1916 | /* See the end of i386_push_dummy_call. */ | |
1917 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
1918 | } | |
acd5c798 MK |
1919 | } |
1920 | ||
8fbca658 PA |
1921 | static enum unwind_stop_reason |
1922 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1923 | void **this_cache) | |
1924 | { | |
1925 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
1926 | ||
1927 | if (!cache->base_p) | |
1928 | return UNWIND_UNAVAILABLE; | |
1929 | ||
1930 | /* This marks the outermost frame. */ | |
1931 | if (cache->base == 0) | |
1932 | return UNWIND_OUTERMOST; | |
1933 | ||
1934 | return UNWIND_NO_REASON; | |
1935 | } | |
1936 | ||
10458914 DJ |
1937 | static struct value * |
1938 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1939 | int regnum) | |
acd5c798 | 1940 | { |
10458914 | 1941 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1942 | |
1943 | gdb_assert (regnum >= 0); | |
1944 | ||
1945 | /* The System V ABI says that: | |
1946 | ||
1947 | "The flags register contains the system flags, such as the | |
1948 | direction flag and the carry flag. The direction flag must be | |
1949 | set to the forward (that is, zero) direction before entry and | |
1950 | upon exit from a function. Other user flags have no specified | |
1951 | role in the standard calling sequence and are not preserved." | |
1952 | ||
1953 | To guarantee the "upon exit" part of that statement we fake a | |
1954 | saved flags register that has its direction flag cleared. | |
1955 | ||
1956 | Note that GCC doesn't seem to rely on the fact that the direction | |
1957 | flag is cleared after a function return; it always explicitly | |
1958 | clears the flag before operations where it matters. | |
1959 | ||
1960 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1961 | right thing to do. The way we fake the flags register here makes | |
1962 | it impossible to change it. */ | |
1963 | ||
1964 | if (regnum == I386_EFLAGS_REGNUM) | |
1965 | { | |
10458914 | 1966 | ULONGEST val; |
c5aa993b | 1967 | |
10458914 DJ |
1968 | val = get_frame_register_unsigned (this_frame, regnum); |
1969 | val &= ~(1 << 10); | |
1970 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1971 | } |
1211c4e4 | 1972 | |
acd5c798 | 1973 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1974 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 1975 | |
fcf250e2 UW |
1976 | if (regnum == I386_ESP_REGNUM |
1977 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
1978 | { |
1979 | /* If the SP has been saved, but we don't know where, then this | |
1980 | means that SAVED_SP_REG register was found unavailable back | |
1981 | when we built the cache. */ | |
fcf250e2 | 1982 | if (cache->saved_sp == 0) |
8fbca658 PA |
1983 | return frame_unwind_got_register (this_frame, regnum, |
1984 | cache->saved_sp_reg); | |
1985 | else | |
1986 | return frame_unwind_got_constant (this_frame, regnum, | |
1987 | cache->saved_sp); | |
1988 | } | |
acd5c798 | 1989 | |
fd13a04a | 1990 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1991 | return frame_unwind_got_memory (this_frame, regnum, |
1992 | cache->saved_regs[regnum]); | |
fd13a04a | 1993 | |
10458914 | 1994 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1995 | } |
1996 | ||
1997 | static const struct frame_unwind i386_frame_unwind = | |
1998 | { | |
1999 | NORMAL_FRAME, | |
8fbca658 | 2000 | i386_frame_unwind_stop_reason, |
acd5c798 | 2001 | i386_frame_this_id, |
10458914 DJ |
2002 | i386_frame_prev_register, |
2003 | NULL, | |
2004 | default_frame_sniffer | |
acd5c798 | 2005 | }; |
06da04c6 MS |
2006 | |
2007 | /* Normal frames, but in a function epilogue. */ | |
2008 | ||
2009 | /* The epilogue is defined here as the 'ret' instruction, which will | |
2010 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
2011 | the function's stack frame. */ | |
2012 | ||
2013 | static int | |
2014 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2015 | { | |
2016 | gdb_byte insn; | |
e0d00bc7 JK |
2017 | struct symtab *symtab; |
2018 | ||
2019 | symtab = find_pc_symtab (pc); | |
2020 | if (symtab && symtab->epilogue_unwind_valid) | |
2021 | return 0; | |
06da04c6 MS |
2022 | |
2023 | if (target_read_memory (pc, &insn, 1)) | |
2024 | return 0; /* Can't read memory at pc. */ | |
2025 | ||
2026 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2027 | return 0; | |
2028 | ||
2029 | return 1; | |
2030 | } | |
2031 | ||
2032 | static int | |
2033 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2034 | struct frame_info *this_frame, | |
2035 | void **this_prologue_cache) | |
2036 | { | |
2037 | if (frame_relative_level (this_frame) == 0) | |
2038 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
2039 | get_frame_pc (this_frame)); | |
2040 | else | |
2041 | return 0; | |
2042 | } | |
2043 | ||
2044 | static struct i386_frame_cache * | |
2045 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2046 | { | |
8fbca658 | 2047 | volatile struct gdb_exception ex; |
06da04c6 | 2048 | struct i386_frame_cache *cache; |
0d6c2135 | 2049 | CORE_ADDR sp; |
06da04c6 MS |
2050 | |
2051 | if (*this_cache) | |
2052 | return *this_cache; | |
2053 | ||
2054 | cache = i386_alloc_frame_cache (); | |
2055 | *this_cache = cache; | |
2056 | ||
8fbca658 PA |
2057 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
2058 | { | |
0d6c2135 | 2059 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2060 | |
0d6c2135 MK |
2061 | /* At this point the stack looks as if we just entered the |
2062 | function, with the return address at the top of the | |
2063 | stack. */ | |
2064 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2065 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2066 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2067 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2068 | |
8fbca658 PA |
2069 | cache->base_p = 1; |
2070 | } | |
2071 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
2072 | throw_exception (ex); | |
06da04c6 MS |
2073 | |
2074 | return cache; | |
2075 | } | |
2076 | ||
8fbca658 PA |
2077 | static enum unwind_stop_reason |
2078 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2079 | void **this_cache) | |
2080 | { | |
0d6c2135 MK |
2081 | struct i386_frame_cache *cache = |
2082 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2083 | |
2084 | if (!cache->base_p) | |
2085 | return UNWIND_UNAVAILABLE; | |
2086 | ||
2087 | return UNWIND_NO_REASON; | |
2088 | } | |
2089 | ||
06da04c6 MS |
2090 | static void |
2091 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2092 | void **this_cache, | |
2093 | struct frame_id *this_id) | |
2094 | { | |
0d6c2135 MK |
2095 | struct i386_frame_cache *cache = |
2096 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2097 | |
8fbca658 | 2098 | if (!cache->base_p) |
5ce0145d PA |
2099 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2100 | else | |
2101 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2102 | } |
2103 | ||
0d6c2135 MK |
2104 | static struct value * |
2105 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2106 | void **this_cache, int regnum) | |
2107 | { | |
2108 | /* Make sure we've initialized the cache. */ | |
2109 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2110 | ||
2111 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2112 | } | |
2113 | ||
06da04c6 MS |
2114 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2115 | { | |
2116 | NORMAL_FRAME, | |
8fbca658 | 2117 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2118 | i386_epilogue_frame_this_id, |
0d6c2135 | 2119 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2120 | NULL, |
2121 | i386_epilogue_frame_sniffer | |
2122 | }; | |
acd5c798 MK |
2123 | \f |
2124 | ||
a3fcb948 JG |
2125 | /* Stack-based trampolines. */ |
2126 | ||
2127 | /* These trampolines are used on cross x86 targets, when taking the | |
2128 | address of a nested function. When executing these trampolines, | |
2129 | no stack frame is set up, so we are in a similar situation as in | |
2130 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2131 | ||
2132 | /* Static chain passed in register. */ | |
2133 | ||
2134 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2135 | { | |
2136 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2137 | { 5, { 0xb8 }, { 0xfe } }, | |
2138 | ||
2139 | /* `jmp imm32' */ | |
2140 | { 5, { 0xe9 }, { 0xff } }, | |
2141 | ||
2142 | {0} | |
2143 | }; | |
2144 | ||
2145 | /* Static chain passed on stack (when regparm=3). */ | |
2146 | ||
2147 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2148 | { | |
2149 | /* `push imm32' */ | |
2150 | { 5, { 0x68 }, { 0xff } }, | |
2151 | ||
2152 | /* `jmp imm32' */ | |
2153 | { 5, { 0xe9 }, { 0xff } }, | |
2154 | ||
2155 | {0} | |
2156 | }; | |
2157 | ||
2158 | /* Return whether PC points inside a stack trampoline. */ | |
2159 | ||
2160 | static int | |
6df81a63 | 2161 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2162 | { |
2163 | gdb_byte insn; | |
2c02bd72 | 2164 | const char *name; |
a3fcb948 JG |
2165 | |
2166 | /* A stack trampoline is detected if no name is associated | |
2167 | to the current pc and if it points inside a trampoline | |
2168 | sequence. */ | |
2169 | ||
2170 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2171 | if (name) | |
2172 | return 0; | |
2173 | ||
2174 | if (target_read_memory (pc, &insn, 1)) | |
2175 | return 0; | |
2176 | ||
2177 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2178 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2179 | return 0; | |
2180 | ||
2181 | return 1; | |
2182 | } | |
2183 | ||
2184 | static int | |
2185 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2186 | struct frame_info *this_frame, |
2187 | void **this_cache) | |
a3fcb948 JG |
2188 | { |
2189 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2190 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2191 | else |
2192 | return 0; | |
2193 | } | |
2194 | ||
2195 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2196 | { | |
2197 | NORMAL_FRAME, | |
2198 | i386_epilogue_frame_unwind_stop_reason, | |
2199 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2200 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2201 | NULL, |
2202 | i386_stack_tramp_frame_sniffer | |
2203 | }; | |
2204 | \f | |
6710bf39 SS |
2205 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2206 | ||
2207 | static void | |
2208 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2209 | struct agent_expr *ax, struct axs_value *value, | |
2210 | CORE_ADDR scope) | |
2211 | { | |
2212 | /* The following sequence assumes the traditional use of the base | |
2213 | register. */ | |
2214 | ax_reg (ax, I386_EBP_REGNUM); | |
2215 | ax_const_l (ax, 4); | |
2216 | ax_simple (ax, aop_add); | |
2217 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2218 | value->kind = axs_lvalue_memory; | |
2219 | } | |
2220 | \f | |
a3fcb948 | 2221 | |
acd5c798 MK |
2222 | /* Signal trampolines. */ |
2223 | ||
2224 | static struct i386_frame_cache * | |
10458914 | 2225 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2226 | { |
e17a4113 UW |
2227 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2228 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2229 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2230 | volatile struct gdb_exception ex; |
acd5c798 | 2231 | struct i386_frame_cache *cache; |
acd5c798 | 2232 | CORE_ADDR addr; |
63c0089f | 2233 | gdb_byte buf[4]; |
acd5c798 MK |
2234 | |
2235 | if (*this_cache) | |
2236 | return *this_cache; | |
2237 | ||
fd13a04a | 2238 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2239 | |
8fbca658 | 2240 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
a3386186 | 2241 | { |
8fbca658 PA |
2242 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2243 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2244 | |
8fbca658 PA |
2245 | addr = tdep->sigcontext_addr (this_frame); |
2246 | if (tdep->sc_reg_offset) | |
2247 | { | |
2248 | int i; | |
a3386186 | 2249 | |
8fbca658 PA |
2250 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2251 | ||
2252 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2253 | if (tdep->sc_reg_offset[i] != -1) | |
2254 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2255 | } | |
2256 | else | |
2257 | { | |
2258 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2259 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2260 | } | |
2261 | ||
2262 | cache->base_p = 1; | |
a3386186 | 2263 | } |
8fbca658 PA |
2264 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
2265 | throw_exception (ex); | |
acd5c798 MK |
2266 | |
2267 | *this_cache = cache; | |
2268 | return cache; | |
2269 | } | |
2270 | ||
8fbca658 PA |
2271 | static enum unwind_stop_reason |
2272 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2273 | void **this_cache) | |
2274 | { | |
2275 | struct i386_frame_cache *cache = | |
2276 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2277 | ||
2278 | if (!cache->base_p) | |
2279 | return UNWIND_UNAVAILABLE; | |
2280 | ||
2281 | return UNWIND_NO_REASON; | |
2282 | } | |
2283 | ||
acd5c798 | 2284 | static void |
10458914 | 2285 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2286 | struct frame_id *this_id) |
2287 | { | |
2288 | struct i386_frame_cache *cache = | |
10458914 | 2289 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2290 | |
8fbca658 | 2291 | if (!cache->base_p) |
5ce0145d PA |
2292 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2293 | else | |
2294 | { | |
2295 | /* See the end of i386_push_dummy_call. */ | |
2296 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2297 | } | |
acd5c798 MK |
2298 | } |
2299 | ||
10458914 DJ |
2300 | static struct value * |
2301 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2302 | void **this_cache, int regnum) | |
acd5c798 MK |
2303 | { |
2304 | /* Make sure we've initialized the cache. */ | |
10458914 | 2305 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2306 | |
10458914 | 2307 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2308 | } |
c0d1d883 | 2309 | |
10458914 DJ |
2310 | static int |
2311 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2312 | struct frame_info *this_frame, | |
2313 | void **this_prologue_cache) | |
acd5c798 | 2314 | { |
10458914 | 2315 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2316 | |
911bc6ee MK |
2317 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2318 | handler. */ | |
2319 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2320 | return 0; |
1c3545ae | 2321 | |
911bc6ee MK |
2322 | if (tdep->sigtramp_p != NULL) |
2323 | { | |
10458914 DJ |
2324 | if (tdep->sigtramp_p (this_frame)) |
2325 | return 1; | |
911bc6ee MK |
2326 | } |
2327 | ||
2328 | if (tdep->sigtramp_start != 0) | |
2329 | { | |
10458914 | 2330 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2331 | |
2332 | gdb_assert (tdep->sigtramp_end != 0); | |
2333 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2334 | return 1; |
911bc6ee | 2335 | } |
acd5c798 | 2336 | |
10458914 | 2337 | return 0; |
acd5c798 | 2338 | } |
10458914 DJ |
2339 | |
2340 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2341 | { | |
2342 | SIGTRAMP_FRAME, | |
8fbca658 | 2343 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2344 | i386_sigtramp_frame_this_id, |
2345 | i386_sigtramp_frame_prev_register, | |
2346 | NULL, | |
2347 | i386_sigtramp_frame_sniffer | |
2348 | }; | |
acd5c798 MK |
2349 | \f |
2350 | ||
2351 | static CORE_ADDR | |
10458914 | 2352 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2353 | { |
10458914 | 2354 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2355 | |
2356 | return cache->base; | |
2357 | } | |
2358 | ||
2359 | static const struct frame_base i386_frame_base = | |
2360 | { | |
2361 | &i386_frame_unwind, | |
2362 | i386_frame_base_address, | |
2363 | i386_frame_base_address, | |
2364 | i386_frame_base_address | |
2365 | }; | |
2366 | ||
acd5c798 | 2367 | static struct frame_id |
10458914 | 2368 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2369 | { |
acd5c798 MK |
2370 | CORE_ADDR fp; |
2371 | ||
10458914 | 2372 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2373 | |
3e210248 | 2374 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2375 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2376 | } |
e04e5beb JM |
2377 | |
2378 | /* _Decimal128 function return values need 16-byte alignment on the | |
2379 | stack. */ | |
2380 | ||
2381 | static CORE_ADDR | |
2382 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2383 | { | |
2384 | return sp & -(CORE_ADDR)16; | |
2385 | } | |
fc338970 | 2386 | \f |
c906108c | 2387 | |
fc338970 MK |
2388 | /* Figure out where the longjmp will land. Slurp the args out of the |
2389 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2390 | structure from which we extract the address that we will land at. |
28bcfd30 | 2391 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2392 | success. */ |
c906108c | 2393 | |
8201327c | 2394 | static int |
60ade65d | 2395 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2396 | { |
436675d3 | 2397 | gdb_byte buf[4]; |
c906108c | 2398 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2399 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2400 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2401 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2402 | |
8201327c MK |
2403 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2404 | longjmp will land. */ | |
2405 | if (jb_pc_offset == -1) | |
c906108c SS |
2406 | return 0; |
2407 | ||
436675d3 | 2408 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2409 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2410 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2411 | return 0; |
2412 | ||
e17a4113 | 2413 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2414 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2415 | return 0; |
c906108c | 2416 | |
e17a4113 | 2417 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2418 | return 1; |
2419 | } | |
fc338970 | 2420 | \f |
c906108c | 2421 | |
7ccc1c74 JM |
2422 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2423 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2424 | unions containing such types must be 16-byte-aligned; other | |
2425 | arguments are 4-byte-aligned. */ | |
2426 | ||
2427 | static int | |
2428 | i386_16_byte_align_p (struct type *type) | |
2429 | { | |
2430 | type = check_typedef (type); | |
2431 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2432 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2433 | && TYPE_LENGTH (type) == 16) | |
2434 | return 1; | |
2435 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2436 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2437 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2438 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2439 | { | |
2440 | int i; | |
2441 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2442 | { | |
2443 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2444 | return 1; | |
2445 | } | |
2446 | } | |
2447 | return 0; | |
2448 | } | |
2449 | ||
a9b8d892 JK |
2450 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2451 | ||
2452 | static CORE_ADDR | |
2453 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2454 | struct value **args, int nargs, struct type *value_type, | |
2455 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2456 | struct regcache *regcache) | |
2457 | { | |
2458 | /* Use 0xcc breakpoint - 1 byte. */ | |
2459 | *bp_addr = sp - 1; | |
2460 | *real_pc = funaddr; | |
2461 | ||
2462 | /* Keep the stack aligned. */ | |
2463 | return sp - 16; | |
2464 | } | |
2465 | ||
3a1e71e3 | 2466 | static CORE_ADDR |
7d9b040b | 2467 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2468 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2469 | struct value **args, CORE_ADDR sp, int struct_return, | |
2470 | CORE_ADDR struct_addr) | |
22f8ba57 | 2471 | { |
e17a4113 | 2472 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2473 | gdb_byte buf[4]; |
acd5c798 | 2474 | int i; |
7ccc1c74 JM |
2475 | int write_pass; |
2476 | int args_space = 0; | |
acd5c798 | 2477 | |
7ccc1c74 JM |
2478 | /* Determine the total space required for arguments and struct |
2479 | return address in a first pass (allowing for 16-byte-aligned | |
2480 | arguments), then push arguments in a second pass. */ | |
2481 | ||
2482 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2483 | { |
7ccc1c74 | 2484 | int args_space_used = 0; |
7ccc1c74 JM |
2485 | |
2486 | if (struct_return) | |
2487 | { | |
2488 | if (write_pass) | |
2489 | { | |
2490 | /* Push value address. */ | |
e17a4113 | 2491 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2492 | write_memory (sp, buf, 4); |
2493 | args_space_used += 4; | |
2494 | } | |
2495 | else | |
2496 | args_space += 4; | |
2497 | } | |
2498 | ||
2499 | for (i = 0; i < nargs; i++) | |
2500 | { | |
2501 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2502 | |
7ccc1c74 JM |
2503 | if (write_pass) |
2504 | { | |
2505 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2506 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2507 | |
7ccc1c74 JM |
2508 | write_memory (sp + args_space_used, |
2509 | value_contents_all (args[i]), len); | |
2510 | /* The System V ABI says that: | |
acd5c798 | 2511 | |
7ccc1c74 JM |
2512 | "An argument's size is increased, if necessary, to make it a |
2513 | multiple of [32-bit] words. This may require tail padding, | |
2514 | depending on the size of the argument." | |
22f8ba57 | 2515 | |
7ccc1c74 JM |
2516 | This makes sure the stack stays word-aligned. */ |
2517 | args_space_used += align_up (len, 4); | |
2518 | } | |
2519 | else | |
2520 | { | |
2521 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2522 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2523 | args_space += align_up (len, 4); |
2524 | } | |
2525 | } | |
2526 | ||
2527 | if (!write_pass) | |
2528 | { | |
7ccc1c74 | 2529 | sp -= args_space; |
284c5a60 MK |
2530 | |
2531 | /* The original System V ABI only requires word alignment, | |
2532 | but modern incarnations need 16-byte alignment in order | |
2533 | to support SSE. Since wasting a few bytes here isn't | |
2534 | harmful we unconditionally enforce 16-byte alignment. */ | |
2535 | sp &= ~0xf; | |
7ccc1c74 | 2536 | } |
22f8ba57 MK |
2537 | } |
2538 | ||
acd5c798 MK |
2539 | /* Store return address. */ |
2540 | sp -= 4; | |
e17a4113 | 2541 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2542 | write_memory (sp, buf, 4); |
2543 | ||
2544 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2545 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2546 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2547 | ||
2548 | /* ...and fake a frame pointer. */ | |
2549 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2550 | ||
3e210248 AC |
2551 | /* MarkK wrote: This "+ 8" is all over the place: |
2552 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2553 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2554 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2555 | definition of the stack address of a frame. Otherwise frame id |
2556 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2557 | stack address *before* the function call as a frame's CFA. On |
2558 | the i386, when %ebp is used as a frame pointer, the offset | |
2559 | between the contents %ebp and the CFA as defined by GCC. */ | |
2560 | return sp + 8; | |
22f8ba57 MK |
2561 | } |
2562 | ||
1a309862 MK |
2563 | /* These registers are used for returning integers (and on some |
2564 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2565 | size and alignment match an integer type). */ |
acd5c798 MK |
2566 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2567 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2568 | |
c5e656c1 MK |
2569 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2570 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2571 | |
3a1e71e3 | 2572 | static void |
c5e656c1 | 2573 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2574 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2575 | { |
c5e656c1 | 2576 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2577 | int len = TYPE_LENGTH (type); |
63c0089f | 2578 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2579 | |
1e8d0a7b | 2580 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2581 | { |
5716833c | 2582 | if (tdep->st0_regnum < 0) |
1a309862 | 2583 | { |
8a3fe4f8 | 2584 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2585 | memset (valbuf, 0, len); |
ef9dff19 | 2586 | return; |
1a309862 MK |
2587 | } |
2588 | ||
c6ba6f0d MK |
2589 | /* Floating-point return values can be found in %st(0). Convert |
2590 | its contents to the desired type. This is probably not | |
2591 | exactly how it would happen on the target itself, but it is | |
2592 | the best we can do. */ | |
acd5c798 | 2593 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2594 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2595 | } |
2596 | else | |
c5aa993b | 2597 | { |
875f8d0e UW |
2598 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2599 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2600 | |
2601 | if (len <= low_size) | |
00f8375e | 2602 | { |
0818c12a | 2603 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2604 | memcpy (valbuf, buf, len); |
2605 | } | |
d4f3574e SS |
2606 | else if (len <= (low_size + high_size)) |
2607 | { | |
0818c12a | 2608 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2609 | memcpy (valbuf, buf, low_size); |
0818c12a | 2610 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2611 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2612 | } |
2613 | else | |
8e65ff28 | 2614 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2615 | _("Cannot extract return value of %d bytes long."), |
2616 | len); | |
c906108c SS |
2617 | } |
2618 | } | |
2619 | ||
c5e656c1 MK |
2620 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2621 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2622 | |
3a1e71e3 | 2623 | static void |
c5e656c1 | 2624 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2625 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2626 | { |
c5e656c1 | 2627 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2628 | int len = TYPE_LENGTH (type); |
2629 | ||
1e8d0a7b | 2630 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2631 | { |
3d7f4f49 | 2632 | ULONGEST fstat; |
63c0089f | 2633 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2634 | |
5716833c | 2635 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2636 | { |
8a3fe4f8 | 2637 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2638 | return; |
2639 | } | |
2640 | ||
635b0cc1 MK |
2641 | /* Returning floating-point values is a bit tricky. Apart from |
2642 | storing the return value in %st(0), we have to simulate the | |
2643 | state of the FPU at function return point. */ | |
2644 | ||
c6ba6f0d MK |
2645 | /* Convert the value found in VALBUF to the extended |
2646 | floating-point format used by the FPU. This is probably | |
2647 | not exactly how it would happen on the target itself, but | |
2648 | it is the best we can do. */ | |
27067745 | 2649 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2650 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2651 | |
635b0cc1 MK |
2652 | /* Set the top of the floating-point register stack to 7. The |
2653 | actual value doesn't really matter, but 7 is what a normal | |
2654 | function return would end up with if the program started out | |
2655 | with a freshly initialized FPU. */ | |
20a6ec49 | 2656 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2657 | fstat |= (7 << 11); |
20a6ec49 | 2658 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2659 | |
635b0cc1 MK |
2660 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2661 | the floating-point register stack to 7, the appropriate value | |
2662 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2663 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2664 | } |
2665 | else | |
2666 | { | |
875f8d0e UW |
2667 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2668 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2669 | |
2670 | if (len <= low_size) | |
3d7f4f49 | 2671 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2672 | else if (len <= (low_size + high_size)) |
2673 | { | |
3d7f4f49 MK |
2674 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2675 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2676 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2677 | } |
2678 | else | |
8e65ff28 | 2679 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2680 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2681 | } |
2682 | } | |
fc338970 | 2683 | \f |
ef9dff19 | 2684 | |
8201327c MK |
2685 | /* This is the variable that is set with "set struct-convention", and |
2686 | its legitimate values. */ | |
2687 | static const char default_struct_convention[] = "default"; | |
2688 | static const char pcc_struct_convention[] = "pcc"; | |
2689 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2690 | static const char *const valid_conventions[] = |
8201327c MK |
2691 | { |
2692 | default_struct_convention, | |
2693 | pcc_struct_convention, | |
2694 | reg_struct_convention, | |
2695 | NULL | |
2696 | }; | |
2697 | static const char *struct_convention = default_struct_convention; | |
2698 | ||
0e4377e1 JB |
2699 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2700 | a union type, or an array type, should be returned in registers | |
2701 | for architecture GDBARCH. */ | |
c5e656c1 | 2702 | |
8201327c | 2703 | static int |
c5e656c1 | 2704 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2705 | { |
c5e656c1 MK |
2706 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2707 | enum type_code code = TYPE_CODE (type); | |
2708 | int len = TYPE_LENGTH (type); | |
8201327c | 2709 | |
0e4377e1 JB |
2710 | gdb_assert (code == TYPE_CODE_STRUCT |
2711 | || code == TYPE_CODE_UNION | |
2712 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2713 | |
2714 | if (struct_convention == pcc_struct_convention | |
2715 | || (struct_convention == default_struct_convention | |
2716 | && tdep->struct_return == pcc_struct_return)) | |
2717 | return 0; | |
2718 | ||
9edde48e MK |
2719 | /* Structures consisting of a single `float', `double' or 'long |
2720 | double' member are returned in %st(0). */ | |
2721 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2722 | { | |
2723 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2724 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2725 | return (len == 4 || len == 8 || len == 12); | |
2726 | } | |
2727 | ||
c5e656c1 MK |
2728 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2729 | } | |
2730 | ||
2731 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2732 | should be returned. If it is supposed to be returned in registers, | |
2733 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2734 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2735 | from WRITEBUF into REGCACHE. */ | |
2736 | ||
2737 | static enum return_value_convention | |
6a3a010b | 2738 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2739 | struct type *type, struct regcache *regcache, |
2740 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2741 | { |
2742 | enum type_code code = TYPE_CODE (type); | |
2743 | ||
5daa78cc TJB |
2744 | if (((code == TYPE_CODE_STRUCT |
2745 | || code == TYPE_CODE_UNION | |
2746 | || code == TYPE_CODE_ARRAY) | |
2747 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2445fd7b MK |
2748 | /* Complex double and long double uses the struct return covention. */ |
2749 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) | |
2750 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2751 | /* 128-bit decimal float uses the struct return convention. */ |
2752 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2753 | { |
2754 | /* The System V ABI says that: | |
2755 | ||
2756 | "A function that returns a structure or union also sets %eax | |
2757 | to the value of the original address of the caller's area | |
2758 | before it returns. Thus when the caller receives control | |
2759 | again, the address of the returned object resides in register | |
2760 | %eax and can be used to access the object." | |
2761 | ||
2762 | So the ABI guarantees that we can always find the return | |
2763 | value just after the function has returned. */ | |
2764 | ||
0e4377e1 JB |
2765 | /* Note that the ABI doesn't mention functions returning arrays, |
2766 | which is something possible in certain languages such as Ada. | |
2767 | In this case, the value is returned as if it was wrapped in | |
2768 | a record, so the convention applied to records also applies | |
2769 | to arrays. */ | |
2770 | ||
31db7b6c MK |
2771 | if (readbuf) |
2772 | { | |
2773 | ULONGEST addr; | |
2774 | ||
2775 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2776 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2777 | } | |
2778 | ||
2779 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2780 | } | |
c5e656c1 MK |
2781 | |
2782 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2783 | `float', `double' or 'long double' member. These structures are |
2784 | returned in %st(0). For these structures, we call ourselves | |
2785 | recursively, changing TYPE into the type of the first member of | |
2786 | the structure. Since that should work for all structures that | |
2787 | have only one member, we don't bother to check the member's type | |
2788 | here. */ | |
c5e656c1 MK |
2789 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2790 | { | |
2791 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
6a3a010b | 2792 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 2793 | readbuf, writebuf); |
c5e656c1 MK |
2794 | } |
2795 | ||
2796 | if (readbuf) | |
2797 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2798 | if (writebuf) | |
2799 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2800 | |
c5e656c1 | 2801 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2802 | } |
2803 | \f | |
2804 | ||
27067745 UW |
2805 | struct type * |
2806 | i387_ext_type (struct gdbarch *gdbarch) | |
2807 | { | |
2808 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2809 | ||
2810 | if (!tdep->i387_ext_type) | |
90884b2b L |
2811 | { |
2812 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2813 | gdb_assert (tdep->i387_ext_type != NULL); | |
2814 | } | |
27067745 UW |
2815 | |
2816 | return tdep->i387_ext_type; | |
2817 | } | |
2818 | ||
1dbcd68c WT |
2819 | /* Construct type for pseudo BND registers. We can't use |
2820 | tdesc_find_type since a complement of one value has to be used | |
2821 | to describe the upper bound. */ | |
2822 | ||
2823 | static struct type * | |
2824 | i386_bnd_type (struct gdbarch *gdbarch) | |
2825 | { | |
2826 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2827 | ||
2828 | ||
2829 | if (!tdep->i386_bnd_type) | |
2830 | { | |
2831 | struct type *t, *bound_t; | |
2832 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2833 | ||
2834 | /* The type we're building is described bellow: */ | |
2835 | #if 0 | |
2836 | struct __bound128 | |
2837 | { | |
2838 | void *lbound; | |
2839 | void *ubound; /* One complement of raw ubound field. */ | |
2840 | }; | |
2841 | #endif | |
2842 | ||
2843 | t = arch_composite_type (gdbarch, | |
2844 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
2845 | ||
2846 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
2847 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
2848 | ||
2849 | TYPE_NAME (t) = "builtin_type_bound128"; | |
2850 | tdep->i386_bnd_type = t; | |
2851 | } | |
2852 | ||
2853 | return tdep->i386_bnd_type; | |
2854 | } | |
2855 | ||
c131fcee L |
2856 | /* Construct vector type for pseudo YMM registers. We can't use |
2857 | tdesc_find_type since YMM isn't described in target description. */ | |
2858 | ||
2859 | static struct type * | |
2860 | i386_ymm_type (struct gdbarch *gdbarch) | |
2861 | { | |
2862 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2863 | ||
2864 | if (!tdep->i386_ymm_type) | |
2865 | { | |
2866 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2867 | ||
2868 | /* The type we're building is this: */ | |
2869 | #if 0 | |
2870 | union __gdb_builtin_type_vec256i | |
2871 | { | |
2872 | int128_t uint128[2]; | |
2873 | int64_t v2_int64[4]; | |
2874 | int32_t v4_int32[8]; | |
2875 | int16_t v8_int16[16]; | |
2876 | int8_t v16_int8[32]; | |
2877 | double v2_double[4]; | |
2878 | float v4_float[8]; | |
2879 | }; | |
2880 | #endif | |
2881 | ||
2882 | struct type *t; | |
2883 | ||
2884 | t = arch_composite_type (gdbarch, | |
2885 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2886 | append_composite_type_field (t, "v8_float", | |
2887 | init_vector_type (bt->builtin_float, 8)); | |
2888 | append_composite_type_field (t, "v4_double", | |
2889 | init_vector_type (bt->builtin_double, 4)); | |
2890 | append_composite_type_field (t, "v32_int8", | |
2891 | init_vector_type (bt->builtin_int8, 32)); | |
2892 | append_composite_type_field (t, "v16_int16", | |
2893 | init_vector_type (bt->builtin_int16, 16)); | |
2894 | append_composite_type_field (t, "v8_int32", | |
2895 | init_vector_type (bt->builtin_int32, 8)); | |
2896 | append_composite_type_field (t, "v4_int64", | |
2897 | init_vector_type (bt->builtin_int64, 4)); | |
2898 | append_composite_type_field (t, "v2_int128", | |
2899 | init_vector_type (bt->builtin_int128, 2)); | |
2900 | ||
2901 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 2902 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
2903 | tdep->i386_ymm_type = t; |
2904 | } | |
2905 | ||
2906 | return tdep->i386_ymm_type; | |
2907 | } | |
2908 | ||
794ac428 | 2909 | /* Construct vector type for MMX registers. */ |
90884b2b | 2910 | static struct type * |
794ac428 UW |
2911 | i386_mmx_type (struct gdbarch *gdbarch) |
2912 | { | |
2913 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2914 | ||
2915 | if (!tdep->i386_mmx_type) | |
2916 | { | |
df4df182 UW |
2917 | const struct builtin_type *bt = builtin_type (gdbarch); |
2918 | ||
794ac428 UW |
2919 | /* The type we're building is this: */ |
2920 | #if 0 | |
2921 | union __gdb_builtin_type_vec64i | |
2922 | { | |
2923 | int64_t uint64; | |
2924 | int32_t v2_int32[2]; | |
2925 | int16_t v4_int16[4]; | |
2926 | int8_t v8_int8[8]; | |
2927 | }; | |
2928 | #endif | |
2929 | ||
2930 | struct type *t; | |
2931 | ||
e9bb382b UW |
2932 | t = arch_composite_type (gdbarch, |
2933 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2934 | |
2935 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2936 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2937 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2938 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2939 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2940 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2941 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2942 | |
876cecd0 | 2943 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2944 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2945 | tdep->i386_mmx_type = t; | |
2946 | } | |
2947 | ||
2948 | return tdep->i386_mmx_type; | |
2949 | } | |
2950 | ||
d7a0d72c | 2951 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 2952 | register REGNUM. */ |
d7a0d72c | 2953 | |
fff4548b | 2954 | struct type * |
90884b2b | 2955 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2956 | { |
1dbcd68c WT |
2957 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
2958 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
2959 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2960 | return i386_mmx_type (gdbarch); | |
c131fcee L |
2961 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
2962 | return i386_ymm_type (gdbarch); | |
1ba53b71 L |
2963 | else |
2964 | { | |
2965 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2966 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2967 | return bt->builtin_int8; | |
2968 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2969 | return bt->builtin_int16; | |
2970 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2971 | return bt->builtin_int32; | |
2972 | } | |
2973 | ||
2974 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2975 | } |
2976 | ||
28fc6740 | 2977 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2978 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2979 | |
2980 | static int | |
c86c27af | 2981 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2982 | { |
5716833c MK |
2983 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2984 | int mmxreg, fpreg; | |
28fc6740 AC |
2985 | ULONGEST fstat; |
2986 | int tos; | |
c86c27af | 2987 | |
5716833c | 2988 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2989 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2990 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2991 | fpreg = (mmxreg + tos) % 8; |
2992 | ||
20a6ec49 | 2993 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2994 | } |
2995 | ||
3543a589 TT |
2996 | /* A helper function for us by i386_pseudo_register_read_value and |
2997 | amd64_pseudo_register_read_value. It does all the work but reads | |
2998 | the data into an already-allocated value. */ | |
2999 | ||
3000 | void | |
3001 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
3002 | struct regcache *regcache, | |
3003 | int regnum, | |
3004 | struct value *result_value) | |
28fc6740 | 3005 | { |
1ba53b71 | 3006 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 3007 | enum register_status status; |
3543a589 | 3008 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 3009 | |
5716833c | 3010 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3011 | { |
c86c27af MK |
3012 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3013 | ||
28fc6740 | 3014 | /* Extract (always little endian). */ |
05d1431c PA |
3015 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
3016 | if (status != REG_VALID) | |
3543a589 TT |
3017 | mark_value_bytes_unavailable (result_value, 0, |
3018 | TYPE_LENGTH (value_type (result_value))); | |
3019 | else | |
3020 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3021 | } |
3022 | else | |
1ba53b71 L |
3023 | { |
3024 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dbcd68c WT |
3025 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3026 | { | |
3027 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3028 | |
1dbcd68c WT |
3029 | /* Extract (always little endian). Read lower 128bits. */ |
3030 | status = regcache_raw_read (regcache, | |
3031 | I387_BND0R_REGNUM (tdep) + regnum, | |
3032 | raw_buf); | |
3033 | if (status != REG_VALID) | |
3034 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3035 | else | |
3036 | { | |
3037 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3038 | LONGEST upper, lower; | |
3039 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3040 | ||
3041 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3042 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3043 | upper = ~upper; | |
3044 | ||
3045 | memcpy (buf, &lower, size); | |
3046 | memcpy (buf + size, &upper, size); | |
3047 | } | |
3048 | } | |
3049 | else if (i386_ymm_regnum_p (gdbarch, regnum)) | |
c131fcee L |
3050 | { |
3051 | regnum -= tdep->ymm0_regnum; | |
3052 | ||
1777feb0 | 3053 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
3054 | status = regcache_raw_read (regcache, |
3055 | I387_XMM0_REGNUM (tdep) + regnum, | |
3056 | raw_buf); | |
3057 | if (status != REG_VALID) | |
3543a589 TT |
3058 | mark_value_bytes_unavailable (result_value, 0, 16); |
3059 | else | |
3060 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3061 | /* Read upper 128bits. */ |
05d1431c PA |
3062 | status = regcache_raw_read (regcache, |
3063 | tdep->ymm0h_regnum + regnum, | |
3064 | raw_buf); | |
3065 | if (status != REG_VALID) | |
3543a589 TT |
3066 | mark_value_bytes_unavailable (result_value, 16, 32); |
3067 | else | |
3068 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee L |
3069 | } |
3070 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
3071 | { |
3072 | int gpnum = regnum - tdep->ax_regnum; | |
3073 | ||
3074 | /* Extract (always little endian). */ | |
05d1431c PA |
3075 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
3076 | if (status != REG_VALID) | |
3543a589 TT |
3077 | mark_value_bytes_unavailable (result_value, 0, |
3078 | TYPE_LENGTH (value_type (result_value))); | |
3079 | else | |
3080 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3081 | } |
3082 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3083 | { | |
3084 | /* Check byte pseudo registers last since this function will | |
3085 | be called from amd64_pseudo_register_read, which handles | |
3086 | byte pseudo registers differently. */ | |
3087 | int gpnum = regnum - tdep->al_regnum; | |
3088 | ||
3089 | /* Extract (always little endian). We read both lower and | |
3090 | upper registers. */ | |
05d1431c PA |
3091 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
3092 | if (status != REG_VALID) | |
3543a589 TT |
3093 | mark_value_bytes_unavailable (result_value, 0, |
3094 | TYPE_LENGTH (value_type (result_value))); | |
3095 | else if (gpnum >= 4) | |
1ba53b71 L |
3096 | memcpy (buf, raw_buf + 1, 1); |
3097 | else | |
3098 | memcpy (buf, raw_buf, 1); | |
3099 | } | |
3100 | else | |
3101 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3102 | } | |
3543a589 TT |
3103 | } |
3104 | ||
3105 | static struct value * | |
3106 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
3107 | struct regcache *regcache, | |
3108 | int regnum) | |
3109 | { | |
3110 | struct value *result; | |
3111 | ||
3112 | result = allocate_value (register_type (gdbarch, regnum)); | |
3113 | VALUE_LVAL (result) = lval_register; | |
3114 | VALUE_REGNUM (result) = regnum; | |
3115 | ||
3116 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3117 | |
3543a589 | 3118 | return result; |
28fc6740 AC |
3119 | } |
3120 | ||
1ba53b71 | 3121 | void |
28fc6740 | 3122 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3123 | int regnum, const gdb_byte *buf) |
28fc6740 | 3124 | { |
1ba53b71 L |
3125 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
3126 | ||
5716833c | 3127 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3128 | { |
c86c27af MK |
3129 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3130 | ||
28fc6740 | 3131 | /* Read ... */ |
1ba53b71 | 3132 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 3133 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3134 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3135 | /* ... Write. */ |
1ba53b71 | 3136 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
3137 | } |
3138 | else | |
1ba53b71 L |
3139 | { |
3140 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3141 | ||
1dbcd68c WT |
3142 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3143 | { | |
3144 | ULONGEST upper, lower; | |
3145 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3146 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3147 | ||
3148 | /* New values from input value. */ | |
3149 | regnum -= tdep->bnd0_regnum; | |
3150 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3151 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3152 | ||
3153 | /* Fetching register buffer. */ | |
3154 | regcache_raw_read (regcache, | |
3155 | I387_BND0R_REGNUM (tdep) + regnum, | |
3156 | raw_buf); | |
3157 | ||
3158 | upper = ~upper; | |
3159 | ||
3160 | /* Set register bits. */ | |
3161 | memcpy (raw_buf, &lower, 8); | |
3162 | memcpy (raw_buf + 8, &upper, 8); | |
3163 | ||
3164 | ||
3165 | regcache_raw_write (regcache, | |
3166 | I387_BND0R_REGNUM (tdep) + regnum, | |
3167 | raw_buf); | |
3168 | } | |
3169 | else if (i386_ymm_regnum_p (gdbarch, regnum)) | |
c131fcee L |
3170 | { |
3171 | regnum -= tdep->ymm0_regnum; | |
3172 | ||
3173 | /* ... Write lower 128bits. */ | |
3174 | regcache_raw_write (regcache, | |
3175 | I387_XMM0_REGNUM (tdep) + regnum, | |
3176 | buf); | |
3177 | /* ... Write upper 128bits. */ | |
3178 | regcache_raw_write (regcache, | |
3179 | tdep->ymm0h_regnum + regnum, | |
3180 | buf + 16); | |
3181 | } | |
3182 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
3183 | { |
3184 | int gpnum = regnum - tdep->ax_regnum; | |
3185 | ||
3186 | /* Read ... */ | |
3187 | regcache_raw_read (regcache, gpnum, raw_buf); | |
3188 | /* ... Modify ... (always little endian). */ | |
3189 | memcpy (raw_buf, buf, 2); | |
3190 | /* ... Write. */ | |
3191 | regcache_raw_write (regcache, gpnum, raw_buf); | |
3192 | } | |
3193 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3194 | { | |
3195 | /* Check byte pseudo registers last since this function will | |
3196 | be called from amd64_pseudo_register_read, which handles | |
3197 | byte pseudo registers differently. */ | |
3198 | int gpnum = regnum - tdep->al_regnum; | |
3199 | ||
3200 | /* Read ... We read both lower and upper registers. */ | |
3201 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
3202 | /* ... Modify ... (always little endian). */ | |
3203 | if (gpnum >= 4) | |
3204 | memcpy (raw_buf + 1, buf, 1); | |
3205 | else | |
3206 | memcpy (raw_buf, buf, 1); | |
3207 | /* ... Write. */ | |
3208 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
3209 | } | |
3210 | else | |
3211 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3212 | } | |
28fc6740 | 3213 | } |
ff2e87ac AC |
3214 | \f |
3215 | ||
ff2e87ac AC |
3216 | /* Return the register number of the register allocated by GCC after |
3217 | REGNUM, or -1 if there is no such register. */ | |
3218 | ||
3219 | static int | |
3220 | i386_next_regnum (int regnum) | |
3221 | { | |
3222 | /* GCC allocates the registers in the order: | |
3223 | ||
3224 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3225 | ||
3226 | Since storing a variable in %esp doesn't make any sense we return | |
3227 | -1 for %ebp and for %esp itself. */ | |
3228 | static int next_regnum[] = | |
3229 | { | |
3230 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3231 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3232 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3233 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3234 | -1, -1, /* Slots for %esp and %ebp. */ | |
3235 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3236 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3237 | }; | |
3238 | ||
de5b9bb9 | 3239 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3240 | return next_regnum[regnum]; |
28fc6740 | 3241 | |
ff2e87ac AC |
3242 | return -1; |
3243 | } | |
3244 | ||
3245 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3246 | needs any special handling. */ | |
d7a0d72c | 3247 | |
3a1e71e3 | 3248 | static int |
1777feb0 MS |
3249 | i386_convert_register_p (struct gdbarch *gdbarch, |
3250 | int regnum, struct type *type) | |
d7a0d72c | 3251 | { |
de5b9bb9 MK |
3252 | int len = TYPE_LENGTH (type); |
3253 | ||
ff2e87ac AC |
3254 | /* Values may be spread across multiple registers. Most debugging |
3255 | formats aren't expressive enough to specify the locations, so | |
3256 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3257 | have a length that is a multiple of the word size, since GCC |
3258 | doesn't seem to put any other types into registers. */ | |
3259 | if (len > 4 && len % 4 == 0) | |
3260 | { | |
3261 | int last_regnum = regnum; | |
3262 | ||
3263 | while (len > 4) | |
3264 | { | |
3265 | last_regnum = i386_next_regnum (last_regnum); | |
3266 | len -= 4; | |
3267 | } | |
3268 | ||
3269 | if (last_regnum != -1) | |
3270 | return 1; | |
3271 | } | |
ff2e87ac | 3272 | |
0abe36f5 | 3273 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3274 | } |
3275 | ||
ff2e87ac AC |
3276 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3277 | return its contents in TO. */ | |
ac27f131 | 3278 | |
8dccd430 | 3279 | static int |
ff2e87ac | 3280 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3281 | struct type *type, gdb_byte *to, |
3282 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3283 | { |
20a6ec49 | 3284 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3285 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3286 | |
20a6ec49 | 3287 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3288 | return i387_register_to_value (frame, regnum, type, to, |
3289 | optimizedp, unavailablep); | |
ff2e87ac | 3290 | |
fd35795f | 3291 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3292 | |
3293 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3294 | |
de5b9bb9 MK |
3295 | while (len > 0) |
3296 | { | |
3297 | gdb_assert (regnum != -1); | |
20a6ec49 | 3298 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3299 | |
8dccd430 PA |
3300 | if (!get_frame_register_bytes (frame, regnum, 0, |
3301 | register_size (gdbarch, regnum), | |
3302 | to, optimizedp, unavailablep)) | |
3303 | return 0; | |
3304 | ||
de5b9bb9 MK |
3305 | regnum = i386_next_regnum (regnum); |
3306 | len -= 4; | |
42835c2b | 3307 | to += 4; |
de5b9bb9 | 3308 | } |
8dccd430 PA |
3309 | |
3310 | *optimizedp = *unavailablep = 0; | |
3311 | return 1; | |
ac27f131 MK |
3312 | } |
3313 | ||
ff2e87ac AC |
3314 | /* Write the contents FROM of a value of type TYPE into register |
3315 | REGNUM in frame FRAME. */ | |
ac27f131 | 3316 | |
3a1e71e3 | 3317 | static void |
ff2e87ac | 3318 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3319 | struct type *type, const gdb_byte *from) |
ac27f131 | 3320 | { |
de5b9bb9 | 3321 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3322 | |
20a6ec49 | 3323 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3324 | { |
d532c08f MK |
3325 | i387_value_to_register (frame, regnum, type, from); |
3326 | return; | |
3327 | } | |
3d261580 | 3328 | |
fd35795f | 3329 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3330 | |
3331 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3332 | |
de5b9bb9 MK |
3333 | while (len > 0) |
3334 | { | |
3335 | gdb_assert (regnum != -1); | |
875f8d0e | 3336 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3337 | |
42835c2b | 3338 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3339 | regnum = i386_next_regnum (regnum); |
3340 | len -= 4; | |
42835c2b | 3341 | from += 4; |
de5b9bb9 | 3342 | } |
ac27f131 | 3343 | } |
ff2e87ac | 3344 | \f |
7fdafb5a MK |
3345 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3346 | in the general-purpose register set REGSET to register cache | |
3347 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3348 | |
20187ed5 | 3349 | void |
473f17b0 MK |
3350 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3351 | int regnum, const void *gregs, size_t len) | |
3352 | { | |
9ea75c57 | 3353 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 3354 | const gdb_byte *regs = gregs; |
473f17b0 MK |
3355 | int i; |
3356 | ||
3357 | gdb_assert (len == tdep->sizeof_gregset); | |
3358 | ||
3359 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3360 | { | |
3361 | if ((regnum == i || regnum == -1) | |
3362 | && tdep->gregset_reg_offset[i] != -1) | |
3363 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3364 | } | |
3365 | } | |
3366 | ||
7fdafb5a MK |
3367 | /* Collect register REGNUM from the register cache REGCACHE and store |
3368 | it in the buffer specified by GREGS and LEN as described by the | |
3369 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3370 | all registers in REGSET. */ | |
3371 | ||
3372 | void | |
3373 | i386_collect_gregset (const struct regset *regset, | |
3374 | const struct regcache *regcache, | |
3375 | int regnum, void *gregs, size_t len) | |
3376 | { | |
3377 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 3378 | gdb_byte *regs = gregs; |
7fdafb5a MK |
3379 | int i; |
3380 | ||
3381 | gdb_assert (len == tdep->sizeof_gregset); | |
3382 | ||
3383 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3384 | { | |
3385 | if ((regnum == i || regnum == -1) | |
3386 | && tdep->gregset_reg_offset[i] != -1) | |
3387 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3388 | } | |
3389 | } | |
3390 | ||
3391 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3392 | in the floating-point register set REGSET to register cache | |
3393 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3394 | |
3395 | static void | |
3396 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3397 | int regnum, const void *fpregs, size_t len) | |
3398 | { | |
9ea75c57 | 3399 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 3400 | |
66a72d25 MK |
3401 | if (len == I387_SIZEOF_FXSAVE) |
3402 | { | |
3403 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3404 | return; | |
3405 | } | |
3406 | ||
473f17b0 MK |
3407 | gdb_assert (len == tdep->sizeof_fpregset); |
3408 | i387_supply_fsave (regcache, regnum, fpregs); | |
3409 | } | |
8446b36a | 3410 | |
2f305df1 MK |
3411 | /* Collect register REGNUM from the register cache REGCACHE and store |
3412 | it in the buffer specified by FPREGS and LEN as described by the | |
3413 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3414 | all registers in REGSET. */ | |
7fdafb5a MK |
3415 | |
3416 | static void | |
3417 | i386_collect_fpregset (const struct regset *regset, | |
3418 | const struct regcache *regcache, | |
3419 | int regnum, void *fpregs, size_t len) | |
3420 | { | |
3421 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
3422 | ||
3423 | if (len == I387_SIZEOF_FXSAVE) | |
3424 | { | |
3425 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3426 | return; | |
3427 | } | |
3428 | ||
3429 | gdb_assert (len == tdep->sizeof_fpregset); | |
3430 | i387_collect_fsave (regcache, regnum, fpregs); | |
3431 | } | |
3432 | ||
c131fcee L |
3433 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
3434 | ||
3435 | static void | |
3436 | i386_supply_xstateregset (const struct regset *regset, | |
3437 | struct regcache *regcache, int regnum, | |
3438 | const void *xstateregs, size_t len) | |
3439 | { | |
c131fcee L |
3440 | i387_supply_xsave (regcache, regnum, xstateregs); |
3441 | } | |
3442 | ||
3443 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
3444 | ||
3445 | static void | |
3446 | i386_collect_xstateregset (const struct regset *regset, | |
3447 | const struct regcache *regcache, | |
3448 | int regnum, void *xstateregs, size_t len) | |
3449 | { | |
c131fcee L |
3450 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
3451 | } | |
3452 | ||
8446b36a MK |
3453 | /* Return the appropriate register set for the core section identified |
3454 | by SECT_NAME and SECT_SIZE. */ | |
3455 | ||
3456 | const struct regset * | |
3457 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
3458 | const char *sect_name, size_t sect_size) | |
3459 | { | |
3460 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3461 | ||
3462 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
3463 | { | |
3464 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
3465 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
3466 | i386_collect_gregset); | |
8446b36a MK |
3467 | return tdep->gregset; |
3468 | } | |
3469 | ||
66a72d25 MK |
3470 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
3471 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
3472 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
3473 | { |
3474 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
3475 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
3476 | i386_collect_fpregset); | |
8446b36a MK |
3477 | return tdep->fpregset; |
3478 | } | |
3479 | ||
c131fcee L |
3480 | if (strcmp (sect_name, ".reg-xstate") == 0) |
3481 | { | |
3482 | if (tdep->xstateregset == NULL) | |
3483 | tdep->xstateregset = regset_alloc (gdbarch, | |
3484 | i386_supply_xstateregset, | |
3485 | i386_collect_xstateregset); | |
3486 | ||
3487 | return tdep->xstateregset; | |
3488 | } | |
3489 | ||
8446b36a MK |
3490 | return NULL; |
3491 | } | |
473f17b0 | 3492 | \f |
fc338970 | 3493 | |
fc338970 | 3494 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3495 | |
3496 | CORE_ADDR | |
e17a4113 UW |
3497 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3498 | CORE_ADDR pc, char *name) | |
c906108c | 3499 | { |
e17a4113 UW |
3500 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3501 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3502 | ||
3503 | /* jmp *(dest) */ | |
3504 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3505 | { |
e17a4113 UW |
3506 | unsigned long indirect = |
3507 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3508 | struct minimal_symbol *indsym = |
7cbd4a93 | 3509 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
0d5cff50 | 3510 | const char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3511 | |
c5aa993b | 3512 | if (symname) |
c906108c | 3513 | { |
c5aa993b JM |
3514 | if (strncmp (symname, "__imp_", 6) == 0 |
3515 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
3516 | return name ? 1 : |
3517 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3518 | } |
3519 | } | |
fc338970 | 3520 | return 0; /* Not a trampoline. */ |
c906108c | 3521 | } |
fc338970 MK |
3522 | \f |
3523 | ||
10458914 DJ |
3524 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3525 | routine. */ | |
8201327c | 3526 | |
4bd207ef | 3527 | int |
10458914 | 3528 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3529 | { |
10458914 | 3530 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3531 | const char *name; |
911bc6ee MK |
3532 | |
3533 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3534 | return (name && strcmp ("_sigtramp", name) == 0); |
3535 | } | |
3536 | \f | |
3537 | ||
fc338970 MK |
3538 | /* We have two flavours of disassembly. The machinery on this page |
3539 | deals with switching between those. */ | |
c906108c SS |
3540 | |
3541 | static int | |
a89aa300 | 3542 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3543 | { |
5e3397bb MK |
3544 | gdb_assert (disassembly_flavor == att_flavor |
3545 | || disassembly_flavor == intel_flavor); | |
3546 | ||
3547 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3548 | constified, cast to prevent a compiler warning. */ | |
3549 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3550 | |
3551 | return print_insn_i386 (pc, info); | |
7a292a7a | 3552 | } |
fc338970 | 3553 | \f |
3ce1502b | 3554 | |
8201327c MK |
3555 | /* There are a few i386 architecture variants that differ only |
3556 | slightly from the generic i386 target. For now, we don't give them | |
3557 | their own source file, but include them here. As a consequence, | |
3558 | they'll always be included. */ | |
3ce1502b | 3559 | |
8201327c | 3560 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3561 | |
10458914 DJ |
3562 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3563 | routine. */ | |
911bc6ee | 3564 | |
8201327c | 3565 | static int |
10458914 | 3566 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3567 | { |
10458914 | 3568 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3569 | const char *name; |
911bc6ee | 3570 | |
05b4bd79 | 3571 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 3572 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 3573 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
3574 | || strcmp ("sigvechandler", name) == 0)); |
3575 | } | |
d2a7c97a | 3576 | |
10458914 DJ |
3577 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3578 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3579 | |
3a1e71e3 | 3580 | static CORE_ADDR |
10458914 | 3581 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3582 | { |
e17a4113 UW |
3583 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3584 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3585 | gdb_byte buf[4]; |
acd5c798 | 3586 | CORE_ADDR sp; |
3ce1502b | 3587 | |
10458914 | 3588 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3589 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3590 | |
e17a4113 | 3591 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 3592 | } |
55aa24fb SDJ |
3593 | |
3594 | \f | |
3595 | ||
3596 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
3597 | gdbarch.h. */ | |
3598 | ||
3599 | int | |
3600 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
3601 | { | |
3602 | return (*s == '$' /* Literal number. */ | |
3603 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
3604 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
3605 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
3606 | } | |
3607 | ||
3608 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in | |
3609 | gdbarch.h. */ | |
3610 | ||
3611 | int | |
3612 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
3613 | struct stap_parse_info *p) | |
3614 | { | |
55aa24fb SDJ |
3615 | /* In order to parse special tokens, we use a state-machine that go |
3616 | through every known token and try to get a match. */ | |
3617 | enum | |
3618 | { | |
3619 | TRIPLET, | |
3620 | THREE_ARG_DISPLACEMENT, | |
3621 | DONE | |
3622 | } current_state; | |
3623 | ||
3624 | current_state = TRIPLET; | |
3625 | ||
3626 | /* The special tokens to be parsed here are: | |
3627 | ||
3628 | - `register base + (register index * size) + offset', as represented | |
3629 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
3630 | ||
3631 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
3632 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
3633 | ||
3634 | while (current_state != DONE) | |
3635 | { | |
3636 | const char *s = p->arg; | |
3637 | ||
3638 | switch (current_state) | |
3639 | { | |
3640 | case TRIPLET: | |
3641 | { | |
3642 | if (isdigit (*s) || *s == '-' || *s == '+') | |
3643 | { | |
3644 | int got_minus[3]; | |
3645 | int i; | |
3646 | long displacements[3]; | |
3647 | const char *start; | |
3648 | char *regname; | |
3649 | int len; | |
3650 | struct stoken str; | |
a0bcdaa7 | 3651 | char *endp; |
55aa24fb SDJ |
3652 | |
3653 | got_minus[0] = 0; | |
3654 | if (*s == '+') | |
3655 | ++s; | |
3656 | else if (*s == '-') | |
3657 | { | |
3658 | ++s; | |
3659 | got_minus[0] = 1; | |
3660 | } | |
3661 | ||
a0bcdaa7 PA |
3662 | displacements[0] = strtol (s, &endp, 10); |
3663 | s = endp; | |
55aa24fb SDJ |
3664 | |
3665 | if (*s != '+' && *s != '-') | |
3666 | { | |
3667 | /* We are not dealing with a triplet. */ | |
3668 | break; | |
3669 | } | |
3670 | ||
3671 | got_minus[1] = 0; | |
3672 | if (*s == '+') | |
3673 | ++s; | |
3674 | else | |
3675 | { | |
3676 | ++s; | |
3677 | got_minus[1] = 1; | |
3678 | } | |
3679 | ||
a0bcdaa7 PA |
3680 | displacements[1] = strtol (s, &endp, 10); |
3681 | s = endp; | |
55aa24fb SDJ |
3682 | |
3683 | if (*s != '+' && *s != '-') | |
3684 | { | |
3685 | /* We are not dealing with a triplet. */ | |
3686 | break; | |
3687 | } | |
3688 | ||
3689 | got_minus[2] = 0; | |
3690 | if (*s == '+') | |
3691 | ++s; | |
3692 | else | |
3693 | { | |
3694 | ++s; | |
3695 | got_minus[2] = 1; | |
3696 | } | |
3697 | ||
a0bcdaa7 PA |
3698 | displacements[2] = strtol (s, &endp, 10); |
3699 | s = endp; | |
55aa24fb SDJ |
3700 | |
3701 | if (*s != '(' || s[1] != '%') | |
3702 | break; | |
3703 | ||
3704 | s += 2; | |
3705 | start = s; | |
3706 | ||
3707 | while (isalnum (*s)) | |
3708 | ++s; | |
3709 | ||
3710 | if (*s++ != ')') | |
3711 | break; | |
3712 | ||
3713 | len = s - start; | |
3714 | regname = alloca (len + 1); | |
3715 | ||
3716 | strncpy (regname, start, len); | |
3717 | regname[len] = '\0'; | |
3718 | ||
3719 | if (user_reg_map_name_to_regnum (gdbarch, | |
3720 | regname, len) == -1) | |
3721 | error (_("Invalid register name `%s' " | |
3722 | "on expression `%s'."), | |
3723 | regname, p->saved_arg); | |
3724 | ||
3725 | for (i = 0; i < 3; i++) | |
3726 | { | |
3727 | write_exp_elt_opcode (OP_LONG); | |
3728 | write_exp_elt_type | |
3729 | (builtin_type (gdbarch)->builtin_long); | |
3730 | write_exp_elt_longcst (displacements[i]); | |
3731 | write_exp_elt_opcode (OP_LONG); | |
3732 | if (got_minus[i]) | |
3733 | write_exp_elt_opcode (UNOP_NEG); | |
3734 | } | |
3735 | ||
3736 | write_exp_elt_opcode (OP_REGISTER); | |
3737 | str.ptr = regname; | |
3738 | str.length = len; | |
3739 | write_exp_string (str); | |
3740 | write_exp_elt_opcode (OP_REGISTER); | |
3741 | ||
3742 | write_exp_elt_opcode (UNOP_CAST); | |
3743 | write_exp_elt_type (builtin_type (gdbarch)->builtin_data_ptr); | |
3744 | write_exp_elt_opcode (UNOP_CAST); | |
3745 | ||
3746 | write_exp_elt_opcode (BINOP_ADD); | |
3747 | write_exp_elt_opcode (BINOP_ADD); | |
3748 | write_exp_elt_opcode (BINOP_ADD); | |
3749 | ||
3750 | write_exp_elt_opcode (UNOP_CAST); | |
3751 | write_exp_elt_type (lookup_pointer_type (p->arg_type)); | |
3752 | write_exp_elt_opcode (UNOP_CAST); | |
3753 | ||
3754 | write_exp_elt_opcode (UNOP_IND); | |
3755 | ||
3756 | p->arg = s; | |
3757 | ||
3758 | return 1; | |
3759 | } | |
3760 | break; | |
3761 | } | |
3762 | case THREE_ARG_DISPLACEMENT: | |
3763 | { | |
3764 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
3765 | { | |
3766 | int offset_minus = 0; | |
3767 | long offset = 0; | |
3768 | int size_minus = 0; | |
3769 | long size = 0; | |
3770 | const char *start; | |
3771 | char *base; | |
3772 | int len_base; | |
3773 | char *index; | |
3774 | int len_index; | |
3775 | struct stoken base_token, index_token; | |
3776 | ||
3777 | if (*s == '+') | |
3778 | ++s; | |
3779 | else if (*s == '-') | |
3780 | { | |
3781 | ++s; | |
3782 | offset_minus = 1; | |
3783 | } | |
3784 | ||
3785 | if (offset_minus && !isdigit (*s)) | |
3786 | break; | |
3787 | ||
3788 | if (isdigit (*s)) | |
a0bcdaa7 PA |
3789 | { |
3790 | char *endp; | |
3791 | ||
3792 | offset = strtol (s, &endp, 10); | |
3793 | s = endp; | |
3794 | } | |
55aa24fb SDJ |
3795 | |
3796 | if (*s != '(' || s[1] != '%') | |
3797 | break; | |
3798 | ||
3799 | s += 2; | |
3800 | start = s; | |
3801 | ||
3802 | while (isalnum (*s)) | |
3803 | ++s; | |
3804 | ||
3805 | if (*s != ',' || s[1] != '%') | |
3806 | break; | |
3807 | ||
3808 | len_base = s - start; | |
3809 | base = alloca (len_base + 1); | |
3810 | strncpy (base, start, len_base); | |
3811 | base[len_base] = '\0'; | |
3812 | ||
3813 | if (user_reg_map_name_to_regnum (gdbarch, | |
3814 | base, len_base) == -1) | |
3815 | error (_("Invalid register name `%s' " | |
3816 | "on expression `%s'."), | |
3817 | base, p->saved_arg); | |
3818 | ||
3819 | s += 2; | |
3820 | start = s; | |
3821 | ||
3822 | while (isalnum (*s)) | |
3823 | ++s; | |
3824 | ||
3825 | len_index = s - start; | |
3826 | index = alloca (len_index + 1); | |
3827 | strncpy (index, start, len_index); | |
3828 | index[len_index] = '\0'; | |
3829 | ||
3830 | if (user_reg_map_name_to_regnum (gdbarch, | |
3831 | index, len_index) == -1) | |
3832 | error (_("Invalid register name `%s' " | |
3833 | "on expression `%s'."), | |
3834 | index, p->saved_arg); | |
3835 | ||
3836 | if (*s != ',' && *s != ')') | |
3837 | break; | |
3838 | ||
3839 | if (*s == ',') | |
3840 | { | |
a0bcdaa7 PA |
3841 | char *endp; |
3842 | ||
55aa24fb SDJ |
3843 | ++s; |
3844 | if (*s == '+') | |
3845 | ++s; | |
3846 | else if (*s == '-') | |
3847 | { | |
3848 | ++s; | |
3849 | size_minus = 1; | |
3850 | } | |
3851 | ||
a0bcdaa7 PA |
3852 | size = strtol (s, &endp, 10); |
3853 | s = endp; | |
55aa24fb SDJ |
3854 | |
3855 | if (*s != ')') | |
3856 | break; | |
3857 | } | |
3858 | ||
3859 | ++s; | |
3860 | ||
3861 | if (offset) | |
3862 | { | |
3863 | write_exp_elt_opcode (OP_LONG); | |
3864 | write_exp_elt_type | |
3865 | (builtin_type (gdbarch)->builtin_long); | |
3866 | write_exp_elt_longcst (offset); | |
3867 | write_exp_elt_opcode (OP_LONG); | |
3868 | if (offset_minus) | |
3869 | write_exp_elt_opcode (UNOP_NEG); | |
3870 | } | |
3871 | ||
3872 | write_exp_elt_opcode (OP_REGISTER); | |
3873 | base_token.ptr = base; | |
3874 | base_token.length = len_base; | |
3875 | write_exp_string (base_token); | |
3876 | write_exp_elt_opcode (OP_REGISTER); | |
3877 | ||
3878 | if (offset) | |
3879 | write_exp_elt_opcode (BINOP_ADD); | |
3880 | ||
3881 | write_exp_elt_opcode (OP_REGISTER); | |
3882 | index_token.ptr = index; | |
3883 | index_token.length = len_index; | |
3884 | write_exp_string (index_token); | |
3885 | write_exp_elt_opcode (OP_REGISTER); | |
3886 | ||
3887 | if (size) | |
3888 | { | |
3889 | write_exp_elt_opcode (OP_LONG); | |
3890 | write_exp_elt_type | |
3891 | (builtin_type (gdbarch)->builtin_long); | |
3892 | write_exp_elt_longcst (size); | |
3893 | write_exp_elt_opcode (OP_LONG); | |
3894 | if (size_minus) | |
3895 | write_exp_elt_opcode (UNOP_NEG); | |
3896 | write_exp_elt_opcode (BINOP_MUL); | |
3897 | } | |
3898 | ||
3899 | write_exp_elt_opcode (BINOP_ADD); | |
3900 | ||
3901 | write_exp_elt_opcode (UNOP_CAST); | |
3902 | write_exp_elt_type (lookup_pointer_type (p->arg_type)); | |
3903 | write_exp_elt_opcode (UNOP_CAST); | |
3904 | ||
3905 | write_exp_elt_opcode (UNOP_IND); | |
3906 | ||
3907 | p->arg = s; | |
3908 | ||
3909 | return 1; | |
3910 | } | |
3911 | break; | |
3912 | } | |
3913 | } | |
3914 | ||
3915 | /* Advancing to the next state. */ | |
3916 | ++current_state; | |
3917 | } | |
3918 | ||
3919 | return 0; | |
3920 | } | |
3921 | ||
8201327c | 3922 | \f |
3ce1502b | 3923 | |
8201327c | 3924 | /* Generic ELF. */ |
d2a7c97a | 3925 | |
8201327c MK |
3926 | void |
3927 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3928 | { | |
05c0465e SDJ |
3929 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
3930 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
3931 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
3932 | NULL }; | |
3933 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
3934 | NULL }; | |
3935 | ||
c4fc7f1b MK |
3936 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
3937 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
3938 | |
3939 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
3940 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
3941 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
3942 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
3943 | stap_register_indirection_prefixes); | |
3944 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
3945 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
3946 | set_gdbarch_stap_is_single_operand (gdbarch, |
3947 | i386_stap_is_single_operand); | |
3948 | set_gdbarch_stap_parse_special_token (gdbarch, | |
3949 | i386_stap_parse_special_token); | |
8201327c | 3950 | } |
3ce1502b | 3951 | |
8201327c | 3952 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3953 | |
8201327c MK |
3954 | void |
3955 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3956 | { | |
3957 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 3958 | |
8201327c MK |
3959 | /* System V Release 4 uses ELF. */ |
3960 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 3961 | |
dfe01d39 | 3962 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
3963 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
3964 | ||
911bc6ee | 3965 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 3966 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
3967 | tdep->sc_pc_offset = 36 + 14 * 4; |
3968 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 3969 | |
8201327c | 3970 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
3971 | } |
3972 | ||
8201327c | 3973 | /* DJGPP. */ |
3ce1502b | 3974 | |
3a1e71e3 | 3975 | static void |
8201327c | 3976 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 3977 | { |
8201327c | 3978 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 3979 | |
911bc6ee MK |
3980 | /* DJGPP doesn't have any special frames for signal handlers. */ |
3981 | tdep->sigtramp_p = NULL; | |
3ce1502b | 3982 | |
8201327c | 3983 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
3984 | |
3985 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
3986 | if (! tdesc_has_registers (info.target_desc)) |
3987 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
3988 | |
3989 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
3990 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
3991 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
3992 | set_gdbarch_sdb_reg_to_regnum. */ | |
3993 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3994 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
3995 | |
3996 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 3997 | } |
8201327c | 3998 | \f |
2acceee2 | 3999 | |
38c968cf AC |
4000 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4001 | and "sse". */ | |
4002 | ||
4003 | static struct reggroup *i386_sse_reggroup; | |
4004 | static struct reggroup *i386_mmx_reggroup; | |
4005 | ||
4006 | static void | |
4007 | i386_init_reggroups (void) | |
4008 | { | |
4009 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4010 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4011 | } | |
4012 | ||
4013 | static void | |
4014 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4015 | { | |
4016 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4017 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
4018 | reggroup_add (gdbarch, general_reggroup); | |
4019 | reggroup_add (gdbarch, float_reggroup); | |
4020 | reggroup_add (gdbarch, all_reggroup); | |
4021 | reggroup_add (gdbarch, save_reggroup); | |
4022 | reggroup_add (gdbarch, restore_reggroup); | |
4023 | reggroup_add (gdbarch, vector_reggroup); | |
4024 | reggroup_add (gdbarch, system_reggroup); | |
4025 | } | |
4026 | ||
4027 | int | |
4028 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
4029 | struct reggroup *group) | |
4030 | { | |
c131fcee L |
4031 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4032 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
1dbcd68c WT |
4033 | ymm_regnum_p, ymmh_regnum_p, bndr_regnum_p, bnd_regnum_p, |
4034 | mpx_ctrl_regnum_p; | |
acd5c798 | 4035 | |
1ba53b71 L |
4036 | /* Don't include pseudo registers, except for MMX, in any register |
4037 | groups. */ | |
c131fcee | 4038 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4039 | return 0; |
4040 | ||
c131fcee | 4041 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4042 | return 0; |
4043 | ||
c131fcee | 4044 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4045 | return 0; |
4046 | ||
4047 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4048 | if (group == i386_mmx_reggroup) |
4049 | return mmx_regnum_p; | |
1ba53b71 | 4050 | |
c131fcee L |
4051 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
4052 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); | |
38c968cf | 4053 | if (group == i386_sse_reggroup) |
c131fcee L |
4054 | return xmm_regnum_p || mxcsr_regnum_p; |
4055 | ||
4056 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
38c968cf | 4057 | if (group == vector_reggroup) |
c131fcee L |
4058 | return (mmx_regnum_p |
4059 | || ymm_regnum_p | |
4060 | || mxcsr_regnum_p | |
4061 | || (xmm_regnum_p | |
4062 | && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) | |
4063 | == I386_XSTATE_SSE_MASK))); | |
1ba53b71 L |
4064 | |
4065 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4066 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4067 | if (group == float_reggroup) |
4068 | return fp_regnum_p; | |
1ba53b71 | 4069 | |
c131fcee L |
4070 | /* For "info reg all", don't include upper YMM registers nor XMM |
4071 | registers when AVX is supported. */ | |
4072 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
4073 | if (group == all_reggroup | |
4074 | && ((xmm_regnum_p | |
4075 | && (tdep->xcr0 & I386_XSTATE_AVX)) | |
4076 | || ymmh_regnum_p)) | |
4077 | return 0; | |
4078 | ||
1dbcd68c WT |
4079 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4080 | if (group == all_reggroup | |
4081 | && ((bnd_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK)))) | |
4082 | return bnd_regnum_p; | |
4083 | ||
4084 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4085 | if (group == all_reggroup | |
4086 | && ((bndr_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK)))) | |
4087 | return 0; | |
4088 | ||
4089 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4090 | if (group == all_reggroup | |
4091 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK)))) | |
4092 | return mpx_ctrl_regnum_p; | |
4093 | ||
38c968cf | 4094 | if (group == general_reggroup) |
1ba53b71 L |
4095 | return (!fp_regnum_p |
4096 | && !mmx_regnum_p | |
c131fcee L |
4097 | && !mxcsr_regnum_p |
4098 | && !xmm_regnum_p | |
4099 | && !ymm_regnum_p | |
1dbcd68c WT |
4100 | && !ymmh_regnum_p |
4101 | && !bndr_regnum_p | |
4102 | && !bnd_regnum_p | |
4103 | && !mpx_ctrl_regnum_p); | |
acd5c798 | 4104 | |
38c968cf AC |
4105 | return default_register_reggroup_p (gdbarch, regnum, group); |
4106 | } | |
38c968cf | 4107 | \f |
acd5c798 | 4108 | |
f837910f MK |
4109 | /* Get the ARGIth function argument for the current function. */ |
4110 | ||
42c466d7 | 4111 | static CORE_ADDR |
143985b7 AF |
4112 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
4113 | struct type *type) | |
4114 | { | |
e17a4113 UW |
4115 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4116 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4117 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4118 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4119 | } |
4120 | ||
514f746b AR |
4121 | static void |
4122 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
4123 | { | |
4124 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
4125 | ||
4126 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
4127 | adjust the PC in the regcache. */ | |
4128 | current_pc += 1; | |
4129 | regcache_write_pc (regcache, current_pc); | |
4130 | } | |
4131 | ||
4132 | ||
7ad10968 HZ |
4133 | #define PREFIX_REPZ 0x01 |
4134 | #define PREFIX_REPNZ 0x02 | |
4135 | #define PREFIX_LOCK 0x04 | |
4136 | #define PREFIX_DATA 0x08 | |
4137 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4138 | |
7ad10968 HZ |
4139 | /* operand size */ |
4140 | enum | |
4141 | { | |
4142 | OT_BYTE = 0, | |
4143 | OT_WORD, | |
4144 | OT_LONG, | |
cf648174 | 4145 | OT_QUAD, |
a3c4230a | 4146 | OT_DQUAD, |
7ad10968 | 4147 | }; |
473f17b0 | 4148 | |
7ad10968 HZ |
4149 | /* i386 arith/logic operations */ |
4150 | enum | |
4151 | { | |
4152 | OP_ADDL, | |
4153 | OP_ORL, | |
4154 | OP_ADCL, | |
4155 | OP_SBBL, | |
4156 | OP_ANDL, | |
4157 | OP_SUBL, | |
4158 | OP_XORL, | |
4159 | OP_CMPL, | |
4160 | }; | |
5716833c | 4161 | |
7ad10968 HZ |
4162 | struct i386_record_s |
4163 | { | |
cf648174 | 4164 | struct gdbarch *gdbarch; |
7ad10968 | 4165 | struct regcache *regcache; |
df61f520 | 4166 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4167 | CORE_ADDR addr; |
4168 | int aflag; | |
4169 | int dflag; | |
4170 | int override; | |
4171 | uint8_t modrm; | |
4172 | uint8_t mod, reg, rm; | |
4173 | int ot; | |
cf648174 HZ |
4174 | uint8_t rex_x; |
4175 | uint8_t rex_b; | |
4176 | int rip_offset; | |
4177 | int popl_esp_hack; | |
4178 | const int *regmap; | |
7ad10968 | 4179 | }; |
5716833c | 4180 | |
99c1624c PA |
4181 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4182 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4183 | |
7ad10968 HZ |
4184 | static int |
4185 | i386_record_modrm (struct i386_record_s *irp) | |
4186 | { | |
cf648174 | 4187 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4188 | |
4ffa4fc7 PA |
4189 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4190 | return -1; | |
4191 | ||
7ad10968 HZ |
4192 | irp->addr++; |
4193 | irp->mod = (irp->modrm >> 6) & 3; | |
4194 | irp->reg = (irp->modrm >> 3) & 7; | |
4195 | irp->rm = irp->modrm & 7; | |
5716833c | 4196 | |
7ad10968 HZ |
4197 | return 0; |
4198 | } | |
d2a7c97a | 4199 | |
99c1624c PA |
4200 | /* Extract the memory address that the current instruction writes to, |
4201 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4202 | |
7ad10968 | 4203 | static int |
cf648174 | 4204 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4205 | { |
cf648174 | 4206 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4207 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4208 | gdb_byte buf[4]; | |
4209 | ULONGEST offset64; | |
21d0e8a4 | 4210 | |
7ad10968 HZ |
4211 | *addr = 0; |
4212 | if (irp->aflag) | |
4213 | { | |
4214 | /* 32 bits */ | |
4215 | int havesib = 0; | |
4216 | uint8_t scale = 0; | |
648d0c8b | 4217 | uint8_t byte; |
7ad10968 HZ |
4218 | uint8_t index = 0; |
4219 | uint8_t base = irp->rm; | |
896fb97d | 4220 | |
7ad10968 HZ |
4221 | if (base == 4) |
4222 | { | |
4223 | havesib = 1; | |
4ffa4fc7 PA |
4224 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4225 | return -1; | |
7ad10968 | 4226 | irp->addr++; |
648d0c8b MS |
4227 | scale = (byte >> 6) & 3; |
4228 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4229 | base = (byte & 7); | |
7ad10968 | 4230 | } |
cf648174 | 4231 | base |= irp->rex_b; |
21d0e8a4 | 4232 | |
7ad10968 HZ |
4233 | switch (irp->mod) |
4234 | { | |
4235 | case 0: | |
4236 | if ((base & 7) == 5) | |
4237 | { | |
4238 | base = 0xff; | |
4ffa4fc7 PA |
4239 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4240 | return -1; | |
7ad10968 | 4241 | irp->addr += 4; |
60a1502a | 4242 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4243 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4244 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4245 | } |
7ad10968 HZ |
4246 | break; |
4247 | case 1: | |
4ffa4fc7 PA |
4248 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4249 | return -1; | |
7ad10968 | 4250 | irp->addr++; |
60a1502a | 4251 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4252 | break; |
4253 | case 2: | |
4ffa4fc7 PA |
4254 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4255 | return -1; | |
60a1502a | 4256 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4257 | irp->addr += 4; |
4258 | break; | |
4259 | } | |
356a6b3e | 4260 | |
60a1502a | 4261 | offset64 = 0; |
7ad10968 | 4262 | if (base != 0xff) |
cf648174 HZ |
4263 | { |
4264 | if (base == 4 && irp->popl_esp_hack) | |
4265 | *addr += irp->popl_esp_hack; | |
4266 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4267 | &offset64); |
7ad10968 | 4268 | } |
cf648174 HZ |
4269 | if (irp->aflag == 2) |
4270 | { | |
60a1502a | 4271 | *addr += offset64; |
cf648174 HZ |
4272 | } |
4273 | else | |
60a1502a | 4274 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4275 | |
7ad10968 HZ |
4276 | if (havesib && (index != 4 || scale != 0)) |
4277 | { | |
cf648174 | 4278 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4279 | &offset64); |
cf648174 | 4280 | if (irp->aflag == 2) |
60a1502a | 4281 | *addr += offset64 << scale; |
cf648174 | 4282 | else |
60a1502a | 4283 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 HZ |
4284 | } |
4285 | } | |
4286 | else | |
4287 | { | |
4288 | /* 16 bits */ | |
4289 | switch (irp->mod) | |
4290 | { | |
4291 | case 0: | |
4292 | if (irp->rm == 6) | |
4293 | { | |
4ffa4fc7 PA |
4294 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4295 | return -1; | |
7ad10968 | 4296 | irp->addr += 2; |
60a1502a | 4297 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4298 | irp->rm = 0; |
4299 | goto no_rm; | |
4300 | } | |
7ad10968 HZ |
4301 | break; |
4302 | case 1: | |
4ffa4fc7 PA |
4303 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4304 | return -1; | |
7ad10968 | 4305 | irp->addr++; |
60a1502a | 4306 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4307 | break; |
4308 | case 2: | |
4ffa4fc7 PA |
4309 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4310 | return -1; | |
7ad10968 | 4311 | irp->addr += 2; |
60a1502a | 4312 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4313 | break; |
4314 | } | |
c4fc7f1b | 4315 | |
7ad10968 HZ |
4316 | switch (irp->rm) |
4317 | { | |
4318 | case 0: | |
cf648174 HZ |
4319 | regcache_raw_read_unsigned (irp->regcache, |
4320 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4321 | &offset64); |
4322 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4323 | regcache_raw_read_unsigned (irp->regcache, |
4324 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4325 | &offset64); |
4326 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4327 | break; |
4328 | case 1: | |
cf648174 HZ |
4329 | regcache_raw_read_unsigned (irp->regcache, |
4330 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4331 | &offset64); |
4332 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4333 | regcache_raw_read_unsigned (irp->regcache, |
4334 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4335 | &offset64); |
4336 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4337 | break; |
4338 | case 2: | |
cf648174 HZ |
4339 | regcache_raw_read_unsigned (irp->regcache, |
4340 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4341 | &offset64); |
4342 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4343 | regcache_raw_read_unsigned (irp->regcache, |
4344 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4345 | &offset64); |
4346 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4347 | break; |
4348 | case 3: | |
cf648174 HZ |
4349 | regcache_raw_read_unsigned (irp->regcache, |
4350 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4351 | &offset64); |
4352 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4353 | regcache_raw_read_unsigned (irp->regcache, |
4354 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4355 | &offset64); |
4356 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4357 | break; |
4358 | case 4: | |
cf648174 HZ |
4359 | regcache_raw_read_unsigned (irp->regcache, |
4360 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4361 | &offset64); |
4362 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4363 | break; |
4364 | case 5: | |
cf648174 HZ |
4365 | regcache_raw_read_unsigned (irp->regcache, |
4366 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4367 | &offset64); |
4368 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4369 | break; |
4370 | case 6: | |
cf648174 HZ |
4371 | regcache_raw_read_unsigned (irp->regcache, |
4372 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4373 | &offset64); |
4374 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4375 | break; |
4376 | case 7: | |
cf648174 HZ |
4377 | regcache_raw_read_unsigned (irp->regcache, |
4378 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4379 | &offset64); |
4380 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4381 | break; |
4382 | } | |
4383 | *addr &= 0xffff; | |
4384 | } | |
c4fc7f1b | 4385 | |
01fe1b41 | 4386 | no_rm: |
7ad10968 HZ |
4387 | return 0; |
4388 | } | |
c4fc7f1b | 4389 | |
99c1624c PA |
4390 | /* Record the address and contents of the memory that will be changed |
4391 | by the current instruction. Return -1 if something goes wrong, 0 | |
4392 | otherwise. */ | |
356a6b3e | 4393 | |
7ad10968 HZ |
4394 | static int |
4395 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4396 | { | |
cf648174 HZ |
4397 | struct gdbarch *gdbarch = irp->gdbarch; |
4398 | uint64_t addr; | |
356a6b3e | 4399 | |
d7877f7e | 4400 | if (irp->override >= 0) |
7ad10968 | 4401 | { |
25ea693b | 4402 | if (record_full_memory_query) |
bb08c432 HZ |
4403 | { |
4404 | int q; | |
4405 | ||
4406 | target_terminal_ours (); | |
4407 | q = yquery (_("\ | |
4408 | Process record ignores the memory change of instruction at address %s\n\ | |
4409 | because it can't get the value of the segment register.\n\ | |
4410 | Do you want to stop the program?"), | |
4411 | paddress (gdbarch, irp->orig_addr)); | |
4412 | target_terminal_inferior (); | |
4413 | if (q) | |
4414 | return -1; | |
4415 | } | |
4416 | ||
7ad10968 HZ |
4417 | return 0; |
4418 | } | |
61113f8b | 4419 | |
7ad10968 HZ |
4420 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4421 | return -1; | |
96297dab | 4422 | |
25ea693b | 4423 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4424 | return -1; |
a62cc96e | 4425 | |
7ad10968 HZ |
4426 | return 0; |
4427 | } | |
b6197528 | 4428 | |
99c1624c PA |
4429 | /* Record the effects of a push operation. Return -1 if something |
4430 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4431 | |
4432 | static int | |
4433 | i386_record_push (struct i386_record_s *irp, int size) | |
4434 | { | |
648d0c8b | 4435 | ULONGEST addr; |
cf648174 | 4436 | |
25ea693b MM |
4437 | if (record_full_arch_list_add_reg (irp->regcache, |
4438 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4439 | return -1; |
4440 | regcache_raw_read_unsigned (irp->regcache, | |
4441 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4442 | &addr); |
25ea693b | 4443 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4444 | return -1; |
4445 | ||
4446 | return 0; | |
4447 | } | |
4448 | ||
0289bdd7 MS |
4449 | |
4450 | /* Defines contents to record. */ | |
4451 | #define I386_SAVE_FPU_REGS 0xfffd | |
4452 | #define I386_SAVE_FPU_ENV 0xfffe | |
4453 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4454 | ||
99c1624c PA |
4455 | /* Record the values of the floating point registers which will be |
4456 | changed by the current instruction. Returns -1 if something is | |
4457 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4458 | |
4459 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4460 | struct i386_record_s *ir, | |
4461 | uint32_t iregnum) | |
4462 | { | |
4463 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4464 | int i; | |
4465 | ||
4466 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4467 | happen. Currently we store st0-st7 registers, but we need not store all | |
4468 | registers all the time, in future we use ftag register and record only | |
4469 | those who are not marked as an empty. */ | |
4470 | ||
4471 | if (I386_SAVE_FPU_REGS == iregnum) | |
4472 | { | |
4473 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
4474 | { | |
25ea693b | 4475 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4476 | return -1; |
4477 | } | |
4478 | } | |
4479 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4480 | { | |
4481 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4482 | { | |
25ea693b | 4483 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4484 | return -1; |
4485 | } | |
4486 | } | |
4487 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4488 | { | |
4489 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4490 | { | |
25ea693b | 4491 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4492 | return -1; |
4493 | } | |
4494 | } | |
4495 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
4496 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
4497 | { | |
25ea693b | 4498 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
0289bdd7 MS |
4499 | return -1; |
4500 | } | |
4501 | else | |
4502 | { | |
4503 | /* Parameter error. */ | |
4504 | return -1; | |
4505 | } | |
4506 | if(I386_SAVE_FPU_ENV != iregnum) | |
4507 | { | |
4508 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4509 | { | |
25ea693b | 4510 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4511 | return -1; |
4512 | } | |
4513 | } | |
4514 | return 0; | |
4515 | } | |
4516 | ||
99c1624c PA |
4517 | /* Parse the current instruction, and record the values of the |
4518 | registers and memory that will be changed by the current | |
4519 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 4520 | |
25ea693b MM |
4521 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
4522 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 4523 | |
a6b808b4 | 4524 | int |
7ad10968 | 4525 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 4526 | CORE_ADDR input_addr) |
7ad10968 | 4527 | { |
60a1502a | 4528 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 4529 | int prefixes = 0; |
580879fc | 4530 | int regnum = 0; |
425b824a | 4531 | uint32_t opcode; |
f4644a3f | 4532 | uint8_t opcode8; |
648d0c8b | 4533 | ULONGEST addr; |
60a1502a | 4534 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 4535 | struct i386_record_s ir; |
0289bdd7 | 4536 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
4537 | uint8_t rex_w = -1; |
4538 | uint8_t rex_r = 0; | |
7ad10968 | 4539 | |
8408d274 | 4540 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 4541 | ir.regcache = regcache; |
648d0c8b MS |
4542 | ir.addr = input_addr; |
4543 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
4544 | ir.aflag = 1; |
4545 | ir.dflag = 1; | |
cf648174 HZ |
4546 | ir.override = -1; |
4547 | ir.popl_esp_hack = 0; | |
a3c4230a | 4548 | ir.regmap = tdep->record_regmap; |
cf648174 | 4549 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
4550 | |
4551 | if (record_debug > 1) | |
4552 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
4553 | "addr = %s\n", |
4554 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4555 | |
4556 | /* prefixes */ | |
4557 | while (1) | |
4558 | { | |
4ffa4fc7 PA |
4559 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
4560 | return -1; | |
7ad10968 | 4561 | ir.addr++; |
425b824a | 4562 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 4563 | { |
01fe1b41 | 4564 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
4565 | prefixes |= PREFIX_REPZ; |
4566 | break; | |
01fe1b41 | 4567 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
4568 | prefixes |= PREFIX_REPNZ; |
4569 | break; | |
01fe1b41 | 4570 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
4571 | prefixes |= PREFIX_LOCK; |
4572 | break; | |
01fe1b41 | 4573 | case CS_PREFIX_OPCODE: |
cf648174 | 4574 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 4575 | break; |
01fe1b41 | 4576 | case SS_PREFIX_OPCODE: |
cf648174 | 4577 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 4578 | break; |
01fe1b41 | 4579 | case DS_PREFIX_OPCODE: |
cf648174 | 4580 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 4581 | break; |
01fe1b41 | 4582 | case ES_PREFIX_OPCODE: |
cf648174 | 4583 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 4584 | break; |
01fe1b41 | 4585 | case FS_PREFIX_OPCODE: |
cf648174 | 4586 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 4587 | break; |
01fe1b41 | 4588 | case GS_PREFIX_OPCODE: |
cf648174 | 4589 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 4590 | break; |
01fe1b41 | 4591 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
4592 | prefixes |= PREFIX_DATA; |
4593 | break; | |
01fe1b41 | 4594 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
4595 | prefixes |= PREFIX_ADDR; |
4596 | break; | |
d691bec7 MS |
4597 | case 0x40: /* i386 inc %eax */ |
4598 | case 0x41: /* i386 inc %ecx */ | |
4599 | case 0x42: /* i386 inc %edx */ | |
4600 | case 0x43: /* i386 inc %ebx */ | |
4601 | case 0x44: /* i386 inc %esp */ | |
4602 | case 0x45: /* i386 inc %ebp */ | |
4603 | case 0x46: /* i386 inc %esi */ | |
4604 | case 0x47: /* i386 inc %edi */ | |
4605 | case 0x48: /* i386 dec %eax */ | |
4606 | case 0x49: /* i386 dec %ecx */ | |
4607 | case 0x4a: /* i386 dec %edx */ | |
4608 | case 0x4b: /* i386 dec %ebx */ | |
4609 | case 0x4c: /* i386 dec %esp */ | |
4610 | case 0x4d: /* i386 dec %ebp */ | |
4611 | case 0x4e: /* i386 dec %esi */ | |
4612 | case 0x4f: /* i386 dec %edi */ | |
4613 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
4614 | { |
4615 | /* REX */ | |
425b824a MS |
4616 | rex_w = (opcode8 >> 3) & 1; |
4617 | rex_r = (opcode8 & 0x4) << 1; | |
4618 | ir.rex_x = (opcode8 & 0x2) << 2; | |
4619 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 4620 | } |
d691bec7 MS |
4621 | else /* 32 bit target */ |
4622 | goto out_prefixes; | |
cf648174 | 4623 | break; |
7ad10968 HZ |
4624 | default: |
4625 | goto out_prefixes; | |
4626 | break; | |
4627 | } | |
4628 | } | |
01fe1b41 | 4629 | out_prefixes: |
cf648174 HZ |
4630 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
4631 | { | |
4632 | ir.dflag = 2; | |
4633 | } | |
4634 | else | |
4635 | { | |
4636 | if (prefixes & PREFIX_DATA) | |
4637 | ir.dflag ^= 1; | |
4638 | } | |
7ad10968 HZ |
4639 | if (prefixes & PREFIX_ADDR) |
4640 | ir.aflag ^= 1; | |
cf648174 HZ |
4641 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4642 | ir.aflag = 2; | |
7ad10968 | 4643 | |
1777feb0 | 4644 | /* Now check op code. */ |
425b824a | 4645 | opcode = (uint32_t) opcode8; |
01fe1b41 | 4646 | reswitch: |
7ad10968 HZ |
4647 | switch (opcode) |
4648 | { | |
4649 | case 0x0f: | |
4ffa4fc7 PA |
4650 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
4651 | return -1; | |
7ad10968 | 4652 | ir.addr++; |
a3c4230a | 4653 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
4654 | goto reswitch; |
4655 | break; | |
93924b6b | 4656 | |
a38bba38 | 4657 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
4658 | case 0x01: |
4659 | case 0x02: | |
4660 | case 0x03: | |
4661 | case 0x04: | |
4662 | case 0x05: | |
4663 | case 0x08: | |
4664 | case 0x09: | |
4665 | case 0x0a: | |
4666 | case 0x0b: | |
4667 | case 0x0c: | |
4668 | case 0x0d: | |
4669 | case 0x10: | |
4670 | case 0x11: | |
4671 | case 0x12: | |
4672 | case 0x13: | |
4673 | case 0x14: | |
4674 | case 0x15: | |
4675 | case 0x18: | |
4676 | case 0x19: | |
4677 | case 0x1a: | |
4678 | case 0x1b: | |
4679 | case 0x1c: | |
4680 | case 0x1d: | |
4681 | case 0x20: | |
4682 | case 0x21: | |
4683 | case 0x22: | |
4684 | case 0x23: | |
4685 | case 0x24: | |
4686 | case 0x25: | |
4687 | case 0x28: | |
4688 | case 0x29: | |
4689 | case 0x2a: | |
4690 | case 0x2b: | |
4691 | case 0x2c: | |
4692 | case 0x2d: | |
4693 | case 0x30: | |
4694 | case 0x31: | |
4695 | case 0x32: | |
4696 | case 0x33: | |
4697 | case 0x34: | |
4698 | case 0x35: | |
4699 | case 0x38: | |
4700 | case 0x39: | |
4701 | case 0x3a: | |
4702 | case 0x3b: | |
4703 | case 0x3c: | |
4704 | case 0x3d: | |
4705 | if (((opcode >> 3) & 7) != OP_CMPL) | |
4706 | { | |
4707 | if ((opcode & 1) == 0) | |
4708 | ir.ot = OT_BYTE; | |
4709 | else | |
4710 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 4711 | |
7ad10968 HZ |
4712 | switch ((opcode >> 1) & 3) |
4713 | { | |
a38bba38 | 4714 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
4715 | if (i386_record_modrm (&ir)) |
4716 | return -1; | |
4717 | if (ir.mod != 3) | |
4718 | { | |
4719 | if (i386_record_lea_modrm (&ir)) | |
4720 | return -1; | |
4721 | } | |
4722 | else | |
4723 | { | |
cf648174 HZ |
4724 | ir.rm |= ir.rex_b; |
4725 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4726 | ir.rm &= 0x3; |
25ea693b | 4727 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4728 | } |
4729 | break; | |
a38bba38 | 4730 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
4731 | if (i386_record_modrm (&ir)) |
4732 | return -1; | |
cf648174 HZ |
4733 | ir.reg |= rex_r; |
4734 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4735 | ir.reg &= 0x3; |
25ea693b | 4736 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4737 | break; |
a38bba38 | 4738 | case 2: /* OP A, Iv */ |
25ea693b | 4739 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4740 | break; |
4741 | } | |
4742 | } | |
25ea693b | 4743 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4744 | break; |
42fdc8df | 4745 | |
a38bba38 | 4746 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
4747 | case 0x81: |
4748 | case 0x82: | |
4749 | case 0x83: | |
4750 | if (i386_record_modrm (&ir)) | |
4751 | return -1; | |
8201327c | 4752 | |
7ad10968 HZ |
4753 | if (ir.reg != OP_CMPL) |
4754 | { | |
4755 | if ((opcode & 1) == 0) | |
4756 | ir.ot = OT_BYTE; | |
4757 | else | |
4758 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 4759 | |
7ad10968 HZ |
4760 | if (ir.mod != 3) |
4761 | { | |
cf648174 HZ |
4762 | if (opcode == 0x83) |
4763 | ir.rip_offset = 1; | |
4764 | else | |
4765 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4766 | if (i386_record_lea_modrm (&ir)) |
4767 | return -1; | |
4768 | } | |
4769 | else | |
25ea693b | 4770 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 4771 | } |
25ea693b | 4772 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4773 | break; |
5e3397bb | 4774 | |
a38bba38 | 4775 | case 0x40: /* inc */ |
7ad10968 HZ |
4776 | case 0x41: |
4777 | case 0x42: | |
4778 | case 0x43: | |
4779 | case 0x44: | |
4780 | case 0x45: | |
4781 | case 0x46: | |
4782 | case 0x47: | |
a38bba38 MS |
4783 | |
4784 | case 0x48: /* dec */ | |
7ad10968 HZ |
4785 | case 0x49: |
4786 | case 0x4a: | |
4787 | case 0x4b: | |
4788 | case 0x4c: | |
4789 | case 0x4d: | |
4790 | case 0x4e: | |
4791 | case 0x4f: | |
a38bba38 | 4792 | |
25ea693b MM |
4793 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
4794 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 4795 | break; |
acd5c798 | 4796 | |
a38bba38 | 4797 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
4798 | case 0xf7: |
4799 | if ((opcode & 1) == 0) | |
4800 | ir.ot = OT_BYTE; | |
4801 | else | |
4802 | ir.ot = ir.dflag + OT_WORD; | |
4803 | if (i386_record_modrm (&ir)) | |
4804 | return -1; | |
acd5c798 | 4805 | |
cf648174 HZ |
4806 | if (ir.mod != 3 && ir.reg == 0) |
4807 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4808 | ||
7ad10968 HZ |
4809 | switch (ir.reg) |
4810 | { | |
a38bba38 | 4811 | case 0: /* test */ |
25ea693b | 4812 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4813 | break; |
a38bba38 MS |
4814 | case 2: /* not */ |
4815 | case 3: /* neg */ | |
7ad10968 HZ |
4816 | if (ir.mod != 3) |
4817 | { | |
4818 | if (i386_record_lea_modrm (&ir)) | |
4819 | return -1; | |
4820 | } | |
4821 | else | |
4822 | { | |
cf648174 HZ |
4823 | ir.rm |= ir.rex_b; |
4824 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4825 | ir.rm &= 0x3; |
25ea693b | 4826 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4827 | } |
a38bba38 | 4828 | if (ir.reg == 3) /* neg */ |
25ea693b | 4829 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4830 | break; |
a38bba38 MS |
4831 | case 4: /* mul */ |
4832 | case 5: /* imul */ | |
4833 | case 6: /* div */ | |
4834 | case 7: /* idiv */ | |
25ea693b | 4835 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 4836 | if (ir.ot != OT_BYTE) |
25ea693b MM |
4837 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
4838 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4839 | break; |
4840 | default: | |
4841 | ir.addr -= 2; | |
4842 | opcode = opcode << 8 | ir.modrm; | |
4843 | goto no_support; | |
4844 | break; | |
4845 | } | |
4846 | break; | |
4847 | ||
a38bba38 MS |
4848 | case 0xfe: /* GRP4 */ |
4849 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
4850 | if (i386_record_modrm (&ir)) |
4851 | return -1; | |
4852 | if (ir.reg >= 2 && opcode == 0xfe) | |
4853 | { | |
4854 | ir.addr -= 2; | |
4855 | opcode = opcode << 8 | ir.modrm; | |
4856 | goto no_support; | |
4857 | } | |
7ad10968 HZ |
4858 | switch (ir.reg) |
4859 | { | |
a38bba38 MS |
4860 | case 0: /* inc */ |
4861 | case 1: /* dec */ | |
cf648174 HZ |
4862 | if ((opcode & 1) == 0) |
4863 | ir.ot = OT_BYTE; | |
4864 | else | |
4865 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4866 | if (ir.mod != 3) |
4867 | { | |
4868 | if (i386_record_lea_modrm (&ir)) | |
4869 | return -1; | |
4870 | } | |
4871 | else | |
4872 | { | |
cf648174 HZ |
4873 | ir.rm |= ir.rex_b; |
4874 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4875 | ir.rm &= 0x3; |
25ea693b | 4876 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4877 | } |
25ea693b | 4878 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4879 | break; |
a38bba38 | 4880 | case 2: /* call */ |
cf648174 HZ |
4881 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4882 | ir.dflag = 2; | |
4883 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4884 | return -1; |
25ea693b | 4885 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4886 | break; |
a38bba38 | 4887 | case 3: /* lcall */ |
25ea693b | 4888 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 4889 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 4890 | return -1; |
25ea693b | 4891 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4892 | break; |
a38bba38 MS |
4893 | case 4: /* jmp */ |
4894 | case 5: /* ljmp */ | |
25ea693b | 4895 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 4896 | break; |
a38bba38 | 4897 | case 6: /* push */ |
cf648174 HZ |
4898 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4899 | ir.dflag = 2; | |
4900 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4901 | return -1; | |
7ad10968 HZ |
4902 | break; |
4903 | default: | |
4904 | ir.addr -= 2; | |
4905 | opcode = opcode << 8 | ir.modrm; | |
4906 | goto no_support; | |
4907 | break; | |
4908 | } | |
4909 | break; | |
4910 | ||
a38bba38 | 4911 | case 0x84: /* test */ |
7ad10968 HZ |
4912 | case 0x85: |
4913 | case 0xa8: | |
4914 | case 0xa9: | |
25ea693b | 4915 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4916 | break; |
4917 | ||
a38bba38 | 4918 | case 0x98: /* CWDE/CBW */ |
25ea693b | 4919 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4920 | break; |
4921 | ||
a38bba38 | 4922 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
4923 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4924 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4925 | break; |
4926 | ||
a38bba38 | 4927 | case 0x0faf: /* imul */ |
7ad10968 HZ |
4928 | case 0x69: |
4929 | case 0x6b: | |
4930 | ir.ot = ir.dflag + OT_WORD; | |
4931 | if (i386_record_modrm (&ir)) | |
4932 | return -1; | |
cf648174 HZ |
4933 | if (opcode == 0x69) |
4934 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4935 | else if (opcode == 0x6b) | |
4936 | ir.rip_offset = 1; | |
4937 | ir.reg |= rex_r; | |
4938 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4939 | ir.reg &= 0x3; |
25ea693b MM |
4940 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
4941 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4942 | break; |
4943 | ||
a38bba38 | 4944 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
4945 | case 0x0fc1: |
4946 | if ((opcode & 1) == 0) | |
4947 | ir.ot = OT_BYTE; | |
4948 | else | |
4949 | ir.ot = ir.dflag + OT_WORD; | |
4950 | if (i386_record_modrm (&ir)) | |
4951 | return -1; | |
cf648174 | 4952 | ir.reg |= rex_r; |
7ad10968 HZ |
4953 | if (ir.mod == 3) |
4954 | { | |
cf648174 | 4955 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4956 | ir.reg &= 0x3; |
25ea693b | 4957 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 4958 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4959 | ir.rm &= 0x3; |
25ea693b | 4960 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4961 | } |
4962 | else | |
4963 | { | |
4964 | if (i386_record_lea_modrm (&ir)) | |
4965 | return -1; | |
cf648174 | 4966 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4967 | ir.reg &= 0x3; |
25ea693b | 4968 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4969 | } |
25ea693b | 4970 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4971 | break; |
4972 | ||
a38bba38 | 4973 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
4974 | case 0x0fb1: |
4975 | if ((opcode & 1) == 0) | |
4976 | ir.ot = OT_BYTE; | |
4977 | else | |
4978 | ir.ot = ir.dflag + OT_WORD; | |
4979 | if (i386_record_modrm (&ir)) | |
4980 | return -1; | |
4981 | if (ir.mod == 3) | |
4982 | { | |
cf648174 | 4983 | ir.reg |= rex_r; |
25ea693b | 4984 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 4985 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4986 | ir.reg &= 0x3; |
25ea693b | 4987 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4988 | } |
4989 | else | |
4990 | { | |
25ea693b | 4991 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4992 | if (i386_record_lea_modrm (&ir)) |
4993 | return -1; | |
4994 | } | |
25ea693b | 4995 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4996 | break; |
4997 | ||
a38bba38 | 4998 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
4999 | if (i386_record_modrm (&ir)) |
5000 | return -1; | |
5001 | if (ir.mod == 3) | |
5002 | { | |
5003 | ir.addr -= 2; | |
5004 | opcode = opcode << 8 | ir.modrm; | |
5005 | goto no_support; | |
5006 | } | |
25ea693b MM |
5007 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5008 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5009 | if (i386_record_lea_modrm (&ir)) |
5010 | return -1; | |
25ea693b | 5011 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5012 | break; |
5013 | ||
a38bba38 | 5014 | case 0x50: /* push */ |
7ad10968 HZ |
5015 | case 0x51: |
5016 | case 0x52: | |
5017 | case 0x53: | |
5018 | case 0x54: | |
5019 | case 0x55: | |
5020 | case 0x56: | |
5021 | case 0x57: | |
5022 | case 0x68: | |
5023 | case 0x6a: | |
cf648174 HZ |
5024 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5025 | ir.dflag = 2; | |
5026 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5027 | return -1; | |
5028 | break; | |
5029 | ||
a38bba38 MS |
5030 | case 0x06: /* push es */ |
5031 | case 0x0e: /* push cs */ | |
5032 | case 0x16: /* push ss */ | |
5033 | case 0x1e: /* push ds */ | |
cf648174 HZ |
5034 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5035 | { | |
5036 | ir.addr -= 1; | |
5037 | goto no_support; | |
5038 | } | |
5039 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5040 | return -1; | |
5041 | break; | |
5042 | ||
a38bba38 MS |
5043 | case 0x0fa0: /* push fs */ |
5044 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
5045 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5046 | { | |
5047 | ir.addr -= 2; | |
5048 | goto no_support; | |
5049 | } | |
5050 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5051 | return -1; |
cf648174 HZ |
5052 | break; |
5053 | ||
a38bba38 | 5054 | case 0x60: /* pusha */ |
cf648174 HZ |
5055 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5056 | { | |
5057 | ir.addr -= 1; | |
5058 | goto no_support; | |
5059 | } | |
5060 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5061 | return -1; |
5062 | break; | |
5063 | ||
a38bba38 | 5064 | case 0x58: /* pop */ |
7ad10968 HZ |
5065 | case 0x59: |
5066 | case 0x5a: | |
5067 | case 0x5b: | |
5068 | case 0x5c: | |
5069 | case 0x5d: | |
5070 | case 0x5e: | |
5071 | case 0x5f: | |
25ea693b MM |
5072 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5073 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5074 | break; |
5075 | ||
a38bba38 | 5076 | case 0x61: /* popa */ |
cf648174 HZ |
5077 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5078 | { | |
5079 | ir.addr -= 1; | |
5080 | goto no_support; | |
7ad10968 | 5081 | } |
425b824a MS |
5082 | for (regnum = X86_RECORD_REAX_REGNUM; |
5083 | regnum <= X86_RECORD_REDI_REGNUM; | |
5084 | regnum++) | |
25ea693b | 5085 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5086 | break; |
5087 | ||
a38bba38 | 5088 | case 0x8f: /* pop */ |
cf648174 HZ |
5089 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5090 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5091 | else | |
5092 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5093 | if (i386_record_modrm (&ir)) |
5094 | return -1; | |
5095 | if (ir.mod == 3) | |
25ea693b | 5096 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5097 | else |
5098 | { | |
cf648174 | 5099 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5100 | if (i386_record_lea_modrm (&ir)) |
5101 | return -1; | |
5102 | } | |
25ea693b | 5103 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5104 | break; |
5105 | ||
a38bba38 | 5106 | case 0xc8: /* enter */ |
25ea693b | 5107 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 HZ |
5108 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5109 | ir.dflag = 2; | |
5110 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
5111 | return -1; |
5112 | break; | |
5113 | ||
a38bba38 | 5114 | case 0xc9: /* leave */ |
25ea693b MM |
5115 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5116 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5117 | break; |
5118 | ||
a38bba38 | 5119 | case 0x07: /* pop es */ |
cf648174 HZ |
5120 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5121 | { | |
5122 | ir.addr -= 1; | |
5123 | goto no_support; | |
5124 | } | |
25ea693b MM |
5125 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5126 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5127 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5128 | break; |
5129 | ||
a38bba38 | 5130 | case 0x17: /* pop ss */ |
cf648174 HZ |
5131 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5132 | { | |
5133 | ir.addr -= 1; | |
5134 | goto no_support; | |
5135 | } | |
25ea693b MM |
5136 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5137 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5138 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5139 | break; |
5140 | ||
a38bba38 | 5141 | case 0x1f: /* pop ds */ |
cf648174 HZ |
5142 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5143 | { | |
5144 | ir.addr -= 1; | |
5145 | goto no_support; | |
5146 | } | |
25ea693b MM |
5147 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5148 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5149 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5150 | break; |
5151 | ||
a38bba38 | 5152 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5153 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5154 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5155 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5156 | break; |
5157 | ||
a38bba38 | 5158 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5159 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5160 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5161 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5162 | break; |
5163 | ||
a38bba38 | 5164 | case 0x88: /* mov */ |
7ad10968 HZ |
5165 | case 0x89: |
5166 | case 0xc6: | |
5167 | case 0xc7: | |
5168 | if ((opcode & 1) == 0) | |
5169 | ir.ot = OT_BYTE; | |
5170 | else | |
5171 | ir.ot = ir.dflag + OT_WORD; | |
5172 | ||
5173 | if (i386_record_modrm (&ir)) | |
5174 | return -1; | |
5175 | ||
5176 | if (ir.mod != 3) | |
5177 | { | |
cf648174 HZ |
5178 | if (opcode == 0xc6 || opcode == 0xc7) |
5179 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5180 | if (i386_record_lea_modrm (&ir)) |
5181 | return -1; | |
5182 | } | |
5183 | else | |
5184 | { | |
cf648174 HZ |
5185 | if (opcode == 0xc6 || opcode == 0xc7) |
5186 | ir.rm |= ir.rex_b; | |
5187 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5188 | ir.rm &= 0x3; |
25ea693b | 5189 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5190 | } |
7ad10968 | 5191 | break; |
cf648174 | 5192 | |
a38bba38 | 5193 | case 0x8a: /* mov */ |
7ad10968 HZ |
5194 | case 0x8b: |
5195 | if ((opcode & 1) == 0) | |
5196 | ir.ot = OT_BYTE; | |
5197 | else | |
5198 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5199 | if (i386_record_modrm (&ir)) |
5200 | return -1; | |
cf648174 HZ |
5201 | ir.reg |= rex_r; |
5202 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5203 | ir.reg &= 0x3; |
25ea693b | 5204 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5205 | break; |
7ad10968 | 5206 | |
a38bba38 | 5207 | case 0x8c: /* mov seg */ |
cf648174 | 5208 | if (i386_record_modrm (&ir)) |
7ad10968 | 5209 | return -1; |
cf648174 HZ |
5210 | if (ir.reg > 5) |
5211 | { | |
5212 | ir.addr -= 2; | |
5213 | opcode = opcode << 8 | ir.modrm; | |
5214 | goto no_support; | |
5215 | } | |
5216 | ||
5217 | if (ir.mod == 3) | |
25ea693b | 5218 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5219 | else |
5220 | { | |
5221 | ir.ot = OT_WORD; | |
5222 | if (i386_record_lea_modrm (&ir)) | |
5223 | return -1; | |
5224 | } | |
7ad10968 HZ |
5225 | break; |
5226 | ||
a38bba38 | 5227 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5228 | if (i386_record_modrm (&ir)) |
5229 | return -1; | |
7ad10968 HZ |
5230 | switch (ir.reg) |
5231 | { | |
5232 | case 0: | |
425b824a | 5233 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5234 | break; |
5235 | case 2: | |
425b824a | 5236 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5237 | break; |
5238 | case 3: | |
425b824a | 5239 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5240 | break; |
5241 | case 4: | |
425b824a | 5242 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5243 | break; |
5244 | case 5: | |
425b824a | 5245 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5246 | break; |
5247 | default: | |
5248 | ir.addr -= 2; | |
5249 | opcode = opcode << 8 | ir.modrm; | |
5250 | goto no_support; | |
5251 | break; | |
5252 | } | |
25ea693b MM |
5253 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5254 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5255 | break; |
5256 | ||
a38bba38 MS |
5257 | case 0x0fb6: /* movzbS */ |
5258 | case 0x0fb7: /* movzwS */ | |
5259 | case 0x0fbe: /* movsbS */ | |
5260 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5261 | if (i386_record_modrm (&ir)) |
5262 | return -1; | |
25ea693b | 5263 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5264 | break; |
5265 | ||
a38bba38 | 5266 | case 0x8d: /* lea */ |
7ad10968 HZ |
5267 | if (i386_record_modrm (&ir)) |
5268 | return -1; | |
5269 | if (ir.mod == 3) | |
5270 | { | |
5271 | ir.addr -= 2; | |
5272 | opcode = opcode << 8 | ir.modrm; | |
5273 | goto no_support; | |
5274 | } | |
7ad10968 | 5275 | ir.ot = ir.dflag; |
cf648174 HZ |
5276 | ir.reg |= rex_r; |
5277 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5278 | ir.reg &= 0x3; |
25ea693b | 5279 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5280 | break; |
5281 | ||
a38bba38 | 5282 | case 0xa0: /* mov EAX */ |
7ad10968 | 5283 | case 0xa1: |
a38bba38 MS |
5284 | |
5285 | case 0xd7: /* xlat */ | |
25ea693b | 5286 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5287 | break; |
5288 | ||
a38bba38 | 5289 | case 0xa2: /* mov EAX */ |
7ad10968 | 5290 | case 0xa3: |
d7877f7e | 5291 | if (ir.override >= 0) |
cf648174 | 5292 | { |
25ea693b | 5293 | if (record_full_memory_query) |
bb08c432 HZ |
5294 | { |
5295 | int q; | |
5296 | ||
5297 | target_terminal_ours (); | |
5298 | q = yquery (_("\ | |
5299 | Process record ignores the memory change of instruction at address %s\n\ | |
5300 | because it can't get the value of the segment register.\n\ | |
5301 | Do you want to stop the program?"), | |
5302 | paddress (gdbarch, ir.orig_addr)); | |
5303 | target_terminal_inferior (); | |
5304 | if (q) | |
5305 | return -1; | |
5306 | } | |
cf648174 HZ |
5307 | } |
5308 | else | |
5309 | { | |
5310 | if ((opcode & 1) == 0) | |
5311 | ir.ot = OT_BYTE; | |
5312 | else | |
5313 | ir.ot = ir.dflag + OT_WORD; | |
5314 | if (ir.aflag == 2) | |
5315 | { | |
4ffa4fc7 PA |
5316 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
5317 | return -1; | |
cf648174 | 5318 | ir.addr += 8; |
60a1502a | 5319 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5320 | } |
5321 | else if (ir.aflag) | |
5322 | { | |
4ffa4fc7 PA |
5323 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
5324 | return -1; | |
cf648174 | 5325 | ir.addr += 4; |
60a1502a | 5326 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5327 | } |
5328 | else | |
5329 | { | |
4ffa4fc7 PA |
5330 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
5331 | return -1; | |
cf648174 | 5332 | ir.addr += 2; |
60a1502a | 5333 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5334 | } |
25ea693b | 5335 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5336 | return -1; |
5337 | } | |
7ad10968 HZ |
5338 | break; |
5339 | ||
a38bba38 | 5340 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5341 | case 0xb1: |
5342 | case 0xb2: | |
5343 | case 0xb3: | |
5344 | case 0xb4: | |
5345 | case 0xb5: | |
5346 | case 0xb6: | |
5347 | case 0xb7: | |
25ea693b MM |
5348 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5349 | ? ((opcode & 0x7) | ir.rex_b) | |
5350 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5351 | break; |
5352 | ||
a38bba38 | 5353 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5354 | case 0xb9: |
5355 | case 0xba: | |
5356 | case 0xbb: | |
5357 | case 0xbc: | |
5358 | case 0xbd: | |
5359 | case 0xbe: | |
5360 | case 0xbf: | |
25ea693b | 5361 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5362 | break; |
5363 | ||
a38bba38 | 5364 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5365 | case 0x92: |
5366 | case 0x93: | |
5367 | case 0x94: | |
5368 | case 0x95: | |
5369 | case 0x96: | |
5370 | case 0x97: | |
25ea693b MM |
5371 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5372 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5373 | break; |
5374 | ||
a38bba38 | 5375 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5376 | case 0x87: |
5377 | if ((opcode & 1) == 0) | |
5378 | ir.ot = OT_BYTE; | |
5379 | else | |
5380 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5381 | if (i386_record_modrm (&ir)) |
5382 | return -1; | |
7ad10968 HZ |
5383 | if (ir.mod == 3) |
5384 | { | |
86839d38 | 5385 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5386 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5387 | ir.rm &= 0x3; | |
25ea693b | 5388 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5389 | } |
5390 | else | |
5391 | { | |
5392 | if (i386_record_lea_modrm (&ir)) | |
5393 | return -1; | |
5394 | } | |
cf648174 HZ |
5395 | ir.reg |= rex_r; |
5396 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5397 | ir.reg &= 0x3; |
25ea693b | 5398 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5399 | break; |
5400 | ||
a38bba38 MS |
5401 | case 0xc4: /* les Gv */ |
5402 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5403 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5404 | { | |
5405 | ir.addr -= 1; | |
5406 | goto no_support; | |
5407 | } | |
d3f323f3 | 5408 | /* FALLTHROUGH */ |
a38bba38 MS |
5409 | case 0x0fb2: /* lss Gv */ |
5410 | case 0x0fb4: /* lfs Gv */ | |
5411 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5412 | if (i386_record_modrm (&ir)) |
5413 | return -1; | |
5414 | if (ir.mod == 3) | |
5415 | { | |
5416 | if (opcode > 0xff) | |
5417 | ir.addr -= 3; | |
5418 | else | |
5419 | ir.addr -= 2; | |
5420 | opcode = opcode << 8 | ir.modrm; | |
5421 | goto no_support; | |
5422 | } | |
7ad10968 HZ |
5423 | switch (opcode) |
5424 | { | |
a38bba38 | 5425 | case 0xc4: /* les Gv */ |
425b824a | 5426 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5427 | break; |
a38bba38 | 5428 | case 0xc5: /* lds Gv */ |
425b824a | 5429 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5430 | break; |
a38bba38 | 5431 | case 0x0fb2: /* lss Gv */ |
425b824a | 5432 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5433 | break; |
a38bba38 | 5434 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5435 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5436 | break; |
a38bba38 | 5437 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5438 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5439 | break; |
5440 | } | |
25ea693b MM |
5441 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5442 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5443 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5444 | break; |
5445 | ||
a38bba38 | 5446 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5447 | case 0xc1: |
5448 | case 0xd0: | |
5449 | case 0xd1: | |
5450 | case 0xd2: | |
5451 | case 0xd3: | |
5452 | if ((opcode & 1) == 0) | |
5453 | ir.ot = OT_BYTE; | |
5454 | else | |
5455 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5456 | if (i386_record_modrm (&ir)) |
5457 | return -1; | |
7ad10968 HZ |
5458 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5459 | { | |
5460 | if (i386_record_lea_modrm (&ir)) | |
5461 | return -1; | |
5462 | } | |
5463 | else | |
5464 | { | |
cf648174 HZ |
5465 | ir.rm |= ir.rex_b; |
5466 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5467 | ir.rm &= 0x3; |
25ea693b | 5468 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5469 | } |
25ea693b | 5470 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5471 | break; |
5472 | ||
5473 | case 0x0fa4: | |
5474 | case 0x0fa5: | |
5475 | case 0x0fac: | |
5476 | case 0x0fad: | |
5477 | if (i386_record_modrm (&ir)) | |
5478 | return -1; | |
5479 | if (ir.mod == 3) | |
5480 | { | |
25ea693b | 5481 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
5482 | return -1; |
5483 | } | |
5484 | else | |
5485 | { | |
5486 | if (i386_record_lea_modrm (&ir)) | |
5487 | return -1; | |
5488 | } | |
5489 | break; | |
5490 | ||
a38bba38 | 5491 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
5492 | case 0xd9: |
5493 | case 0xda: | |
5494 | case 0xdb: | |
5495 | case 0xdc: | |
5496 | case 0xdd: | |
5497 | case 0xde: | |
5498 | case 0xdf: | |
5499 | if (i386_record_modrm (&ir)) | |
5500 | return -1; | |
5501 | ir.reg |= ((opcode & 7) << 3); | |
5502 | if (ir.mod != 3) | |
5503 | { | |
1777feb0 | 5504 | /* Memory. */ |
955db0c0 | 5505 | uint64_t addr64; |
7ad10968 | 5506 | |
955db0c0 | 5507 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
5508 | return -1; |
5509 | switch (ir.reg) | |
5510 | { | |
7ad10968 | 5511 | case 0x02: |
0289bdd7 MS |
5512 | case 0x12: |
5513 | case 0x22: | |
5514 | case 0x32: | |
5515 | /* For fcom, ficom nothing to do. */ | |
5516 | break; | |
7ad10968 | 5517 | case 0x03: |
0289bdd7 MS |
5518 | case 0x13: |
5519 | case 0x23: | |
5520 | case 0x33: | |
5521 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
5522 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5523 | return -1; | |
5524 | break; | |
5525 | case 0x00: | |
5526 | case 0x01: | |
7ad10968 HZ |
5527 | case 0x04: |
5528 | case 0x05: | |
5529 | case 0x06: | |
5530 | case 0x07: | |
5531 | case 0x10: | |
5532 | case 0x11: | |
7ad10968 HZ |
5533 | case 0x14: |
5534 | case 0x15: | |
5535 | case 0x16: | |
5536 | case 0x17: | |
5537 | case 0x20: | |
5538 | case 0x21: | |
7ad10968 HZ |
5539 | case 0x24: |
5540 | case 0x25: | |
5541 | case 0x26: | |
5542 | case 0x27: | |
5543 | case 0x30: | |
5544 | case 0x31: | |
7ad10968 HZ |
5545 | case 0x34: |
5546 | case 0x35: | |
5547 | case 0x36: | |
5548 | case 0x37: | |
0289bdd7 MS |
5549 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
5550 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
5551 | of code, always affects st(0) register. */ | |
5552 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5553 | return -1; | |
7ad10968 HZ |
5554 | break; |
5555 | case 0x08: | |
5556 | case 0x0a: | |
5557 | case 0x0b: | |
5558 | case 0x18: | |
5559 | case 0x19: | |
5560 | case 0x1a: | |
5561 | case 0x1b: | |
0289bdd7 | 5562 | case 0x1d: |
7ad10968 HZ |
5563 | case 0x28: |
5564 | case 0x29: | |
5565 | case 0x2a: | |
5566 | case 0x2b: | |
5567 | case 0x38: | |
5568 | case 0x39: | |
5569 | case 0x3a: | |
5570 | case 0x3b: | |
0289bdd7 MS |
5571 | case 0x3c: |
5572 | case 0x3d: | |
7ad10968 HZ |
5573 | switch (ir.reg & 7) |
5574 | { | |
5575 | case 0: | |
0289bdd7 MS |
5576 | /* Handling fld, fild. */ |
5577 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5578 | return -1; | |
7ad10968 HZ |
5579 | break; |
5580 | case 1: | |
5581 | switch (ir.reg >> 4) | |
5582 | { | |
5583 | case 0: | |
25ea693b | 5584 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
5585 | return -1; |
5586 | break; | |
5587 | case 2: | |
25ea693b | 5588 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
5589 | return -1; |
5590 | break; | |
5591 | case 3: | |
0289bdd7 | 5592 | break; |
7ad10968 | 5593 | default: |
25ea693b | 5594 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5595 | return -1; |
5596 | break; | |
5597 | } | |
5598 | break; | |
5599 | default: | |
5600 | switch (ir.reg >> 4) | |
5601 | { | |
5602 | case 0: | |
25ea693b | 5603 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
5604 | return -1; |
5605 | if (3 == (ir.reg & 7)) | |
5606 | { | |
5607 | /* For fstp m32fp. */ | |
5608 | if (i386_record_floats (gdbarch, &ir, | |
5609 | I386_SAVE_FPU_REGS)) | |
5610 | return -1; | |
5611 | } | |
5612 | break; | |
7ad10968 | 5613 | case 1: |
25ea693b | 5614 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 5615 | return -1; |
0289bdd7 MS |
5616 | if ((3 == (ir.reg & 7)) |
5617 | || (5 == (ir.reg & 7)) | |
5618 | || (7 == (ir.reg & 7))) | |
5619 | { | |
5620 | /* For fstp insn. */ | |
5621 | if (i386_record_floats (gdbarch, &ir, | |
5622 | I386_SAVE_FPU_REGS)) | |
5623 | return -1; | |
5624 | } | |
7ad10968 HZ |
5625 | break; |
5626 | case 2: | |
25ea693b | 5627 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5628 | return -1; |
0289bdd7 MS |
5629 | if (3 == (ir.reg & 7)) |
5630 | { | |
5631 | /* For fstp m64fp. */ | |
5632 | if (i386_record_floats (gdbarch, &ir, | |
5633 | I386_SAVE_FPU_REGS)) | |
5634 | return -1; | |
5635 | } | |
7ad10968 HZ |
5636 | break; |
5637 | case 3: | |
0289bdd7 MS |
5638 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
5639 | { | |
5640 | /* For fistp, fbld, fild, fbstp. */ | |
5641 | if (i386_record_floats (gdbarch, &ir, | |
5642 | I386_SAVE_FPU_REGS)) | |
5643 | return -1; | |
5644 | } | |
5645 | /* Fall through */ | |
7ad10968 | 5646 | default: |
25ea693b | 5647 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5648 | return -1; |
5649 | break; | |
5650 | } | |
5651 | break; | |
5652 | } | |
5653 | break; | |
5654 | case 0x0c: | |
0289bdd7 MS |
5655 | /* Insn fldenv. */ |
5656 | if (i386_record_floats (gdbarch, &ir, | |
5657 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5658 | return -1; | |
5659 | break; | |
7ad10968 | 5660 | case 0x0d: |
0289bdd7 MS |
5661 | /* Insn fldcw. */ |
5662 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
5663 | return -1; | |
5664 | break; | |
7ad10968 | 5665 | case 0x2c: |
0289bdd7 MS |
5666 | /* Insn frstor. */ |
5667 | if (i386_record_floats (gdbarch, &ir, | |
5668 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5669 | return -1; | |
7ad10968 HZ |
5670 | break; |
5671 | case 0x0e: | |
5672 | if (ir.dflag) | |
5673 | { | |
25ea693b | 5674 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
5675 | return -1; |
5676 | } | |
5677 | else | |
5678 | { | |
25ea693b | 5679 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
5680 | return -1; |
5681 | } | |
5682 | break; | |
5683 | case 0x0f: | |
5684 | case 0x2f: | |
25ea693b | 5685 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5686 | return -1; |
0289bdd7 MS |
5687 | /* Insn fstp, fbstp. */ |
5688 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5689 | return -1; | |
7ad10968 HZ |
5690 | break; |
5691 | case 0x1f: | |
5692 | case 0x3e: | |
25ea693b | 5693 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
5694 | return -1; |
5695 | break; | |
5696 | case 0x2e: | |
5697 | if (ir.dflag) | |
5698 | { | |
25ea693b | 5699 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 5700 | return -1; |
955db0c0 | 5701 | addr64 += 28; |
7ad10968 HZ |
5702 | } |
5703 | else | |
5704 | { | |
25ea693b | 5705 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 5706 | return -1; |
955db0c0 | 5707 | addr64 += 14; |
7ad10968 | 5708 | } |
25ea693b | 5709 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 5710 | return -1; |
0289bdd7 MS |
5711 | /* Insn fsave. */ |
5712 | if (i386_record_floats (gdbarch, &ir, | |
5713 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5714 | return -1; | |
7ad10968 HZ |
5715 | break; |
5716 | case 0x3f: | |
25ea693b | 5717 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5718 | return -1; |
0289bdd7 MS |
5719 | /* Insn fistp. */ |
5720 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5721 | return -1; | |
7ad10968 HZ |
5722 | break; |
5723 | default: | |
5724 | ir.addr -= 2; | |
5725 | opcode = opcode << 8 | ir.modrm; | |
5726 | goto no_support; | |
5727 | break; | |
5728 | } | |
5729 | } | |
0289bdd7 MS |
5730 | /* Opcode is an extension of modR/M byte. */ |
5731 | else | |
5732 | { | |
5733 | switch (opcode) | |
5734 | { | |
5735 | case 0xd8: | |
5736 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5737 | return -1; | |
5738 | break; | |
5739 | case 0xd9: | |
5740 | if (0x0c == (ir.modrm >> 4)) | |
5741 | { | |
5742 | if ((ir.modrm & 0x0f) <= 7) | |
5743 | { | |
5744 | if (i386_record_floats (gdbarch, &ir, | |
5745 | I386_SAVE_FPU_REGS)) | |
5746 | return -1; | |
5747 | } | |
5748 | else | |
5749 | { | |
5750 | if (i386_record_floats (gdbarch, &ir, | |
5751 | I387_ST0_REGNUM (tdep))) | |
5752 | return -1; | |
5753 | /* If only st(0) is changing, then we have already | |
5754 | recorded. */ | |
5755 | if ((ir.modrm & 0x0f) - 0x08) | |
5756 | { | |
5757 | if (i386_record_floats (gdbarch, &ir, | |
5758 | I387_ST0_REGNUM (tdep) + | |
5759 | ((ir.modrm & 0x0f) - 0x08))) | |
5760 | return -1; | |
5761 | } | |
5762 | } | |
5763 | } | |
5764 | else | |
5765 | { | |
5766 | switch (ir.modrm) | |
5767 | { | |
5768 | case 0xe0: | |
5769 | case 0xe1: | |
5770 | case 0xf0: | |
5771 | case 0xf5: | |
5772 | case 0xf8: | |
5773 | case 0xfa: | |
5774 | case 0xfc: | |
5775 | case 0xfe: | |
5776 | case 0xff: | |
5777 | if (i386_record_floats (gdbarch, &ir, | |
5778 | I387_ST0_REGNUM (tdep))) | |
5779 | return -1; | |
5780 | break; | |
5781 | case 0xf1: | |
5782 | case 0xf2: | |
5783 | case 0xf3: | |
5784 | case 0xf4: | |
5785 | case 0xf6: | |
5786 | case 0xf7: | |
5787 | case 0xe8: | |
5788 | case 0xe9: | |
5789 | case 0xea: | |
5790 | case 0xeb: | |
5791 | case 0xec: | |
5792 | case 0xed: | |
5793 | case 0xee: | |
5794 | case 0xf9: | |
5795 | case 0xfb: | |
5796 | if (i386_record_floats (gdbarch, &ir, | |
5797 | I386_SAVE_FPU_REGS)) | |
5798 | return -1; | |
5799 | break; | |
5800 | case 0xfd: | |
5801 | if (i386_record_floats (gdbarch, &ir, | |
5802 | I387_ST0_REGNUM (tdep))) | |
5803 | return -1; | |
5804 | if (i386_record_floats (gdbarch, &ir, | |
5805 | I387_ST0_REGNUM (tdep) + 1)) | |
5806 | return -1; | |
5807 | break; | |
5808 | } | |
5809 | } | |
5810 | break; | |
5811 | case 0xda: | |
5812 | if (0xe9 == ir.modrm) | |
5813 | { | |
5814 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5815 | return -1; | |
5816 | } | |
5817 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5818 | { | |
5819 | if (i386_record_floats (gdbarch, &ir, | |
5820 | I387_ST0_REGNUM (tdep))) | |
5821 | return -1; | |
5822 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5823 | { | |
5824 | if (i386_record_floats (gdbarch, &ir, | |
5825 | I387_ST0_REGNUM (tdep) + | |
5826 | (ir.modrm & 0x0f))) | |
5827 | return -1; | |
5828 | } | |
5829 | else if ((ir.modrm & 0x0f) - 0x08) | |
5830 | { | |
5831 | if (i386_record_floats (gdbarch, &ir, | |
5832 | I387_ST0_REGNUM (tdep) + | |
5833 | ((ir.modrm & 0x0f) - 0x08))) | |
5834 | return -1; | |
5835 | } | |
5836 | } | |
5837 | break; | |
5838 | case 0xdb: | |
5839 | if (0xe3 == ir.modrm) | |
5840 | { | |
5841 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
5842 | return -1; | |
5843 | } | |
5844 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5845 | { | |
5846 | if (i386_record_floats (gdbarch, &ir, | |
5847 | I387_ST0_REGNUM (tdep))) | |
5848 | return -1; | |
5849 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5850 | { | |
5851 | if (i386_record_floats (gdbarch, &ir, | |
5852 | I387_ST0_REGNUM (tdep) + | |
5853 | (ir.modrm & 0x0f))) | |
5854 | return -1; | |
5855 | } | |
5856 | else if ((ir.modrm & 0x0f) - 0x08) | |
5857 | { | |
5858 | if (i386_record_floats (gdbarch, &ir, | |
5859 | I387_ST0_REGNUM (tdep) + | |
5860 | ((ir.modrm & 0x0f) - 0x08))) | |
5861 | return -1; | |
5862 | } | |
5863 | } | |
5864 | break; | |
5865 | case 0xdc: | |
5866 | if ((0x0c == ir.modrm >> 4) | |
5867 | || (0x0d == ir.modrm >> 4) | |
5868 | || (0x0f == ir.modrm >> 4)) | |
5869 | { | |
5870 | if ((ir.modrm & 0x0f) <= 7) | |
5871 | { | |
5872 | if (i386_record_floats (gdbarch, &ir, | |
5873 | I387_ST0_REGNUM (tdep) + | |
5874 | (ir.modrm & 0x0f))) | |
5875 | return -1; | |
5876 | } | |
5877 | else | |
5878 | { | |
5879 | if (i386_record_floats (gdbarch, &ir, | |
5880 | I387_ST0_REGNUM (tdep) + | |
5881 | ((ir.modrm & 0x0f) - 0x08))) | |
5882 | return -1; | |
5883 | } | |
5884 | } | |
5885 | break; | |
5886 | case 0xdd: | |
5887 | if (0x0c == ir.modrm >> 4) | |
5888 | { | |
5889 | if (i386_record_floats (gdbarch, &ir, | |
5890 | I387_FTAG_REGNUM (tdep))) | |
5891 | return -1; | |
5892 | } | |
5893 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5894 | { | |
5895 | if ((ir.modrm & 0x0f) <= 7) | |
5896 | { | |
5897 | if (i386_record_floats (gdbarch, &ir, | |
5898 | I387_ST0_REGNUM (tdep) + | |
5899 | (ir.modrm & 0x0f))) | |
5900 | return -1; | |
5901 | } | |
5902 | else | |
5903 | { | |
5904 | if (i386_record_floats (gdbarch, &ir, | |
5905 | I386_SAVE_FPU_REGS)) | |
5906 | return -1; | |
5907 | } | |
5908 | } | |
5909 | break; | |
5910 | case 0xde: | |
5911 | if ((0x0c == ir.modrm >> 4) | |
5912 | || (0x0e == ir.modrm >> 4) | |
5913 | || (0x0f == ir.modrm >> 4) | |
5914 | || (0xd9 == ir.modrm)) | |
5915 | { | |
5916 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5917 | return -1; | |
5918 | } | |
5919 | break; | |
5920 | case 0xdf: | |
5921 | if (0xe0 == ir.modrm) | |
5922 | { | |
25ea693b MM |
5923 | if (record_full_arch_list_add_reg (ir.regcache, |
5924 | I386_EAX_REGNUM)) | |
0289bdd7 MS |
5925 | return -1; |
5926 | } | |
5927 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5928 | { | |
5929 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5930 | return -1; | |
5931 | } | |
5932 | break; | |
5933 | } | |
5934 | } | |
7ad10968 | 5935 | break; |
7ad10968 | 5936 | /* string ops */ |
a38bba38 | 5937 | case 0xa4: /* movsS */ |
7ad10968 | 5938 | case 0xa5: |
a38bba38 | 5939 | case 0xaa: /* stosS */ |
7ad10968 | 5940 | case 0xab: |
a38bba38 | 5941 | case 0x6c: /* insS */ |
7ad10968 | 5942 | case 0x6d: |
cf648174 | 5943 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 5944 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
5945 | &addr); |
5946 | if (addr) | |
cf648174 | 5947 | { |
77d7dc92 HZ |
5948 | ULONGEST es, ds; |
5949 | ||
5950 | if ((opcode & 1) == 0) | |
5951 | ir.ot = OT_BYTE; | |
5952 | else | |
5953 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
5954 | regcache_raw_read_unsigned (ir.regcache, |
5955 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 5956 | &addr); |
77d7dc92 | 5957 | |
d7877f7e HZ |
5958 | regcache_raw_read_unsigned (ir.regcache, |
5959 | ir.regmap[X86_RECORD_ES_REGNUM], | |
5960 | &es); | |
5961 | regcache_raw_read_unsigned (ir.regcache, | |
5962 | ir.regmap[X86_RECORD_DS_REGNUM], | |
5963 | &ds); | |
5964 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
5965 | { |
5966 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
25ea693b | 5967 | if (record_full_memory_query) |
bb08c432 HZ |
5968 | { |
5969 | int q; | |
5970 | ||
5971 | target_terminal_ours (); | |
5972 | q = yquery (_("\ | |
5973 | Process record ignores the memory change of instruction at address %s\n\ | |
5974 | because it can't get the value of the segment register.\n\ | |
5975 | Do you want to stop the program?"), | |
5976 | paddress (gdbarch, ir.orig_addr)); | |
5977 | target_terminal_inferior (); | |
5978 | if (q) | |
5979 | return -1; | |
5980 | } | |
df61f520 HZ |
5981 | } |
5982 | else | |
5983 | { | |
25ea693b | 5984 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 5985 | return -1; |
77d7dc92 HZ |
5986 | } |
5987 | ||
5988 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
25ea693b | 5989 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
77d7dc92 | 5990 | if (opcode == 0xa4 || opcode == 0xa5) |
25ea693b MM |
5991 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
5992 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5993 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 5994 | } |
cf648174 | 5995 | break; |
7ad10968 | 5996 | |
a38bba38 | 5997 | case 0xa6: /* cmpsS */ |
cf648174 | 5998 | case 0xa7: |
25ea693b MM |
5999 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6000 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6001 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6002 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6003 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6004 | break; |
6005 | ||
a38bba38 | 6006 | case 0xac: /* lodsS */ |
7ad10968 | 6007 | case 0xad: |
25ea693b MM |
6008 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6009 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6010 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6011 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6012 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6013 | break; |
6014 | ||
a38bba38 | 6015 | case 0xae: /* scasS */ |
7ad10968 | 6016 | case 0xaf: |
25ea693b | 6017 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6018 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6019 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6020 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6021 | break; |
6022 | ||
a38bba38 | 6023 | case 0x6e: /* outsS */ |
cf648174 | 6024 | case 0x6f: |
25ea693b | 6025 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6026 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6027 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6028 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6029 | break; |
6030 | ||
a38bba38 | 6031 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6032 | case 0xe5: |
6033 | case 0xec: | |
6034 | case 0xed: | |
25ea693b MM |
6035 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6036 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6037 | break; |
6038 | ||
6039 | case 0xe6: | |
6040 | case 0xe7: | |
6041 | case 0xee: | |
6042 | case 0xef: | |
6043 | break; | |
6044 | ||
6045 | /* control */ | |
a38bba38 MS |
6046 | case 0xc2: /* ret im */ |
6047 | case 0xc3: /* ret */ | |
25ea693b MM |
6048 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6049 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6050 | break; |
6051 | ||
a38bba38 MS |
6052 | case 0xca: /* lret im */ |
6053 | case 0xcb: /* lret */ | |
6054 | case 0xcf: /* iret */ | |
25ea693b MM |
6055 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6056 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6057 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6058 | break; |
6059 | ||
a38bba38 | 6060 | case 0xe8: /* call im */ |
cf648174 HZ |
6061 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6062 | ir.dflag = 2; | |
6063 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6064 | return -1; | |
7ad10968 HZ |
6065 | break; |
6066 | ||
a38bba38 | 6067 | case 0x9a: /* lcall im */ |
cf648174 HZ |
6068 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6069 | { | |
6070 | ir.addr -= 1; | |
6071 | goto no_support; | |
6072 | } | |
25ea693b | 6073 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 HZ |
6074 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
6075 | return -1; | |
7ad10968 HZ |
6076 | break; |
6077 | ||
a38bba38 MS |
6078 | case 0xe9: /* jmp im */ |
6079 | case 0xea: /* ljmp im */ | |
6080 | case 0xeb: /* jmp Jb */ | |
6081 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6082 | case 0x71: |
6083 | case 0x72: | |
6084 | case 0x73: | |
6085 | case 0x74: | |
6086 | case 0x75: | |
6087 | case 0x76: | |
6088 | case 0x77: | |
6089 | case 0x78: | |
6090 | case 0x79: | |
6091 | case 0x7a: | |
6092 | case 0x7b: | |
6093 | case 0x7c: | |
6094 | case 0x7d: | |
6095 | case 0x7e: | |
6096 | case 0x7f: | |
a38bba38 | 6097 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6098 | case 0x0f81: |
6099 | case 0x0f82: | |
6100 | case 0x0f83: | |
6101 | case 0x0f84: | |
6102 | case 0x0f85: | |
6103 | case 0x0f86: | |
6104 | case 0x0f87: | |
6105 | case 0x0f88: | |
6106 | case 0x0f89: | |
6107 | case 0x0f8a: | |
6108 | case 0x0f8b: | |
6109 | case 0x0f8c: | |
6110 | case 0x0f8d: | |
6111 | case 0x0f8e: | |
6112 | case 0x0f8f: | |
6113 | break; | |
6114 | ||
a38bba38 | 6115 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6116 | case 0x0f91: |
6117 | case 0x0f92: | |
6118 | case 0x0f93: | |
6119 | case 0x0f94: | |
6120 | case 0x0f95: | |
6121 | case 0x0f96: | |
6122 | case 0x0f97: | |
6123 | case 0x0f98: | |
6124 | case 0x0f99: | |
6125 | case 0x0f9a: | |
6126 | case 0x0f9b: | |
6127 | case 0x0f9c: | |
6128 | case 0x0f9d: | |
6129 | case 0x0f9e: | |
6130 | case 0x0f9f: | |
25ea693b | 6131 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6132 | ir.ot = OT_BYTE; |
6133 | if (i386_record_modrm (&ir)) | |
6134 | return -1; | |
6135 | if (ir.mod == 3) | |
25ea693b MM |
6136 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
6137 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
6138 | else |
6139 | { | |
6140 | if (i386_record_lea_modrm (&ir)) | |
6141 | return -1; | |
6142 | } | |
6143 | break; | |
6144 | ||
a38bba38 | 6145 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6146 | case 0x0f41: |
6147 | case 0x0f42: | |
6148 | case 0x0f43: | |
6149 | case 0x0f44: | |
6150 | case 0x0f45: | |
6151 | case 0x0f46: | |
6152 | case 0x0f47: | |
6153 | case 0x0f48: | |
6154 | case 0x0f49: | |
6155 | case 0x0f4a: | |
6156 | case 0x0f4b: | |
6157 | case 0x0f4c: | |
6158 | case 0x0f4d: | |
6159 | case 0x0f4e: | |
6160 | case 0x0f4f: | |
6161 | if (i386_record_modrm (&ir)) | |
6162 | return -1; | |
cf648174 | 6163 | ir.reg |= rex_r; |
7ad10968 HZ |
6164 | if (ir.dflag == OT_BYTE) |
6165 | ir.reg &= 0x3; | |
25ea693b | 6166 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6167 | break; |
6168 | ||
6169 | /* flags */ | |
a38bba38 | 6170 | case 0x9c: /* pushf */ |
25ea693b | 6171 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6172 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6173 | ir.dflag = 2; | |
6174 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6175 | return -1; | |
7ad10968 HZ |
6176 | break; |
6177 | ||
a38bba38 | 6178 | case 0x9d: /* popf */ |
25ea693b MM |
6179 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6180 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6181 | break; |
6182 | ||
a38bba38 | 6183 | case 0x9e: /* sahf */ |
cf648174 HZ |
6184 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6185 | { | |
6186 | ir.addr -= 1; | |
6187 | goto no_support; | |
6188 | } | |
d3f323f3 | 6189 | /* FALLTHROUGH */ |
a38bba38 MS |
6190 | case 0xf5: /* cmc */ |
6191 | case 0xf8: /* clc */ | |
6192 | case 0xf9: /* stc */ | |
6193 | case 0xfc: /* cld */ | |
6194 | case 0xfd: /* std */ | |
25ea693b | 6195 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6196 | break; |
6197 | ||
a38bba38 | 6198 | case 0x9f: /* lahf */ |
cf648174 HZ |
6199 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6200 | { | |
6201 | ir.addr -= 1; | |
6202 | goto no_support; | |
6203 | } | |
25ea693b MM |
6204 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6205 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6206 | break; |
6207 | ||
6208 | /* bit operations */ | |
a38bba38 | 6209 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6210 | ir.ot = ir.dflag + OT_WORD; |
6211 | if (i386_record_modrm (&ir)) | |
6212 | return -1; | |
6213 | if (ir.reg < 4) | |
6214 | { | |
cf648174 | 6215 | ir.addr -= 2; |
7ad10968 HZ |
6216 | opcode = opcode << 8 | ir.modrm; |
6217 | goto no_support; | |
6218 | } | |
cf648174 | 6219 | if (ir.reg != 4) |
7ad10968 | 6220 | { |
cf648174 | 6221 | if (ir.mod == 3) |
25ea693b | 6222 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6223 | else |
6224 | { | |
cf648174 | 6225 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6226 | return -1; |
6227 | } | |
6228 | } | |
25ea693b | 6229 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6230 | break; |
6231 | ||
a38bba38 | 6232 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6233 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6234 | break; |
6235 | ||
a38bba38 MS |
6236 | case 0x0fab: /* bts */ |
6237 | case 0x0fb3: /* btr */ | |
6238 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6239 | ir.ot = ir.dflag + OT_WORD; |
6240 | if (i386_record_modrm (&ir)) | |
6241 | return -1; | |
6242 | if (ir.mod == 3) | |
25ea693b | 6243 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 HZ |
6244 | else |
6245 | { | |
955db0c0 MS |
6246 | uint64_t addr64; |
6247 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6248 | return -1; |
6249 | regcache_raw_read_unsigned (ir.regcache, | |
6250 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6251 | &addr); |
cf648174 HZ |
6252 | switch (ir.dflag) |
6253 | { | |
6254 | case 0: | |
648d0c8b | 6255 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6256 | break; |
6257 | case 1: | |
648d0c8b | 6258 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6259 | break; |
6260 | case 2: | |
648d0c8b | 6261 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6262 | break; |
6263 | } | |
25ea693b | 6264 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6265 | return -1; |
6266 | if (i386_record_lea_modrm (&ir)) | |
6267 | return -1; | |
6268 | } | |
25ea693b | 6269 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6270 | break; |
6271 | ||
a38bba38 MS |
6272 | case 0x0fbc: /* bsf */ |
6273 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6274 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6275 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6276 | break; |
6277 | ||
6278 | /* bcd */ | |
a38bba38 MS |
6279 | case 0x27: /* daa */ |
6280 | case 0x2f: /* das */ | |
6281 | case 0x37: /* aaa */ | |
6282 | case 0x3f: /* aas */ | |
6283 | case 0xd4: /* aam */ | |
6284 | case 0xd5: /* aad */ | |
cf648174 HZ |
6285 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6286 | { | |
6287 | ir.addr -= 1; | |
6288 | goto no_support; | |
6289 | } | |
25ea693b MM |
6290 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6291 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6292 | break; |
6293 | ||
6294 | /* misc */ | |
a38bba38 | 6295 | case 0x90: /* nop */ |
7ad10968 HZ |
6296 | if (prefixes & PREFIX_LOCK) |
6297 | { | |
6298 | ir.addr -= 1; | |
6299 | goto no_support; | |
6300 | } | |
6301 | break; | |
6302 | ||
a38bba38 | 6303 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6304 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6305 | return -1; | |
425b824a | 6306 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6307 | ir.addr++; |
6308 | goto reswitch; | |
7ad10968 HZ |
6309 | break; |
6310 | ||
7ad10968 | 6311 | /* XXX */ |
a38bba38 | 6312 | case 0xcc: /* int3 */ |
a3c4230a | 6313 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6314 | "int3.\n")); |
6315 | ir.addr -= 1; | |
6316 | goto no_support; | |
6317 | break; | |
6318 | ||
7ad10968 | 6319 | /* XXX */ |
a38bba38 | 6320 | case 0xcd: /* int */ |
7ad10968 HZ |
6321 | { |
6322 | int ret; | |
425b824a | 6323 | uint8_t interrupt; |
4ffa4fc7 PA |
6324 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6325 | return -1; | |
7ad10968 | 6326 | ir.addr++; |
425b824a | 6327 | if (interrupt != 0x80 |
a3c4230a | 6328 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6329 | { |
a3c4230a | 6330 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6331 | "instruction int 0x%02x.\n"), |
425b824a | 6332 | interrupt); |
7ad10968 HZ |
6333 | ir.addr -= 2; |
6334 | goto no_support; | |
6335 | } | |
a3c4230a | 6336 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6337 | if (ret) |
6338 | return ret; | |
6339 | } | |
6340 | break; | |
6341 | ||
7ad10968 | 6342 | /* XXX */ |
a38bba38 | 6343 | case 0xce: /* into */ |
a3c4230a | 6344 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6345 | "instruction into.\n")); |
6346 | ir.addr -= 1; | |
6347 | goto no_support; | |
6348 | break; | |
6349 | ||
a38bba38 MS |
6350 | case 0xfa: /* cli */ |
6351 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6352 | break; |
6353 | ||
a38bba38 | 6354 | case 0x62: /* bound */ |
a3c4230a | 6355 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6356 | "instruction bound.\n")); |
6357 | ir.addr -= 1; | |
6358 | goto no_support; | |
6359 | break; | |
6360 | ||
a38bba38 | 6361 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6362 | case 0x0fc9: |
6363 | case 0x0fca: | |
6364 | case 0x0fcb: | |
6365 | case 0x0fcc: | |
6366 | case 0x0fcd: | |
6367 | case 0x0fce: | |
6368 | case 0x0fcf: | |
25ea693b | 6369 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6370 | break; |
6371 | ||
a38bba38 | 6372 | case 0xd6: /* salc */ |
cf648174 HZ |
6373 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6374 | { | |
6375 | ir.addr -= 1; | |
6376 | goto no_support; | |
6377 | } | |
25ea693b MM |
6378 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6379 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6380 | break; |
6381 | ||
a38bba38 MS |
6382 | case 0xe0: /* loopnz */ |
6383 | case 0xe1: /* loopz */ | |
6384 | case 0xe2: /* loop */ | |
6385 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6386 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6387 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6388 | break; |
6389 | ||
a38bba38 | 6390 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6391 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6392 | "instruction wrmsr.\n")); |
6393 | ir.addr -= 2; | |
6394 | goto no_support; | |
6395 | break; | |
6396 | ||
a38bba38 | 6397 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6398 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6399 | "instruction rdmsr.\n")); |
6400 | ir.addr -= 2; | |
6401 | goto no_support; | |
6402 | break; | |
6403 | ||
a38bba38 | 6404 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6405 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6406 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6407 | break; |
6408 | ||
a38bba38 | 6409 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6410 | { |
6411 | int ret; | |
cf648174 HZ |
6412 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6413 | { | |
6414 | ir.addr -= 2; | |
6415 | goto no_support; | |
6416 | } | |
a3c4230a | 6417 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6418 | { |
a3c4230a | 6419 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6420 | "instruction sysenter.\n")); |
6421 | ir.addr -= 2; | |
6422 | goto no_support; | |
6423 | } | |
a3c4230a | 6424 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6425 | if (ret) |
6426 | return ret; | |
6427 | } | |
6428 | break; | |
6429 | ||
a38bba38 | 6430 | case 0x0f35: /* sysexit */ |
a3c4230a | 6431 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6432 | "instruction sysexit.\n")); |
6433 | ir.addr -= 2; | |
6434 | goto no_support; | |
6435 | break; | |
6436 | ||
a38bba38 | 6437 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6438 | { |
6439 | int ret; | |
a3c4230a | 6440 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6441 | { |
a3c4230a | 6442 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6443 | "instruction syscall.\n")); |
6444 | ir.addr -= 2; | |
6445 | goto no_support; | |
6446 | } | |
a3c4230a | 6447 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6448 | if (ret) |
6449 | return ret; | |
6450 | } | |
6451 | break; | |
6452 | ||
a38bba38 | 6453 | case 0x0f07: /* sysret */ |
a3c4230a | 6454 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6455 | "instruction sysret.\n")); |
6456 | ir.addr -= 2; | |
6457 | goto no_support; | |
6458 | break; | |
6459 | ||
a38bba38 | 6460 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
6461 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6462 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6463 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6464 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6465 | break; |
6466 | ||
a38bba38 | 6467 | case 0xf4: /* hlt */ |
a3c4230a | 6468 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6469 | "instruction hlt.\n")); |
6470 | ir.addr -= 1; | |
6471 | goto no_support; | |
6472 | break; | |
6473 | ||
6474 | case 0x0f00: | |
6475 | if (i386_record_modrm (&ir)) | |
6476 | return -1; | |
6477 | switch (ir.reg) | |
6478 | { | |
a38bba38 MS |
6479 | case 0: /* sldt */ |
6480 | case 1: /* str */ | |
7ad10968 | 6481 | if (ir.mod == 3) |
25ea693b | 6482 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6483 | else |
6484 | { | |
6485 | ir.ot = OT_WORD; | |
6486 | if (i386_record_lea_modrm (&ir)) | |
6487 | return -1; | |
6488 | } | |
6489 | break; | |
a38bba38 MS |
6490 | case 2: /* lldt */ |
6491 | case 3: /* ltr */ | |
7ad10968 | 6492 | break; |
a38bba38 MS |
6493 | case 4: /* verr */ |
6494 | case 5: /* verw */ | |
25ea693b | 6495 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6496 | break; |
6497 | default: | |
6498 | ir.addr -= 3; | |
6499 | opcode = opcode << 8 | ir.modrm; | |
6500 | goto no_support; | |
6501 | break; | |
6502 | } | |
6503 | break; | |
6504 | ||
6505 | case 0x0f01: | |
6506 | if (i386_record_modrm (&ir)) | |
6507 | return -1; | |
6508 | switch (ir.reg) | |
6509 | { | |
a38bba38 | 6510 | case 0: /* sgdt */ |
7ad10968 | 6511 | { |
955db0c0 | 6512 | uint64_t addr64; |
7ad10968 HZ |
6513 | |
6514 | if (ir.mod == 3) | |
6515 | { | |
6516 | ir.addr -= 3; | |
6517 | opcode = opcode << 8 | ir.modrm; | |
6518 | goto no_support; | |
6519 | } | |
d7877f7e | 6520 | if (ir.override >= 0) |
7ad10968 | 6521 | { |
25ea693b | 6522 | if (record_full_memory_query) |
bb08c432 HZ |
6523 | { |
6524 | int q; | |
6525 | ||
6526 | target_terminal_ours (); | |
6527 | q = yquery (_("\ | |
6528 | Process record ignores the memory change of instruction at address %s\n\ | |
6529 | because it can't get the value of the segment register.\n\ | |
6530 | Do you want to stop the program?"), | |
6531 | paddress (gdbarch, ir.orig_addr)); | |
6532 | target_terminal_inferior (); | |
6533 | if (q) | |
6534 | return -1; | |
6535 | } | |
7ad10968 HZ |
6536 | } |
6537 | else | |
6538 | { | |
955db0c0 | 6539 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6540 | return -1; |
25ea693b | 6541 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6542 | return -1; |
955db0c0 | 6543 | addr64 += 2; |
cf648174 HZ |
6544 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6545 | { | |
25ea693b | 6546 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6547 | return -1; |
6548 | } | |
6549 | else | |
6550 | { | |
25ea693b | 6551 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6552 | return -1; |
6553 | } | |
7ad10968 HZ |
6554 | } |
6555 | } | |
6556 | break; | |
6557 | case 1: | |
6558 | if (ir.mod == 3) | |
6559 | { | |
6560 | switch (ir.rm) | |
6561 | { | |
a38bba38 | 6562 | case 0: /* monitor */ |
7ad10968 | 6563 | break; |
a38bba38 | 6564 | case 1: /* mwait */ |
25ea693b | 6565 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6566 | break; |
6567 | default: | |
6568 | ir.addr -= 3; | |
6569 | opcode = opcode << 8 | ir.modrm; | |
6570 | goto no_support; | |
6571 | break; | |
6572 | } | |
6573 | } | |
6574 | else | |
6575 | { | |
6576 | /* sidt */ | |
d7877f7e | 6577 | if (ir.override >= 0) |
7ad10968 | 6578 | { |
25ea693b | 6579 | if (record_full_memory_query) |
bb08c432 HZ |
6580 | { |
6581 | int q; | |
6582 | ||
6583 | target_terminal_ours (); | |
6584 | q = yquery (_("\ | |
6585 | Process record ignores the memory change of instruction at address %s\n\ | |
6586 | because it can't get the value of the segment register.\n\ | |
6587 | Do you want to stop the program?"), | |
6588 | paddress (gdbarch, ir.orig_addr)); | |
6589 | target_terminal_inferior (); | |
6590 | if (q) | |
6591 | return -1; | |
6592 | } | |
7ad10968 HZ |
6593 | } |
6594 | else | |
6595 | { | |
955db0c0 | 6596 | uint64_t addr64; |
7ad10968 | 6597 | |
955db0c0 | 6598 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6599 | return -1; |
25ea693b | 6600 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6601 | return -1; |
955db0c0 | 6602 | addr64 += 2; |
cf648174 HZ |
6603 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6604 | { | |
25ea693b | 6605 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6606 | return -1; |
6607 | } | |
6608 | else | |
6609 | { | |
25ea693b | 6610 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6611 | return -1; |
6612 | } | |
7ad10968 HZ |
6613 | } |
6614 | } | |
6615 | break; | |
a38bba38 | 6616 | case 2: /* lgdt */ |
3800e645 MS |
6617 | if (ir.mod == 3) |
6618 | { | |
6619 | /* xgetbv */ | |
6620 | if (ir.rm == 0) | |
6621 | { | |
25ea693b MM |
6622 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6623 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
6624 | break; |
6625 | } | |
6626 | /* xsetbv */ | |
6627 | else if (ir.rm == 1) | |
6628 | break; | |
6629 | } | |
a38bba38 | 6630 | case 3: /* lidt */ |
7ad10968 HZ |
6631 | if (ir.mod == 3) |
6632 | { | |
6633 | ir.addr -= 3; | |
6634 | opcode = opcode << 8 | ir.modrm; | |
6635 | goto no_support; | |
6636 | } | |
6637 | break; | |
a38bba38 | 6638 | case 4: /* smsw */ |
7ad10968 HZ |
6639 | if (ir.mod == 3) |
6640 | { | |
25ea693b | 6641 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
6642 | return -1; |
6643 | } | |
6644 | else | |
6645 | { | |
6646 | ir.ot = OT_WORD; | |
6647 | if (i386_record_lea_modrm (&ir)) | |
6648 | return -1; | |
6649 | } | |
25ea693b | 6650 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6651 | break; |
a38bba38 | 6652 | case 6: /* lmsw */ |
25ea693b | 6653 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 6654 | break; |
a38bba38 | 6655 | case 7: /* invlpg */ |
cf648174 HZ |
6656 | if (ir.mod == 3) |
6657 | { | |
6658 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 6659 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 HZ |
6660 | else |
6661 | { | |
6662 | ir.addr -= 3; | |
6663 | opcode = opcode << 8 | ir.modrm; | |
6664 | goto no_support; | |
6665 | } | |
6666 | } | |
6667 | else | |
25ea693b | 6668 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6669 | break; |
6670 | default: | |
6671 | ir.addr -= 3; | |
6672 | opcode = opcode << 8 | ir.modrm; | |
6673 | goto no_support; | |
7ad10968 HZ |
6674 | break; |
6675 | } | |
6676 | break; | |
6677 | ||
a38bba38 MS |
6678 | case 0x0f08: /* invd */ |
6679 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
6680 | break; |
6681 | ||
a38bba38 | 6682 | case 0x63: /* arpl */ |
7ad10968 HZ |
6683 | if (i386_record_modrm (&ir)) |
6684 | return -1; | |
cf648174 HZ |
6685 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
6686 | { | |
25ea693b MM |
6687 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
6688 | ? (ir.reg | rex_r) : ir.rm); | |
cf648174 | 6689 | } |
7ad10968 | 6690 | else |
cf648174 HZ |
6691 | { |
6692 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
6693 | if (i386_record_lea_modrm (&ir)) | |
6694 | return -1; | |
6695 | } | |
6696 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 6697 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6698 | break; |
6699 | ||
a38bba38 MS |
6700 | case 0x0f02: /* lar */ |
6701 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
6702 | if (i386_record_modrm (&ir)) |
6703 | return -1; | |
25ea693b MM |
6704 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6705 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6706 | break; |
6707 | ||
6708 | case 0x0f18: | |
cf648174 HZ |
6709 | if (i386_record_modrm (&ir)) |
6710 | return -1; | |
6711 | if (ir.mod == 3 && ir.reg == 3) | |
6712 | { | |
6713 | ir.addr -= 3; | |
6714 | opcode = opcode << 8 | ir.modrm; | |
6715 | goto no_support; | |
6716 | } | |
7ad10968 HZ |
6717 | break; |
6718 | ||
7ad10968 HZ |
6719 | case 0x0f19: |
6720 | case 0x0f1a: | |
6721 | case 0x0f1b: | |
6722 | case 0x0f1c: | |
6723 | case 0x0f1d: | |
6724 | case 0x0f1e: | |
6725 | case 0x0f1f: | |
a38bba38 | 6726 | /* nop (multi byte) */ |
7ad10968 HZ |
6727 | break; |
6728 | ||
a38bba38 MS |
6729 | case 0x0f20: /* mov reg, crN */ |
6730 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
6731 | if (i386_record_modrm (&ir)) |
6732 | return -1; | |
6733 | if ((ir.modrm & 0xc0) != 0xc0) | |
6734 | { | |
cf648174 | 6735 | ir.addr -= 3; |
7ad10968 HZ |
6736 | opcode = opcode << 8 | ir.modrm; |
6737 | goto no_support; | |
6738 | } | |
6739 | switch (ir.reg) | |
6740 | { | |
6741 | case 0: | |
6742 | case 2: | |
6743 | case 3: | |
6744 | case 4: | |
6745 | case 8: | |
6746 | if (opcode & 2) | |
25ea693b | 6747 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6748 | else |
25ea693b | 6749 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6750 | break; |
6751 | default: | |
cf648174 | 6752 | ir.addr -= 3; |
7ad10968 HZ |
6753 | opcode = opcode << 8 | ir.modrm; |
6754 | goto no_support; | |
6755 | break; | |
6756 | } | |
6757 | break; | |
6758 | ||
a38bba38 MS |
6759 | case 0x0f21: /* mov reg, drN */ |
6760 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
6761 | if (i386_record_modrm (&ir)) |
6762 | return -1; | |
6763 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
6764 | || ir.reg == 5 || ir.reg >= 8) | |
6765 | { | |
cf648174 | 6766 | ir.addr -= 3; |
7ad10968 HZ |
6767 | opcode = opcode << 8 | ir.modrm; |
6768 | goto no_support; | |
6769 | } | |
6770 | if (opcode & 2) | |
25ea693b | 6771 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6772 | else |
25ea693b | 6773 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6774 | break; |
6775 | ||
a38bba38 | 6776 | case 0x0f06: /* clts */ |
25ea693b | 6777 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6778 | break; |
6779 | ||
a3c4230a HZ |
6780 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
6781 | ||
6782 | case 0x0f0d: /* 3DNow! prefetch */ | |
6783 | break; | |
6784 | ||
6785 | case 0x0f0e: /* 3DNow! femms */ | |
6786 | case 0x0f77: /* emms */ | |
6787 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
6788 | goto no_support; | |
25ea693b | 6789 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
6790 | break; |
6791 | ||
6792 | case 0x0f0f: /* 3DNow! data */ | |
6793 | if (i386_record_modrm (&ir)) | |
6794 | return -1; | |
4ffa4fc7 PA |
6795 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6796 | return -1; | |
a3c4230a HZ |
6797 | ir.addr++; |
6798 | switch (opcode8) | |
6799 | { | |
6800 | case 0x0c: /* 3DNow! pi2fw */ | |
6801 | case 0x0d: /* 3DNow! pi2fd */ | |
6802 | case 0x1c: /* 3DNow! pf2iw */ | |
6803 | case 0x1d: /* 3DNow! pf2id */ | |
6804 | case 0x8a: /* 3DNow! pfnacc */ | |
6805 | case 0x8e: /* 3DNow! pfpnacc */ | |
6806 | case 0x90: /* 3DNow! pfcmpge */ | |
6807 | case 0x94: /* 3DNow! pfmin */ | |
6808 | case 0x96: /* 3DNow! pfrcp */ | |
6809 | case 0x97: /* 3DNow! pfrsqrt */ | |
6810 | case 0x9a: /* 3DNow! pfsub */ | |
6811 | case 0x9e: /* 3DNow! pfadd */ | |
6812 | case 0xa0: /* 3DNow! pfcmpgt */ | |
6813 | case 0xa4: /* 3DNow! pfmax */ | |
6814 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
6815 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
6816 | case 0xaa: /* 3DNow! pfsubr */ | |
6817 | case 0xae: /* 3DNow! pfacc */ | |
6818 | case 0xb0: /* 3DNow! pfcmpeq */ | |
6819 | case 0xb4: /* 3DNow! pfmul */ | |
6820 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
6821 | case 0xb7: /* 3DNow! pmulhrw */ | |
6822 | case 0xbb: /* 3DNow! pswapd */ | |
6823 | case 0xbf: /* 3DNow! pavgusb */ | |
6824 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6825 | goto no_support_3dnow_data; | |
25ea693b | 6826 | record_full_arch_list_add_reg (ir.regcache, ir.reg); |
a3c4230a HZ |
6827 | break; |
6828 | ||
6829 | default: | |
6830 | no_support_3dnow_data: | |
6831 | opcode = (opcode << 8) | opcode8; | |
6832 | goto no_support; | |
6833 | break; | |
6834 | } | |
6835 | break; | |
6836 | ||
6837 | case 0x0faa: /* rsm */ | |
25ea693b MM |
6838 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6839 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6840 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6841 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6842 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
6843 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6844 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
6845 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6846 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
6847 | break; |
6848 | ||
6849 | case 0x0fae: | |
6850 | if (i386_record_modrm (&ir)) | |
6851 | return -1; | |
6852 | switch(ir.reg) | |
6853 | { | |
6854 | case 0: /* fxsave */ | |
6855 | { | |
6856 | uint64_t tmpu64; | |
6857 | ||
25ea693b | 6858 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
6859 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
6860 | return -1; | |
25ea693b | 6861 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
a3c4230a HZ |
6862 | return -1; |
6863 | } | |
6864 | break; | |
6865 | ||
6866 | case 1: /* fxrstor */ | |
6867 | { | |
6868 | int i; | |
6869 | ||
25ea693b | 6870 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
6871 | |
6872 | for (i = I387_MM0_REGNUM (tdep); | |
6873 | i386_mmx_regnum_p (gdbarch, i); i++) | |
25ea693b | 6874 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
6875 | |
6876 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 6877 | i386_xmm_regnum_p (gdbarch, i); i++) |
25ea693b | 6878 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
6879 | |
6880 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
25ea693b MM |
6881 | record_full_arch_list_add_reg (ir.regcache, |
6882 | I387_MXCSR_REGNUM(tdep)); | |
a3c4230a HZ |
6883 | |
6884 | for (i = I387_ST0_REGNUM (tdep); | |
6885 | i386_fp_regnum_p (gdbarch, i); i++) | |
25ea693b | 6886 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
6887 | |
6888 | for (i = I387_FCTRL_REGNUM (tdep); | |
6889 | i386_fpc_regnum_p (gdbarch, i); i++) | |
25ea693b | 6890 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
6891 | } |
6892 | break; | |
6893 | ||
6894 | case 2: /* ldmxcsr */ | |
6895 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6896 | goto no_support; | |
25ea693b | 6897 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
a3c4230a HZ |
6898 | break; |
6899 | ||
6900 | case 3: /* stmxcsr */ | |
6901 | ir.ot = OT_LONG; | |
6902 | if (i386_record_lea_modrm (&ir)) | |
6903 | return -1; | |
6904 | break; | |
6905 | ||
6906 | case 5: /* lfence */ | |
6907 | case 6: /* mfence */ | |
6908 | case 7: /* sfence clflush */ | |
6909 | break; | |
6910 | ||
6911 | default: | |
6912 | opcode = (opcode << 8) | ir.modrm; | |
6913 | goto no_support; | |
6914 | break; | |
6915 | } | |
6916 | break; | |
6917 | ||
6918 | case 0x0fc3: /* movnti */ | |
6919 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
6920 | if (i386_record_modrm (&ir)) | |
6921 | return -1; | |
6922 | if (ir.mod == 3) | |
6923 | goto no_support; | |
6924 | ir.reg |= rex_r; | |
6925 | if (i386_record_lea_modrm (&ir)) | |
6926 | return -1; | |
6927 | break; | |
6928 | ||
6929 | /* Add prefix to opcode. */ | |
6930 | case 0x0f10: | |
6931 | case 0x0f11: | |
6932 | case 0x0f12: | |
6933 | case 0x0f13: | |
6934 | case 0x0f14: | |
6935 | case 0x0f15: | |
6936 | case 0x0f16: | |
6937 | case 0x0f17: | |
6938 | case 0x0f28: | |
6939 | case 0x0f29: | |
6940 | case 0x0f2a: | |
6941 | case 0x0f2b: | |
6942 | case 0x0f2c: | |
6943 | case 0x0f2d: | |
6944 | case 0x0f2e: | |
6945 | case 0x0f2f: | |
6946 | case 0x0f38: | |
6947 | case 0x0f39: | |
6948 | case 0x0f3a: | |
6949 | case 0x0f50: | |
6950 | case 0x0f51: | |
6951 | case 0x0f52: | |
6952 | case 0x0f53: | |
6953 | case 0x0f54: | |
6954 | case 0x0f55: | |
6955 | case 0x0f56: | |
6956 | case 0x0f57: | |
6957 | case 0x0f58: | |
6958 | case 0x0f59: | |
6959 | case 0x0f5a: | |
6960 | case 0x0f5b: | |
6961 | case 0x0f5c: | |
6962 | case 0x0f5d: | |
6963 | case 0x0f5e: | |
6964 | case 0x0f5f: | |
6965 | case 0x0f60: | |
6966 | case 0x0f61: | |
6967 | case 0x0f62: | |
6968 | case 0x0f63: | |
6969 | case 0x0f64: | |
6970 | case 0x0f65: | |
6971 | case 0x0f66: | |
6972 | case 0x0f67: | |
6973 | case 0x0f68: | |
6974 | case 0x0f69: | |
6975 | case 0x0f6a: | |
6976 | case 0x0f6b: | |
6977 | case 0x0f6c: | |
6978 | case 0x0f6d: | |
6979 | case 0x0f6e: | |
6980 | case 0x0f6f: | |
6981 | case 0x0f70: | |
6982 | case 0x0f71: | |
6983 | case 0x0f72: | |
6984 | case 0x0f73: | |
6985 | case 0x0f74: | |
6986 | case 0x0f75: | |
6987 | case 0x0f76: | |
6988 | case 0x0f7c: | |
6989 | case 0x0f7d: | |
6990 | case 0x0f7e: | |
6991 | case 0x0f7f: | |
6992 | case 0x0fb8: | |
6993 | case 0x0fc2: | |
6994 | case 0x0fc4: | |
6995 | case 0x0fc5: | |
6996 | case 0x0fc6: | |
6997 | case 0x0fd0: | |
6998 | case 0x0fd1: | |
6999 | case 0x0fd2: | |
7000 | case 0x0fd3: | |
7001 | case 0x0fd4: | |
7002 | case 0x0fd5: | |
7003 | case 0x0fd6: | |
7004 | case 0x0fd7: | |
7005 | case 0x0fd8: | |
7006 | case 0x0fd9: | |
7007 | case 0x0fda: | |
7008 | case 0x0fdb: | |
7009 | case 0x0fdc: | |
7010 | case 0x0fdd: | |
7011 | case 0x0fde: | |
7012 | case 0x0fdf: | |
7013 | case 0x0fe0: | |
7014 | case 0x0fe1: | |
7015 | case 0x0fe2: | |
7016 | case 0x0fe3: | |
7017 | case 0x0fe4: | |
7018 | case 0x0fe5: | |
7019 | case 0x0fe6: | |
7020 | case 0x0fe7: | |
7021 | case 0x0fe8: | |
7022 | case 0x0fe9: | |
7023 | case 0x0fea: | |
7024 | case 0x0feb: | |
7025 | case 0x0fec: | |
7026 | case 0x0fed: | |
7027 | case 0x0fee: | |
7028 | case 0x0fef: | |
7029 | case 0x0ff0: | |
7030 | case 0x0ff1: | |
7031 | case 0x0ff2: | |
7032 | case 0x0ff3: | |
7033 | case 0x0ff4: | |
7034 | case 0x0ff5: | |
7035 | case 0x0ff6: | |
7036 | case 0x0ff7: | |
7037 | case 0x0ff8: | |
7038 | case 0x0ff9: | |
7039 | case 0x0ffa: | |
7040 | case 0x0ffb: | |
7041 | case 0x0ffc: | |
7042 | case 0x0ffd: | |
7043 | case 0x0ffe: | |
7044 | switch (prefixes) | |
7045 | { | |
7046 | case PREFIX_REPNZ: | |
7047 | opcode |= 0xf20000; | |
7048 | break; | |
7049 | case PREFIX_DATA: | |
7050 | opcode |= 0x660000; | |
7051 | break; | |
7052 | case PREFIX_REPZ: | |
7053 | opcode |= 0xf30000; | |
7054 | break; | |
7055 | } | |
7056 | reswitch_prefix_add: | |
7057 | switch (opcode) | |
7058 | { | |
7059 | case 0x0f38: | |
7060 | case 0x660f38: | |
7061 | case 0xf20f38: | |
7062 | case 0x0f3a: | |
7063 | case 0x660f3a: | |
4ffa4fc7 PA |
7064 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7065 | return -1; | |
a3c4230a HZ |
7066 | ir.addr++; |
7067 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7068 | goto reswitch_prefix_add; | |
7069 | break; | |
7070 | ||
7071 | case 0x0f10: /* movups */ | |
7072 | case 0x660f10: /* movupd */ | |
7073 | case 0xf30f10: /* movss */ | |
7074 | case 0xf20f10: /* movsd */ | |
7075 | case 0x0f12: /* movlps */ | |
7076 | case 0x660f12: /* movlpd */ | |
7077 | case 0xf30f12: /* movsldup */ | |
7078 | case 0xf20f12: /* movddup */ | |
7079 | case 0x0f14: /* unpcklps */ | |
7080 | case 0x660f14: /* unpcklpd */ | |
7081 | case 0x0f15: /* unpckhps */ | |
7082 | case 0x660f15: /* unpckhpd */ | |
7083 | case 0x0f16: /* movhps */ | |
7084 | case 0x660f16: /* movhpd */ | |
7085 | case 0xf30f16: /* movshdup */ | |
7086 | case 0x0f28: /* movaps */ | |
7087 | case 0x660f28: /* movapd */ | |
7088 | case 0x0f2a: /* cvtpi2ps */ | |
7089 | case 0x660f2a: /* cvtpi2pd */ | |
7090 | case 0xf30f2a: /* cvtsi2ss */ | |
7091 | case 0xf20f2a: /* cvtsi2sd */ | |
7092 | case 0x0f2c: /* cvttps2pi */ | |
7093 | case 0x660f2c: /* cvttpd2pi */ | |
7094 | case 0x0f2d: /* cvtps2pi */ | |
7095 | case 0x660f2d: /* cvtpd2pi */ | |
7096 | case 0x660f3800: /* pshufb */ | |
7097 | case 0x660f3801: /* phaddw */ | |
7098 | case 0x660f3802: /* phaddd */ | |
7099 | case 0x660f3803: /* phaddsw */ | |
7100 | case 0x660f3804: /* pmaddubsw */ | |
7101 | case 0x660f3805: /* phsubw */ | |
7102 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 7103 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
7104 | case 0x660f3808: /* psignb */ |
7105 | case 0x660f3809: /* psignw */ | |
7106 | case 0x660f380a: /* psignd */ | |
7107 | case 0x660f380b: /* pmulhrsw */ | |
7108 | case 0x660f3810: /* pblendvb */ | |
7109 | case 0x660f3814: /* blendvps */ | |
7110 | case 0x660f3815: /* blendvpd */ | |
7111 | case 0x660f381c: /* pabsb */ | |
7112 | case 0x660f381d: /* pabsw */ | |
7113 | case 0x660f381e: /* pabsd */ | |
7114 | case 0x660f3820: /* pmovsxbw */ | |
7115 | case 0x660f3821: /* pmovsxbd */ | |
7116 | case 0x660f3822: /* pmovsxbq */ | |
7117 | case 0x660f3823: /* pmovsxwd */ | |
7118 | case 0x660f3824: /* pmovsxwq */ | |
7119 | case 0x660f3825: /* pmovsxdq */ | |
7120 | case 0x660f3828: /* pmuldq */ | |
7121 | case 0x660f3829: /* pcmpeqq */ | |
7122 | case 0x660f382a: /* movntdqa */ | |
7123 | case 0x660f3a08: /* roundps */ | |
7124 | case 0x660f3a09: /* roundpd */ | |
7125 | case 0x660f3a0a: /* roundss */ | |
7126 | case 0x660f3a0b: /* roundsd */ | |
7127 | case 0x660f3a0c: /* blendps */ | |
7128 | case 0x660f3a0d: /* blendpd */ | |
7129 | case 0x660f3a0e: /* pblendw */ | |
7130 | case 0x660f3a0f: /* palignr */ | |
7131 | case 0x660f3a20: /* pinsrb */ | |
7132 | case 0x660f3a21: /* insertps */ | |
7133 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7134 | case 0x660f3a40: /* dpps */ | |
7135 | case 0x660f3a41: /* dppd */ | |
7136 | case 0x660f3a42: /* mpsadbw */ | |
7137 | case 0x660f3a60: /* pcmpestrm */ | |
7138 | case 0x660f3a61: /* pcmpestri */ | |
7139 | case 0x660f3a62: /* pcmpistrm */ | |
7140 | case 0x660f3a63: /* pcmpistri */ | |
7141 | case 0x0f51: /* sqrtps */ | |
7142 | case 0x660f51: /* sqrtpd */ | |
7143 | case 0xf20f51: /* sqrtsd */ | |
7144 | case 0xf30f51: /* sqrtss */ | |
7145 | case 0x0f52: /* rsqrtps */ | |
7146 | case 0xf30f52: /* rsqrtss */ | |
7147 | case 0x0f53: /* rcpps */ | |
7148 | case 0xf30f53: /* rcpss */ | |
7149 | case 0x0f54: /* andps */ | |
7150 | case 0x660f54: /* andpd */ | |
7151 | case 0x0f55: /* andnps */ | |
7152 | case 0x660f55: /* andnpd */ | |
7153 | case 0x0f56: /* orps */ | |
7154 | case 0x660f56: /* orpd */ | |
7155 | case 0x0f57: /* xorps */ | |
7156 | case 0x660f57: /* xorpd */ | |
7157 | case 0x0f58: /* addps */ | |
7158 | case 0x660f58: /* addpd */ | |
7159 | case 0xf20f58: /* addsd */ | |
7160 | case 0xf30f58: /* addss */ | |
7161 | case 0x0f59: /* mulps */ | |
7162 | case 0x660f59: /* mulpd */ | |
7163 | case 0xf20f59: /* mulsd */ | |
7164 | case 0xf30f59: /* mulss */ | |
7165 | case 0x0f5a: /* cvtps2pd */ | |
7166 | case 0x660f5a: /* cvtpd2ps */ | |
7167 | case 0xf20f5a: /* cvtsd2ss */ | |
7168 | case 0xf30f5a: /* cvtss2sd */ | |
7169 | case 0x0f5b: /* cvtdq2ps */ | |
7170 | case 0x660f5b: /* cvtps2dq */ | |
7171 | case 0xf30f5b: /* cvttps2dq */ | |
7172 | case 0x0f5c: /* subps */ | |
7173 | case 0x660f5c: /* subpd */ | |
7174 | case 0xf20f5c: /* subsd */ | |
7175 | case 0xf30f5c: /* subss */ | |
7176 | case 0x0f5d: /* minps */ | |
7177 | case 0x660f5d: /* minpd */ | |
7178 | case 0xf20f5d: /* minsd */ | |
7179 | case 0xf30f5d: /* minss */ | |
7180 | case 0x0f5e: /* divps */ | |
7181 | case 0x660f5e: /* divpd */ | |
7182 | case 0xf20f5e: /* divsd */ | |
7183 | case 0xf30f5e: /* divss */ | |
7184 | case 0x0f5f: /* maxps */ | |
7185 | case 0x660f5f: /* maxpd */ | |
7186 | case 0xf20f5f: /* maxsd */ | |
7187 | case 0xf30f5f: /* maxss */ | |
7188 | case 0x660f60: /* punpcklbw */ | |
7189 | case 0x660f61: /* punpcklwd */ | |
7190 | case 0x660f62: /* punpckldq */ | |
7191 | case 0x660f63: /* packsswb */ | |
7192 | case 0x660f64: /* pcmpgtb */ | |
7193 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 7194 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
7195 | case 0x660f67: /* packuswb */ |
7196 | case 0x660f68: /* punpckhbw */ | |
7197 | case 0x660f69: /* punpckhwd */ | |
7198 | case 0x660f6a: /* punpckhdq */ | |
7199 | case 0x660f6b: /* packssdw */ | |
7200 | case 0x660f6c: /* punpcklqdq */ | |
7201 | case 0x660f6d: /* punpckhqdq */ | |
7202 | case 0x660f6e: /* movd */ | |
7203 | case 0x660f6f: /* movdqa */ | |
7204 | case 0xf30f6f: /* movdqu */ | |
7205 | case 0x660f70: /* pshufd */ | |
7206 | case 0xf20f70: /* pshuflw */ | |
7207 | case 0xf30f70: /* pshufhw */ | |
7208 | case 0x660f74: /* pcmpeqb */ | |
7209 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 7210 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
7211 | case 0x660f7c: /* haddpd */ |
7212 | case 0xf20f7c: /* haddps */ | |
7213 | case 0x660f7d: /* hsubpd */ | |
7214 | case 0xf20f7d: /* hsubps */ | |
7215 | case 0xf30f7e: /* movq */ | |
7216 | case 0x0fc2: /* cmpps */ | |
7217 | case 0x660fc2: /* cmppd */ | |
7218 | case 0xf20fc2: /* cmpsd */ | |
7219 | case 0xf30fc2: /* cmpss */ | |
7220 | case 0x660fc4: /* pinsrw */ | |
7221 | case 0x0fc6: /* shufps */ | |
7222 | case 0x660fc6: /* shufpd */ | |
7223 | case 0x660fd0: /* addsubpd */ | |
7224 | case 0xf20fd0: /* addsubps */ | |
7225 | case 0x660fd1: /* psrlw */ | |
7226 | case 0x660fd2: /* psrld */ | |
7227 | case 0x660fd3: /* psrlq */ | |
7228 | case 0x660fd4: /* paddq */ | |
7229 | case 0x660fd5: /* pmullw */ | |
7230 | case 0xf30fd6: /* movq2dq */ | |
7231 | case 0x660fd8: /* psubusb */ | |
7232 | case 0x660fd9: /* psubusw */ | |
7233 | case 0x660fda: /* pminub */ | |
7234 | case 0x660fdb: /* pand */ | |
7235 | case 0x660fdc: /* paddusb */ | |
7236 | case 0x660fdd: /* paddusw */ | |
7237 | case 0x660fde: /* pmaxub */ | |
7238 | case 0x660fdf: /* pandn */ | |
7239 | case 0x660fe0: /* pavgb */ | |
7240 | case 0x660fe1: /* psraw */ | |
7241 | case 0x660fe2: /* psrad */ | |
7242 | case 0x660fe3: /* pavgw */ | |
7243 | case 0x660fe4: /* pmulhuw */ | |
7244 | case 0x660fe5: /* pmulhw */ | |
7245 | case 0x660fe6: /* cvttpd2dq */ | |
7246 | case 0xf20fe6: /* cvtpd2dq */ | |
7247 | case 0xf30fe6: /* cvtdq2pd */ | |
7248 | case 0x660fe8: /* psubsb */ | |
7249 | case 0x660fe9: /* psubsw */ | |
7250 | case 0x660fea: /* pminsw */ | |
7251 | case 0x660feb: /* por */ | |
7252 | case 0x660fec: /* paddsb */ | |
7253 | case 0x660fed: /* paddsw */ | |
7254 | case 0x660fee: /* pmaxsw */ | |
7255 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7256 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7257 | case 0x660ff1: /* psllw */ |
7258 | case 0x660ff2: /* pslld */ | |
7259 | case 0x660ff3: /* psllq */ | |
7260 | case 0x660ff4: /* pmuludq */ | |
7261 | case 0x660ff5: /* pmaddwd */ | |
7262 | case 0x660ff6: /* psadbw */ | |
7263 | case 0x660ff8: /* psubb */ | |
7264 | case 0x660ff9: /* psubw */ | |
56d2815c | 7265 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7266 | case 0x660ffb: /* psubq */ |
7267 | case 0x660ffc: /* paddb */ | |
7268 | case 0x660ffd: /* paddw */ | |
56d2815c | 7269 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7270 | if (i386_record_modrm (&ir)) |
7271 | return -1; | |
7272 | ir.reg |= rex_r; | |
c131fcee | 7273 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a | 7274 | goto no_support; |
25ea693b MM |
7275 | record_full_arch_list_add_reg (ir.regcache, |
7276 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
a3c4230a | 7277 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
25ea693b | 7278 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7279 | break; |
7280 | ||
7281 | case 0x0f11: /* movups */ | |
7282 | case 0x660f11: /* movupd */ | |
7283 | case 0xf30f11: /* movss */ | |
7284 | case 0xf20f11: /* movsd */ | |
7285 | case 0x0f13: /* movlps */ | |
7286 | case 0x660f13: /* movlpd */ | |
7287 | case 0x0f17: /* movhps */ | |
7288 | case 0x660f17: /* movhpd */ | |
7289 | case 0x0f29: /* movaps */ | |
7290 | case 0x660f29: /* movapd */ | |
7291 | case 0x660f3a14: /* pextrb */ | |
7292 | case 0x660f3a15: /* pextrw */ | |
7293 | case 0x660f3a16: /* pextrd pextrq */ | |
7294 | case 0x660f3a17: /* extractps */ | |
7295 | case 0x660f7f: /* movdqa */ | |
7296 | case 0xf30f7f: /* movdqu */ | |
7297 | if (i386_record_modrm (&ir)) | |
7298 | return -1; | |
7299 | if (ir.mod == 3) | |
7300 | { | |
7301 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7302 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7303 | goto no_support; | |
7304 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7305 | if (!i386_xmm_regnum_p (gdbarch, |
7306 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7307 | goto no_support; |
25ea693b MM |
7308 | record_full_arch_list_add_reg (ir.regcache, |
7309 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7310 | } |
7311 | else | |
7312 | { | |
7313 | switch (opcode) | |
7314 | { | |
7315 | case 0x660f3a14: | |
7316 | ir.ot = OT_BYTE; | |
7317 | break; | |
7318 | case 0x660f3a15: | |
7319 | ir.ot = OT_WORD; | |
7320 | break; | |
7321 | case 0x660f3a16: | |
7322 | ir.ot = OT_LONG; | |
7323 | break; | |
7324 | case 0x660f3a17: | |
7325 | ir.ot = OT_QUAD; | |
7326 | break; | |
7327 | default: | |
7328 | ir.ot = OT_DQUAD; | |
7329 | break; | |
7330 | } | |
7331 | if (i386_record_lea_modrm (&ir)) | |
7332 | return -1; | |
7333 | } | |
7334 | break; | |
7335 | ||
7336 | case 0x0f2b: /* movntps */ | |
7337 | case 0x660f2b: /* movntpd */ | |
7338 | case 0x0fe7: /* movntq */ | |
7339 | case 0x660fe7: /* movntdq */ | |
7340 | if (ir.mod == 3) | |
7341 | goto no_support; | |
7342 | if (opcode == 0x0fe7) | |
7343 | ir.ot = OT_QUAD; | |
7344 | else | |
7345 | ir.ot = OT_DQUAD; | |
7346 | if (i386_record_lea_modrm (&ir)) | |
7347 | return -1; | |
7348 | break; | |
7349 | ||
7350 | case 0xf30f2c: /* cvttss2si */ | |
7351 | case 0xf20f2c: /* cvttsd2si */ | |
7352 | case 0xf30f2d: /* cvtss2si */ | |
7353 | case 0xf20f2d: /* cvtsd2si */ | |
7354 | case 0xf20f38f0: /* crc32 */ | |
7355 | case 0xf20f38f1: /* crc32 */ | |
7356 | case 0x0f50: /* movmskps */ | |
7357 | case 0x660f50: /* movmskpd */ | |
7358 | case 0x0fc5: /* pextrw */ | |
7359 | case 0x660fc5: /* pextrw */ | |
7360 | case 0x0fd7: /* pmovmskb */ | |
7361 | case 0x660fd7: /* pmovmskb */ | |
25ea693b | 7362 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
a3c4230a HZ |
7363 | break; |
7364 | ||
7365 | case 0x0f3800: /* pshufb */ | |
7366 | case 0x0f3801: /* phaddw */ | |
7367 | case 0x0f3802: /* phaddd */ | |
7368 | case 0x0f3803: /* phaddsw */ | |
7369 | case 0x0f3804: /* pmaddubsw */ | |
7370 | case 0x0f3805: /* phsubw */ | |
7371 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7372 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7373 | case 0x0f3808: /* psignb */ |
7374 | case 0x0f3809: /* psignw */ | |
7375 | case 0x0f380a: /* psignd */ | |
7376 | case 0x0f380b: /* pmulhrsw */ | |
7377 | case 0x0f381c: /* pabsb */ | |
7378 | case 0x0f381d: /* pabsw */ | |
7379 | case 0x0f381e: /* pabsd */ | |
7380 | case 0x0f382b: /* packusdw */ | |
7381 | case 0x0f3830: /* pmovzxbw */ | |
7382 | case 0x0f3831: /* pmovzxbd */ | |
7383 | case 0x0f3832: /* pmovzxbq */ | |
7384 | case 0x0f3833: /* pmovzxwd */ | |
7385 | case 0x0f3834: /* pmovzxwq */ | |
7386 | case 0x0f3835: /* pmovzxdq */ | |
7387 | case 0x0f3837: /* pcmpgtq */ | |
7388 | case 0x0f3838: /* pminsb */ | |
7389 | case 0x0f3839: /* pminsd */ | |
7390 | case 0x0f383a: /* pminuw */ | |
7391 | case 0x0f383b: /* pminud */ | |
7392 | case 0x0f383c: /* pmaxsb */ | |
7393 | case 0x0f383d: /* pmaxsd */ | |
7394 | case 0x0f383e: /* pmaxuw */ | |
7395 | case 0x0f383f: /* pmaxud */ | |
7396 | case 0x0f3840: /* pmulld */ | |
7397 | case 0x0f3841: /* phminposuw */ | |
7398 | case 0x0f3a0f: /* palignr */ | |
7399 | case 0x0f60: /* punpcklbw */ | |
7400 | case 0x0f61: /* punpcklwd */ | |
7401 | case 0x0f62: /* punpckldq */ | |
7402 | case 0x0f63: /* packsswb */ | |
7403 | case 0x0f64: /* pcmpgtb */ | |
7404 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7405 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7406 | case 0x0f67: /* packuswb */ |
7407 | case 0x0f68: /* punpckhbw */ | |
7408 | case 0x0f69: /* punpckhwd */ | |
7409 | case 0x0f6a: /* punpckhdq */ | |
7410 | case 0x0f6b: /* packssdw */ | |
7411 | case 0x0f6e: /* movd */ | |
7412 | case 0x0f6f: /* movq */ | |
7413 | case 0x0f70: /* pshufw */ | |
7414 | case 0x0f74: /* pcmpeqb */ | |
7415 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7416 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7417 | case 0x0fc4: /* pinsrw */ |
7418 | case 0x0fd1: /* psrlw */ | |
7419 | case 0x0fd2: /* psrld */ | |
7420 | case 0x0fd3: /* psrlq */ | |
7421 | case 0x0fd4: /* paddq */ | |
7422 | case 0x0fd5: /* pmullw */ | |
7423 | case 0xf20fd6: /* movdq2q */ | |
7424 | case 0x0fd8: /* psubusb */ | |
7425 | case 0x0fd9: /* psubusw */ | |
7426 | case 0x0fda: /* pminub */ | |
7427 | case 0x0fdb: /* pand */ | |
7428 | case 0x0fdc: /* paddusb */ | |
7429 | case 0x0fdd: /* paddusw */ | |
7430 | case 0x0fde: /* pmaxub */ | |
7431 | case 0x0fdf: /* pandn */ | |
7432 | case 0x0fe0: /* pavgb */ | |
7433 | case 0x0fe1: /* psraw */ | |
7434 | case 0x0fe2: /* psrad */ | |
7435 | case 0x0fe3: /* pavgw */ | |
7436 | case 0x0fe4: /* pmulhuw */ | |
7437 | case 0x0fe5: /* pmulhw */ | |
7438 | case 0x0fe8: /* psubsb */ | |
7439 | case 0x0fe9: /* psubsw */ | |
7440 | case 0x0fea: /* pminsw */ | |
7441 | case 0x0feb: /* por */ | |
7442 | case 0x0fec: /* paddsb */ | |
7443 | case 0x0fed: /* paddsw */ | |
7444 | case 0x0fee: /* pmaxsw */ | |
7445 | case 0x0fef: /* pxor */ | |
7446 | case 0x0ff1: /* psllw */ | |
7447 | case 0x0ff2: /* pslld */ | |
7448 | case 0x0ff3: /* psllq */ | |
7449 | case 0x0ff4: /* pmuludq */ | |
7450 | case 0x0ff5: /* pmaddwd */ | |
7451 | case 0x0ff6: /* psadbw */ | |
7452 | case 0x0ff8: /* psubb */ | |
7453 | case 0x0ff9: /* psubw */ | |
56d2815c | 7454 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7455 | case 0x0ffb: /* psubq */ |
7456 | case 0x0ffc: /* paddb */ | |
7457 | case 0x0ffd: /* paddw */ | |
56d2815c | 7458 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7459 | if (i386_record_modrm (&ir)) |
7460 | return -1; | |
7461 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7462 | goto no_support; | |
25ea693b MM |
7463 | record_full_arch_list_add_reg (ir.regcache, |
7464 | I387_MM0_REGNUM (tdep) + ir.reg); | |
a3c4230a HZ |
7465 | break; |
7466 | ||
7467 | case 0x0f71: /* psllw */ | |
7468 | case 0x0f72: /* pslld */ | |
7469 | case 0x0f73: /* psllq */ | |
7470 | if (i386_record_modrm (&ir)) | |
7471 | return -1; | |
7472 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7473 | goto no_support; | |
25ea693b MM |
7474 | record_full_arch_list_add_reg (ir.regcache, |
7475 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7476 | break; |
7477 | ||
7478 | case 0x660f71: /* psllw */ | |
7479 | case 0x660f72: /* pslld */ | |
7480 | case 0x660f73: /* psllq */ | |
7481 | if (i386_record_modrm (&ir)) | |
7482 | return -1; | |
7483 | ir.rm |= ir.rex_b; | |
c131fcee | 7484 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a | 7485 | goto no_support; |
25ea693b MM |
7486 | record_full_arch_list_add_reg (ir.regcache, |
7487 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7488 | break; |
7489 | ||
7490 | case 0x0f7e: /* movd */ | |
7491 | case 0x660f7e: /* movd */ | |
7492 | if (i386_record_modrm (&ir)) | |
7493 | return -1; | |
7494 | if (ir.mod == 3) | |
25ea693b | 7495 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
a3c4230a HZ |
7496 | else |
7497 | { | |
7498 | if (ir.dflag == 2) | |
7499 | ir.ot = OT_QUAD; | |
7500 | else | |
7501 | ir.ot = OT_LONG; | |
7502 | if (i386_record_lea_modrm (&ir)) | |
7503 | return -1; | |
7504 | } | |
7505 | break; | |
7506 | ||
7507 | case 0x0f7f: /* movq */ | |
7508 | if (i386_record_modrm (&ir)) | |
7509 | return -1; | |
7510 | if (ir.mod == 3) | |
7511 | { | |
7512 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7513 | goto no_support; | |
25ea693b MM |
7514 | record_full_arch_list_add_reg (ir.regcache, |
7515 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7516 | } |
7517 | else | |
7518 | { | |
7519 | ir.ot = OT_QUAD; | |
7520 | if (i386_record_lea_modrm (&ir)) | |
7521 | return -1; | |
7522 | } | |
7523 | break; | |
7524 | ||
7525 | case 0xf30fb8: /* popcnt */ | |
7526 | if (i386_record_modrm (&ir)) | |
7527 | return -1; | |
25ea693b MM |
7528 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7529 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
a3c4230a HZ |
7530 | break; |
7531 | ||
7532 | case 0x660fd6: /* movq */ | |
7533 | if (i386_record_modrm (&ir)) | |
7534 | return -1; | |
7535 | if (ir.mod == 3) | |
7536 | { | |
7537 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7538 | if (!i386_xmm_regnum_p (gdbarch, |
7539 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7540 | goto no_support; |
25ea693b MM |
7541 | record_full_arch_list_add_reg (ir.regcache, |
7542 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7543 | } |
7544 | else | |
7545 | { | |
7546 | ir.ot = OT_QUAD; | |
7547 | if (i386_record_lea_modrm (&ir)) | |
7548 | return -1; | |
7549 | } | |
7550 | break; | |
7551 | ||
7552 | case 0x660f3817: /* ptest */ | |
7553 | case 0x0f2e: /* ucomiss */ | |
7554 | case 0x660f2e: /* ucomisd */ | |
7555 | case 0x0f2f: /* comiss */ | |
7556 | case 0x660f2f: /* comisd */ | |
25ea693b | 7557 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7558 | break; |
7559 | ||
7560 | case 0x0ff7: /* maskmovq */ | |
7561 | regcache_raw_read_unsigned (ir.regcache, | |
7562 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7563 | &addr); | |
25ea693b | 7564 | if (record_full_arch_list_add_mem (addr, 64)) |
a3c4230a HZ |
7565 | return -1; |
7566 | break; | |
7567 | ||
7568 | case 0x660ff7: /* maskmovdqu */ | |
7569 | regcache_raw_read_unsigned (ir.regcache, | |
7570 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7571 | &addr); | |
25ea693b | 7572 | if (record_full_arch_list_add_mem (addr, 128)) |
a3c4230a HZ |
7573 | return -1; |
7574 | break; | |
7575 | ||
7576 | default: | |
7577 | goto no_support; | |
7578 | break; | |
7579 | } | |
7580 | break; | |
7ad10968 HZ |
7581 | |
7582 | default: | |
7ad10968 HZ |
7583 | goto no_support; |
7584 | break; | |
7585 | } | |
7586 | ||
cf648174 | 7587 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
7588 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
7589 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
7590 | return -1; |
7591 | ||
7592 | return 0; | |
7593 | ||
01fe1b41 | 7594 | no_support: |
a3c4230a HZ |
7595 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
7596 | "at address %s.\n"), | |
7597 | (unsigned int) (opcode), | |
7598 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
7599 | return -1; |
7600 | } | |
7601 | ||
cf648174 HZ |
7602 | static const int i386_record_regmap[] = |
7603 | { | |
7604 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
7605 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
7606 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7607 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
7608 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
7609 | }; | |
7610 | ||
7a697b8d | 7611 | /* Check that the given address appears suitable for a fast |
405f8e94 | 7612 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
7613 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
7614 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
7615 | middle of the tracepoint jump. On x86, it may be possible to use |
7616 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
7617 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
7618 | of instruction to replace, and 0 if not, plus an explanatory |
7619 | string. */ | |
7620 | ||
7621 | static int | |
7622 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
7623 | CORE_ADDR addr, int *isize, char **msg) | |
7624 | { | |
7625 | int len, jumplen; | |
7626 | static struct ui_file *gdb_null = NULL; | |
7627 | ||
405f8e94 SS |
7628 | /* Ask the target for the minimum instruction length supported. */ |
7629 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
7630 | ||
7631 | if (jumplen < 0) | |
7632 | { | |
7633 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
7634 | operation, assume that fast tracepoints will always be implemented | |
7635 | using 4-byte relative jumps on both x86 and x86-64. */ | |
7636 | jumplen = 5; | |
7637 | } | |
7638 | else if (jumplen == 0) | |
7639 | { | |
7640 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
7641 | returns zero, then the IPA has not loaded yet. In this case, | |
7642 | we optimistically assume that truncated 2-byte relative jumps | |
7643 | will be available on x86, and compensate later if this assumption | |
7644 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
7645 | jumps will always be used. */ | |
7646 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
7647 | } | |
7a697b8d SS |
7648 | |
7649 | /* Dummy file descriptor for the disassembler. */ | |
7650 | if (!gdb_null) | |
7651 | gdb_null = ui_file_new (); | |
7652 | ||
7653 | /* Check for fit. */ | |
7654 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
405f8e94 SS |
7655 | if (isize) |
7656 | *isize = len; | |
7657 | ||
7a697b8d SS |
7658 | if (len < jumplen) |
7659 | { | |
7660 | /* Return a bit of target-specific detail to add to the caller's | |
7661 | generic failure message. */ | |
7662 | if (msg) | |
1777feb0 MS |
7663 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
7664 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
7665 | len, jumplen); |
7666 | return 0; | |
7667 | } | |
405f8e94 SS |
7668 | else |
7669 | { | |
7670 | if (msg) | |
7671 | *msg = NULL; | |
7672 | return 1; | |
7673 | } | |
7a697b8d SS |
7674 | } |
7675 | ||
90884b2b L |
7676 | static int |
7677 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
7678 | struct tdesc_arch_data *tdesc_data) | |
7679 | { | |
7680 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 7681 | const struct tdesc_feature *feature_core; |
1dbcd68c | 7682 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx; |
90884b2b L |
7683 | int i, num_regs, valid_p; |
7684 | ||
7685 | if (! tdesc_has_registers (tdesc)) | |
7686 | return 0; | |
7687 | ||
7688 | /* Get core registers. */ | |
7689 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
7690 | if (feature_core == NULL) |
7691 | return 0; | |
90884b2b L |
7692 | |
7693 | /* Get SSE registers. */ | |
c131fcee | 7694 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 7695 | |
c131fcee L |
7696 | /* Try AVX registers. */ |
7697 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
7698 | ||
1dbcd68c WT |
7699 | /* Try MPX registers. */ |
7700 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
7701 | ||
90884b2b L |
7702 | valid_p = 1; |
7703 | ||
c131fcee L |
7704 | /* The XCR0 bits. */ |
7705 | if (feature_avx) | |
7706 | { | |
3a13a53b L |
7707 | /* AVX register description requires SSE register description. */ |
7708 | if (!feature_sse) | |
7709 | return 0; | |
7710 | ||
c131fcee L |
7711 | tdep->xcr0 = I386_XSTATE_AVX_MASK; |
7712 | ||
7713 | /* It may have been set by OSABI initialization function. */ | |
7714 | if (tdep->num_ymm_regs == 0) | |
7715 | { | |
7716 | tdep->ymmh_register_names = i386_ymmh_names; | |
7717 | tdep->num_ymm_regs = 8; | |
7718 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
7719 | } | |
7720 | ||
7721 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
7722 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
7723 | tdep->ymm0h_regnum + i, | |
7724 | tdep->ymmh_register_names[i]); | |
7725 | } | |
3a13a53b | 7726 | else if (feature_sse) |
c131fcee | 7727 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
3a13a53b L |
7728 | else |
7729 | { | |
7730 | tdep->xcr0 = I386_XSTATE_X87_MASK; | |
7731 | tdep->num_xmm_regs = 0; | |
7732 | } | |
c131fcee | 7733 | |
90884b2b L |
7734 | num_regs = tdep->num_core_regs; |
7735 | for (i = 0; i < num_regs; i++) | |
7736 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
7737 | tdep->register_names[i]); | |
7738 | ||
3a13a53b L |
7739 | if (feature_sse) |
7740 | { | |
7741 | /* Need to include %mxcsr, so add one. */ | |
7742 | num_regs += tdep->num_xmm_regs + 1; | |
7743 | for (; i < num_regs; i++) | |
7744 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
7745 | tdep->register_names[i]); | |
7746 | } | |
90884b2b | 7747 | |
1dbcd68c WT |
7748 | if (feature_mpx) |
7749 | { | |
7750 | tdep->xcr0 = I386_XSTATE_MPX_MASK; | |
7751 | ||
7752 | if (tdep->bnd0r_regnum < 0) | |
7753 | { | |
7754 | tdep->mpx_register_names = i386_mpx_names; | |
7755 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
7756 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
7757 | } | |
7758 | ||
7759 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
7760 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
7761 | I387_BND0R_REGNUM (tdep) + i, | |
7762 | tdep->mpx_register_names[i]); | |
7763 | } | |
7764 | ||
90884b2b L |
7765 | return valid_p; |
7766 | } | |
7767 | ||
7ad10968 HZ |
7768 | \f |
7769 | static struct gdbarch * | |
7770 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
7771 | { | |
7772 | struct gdbarch_tdep *tdep; | |
7773 | struct gdbarch *gdbarch; | |
90884b2b L |
7774 | struct tdesc_arch_data *tdesc_data; |
7775 | const struct target_desc *tdesc; | |
1ba53b71 | 7776 | int mm0_regnum; |
c131fcee | 7777 | int ymm0_regnum; |
1dbcd68c WT |
7778 | int bnd0_regnum; |
7779 | int num_bnd_cooked; | |
7ad10968 HZ |
7780 | |
7781 | /* If there is already a candidate, use it. */ | |
7782 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
7783 | if (arches != NULL) | |
7784 | return arches->gdbarch; | |
7785 | ||
7786 | /* Allocate space for the new architecture. */ | |
7787 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
7788 | gdbarch = gdbarch_alloc (&info, tdep); | |
7789 | ||
7790 | /* General-purpose registers. */ | |
7791 | tdep->gregset = NULL; | |
7792 | tdep->gregset_reg_offset = NULL; | |
7793 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
7794 | tdep->sizeof_gregset = 0; | |
7795 | ||
7796 | /* Floating-point registers. */ | |
7797 | tdep->fpregset = NULL; | |
7798 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
7799 | ||
c131fcee L |
7800 | tdep->xstateregset = NULL; |
7801 | ||
7ad10968 HZ |
7802 | /* The default settings include the FPU registers, the MMX registers |
7803 | and the SSE registers. This can be overridden for a specific ABI | |
7804 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
7805 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 7806 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
7807 | |
7808 | tdep->st0_regnum = I386_ST0_REGNUM; | |
7809 | ||
7ad10968 HZ |
7810 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
7811 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
7812 | ||
7813 | tdep->jb_pc_offset = -1; | |
7814 | tdep->struct_return = pcc_struct_return; | |
7815 | tdep->sigtramp_start = 0; | |
7816 | tdep->sigtramp_end = 0; | |
7817 | tdep->sigtramp_p = i386_sigtramp_p; | |
7818 | tdep->sigcontext_addr = NULL; | |
7819 | tdep->sc_reg_offset = NULL; | |
7820 | tdep->sc_pc_offset = -1; | |
7821 | tdep->sc_sp_offset = -1; | |
7822 | ||
c131fcee L |
7823 | tdep->xsave_xcr0_offset = -1; |
7824 | ||
cf648174 HZ |
7825 | tdep->record_regmap = i386_record_regmap; |
7826 | ||
205c306f DM |
7827 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
7828 | ||
7ad10968 HZ |
7829 | /* The format used for `long double' on almost all i386 targets is |
7830 | the i387 extended floating-point format. In fact, of all targets | |
7831 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
7832 | on having a `long double' that's not `long' at all. */ | |
7833 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
7834 | ||
7835 | /* Although the i387 extended floating-point has only 80 significant | |
7836 | bits, a `long double' actually takes up 96, probably to enforce | |
7837 | alignment. */ | |
7838 | set_gdbarch_long_double_bit (gdbarch, 96); | |
7839 | ||
7ad10968 HZ |
7840 | /* Register numbers of various important registers. */ |
7841 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
7842 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
7843 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
7844 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
7845 | ||
7846 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
7847 | numbering schemes on the i386: dbx and SVR4. These schemes | |
7848 | differ in how they number %ebp, %esp, %eflags, and the | |
7849 | floating-point registers, and are implemented by the arrays | |
7850 | dbx_register_map[] and svr4_dbx_register_map in | |
7851 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
7852 | gcc/config/i386.c, which it designates as the "default" register | |
7853 | map used in 64bit mode. This last register numbering scheme is | |
7854 | implemented in dbx64_register_map, and is used for AMD64; see | |
7855 | amd64-tdep.c. | |
7856 | ||
7857 | Currently, each GCC i386 target always uses the same register | |
7858 | numbering scheme across all its supported debugging formats | |
7859 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
7860 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
7861 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
7862 | respective config header in a manner independent of the requested | |
7863 | output debugging format. | |
7864 | ||
7865 | This does not match the arrangement below, which presumes that | |
7866 | the SDB and stabs numbering schemes differ from the DWARF and | |
7867 | DWARF 2 ones. The reason for this arrangement is that it is | |
7868 | likely to get the numbering scheme for the target's | |
7869 | default/native debug format right. For targets where GCC is the | |
7870 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
7871 | targets where the native toolchain uses a different numbering | |
7872 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
7873 | the defaults below will have to be overridden, like | |
7874 | i386_elf_init_abi() does. */ | |
7875 | ||
7876 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
7877 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7878 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7879 | ||
7880 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
7881 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
7882 | ||
7883 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
7884 | be in use on any of the supported i386 targets. */ | |
7885 | ||
7886 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
7887 | ||
7888 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
7889 | ||
7890 | /* Call dummy code. */ | |
a9b8d892 JK |
7891 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
7892 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 7893 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 7894 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
7895 | |
7896 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
7897 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
7898 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
7899 | ||
7900 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
7901 | ||
7902 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
7903 | ||
7904 | /* Stack grows downward. */ | |
7905 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7906 | ||
7907 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
7908 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
7909 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
7910 | ||
7911 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
7912 | ||
7ad10968 HZ |
7913 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
7914 | ||
7915 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
7916 | ||
7917 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
7918 | ||
7919 | /* Add the i386 register groups. */ | |
7920 | i386_add_reggroups (gdbarch); | |
90884b2b | 7921 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 7922 | |
143985b7 AF |
7923 | /* Helper for function argument information. */ |
7924 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
7925 | ||
06da04c6 | 7926 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
7927 | appended to the list first, so that it supercedes the DWARF |
7928 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
7929 | currently fails). */ |
7930 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
7931 | ||
7932 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 7933 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 7934 | CFI info will be used if it is available. */ |
10458914 | 7935 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 7936 | |
acd5c798 | 7937 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 7938 | |
1ba53b71 | 7939 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
7940 | set_gdbarch_pseudo_register_read_value (gdbarch, |
7941 | i386_pseudo_register_read_value); | |
90884b2b L |
7942 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
7943 | ||
7944 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
7945 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
7946 | ||
c131fcee L |
7947 | /* Override the normal target description method to make the AVX |
7948 | upper halves anonymous. */ | |
7949 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
7950 | ||
7951 | /* Even though the default ABI only includes general-purpose registers, | |
7952 | floating-point registers and the SSE registers, we have to leave a | |
1dbcd68c WT |
7953 | gap for the upper AVX registers and the MPX registers. */ |
7954 | set_gdbarch_num_regs (gdbarch, I386_MPX_NUM_REGS); | |
90884b2b L |
7955 | |
7956 | /* Get the x86 target description from INFO. */ | |
7957 | tdesc = info.target_desc; | |
7958 | if (! tdesc_has_registers (tdesc)) | |
7959 | tdesc = tdesc_i386; | |
7960 | tdep->tdesc = tdesc; | |
7961 | ||
7962 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
7963 | tdep->register_names = i386_register_names; | |
7964 | ||
c131fcee L |
7965 | /* No upper YMM registers. */ |
7966 | tdep->ymmh_register_names = NULL; | |
7967 | tdep->ymm0h_regnum = -1; | |
7968 | ||
1ba53b71 L |
7969 | tdep->num_byte_regs = 8; |
7970 | tdep->num_word_regs = 8; | |
7971 | tdep->num_dword_regs = 0; | |
7972 | tdep->num_mmx_regs = 8; | |
c131fcee | 7973 | tdep->num_ymm_regs = 0; |
1ba53b71 | 7974 | |
1dbcd68c WT |
7975 | /* No MPX registers. */ |
7976 | tdep->bnd0r_regnum = -1; | |
7977 | tdep->bndcfgu_regnum = -1; | |
7978 | ||
90884b2b L |
7979 | tdesc_data = tdesc_data_alloc (); |
7980 | ||
dde08ee1 PA |
7981 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
7982 | ||
6710bf39 SS |
7983 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
7984 | ||
3ce1502b | 7985 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 7986 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 7987 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 7988 | |
c131fcee L |
7989 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
7990 | { | |
7991 | tdesc_data_cleanup (tdesc_data); | |
7992 | xfree (tdep); | |
7993 | gdbarch_free (gdbarch); | |
7994 | return NULL; | |
7995 | } | |
7996 | ||
1dbcd68c WT |
7997 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
7998 | ||
1ba53b71 L |
7999 | /* Wire in pseudo registers. Number of pseudo registers may be |
8000 | changed. */ | |
8001 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8002 | + tdep->num_word_regs | |
8003 | + tdep->num_dword_regs | |
c131fcee | 8004 | + tdep->num_mmx_regs |
1dbcd68c WT |
8005 | + tdep->num_ymm_regs |
8006 | + num_bnd_cooked)); | |
1ba53b71 | 8007 | |
90884b2b L |
8008 | /* Target description may be changed. */ |
8009 | tdesc = tdep->tdesc; | |
8010 | ||
90884b2b L |
8011 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
8012 | ||
8013 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8014 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8015 | ||
1ba53b71 L |
8016 | /* Make %al the first pseudo-register. */ |
8017 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8018 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8019 | ||
c131fcee | 8020 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8021 | if (tdep->num_dword_regs) |
8022 | { | |
1c6272a6 | 8023 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8024 | tdep->eax_regnum = ymm0_regnum; |
8025 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8026 | } |
8027 | else | |
8028 | tdep->eax_regnum = -1; | |
8029 | ||
c131fcee L |
8030 | mm0_regnum = ymm0_regnum; |
8031 | if (tdep->num_ymm_regs) | |
8032 | { | |
1c6272a6 | 8033 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8034 | tdep->ymm0_regnum = ymm0_regnum; |
8035 | mm0_regnum += tdep->num_ymm_regs; | |
8036 | } | |
8037 | else | |
8038 | tdep->ymm0_regnum = -1; | |
8039 | ||
1dbcd68c | 8040 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8041 | if (tdep->num_mmx_regs != 0) |
8042 | { | |
1c6272a6 | 8043 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8044 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8045 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8046 | } |
8047 | else | |
8048 | tdep->mm0_regnum = -1; | |
8049 | ||
1dbcd68c WT |
8050 | if (tdep->bnd0r_regnum > 0) |
8051 | tdep->bnd0_regnum = bnd0_regnum; | |
8052 | else | |
8053 | tdep-> bnd0_regnum = -1; | |
8054 | ||
06da04c6 | 8055 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 8056 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
8057 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
8058 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 8059 | |
8446b36a MK |
8060 | /* If we have a register mapping, enable the generic core file |
8061 | support, unless it has already been enabled. */ | |
8062 | if (tdep->gregset_reg_offset | |
8063 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
8064 | set_gdbarch_regset_from_core_section (gdbarch, | |
8065 | i386_regset_from_core_section); | |
8066 | ||
514f746b AR |
8067 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
8068 | i386_skip_permanent_breakpoint); | |
8069 | ||
7a697b8d SS |
8070 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8071 | i386_fast_tracepoint_valid_at); | |
8072 | ||
a62cc96e AC |
8073 | return gdbarch; |
8074 | } | |
8075 | ||
8201327c MK |
8076 | static enum gdb_osabi |
8077 | i386_coff_osabi_sniffer (bfd *abfd) | |
8078 | { | |
762c5349 MK |
8079 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
8080 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
8081 | return GDB_OSABI_GO32; |
8082 | ||
8083 | return GDB_OSABI_UNKNOWN; | |
8084 | } | |
8201327c MK |
8085 | \f |
8086 | ||
28e9e0f0 MK |
8087 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
8088 | void _initialize_i386_tdep (void); | |
8089 | ||
c906108c | 8090 | void |
fba45db2 | 8091 | _initialize_i386_tdep (void) |
c906108c | 8092 | { |
a62cc96e AC |
8093 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
8094 | ||
fc338970 | 8095 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
8096 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
8097 | &disassembly_flavor, _("\ | |
8098 | Set the disassembly flavor."), _("\ | |
8099 | Show the disassembly flavor."), _("\ | |
8100 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
8101 | NULL, | |
8102 | NULL, /* FIXME: i18n: */ | |
8103 | &setlist, &showlist); | |
8201327c MK |
8104 | |
8105 | /* Add the variable that controls the convention for returning | |
8106 | structs. */ | |
7ab04401 AC |
8107 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
8108 | &struct_convention, _("\ | |
8109 | Set the convention for returning small structs."), _("\ | |
8110 | Show the convention for returning small structs."), _("\ | |
8111 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
8112 | is \"default\"."), | |
8113 | NULL, | |
8114 | NULL, /* FIXME: i18n: */ | |
8115 | &setlist, &showlist); | |
8201327c MK |
8116 | |
8117 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
8118 | i386_coff_osabi_sniffer); | |
8201327c | 8119 | |
05816f70 | 8120 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 8121 | i386_svr4_init_abi); |
05816f70 | 8122 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 8123 | i386_go32_init_abi); |
38c968cf | 8124 | |
209bd28e | 8125 | /* Initialize the i386-specific register groups. */ |
38c968cf | 8126 | i386_init_reggroups (); |
90884b2b L |
8127 | |
8128 | /* Initialize the standard target descriptions. */ | |
8129 | initialize_tdesc_i386 (); | |
3a13a53b | 8130 | initialize_tdesc_i386_mmx (); |
c131fcee | 8131 | initialize_tdesc_i386_avx (); |
1dbcd68c | 8132 | initialize_tdesc_i386_mpx (); |
c8d5aac9 L |
8133 | |
8134 | /* Tell remote stub that we support XML target description. */ | |
8135 | register_remote_support_xml ("i386"); | |
c906108c | 8136 | } |