Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 JB |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
5 | 2010 Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
7a697b8d | 46 | #include "disasm.h" |
acd5c798 | 47 | |
3d261580 | 48 | #include "gdb_assert.h" |
acd5c798 | 49 | #include "gdb_string.h" |
3d261580 | 50 | |
d2a7c97a | 51 | #include "i386-tdep.h" |
61113f8b | 52 | #include "i387-tdep.h" |
d2a7c97a | 53 | |
7ad10968 HZ |
54 | #include "record.h" |
55 | #include <stdint.h> | |
56 | ||
90884b2b L |
57 | #include "features/i386/i386.c" |
58 | ||
c4fc7f1b | 59 | /* Register names. */ |
c40e1eab | 60 | |
90884b2b | 61 | static const char *i386_register_names[] = |
fc633446 MK |
62 | { |
63 | "eax", "ecx", "edx", "ebx", | |
64 | "esp", "ebp", "esi", "edi", | |
65 | "eip", "eflags", "cs", "ss", | |
66 | "ds", "es", "fs", "gs", | |
67 | "st0", "st1", "st2", "st3", | |
68 | "st4", "st5", "st6", "st7", | |
69 | "fctrl", "fstat", "ftag", "fiseg", | |
70 | "fioff", "foseg", "fooff", "fop", | |
71 | "xmm0", "xmm1", "xmm2", "xmm3", | |
72 | "xmm4", "xmm5", "xmm6", "xmm7", | |
73 | "mxcsr" | |
74 | }; | |
75 | ||
c4fc7f1b | 76 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 77 | |
90884b2b | 78 | static const char *i386_mmx_names[] = |
28fc6740 AC |
79 | { |
80 | "mm0", "mm1", "mm2", "mm3", | |
81 | "mm4", "mm5", "mm6", "mm7" | |
82 | }; | |
c40e1eab | 83 | |
1cb97e17 | 84 | static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names); |
c40e1eab | 85 | |
28fc6740 | 86 | static int |
5716833c | 87 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 88 | { |
5716833c MK |
89 | int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum; |
90 | ||
91 | if (mm0_regnum < 0) | |
92 | return 0; | |
93 | ||
94 | return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs); | |
28fc6740 AC |
95 | } |
96 | ||
5716833c | 97 | /* SSE register? */ |
23a34459 | 98 | |
5716833c MK |
99 | static int |
100 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 101 | { |
5716833c MK |
102 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
103 | ||
20a6ec49 | 104 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
105 | return 0; |
106 | ||
20a6ec49 MD |
107 | return (I387_XMM0_REGNUM (tdep) <= regnum |
108 | && regnum < I387_MXCSR_REGNUM (tdep)); | |
23a34459 AC |
109 | } |
110 | ||
5716833c MK |
111 | static int |
112 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 113 | { |
5716833c MK |
114 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
115 | ||
20a6ec49 | 116 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
117 | return 0; |
118 | ||
20a6ec49 | 119 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
120 | } |
121 | ||
5716833c | 122 | /* FP register? */ |
23a34459 AC |
123 | |
124 | int | |
20a6ec49 | 125 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 126 | { |
20a6ec49 MD |
127 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
128 | ||
129 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
130 | return 0; |
131 | ||
20a6ec49 MD |
132 | return (I387_ST0_REGNUM (tdep) <= regnum |
133 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
134 | } |
135 | ||
136 | int | |
20a6ec49 | 137 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 138 | { |
20a6ec49 MD |
139 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
140 | ||
141 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
142 | return 0; |
143 | ||
20a6ec49 MD |
144 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
145 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
146 | } |
147 | ||
30b0e2d8 | 148 | /* Return the name of register REGNUM. */ |
fc633446 | 149 | |
90884b2b L |
150 | static const char * |
151 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
fc633446 | 152 | { |
90884b2b L |
153 | gdb_assert (i386_mmx_regnum_p (gdbarch, regnum)); |
154 | return i386_mmx_names[regnum - I387_MM0_REGNUM (gdbarch_tdep (gdbarch))]; | |
fc633446 MK |
155 | } |
156 | ||
c4fc7f1b | 157 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
158 | number used by GDB. */ |
159 | ||
8201327c | 160 | static int |
d3f73121 | 161 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 162 | { |
20a6ec49 MD |
163 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
164 | ||
c4fc7f1b MK |
165 | /* This implements what GCC calls the "default" register map |
166 | (dbx_register_map[]). */ | |
167 | ||
85540d8c MK |
168 | if (reg >= 0 && reg <= 7) |
169 | { | |
9872ad24 JB |
170 | /* General-purpose registers. The debug info calls %ebp |
171 | register 4, and %esp register 5. */ | |
172 | if (reg == 4) | |
173 | return 5; | |
174 | else if (reg == 5) | |
175 | return 4; | |
176 | else return reg; | |
85540d8c MK |
177 | } |
178 | else if (reg >= 12 && reg <= 19) | |
179 | { | |
180 | /* Floating-point registers. */ | |
20a6ec49 | 181 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
182 | } |
183 | else if (reg >= 21 && reg <= 28) | |
184 | { | |
185 | /* SSE registers. */ | |
20a6ec49 | 186 | return reg - 21 + I387_XMM0_REGNUM (tdep); |
85540d8c MK |
187 | } |
188 | else if (reg >= 29 && reg <= 36) | |
189 | { | |
190 | /* MMX registers. */ | |
20a6ec49 | 191 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
192 | } |
193 | ||
194 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 195 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
196 | } |
197 | ||
c4fc7f1b MK |
198 | /* Convert SVR4 register number REG to the appropriate register number |
199 | used by GDB. */ | |
85540d8c | 200 | |
8201327c | 201 | static int |
d3f73121 | 202 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 203 | { |
20a6ec49 MD |
204 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
205 | ||
c4fc7f1b MK |
206 | /* This implements the GCC register map that tries to be compatible |
207 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
208 | ||
209 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
210 | numbers the floating point registers differently. */ |
211 | if (reg >= 0 && reg <= 9) | |
212 | { | |
acd5c798 | 213 | /* General-purpose registers. */ |
85540d8c MK |
214 | return reg; |
215 | } | |
216 | else if (reg >= 11 && reg <= 18) | |
217 | { | |
218 | /* Floating-point registers. */ | |
20a6ec49 | 219 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 220 | } |
c6f4c129 | 221 | else if (reg >= 21 && reg <= 36) |
85540d8c | 222 | { |
c4fc7f1b | 223 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 224 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
225 | } |
226 | ||
c6f4c129 JB |
227 | switch (reg) |
228 | { | |
20a6ec49 MD |
229 | case 37: return I387_FCTRL_REGNUM (tdep); |
230 | case 38: return I387_FSTAT_REGNUM (tdep); | |
231 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
232 | case 40: return I386_ES_REGNUM; |
233 | case 41: return I386_CS_REGNUM; | |
234 | case 42: return I386_SS_REGNUM; | |
235 | case 43: return I386_DS_REGNUM; | |
236 | case 44: return I386_FS_REGNUM; | |
237 | case 45: return I386_GS_REGNUM; | |
238 | } | |
239 | ||
85540d8c | 240 | /* This will hopefully provoke a warning. */ |
d3f73121 | 241 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 242 | } |
5716833c | 243 | |
fc338970 | 244 | \f |
917317f4 | 245 | |
fc338970 MK |
246 | /* This is the variable that is set with "set disassembly-flavor", and |
247 | its legitimate values. */ | |
53904c9e AC |
248 | static const char att_flavor[] = "att"; |
249 | static const char intel_flavor[] = "intel"; | |
250 | static const char *valid_flavors[] = | |
c5aa993b | 251 | { |
c906108c SS |
252 | att_flavor, |
253 | intel_flavor, | |
254 | NULL | |
255 | }; | |
53904c9e | 256 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 257 | \f |
c906108c | 258 | |
acd5c798 MK |
259 | /* Use the program counter to determine the contents and size of a |
260 | breakpoint instruction. Return a pointer to a string of bytes that | |
261 | encode a breakpoint instruction, store the length of the string in | |
262 | *LEN and optionally adjust *PC to point to the correct memory | |
263 | location for inserting the breakpoint. | |
c906108c | 264 | |
acd5c798 MK |
265 | On the i386 we have a single breakpoint that fits in a single byte |
266 | and can be inserted anywhere. | |
c906108c | 267 | |
acd5c798 | 268 | This function is 64-bit safe. */ |
63c0089f MK |
269 | |
270 | static const gdb_byte * | |
67d57894 | 271 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 272 | { |
63c0089f MK |
273 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
274 | ||
acd5c798 MK |
275 | *len = sizeof (break_insn); |
276 | return break_insn; | |
c906108c | 277 | } |
237fc4c9 PA |
278 | \f |
279 | /* Displaced instruction handling. */ | |
280 | ||
1903f0e6 DE |
281 | /* Skip the legacy instruction prefixes in INSN. |
282 | Not all prefixes are valid for any particular insn | |
283 | but we needn't care, the insn will fault if it's invalid. | |
284 | The result is a pointer to the first opcode byte, | |
285 | or NULL if we run off the end of the buffer. */ | |
286 | ||
287 | static gdb_byte * | |
288 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
289 | { | |
290 | gdb_byte *end = insn + max_len; | |
291 | ||
292 | while (insn < end) | |
293 | { | |
294 | switch (*insn) | |
295 | { | |
296 | case DATA_PREFIX_OPCODE: | |
297 | case ADDR_PREFIX_OPCODE: | |
298 | case CS_PREFIX_OPCODE: | |
299 | case DS_PREFIX_OPCODE: | |
300 | case ES_PREFIX_OPCODE: | |
301 | case FS_PREFIX_OPCODE: | |
302 | case GS_PREFIX_OPCODE: | |
303 | case SS_PREFIX_OPCODE: | |
304 | case LOCK_PREFIX_OPCODE: | |
305 | case REPE_PREFIX_OPCODE: | |
306 | case REPNE_PREFIX_OPCODE: | |
307 | ++insn; | |
308 | continue; | |
309 | default: | |
310 | return insn; | |
311 | } | |
312 | } | |
313 | ||
314 | return NULL; | |
315 | } | |
237fc4c9 PA |
316 | |
317 | static int | |
1903f0e6 | 318 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 PA |
319 | { |
320 | /* jmp far (absolute address in operand) */ | |
321 | if (insn[0] == 0xea) | |
322 | return 1; | |
323 | ||
324 | if (insn[0] == 0xff) | |
325 | { | |
326 | /* jump near, absolute indirect (/4) */ | |
327 | if ((insn[1] & 0x38) == 0x20) | |
328 | return 1; | |
329 | ||
330 | /* jump far, absolute indirect (/5) */ | |
331 | if ((insn[1] & 0x38) == 0x28) | |
332 | return 1; | |
333 | } | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | static int | |
1903f0e6 | 339 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 PA |
340 | { |
341 | /* call far, absolute */ | |
342 | if (insn[0] == 0x9a) | |
343 | return 1; | |
344 | ||
345 | if (insn[0] == 0xff) | |
346 | { | |
347 | /* Call near, absolute indirect (/2) */ | |
348 | if ((insn[1] & 0x38) == 0x10) | |
349 | return 1; | |
350 | ||
351 | /* Call far, absolute indirect (/3) */ | |
352 | if ((insn[1] & 0x38) == 0x18) | |
353 | return 1; | |
354 | } | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | static int | |
1903f0e6 | 360 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
361 | { |
362 | switch (insn[0]) | |
363 | { | |
364 | case 0xc2: /* ret near, pop N bytes */ | |
365 | case 0xc3: /* ret near */ | |
366 | case 0xca: /* ret far, pop N bytes */ | |
367 | case 0xcb: /* ret far */ | |
368 | case 0xcf: /* iret */ | |
369 | return 1; | |
370 | ||
371 | default: | |
372 | return 0; | |
373 | } | |
374 | } | |
375 | ||
376 | static int | |
1903f0e6 | 377 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
378 | { |
379 | if (i386_absolute_call_p (insn)) | |
380 | return 1; | |
381 | ||
382 | /* call near, relative */ | |
383 | if (insn[0] == 0xe8) | |
384 | return 1; | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
237fc4c9 PA |
389 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
390 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 391 | |
237fc4c9 | 392 | static int |
1903f0e6 | 393 | i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp) |
237fc4c9 PA |
394 | { |
395 | if (insn[0] == 0xcd) | |
396 | { | |
397 | *lengthp = 2; | |
398 | return 1; | |
399 | } | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
404 | /* Fix up the state of registers and memory after having single-stepped | |
405 | a displaced instruction. */ | |
1903f0e6 | 406 | |
237fc4c9 PA |
407 | void |
408 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
409 | struct displaced_step_closure *closure, | |
410 | CORE_ADDR from, CORE_ADDR to, | |
411 | struct regcache *regs) | |
412 | { | |
e17a4113 UW |
413 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
414 | ||
237fc4c9 PA |
415 | /* The offset we applied to the instruction's address. |
416 | This could well be negative (when viewed as a signed 32-bit | |
417 | value), but ULONGEST won't reflect that, so take care when | |
418 | applying it. */ | |
419 | ULONGEST insn_offset = to - from; | |
420 | ||
421 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
422 | copy of the instruction. */ | |
423 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
424 | /* The start of the insn, needed in case we see some prefixes. */ |
425 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
426 | |
427 | if (debug_displaced) | |
428 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 429 | "displaced: fixup (%s, %s), " |
237fc4c9 | 430 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
431 | paddress (gdbarch, from), paddress (gdbarch, to), |
432 | insn[0], insn[1]); | |
237fc4c9 PA |
433 | |
434 | /* The list of issues to contend with here is taken from | |
435 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
436 | Yay for Free Software! */ | |
437 | ||
438 | /* Relocate the %eip, if necessary. */ | |
439 | ||
1903f0e6 DE |
440 | /* The instruction recognizers we use assume any leading prefixes |
441 | have been skipped. */ | |
442 | { | |
443 | /* This is the size of the buffer in closure. */ | |
444 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
445 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
446 | /* If there are too many prefixes, just ignore the insn. | |
447 | It will fault when run. */ | |
448 | if (opcode != NULL) | |
449 | insn = opcode; | |
450 | } | |
451 | ||
237fc4c9 PA |
452 | /* Except in the case of absolute or indirect jump or call |
453 | instructions, or a return instruction, the new eip is relative to | |
454 | the displaced instruction; make it relative. Well, signal | |
455 | handler returns don't need relocation either, but we use the | |
456 | value of %eip to recognize those; see below. */ | |
457 | if (! i386_absolute_jmp_p (insn) | |
458 | && ! i386_absolute_call_p (insn) | |
459 | && ! i386_ret_p (insn)) | |
460 | { | |
461 | ULONGEST orig_eip; | |
462 | ULONGEST insn_len; | |
463 | ||
464 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
465 | ||
466 | /* A signal trampoline system call changes the %eip, resuming | |
467 | execution of the main program after the signal handler has | |
468 | returned. That makes them like 'return' instructions; we | |
469 | shouldn't relocate %eip. | |
470 | ||
471 | But most system calls don't, and we do need to relocate %eip. | |
472 | ||
473 | Our heuristic for distinguishing these cases: if stepping | |
474 | over the system call instruction left control directly after | |
475 | the instruction, the we relocate --- control almost certainly | |
476 | doesn't belong in the displaced copy. Otherwise, we assume | |
477 | the instruction has put control where it belongs, and leave | |
478 | it unrelocated. Goodness help us if there are PC-relative | |
479 | system calls. */ | |
480 | if (i386_syscall_p (insn, &insn_len) | |
1903f0e6 | 481 | && orig_eip != to + (insn - insn_start) + insn_len) |
237fc4c9 PA |
482 | { |
483 | if (debug_displaced) | |
484 | fprintf_unfiltered (gdb_stdlog, | |
485 | "displaced: syscall changed %%eip; " | |
486 | "not relocating\n"); | |
487 | } | |
488 | else | |
489 | { | |
490 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
491 | ||
1903f0e6 DE |
492 | /* If we just stepped over a breakpoint insn, we don't backup |
493 | the pc on purpose; this is to match behaviour without | |
494 | stepping. */ | |
237fc4c9 PA |
495 | |
496 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
497 | ||
498 | if (debug_displaced) | |
499 | fprintf_unfiltered (gdb_stdlog, | |
500 | "displaced: " | |
5af949e3 UW |
501 | "relocated %%eip from %s to %s\n", |
502 | paddress (gdbarch, orig_eip), | |
503 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
504 | } |
505 | } | |
506 | ||
507 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
508 | pushed value, and should be cleared. We'll leave this for later, | |
509 | since GDB already messes up the TF flag when stepping over a | |
510 | pushfl. */ | |
511 | ||
512 | /* If the instruction was a call, the return address now atop the | |
513 | stack is the address following the copied instruction. We need | |
514 | to make it the address following the original instruction. */ | |
515 | if (i386_call_p (insn)) | |
516 | { | |
517 | ULONGEST esp; | |
518 | ULONGEST retaddr; | |
519 | const ULONGEST retaddr_len = 4; | |
520 | ||
521 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 522 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 523 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 524 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
525 | |
526 | if (debug_displaced) | |
527 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
528 | "displaced: relocated return addr at %s to %s\n", |
529 | paddress (gdbarch, esp), | |
530 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
531 | } |
532 | } | |
fc338970 | 533 | \f |
acd5c798 MK |
534 | #ifdef I386_REGNO_TO_SYMMETRY |
535 | #error "The Sequent Symmetry is no longer supported." | |
536 | #endif | |
c906108c | 537 | |
acd5c798 MK |
538 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
539 | and %esp "belong" to the calling function. Therefore these | |
540 | registers should be saved if they're going to be modified. */ | |
c906108c | 541 | |
acd5c798 MK |
542 | /* The maximum number of saved registers. This should include all |
543 | registers mentioned above, and %eip. */ | |
a3386186 | 544 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
545 | |
546 | struct i386_frame_cache | |
c906108c | 547 | { |
acd5c798 MK |
548 | /* Base address. */ |
549 | CORE_ADDR base; | |
772562f8 | 550 | LONGEST sp_offset; |
acd5c798 MK |
551 | CORE_ADDR pc; |
552 | ||
fd13a04a AC |
553 | /* Saved registers. */ |
554 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 555 | CORE_ADDR saved_sp; |
e0c62198 | 556 | int saved_sp_reg; |
acd5c798 MK |
557 | int pc_in_eax; |
558 | ||
559 | /* Stack space reserved for local variables. */ | |
560 | long locals; | |
561 | }; | |
562 | ||
563 | /* Allocate and initialize a frame cache. */ | |
564 | ||
565 | static struct i386_frame_cache * | |
fd13a04a | 566 | i386_alloc_frame_cache (void) |
acd5c798 MK |
567 | { |
568 | struct i386_frame_cache *cache; | |
569 | int i; | |
570 | ||
571 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
572 | ||
573 | /* Base address. */ | |
574 | cache->base = 0; | |
575 | cache->sp_offset = -4; | |
576 | cache->pc = 0; | |
577 | ||
fd13a04a AC |
578 | /* Saved registers. We initialize these to -1 since zero is a valid |
579 | offset (that's where %ebp is supposed to be stored). */ | |
580 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
581 | cache->saved_regs[i] = -1; | |
acd5c798 | 582 | cache->saved_sp = 0; |
e0c62198 | 583 | cache->saved_sp_reg = -1; |
acd5c798 MK |
584 | cache->pc_in_eax = 0; |
585 | ||
586 | /* Frameless until proven otherwise. */ | |
587 | cache->locals = -1; | |
588 | ||
589 | return cache; | |
590 | } | |
c906108c | 591 | |
acd5c798 MK |
592 | /* If the instruction at PC is a jump, return the address of its |
593 | target. Otherwise, return PC. */ | |
c906108c | 594 | |
acd5c798 | 595 | static CORE_ADDR |
e17a4113 | 596 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 597 | { |
e17a4113 | 598 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 599 | gdb_byte op; |
acd5c798 MK |
600 | long delta = 0; |
601 | int data16 = 0; | |
c906108c | 602 | |
8defab1a | 603 | target_read_memory (pc, &op, 1); |
acd5c798 | 604 | if (op == 0x66) |
c906108c | 605 | { |
c906108c | 606 | data16 = 1; |
e17a4113 | 607 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
608 | } |
609 | ||
acd5c798 | 610 | switch (op) |
c906108c SS |
611 | { |
612 | case 0xe9: | |
fc338970 | 613 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
614 | if (data16) |
615 | { | |
e17a4113 | 616 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 617 | |
fc338970 MK |
618 | /* Include the size of the jmp instruction (including the |
619 | 0x66 prefix). */ | |
acd5c798 | 620 | delta += 4; |
c906108c SS |
621 | } |
622 | else | |
623 | { | |
e17a4113 | 624 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 625 | |
acd5c798 MK |
626 | /* Include the size of the jmp instruction. */ |
627 | delta += 5; | |
c906108c SS |
628 | } |
629 | break; | |
630 | case 0xeb: | |
fc338970 | 631 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 632 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 633 | |
acd5c798 | 634 | delta += data16 + 2; |
c906108c SS |
635 | break; |
636 | } | |
c906108c | 637 | |
acd5c798 MK |
638 | return pc + delta; |
639 | } | |
fc338970 | 640 | |
acd5c798 MK |
641 | /* Check whether PC points at a prologue for a function returning a |
642 | structure or union. If so, it updates CACHE and returns the | |
643 | address of the first instruction after the code sequence that | |
644 | removes the "hidden" argument from the stack or CURRENT_PC, | |
645 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 646 | |
acd5c798 MK |
647 | static CORE_ADDR |
648 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
649 | struct i386_frame_cache *cache) | |
c906108c | 650 | { |
acd5c798 MK |
651 | /* Functions that return a structure or union start with: |
652 | ||
653 | popl %eax 0x58 | |
654 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
655 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
656 | ||
657 | (the System V compiler puts out the second `xchg' instruction, | |
658 | and the assembler doesn't try to optimize it, so the 'sib' form | |
659 | gets generated). This sequence is used to get the address of the | |
660 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
661 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
662 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
663 | gdb_byte buf[4]; | |
664 | gdb_byte op; | |
c906108c | 665 | |
acd5c798 MK |
666 | if (current_pc <= pc) |
667 | return pc; | |
668 | ||
8defab1a | 669 | target_read_memory (pc, &op, 1); |
c906108c | 670 | |
acd5c798 MK |
671 | if (op != 0x58) /* popl %eax */ |
672 | return pc; | |
c906108c | 673 | |
8defab1a | 674 | target_read_memory (pc + 1, buf, 4); |
acd5c798 MK |
675 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
676 | return pc; | |
c906108c | 677 | |
acd5c798 | 678 | if (current_pc == pc) |
c906108c | 679 | { |
acd5c798 MK |
680 | cache->sp_offset += 4; |
681 | return current_pc; | |
c906108c SS |
682 | } |
683 | ||
acd5c798 | 684 | if (current_pc == pc + 1) |
c906108c | 685 | { |
acd5c798 MK |
686 | cache->pc_in_eax = 1; |
687 | return current_pc; | |
688 | } | |
689 | ||
690 | if (buf[1] == proto1[1]) | |
691 | return pc + 4; | |
692 | else | |
693 | return pc + 5; | |
694 | } | |
695 | ||
696 | static CORE_ADDR | |
697 | i386_skip_probe (CORE_ADDR pc) | |
698 | { | |
699 | /* A function may start with | |
fc338970 | 700 | |
acd5c798 MK |
701 | pushl constant |
702 | call _probe | |
703 | addl $4, %esp | |
fc338970 | 704 | |
acd5c798 MK |
705 | followed by |
706 | ||
707 | pushl %ebp | |
fc338970 | 708 | |
acd5c798 | 709 | etc. */ |
63c0089f MK |
710 | gdb_byte buf[8]; |
711 | gdb_byte op; | |
fc338970 | 712 | |
8defab1a | 713 | target_read_memory (pc, &op, 1); |
acd5c798 MK |
714 | |
715 | if (op == 0x68 || op == 0x6a) | |
716 | { | |
717 | int delta; | |
c906108c | 718 | |
acd5c798 MK |
719 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
720 | four-byte operand, depending on the opcode. */ | |
c906108c | 721 | if (op == 0x68) |
acd5c798 | 722 | delta = 5; |
c906108c | 723 | else |
acd5c798 | 724 | delta = 2; |
c906108c | 725 | |
acd5c798 MK |
726 | /* Read the following 8 bytes, which should be `call _probe' (6 |
727 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
728 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 729 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 730 | pc += delta + sizeof (buf); |
c906108c SS |
731 | } |
732 | ||
acd5c798 MK |
733 | return pc; |
734 | } | |
735 | ||
92dd43fa MK |
736 | /* GCC 4.1 and later, can put code in the prologue to realign the |
737 | stack pointer. Check whether PC points to such code, and update | |
738 | CACHE accordingly. Return the first instruction after the code | |
739 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
740 | recognize the code, return PC. */ | |
741 | ||
742 | static CORE_ADDR | |
743 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
744 | struct i386_frame_cache *cache) | |
745 | { | |
e0c62198 L |
746 | /* There are 2 code sequences to re-align stack before the frame |
747 | gets set up: | |
748 | ||
749 | 1. Use a caller-saved saved register: | |
750 | ||
751 | leal 4(%esp), %reg | |
752 | andl $-XXX, %esp | |
753 | pushl -4(%reg) | |
754 | ||
755 | 2. Use a callee-saved saved register: | |
756 | ||
757 | pushl %reg | |
758 | leal 8(%esp), %reg | |
759 | andl $-XXX, %esp | |
760 | pushl -4(%reg) | |
761 | ||
762 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
763 | ||
764 | 0x83 0xe4 0xf0 andl $-16, %esp | |
765 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
766 | */ | |
767 | ||
768 | gdb_byte buf[14]; | |
769 | int reg; | |
770 | int offset, offset_and; | |
771 | static int regnums[8] = { | |
772 | I386_EAX_REGNUM, /* %eax */ | |
773 | I386_ECX_REGNUM, /* %ecx */ | |
774 | I386_EDX_REGNUM, /* %edx */ | |
775 | I386_EBX_REGNUM, /* %ebx */ | |
776 | I386_ESP_REGNUM, /* %esp */ | |
777 | I386_EBP_REGNUM, /* %ebp */ | |
778 | I386_ESI_REGNUM, /* %esi */ | |
779 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 780 | }; |
92dd43fa | 781 | |
e0c62198 L |
782 | if (target_read_memory (pc, buf, sizeof buf)) |
783 | return pc; | |
784 | ||
785 | /* Check caller-saved saved register. The first instruction has | |
786 | to be "leal 4(%esp), %reg". */ | |
787 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
788 | { | |
789 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
790 | if ((buf[1] & 0xc7) != 0x44) | |
791 | return pc; | |
792 | ||
793 | /* REG has register number. */ | |
794 | reg = (buf[1] >> 3) & 7; | |
795 | offset = 4; | |
796 | } | |
797 | else | |
798 | { | |
799 | /* Check callee-saved saved register. The first instruction | |
800 | has to be "pushl %reg". */ | |
801 | if ((buf[0] & 0xf8) != 0x50) | |
802 | return pc; | |
803 | ||
804 | /* Get register. */ | |
805 | reg = buf[0] & 0x7; | |
806 | ||
807 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
808 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
809 | return pc; | |
810 | ||
811 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
812 | if ((buf[2] & 0xc7) != 0x44) | |
813 | return pc; | |
814 | ||
815 | /* REG has register number. Registers in pushl and leal have to | |
816 | be the same. */ | |
817 | if (reg != ((buf[2] >> 3) & 7)) | |
818 | return pc; | |
819 | ||
820 | offset = 5; | |
821 | } | |
822 | ||
823 | /* Rigister can't be %esp nor %ebp. */ | |
824 | if (reg == 4 || reg == 5) | |
825 | return pc; | |
826 | ||
827 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
828 | if (buf[offset + 1] != 0xe4 | |
829 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
830 | return pc; | |
831 | ||
832 | offset_and = offset; | |
833 | offset += buf[offset] == 0x81 ? 6 : 3; | |
834 | ||
835 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
836 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
837 | if (buf[offset] != 0xff | |
838 | || buf[offset + 2] != 0xfc | |
839 | || (buf[offset + 1] & 0xf8) != 0x70) | |
840 | return pc; | |
841 | ||
842 | /* R/M has register. Registers in leal and pushl have to be the | |
843 | same. */ | |
844 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
845 | return pc; |
846 | ||
e0c62198 L |
847 | if (current_pc > pc + offset_and) |
848 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 849 | |
e0c62198 | 850 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
851 | } |
852 | ||
37bdc87e | 853 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 854 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
855 | |
856 | /* Instruction description. */ | |
857 | struct i386_insn | |
858 | { | |
859 | size_t len; | |
237fc4c9 PA |
860 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
861 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
862 | }; |
863 | ||
864 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
865 | the first instruction description that matches. Otherwise, return | |
866 | NULL. */ | |
867 | ||
868 | static struct i386_insn * | |
869 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
870 | { | |
871 | struct i386_insn *insn; | |
63c0089f | 872 | gdb_byte op; |
37bdc87e | 873 | |
8defab1a | 874 | target_read_memory (pc, &op, 1); |
37bdc87e MK |
875 | |
876 | for (insn = skip_insns; insn->len > 0; insn++) | |
877 | { | |
878 | if ((op & insn->mask[0]) == insn->insn[0]) | |
879 | { | |
237fc4c9 | 880 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
613e8135 | 881 | int insn_matched = 1; |
37bdc87e MK |
882 | size_t i; |
883 | ||
884 | gdb_assert (insn->len > 1); | |
237fc4c9 | 885 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
37bdc87e | 886 | |
8defab1a | 887 | target_read_memory (pc + 1, buf, insn->len - 1); |
37bdc87e MK |
888 | for (i = 1; i < insn->len; i++) |
889 | { | |
890 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 891 | insn_matched = 0; |
37bdc87e | 892 | } |
613e8135 MK |
893 | |
894 | if (insn_matched) | |
895 | return insn; | |
37bdc87e MK |
896 | } |
897 | } | |
898 | ||
899 | return NULL; | |
900 | } | |
901 | ||
902 | /* Some special instructions that might be migrated by GCC into the | |
903 | part of the prologue that sets up the new stack frame. Because the | |
904 | stack frame hasn't been setup yet, no registers have been saved | |
905 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
906 | touched. */ | |
907 | ||
908 | struct i386_insn i386_frame_setup_skip_insns[] = | |
909 | { | |
910 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
911 | ||
912 | ??? Should we handle 16-bit operand-sizes here? */ | |
913 | ||
914 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
915 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
916 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
917 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
918 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
919 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
920 | { 5, { 0xb8 }, { 0xfe } }, | |
921 | /* `movl imm32, %edx' */ | |
922 | { 5, { 0xba }, { 0xff } }, | |
923 | ||
924 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
925 | encoding for `mov m32, %eax'. | |
926 | ||
927 | ??? Should we handle SIB adressing here? | |
928 | ??? Should we handle 16-bit operand-sizes here? */ | |
929 | ||
930 | /* `movl m32, %eax' */ | |
931 | { 5, { 0xa1 }, { 0xff } }, | |
932 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
933 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
934 | /* `movl m32, %edx' */ | |
935 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
936 | ||
937 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
938 | Because of the symmetry, there are actually two ways to encode | |
939 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
940 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
941 | ||
942 | /* `subl %eax, %eax' */ | |
943 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
944 | /* `subl %ecx, %ecx' */ | |
945 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
946 | /* `subl %edx, %edx' */ | |
947 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
948 | /* `xorl %eax, %eax' */ | |
949 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
950 | /* `xorl %ecx, %ecx' */ | |
951 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
952 | /* `xorl %edx, %edx' */ | |
953 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
954 | { 0 } | |
955 | }; | |
956 | ||
e11481da PM |
957 | |
958 | /* Check whether PC points to a no-op instruction. */ | |
959 | static CORE_ADDR | |
960 | i386_skip_noop (CORE_ADDR pc) | |
961 | { | |
962 | gdb_byte op; | |
963 | int check = 1; | |
964 | ||
8defab1a | 965 | target_read_memory (pc, &op, 1); |
e11481da PM |
966 | |
967 | while (check) | |
968 | { | |
969 | check = 0; | |
970 | /* Ignore `nop' instruction. */ | |
971 | if (op == 0x90) | |
972 | { | |
973 | pc += 1; | |
8defab1a | 974 | target_read_memory (pc, &op, 1); |
e11481da PM |
975 | check = 1; |
976 | } | |
977 | /* Ignore no-op instruction `mov %edi, %edi'. | |
978 | Microsoft system dlls often start with | |
979 | a `mov %edi,%edi' instruction. | |
980 | The 5 bytes before the function start are | |
981 | filled with `nop' instructions. | |
982 | This pattern can be used for hot-patching: | |
983 | The `mov %edi, %edi' instruction can be replaced by a | |
984 | near jump to the location of the 5 `nop' instructions | |
985 | which can be replaced by a 32-bit jump to anywhere | |
986 | in the 32-bit address space. */ | |
987 | ||
988 | else if (op == 0x8b) | |
989 | { | |
8defab1a | 990 | target_read_memory (pc + 1, &op, 1); |
e11481da PM |
991 | if (op == 0xff) |
992 | { | |
993 | pc += 2; | |
8defab1a | 994 | target_read_memory (pc, &op, 1); |
e11481da PM |
995 | check = 1; |
996 | } | |
997 | } | |
998 | } | |
999 | return pc; | |
1000 | } | |
1001 | ||
acd5c798 MK |
1002 | /* Check whether PC points at a code that sets up a new stack frame. |
1003 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1004 | instruction after the sequence that sets up the frame or LIMIT, |
1005 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1006 | |
1007 | static CORE_ADDR | |
e17a4113 UW |
1008 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1009 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1010 | struct i386_frame_cache *cache) |
1011 | { | |
e17a4113 | 1012 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1013 | struct i386_insn *insn; |
63c0089f | 1014 | gdb_byte op; |
26604a34 | 1015 | int skip = 0; |
acd5c798 | 1016 | |
37bdc87e MK |
1017 | if (limit <= pc) |
1018 | return limit; | |
acd5c798 | 1019 | |
8defab1a | 1020 | target_read_memory (pc, &op, 1); |
acd5c798 | 1021 | |
c906108c | 1022 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1023 | { |
acd5c798 MK |
1024 | /* Take into account that we've executed the `pushl %ebp' that |
1025 | starts this instruction sequence. */ | |
fd13a04a | 1026 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1027 | cache->sp_offset += 4; |
37bdc87e | 1028 | pc++; |
acd5c798 MK |
1029 | |
1030 | /* If that's all, return now. */ | |
37bdc87e MK |
1031 | if (limit <= pc) |
1032 | return limit; | |
26604a34 | 1033 | |
b4632131 | 1034 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1035 | GCC into the prologue and skip them. At this point in the |
1036 | prologue, code should only touch the scratch registers %eax, | |
1037 | %ecx and %edx, so while the number of posibilities is sheer, | |
1038 | it is limited. | |
5daa5b4e | 1039 | |
26604a34 MK |
1040 | Make sure we only skip these instructions if we later see the |
1041 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1042 | while (pc + skip < limit) |
26604a34 | 1043 | { |
37bdc87e MK |
1044 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1045 | if (insn == NULL) | |
1046 | break; | |
b4632131 | 1047 | |
37bdc87e | 1048 | skip += insn->len; |
26604a34 MK |
1049 | } |
1050 | ||
37bdc87e MK |
1051 | /* If that's all, return now. */ |
1052 | if (limit <= pc + skip) | |
1053 | return limit; | |
1054 | ||
8defab1a | 1055 | target_read_memory (pc + skip, &op, 1); |
37bdc87e | 1056 | |
26604a34 | 1057 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1058 | switch (op) |
c906108c SS |
1059 | { |
1060 | case 0x8b: | |
e17a4113 UW |
1061 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1062 | != 0xec) | |
37bdc87e | 1063 | return pc; |
c906108c SS |
1064 | break; |
1065 | case 0x89: | |
e17a4113 UW |
1066 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1067 | != 0xe5) | |
37bdc87e | 1068 | return pc; |
c906108c SS |
1069 | break; |
1070 | default: | |
37bdc87e | 1071 | return pc; |
c906108c | 1072 | } |
acd5c798 | 1073 | |
26604a34 MK |
1074 | /* OK, we actually have a frame. We just don't know how large |
1075 | it is yet. Set its size to zero. We'll adjust it if | |
1076 | necessary. We also now commit to skipping the special | |
1077 | instructions mentioned before. */ | |
acd5c798 | 1078 | cache->locals = 0; |
37bdc87e | 1079 | pc += (skip + 2); |
acd5c798 MK |
1080 | |
1081 | /* If that's all, return now. */ | |
37bdc87e MK |
1082 | if (limit <= pc) |
1083 | return limit; | |
acd5c798 | 1084 | |
fc338970 MK |
1085 | /* Check for stack adjustment |
1086 | ||
acd5c798 | 1087 | subl $XXX, %esp |
fc338970 | 1088 | |
fd35795f | 1089 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1090 | reg, so we don't have to worry about a data16 prefix. */ |
8defab1a | 1091 | target_read_memory (pc, &op, 1); |
c906108c SS |
1092 | if (op == 0x83) |
1093 | { | |
fd35795f | 1094 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1095 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1096 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1097 | return pc; |
acd5c798 | 1098 | |
37bdc87e MK |
1099 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1100 | make sense to be negative). */ | |
e17a4113 | 1101 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1102 | return pc + 3; |
c906108c SS |
1103 | } |
1104 | else if (op == 0x81) | |
1105 | { | |
fd35795f | 1106 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1107 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1108 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1109 | return pc; |
acd5c798 | 1110 | |
fd35795f | 1111 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1112 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1113 | return pc + 6; |
c906108c SS |
1114 | } |
1115 | else | |
1116 | { | |
acd5c798 | 1117 | /* Some instruction other than `subl'. */ |
37bdc87e | 1118 | return pc; |
c906108c SS |
1119 | } |
1120 | } | |
37bdc87e | 1121 | else if (op == 0xc8) /* enter */ |
c906108c | 1122 | { |
e17a4113 | 1123 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1124 | return pc + 4; |
c906108c | 1125 | } |
21d0e8a4 | 1126 | |
acd5c798 | 1127 | return pc; |
21d0e8a4 MK |
1128 | } |
1129 | ||
acd5c798 MK |
1130 | /* Check whether PC points at code that saves registers on the stack. |
1131 | If so, it updates CACHE and returns the address of the first | |
1132 | instruction after the register saves or CURRENT_PC, whichever is | |
1133 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1134 | |
1135 | static CORE_ADDR | |
acd5c798 MK |
1136 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1137 | struct i386_frame_cache *cache) | |
6bff26de | 1138 | { |
99ab4326 | 1139 | CORE_ADDR offset = 0; |
63c0089f | 1140 | gdb_byte op; |
99ab4326 | 1141 | int i; |
c0d1d883 | 1142 | |
99ab4326 MK |
1143 | if (cache->locals > 0) |
1144 | offset -= cache->locals; | |
1145 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1146 | { | |
8defab1a | 1147 | target_read_memory (pc, &op, 1); |
99ab4326 MK |
1148 | if (op < 0x50 || op > 0x57) |
1149 | break; | |
0d17c81d | 1150 | |
99ab4326 MK |
1151 | offset -= 4; |
1152 | cache->saved_regs[op - 0x50] = offset; | |
1153 | cache->sp_offset += 4; | |
1154 | pc++; | |
6bff26de MK |
1155 | } |
1156 | ||
acd5c798 | 1157 | return pc; |
22797942 AC |
1158 | } |
1159 | ||
acd5c798 MK |
1160 | /* Do a full analysis of the prologue at PC and update CACHE |
1161 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1162 | address where the analysis stopped. | |
ed84f6c1 | 1163 | |
fc338970 MK |
1164 | We handle these cases: |
1165 | ||
1166 | The startup sequence can be at the start of the function, or the | |
1167 | function can start with a branch to startup code at the end. | |
1168 | ||
1169 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1170 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1171 | once used in the System V compiler). | |
1172 | ||
1173 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1174 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1175 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1176 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1177 | |
1178 | Next, the registers used by this function are pushed. With the | |
1179 | System V compiler they will always be in the order: %edi, %esi, | |
1180 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1181 | restore %eax); however, the code below is willing to see the pushes | |
1182 | in any order, and will handle up to 8 of them. | |
1183 | ||
1184 | If the setup sequence is at the end of the function, then the next | |
1185 | instruction will be a branch back to the start. */ | |
c906108c | 1186 | |
acd5c798 | 1187 | static CORE_ADDR |
e17a4113 UW |
1188 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1189 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1190 | struct i386_frame_cache *cache) |
c906108c | 1191 | { |
e11481da | 1192 | pc = i386_skip_noop (pc); |
e17a4113 | 1193 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1194 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1195 | pc = i386_skip_probe (pc); | |
92dd43fa | 1196 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1197 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1198 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1199 | } |
1200 | ||
fc338970 | 1201 | /* Return PC of first real instruction. */ |
c906108c | 1202 | |
3a1e71e3 | 1203 | static CORE_ADDR |
6093d2eb | 1204 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1205 | { |
e17a4113 UW |
1206 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1207 | ||
63c0089f | 1208 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1209 | { |
1210 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1211 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1212 | }; |
acd5c798 MK |
1213 | struct i386_frame_cache cache; |
1214 | CORE_ADDR pc; | |
63c0089f | 1215 | gdb_byte op; |
acd5c798 | 1216 | int i; |
c5aa993b | 1217 | |
acd5c798 | 1218 | cache.locals = -1; |
e17a4113 | 1219 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1220 | if (cache.locals < 0) |
1221 | return start_pc; | |
c5aa993b | 1222 | |
acd5c798 | 1223 | /* Found valid frame setup. */ |
c906108c | 1224 | |
fc338970 MK |
1225 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1226 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1227 | %ebx: |
1228 | ||
fc338970 MK |
1229 | call 0x0 |
1230 | popl %ebx | |
1231 | movl %ebx,x(%ebp) (optional) | |
1232 | addl y,%ebx | |
1233 | ||
c906108c SS |
1234 | This code is with the rest of the prologue (at the end of the |
1235 | function), so we have to skip it to get to the first real | |
1236 | instruction at the start of the function. */ | |
c5aa993b | 1237 | |
c906108c SS |
1238 | for (i = 0; i < 6; i++) |
1239 | { | |
8defab1a | 1240 | target_read_memory (pc + i, &op, 1); |
c5aa993b | 1241 | if (pic_pat[i] != op) |
c906108c SS |
1242 | break; |
1243 | } | |
1244 | if (i == 6) | |
1245 | { | |
acd5c798 MK |
1246 | int delta = 6; |
1247 | ||
8defab1a | 1248 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1249 | |
c5aa993b | 1250 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1251 | { |
e17a4113 | 1252 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1253 | |
fc338970 | 1254 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1255 | delta += 3; |
fc338970 | 1256 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1257 | delta += 6; |
fc338970 | 1258 | else /* Unexpected instruction. */ |
acd5c798 MK |
1259 | delta = 0; |
1260 | ||
8defab1a | 1261 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1262 | } |
acd5c798 | 1263 | |
c5aa993b | 1264 | /* addl y,%ebx */ |
acd5c798 | 1265 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1266 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1267 | == 0xc3) | |
c906108c | 1268 | { |
acd5c798 | 1269 | pc += delta + 6; |
c906108c SS |
1270 | } |
1271 | } | |
c5aa993b | 1272 | |
e63bbc88 MK |
1273 | /* If the function starts with a branch (to startup code at the end) |
1274 | the last instruction should bring us back to the first | |
1275 | instruction of the real code. */ | |
e17a4113 UW |
1276 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1277 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1278 | |
1279 | return pc; | |
c906108c SS |
1280 | } |
1281 | ||
4309257c PM |
1282 | /* Check that the code pointed to by PC corresponds to a call to |
1283 | __main, skip it if so. Return PC otherwise. */ | |
1284 | ||
1285 | CORE_ADDR | |
1286 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1287 | { | |
e17a4113 | 1288 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1289 | gdb_byte op; |
1290 | ||
1291 | target_read_memory (pc, &op, 1); | |
1292 | if (op == 0xe8) | |
1293 | { | |
1294 | gdb_byte buf[4]; | |
1295 | ||
1296 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1297 | { | |
1298 | /* Make sure address is computed correctly as a 32bit | |
1299 | integer even if CORE_ADDR is 64 bit wide. */ | |
1300 | struct minimal_symbol *s; | |
e17a4113 | 1301 | CORE_ADDR call_dest; |
4309257c | 1302 | |
e17a4113 | 1303 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1304 | call_dest = call_dest & 0xffffffffU; |
1305 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1306 | if (s != NULL | |
1307 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1308 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1309 | pc += 5; | |
1310 | } | |
1311 | } | |
1312 | ||
1313 | return pc; | |
1314 | } | |
1315 | ||
acd5c798 | 1316 | /* This function is 64-bit safe. */ |
93924b6b | 1317 | |
acd5c798 MK |
1318 | static CORE_ADDR |
1319 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1320 | { |
63c0089f | 1321 | gdb_byte buf[8]; |
acd5c798 | 1322 | |
875f8d0e | 1323 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1324 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1325 | } |
acd5c798 | 1326 | \f |
93924b6b | 1327 | |
acd5c798 | 1328 | /* Normal frames. */ |
c5aa993b | 1329 | |
acd5c798 | 1330 | static struct i386_frame_cache * |
10458914 | 1331 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
a7769679 | 1332 | { |
e17a4113 UW |
1333 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1334 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1335 | struct i386_frame_cache *cache; |
63c0089f | 1336 | gdb_byte buf[4]; |
acd5c798 MK |
1337 | int i; |
1338 | ||
1339 | if (*this_cache) | |
1340 | return *this_cache; | |
1341 | ||
fd13a04a | 1342 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1343 | *this_cache = cache; |
1344 | ||
1345 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1346 | which holds the base address for the current stack frame. | |
1347 | However, for functions that don't need it, the frame pointer is | |
1348 | optional. For these "frameless" functions the frame pointer is | |
1349 | actually the frame pointer of the calling frame. Signal | |
1350 | trampolines are just a special case of a "frameless" function. | |
1351 | They (usually) share their frame pointer with the frame that was | |
1352 | in progress when the signal occurred. */ | |
1353 | ||
10458914 | 1354 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1355 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 MK |
1356 | if (cache->base == 0) |
1357 | return cache; | |
1358 | ||
1359 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1360 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1361 | |
10458914 | 1362 | cache->pc = get_frame_func (this_frame); |
acd5c798 | 1363 | if (cache->pc != 0) |
e17a4113 UW |
1364 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1365 | cache); | |
acd5c798 | 1366 | |
e0c62198 | 1367 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1368 | { |
e0c62198 L |
1369 | /* Saved stack pointer has been saved. */ |
1370 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
e17a4113 | 1371 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
92dd43fa MK |
1372 | } |
1373 | ||
acd5c798 MK |
1374 | if (cache->locals < 0) |
1375 | { | |
1376 | /* We didn't find a valid frame, which means that CACHE->base | |
1377 | currently holds the frame pointer for our calling frame. If | |
1378 | we're at the start of a function, or somewhere half-way its | |
1379 | prologue, the function's frame probably hasn't been fully | |
1380 | setup yet. Try to reconstruct the base address for the stack | |
1381 | frame by looking at the stack pointer. For truly "frameless" | |
1382 | functions this might work too. */ | |
1383 | ||
e0c62198 | 1384 | if (cache->saved_sp_reg != -1) |
92dd43fa MK |
1385 | { |
1386 | /* We're halfway aligning the stack. */ | |
1387 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1388 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1389 | ||
1390 | /* This will be added back below. */ | |
1391 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1392 | } | |
7618e12b DJ |
1393 | else if (cache->pc != 0 |
1394 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1395 | { |
7618e12b DJ |
1396 | /* We're in a known function, but did not find a frame |
1397 | setup. Assume that the function does not use %ebp. | |
1398 | Alternatively, we may have jumped to an invalid | |
1399 | address; in that case there is definitely no new | |
1400 | frame in %ebp. */ | |
10458914 | 1401 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1402 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1403 | + cache->sp_offset; | |
92dd43fa | 1404 | } |
7618e12b DJ |
1405 | else |
1406 | /* We're in an unknown function. We could not find the start | |
1407 | of the function to analyze the prologue; our best option is | |
1408 | to assume a typical frame layout with the caller's %ebp | |
1409 | saved. */ | |
1410 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1411 | } |
1412 | ||
1413 | /* Now that we have the base address for the stack frame we can | |
1414 | calculate the value of %esp in the calling frame. */ | |
92dd43fa MK |
1415 | if (cache->saved_sp == 0) |
1416 | cache->saved_sp = cache->base + 8; | |
a7769679 | 1417 | |
acd5c798 MK |
1418 | /* Adjust all the saved registers such that they contain addresses |
1419 | instead of offsets. */ | |
1420 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1421 | if (cache->saved_regs[i] != -1) |
1422 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
1423 | |
1424 | return cache; | |
a7769679 MK |
1425 | } |
1426 | ||
3a1e71e3 | 1427 | static void |
10458914 | 1428 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1429 | struct frame_id *this_id) |
c906108c | 1430 | { |
10458914 | 1431 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1432 | |
1433 | /* This marks the outermost frame. */ | |
1434 | if (cache->base == 0) | |
1435 | return; | |
1436 | ||
3e210248 | 1437 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1438 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1439 | } | |
1440 | ||
10458914 DJ |
1441 | static struct value * |
1442 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1443 | int regnum) | |
acd5c798 | 1444 | { |
10458914 | 1445 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1446 | |
1447 | gdb_assert (regnum >= 0); | |
1448 | ||
1449 | /* The System V ABI says that: | |
1450 | ||
1451 | "The flags register contains the system flags, such as the | |
1452 | direction flag and the carry flag. The direction flag must be | |
1453 | set to the forward (that is, zero) direction before entry and | |
1454 | upon exit from a function. Other user flags have no specified | |
1455 | role in the standard calling sequence and are not preserved." | |
1456 | ||
1457 | To guarantee the "upon exit" part of that statement we fake a | |
1458 | saved flags register that has its direction flag cleared. | |
1459 | ||
1460 | Note that GCC doesn't seem to rely on the fact that the direction | |
1461 | flag is cleared after a function return; it always explicitly | |
1462 | clears the flag before operations where it matters. | |
1463 | ||
1464 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1465 | right thing to do. The way we fake the flags register here makes | |
1466 | it impossible to change it. */ | |
1467 | ||
1468 | if (regnum == I386_EFLAGS_REGNUM) | |
1469 | { | |
10458914 | 1470 | ULONGEST val; |
c5aa993b | 1471 | |
10458914 DJ |
1472 | val = get_frame_register_unsigned (this_frame, regnum); |
1473 | val &= ~(1 << 10); | |
1474 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1475 | } |
1211c4e4 | 1476 | |
acd5c798 | 1477 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1478 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 MK |
1479 | |
1480 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
10458914 | 1481 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
acd5c798 | 1482 | |
fd13a04a | 1483 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1484 | return frame_unwind_got_memory (this_frame, regnum, |
1485 | cache->saved_regs[regnum]); | |
fd13a04a | 1486 | |
10458914 | 1487 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1488 | } |
1489 | ||
1490 | static const struct frame_unwind i386_frame_unwind = | |
1491 | { | |
1492 | NORMAL_FRAME, | |
1493 | i386_frame_this_id, | |
10458914 DJ |
1494 | i386_frame_prev_register, |
1495 | NULL, | |
1496 | default_frame_sniffer | |
acd5c798 | 1497 | }; |
06da04c6 MS |
1498 | |
1499 | /* Normal frames, but in a function epilogue. */ | |
1500 | ||
1501 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1502 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1503 | the function's stack frame. */ | |
1504 | ||
1505 | static int | |
1506 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1507 | { | |
1508 | gdb_byte insn; | |
1509 | ||
1510 | if (target_read_memory (pc, &insn, 1)) | |
1511 | return 0; /* Can't read memory at pc. */ | |
1512 | ||
1513 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1514 | return 0; | |
1515 | ||
1516 | return 1; | |
1517 | } | |
1518 | ||
1519 | static int | |
1520 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1521 | struct frame_info *this_frame, | |
1522 | void **this_prologue_cache) | |
1523 | { | |
1524 | if (frame_relative_level (this_frame) == 0) | |
1525 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1526 | get_frame_pc (this_frame)); | |
1527 | else | |
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | static struct i386_frame_cache * | |
1532 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1533 | { | |
1534 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1535 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1536 | struct i386_frame_cache *cache; | |
1537 | gdb_byte buf[4]; | |
1538 | ||
1539 | if (*this_cache) | |
1540 | return *this_cache; | |
1541 | ||
1542 | cache = i386_alloc_frame_cache (); | |
1543 | *this_cache = cache; | |
1544 | ||
1545 | /* Cache base will be %esp plus cache->sp_offset (-4). */ | |
1546 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); | |
1547 | cache->base = extract_unsigned_integer (buf, 4, | |
1548 | byte_order) + cache->sp_offset; | |
1549 | ||
1550 | /* Cache pc will be the frame func. */ | |
1551 | cache->pc = get_frame_pc (this_frame); | |
1552 | ||
1553 | /* The saved %esp will be at cache->base plus 8. */ | |
1554 | cache->saved_sp = cache->base + 8; | |
1555 | ||
1556 | /* The saved %eip will be at cache->base plus 4. */ | |
1557 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; | |
1558 | ||
1559 | return cache; | |
1560 | } | |
1561 | ||
1562 | static void | |
1563 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1564 | void **this_cache, | |
1565 | struct frame_id *this_id) | |
1566 | { | |
1567 | struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame, | |
1568 | this_cache); | |
1569 | ||
1570 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
1571 | } | |
1572 | ||
1573 | static const struct frame_unwind i386_epilogue_frame_unwind = | |
1574 | { | |
1575 | NORMAL_FRAME, | |
1576 | i386_epilogue_frame_this_id, | |
1577 | i386_frame_prev_register, | |
1578 | NULL, | |
1579 | i386_epilogue_frame_sniffer | |
1580 | }; | |
acd5c798 MK |
1581 | \f |
1582 | ||
1583 | /* Signal trampolines. */ | |
1584 | ||
1585 | static struct i386_frame_cache * | |
10458914 | 1586 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1587 | { |
e17a4113 UW |
1588 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1589 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1590 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1591 | struct i386_frame_cache *cache; |
acd5c798 | 1592 | CORE_ADDR addr; |
63c0089f | 1593 | gdb_byte buf[4]; |
acd5c798 MK |
1594 | |
1595 | if (*this_cache) | |
1596 | return *this_cache; | |
1597 | ||
fd13a04a | 1598 | cache = i386_alloc_frame_cache (); |
acd5c798 | 1599 | |
10458914 | 1600 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1601 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; |
acd5c798 | 1602 | |
10458914 | 1603 | addr = tdep->sigcontext_addr (this_frame); |
a3386186 MK |
1604 | if (tdep->sc_reg_offset) |
1605 | { | |
1606 | int i; | |
1607 | ||
1608 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1609 | ||
1610 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1611 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1612 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1613 | } |
1614 | else | |
1615 | { | |
fd13a04a AC |
1616 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1617 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1618 | } |
acd5c798 MK |
1619 | |
1620 | *this_cache = cache; | |
1621 | return cache; | |
1622 | } | |
1623 | ||
1624 | static void | |
10458914 | 1625 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
1626 | struct frame_id *this_id) |
1627 | { | |
1628 | struct i386_frame_cache *cache = | |
10458914 | 1629 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1630 | |
3e210248 | 1631 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1632 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
1633 | } |
1634 | ||
10458914 DJ |
1635 | static struct value * |
1636 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1637 | void **this_cache, int regnum) | |
acd5c798 MK |
1638 | { |
1639 | /* Make sure we've initialized the cache. */ | |
10458914 | 1640 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1641 | |
10458914 | 1642 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 1643 | } |
c0d1d883 | 1644 | |
10458914 DJ |
1645 | static int |
1646 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1647 | struct frame_info *this_frame, | |
1648 | void **this_prologue_cache) | |
acd5c798 | 1649 | { |
10458914 | 1650 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1651 | |
911bc6ee MK |
1652 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1653 | handler. */ | |
1654 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1655 | return 0; |
1c3545ae | 1656 | |
911bc6ee MK |
1657 | if (tdep->sigtramp_p != NULL) |
1658 | { | |
10458914 DJ |
1659 | if (tdep->sigtramp_p (this_frame)) |
1660 | return 1; | |
911bc6ee MK |
1661 | } |
1662 | ||
1663 | if (tdep->sigtramp_start != 0) | |
1664 | { | |
10458914 | 1665 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
1666 | |
1667 | gdb_assert (tdep->sigtramp_end != 0); | |
1668 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1669 | return 1; |
911bc6ee | 1670 | } |
acd5c798 | 1671 | |
10458914 | 1672 | return 0; |
acd5c798 | 1673 | } |
10458914 DJ |
1674 | |
1675 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
1676 | { | |
1677 | SIGTRAMP_FRAME, | |
1678 | i386_sigtramp_frame_this_id, | |
1679 | i386_sigtramp_frame_prev_register, | |
1680 | NULL, | |
1681 | i386_sigtramp_frame_sniffer | |
1682 | }; | |
acd5c798 MK |
1683 | \f |
1684 | ||
1685 | static CORE_ADDR | |
10458914 | 1686 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1687 | { |
10458914 | 1688 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1689 | |
1690 | return cache->base; | |
1691 | } | |
1692 | ||
1693 | static const struct frame_base i386_frame_base = | |
1694 | { | |
1695 | &i386_frame_unwind, | |
1696 | i386_frame_base_address, | |
1697 | i386_frame_base_address, | |
1698 | i386_frame_base_address | |
1699 | }; | |
1700 | ||
acd5c798 | 1701 | static struct frame_id |
10458914 | 1702 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 1703 | { |
acd5c798 MK |
1704 | CORE_ADDR fp; |
1705 | ||
10458914 | 1706 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 1707 | |
3e210248 | 1708 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1709 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 1710 | } |
fc338970 | 1711 | \f |
c906108c | 1712 | |
fc338970 MK |
1713 | /* Figure out where the longjmp will land. Slurp the args out of the |
1714 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1715 | structure from which we extract the address that we will land at. |
28bcfd30 | 1716 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 1717 | success. */ |
c906108c | 1718 | |
8201327c | 1719 | static int |
60ade65d | 1720 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 1721 | { |
436675d3 | 1722 | gdb_byte buf[4]; |
c906108c | 1723 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 1724 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 1725 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 1726 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 1727 | |
8201327c MK |
1728 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1729 | longjmp will land. */ | |
1730 | if (jb_pc_offset == -1) | |
c906108c SS |
1731 | return 0; |
1732 | ||
436675d3 | 1733 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1734 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1735 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
1736 | return 0; |
1737 | ||
e17a4113 | 1738 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1739 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 1740 | return 0; |
c906108c | 1741 | |
e17a4113 | 1742 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
1743 | return 1; |
1744 | } | |
fc338970 | 1745 | \f |
c906108c | 1746 | |
7ccc1c74 JM |
1747 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
1748 | function argument. 16-byte vectors, _Decimal128 and structures or | |
1749 | unions containing such types must be 16-byte-aligned; other | |
1750 | arguments are 4-byte-aligned. */ | |
1751 | ||
1752 | static int | |
1753 | i386_16_byte_align_p (struct type *type) | |
1754 | { | |
1755 | type = check_typedef (type); | |
1756 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
1757 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
1758 | && TYPE_LENGTH (type) == 16) | |
1759 | return 1; | |
1760 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
1761 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
1762 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1763 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
1764 | { | |
1765 | int i; | |
1766 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
1767 | { | |
1768 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
1769 | return 1; | |
1770 | } | |
1771 | } | |
1772 | return 0; | |
1773 | } | |
1774 | ||
3a1e71e3 | 1775 | static CORE_ADDR |
7d9b040b | 1776 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1777 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1778 | struct value **args, CORE_ADDR sp, int struct_return, | |
1779 | CORE_ADDR struct_addr) | |
22f8ba57 | 1780 | { |
e17a4113 | 1781 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1782 | gdb_byte buf[4]; |
acd5c798 | 1783 | int i; |
7ccc1c74 JM |
1784 | int write_pass; |
1785 | int args_space = 0; | |
acd5c798 | 1786 | |
7ccc1c74 JM |
1787 | /* Determine the total space required for arguments and struct |
1788 | return address in a first pass (allowing for 16-byte-aligned | |
1789 | arguments), then push arguments in a second pass. */ | |
1790 | ||
1791 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 1792 | { |
7ccc1c74 JM |
1793 | int args_space_used = 0; |
1794 | int have_16_byte_aligned_arg = 0; | |
1795 | ||
1796 | if (struct_return) | |
1797 | { | |
1798 | if (write_pass) | |
1799 | { | |
1800 | /* Push value address. */ | |
e17a4113 | 1801 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
1802 | write_memory (sp, buf, 4); |
1803 | args_space_used += 4; | |
1804 | } | |
1805 | else | |
1806 | args_space += 4; | |
1807 | } | |
1808 | ||
1809 | for (i = 0; i < nargs; i++) | |
1810 | { | |
1811 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 1812 | |
7ccc1c74 JM |
1813 | if (write_pass) |
1814 | { | |
1815 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1816 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 1817 | |
7ccc1c74 JM |
1818 | write_memory (sp + args_space_used, |
1819 | value_contents_all (args[i]), len); | |
1820 | /* The System V ABI says that: | |
acd5c798 | 1821 | |
7ccc1c74 JM |
1822 | "An argument's size is increased, if necessary, to make it a |
1823 | multiple of [32-bit] words. This may require tail padding, | |
1824 | depending on the size of the argument." | |
22f8ba57 | 1825 | |
7ccc1c74 JM |
1826 | This makes sure the stack stays word-aligned. */ |
1827 | args_space_used += align_up (len, 4); | |
1828 | } | |
1829 | else | |
1830 | { | |
1831 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1832 | { | |
1833 | args_space = align_up (args_space, 16); | |
1834 | have_16_byte_aligned_arg = 1; | |
1835 | } | |
1836 | args_space += align_up (len, 4); | |
1837 | } | |
1838 | } | |
1839 | ||
1840 | if (!write_pass) | |
1841 | { | |
1842 | if (have_16_byte_aligned_arg) | |
1843 | args_space = align_up (args_space, 16); | |
1844 | sp -= args_space; | |
1845 | } | |
22f8ba57 MK |
1846 | } |
1847 | ||
acd5c798 MK |
1848 | /* Store return address. */ |
1849 | sp -= 4; | |
e17a4113 | 1850 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
1851 | write_memory (sp, buf, 4); |
1852 | ||
1853 | /* Finally, update the stack pointer... */ | |
e17a4113 | 1854 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
1855 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
1856 | ||
1857 | /* ...and fake a frame pointer. */ | |
1858 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
1859 | ||
3e210248 AC |
1860 | /* MarkK wrote: This "+ 8" is all over the place: |
1861 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 1862 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 1863 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
1864 | definition of the stack address of a frame. Otherwise frame id |
1865 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
1866 | stack address *before* the function call as a frame's CFA. On |
1867 | the i386, when %ebp is used as a frame pointer, the offset | |
1868 | between the contents %ebp and the CFA as defined by GCC. */ | |
1869 | return sp + 8; | |
22f8ba57 MK |
1870 | } |
1871 | ||
1a309862 MK |
1872 | /* These registers are used for returning integers (and on some |
1873 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 1874 | size and alignment match an integer type). */ |
acd5c798 MK |
1875 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
1876 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 1877 | |
c5e656c1 MK |
1878 | /* Read, for architecture GDBARCH, a function return value of TYPE |
1879 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 1880 | |
3a1e71e3 | 1881 | static void |
c5e656c1 | 1882 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1883 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 1884 | { |
c5e656c1 | 1885 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 1886 | int len = TYPE_LENGTH (type); |
63c0089f | 1887 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 1888 | |
1e8d0a7b | 1889 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 1890 | { |
5716833c | 1891 | if (tdep->st0_regnum < 0) |
1a309862 | 1892 | { |
8a3fe4f8 | 1893 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 1894 | memset (valbuf, 0, len); |
ef9dff19 | 1895 | return; |
1a309862 MK |
1896 | } |
1897 | ||
c6ba6f0d MK |
1898 | /* Floating-point return values can be found in %st(0). Convert |
1899 | its contents to the desired type. This is probably not | |
1900 | exactly how it would happen on the target itself, but it is | |
1901 | the best we can do. */ | |
acd5c798 | 1902 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 1903 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
1904 | } |
1905 | else | |
c5aa993b | 1906 | { |
875f8d0e UW |
1907 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1908 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
1909 | |
1910 | if (len <= low_size) | |
00f8375e | 1911 | { |
0818c12a | 1912 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
1913 | memcpy (valbuf, buf, len); |
1914 | } | |
d4f3574e SS |
1915 | else if (len <= (low_size + high_size)) |
1916 | { | |
0818c12a | 1917 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 1918 | memcpy (valbuf, buf, low_size); |
0818c12a | 1919 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 1920 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
1921 | } |
1922 | else | |
8e65ff28 | 1923 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1924 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
1925 | } |
1926 | } | |
1927 | ||
c5e656c1 MK |
1928 | /* Write, for architecture GDBARCH, a function return value of TYPE |
1929 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 1930 | |
3a1e71e3 | 1931 | static void |
c5e656c1 | 1932 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1933 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 1934 | { |
c5e656c1 | 1935 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
1936 | int len = TYPE_LENGTH (type); |
1937 | ||
1e8d0a7b | 1938 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 1939 | { |
3d7f4f49 | 1940 | ULONGEST fstat; |
63c0089f | 1941 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 1942 | |
5716833c | 1943 | if (tdep->st0_regnum < 0) |
ef9dff19 | 1944 | { |
8a3fe4f8 | 1945 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
1946 | return; |
1947 | } | |
1948 | ||
635b0cc1 MK |
1949 | /* Returning floating-point values is a bit tricky. Apart from |
1950 | storing the return value in %st(0), we have to simulate the | |
1951 | state of the FPU at function return point. */ | |
1952 | ||
c6ba6f0d MK |
1953 | /* Convert the value found in VALBUF to the extended |
1954 | floating-point format used by the FPU. This is probably | |
1955 | not exactly how it would happen on the target itself, but | |
1956 | it is the best we can do. */ | |
27067745 | 1957 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 1958 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 1959 | |
635b0cc1 MK |
1960 | /* Set the top of the floating-point register stack to 7. The |
1961 | actual value doesn't really matter, but 7 is what a normal | |
1962 | function return would end up with if the program started out | |
1963 | with a freshly initialized FPU. */ | |
20a6ec49 | 1964 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 1965 | fstat |= (7 << 11); |
20a6ec49 | 1966 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 1967 | |
635b0cc1 MK |
1968 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
1969 | the floating-point register stack to 7, the appropriate value | |
1970 | for the tag word is 0x3fff. */ | |
20a6ec49 | 1971 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
1972 | } |
1973 | else | |
1974 | { | |
875f8d0e UW |
1975 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1976 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
1977 | |
1978 | if (len <= low_size) | |
3d7f4f49 | 1979 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
1980 | else if (len <= (low_size + high_size)) |
1981 | { | |
3d7f4f49 MK |
1982 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
1983 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 1984 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
1985 | } |
1986 | else | |
8e65ff28 | 1987 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1988 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
1989 | } |
1990 | } | |
fc338970 | 1991 | \f |
ef9dff19 | 1992 | |
8201327c MK |
1993 | /* This is the variable that is set with "set struct-convention", and |
1994 | its legitimate values. */ | |
1995 | static const char default_struct_convention[] = "default"; | |
1996 | static const char pcc_struct_convention[] = "pcc"; | |
1997 | static const char reg_struct_convention[] = "reg"; | |
1998 | static const char *valid_conventions[] = | |
1999 | { | |
2000 | default_struct_convention, | |
2001 | pcc_struct_convention, | |
2002 | reg_struct_convention, | |
2003 | NULL | |
2004 | }; | |
2005 | static const char *struct_convention = default_struct_convention; | |
2006 | ||
0e4377e1 JB |
2007 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2008 | a union type, or an array type, should be returned in registers | |
2009 | for architecture GDBARCH. */ | |
c5e656c1 | 2010 | |
8201327c | 2011 | static int |
c5e656c1 | 2012 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2013 | { |
c5e656c1 MK |
2014 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2015 | enum type_code code = TYPE_CODE (type); | |
2016 | int len = TYPE_LENGTH (type); | |
8201327c | 2017 | |
0e4377e1 JB |
2018 | gdb_assert (code == TYPE_CODE_STRUCT |
2019 | || code == TYPE_CODE_UNION | |
2020 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2021 | |
2022 | if (struct_convention == pcc_struct_convention | |
2023 | || (struct_convention == default_struct_convention | |
2024 | && tdep->struct_return == pcc_struct_return)) | |
2025 | return 0; | |
2026 | ||
9edde48e MK |
2027 | /* Structures consisting of a single `float', `double' or 'long |
2028 | double' member are returned in %st(0). */ | |
2029 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2030 | { | |
2031 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2032 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2033 | return (len == 4 || len == 8 || len == 12); | |
2034 | } | |
2035 | ||
c5e656c1 MK |
2036 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2037 | } | |
2038 | ||
2039 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2040 | should be returned. If it is supposed to be returned in registers, | |
2041 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2042 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2043 | from WRITEBUF into REGCACHE. */ | |
2044 | ||
2045 | static enum return_value_convention | |
c055b101 CV |
2046 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2047 | struct type *type, struct regcache *regcache, | |
2048 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2049 | { |
2050 | enum type_code code = TYPE_CODE (type); | |
2051 | ||
5daa78cc TJB |
2052 | if (((code == TYPE_CODE_STRUCT |
2053 | || code == TYPE_CODE_UNION | |
2054 | || code == TYPE_CODE_ARRAY) | |
2055 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2056 | /* 128-bit decimal float uses the struct return convention. */ | |
2057 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2058 | { |
2059 | /* The System V ABI says that: | |
2060 | ||
2061 | "A function that returns a structure or union also sets %eax | |
2062 | to the value of the original address of the caller's area | |
2063 | before it returns. Thus when the caller receives control | |
2064 | again, the address of the returned object resides in register | |
2065 | %eax and can be used to access the object." | |
2066 | ||
2067 | So the ABI guarantees that we can always find the return | |
2068 | value just after the function has returned. */ | |
2069 | ||
0e4377e1 JB |
2070 | /* Note that the ABI doesn't mention functions returning arrays, |
2071 | which is something possible in certain languages such as Ada. | |
2072 | In this case, the value is returned as if it was wrapped in | |
2073 | a record, so the convention applied to records also applies | |
2074 | to arrays. */ | |
2075 | ||
31db7b6c MK |
2076 | if (readbuf) |
2077 | { | |
2078 | ULONGEST addr; | |
2079 | ||
2080 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2081 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2082 | } | |
2083 | ||
2084 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2085 | } | |
c5e656c1 MK |
2086 | |
2087 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2088 | `float', `double' or 'long double' member. These structures are |
2089 | returned in %st(0). For these structures, we call ourselves | |
2090 | recursively, changing TYPE into the type of the first member of | |
2091 | the structure. Since that should work for all structures that | |
2092 | have only one member, we don't bother to check the member's type | |
2093 | here. */ | |
c5e656c1 MK |
2094 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2095 | { | |
2096 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2097 | return i386_return_value (gdbarch, func_type, type, regcache, |
2098 | readbuf, writebuf); | |
c5e656c1 MK |
2099 | } |
2100 | ||
2101 | if (readbuf) | |
2102 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2103 | if (writebuf) | |
2104 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2105 | |
c5e656c1 | 2106 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2107 | } |
2108 | \f | |
2109 | ||
27067745 UW |
2110 | struct type * |
2111 | i387_ext_type (struct gdbarch *gdbarch) | |
2112 | { | |
2113 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2114 | ||
2115 | if (!tdep->i387_ext_type) | |
90884b2b L |
2116 | { |
2117 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2118 | gdb_assert (tdep->i387_ext_type != NULL); | |
2119 | } | |
27067745 UW |
2120 | |
2121 | return tdep->i387_ext_type; | |
2122 | } | |
2123 | ||
794ac428 | 2124 | /* Construct vector type for MMX registers. */ |
90884b2b | 2125 | static struct type * |
794ac428 UW |
2126 | i386_mmx_type (struct gdbarch *gdbarch) |
2127 | { | |
2128 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2129 | ||
2130 | if (!tdep->i386_mmx_type) | |
2131 | { | |
df4df182 UW |
2132 | const struct builtin_type *bt = builtin_type (gdbarch); |
2133 | ||
794ac428 UW |
2134 | /* The type we're building is this: */ |
2135 | #if 0 | |
2136 | union __gdb_builtin_type_vec64i | |
2137 | { | |
2138 | int64_t uint64; | |
2139 | int32_t v2_int32[2]; | |
2140 | int16_t v4_int16[4]; | |
2141 | int8_t v8_int8[8]; | |
2142 | }; | |
2143 | #endif | |
2144 | ||
2145 | struct type *t; | |
2146 | ||
e9bb382b UW |
2147 | t = arch_composite_type (gdbarch, |
2148 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2149 | |
2150 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2151 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2152 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2153 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2154 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2155 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2156 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2157 | |
876cecd0 | 2158 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2159 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2160 | tdep->i386_mmx_type = t; | |
2161 | } | |
2162 | ||
2163 | return tdep->i386_mmx_type; | |
2164 | } | |
2165 | ||
d7a0d72c | 2166 | /* Return the GDB type object for the "standard" data type of data in |
90884b2b | 2167 | register REGNUM. */ |
d7a0d72c | 2168 | |
3a1e71e3 | 2169 | static struct type * |
90884b2b | 2170 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2171 | { |
90884b2b L |
2172 | gdb_assert (i386_mmx_regnum_p (gdbarch, regnum)); |
2173 | return i386_mmx_type (gdbarch); | |
d7a0d72c MK |
2174 | } |
2175 | ||
28fc6740 | 2176 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2177 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2178 | |
2179 | static int | |
c86c27af | 2180 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2181 | { |
5716833c MK |
2182 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2183 | int mmxreg, fpreg; | |
28fc6740 AC |
2184 | ULONGEST fstat; |
2185 | int tos; | |
c86c27af | 2186 | |
5716833c | 2187 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2188 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2189 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2190 | fpreg = (mmxreg + tos) % 8; |
2191 | ||
20a6ec49 | 2192 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2193 | } |
2194 | ||
2195 | static void | |
2196 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2197 | int regnum, gdb_byte *buf) |
28fc6740 | 2198 | { |
5716833c | 2199 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2200 | { |
63c0089f | 2201 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2202 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2203 | ||
28fc6740 | 2204 | /* Extract (always little endian). */ |
c86c27af | 2205 | regcache_raw_read (regcache, fpnum, mmx_buf); |
f837910f | 2206 | memcpy (buf, mmx_buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2207 | } |
2208 | else | |
2209 | regcache_raw_read (regcache, regnum, buf); | |
2210 | } | |
2211 | ||
2212 | static void | |
2213 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2214 | int regnum, const gdb_byte *buf) |
28fc6740 | 2215 | { |
5716833c | 2216 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2217 | { |
63c0089f | 2218 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2219 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2220 | ||
28fc6740 AC |
2221 | /* Read ... */ |
2222 | regcache_raw_read (regcache, fpnum, mmx_buf); | |
2223 | /* ... Modify ... (always little endian). */ | |
f837910f | 2224 | memcpy (mmx_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2225 | /* ... Write. */ |
2226 | regcache_raw_write (regcache, fpnum, mmx_buf); | |
2227 | } | |
2228 | else | |
2229 | regcache_raw_write (regcache, regnum, buf); | |
2230 | } | |
ff2e87ac AC |
2231 | \f |
2232 | ||
ff2e87ac AC |
2233 | /* Return the register number of the register allocated by GCC after |
2234 | REGNUM, or -1 if there is no such register. */ | |
2235 | ||
2236 | static int | |
2237 | i386_next_regnum (int regnum) | |
2238 | { | |
2239 | /* GCC allocates the registers in the order: | |
2240 | ||
2241 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2242 | ||
2243 | Since storing a variable in %esp doesn't make any sense we return | |
2244 | -1 for %ebp and for %esp itself. */ | |
2245 | static int next_regnum[] = | |
2246 | { | |
2247 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2248 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2249 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2250 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2251 | -1, -1, /* Slots for %esp and %ebp. */ | |
2252 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2253 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2254 | }; | |
2255 | ||
de5b9bb9 | 2256 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2257 | return next_regnum[regnum]; |
28fc6740 | 2258 | |
ff2e87ac AC |
2259 | return -1; |
2260 | } | |
2261 | ||
2262 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2263 | needs any special handling. */ | |
d7a0d72c | 2264 | |
3a1e71e3 | 2265 | static int |
0abe36f5 | 2266 | i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
d7a0d72c | 2267 | { |
de5b9bb9 MK |
2268 | int len = TYPE_LENGTH (type); |
2269 | ||
ff2e87ac AC |
2270 | /* Values may be spread across multiple registers. Most debugging |
2271 | formats aren't expressive enough to specify the locations, so | |
2272 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2273 | have a length that is a multiple of the word size, since GCC |
2274 | doesn't seem to put any other types into registers. */ | |
2275 | if (len > 4 && len % 4 == 0) | |
2276 | { | |
2277 | int last_regnum = regnum; | |
2278 | ||
2279 | while (len > 4) | |
2280 | { | |
2281 | last_regnum = i386_next_regnum (last_regnum); | |
2282 | len -= 4; | |
2283 | } | |
2284 | ||
2285 | if (last_regnum != -1) | |
2286 | return 1; | |
2287 | } | |
ff2e87ac | 2288 | |
0abe36f5 | 2289 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2290 | } |
2291 | ||
ff2e87ac AC |
2292 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2293 | return its contents in TO. */ | |
ac27f131 | 2294 | |
3a1e71e3 | 2295 | static void |
ff2e87ac | 2296 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 2297 | struct type *type, gdb_byte *to) |
ac27f131 | 2298 | { |
20a6ec49 | 2299 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2300 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2301 | |
ff2e87ac AC |
2302 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
2303 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 2304 | |
20a6ec49 | 2305 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8d7f6b4a | 2306 | { |
d532c08f MK |
2307 | i387_register_to_value (frame, regnum, type, to); |
2308 | return; | |
8d7f6b4a | 2309 | } |
ff2e87ac | 2310 | |
fd35795f | 2311 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2312 | |
2313 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2314 | |
de5b9bb9 MK |
2315 | while (len > 0) |
2316 | { | |
2317 | gdb_assert (regnum != -1); | |
20a6ec49 | 2318 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 2319 | |
42835c2b | 2320 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
2321 | regnum = i386_next_regnum (regnum); |
2322 | len -= 4; | |
42835c2b | 2323 | to += 4; |
de5b9bb9 | 2324 | } |
ac27f131 MK |
2325 | } |
2326 | ||
ff2e87ac AC |
2327 | /* Write the contents FROM of a value of type TYPE into register |
2328 | REGNUM in frame FRAME. */ | |
ac27f131 | 2329 | |
3a1e71e3 | 2330 | static void |
ff2e87ac | 2331 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 2332 | struct type *type, const gdb_byte *from) |
ac27f131 | 2333 | { |
de5b9bb9 | 2334 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2335 | |
20a6ec49 | 2336 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 2337 | { |
d532c08f MK |
2338 | i387_value_to_register (frame, regnum, type, from); |
2339 | return; | |
2340 | } | |
3d261580 | 2341 | |
fd35795f | 2342 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
2343 | |
2344 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 2345 | |
de5b9bb9 MK |
2346 | while (len > 0) |
2347 | { | |
2348 | gdb_assert (regnum != -1); | |
875f8d0e | 2349 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 2350 | |
42835c2b | 2351 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
2352 | regnum = i386_next_regnum (regnum); |
2353 | len -= 4; | |
42835c2b | 2354 | from += 4; |
de5b9bb9 | 2355 | } |
ac27f131 | 2356 | } |
ff2e87ac | 2357 | \f |
7fdafb5a MK |
2358 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
2359 | in the general-purpose register set REGSET to register cache | |
2360 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 2361 | |
20187ed5 | 2362 | void |
473f17b0 MK |
2363 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
2364 | int regnum, const void *gregs, size_t len) | |
2365 | { | |
9ea75c57 | 2366 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 2367 | const gdb_byte *regs = gregs; |
473f17b0 MK |
2368 | int i; |
2369 | ||
2370 | gdb_assert (len == tdep->sizeof_gregset); | |
2371 | ||
2372 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2373 | { | |
2374 | if ((regnum == i || regnum == -1) | |
2375 | && tdep->gregset_reg_offset[i] != -1) | |
2376 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2377 | } | |
2378 | } | |
2379 | ||
7fdafb5a MK |
2380 | /* Collect register REGNUM from the register cache REGCACHE and store |
2381 | it in the buffer specified by GREGS and LEN as described by the | |
2382 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
2383 | all registers in REGSET. */ | |
2384 | ||
2385 | void | |
2386 | i386_collect_gregset (const struct regset *regset, | |
2387 | const struct regcache *regcache, | |
2388 | int regnum, void *gregs, size_t len) | |
2389 | { | |
2390 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 2391 | gdb_byte *regs = gregs; |
7fdafb5a MK |
2392 | int i; |
2393 | ||
2394 | gdb_assert (len == tdep->sizeof_gregset); | |
2395 | ||
2396 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2397 | { | |
2398 | if ((regnum == i || regnum == -1) | |
2399 | && tdep->gregset_reg_offset[i] != -1) | |
2400 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2401 | } | |
2402 | } | |
2403 | ||
2404 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
2405 | in the floating-point register set REGSET to register cache | |
2406 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2407 | |
2408 | static void | |
2409 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
2410 | int regnum, const void *fpregs, size_t len) | |
2411 | { | |
9ea75c57 | 2412 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 2413 | |
66a72d25 MK |
2414 | if (len == I387_SIZEOF_FXSAVE) |
2415 | { | |
2416 | i387_supply_fxsave (regcache, regnum, fpregs); | |
2417 | return; | |
2418 | } | |
2419 | ||
473f17b0 MK |
2420 | gdb_assert (len == tdep->sizeof_fpregset); |
2421 | i387_supply_fsave (regcache, regnum, fpregs); | |
2422 | } | |
8446b36a | 2423 | |
2f305df1 MK |
2424 | /* Collect register REGNUM from the register cache REGCACHE and store |
2425 | it in the buffer specified by FPREGS and LEN as described by the | |
2426 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2427 | all registers in REGSET. */ | |
7fdafb5a MK |
2428 | |
2429 | static void | |
2430 | i386_collect_fpregset (const struct regset *regset, | |
2431 | const struct regcache *regcache, | |
2432 | int regnum, void *fpregs, size_t len) | |
2433 | { | |
2434 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2435 | ||
2436 | if (len == I387_SIZEOF_FXSAVE) | |
2437 | { | |
2438 | i387_collect_fxsave (regcache, regnum, fpregs); | |
2439 | return; | |
2440 | } | |
2441 | ||
2442 | gdb_assert (len == tdep->sizeof_fpregset); | |
2443 | i387_collect_fsave (regcache, regnum, fpregs); | |
2444 | } | |
2445 | ||
8446b36a MK |
2446 | /* Return the appropriate register set for the core section identified |
2447 | by SECT_NAME and SECT_SIZE. */ | |
2448 | ||
2449 | const struct regset * | |
2450 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
2451 | const char *sect_name, size_t sect_size) | |
2452 | { | |
2453 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2454 | ||
2455 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
2456 | { | |
2457 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
2458 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
2459 | i386_collect_gregset); | |
8446b36a MK |
2460 | return tdep->gregset; |
2461 | } | |
2462 | ||
66a72d25 MK |
2463 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
2464 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
2465 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
2466 | { |
2467 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
2468 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
2469 | i386_collect_fpregset); | |
8446b36a MK |
2470 | return tdep->fpregset; |
2471 | } | |
2472 | ||
2473 | return NULL; | |
2474 | } | |
473f17b0 | 2475 | \f |
fc338970 | 2476 | |
fc338970 | 2477 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
2478 | |
2479 | CORE_ADDR | |
e17a4113 UW |
2480 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
2481 | CORE_ADDR pc, char *name) | |
c906108c | 2482 | { |
e17a4113 UW |
2483 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2484 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2485 | ||
2486 | /* jmp *(dest) */ | |
2487 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 2488 | { |
e17a4113 UW |
2489 | unsigned long indirect = |
2490 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 2491 | struct minimal_symbol *indsym = |
fc338970 | 2492 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 2493 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 2494 | |
c5aa993b | 2495 | if (symname) |
c906108c | 2496 | { |
c5aa993b JM |
2497 | if (strncmp (symname, "__imp_", 6) == 0 |
2498 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
2499 | return name ? 1 : |
2500 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
2501 | } |
2502 | } | |
fc338970 | 2503 | return 0; /* Not a trampoline. */ |
c906108c | 2504 | } |
fc338970 MK |
2505 | \f |
2506 | ||
10458914 DJ |
2507 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
2508 | routine. */ | |
8201327c | 2509 | |
4bd207ef | 2510 | int |
10458914 | 2511 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 2512 | { |
10458914 | 2513 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2514 | char *name; |
2515 | ||
2516 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
2517 | return (name && strcmp ("_sigtramp", name) == 0); |
2518 | } | |
2519 | \f | |
2520 | ||
fc338970 MK |
2521 | /* We have two flavours of disassembly. The machinery on this page |
2522 | deals with switching between those. */ | |
c906108c SS |
2523 | |
2524 | static int | |
a89aa300 | 2525 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 2526 | { |
5e3397bb MK |
2527 | gdb_assert (disassembly_flavor == att_flavor |
2528 | || disassembly_flavor == intel_flavor); | |
2529 | ||
2530 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
2531 | constified, cast to prevent a compiler warning. */ | |
2532 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
2533 | |
2534 | return print_insn_i386 (pc, info); | |
7a292a7a | 2535 | } |
fc338970 | 2536 | \f |
3ce1502b | 2537 | |
8201327c MK |
2538 | /* There are a few i386 architecture variants that differ only |
2539 | slightly from the generic i386 target. For now, we don't give them | |
2540 | their own source file, but include them here. As a consequence, | |
2541 | they'll always be included. */ | |
3ce1502b | 2542 | |
8201327c | 2543 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2544 | |
10458914 DJ |
2545 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
2546 | routine. */ | |
911bc6ee | 2547 | |
8201327c | 2548 | static int |
10458914 | 2549 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 2550 | { |
10458914 | 2551 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2552 | char *name; |
2553 | ||
acd5c798 MK |
2554 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
2555 | currently unknown. */ | |
911bc6ee | 2556 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
2557 | return (name && (strcmp ("_sigreturn", name) == 0 |
2558 | || strcmp ("_sigacthandler", name) == 0 | |
2559 | || strcmp ("sigvechandler", name) == 0)); | |
2560 | } | |
d2a7c97a | 2561 | |
10458914 DJ |
2562 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
2563 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 2564 | |
3a1e71e3 | 2565 | static CORE_ADDR |
10458914 | 2566 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 2567 | { |
e17a4113 UW |
2568 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2569 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 2570 | gdb_byte buf[4]; |
acd5c798 | 2571 | CORE_ADDR sp; |
3ce1502b | 2572 | |
10458914 | 2573 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2574 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 2575 | |
e17a4113 | 2576 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c MK |
2577 | } |
2578 | \f | |
3ce1502b | 2579 | |
8201327c | 2580 | /* Generic ELF. */ |
d2a7c97a | 2581 | |
8201327c MK |
2582 | void |
2583 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2584 | { | |
c4fc7f1b MK |
2585 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2586 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2587 | } |
3ce1502b | 2588 | |
8201327c | 2589 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2590 | |
8201327c MK |
2591 | void |
2592 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2593 | { | |
2594 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2595 | |
8201327c MK |
2596 | /* System V Release 4 uses ELF. */ |
2597 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2598 | |
dfe01d39 | 2599 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2600 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2601 | ||
911bc6ee | 2602 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2603 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
2604 | tdep->sc_pc_offset = 36 + 14 * 4; |
2605 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 2606 | |
8201327c | 2607 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
2608 | } |
2609 | ||
8201327c | 2610 | /* DJGPP. */ |
3ce1502b | 2611 | |
3a1e71e3 | 2612 | static void |
8201327c | 2613 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2614 | { |
8201327c | 2615 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2616 | |
911bc6ee MK |
2617 | /* DJGPP doesn't have any special frames for signal handlers. */ |
2618 | tdep->sigtramp_p = NULL; | |
3ce1502b | 2619 | |
8201327c | 2620 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
2621 | |
2622 | /* DJGPP does not support the SSE registers. */ | |
2623 | tdep->num_xmm_regs = 0; | |
90884b2b | 2624 | set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I387_NUM_REGS); |
3d22076f EZ |
2625 | |
2626 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
2627 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
2628 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
2629 | set_gdbarch_sdb_reg_to_regnum. */ | |
2630 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
2631 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3ce1502b | 2632 | } |
8201327c | 2633 | \f |
2acceee2 | 2634 | |
38c968cf AC |
2635 | /* i386 register groups. In addition to the normal groups, add "mmx" |
2636 | and "sse". */ | |
2637 | ||
2638 | static struct reggroup *i386_sse_reggroup; | |
2639 | static struct reggroup *i386_mmx_reggroup; | |
2640 | ||
2641 | static void | |
2642 | i386_init_reggroups (void) | |
2643 | { | |
2644 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
2645 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
2646 | } | |
2647 | ||
2648 | static void | |
2649 | i386_add_reggroups (struct gdbarch *gdbarch) | |
2650 | { | |
2651 | reggroup_add (gdbarch, i386_sse_reggroup); | |
2652 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
2653 | reggroup_add (gdbarch, general_reggroup); | |
2654 | reggroup_add (gdbarch, float_reggroup); | |
2655 | reggroup_add (gdbarch, all_reggroup); | |
2656 | reggroup_add (gdbarch, save_reggroup); | |
2657 | reggroup_add (gdbarch, restore_reggroup); | |
2658 | reggroup_add (gdbarch, vector_reggroup); | |
2659 | reggroup_add (gdbarch, system_reggroup); | |
2660 | } | |
2661 | ||
2662 | int | |
2663 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2664 | struct reggroup *group) | |
2665 | { | |
5716833c MK |
2666 | int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) |
2667 | || i386_mxcsr_regnum_p (gdbarch, regnum)); | |
20a6ec49 MD |
2668 | int fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) |
2669 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
5716833c | 2670 | int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum)); |
acd5c798 | 2671 | |
38c968cf AC |
2672 | if (group == i386_mmx_reggroup) |
2673 | return mmx_regnum_p; | |
2674 | if (group == i386_sse_reggroup) | |
2675 | return sse_regnum_p; | |
2676 | if (group == vector_reggroup) | |
2677 | return (mmx_regnum_p || sse_regnum_p); | |
2678 | if (group == float_reggroup) | |
2679 | return fp_regnum_p; | |
2680 | if (group == general_reggroup) | |
2681 | return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p); | |
acd5c798 | 2682 | |
38c968cf AC |
2683 | return default_register_reggroup_p (gdbarch, regnum, group); |
2684 | } | |
38c968cf | 2685 | \f |
acd5c798 | 2686 | |
f837910f MK |
2687 | /* Get the ARGIth function argument for the current function. */ |
2688 | ||
42c466d7 | 2689 | static CORE_ADDR |
143985b7 AF |
2690 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
2691 | struct type *type) | |
2692 | { | |
e17a4113 UW |
2693 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2694 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f837910f | 2695 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 2696 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
2697 | } |
2698 | ||
514f746b AR |
2699 | static void |
2700 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
2701 | { | |
2702 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
2703 | ||
2704 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
2705 | adjust the PC in the regcache. */ | |
2706 | current_pc += 1; | |
2707 | regcache_write_pc (regcache, current_pc); | |
2708 | } | |
2709 | ||
2710 | ||
7ad10968 HZ |
2711 | #define PREFIX_REPZ 0x01 |
2712 | #define PREFIX_REPNZ 0x02 | |
2713 | #define PREFIX_LOCK 0x04 | |
2714 | #define PREFIX_DATA 0x08 | |
2715 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 2716 | |
7ad10968 HZ |
2717 | /* operand size */ |
2718 | enum | |
2719 | { | |
2720 | OT_BYTE = 0, | |
2721 | OT_WORD, | |
2722 | OT_LONG, | |
cf648174 | 2723 | OT_QUAD, |
7ad10968 | 2724 | }; |
473f17b0 | 2725 | |
7ad10968 HZ |
2726 | /* i386 arith/logic operations */ |
2727 | enum | |
2728 | { | |
2729 | OP_ADDL, | |
2730 | OP_ORL, | |
2731 | OP_ADCL, | |
2732 | OP_SBBL, | |
2733 | OP_ANDL, | |
2734 | OP_SUBL, | |
2735 | OP_XORL, | |
2736 | OP_CMPL, | |
2737 | }; | |
5716833c | 2738 | |
7ad10968 HZ |
2739 | struct i386_record_s |
2740 | { | |
cf648174 | 2741 | struct gdbarch *gdbarch; |
7ad10968 | 2742 | struct regcache *regcache; |
df61f520 | 2743 | CORE_ADDR orig_addr; |
7ad10968 HZ |
2744 | CORE_ADDR addr; |
2745 | int aflag; | |
2746 | int dflag; | |
2747 | int override; | |
2748 | uint8_t modrm; | |
2749 | uint8_t mod, reg, rm; | |
2750 | int ot; | |
cf648174 HZ |
2751 | uint8_t rex_x; |
2752 | uint8_t rex_b; | |
2753 | int rip_offset; | |
2754 | int popl_esp_hack; | |
2755 | const int *regmap; | |
7ad10968 | 2756 | }; |
5716833c | 2757 | |
7ad10968 HZ |
2758 | /* Parse "modrm" part in current memory address that irp->addr point to |
2759 | Return -1 if something wrong. */ | |
5716833c | 2760 | |
7ad10968 HZ |
2761 | static int |
2762 | i386_record_modrm (struct i386_record_s *irp) | |
2763 | { | |
cf648174 | 2764 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 2765 | |
7ad10968 HZ |
2766 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
2767 | { | |
2768 | if (record_debug) | |
2769 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
2770 | "addr %s len = 1.\n"), |
2771 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2772 | return -1; |
2773 | } | |
2774 | irp->addr++; | |
2775 | irp->mod = (irp->modrm >> 6) & 3; | |
2776 | irp->reg = (irp->modrm >> 3) & 7; | |
2777 | irp->rm = irp->modrm & 7; | |
5716833c | 2778 | |
7ad10968 HZ |
2779 | return 0; |
2780 | } | |
d2a7c97a | 2781 | |
7ad10968 HZ |
2782 | /* Get the memory address that current instruction write to and set it to |
2783 | the argument "addr". | |
2784 | Return -1 if something wrong. */ | |
8201327c | 2785 | |
7ad10968 | 2786 | static int |
cf648174 | 2787 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 2788 | { |
cf648174 | 2789 | struct gdbarch *gdbarch = irp->gdbarch; |
7ad10968 | 2790 | uint8_t tmpu8; |
cf648174 HZ |
2791 | int16_t tmpi16; |
2792 | int32_t tmpi32; | |
2793 | ULONGEST tmpulongest; | |
21d0e8a4 | 2794 | |
7ad10968 HZ |
2795 | *addr = 0; |
2796 | if (irp->aflag) | |
2797 | { | |
2798 | /* 32 bits */ | |
2799 | int havesib = 0; | |
2800 | uint8_t scale = 0; | |
2801 | uint8_t index = 0; | |
2802 | uint8_t base = irp->rm; | |
896fb97d | 2803 | |
7ad10968 HZ |
2804 | if (base == 4) |
2805 | { | |
2806 | havesib = 1; | |
2807 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
2808 | { | |
2809 | if (record_debug) | |
2810 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2811 | "at addr %s len = 1.\n"), |
2812 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2813 | return -1; |
2814 | } | |
2815 | irp->addr++; | |
2816 | scale = (tmpu8 >> 6) & 3; | |
cf648174 | 2817 | index = ((tmpu8 >> 3) & 7) | irp->rex_x; |
7ad10968 HZ |
2818 | base = (tmpu8 & 7); |
2819 | } | |
cf648174 | 2820 | base |= irp->rex_b; |
21d0e8a4 | 2821 | |
7ad10968 HZ |
2822 | switch (irp->mod) |
2823 | { | |
2824 | case 0: | |
2825 | if ((base & 7) == 5) | |
2826 | { | |
2827 | base = 0xff; | |
cf648174 | 2828 | if (target_read_memory (irp->addr, (gdb_byte *) &tmpi32, 4)) |
7ad10968 HZ |
2829 | { |
2830 | if (record_debug) | |
2831 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
2832 | "memory at addr %s len = 4.\n"), |
2833 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2834 | return -1; |
2835 | } | |
2836 | irp->addr += 4; | |
cf648174 HZ |
2837 | *addr = tmpi32; |
2838 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) | |
2839 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 HZ |
2840 | } |
2841 | else | |
2842 | { | |
2843 | *addr = 0; | |
2844 | } | |
2845 | break; | |
2846 | case 1: | |
2847 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
2848 | { | |
2849 | if (record_debug) | |
2850 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2851 | "at addr %s len = 1.\n"), |
2852 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2853 | return -1; |
2854 | } | |
2855 | irp->addr++; | |
2856 | *addr = (int8_t) tmpu8; | |
2857 | break; | |
2858 | case 2: | |
cf648174 | 2859 | if (target_read_memory (irp->addr, (gdb_byte *) &tmpi32, 4)) |
7ad10968 HZ |
2860 | { |
2861 | if (record_debug) | |
2862 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2863 | "at addr %s len = 4.\n"), |
2864 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2865 | return -1; |
2866 | } | |
cf648174 | 2867 | *addr = tmpi32; |
7ad10968 HZ |
2868 | irp->addr += 4; |
2869 | break; | |
2870 | } | |
356a6b3e | 2871 | |
cf648174 | 2872 | tmpulongest = 0; |
7ad10968 | 2873 | if (base != 0xff) |
cf648174 HZ |
2874 | { |
2875 | if (base == 4 && irp->popl_esp_hack) | |
2876 | *addr += irp->popl_esp_hack; | |
2877 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
2878 | &tmpulongest); | |
7ad10968 | 2879 | } |
cf648174 HZ |
2880 | if (irp->aflag == 2) |
2881 | { | |
2882 | *addr += tmpulongest; | |
2883 | } | |
2884 | else | |
2885 | *addr = (uint32_t) (tmpulongest + *addr); | |
c4fc7f1b | 2886 | |
7ad10968 HZ |
2887 | if (havesib && (index != 4 || scale != 0)) |
2888 | { | |
cf648174 HZ |
2889 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
2890 | &tmpulongest); | |
2891 | if (irp->aflag == 2) | |
2892 | *addr += tmpulongest << scale; | |
2893 | else | |
2894 | *addr = (uint32_t) (*addr + (tmpulongest << scale)); | |
7ad10968 HZ |
2895 | } |
2896 | } | |
2897 | else | |
2898 | { | |
2899 | /* 16 bits */ | |
2900 | switch (irp->mod) | |
2901 | { | |
2902 | case 0: | |
2903 | if (irp->rm == 6) | |
2904 | { | |
2905 | if (target_read_memory | |
cf648174 | 2906 | (irp->addr, (gdb_byte *) &tmpi16, 2)) |
7ad10968 HZ |
2907 | { |
2908 | if (record_debug) | |
2909 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
2910 | "memory at addr %s len = 2.\n"), |
2911 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2912 | return -1; |
2913 | } | |
2914 | irp->addr += 2; | |
cf648174 | 2915 | *addr = tmpi16; |
7ad10968 HZ |
2916 | irp->rm = 0; |
2917 | goto no_rm; | |
2918 | } | |
2919 | else | |
2920 | { | |
2921 | *addr = 0; | |
2922 | } | |
2923 | break; | |
2924 | case 1: | |
2925 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
2926 | { | |
2927 | if (record_debug) | |
2928 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2929 | "at addr %s len = 1.\n"), |
2930 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2931 | return -1; |
2932 | } | |
2933 | irp->addr++; | |
2934 | *addr = (int8_t) tmpu8; | |
2935 | break; | |
2936 | case 2: | |
cf648174 | 2937 | if (target_read_memory (irp->addr, (gdb_byte *) &tmpi16, 2)) |
7ad10968 HZ |
2938 | { |
2939 | if (record_debug) | |
2940 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2941 | "at addr %s len = 2.\n"), |
2942 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2943 | return -1; |
2944 | } | |
2945 | irp->addr += 2; | |
cf648174 | 2946 | *addr = tmpi16; |
7ad10968 HZ |
2947 | break; |
2948 | } | |
c4fc7f1b | 2949 | |
7ad10968 HZ |
2950 | switch (irp->rm) |
2951 | { | |
2952 | case 0: | |
cf648174 HZ |
2953 | regcache_raw_read_unsigned (irp->regcache, |
2954 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
2955 | &tmpulongest); | |
2956 | *addr = (uint32_t) (*addr + tmpulongest); | |
2957 | regcache_raw_read_unsigned (irp->regcache, | |
2958 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
2959 | &tmpulongest); | |
2960 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
2961 | break; |
2962 | case 1: | |
cf648174 HZ |
2963 | regcache_raw_read_unsigned (irp->regcache, |
2964 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
2965 | &tmpulongest); | |
2966 | *addr = (uint32_t) (*addr + tmpulongest); | |
2967 | regcache_raw_read_unsigned (irp->regcache, | |
2968 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
2969 | &tmpulongest); | |
2970 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
2971 | break; |
2972 | case 2: | |
cf648174 HZ |
2973 | regcache_raw_read_unsigned (irp->regcache, |
2974 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
2975 | &tmpulongest); | |
2976 | *addr = (uint32_t) (*addr + tmpulongest); | |
2977 | regcache_raw_read_unsigned (irp->regcache, | |
2978 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
2979 | &tmpulongest); | |
2980 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
2981 | break; |
2982 | case 3: | |
cf648174 HZ |
2983 | regcache_raw_read_unsigned (irp->regcache, |
2984 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
2985 | &tmpulongest); | |
2986 | *addr = (uint32_t) (*addr + tmpulongest); | |
2987 | regcache_raw_read_unsigned (irp->regcache, | |
2988 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
2989 | &tmpulongest); | |
2990 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
2991 | break; |
2992 | case 4: | |
cf648174 HZ |
2993 | regcache_raw_read_unsigned (irp->regcache, |
2994 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
2995 | &tmpulongest); | |
2996 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
2997 | break; |
2998 | case 5: | |
cf648174 HZ |
2999 | regcache_raw_read_unsigned (irp->regcache, |
3000 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
3001 | &tmpulongest); | |
3002 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3003 | break; |
3004 | case 6: | |
cf648174 HZ |
3005 | regcache_raw_read_unsigned (irp->regcache, |
3006 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
3007 | &tmpulongest); | |
3008 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3009 | break; |
3010 | case 7: | |
cf648174 HZ |
3011 | regcache_raw_read_unsigned (irp->regcache, |
3012 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
3013 | &tmpulongest); | |
3014 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3015 | break; |
3016 | } | |
3017 | *addr &= 0xffff; | |
3018 | } | |
c4fc7f1b | 3019 | |
01fe1b41 | 3020 | no_rm: |
7ad10968 HZ |
3021 | return 0; |
3022 | } | |
c4fc7f1b | 3023 | |
7ad10968 HZ |
3024 | /* Record the value of the memory that willbe changed in current instruction |
3025 | to "record_arch_list". | |
3026 | Return -1 if something wrong. */ | |
356a6b3e | 3027 | |
7ad10968 HZ |
3028 | static int |
3029 | i386_record_lea_modrm (struct i386_record_s *irp) | |
3030 | { | |
cf648174 HZ |
3031 | struct gdbarch *gdbarch = irp->gdbarch; |
3032 | uint64_t addr; | |
356a6b3e | 3033 | |
d7877f7e | 3034 | if (irp->override >= 0) |
7ad10968 | 3035 | { |
df61f520 HZ |
3036 | warning (_("Process record ignores the memory change " |
3037 | "of instruction at address %s because it " | |
3038 | "can't get the value of the segment register."), | |
3039 | paddress (gdbarch, irp->orig_addr)); | |
7ad10968 HZ |
3040 | return 0; |
3041 | } | |
61113f8b | 3042 | |
7ad10968 HZ |
3043 | if (i386_record_lea_modrm_addr (irp, &addr)) |
3044 | return -1; | |
96297dab | 3045 | |
7ad10968 HZ |
3046 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
3047 | return -1; | |
a62cc96e | 3048 | |
7ad10968 HZ |
3049 | return 0; |
3050 | } | |
b6197528 | 3051 | |
cf648174 HZ |
3052 | /* Record the push operation to "record_arch_list". |
3053 | Return -1 if something wrong. */ | |
3054 | ||
3055 | static int | |
3056 | i386_record_push (struct i386_record_s *irp, int size) | |
3057 | { | |
3058 | ULONGEST tmpulongest; | |
3059 | ||
3060 | if (record_arch_list_add_reg (irp->regcache, | |
3061 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
3062 | return -1; | |
3063 | regcache_raw_read_unsigned (irp->regcache, | |
3064 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
3065 | &tmpulongest); | |
3066 | if (record_arch_list_add_mem ((CORE_ADDR) tmpulongest - size, size)) | |
3067 | return -1; | |
3068 | ||
3069 | return 0; | |
3070 | } | |
3071 | ||
0289bdd7 MS |
3072 | |
3073 | /* Defines contents to record. */ | |
3074 | #define I386_SAVE_FPU_REGS 0xfffd | |
3075 | #define I386_SAVE_FPU_ENV 0xfffe | |
3076 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
3077 | ||
3078 | /* Record the value of floating point registers which will be changed by the | |
3079 | current instruction to "record_arch_list". Return -1 if something is wrong. | |
3080 | */ | |
3081 | ||
3082 | static int i386_record_floats (struct gdbarch *gdbarch, | |
3083 | struct i386_record_s *ir, | |
3084 | uint32_t iregnum) | |
3085 | { | |
3086 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3087 | int i; | |
3088 | ||
3089 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
3090 | happen. Currently we store st0-st7 registers, but we need not store all | |
3091 | registers all the time, in future we use ftag register and record only | |
3092 | those who are not marked as an empty. */ | |
3093 | ||
3094 | if (I386_SAVE_FPU_REGS == iregnum) | |
3095 | { | |
3096 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
3097 | { | |
3098 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3099 | return -1; | |
3100 | } | |
3101 | } | |
3102 | else if (I386_SAVE_FPU_ENV == iregnum) | |
3103 | { | |
3104 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3105 | { | |
3106 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3107 | return -1; | |
3108 | } | |
3109 | } | |
3110 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
3111 | { | |
3112 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3113 | { | |
3114 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3115 | return -1; | |
3116 | } | |
3117 | } | |
3118 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
3119 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
3120 | { | |
3121 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
3122 | return -1; | |
3123 | } | |
3124 | else | |
3125 | { | |
3126 | /* Parameter error. */ | |
3127 | return -1; | |
3128 | } | |
3129 | if(I386_SAVE_FPU_ENV != iregnum) | |
3130 | { | |
3131 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3132 | { | |
3133 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3134 | return -1; | |
3135 | } | |
3136 | } | |
3137 | return 0; | |
3138 | } | |
3139 | ||
7ad10968 HZ |
3140 | /* Parse the current instruction and record the values of the registers and |
3141 | memory that will be changed in current instruction to "record_arch_list". | |
3142 | Return -1 if something wrong. */ | |
8201327c | 3143 | |
cf648174 HZ |
3144 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
3145 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
3146 | ||
a6b808b4 | 3147 | int |
7ad10968 HZ |
3148 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
3149 | CORE_ADDR addr) | |
3150 | { | |
3151 | int prefixes = 0; | |
3152 | uint8_t tmpu8; | |
3153 | uint16_t tmpu16; | |
3154 | uint32_t tmpu32; | |
cf648174 | 3155 | ULONGEST tmpulongest; |
7ad10968 HZ |
3156 | uint32_t opcode; |
3157 | struct i386_record_s ir; | |
0289bdd7 | 3158 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
3159 | int rex = 0; |
3160 | uint8_t rex_w = -1; | |
3161 | uint8_t rex_r = 0; | |
7ad10968 | 3162 | |
8408d274 | 3163 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 HZ |
3164 | ir.regcache = regcache; |
3165 | ir.addr = addr; | |
df61f520 | 3166 | ir.orig_addr = addr; |
7ad10968 HZ |
3167 | ir.aflag = 1; |
3168 | ir.dflag = 1; | |
cf648174 HZ |
3169 | ir.override = -1; |
3170 | ir.popl_esp_hack = 0; | |
3171 | ir.regmap = gdbarch_tdep (gdbarch)->record_regmap; | |
3172 | ir.gdbarch = gdbarch; | |
7ad10968 HZ |
3173 | |
3174 | if (record_debug > 1) | |
3175 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
3176 | "addr = %s\n", |
3177 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3178 | |
3179 | /* prefixes */ | |
3180 | while (1) | |
3181 | { | |
3182 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
3183 | { | |
3184 | if (record_debug) | |
3185 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3186 | "addr %s len = 1.\n"), |
3187 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3188 | return -1; |
3189 | } | |
3190 | ir.addr++; | |
01fe1b41 | 3191 | switch (tmpu8) /* Instruction prefixes */ |
7ad10968 | 3192 | { |
01fe1b41 | 3193 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
3194 | prefixes |= PREFIX_REPZ; |
3195 | break; | |
01fe1b41 | 3196 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
3197 | prefixes |= PREFIX_REPNZ; |
3198 | break; | |
01fe1b41 | 3199 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
3200 | prefixes |= PREFIX_LOCK; |
3201 | break; | |
01fe1b41 | 3202 | case CS_PREFIX_OPCODE: |
cf648174 | 3203 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 3204 | break; |
01fe1b41 | 3205 | case SS_PREFIX_OPCODE: |
cf648174 | 3206 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 3207 | break; |
01fe1b41 | 3208 | case DS_PREFIX_OPCODE: |
cf648174 | 3209 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 3210 | break; |
01fe1b41 | 3211 | case ES_PREFIX_OPCODE: |
cf648174 | 3212 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 3213 | break; |
01fe1b41 | 3214 | case FS_PREFIX_OPCODE: |
cf648174 | 3215 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 3216 | break; |
01fe1b41 | 3217 | case GS_PREFIX_OPCODE: |
cf648174 | 3218 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 3219 | break; |
01fe1b41 | 3220 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
3221 | prefixes |= PREFIX_DATA; |
3222 | break; | |
01fe1b41 | 3223 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
3224 | prefixes |= PREFIX_ADDR; |
3225 | break; | |
d691bec7 MS |
3226 | case 0x40: /* i386 inc %eax */ |
3227 | case 0x41: /* i386 inc %ecx */ | |
3228 | case 0x42: /* i386 inc %edx */ | |
3229 | case 0x43: /* i386 inc %ebx */ | |
3230 | case 0x44: /* i386 inc %esp */ | |
3231 | case 0x45: /* i386 inc %ebp */ | |
3232 | case 0x46: /* i386 inc %esi */ | |
3233 | case 0x47: /* i386 inc %edi */ | |
3234 | case 0x48: /* i386 dec %eax */ | |
3235 | case 0x49: /* i386 dec %ecx */ | |
3236 | case 0x4a: /* i386 dec %edx */ | |
3237 | case 0x4b: /* i386 dec %ebx */ | |
3238 | case 0x4c: /* i386 dec %esp */ | |
3239 | case 0x4d: /* i386 dec %ebp */ | |
3240 | case 0x4e: /* i386 dec %esi */ | |
3241 | case 0x4f: /* i386 dec %edi */ | |
3242 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
3243 | { |
3244 | /* REX */ | |
3245 | rex = 1; | |
3246 | rex_w = (tmpu8 >> 3) & 1; | |
3247 | rex_r = (tmpu8 & 0x4) << 1; | |
3248 | ir.rex_x = (tmpu8 & 0x2) << 2; | |
3249 | ir.rex_b = (tmpu8 & 0x1) << 3; | |
3250 | } | |
d691bec7 MS |
3251 | else /* 32 bit target */ |
3252 | goto out_prefixes; | |
cf648174 | 3253 | break; |
7ad10968 HZ |
3254 | default: |
3255 | goto out_prefixes; | |
3256 | break; | |
3257 | } | |
3258 | } | |
01fe1b41 | 3259 | out_prefixes: |
cf648174 HZ |
3260 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
3261 | { | |
3262 | ir.dflag = 2; | |
3263 | } | |
3264 | else | |
3265 | { | |
3266 | if (prefixes & PREFIX_DATA) | |
3267 | ir.dflag ^= 1; | |
3268 | } | |
7ad10968 HZ |
3269 | if (prefixes & PREFIX_ADDR) |
3270 | ir.aflag ^= 1; | |
cf648174 HZ |
3271 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3272 | ir.aflag = 2; | |
7ad10968 HZ |
3273 | |
3274 | /* now check op code */ | |
3275 | opcode = (uint32_t) tmpu8; | |
01fe1b41 | 3276 | reswitch: |
7ad10968 HZ |
3277 | switch (opcode) |
3278 | { | |
3279 | case 0x0f: | |
3280 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
3281 | { | |
3282 | if (record_debug) | |
3283 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3284 | "addr %s len = 1.\n"), |
3285 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3286 | return -1; |
3287 | } | |
3288 | ir.addr++; | |
3289 | opcode = (uint16_t) tmpu8 | 0x0f00; | |
3290 | goto reswitch; | |
3291 | break; | |
93924b6b | 3292 | |
a38bba38 | 3293 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
3294 | case 0x01: |
3295 | case 0x02: | |
3296 | case 0x03: | |
3297 | case 0x04: | |
3298 | case 0x05: | |
3299 | case 0x08: | |
3300 | case 0x09: | |
3301 | case 0x0a: | |
3302 | case 0x0b: | |
3303 | case 0x0c: | |
3304 | case 0x0d: | |
3305 | case 0x10: | |
3306 | case 0x11: | |
3307 | case 0x12: | |
3308 | case 0x13: | |
3309 | case 0x14: | |
3310 | case 0x15: | |
3311 | case 0x18: | |
3312 | case 0x19: | |
3313 | case 0x1a: | |
3314 | case 0x1b: | |
3315 | case 0x1c: | |
3316 | case 0x1d: | |
3317 | case 0x20: | |
3318 | case 0x21: | |
3319 | case 0x22: | |
3320 | case 0x23: | |
3321 | case 0x24: | |
3322 | case 0x25: | |
3323 | case 0x28: | |
3324 | case 0x29: | |
3325 | case 0x2a: | |
3326 | case 0x2b: | |
3327 | case 0x2c: | |
3328 | case 0x2d: | |
3329 | case 0x30: | |
3330 | case 0x31: | |
3331 | case 0x32: | |
3332 | case 0x33: | |
3333 | case 0x34: | |
3334 | case 0x35: | |
3335 | case 0x38: | |
3336 | case 0x39: | |
3337 | case 0x3a: | |
3338 | case 0x3b: | |
3339 | case 0x3c: | |
3340 | case 0x3d: | |
3341 | if (((opcode >> 3) & 7) != OP_CMPL) | |
3342 | { | |
3343 | if ((opcode & 1) == 0) | |
3344 | ir.ot = OT_BYTE; | |
3345 | else | |
3346 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 3347 | |
7ad10968 HZ |
3348 | switch ((opcode >> 1) & 3) |
3349 | { | |
a38bba38 | 3350 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
3351 | if (i386_record_modrm (&ir)) |
3352 | return -1; | |
3353 | if (ir.mod != 3) | |
3354 | { | |
3355 | if (i386_record_lea_modrm (&ir)) | |
3356 | return -1; | |
3357 | } | |
3358 | else | |
3359 | { | |
cf648174 HZ |
3360 | ir.rm |= ir.rex_b; |
3361 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3362 | ir.rm &= 0x3; |
cf648174 | 3363 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3364 | } |
3365 | break; | |
a38bba38 | 3366 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
3367 | if (i386_record_modrm (&ir)) |
3368 | return -1; | |
cf648174 HZ |
3369 | ir.reg |= rex_r; |
3370 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3371 | ir.reg &= 0x3; |
cf648174 | 3372 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3373 | break; |
a38bba38 | 3374 | case 2: /* OP A, Iv */ |
cf648174 | 3375 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3376 | break; |
3377 | } | |
3378 | } | |
cf648174 | 3379 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3380 | break; |
42fdc8df | 3381 | |
a38bba38 | 3382 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
3383 | case 0x81: |
3384 | case 0x82: | |
3385 | case 0x83: | |
3386 | if (i386_record_modrm (&ir)) | |
3387 | return -1; | |
8201327c | 3388 | |
7ad10968 HZ |
3389 | if (ir.reg != OP_CMPL) |
3390 | { | |
3391 | if ((opcode & 1) == 0) | |
3392 | ir.ot = OT_BYTE; | |
3393 | else | |
3394 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 3395 | |
7ad10968 HZ |
3396 | if (ir.mod != 3) |
3397 | { | |
cf648174 HZ |
3398 | if (opcode == 0x83) |
3399 | ir.rip_offset = 1; | |
3400 | else | |
3401 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3402 | if (i386_record_lea_modrm (&ir)) |
3403 | return -1; | |
3404 | } | |
3405 | else | |
cf648174 | 3406 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 3407 | } |
cf648174 | 3408 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3409 | break; |
5e3397bb | 3410 | |
a38bba38 | 3411 | case 0x40: /* inc */ |
7ad10968 HZ |
3412 | case 0x41: |
3413 | case 0x42: | |
3414 | case 0x43: | |
3415 | case 0x44: | |
3416 | case 0x45: | |
3417 | case 0x46: | |
3418 | case 0x47: | |
a38bba38 MS |
3419 | |
3420 | case 0x48: /* dec */ | |
7ad10968 HZ |
3421 | case 0x49: |
3422 | case 0x4a: | |
3423 | case 0x4b: | |
3424 | case 0x4c: | |
3425 | case 0x4d: | |
3426 | case 0x4e: | |
3427 | case 0x4f: | |
a38bba38 | 3428 | |
cf648174 HZ |
3429 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
3430 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 3431 | break; |
acd5c798 | 3432 | |
a38bba38 | 3433 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
3434 | case 0xf7: |
3435 | if ((opcode & 1) == 0) | |
3436 | ir.ot = OT_BYTE; | |
3437 | else | |
3438 | ir.ot = ir.dflag + OT_WORD; | |
3439 | if (i386_record_modrm (&ir)) | |
3440 | return -1; | |
acd5c798 | 3441 | |
cf648174 HZ |
3442 | if (ir.mod != 3 && ir.reg == 0) |
3443 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3444 | ||
7ad10968 HZ |
3445 | switch (ir.reg) |
3446 | { | |
a38bba38 | 3447 | case 0: /* test */ |
cf648174 | 3448 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3449 | break; |
a38bba38 MS |
3450 | case 2: /* not */ |
3451 | case 3: /* neg */ | |
7ad10968 HZ |
3452 | if (ir.mod != 3) |
3453 | { | |
3454 | if (i386_record_lea_modrm (&ir)) | |
3455 | return -1; | |
3456 | } | |
3457 | else | |
3458 | { | |
cf648174 HZ |
3459 | ir.rm |= ir.rex_b; |
3460 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3461 | ir.rm &= 0x3; |
cf648174 | 3462 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3463 | } |
a38bba38 | 3464 | if (ir.reg == 3) /* neg */ |
cf648174 | 3465 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3466 | break; |
a38bba38 MS |
3467 | case 4: /* mul */ |
3468 | case 5: /* imul */ | |
3469 | case 6: /* div */ | |
3470 | case 7: /* idiv */ | |
cf648174 | 3471 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 3472 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
3473 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
3474 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3475 | break; |
3476 | default: | |
3477 | ir.addr -= 2; | |
3478 | opcode = opcode << 8 | ir.modrm; | |
3479 | goto no_support; | |
3480 | break; | |
3481 | } | |
3482 | break; | |
3483 | ||
a38bba38 MS |
3484 | case 0xfe: /* GRP4 */ |
3485 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
3486 | if (i386_record_modrm (&ir)) |
3487 | return -1; | |
3488 | if (ir.reg >= 2 && opcode == 0xfe) | |
3489 | { | |
3490 | ir.addr -= 2; | |
3491 | opcode = opcode << 8 | ir.modrm; | |
3492 | goto no_support; | |
3493 | } | |
7ad10968 HZ |
3494 | switch (ir.reg) |
3495 | { | |
a38bba38 MS |
3496 | case 0: /* inc */ |
3497 | case 1: /* dec */ | |
cf648174 HZ |
3498 | if ((opcode & 1) == 0) |
3499 | ir.ot = OT_BYTE; | |
3500 | else | |
3501 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3502 | if (ir.mod != 3) |
3503 | { | |
3504 | if (i386_record_lea_modrm (&ir)) | |
3505 | return -1; | |
3506 | } | |
3507 | else | |
3508 | { | |
cf648174 HZ |
3509 | ir.rm |= ir.rex_b; |
3510 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3511 | ir.rm &= 0x3; |
cf648174 | 3512 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3513 | } |
cf648174 | 3514 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3515 | break; |
a38bba38 | 3516 | case 2: /* call */ |
cf648174 HZ |
3517 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3518 | ir.dflag = 2; | |
3519 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3520 | return -1; |
cf648174 | 3521 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3522 | break; |
a38bba38 | 3523 | case 3: /* lcall */ |
cf648174 HZ |
3524 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
3525 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3526 | return -1; |
cf648174 | 3527 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3528 | break; |
a38bba38 MS |
3529 | case 4: /* jmp */ |
3530 | case 5: /* ljmp */ | |
cf648174 HZ |
3531 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
3532 | break; | |
a38bba38 | 3533 | case 6: /* push */ |
cf648174 HZ |
3534 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3535 | ir.dflag = 2; | |
3536 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3537 | return -1; | |
7ad10968 HZ |
3538 | break; |
3539 | default: | |
3540 | ir.addr -= 2; | |
3541 | opcode = opcode << 8 | ir.modrm; | |
3542 | goto no_support; | |
3543 | break; | |
3544 | } | |
3545 | break; | |
3546 | ||
a38bba38 | 3547 | case 0x84: /* test */ |
7ad10968 HZ |
3548 | case 0x85: |
3549 | case 0xa8: | |
3550 | case 0xa9: | |
cf648174 | 3551 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3552 | break; |
3553 | ||
a38bba38 | 3554 | case 0x98: /* CWDE/CBW */ |
cf648174 | 3555 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3556 | break; |
3557 | ||
a38bba38 | 3558 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
3559 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3560 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3561 | break; |
3562 | ||
a38bba38 | 3563 | case 0x0faf: /* imul */ |
7ad10968 HZ |
3564 | case 0x69: |
3565 | case 0x6b: | |
3566 | ir.ot = ir.dflag + OT_WORD; | |
3567 | if (i386_record_modrm (&ir)) | |
3568 | return -1; | |
cf648174 HZ |
3569 | if (opcode == 0x69) |
3570 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3571 | else if (opcode == 0x6b) | |
3572 | ir.rip_offset = 1; | |
3573 | ir.reg |= rex_r; | |
3574 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3575 | ir.reg &= 0x3; |
cf648174 HZ |
3576 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3577 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3578 | break; |
3579 | ||
a38bba38 | 3580 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
3581 | case 0x0fc1: |
3582 | if ((opcode & 1) == 0) | |
3583 | ir.ot = OT_BYTE; | |
3584 | else | |
3585 | ir.ot = ir.dflag + OT_WORD; | |
3586 | if (i386_record_modrm (&ir)) | |
3587 | return -1; | |
cf648174 | 3588 | ir.reg |= rex_r; |
7ad10968 HZ |
3589 | if (ir.mod == 3) |
3590 | { | |
cf648174 | 3591 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 3592 | ir.reg &= 0x3; |
cf648174 HZ |
3593 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3594 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3595 | ir.rm &= 0x3; |
cf648174 | 3596 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3597 | } |
3598 | else | |
3599 | { | |
3600 | if (i386_record_lea_modrm (&ir)) | |
3601 | return -1; | |
cf648174 | 3602 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 3603 | ir.reg &= 0x3; |
cf648174 | 3604 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3605 | } |
cf648174 | 3606 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3607 | break; |
3608 | ||
a38bba38 | 3609 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
3610 | case 0x0fb1: |
3611 | if ((opcode & 1) == 0) | |
3612 | ir.ot = OT_BYTE; | |
3613 | else | |
3614 | ir.ot = ir.dflag + OT_WORD; | |
3615 | if (i386_record_modrm (&ir)) | |
3616 | return -1; | |
3617 | if (ir.mod == 3) | |
3618 | { | |
cf648174 HZ |
3619 | ir.reg |= rex_r; |
3620 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
3621 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3622 | ir.reg &= 0x3; |
cf648174 | 3623 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
3624 | } |
3625 | else | |
3626 | { | |
cf648174 | 3627 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3628 | if (i386_record_lea_modrm (&ir)) |
3629 | return -1; | |
3630 | } | |
cf648174 | 3631 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3632 | break; |
3633 | ||
a38bba38 | 3634 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
3635 | if (i386_record_modrm (&ir)) |
3636 | return -1; | |
3637 | if (ir.mod == 3) | |
3638 | { | |
3639 | ir.addr -= 2; | |
3640 | opcode = opcode << 8 | ir.modrm; | |
3641 | goto no_support; | |
3642 | } | |
cf648174 HZ |
3643 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3644 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3645 | if (i386_record_lea_modrm (&ir)) |
3646 | return -1; | |
cf648174 | 3647 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3648 | break; |
3649 | ||
a38bba38 | 3650 | case 0x50: /* push */ |
7ad10968 HZ |
3651 | case 0x51: |
3652 | case 0x52: | |
3653 | case 0x53: | |
3654 | case 0x54: | |
3655 | case 0x55: | |
3656 | case 0x56: | |
3657 | case 0x57: | |
3658 | case 0x68: | |
3659 | case 0x6a: | |
cf648174 HZ |
3660 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3661 | ir.dflag = 2; | |
3662 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3663 | return -1; | |
3664 | break; | |
3665 | ||
a38bba38 MS |
3666 | case 0x06: /* push es */ |
3667 | case 0x0e: /* push cs */ | |
3668 | case 0x16: /* push ss */ | |
3669 | case 0x1e: /* push ds */ | |
cf648174 HZ |
3670 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3671 | { | |
3672 | ir.addr -= 1; | |
3673 | goto no_support; | |
3674 | } | |
3675 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3676 | return -1; | |
3677 | break; | |
3678 | ||
a38bba38 MS |
3679 | case 0x0fa0: /* push fs */ |
3680 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
3681 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3682 | { | |
3683 | ir.addr -= 2; | |
3684 | goto no_support; | |
3685 | } | |
3686 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3687 | return -1; |
cf648174 HZ |
3688 | break; |
3689 | ||
a38bba38 | 3690 | case 0x60: /* pusha */ |
cf648174 HZ |
3691 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3692 | { | |
3693 | ir.addr -= 1; | |
3694 | goto no_support; | |
3695 | } | |
3696 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
3697 | return -1; |
3698 | break; | |
3699 | ||
a38bba38 | 3700 | case 0x58: /* pop */ |
7ad10968 HZ |
3701 | case 0x59: |
3702 | case 0x5a: | |
3703 | case 0x5b: | |
3704 | case 0x5c: | |
3705 | case 0x5d: | |
3706 | case 0x5e: | |
3707 | case 0x5f: | |
cf648174 HZ |
3708 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3709 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
3710 | break; |
3711 | ||
a38bba38 | 3712 | case 0x61: /* popa */ |
cf648174 HZ |
3713 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3714 | { | |
3715 | ir.addr -= 1; | |
3716 | goto no_support; | |
7ad10968 | 3717 | } |
cf648174 HZ |
3718 | for (tmpu8 = X86_RECORD_REAX_REGNUM; tmpu8 <= X86_RECORD_REDI_REGNUM; |
3719 | tmpu8++) | |
3720 | I386_RECORD_ARCH_LIST_ADD_REG (tmpu8); | |
7ad10968 HZ |
3721 | break; |
3722 | ||
a38bba38 | 3723 | case 0x8f: /* pop */ |
cf648174 HZ |
3724 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3725 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
3726 | else | |
3727 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3728 | if (i386_record_modrm (&ir)) |
3729 | return -1; | |
3730 | if (ir.mod == 3) | |
cf648174 | 3731 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
3732 | else |
3733 | { | |
cf648174 | 3734 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
3735 | if (i386_record_lea_modrm (&ir)) |
3736 | return -1; | |
3737 | } | |
cf648174 | 3738 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
3739 | break; |
3740 | ||
a38bba38 | 3741 | case 0xc8: /* enter */ |
cf648174 HZ |
3742 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
3743 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
3744 | ir.dflag = 2; | |
3745 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
3746 | return -1; |
3747 | break; | |
3748 | ||
a38bba38 | 3749 | case 0xc9: /* leave */ |
cf648174 HZ |
3750 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3751 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
3752 | break; |
3753 | ||
a38bba38 | 3754 | case 0x07: /* pop es */ |
cf648174 HZ |
3755 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3756 | { | |
3757 | ir.addr -= 1; | |
3758 | goto no_support; | |
3759 | } | |
3760 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3761 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
3762 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3763 | break; |
3764 | ||
a38bba38 | 3765 | case 0x17: /* pop ss */ |
cf648174 HZ |
3766 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3767 | { | |
3768 | ir.addr -= 1; | |
3769 | goto no_support; | |
3770 | } | |
3771 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3772 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
3773 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3774 | break; |
3775 | ||
a38bba38 | 3776 | case 0x1f: /* pop ds */ |
cf648174 HZ |
3777 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3778 | { | |
3779 | ir.addr -= 1; | |
3780 | goto no_support; | |
3781 | } | |
3782 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3783 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
3784 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3785 | break; |
3786 | ||
a38bba38 | 3787 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
3788 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3789 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
3790 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3791 | break; |
3792 | ||
a38bba38 | 3793 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
3794 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3795 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
3796 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3797 | break; |
3798 | ||
a38bba38 | 3799 | case 0x88: /* mov */ |
7ad10968 HZ |
3800 | case 0x89: |
3801 | case 0xc6: | |
3802 | case 0xc7: | |
3803 | if ((opcode & 1) == 0) | |
3804 | ir.ot = OT_BYTE; | |
3805 | else | |
3806 | ir.ot = ir.dflag + OT_WORD; | |
3807 | ||
3808 | if (i386_record_modrm (&ir)) | |
3809 | return -1; | |
3810 | ||
3811 | if (ir.mod != 3) | |
3812 | { | |
cf648174 HZ |
3813 | if (opcode == 0xc6 || opcode == 0xc7) |
3814 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3815 | if (i386_record_lea_modrm (&ir)) |
3816 | return -1; | |
3817 | } | |
3818 | else | |
3819 | { | |
cf648174 HZ |
3820 | if (opcode == 0xc6 || opcode == 0xc7) |
3821 | ir.rm |= ir.rex_b; | |
3822 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3823 | ir.rm &= 0x3; |
cf648174 | 3824 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3825 | } |
7ad10968 | 3826 | break; |
cf648174 | 3827 | |
a38bba38 | 3828 | case 0x8a: /* mov */ |
7ad10968 HZ |
3829 | case 0x8b: |
3830 | if ((opcode & 1) == 0) | |
3831 | ir.ot = OT_BYTE; | |
3832 | else | |
3833 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3834 | if (i386_record_modrm (&ir)) |
3835 | return -1; | |
cf648174 HZ |
3836 | ir.reg |= rex_r; |
3837 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3838 | ir.reg &= 0x3; |
cf648174 HZ |
3839 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3840 | break; | |
7ad10968 | 3841 | |
a38bba38 | 3842 | case 0x8c: /* mov seg */ |
cf648174 | 3843 | if (i386_record_modrm (&ir)) |
7ad10968 | 3844 | return -1; |
cf648174 HZ |
3845 | if (ir.reg > 5) |
3846 | { | |
3847 | ir.addr -= 2; | |
3848 | opcode = opcode << 8 | ir.modrm; | |
3849 | goto no_support; | |
3850 | } | |
3851 | ||
3852 | if (ir.mod == 3) | |
3853 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
3854 | else | |
3855 | { | |
3856 | ir.ot = OT_WORD; | |
3857 | if (i386_record_lea_modrm (&ir)) | |
3858 | return -1; | |
3859 | } | |
7ad10968 HZ |
3860 | break; |
3861 | ||
a38bba38 | 3862 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
3863 | if (i386_record_modrm (&ir)) |
3864 | return -1; | |
7ad10968 HZ |
3865 | switch (ir.reg) |
3866 | { | |
3867 | case 0: | |
cf648174 | 3868 | tmpu8 = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
3869 | break; |
3870 | case 2: | |
cf648174 | 3871 | tmpu8 = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
3872 | break; |
3873 | case 3: | |
cf648174 | 3874 | tmpu8 = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
3875 | break; |
3876 | case 4: | |
cf648174 | 3877 | tmpu8 = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
3878 | break; |
3879 | case 5: | |
cf648174 | 3880 | tmpu8 = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
3881 | break; |
3882 | default: | |
3883 | ir.addr -= 2; | |
3884 | opcode = opcode << 8 | ir.modrm; | |
3885 | goto no_support; | |
3886 | break; | |
3887 | } | |
cf648174 HZ |
3888 | I386_RECORD_ARCH_LIST_ADD_REG (tmpu8); |
3889 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3890 | break; |
3891 | ||
a38bba38 MS |
3892 | case 0x0fb6: /* movzbS */ |
3893 | case 0x0fb7: /* movzwS */ | |
3894 | case 0x0fbe: /* movsbS */ | |
3895 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
3896 | if (i386_record_modrm (&ir)) |
3897 | return -1; | |
cf648174 | 3898 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
3899 | break; |
3900 | ||
a38bba38 | 3901 | case 0x8d: /* lea */ |
7ad10968 HZ |
3902 | if (i386_record_modrm (&ir)) |
3903 | return -1; | |
3904 | if (ir.mod == 3) | |
3905 | { | |
3906 | ir.addr -= 2; | |
3907 | opcode = opcode << 8 | ir.modrm; | |
3908 | goto no_support; | |
3909 | } | |
7ad10968 | 3910 | ir.ot = ir.dflag; |
cf648174 HZ |
3911 | ir.reg |= rex_r; |
3912 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3913 | ir.reg &= 0x3; |
cf648174 | 3914 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
3915 | break; |
3916 | ||
a38bba38 | 3917 | case 0xa0: /* mov EAX */ |
7ad10968 | 3918 | case 0xa1: |
a38bba38 MS |
3919 | |
3920 | case 0xd7: /* xlat */ | |
cf648174 | 3921 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3922 | break; |
3923 | ||
a38bba38 | 3924 | case 0xa2: /* mov EAX */ |
7ad10968 | 3925 | case 0xa3: |
d7877f7e | 3926 | if (ir.override >= 0) |
cf648174 | 3927 | { |
df61f520 | 3928 | warning (_("Process record ignores the memory change " |
926569ae | 3929 | "of instruction at address %s because " |
df61f520 HZ |
3930 | "it can't get the value of the segment " |
3931 | "register."), | |
3932 | paddress (gdbarch, ir.orig_addr)); | |
cf648174 HZ |
3933 | } |
3934 | else | |
3935 | { | |
3936 | if ((opcode & 1) == 0) | |
3937 | ir.ot = OT_BYTE; | |
3938 | else | |
3939 | ir.ot = ir.dflag + OT_WORD; | |
3940 | if (ir.aflag == 2) | |
3941 | { | |
3942 | if (target_read_memory (ir.addr, (gdb_byte *) &addr, 8)) | |
3943 | { | |
3944 | if (record_debug) | |
3945 | printf_unfiltered (_("Process record: error reading " | |
3946 | "memory at addr 0x%s len = 8.\n"), | |
3947 | paddress (gdbarch, ir.addr)); | |
3948 | return -1; | |
3949 | } | |
3950 | ir.addr += 8; | |
3951 | } | |
3952 | else if (ir.aflag) | |
3953 | { | |
3954 | if (target_read_memory (ir.addr, (gdb_byte *) &tmpu32, 4)) | |
3955 | { | |
3956 | if (record_debug) | |
3957 | printf_unfiltered (_("Process record: error reading " | |
3958 | "memory at addr 0x%s len = 4.\n"), | |
3959 | paddress (gdbarch, ir.addr)); | |
3960 | return -1; | |
3961 | } | |
3962 | ir.addr += 4; | |
3963 | addr = tmpu32; | |
3964 | } | |
3965 | else | |
3966 | { | |
3967 | if (target_read_memory (ir.addr, (gdb_byte *) &tmpu16, 2)) | |
3968 | { | |
3969 | if (record_debug) | |
3970 | printf_unfiltered (_("Process record: error reading " | |
3971 | "memory at addr 0x%s len = 2.\n"), | |
3972 | paddress (gdbarch, ir.addr)); | |
3973 | return -1; | |
3974 | } | |
3975 | ir.addr += 2; | |
3976 | addr = tmpu16; | |
3977 | } | |
3978 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) | |
3979 | return -1; | |
3980 | } | |
7ad10968 HZ |
3981 | break; |
3982 | ||
a38bba38 | 3983 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
3984 | case 0xb1: |
3985 | case 0xb2: | |
3986 | case 0xb3: | |
3987 | case 0xb4: | |
3988 | case 0xb5: | |
3989 | case 0xb6: | |
3990 | case 0xb7: | |
cf648174 HZ |
3991 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
3992 | ? ((opcode & 0x7) | ir.rex_b) | |
3993 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
3994 | break; |
3995 | ||
a38bba38 | 3996 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
3997 | case 0xb9: |
3998 | case 0xba: | |
3999 | case 0xbb: | |
4000 | case 0xbc: | |
4001 | case 0xbd: | |
4002 | case 0xbe: | |
4003 | case 0xbf: | |
cf648174 | 4004 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
4005 | break; |
4006 | ||
a38bba38 | 4007 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
4008 | case 0x92: |
4009 | case 0x93: | |
4010 | case 0x94: | |
4011 | case 0x95: | |
4012 | case 0x96: | |
4013 | case 0x97: | |
cf648174 HZ |
4014 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4015 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
4016 | break; |
4017 | ||
a38bba38 | 4018 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
4019 | case 0x87: |
4020 | if ((opcode & 1) == 0) | |
4021 | ir.ot = OT_BYTE; | |
4022 | else | |
4023 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4024 | if (i386_record_modrm (&ir)) |
4025 | return -1; | |
7ad10968 HZ |
4026 | if (ir.mod == 3) |
4027 | { | |
86839d38 | 4028 | ir.rm |= ir.rex_b; |
cf648174 HZ |
4029 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
4030 | ir.rm &= 0x3; | |
4031 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
4032 | } |
4033 | else | |
4034 | { | |
4035 | if (i386_record_lea_modrm (&ir)) | |
4036 | return -1; | |
4037 | } | |
cf648174 HZ |
4038 | ir.reg |= rex_r; |
4039 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4040 | ir.reg &= 0x3; |
cf648174 | 4041 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4042 | break; |
4043 | ||
a38bba38 MS |
4044 | case 0xc4: /* les Gv */ |
4045 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
4046 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4047 | { | |
4048 | ir.addr -= 1; | |
4049 | goto no_support; | |
4050 | } | |
a38bba38 MS |
4051 | case 0x0fb2: /* lss Gv */ |
4052 | case 0x0fb4: /* lfs Gv */ | |
4053 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
4054 | if (i386_record_modrm (&ir)) |
4055 | return -1; | |
4056 | if (ir.mod == 3) | |
4057 | { | |
4058 | if (opcode > 0xff) | |
4059 | ir.addr -= 3; | |
4060 | else | |
4061 | ir.addr -= 2; | |
4062 | opcode = opcode << 8 | ir.modrm; | |
4063 | goto no_support; | |
4064 | } | |
7ad10968 HZ |
4065 | switch (opcode) |
4066 | { | |
a38bba38 | 4067 | case 0xc4: /* les Gv */ |
cf648174 | 4068 | tmpu8 = X86_RECORD_ES_REGNUM; |
7ad10968 | 4069 | break; |
a38bba38 | 4070 | case 0xc5: /* lds Gv */ |
cf648174 | 4071 | tmpu8 = X86_RECORD_DS_REGNUM; |
7ad10968 | 4072 | break; |
a38bba38 | 4073 | case 0x0fb2: /* lss Gv */ |
cf648174 | 4074 | tmpu8 = X86_RECORD_SS_REGNUM; |
7ad10968 | 4075 | break; |
a38bba38 | 4076 | case 0x0fb4: /* lfs Gv */ |
cf648174 | 4077 | tmpu8 = X86_RECORD_FS_REGNUM; |
7ad10968 | 4078 | break; |
a38bba38 | 4079 | case 0x0fb5: /* lgs Gv */ |
cf648174 | 4080 | tmpu8 = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4081 | break; |
4082 | } | |
cf648174 HZ |
4083 | I386_RECORD_ARCH_LIST_ADD_REG (tmpu8); |
4084 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
4085 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4086 | break; |
4087 | ||
a38bba38 | 4088 | case 0xc0: /* shifts */ |
7ad10968 HZ |
4089 | case 0xc1: |
4090 | case 0xd0: | |
4091 | case 0xd1: | |
4092 | case 0xd2: | |
4093 | case 0xd3: | |
4094 | if ((opcode & 1) == 0) | |
4095 | ir.ot = OT_BYTE; | |
4096 | else | |
4097 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4098 | if (i386_record_modrm (&ir)) |
4099 | return -1; | |
7ad10968 HZ |
4100 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
4101 | { | |
4102 | if (i386_record_lea_modrm (&ir)) | |
4103 | return -1; | |
4104 | } | |
4105 | else | |
4106 | { | |
cf648174 HZ |
4107 | ir.rm |= ir.rex_b; |
4108 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4109 | ir.rm &= 0x3; |
cf648174 | 4110 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4111 | } |
cf648174 | 4112 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4113 | break; |
4114 | ||
4115 | case 0x0fa4: | |
4116 | case 0x0fa5: | |
4117 | case 0x0fac: | |
4118 | case 0x0fad: | |
4119 | if (i386_record_modrm (&ir)) | |
4120 | return -1; | |
4121 | if (ir.mod == 3) | |
4122 | { | |
4123 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4124 | return -1; | |
4125 | } | |
4126 | else | |
4127 | { | |
4128 | if (i386_record_lea_modrm (&ir)) | |
4129 | return -1; | |
4130 | } | |
4131 | break; | |
4132 | ||
a38bba38 | 4133 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
4134 | case 0xd9: |
4135 | case 0xda: | |
4136 | case 0xdb: | |
4137 | case 0xdc: | |
4138 | case 0xdd: | |
4139 | case 0xde: | |
4140 | case 0xdf: | |
4141 | if (i386_record_modrm (&ir)) | |
4142 | return -1; | |
4143 | ir.reg |= ((opcode & 7) << 3); | |
4144 | if (ir.mod != 3) | |
4145 | { | |
0289bdd7 | 4146 | /* Memory. */ |
cf648174 | 4147 | uint64_t tmpu64; |
7ad10968 | 4148 | |
cf648174 | 4149 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7ad10968 HZ |
4150 | return -1; |
4151 | switch (ir.reg) | |
4152 | { | |
7ad10968 | 4153 | case 0x02: |
0289bdd7 MS |
4154 | case 0x12: |
4155 | case 0x22: | |
4156 | case 0x32: | |
4157 | /* For fcom, ficom nothing to do. */ | |
4158 | break; | |
7ad10968 | 4159 | case 0x03: |
0289bdd7 MS |
4160 | case 0x13: |
4161 | case 0x23: | |
4162 | case 0x33: | |
4163 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
4164 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4165 | return -1; | |
4166 | break; | |
4167 | case 0x00: | |
4168 | case 0x01: | |
7ad10968 HZ |
4169 | case 0x04: |
4170 | case 0x05: | |
4171 | case 0x06: | |
4172 | case 0x07: | |
4173 | case 0x10: | |
4174 | case 0x11: | |
7ad10968 HZ |
4175 | case 0x14: |
4176 | case 0x15: | |
4177 | case 0x16: | |
4178 | case 0x17: | |
4179 | case 0x20: | |
4180 | case 0x21: | |
7ad10968 HZ |
4181 | case 0x24: |
4182 | case 0x25: | |
4183 | case 0x26: | |
4184 | case 0x27: | |
4185 | case 0x30: | |
4186 | case 0x31: | |
7ad10968 HZ |
4187 | case 0x34: |
4188 | case 0x35: | |
4189 | case 0x36: | |
4190 | case 0x37: | |
0289bdd7 MS |
4191 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
4192 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
4193 | of code, always affects st(0) register. */ | |
4194 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4195 | return -1; | |
7ad10968 HZ |
4196 | break; |
4197 | case 0x08: | |
4198 | case 0x0a: | |
4199 | case 0x0b: | |
4200 | case 0x18: | |
4201 | case 0x19: | |
4202 | case 0x1a: | |
4203 | case 0x1b: | |
0289bdd7 | 4204 | case 0x1d: |
7ad10968 HZ |
4205 | case 0x28: |
4206 | case 0x29: | |
4207 | case 0x2a: | |
4208 | case 0x2b: | |
4209 | case 0x38: | |
4210 | case 0x39: | |
4211 | case 0x3a: | |
4212 | case 0x3b: | |
0289bdd7 MS |
4213 | case 0x3c: |
4214 | case 0x3d: | |
7ad10968 HZ |
4215 | switch (ir.reg & 7) |
4216 | { | |
4217 | case 0: | |
0289bdd7 MS |
4218 | /* Handling fld, fild. */ |
4219 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4220 | return -1; | |
7ad10968 HZ |
4221 | break; |
4222 | case 1: | |
4223 | switch (ir.reg >> 4) | |
4224 | { | |
4225 | case 0: | |
cf648174 | 4226 | if (record_arch_list_add_mem (tmpu64, 4)) |
7ad10968 HZ |
4227 | return -1; |
4228 | break; | |
4229 | case 2: | |
cf648174 | 4230 | if (record_arch_list_add_mem (tmpu64, 8)) |
7ad10968 HZ |
4231 | return -1; |
4232 | break; | |
4233 | case 3: | |
0289bdd7 | 4234 | break; |
7ad10968 | 4235 | default: |
cf648174 | 4236 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 HZ |
4237 | return -1; |
4238 | break; | |
4239 | } | |
4240 | break; | |
4241 | default: | |
4242 | switch (ir.reg >> 4) | |
4243 | { | |
4244 | case 0: | |
0289bdd7 MS |
4245 | if (record_arch_list_add_mem (tmpu64, 4)) |
4246 | return -1; | |
4247 | if (3 == (ir.reg & 7)) | |
4248 | { | |
4249 | /* For fstp m32fp. */ | |
4250 | if (i386_record_floats (gdbarch, &ir, | |
4251 | I386_SAVE_FPU_REGS)) | |
4252 | return -1; | |
4253 | } | |
4254 | break; | |
7ad10968 | 4255 | case 1: |
cf648174 | 4256 | if (record_arch_list_add_mem (tmpu64, 4)) |
7ad10968 | 4257 | return -1; |
0289bdd7 MS |
4258 | if ((3 == (ir.reg & 7)) |
4259 | || (5 == (ir.reg & 7)) | |
4260 | || (7 == (ir.reg & 7))) | |
4261 | { | |
4262 | /* For fstp insn. */ | |
4263 | if (i386_record_floats (gdbarch, &ir, | |
4264 | I386_SAVE_FPU_REGS)) | |
4265 | return -1; | |
4266 | } | |
7ad10968 HZ |
4267 | break; |
4268 | case 2: | |
cf648174 | 4269 | if (record_arch_list_add_mem (tmpu64, 8)) |
7ad10968 | 4270 | return -1; |
0289bdd7 MS |
4271 | if (3 == (ir.reg & 7)) |
4272 | { | |
4273 | /* For fstp m64fp. */ | |
4274 | if (i386_record_floats (gdbarch, &ir, | |
4275 | I386_SAVE_FPU_REGS)) | |
4276 | return -1; | |
4277 | } | |
7ad10968 HZ |
4278 | break; |
4279 | case 3: | |
0289bdd7 MS |
4280 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
4281 | { | |
4282 | /* For fistp, fbld, fild, fbstp. */ | |
4283 | if (i386_record_floats (gdbarch, &ir, | |
4284 | I386_SAVE_FPU_REGS)) | |
4285 | return -1; | |
4286 | } | |
4287 | /* Fall through */ | |
7ad10968 | 4288 | default: |
cf648174 | 4289 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 HZ |
4290 | return -1; |
4291 | break; | |
4292 | } | |
4293 | break; | |
4294 | } | |
4295 | break; | |
4296 | case 0x0c: | |
0289bdd7 MS |
4297 | /* Insn fldenv. */ |
4298 | if (i386_record_floats (gdbarch, &ir, | |
4299 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4300 | return -1; | |
4301 | break; | |
7ad10968 | 4302 | case 0x0d: |
0289bdd7 MS |
4303 | /* Insn fldcw. */ |
4304 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
4305 | return -1; | |
4306 | break; | |
7ad10968 | 4307 | case 0x2c: |
0289bdd7 MS |
4308 | /* Insn frstor. */ |
4309 | if (i386_record_floats (gdbarch, &ir, | |
4310 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4311 | return -1; | |
7ad10968 HZ |
4312 | break; |
4313 | case 0x0e: | |
4314 | if (ir.dflag) | |
4315 | { | |
cf648174 | 4316 | if (record_arch_list_add_mem (tmpu64, 28)) |
7ad10968 HZ |
4317 | return -1; |
4318 | } | |
4319 | else | |
4320 | { | |
cf648174 | 4321 | if (record_arch_list_add_mem (tmpu64, 14)) |
7ad10968 HZ |
4322 | return -1; |
4323 | } | |
4324 | break; | |
4325 | case 0x0f: | |
4326 | case 0x2f: | |
cf648174 | 4327 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 | 4328 | return -1; |
0289bdd7 MS |
4329 | /* Insn fstp, fbstp. */ |
4330 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4331 | return -1; | |
7ad10968 HZ |
4332 | break; |
4333 | case 0x1f: | |
4334 | case 0x3e: | |
cf648174 | 4335 | if (record_arch_list_add_mem (tmpu64, 10)) |
7ad10968 HZ |
4336 | return -1; |
4337 | break; | |
4338 | case 0x2e: | |
4339 | if (ir.dflag) | |
4340 | { | |
cf648174 | 4341 | if (record_arch_list_add_mem (tmpu64, 28)) |
7ad10968 | 4342 | return -1; |
cf648174 | 4343 | tmpu64 += 28; |
7ad10968 HZ |
4344 | } |
4345 | else | |
4346 | { | |
cf648174 | 4347 | if (record_arch_list_add_mem (tmpu64, 14)) |
7ad10968 | 4348 | return -1; |
cf648174 | 4349 | tmpu64 += 14; |
7ad10968 | 4350 | } |
cf648174 | 4351 | if (record_arch_list_add_mem (tmpu64, 80)) |
7ad10968 | 4352 | return -1; |
0289bdd7 MS |
4353 | /* Insn fsave. */ |
4354 | if (i386_record_floats (gdbarch, &ir, | |
4355 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4356 | return -1; | |
7ad10968 HZ |
4357 | break; |
4358 | case 0x3f: | |
cf648174 | 4359 | if (record_arch_list_add_mem (tmpu64, 8)) |
7ad10968 | 4360 | return -1; |
0289bdd7 MS |
4361 | /* Insn fistp. */ |
4362 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4363 | return -1; | |
7ad10968 HZ |
4364 | break; |
4365 | default: | |
4366 | ir.addr -= 2; | |
4367 | opcode = opcode << 8 | ir.modrm; | |
4368 | goto no_support; | |
4369 | break; | |
4370 | } | |
4371 | } | |
0289bdd7 MS |
4372 | /* Opcode is an extension of modR/M byte. */ |
4373 | else | |
4374 | { | |
4375 | switch (opcode) | |
4376 | { | |
4377 | case 0xd8: | |
4378 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4379 | return -1; | |
4380 | break; | |
4381 | case 0xd9: | |
4382 | if (0x0c == (ir.modrm >> 4)) | |
4383 | { | |
4384 | if ((ir.modrm & 0x0f) <= 7) | |
4385 | { | |
4386 | if (i386_record_floats (gdbarch, &ir, | |
4387 | I386_SAVE_FPU_REGS)) | |
4388 | return -1; | |
4389 | } | |
4390 | else | |
4391 | { | |
4392 | if (i386_record_floats (gdbarch, &ir, | |
4393 | I387_ST0_REGNUM (tdep))) | |
4394 | return -1; | |
4395 | /* If only st(0) is changing, then we have already | |
4396 | recorded. */ | |
4397 | if ((ir.modrm & 0x0f) - 0x08) | |
4398 | { | |
4399 | if (i386_record_floats (gdbarch, &ir, | |
4400 | I387_ST0_REGNUM (tdep) + | |
4401 | ((ir.modrm & 0x0f) - 0x08))) | |
4402 | return -1; | |
4403 | } | |
4404 | } | |
4405 | } | |
4406 | else | |
4407 | { | |
4408 | switch (ir.modrm) | |
4409 | { | |
4410 | case 0xe0: | |
4411 | case 0xe1: | |
4412 | case 0xf0: | |
4413 | case 0xf5: | |
4414 | case 0xf8: | |
4415 | case 0xfa: | |
4416 | case 0xfc: | |
4417 | case 0xfe: | |
4418 | case 0xff: | |
4419 | if (i386_record_floats (gdbarch, &ir, | |
4420 | I387_ST0_REGNUM (tdep))) | |
4421 | return -1; | |
4422 | break; | |
4423 | case 0xf1: | |
4424 | case 0xf2: | |
4425 | case 0xf3: | |
4426 | case 0xf4: | |
4427 | case 0xf6: | |
4428 | case 0xf7: | |
4429 | case 0xe8: | |
4430 | case 0xe9: | |
4431 | case 0xea: | |
4432 | case 0xeb: | |
4433 | case 0xec: | |
4434 | case 0xed: | |
4435 | case 0xee: | |
4436 | case 0xf9: | |
4437 | case 0xfb: | |
4438 | if (i386_record_floats (gdbarch, &ir, | |
4439 | I386_SAVE_FPU_REGS)) | |
4440 | return -1; | |
4441 | break; | |
4442 | case 0xfd: | |
4443 | if (i386_record_floats (gdbarch, &ir, | |
4444 | I387_ST0_REGNUM (tdep))) | |
4445 | return -1; | |
4446 | if (i386_record_floats (gdbarch, &ir, | |
4447 | I387_ST0_REGNUM (tdep) + 1)) | |
4448 | return -1; | |
4449 | break; | |
4450 | } | |
4451 | } | |
4452 | break; | |
4453 | case 0xda: | |
4454 | if (0xe9 == ir.modrm) | |
4455 | { | |
4456 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4457 | return -1; | |
4458 | } | |
4459 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4460 | { | |
4461 | if (i386_record_floats (gdbarch, &ir, | |
4462 | I387_ST0_REGNUM (tdep))) | |
4463 | return -1; | |
4464 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4465 | { | |
4466 | if (i386_record_floats (gdbarch, &ir, | |
4467 | I387_ST0_REGNUM (tdep) + | |
4468 | (ir.modrm & 0x0f))) | |
4469 | return -1; | |
4470 | } | |
4471 | else if ((ir.modrm & 0x0f) - 0x08) | |
4472 | { | |
4473 | if (i386_record_floats (gdbarch, &ir, | |
4474 | I387_ST0_REGNUM (tdep) + | |
4475 | ((ir.modrm & 0x0f) - 0x08))) | |
4476 | return -1; | |
4477 | } | |
4478 | } | |
4479 | break; | |
4480 | case 0xdb: | |
4481 | if (0xe3 == ir.modrm) | |
4482 | { | |
4483 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
4484 | return -1; | |
4485 | } | |
4486 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4487 | { | |
4488 | if (i386_record_floats (gdbarch, &ir, | |
4489 | I387_ST0_REGNUM (tdep))) | |
4490 | return -1; | |
4491 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4492 | { | |
4493 | if (i386_record_floats (gdbarch, &ir, | |
4494 | I387_ST0_REGNUM (tdep) + | |
4495 | (ir.modrm & 0x0f))) | |
4496 | return -1; | |
4497 | } | |
4498 | else if ((ir.modrm & 0x0f) - 0x08) | |
4499 | { | |
4500 | if (i386_record_floats (gdbarch, &ir, | |
4501 | I387_ST0_REGNUM (tdep) + | |
4502 | ((ir.modrm & 0x0f) - 0x08))) | |
4503 | return -1; | |
4504 | } | |
4505 | } | |
4506 | break; | |
4507 | case 0xdc: | |
4508 | if ((0x0c == ir.modrm >> 4) | |
4509 | || (0x0d == ir.modrm >> 4) | |
4510 | || (0x0f == ir.modrm >> 4)) | |
4511 | { | |
4512 | if ((ir.modrm & 0x0f) <= 7) | |
4513 | { | |
4514 | if (i386_record_floats (gdbarch, &ir, | |
4515 | I387_ST0_REGNUM (tdep) + | |
4516 | (ir.modrm & 0x0f))) | |
4517 | return -1; | |
4518 | } | |
4519 | else | |
4520 | { | |
4521 | if (i386_record_floats (gdbarch, &ir, | |
4522 | I387_ST0_REGNUM (tdep) + | |
4523 | ((ir.modrm & 0x0f) - 0x08))) | |
4524 | return -1; | |
4525 | } | |
4526 | } | |
4527 | break; | |
4528 | case 0xdd: | |
4529 | if (0x0c == ir.modrm >> 4) | |
4530 | { | |
4531 | if (i386_record_floats (gdbarch, &ir, | |
4532 | I387_FTAG_REGNUM (tdep))) | |
4533 | return -1; | |
4534 | } | |
4535 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
4536 | { | |
4537 | if ((ir.modrm & 0x0f) <= 7) | |
4538 | { | |
4539 | if (i386_record_floats (gdbarch, &ir, | |
4540 | I387_ST0_REGNUM (tdep) + | |
4541 | (ir.modrm & 0x0f))) | |
4542 | return -1; | |
4543 | } | |
4544 | else | |
4545 | { | |
4546 | if (i386_record_floats (gdbarch, &ir, | |
4547 | I386_SAVE_FPU_REGS)) | |
4548 | return -1; | |
4549 | } | |
4550 | } | |
4551 | break; | |
4552 | case 0xde: | |
4553 | if ((0x0c == ir.modrm >> 4) | |
4554 | || (0x0e == ir.modrm >> 4) | |
4555 | || (0x0f == ir.modrm >> 4) | |
4556 | || (0xd9 == ir.modrm)) | |
4557 | { | |
4558 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4559 | return -1; | |
4560 | } | |
4561 | break; | |
4562 | case 0xdf: | |
4563 | if (0xe0 == ir.modrm) | |
4564 | { | |
4565 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4566 | return -1; | |
4567 | } | |
4568 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
4569 | { | |
4570 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4571 | return -1; | |
4572 | } | |
4573 | break; | |
4574 | } | |
4575 | } | |
7ad10968 | 4576 | break; |
7ad10968 | 4577 | /* string ops */ |
a38bba38 | 4578 | case 0xa4: /* movsS */ |
7ad10968 | 4579 | case 0xa5: |
a38bba38 | 4580 | case 0xaa: /* stosS */ |
7ad10968 | 4581 | case 0xab: |
a38bba38 | 4582 | case 0x6c: /* insS */ |
7ad10968 | 4583 | case 0x6d: |
cf648174 | 4584 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 4585 | ir.regmap[X86_RECORD_RECX_REGNUM], |
cf648174 | 4586 | &tmpulongest); |
77d7dc92 | 4587 | if (tmpulongest) |
cf648174 | 4588 | { |
77d7dc92 HZ |
4589 | ULONGEST es, ds; |
4590 | ||
4591 | if ((opcode & 1) == 0) | |
4592 | ir.ot = OT_BYTE; | |
4593 | else | |
4594 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
4595 | regcache_raw_read_unsigned (ir.regcache, |
4596 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
77d7dc92 HZ |
4597 | &tmpulongest); |
4598 | ||
d7877f7e HZ |
4599 | regcache_raw_read_unsigned (ir.regcache, |
4600 | ir.regmap[X86_RECORD_ES_REGNUM], | |
4601 | &es); | |
4602 | regcache_raw_read_unsigned (ir.regcache, | |
4603 | ir.regmap[X86_RECORD_DS_REGNUM], | |
4604 | &ds); | |
4605 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
4606 | { |
4607 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
df61f520 | 4608 | warning (_("Process record ignores the memory " |
926569ae | 4609 | "change of instruction at address %s " |
df61f520 HZ |
4610 | "because it can't get the value of the " |
4611 | "ES segment register."), | |
4612 | paddress (gdbarch, ir.orig_addr)); | |
4613 | } | |
4614 | else | |
4615 | { | |
4616 | if (record_arch_list_add_mem (tmpulongest, 1 << ir.ot)) | |
4617 | return -1; | |
77d7dc92 HZ |
4618 | } |
4619 | ||
4620 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4621 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
4622 | if (opcode == 0xa4 || opcode == 0xa5) |
4623 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
4624 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
4625 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4626 | } | |
cf648174 | 4627 | break; |
7ad10968 | 4628 | |
a38bba38 | 4629 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
4630 | case 0xa7: |
4631 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
4632 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
4633 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4634 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
4635 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4636 | break; |
4637 | ||
a38bba38 | 4638 | case 0xac: /* lodsS */ |
7ad10968 | 4639 | case 0xad: |
cf648174 HZ |
4640 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4641 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 4642 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4643 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4644 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4645 | break; |
4646 | ||
a38bba38 | 4647 | case 0xae: /* scasS */ |
7ad10968 | 4648 | case 0xaf: |
cf648174 | 4649 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 4650 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4651 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4652 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4653 | break; |
4654 | ||
a38bba38 | 4655 | case 0x6e: /* outsS */ |
cf648174 HZ |
4656 | case 0x6f: |
4657 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 4658 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4659 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4660 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4661 | break; |
4662 | ||
a38bba38 | 4663 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
4664 | case 0xe5: |
4665 | case 0xec: | |
4666 | case 0xed: | |
cf648174 HZ |
4667 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4668 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
4669 | break; |
4670 | ||
4671 | case 0xe6: | |
4672 | case 0xe7: | |
4673 | case 0xee: | |
4674 | case 0xef: | |
4675 | break; | |
4676 | ||
4677 | /* control */ | |
a38bba38 MS |
4678 | case 0xc2: /* ret im */ |
4679 | case 0xc3: /* ret */ | |
cf648174 HZ |
4680 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4681 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4682 | break; | |
4683 | ||
a38bba38 MS |
4684 | case 0xca: /* lret im */ |
4685 | case 0xcb: /* lret */ | |
4686 | case 0xcf: /* iret */ | |
cf648174 HZ |
4687 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4688 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4689 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4690 | break; |
4691 | ||
a38bba38 | 4692 | case 0xe8: /* call im */ |
cf648174 HZ |
4693 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4694 | ir.dflag = 2; | |
4695 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4696 | return -1; | |
7ad10968 HZ |
4697 | break; |
4698 | ||
a38bba38 | 4699 | case 0x9a: /* lcall im */ |
cf648174 HZ |
4700 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4701 | { | |
4702 | ir.addr -= 1; | |
4703 | goto no_support; | |
4704 | } | |
4705 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
4706 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4707 | return -1; | |
7ad10968 HZ |
4708 | break; |
4709 | ||
a38bba38 MS |
4710 | case 0xe9: /* jmp im */ |
4711 | case 0xea: /* ljmp im */ | |
4712 | case 0xeb: /* jmp Jb */ | |
4713 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
4714 | case 0x71: |
4715 | case 0x72: | |
4716 | case 0x73: | |
4717 | case 0x74: | |
4718 | case 0x75: | |
4719 | case 0x76: | |
4720 | case 0x77: | |
4721 | case 0x78: | |
4722 | case 0x79: | |
4723 | case 0x7a: | |
4724 | case 0x7b: | |
4725 | case 0x7c: | |
4726 | case 0x7d: | |
4727 | case 0x7e: | |
4728 | case 0x7f: | |
a38bba38 | 4729 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
4730 | case 0x0f81: |
4731 | case 0x0f82: | |
4732 | case 0x0f83: | |
4733 | case 0x0f84: | |
4734 | case 0x0f85: | |
4735 | case 0x0f86: | |
4736 | case 0x0f87: | |
4737 | case 0x0f88: | |
4738 | case 0x0f89: | |
4739 | case 0x0f8a: | |
4740 | case 0x0f8b: | |
4741 | case 0x0f8c: | |
4742 | case 0x0f8d: | |
4743 | case 0x0f8e: | |
4744 | case 0x0f8f: | |
4745 | break; | |
4746 | ||
a38bba38 | 4747 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
4748 | case 0x0f91: |
4749 | case 0x0f92: | |
4750 | case 0x0f93: | |
4751 | case 0x0f94: | |
4752 | case 0x0f95: | |
4753 | case 0x0f96: | |
4754 | case 0x0f97: | |
4755 | case 0x0f98: | |
4756 | case 0x0f99: | |
4757 | case 0x0f9a: | |
4758 | case 0x0f9b: | |
4759 | case 0x0f9c: | |
4760 | case 0x0f9d: | |
4761 | case 0x0f9e: | |
4762 | case 0x0f9f: | |
cf648174 | 4763 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4764 | ir.ot = OT_BYTE; |
4765 | if (i386_record_modrm (&ir)) | |
4766 | return -1; | |
4767 | if (ir.mod == 3) | |
cf648174 HZ |
4768 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
4769 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
4770 | else |
4771 | { | |
4772 | if (i386_record_lea_modrm (&ir)) | |
4773 | return -1; | |
4774 | } | |
4775 | break; | |
4776 | ||
a38bba38 | 4777 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
4778 | case 0x0f41: |
4779 | case 0x0f42: | |
4780 | case 0x0f43: | |
4781 | case 0x0f44: | |
4782 | case 0x0f45: | |
4783 | case 0x0f46: | |
4784 | case 0x0f47: | |
4785 | case 0x0f48: | |
4786 | case 0x0f49: | |
4787 | case 0x0f4a: | |
4788 | case 0x0f4b: | |
4789 | case 0x0f4c: | |
4790 | case 0x0f4d: | |
4791 | case 0x0f4e: | |
4792 | case 0x0f4f: | |
4793 | if (i386_record_modrm (&ir)) | |
4794 | return -1; | |
cf648174 | 4795 | ir.reg |= rex_r; |
7ad10968 HZ |
4796 | if (ir.dflag == OT_BYTE) |
4797 | ir.reg &= 0x3; | |
cf648174 | 4798 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4799 | break; |
4800 | ||
4801 | /* flags */ | |
a38bba38 | 4802 | case 0x9c: /* pushf */ |
cf648174 HZ |
4803 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4804 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4805 | ir.dflag = 2; | |
4806 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4807 | return -1; | |
7ad10968 HZ |
4808 | break; |
4809 | ||
a38bba38 | 4810 | case 0x9d: /* popf */ |
cf648174 HZ |
4811 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4812 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4813 | break; |
4814 | ||
a38bba38 | 4815 | case 0x9e: /* sahf */ |
cf648174 HZ |
4816 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4817 | { | |
4818 | ir.addr -= 1; | |
4819 | goto no_support; | |
4820 | } | |
a38bba38 MS |
4821 | case 0xf5: /* cmc */ |
4822 | case 0xf8: /* clc */ | |
4823 | case 0xf9: /* stc */ | |
4824 | case 0xfc: /* cld */ | |
4825 | case 0xfd: /* std */ | |
cf648174 | 4826 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4827 | break; |
4828 | ||
a38bba38 | 4829 | case 0x9f: /* lahf */ |
cf648174 HZ |
4830 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4831 | { | |
4832 | ir.addr -= 1; | |
4833 | goto no_support; | |
4834 | } | |
4835 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4836 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
4837 | break; |
4838 | ||
4839 | /* bit operations */ | |
a38bba38 | 4840 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
4841 | ir.ot = ir.dflag + OT_WORD; |
4842 | if (i386_record_modrm (&ir)) | |
4843 | return -1; | |
4844 | if (ir.reg < 4) | |
4845 | { | |
cf648174 | 4846 | ir.addr -= 2; |
7ad10968 HZ |
4847 | opcode = opcode << 8 | ir.modrm; |
4848 | goto no_support; | |
4849 | } | |
cf648174 | 4850 | if (ir.reg != 4) |
7ad10968 | 4851 | { |
cf648174 HZ |
4852 | if (ir.mod == 3) |
4853 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
4854 | else |
4855 | { | |
cf648174 | 4856 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
4857 | return -1; |
4858 | } | |
4859 | } | |
cf648174 | 4860 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4861 | break; |
4862 | ||
a38bba38 | 4863 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
4864 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4865 | break; | |
4866 | ||
a38bba38 MS |
4867 | case 0x0fab: /* bts */ |
4868 | case 0x0fb3: /* btr */ | |
4869 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
4870 | ir.ot = ir.dflag + OT_WORD; |
4871 | if (i386_record_modrm (&ir)) | |
4872 | return -1; | |
4873 | if (ir.mod == 3) | |
4874 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
4875 | else | |
4876 | { | |
4877 | uint64_t tmpu64; | |
4878 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) | |
4879 | return -1; | |
4880 | regcache_raw_read_unsigned (ir.regcache, | |
4881 | ir.regmap[ir.reg | rex_r], | |
4882 | &tmpulongest); | |
4883 | switch (ir.dflag) | |
4884 | { | |
4885 | case 0: | |
4886 | tmpu64 += ((int16_t) tmpulongest >> 4) << 4; | |
4887 | break; | |
4888 | case 1: | |
4889 | tmpu64 += ((int32_t) tmpulongest >> 5) << 5; | |
4890 | break; | |
4891 | case 2: | |
4892 | tmpu64 += ((int64_t) tmpulongest >> 6) << 6; | |
4893 | break; | |
4894 | } | |
4895 | if (record_arch_list_add_mem (tmpu64, 1 << ir.ot)) | |
4896 | return -1; | |
4897 | if (i386_record_lea_modrm (&ir)) | |
4898 | return -1; | |
4899 | } | |
4900 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4901 | break; |
4902 | ||
a38bba38 MS |
4903 | case 0x0fbc: /* bsf */ |
4904 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
4905 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
4906 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4907 | break; |
4908 | ||
4909 | /* bcd */ | |
a38bba38 MS |
4910 | case 0x27: /* daa */ |
4911 | case 0x2f: /* das */ | |
4912 | case 0x37: /* aaa */ | |
4913 | case 0x3f: /* aas */ | |
4914 | case 0xd4: /* aam */ | |
4915 | case 0xd5: /* aad */ | |
cf648174 HZ |
4916 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4917 | { | |
4918 | ir.addr -= 1; | |
4919 | goto no_support; | |
4920 | } | |
4921 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
4922 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4923 | break; |
4924 | ||
4925 | /* misc */ | |
a38bba38 | 4926 | case 0x90: /* nop */ |
7ad10968 HZ |
4927 | if (prefixes & PREFIX_LOCK) |
4928 | { | |
4929 | ir.addr -= 1; | |
4930 | goto no_support; | |
4931 | } | |
4932 | break; | |
4933 | ||
a38bba38 | 4934 | case 0x9b: /* fwait */ |
0289bdd7 MS |
4935 | if (target_read_memory (ir.addr, &tmpu8, 1)) |
4936 | { | |
4937 | if (record_debug) | |
4938 | printf_unfiltered (_("Process record: error reading memory at " | |
4939 | "addr 0x%s len = 1.\n"), | |
4940 | paddress (gdbarch, ir.addr)); | |
4941 | return -1; | |
4942 | } | |
4943 | opcode = (uint32_t) tmpu8; | |
4944 | ir.addr++; | |
4945 | goto reswitch; | |
7ad10968 HZ |
4946 | break; |
4947 | ||
7ad10968 | 4948 | /* XXX */ |
a38bba38 | 4949 | case 0xcc: /* int3 */ |
7ad10968 HZ |
4950 | printf_unfiltered (_("Process record doesn't support instruction " |
4951 | "int3.\n")); | |
4952 | ir.addr -= 1; | |
4953 | goto no_support; | |
4954 | break; | |
4955 | ||
7ad10968 | 4956 | /* XXX */ |
a38bba38 | 4957 | case 0xcd: /* int */ |
7ad10968 HZ |
4958 | { |
4959 | int ret; | |
4960 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
4961 | { | |
4962 | if (record_debug) | |
4963 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
4964 | "at addr %s len = 1.\n"), |
4965 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4966 | return -1; |
4967 | } | |
4968 | ir.addr++; | |
4969 | if (tmpu8 != 0x80 | |
4970 | || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL) | |
4971 | { | |
4972 | printf_unfiltered (_("Process record doesn't support " | |
4973 | "instruction int 0x%02x.\n"), | |
4974 | tmpu8); | |
4975 | ir.addr -= 2; | |
4976 | goto no_support; | |
4977 | } | |
4978 | ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache); | |
4979 | if (ret) | |
4980 | return ret; | |
4981 | } | |
4982 | break; | |
4983 | ||
7ad10968 | 4984 | /* XXX */ |
a38bba38 | 4985 | case 0xce: /* into */ |
7ad10968 HZ |
4986 | printf_unfiltered (_("Process record doesn't support " |
4987 | "instruction into.\n")); | |
4988 | ir.addr -= 1; | |
4989 | goto no_support; | |
4990 | break; | |
4991 | ||
a38bba38 MS |
4992 | case 0xfa: /* cli */ |
4993 | case 0xfb: /* sti */ | |
7ad10968 HZ |
4994 | break; |
4995 | ||
a38bba38 | 4996 | case 0x62: /* bound */ |
7ad10968 HZ |
4997 | printf_unfiltered (_("Process record doesn't support " |
4998 | "instruction bound.\n")); | |
4999 | ir.addr -= 1; | |
5000 | goto no_support; | |
5001 | break; | |
5002 | ||
a38bba38 | 5003 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
5004 | case 0x0fc9: |
5005 | case 0x0fca: | |
5006 | case 0x0fcb: | |
5007 | case 0x0fcc: | |
5008 | case 0x0fcd: | |
5009 | case 0x0fce: | |
5010 | case 0x0fcf: | |
cf648174 | 5011 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
5012 | break; |
5013 | ||
a38bba38 | 5014 | case 0xd6: /* salc */ |
cf648174 HZ |
5015 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5016 | { | |
5017 | ir.addr -= 1; | |
5018 | goto no_support; | |
5019 | } | |
5020 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5021 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5022 | break; |
5023 | ||
a38bba38 MS |
5024 | case 0xe0: /* loopnz */ |
5025 | case 0xe1: /* loopz */ | |
5026 | case 0xe2: /* loop */ | |
5027 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
5028 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5029 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5030 | break; |
5031 | ||
a38bba38 | 5032 | case 0x0f30: /* wrmsr */ |
7ad10968 HZ |
5033 | printf_unfiltered (_("Process record doesn't support " |
5034 | "instruction wrmsr.\n")); | |
5035 | ir.addr -= 2; | |
5036 | goto no_support; | |
5037 | break; | |
5038 | ||
a38bba38 | 5039 | case 0x0f32: /* rdmsr */ |
7ad10968 HZ |
5040 | printf_unfiltered (_("Process record doesn't support " |
5041 | "instruction rdmsr.\n")); | |
5042 | ir.addr -= 2; | |
5043 | goto no_support; | |
5044 | break; | |
5045 | ||
a38bba38 | 5046 | case 0x0f31: /* rdtsc */ |
7ad10968 HZ |
5047 | printf_unfiltered (_("Process record doesn't support " |
5048 | "instruction rdtsc.\n")); | |
5049 | ir.addr -= 2; | |
5050 | goto no_support; | |
5051 | break; | |
5052 | ||
a38bba38 | 5053 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
5054 | { |
5055 | int ret; | |
cf648174 HZ |
5056 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5057 | { | |
5058 | ir.addr -= 2; | |
5059 | goto no_support; | |
5060 | } | |
7ad10968 HZ |
5061 | if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL) |
5062 | { | |
5063 | printf_unfiltered (_("Process record doesn't support " | |
5064 | "instruction sysenter.\n")); | |
5065 | ir.addr -= 2; | |
5066 | goto no_support; | |
5067 | } | |
5068 | ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache); | |
5069 | if (ret) | |
5070 | return ret; | |
5071 | } | |
5072 | break; | |
5073 | ||
a38bba38 | 5074 | case 0x0f35: /* sysexit */ |
7ad10968 HZ |
5075 | printf_unfiltered (_("Process record doesn't support " |
5076 | "instruction sysexit.\n")); | |
5077 | ir.addr -= 2; | |
5078 | goto no_support; | |
5079 | break; | |
5080 | ||
a38bba38 | 5081 | case 0x0f05: /* syscall */ |
cf648174 HZ |
5082 | { |
5083 | int ret; | |
5084 | if (gdbarch_tdep (gdbarch)->i386_syscall_record == NULL) | |
5085 | { | |
5086 | printf_unfiltered (_("Process record doesn't support " | |
5087 | "instruction syscall.\n")); | |
5088 | ir.addr -= 2; | |
5089 | goto no_support; | |
5090 | } | |
5091 | ret = gdbarch_tdep (gdbarch)->i386_syscall_record (ir.regcache); | |
5092 | if (ret) | |
5093 | return ret; | |
5094 | } | |
5095 | break; | |
5096 | ||
a38bba38 | 5097 | case 0x0f07: /* sysret */ |
cf648174 HZ |
5098 | printf_unfiltered (_("Process record doesn't support " |
5099 | "instruction sysret.\n")); | |
5100 | ir.addr -= 2; | |
5101 | goto no_support; | |
5102 | break; | |
5103 | ||
a38bba38 | 5104 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
5105 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5106 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5107 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5108 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
5109 | break; |
5110 | ||
a38bba38 | 5111 | case 0xf4: /* hlt */ |
7ad10968 HZ |
5112 | printf_unfiltered (_("Process record doesn't support " |
5113 | "instruction hlt.\n")); | |
5114 | ir.addr -= 1; | |
5115 | goto no_support; | |
5116 | break; | |
5117 | ||
5118 | case 0x0f00: | |
5119 | if (i386_record_modrm (&ir)) | |
5120 | return -1; | |
5121 | switch (ir.reg) | |
5122 | { | |
a38bba38 MS |
5123 | case 0: /* sldt */ |
5124 | case 1: /* str */ | |
7ad10968 | 5125 | if (ir.mod == 3) |
cf648174 | 5126 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5127 | else |
5128 | { | |
5129 | ir.ot = OT_WORD; | |
5130 | if (i386_record_lea_modrm (&ir)) | |
5131 | return -1; | |
5132 | } | |
5133 | break; | |
a38bba38 MS |
5134 | case 2: /* lldt */ |
5135 | case 3: /* ltr */ | |
7ad10968 | 5136 | break; |
a38bba38 MS |
5137 | case 4: /* verr */ |
5138 | case 5: /* verw */ | |
cf648174 | 5139 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5140 | break; |
5141 | default: | |
5142 | ir.addr -= 3; | |
5143 | opcode = opcode << 8 | ir.modrm; | |
5144 | goto no_support; | |
5145 | break; | |
5146 | } | |
5147 | break; | |
5148 | ||
5149 | case 0x0f01: | |
5150 | if (i386_record_modrm (&ir)) | |
5151 | return -1; | |
5152 | switch (ir.reg) | |
5153 | { | |
a38bba38 | 5154 | case 0: /* sgdt */ |
7ad10968 | 5155 | { |
cf648174 | 5156 | uint64_t tmpu64; |
7ad10968 HZ |
5157 | |
5158 | if (ir.mod == 3) | |
5159 | { | |
5160 | ir.addr -= 3; | |
5161 | opcode = opcode << 8 | ir.modrm; | |
5162 | goto no_support; | |
5163 | } | |
d7877f7e | 5164 | if (ir.override >= 0) |
7ad10968 | 5165 | { |
df61f520 HZ |
5166 | warning (_("Process record ignores the memory " |
5167 | "change of instruction at " | |
5168 | "address %s because it can't get " | |
5169 | "the value of the segment " | |
5170 | "register."), | |
5171 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5172 | } |
5173 | else | |
5174 | { | |
cf648174 | 5175 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7ad10968 | 5176 | return -1; |
cf648174 | 5177 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 | 5178 | return -1; |
cf648174 HZ |
5179 | tmpu64 += 2; |
5180 | if (ir.regmap[X86_RECORD_R8_REGNUM]) | |
5181 | { | |
5182 | if (record_arch_list_add_mem (tmpu64, 8)) | |
5183 | return -1; | |
5184 | } | |
5185 | else | |
5186 | { | |
5187 | if (record_arch_list_add_mem (tmpu64, 4)) | |
5188 | return -1; | |
5189 | } | |
7ad10968 HZ |
5190 | } |
5191 | } | |
5192 | break; | |
5193 | case 1: | |
5194 | if (ir.mod == 3) | |
5195 | { | |
5196 | switch (ir.rm) | |
5197 | { | |
a38bba38 | 5198 | case 0: /* monitor */ |
7ad10968 | 5199 | break; |
a38bba38 | 5200 | case 1: /* mwait */ |
cf648174 | 5201 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5202 | break; |
5203 | default: | |
5204 | ir.addr -= 3; | |
5205 | opcode = opcode << 8 | ir.modrm; | |
5206 | goto no_support; | |
5207 | break; | |
5208 | } | |
5209 | } | |
5210 | else | |
5211 | { | |
5212 | /* sidt */ | |
d7877f7e | 5213 | if (ir.override >= 0) |
7ad10968 | 5214 | { |
df61f520 HZ |
5215 | warning (_("Process record ignores the memory " |
5216 | "change of instruction at " | |
5217 | "address %s because it can't get " | |
5218 | "the value of the segment " | |
5219 | "register."), | |
5220 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5221 | } |
5222 | else | |
5223 | { | |
cf648174 | 5224 | uint64_t tmpu64; |
7ad10968 | 5225 | |
cf648174 | 5226 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7ad10968 | 5227 | return -1; |
cf648174 | 5228 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 HZ |
5229 | return -1; |
5230 | addr += 2; | |
cf648174 HZ |
5231 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5232 | { | |
5233 | if (record_arch_list_add_mem (tmpu64, 8)) | |
5234 | return -1; | |
5235 | } | |
5236 | else | |
5237 | { | |
5238 | if (record_arch_list_add_mem (tmpu64, 4)) | |
5239 | return -1; | |
5240 | } | |
7ad10968 HZ |
5241 | } |
5242 | } | |
5243 | break; | |
a38bba38 | 5244 | case 2: /* lgdt */ |
3800e645 MS |
5245 | if (ir.mod == 3) |
5246 | { | |
5247 | /* xgetbv */ | |
5248 | if (ir.rm == 0) | |
5249 | { | |
5250 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5251 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5252 | break; | |
5253 | } | |
5254 | /* xsetbv */ | |
5255 | else if (ir.rm == 1) | |
5256 | break; | |
5257 | } | |
a38bba38 | 5258 | case 3: /* lidt */ |
7ad10968 HZ |
5259 | if (ir.mod == 3) |
5260 | { | |
5261 | ir.addr -= 3; | |
5262 | opcode = opcode << 8 | ir.modrm; | |
5263 | goto no_support; | |
5264 | } | |
5265 | break; | |
a38bba38 | 5266 | case 4: /* smsw */ |
7ad10968 HZ |
5267 | if (ir.mod == 3) |
5268 | { | |
cf648174 | 5269 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
5270 | return -1; |
5271 | } | |
5272 | else | |
5273 | { | |
5274 | ir.ot = OT_WORD; | |
5275 | if (i386_record_lea_modrm (&ir)) | |
5276 | return -1; | |
5277 | } | |
cf648174 | 5278 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5279 | break; |
a38bba38 | 5280 | case 6: /* lmsw */ |
cf648174 HZ |
5281 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5282 | break; | |
a38bba38 | 5283 | case 7: /* invlpg */ |
cf648174 HZ |
5284 | if (ir.mod == 3) |
5285 | { | |
5286 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
5287 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5288 | else | |
5289 | { | |
5290 | ir.addr -= 3; | |
5291 | opcode = opcode << 8 | ir.modrm; | |
5292 | goto no_support; | |
5293 | } | |
5294 | } | |
5295 | else | |
5296 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5297 | break; | |
5298 | default: | |
5299 | ir.addr -= 3; | |
5300 | opcode = opcode << 8 | ir.modrm; | |
5301 | goto no_support; | |
7ad10968 HZ |
5302 | break; |
5303 | } | |
5304 | break; | |
5305 | ||
a38bba38 MS |
5306 | case 0x0f08: /* invd */ |
5307 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
5308 | break; |
5309 | ||
a38bba38 | 5310 | case 0x63: /* arpl */ |
7ad10968 HZ |
5311 | if (i386_record_modrm (&ir)) |
5312 | return -1; | |
cf648174 HZ |
5313 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
5314 | { | |
5315 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
5316 | ? (ir.reg | rex_r) : ir.rm); | |
5317 | } | |
7ad10968 | 5318 | else |
cf648174 HZ |
5319 | { |
5320 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
5321 | if (i386_record_lea_modrm (&ir)) | |
5322 | return -1; | |
5323 | } | |
5324 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
5325 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5326 | break; |
5327 | ||
a38bba38 MS |
5328 | case 0x0f02: /* lar */ |
5329 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
5330 | if (i386_record_modrm (&ir)) |
5331 | return -1; | |
cf648174 HZ |
5332 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5333 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5334 | break; |
5335 | ||
5336 | case 0x0f18: | |
cf648174 HZ |
5337 | if (i386_record_modrm (&ir)) |
5338 | return -1; | |
5339 | if (ir.mod == 3 && ir.reg == 3) | |
5340 | { | |
5341 | ir.addr -= 3; | |
5342 | opcode = opcode << 8 | ir.modrm; | |
5343 | goto no_support; | |
5344 | } | |
7ad10968 HZ |
5345 | break; |
5346 | ||
7ad10968 HZ |
5347 | case 0x0f19: |
5348 | case 0x0f1a: | |
5349 | case 0x0f1b: | |
5350 | case 0x0f1c: | |
5351 | case 0x0f1d: | |
5352 | case 0x0f1e: | |
5353 | case 0x0f1f: | |
a38bba38 | 5354 | /* nop (multi byte) */ |
7ad10968 HZ |
5355 | break; |
5356 | ||
a38bba38 MS |
5357 | case 0x0f20: /* mov reg, crN */ |
5358 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
5359 | if (i386_record_modrm (&ir)) |
5360 | return -1; | |
5361 | if ((ir.modrm & 0xc0) != 0xc0) | |
5362 | { | |
cf648174 | 5363 | ir.addr -= 3; |
7ad10968 HZ |
5364 | opcode = opcode << 8 | ir.modrm; |
5365 | goto no_support; | |
5366 | } | |
5367 | switch (ir.reg) | |
5368 | { | |
5369 | case 0: | |
5370 | case 2: | |
5371 | case 3: | |
5372 | case 4: | |
5373 | case 8: | |
5374 | if (opcode & 2) | |
cf648174 | 5375 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5376 | else |
cf648174 | 5377 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5378 | break; |
5379 | default: | |
cf648174 | 5380 | ir.addr -= 3; |
7ad10968 HZ |
5381 | opcode = opcode << 8 | ir.modrm; |
5382 | goto no_support; | |
5383 | break; | |
5384 | } | |
5385 | break; | |
5386 | ||
a38bba38 MS |
5387 | case 0x0f21: /* mov reg, drN */ |
5388 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
5389 | if (i386_record_modrm (&ir)) |
5390 | return -1; | |
5391 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
5392 | || ir.reg == 5 || ir.reg >= 8) | |
5393 | { | |
cf648174 | 5394 | ir.addr -= 3; |
7ad10968 HZ |
5395 | opcode = opcode << 8 | ir.modrm; |
5396 | goto no_support; | |
5397 | } | |
5398 | if (opcode & 2) | |
cf648174 | 5399 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5400 | else |
cf648174 | 5401 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5402 | break; |
5403 | ||
a38bba38 | 5404 | case 0x0f06: /* clts */ |
cf648174 | 5405 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5406 | break; |
5407 | ||
5408 | /* MMX/SSE/SSE2/PNI support */ | |
5409 | /* XXX */ | |
5410 | ||
5411 | default: | |
5412 | if (opcode > 0xff) | |
5413 | ir.addr -= 2; | |
5414 | else | |
5415 | ir.addr -= 1; | |
5416 | goto no_support; | |
5417 | break; | |
5418 | } | |
5419 | ||
cf648174 HZ |
5420 | /* In the future, maybe still need to deal with need_dasm. */ |
5421 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
5422 | if (record_arch_list_add_end ()) |
5423 | return -1; | |
5424 | ||
5425 | return 0; | |
5426 | ||
01fe1b41 | 5427 | no_support: |
7ad10968 | 5428 | printf_unfiltered (_("Process record doesn't support instruction 0x%02x " |
5af949e3 UW |
5429 | "at address %s.\n"), |
5430 | (unsigned int) (opcode), paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5431 | return -1; |
5432 | } | |
5433 | ||
cf648174 HZ |
5434 | static const int i386_record_regmap[] = |
5435 | { | |
5436 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
5437 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
5438 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5439 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
5440 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
5441 | }; | |
5442 | ||
7a697b8d SS |
5443 | /* Check that the given address appears suitable for a fast |
5444 | tracepoint, which on x86 means that we need an instruction of at | |
5445 | least 5 bytes, so that we can overwrite it with a 4-byte-offset | |
5446 | jump and not have to worry about program jumps to an address in the | |
5447 | middle of the tracepoint jump. Returns 1 if OK, and writes a size | |
5448 | of instruction to replace, and 0 if not, plus an explanatory | |
5449 | string. */ | |
5450 | ||
5451 | static int | |
5452 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
5453 | CORE_ADDR addr, int *isize, char **msg) | |
5454 | { | |
5455 | int len, jumplen; | |
5456 | static struct ui_file *gdb_null = NULL; | |
5457 | ||
5458 | /* This is based on the target agent using a 4-byte relative jump. | |
5459 | Alternate future possibilities include 8-byte offset for x86-84, | |
5460 | or 3-byte jumps if the program has trampoline space close by. */ | |
5461 | jumplen = 5; | |
5462 | ||
5463 | /* Dummy file descriptor for the disassembler. */ | |
5464 | if (!gdb_null) | |
5465 | gdb_null = ui_file_new (); | |
5466 | ||
5467 | /* Check for fit. */ | |
5468 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
5469 | if (len < jumplen) | |
5470 | { | |
5471 | /* Return a bit of target-specific detail to add to the caller's | |
5472 | generic failure message. */ | |
5473 | if (msg) | |
5474 | *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"), | |
5475 | len, jumplen); | |
5476 | return 0; | |
5477 | } | |
5478 | ||
5479 | if (isize) | |
5480 | *isize = len; | |
5481 | if (msg) | |
5482 | *msg = NULL; | |
5483 | return 1; | |
5484 | } | |
5485 | ||
90884b2b L |
5486 | static int |
5487 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
5488 | struct tdesc_arch_data *tdesc_data) | |
5489 | { | |
5490 | const struct target_desc *tdesc = tdep->tdesc; | |
5491 | const struct tdesc_feature *feature_core, *feature_vector; | |
5492 | int i, num_regs, valid_p; | |
5493 | ||
5494 | if (! tdesc_has_registers (tdesc)) | |
5495 | return 0; | |
5496 | ||
5497 | /* Get core registers. */ | |
5498 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
5499 | ||
5500 | /* Get SSE registers. */ | |
5501 | feature_vector = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); | |
5502 | ||
5503 | if (feature_core == NULL || feature_vector == NULL) | |
5504 | return 0; | |
5505 | ||
5506 | valid_p = 1; | |
5507 | ||
5508 | num_regs = tdep->num_core_regs; | |
5509 | for (i = 0; i < num_regs; i++) | |
5510 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
5511 | tdep->register_names[i]); | |
5512 | ||
5513 | /* Need to include %mxcsr, so add one. */ | |
5514 | num_regs += tdep->num_xmm_regs + 1; | |
5515 | for (; i < num_regs; i++) | |
5516 | valid_p &= tdesc_numbered_register (feature_vector, tdesc_data, i, | |
5517 | tdep->register_names[i]); | |
5518 | ||
5519 | return valid_p; | |
5520 | } | |
5521 | ||
7ad10968 HZ |
5522 | \f |
5523 | static struct gdbarch * | |
5524 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
5525 | { | |
5526 | struct gdbarch_tdep *tdep; | |
5527 | struct gdbarch *gdbarch; | |
90884b2b L |
5528 | struct tdesc_arch_data *tdesc_data; |
5529 | const struct target_desc *tdesc; | |
7ad10968 HZ |
5530 | |
5531 | /* If there is already a candidate, use it. */ | |
5532 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
5533 | if (arches != NULL) | |
5534 | return arches->gdbarch; | |
5535 | ||
5536 | /* Allocate space for the new architecture. */ | |
5537 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
5538 | gdbarch = gdbarch_alloc (&info, tdep); | |
5539 | ||
5540 | /* General-purpose registers. */ | |
5541 | tdep->gregset = NULL; | |
5542 | tdep->gregset_reg_offset = NULL; | |
5543 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
5544 | tdep->sizeof_gregset = 0; | |
5545 | ||
5546 | /* Floating-point registers. */ | |
5547 | tdep->fpregset = NULL; | |
5548 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
5549 | ||
5550 | /* The default settings include the FPU registers, the MMX registers | |
5551 | and the SSE registers. This can be overridden for a specific ABI | |
5552 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
5553 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
5554 | will show up in the output of "info all-registers". Ideally we | |
5555 | should try to autodetect whether they are available, such that we | |
5556 | can prevent "info all-registers" from displaying registers that | |
5557 | aren't available. | |
5558 | ||
5559 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing | |
5560 | [the SSE registers] always (even when they don't exist) or never | |
5561 | showing them to the user (even when they do exist), I prefer the | |
5562 | former over the latter. */ | |
5563 | ||
5564 | tdep->st0_regnum = I386_ST0_REGNUM; | |
5565 | ||
5566 | /* The MMX registers are implemented as pseudo-registers. Put off | |
5567 | calculating the register number for %mm0 until we know the number | |
5568 | of raw registers. */ | |
5569 | tdep->mm0_regnum = 0; | |
5570 | ||
5571 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ | |
5572 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
5573 | ||
5574 | tdep->jb_pc_offset = -1; | |
5575 | tdep->struct_return = pcc_struct_return; | |
5576 | tdep->sigtramp_start = 0; | |
5577 | tdep->sigtramp_end = 0; | |
5578 | tdep->sigtramp_p = i386_sigtramp_p; | |
5579 | tdep->sigcontext_addr = NULL; | |
5580 | tdep->sc_reg_offset = NULL; | |
5581 | tdep->sc_pc_offset = -1; | |
5582 | tdep->sc_sp_offset = -1; | |
5583 | ||
cf648174 HZ |
5584 | tdep->record_regmap = i386_record_regmap; |
5585 | ||
7ad10968 HZ |
5586 | /* The format used for `long double' on almost all i386 targets is |
5587 | the i387 extended floating-point format. In fact, of all targets | |
5588 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
5589 | on having a `long double' that's not `long' at all. */ | |
5590 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
5591 | ||
5592 | /* Although the i387 extended floating-point has only 80 significant | |
5593 | bits, a `long double' actually takes up 96, probably to enforce | |
5594 | alignment. */ | |
5595 | set_gdbarch_long_double_bit (gdbarch, 96); | |
5596 | ||
7ad10968 HZ |
5597 | /* Register numbers of various important registers. */ |
5598 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
5599 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
5600 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
5601 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
5602 | ||
5603 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
5604 | numbering schemes on the i386: dbx and SVR4. These schemes | |
5605 | differ in how they number %ebp, %esp, %eflags, and the | |
5606 | floating-point registers, and are implemented by the arrays | |
5607 | dbx_register_map[] and svr4_dbx_register_map in | |
5608 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
5609 | gcc/config/i386.c, which it designates as the "default" register | |
5610 | map used in 64bit mode. This last register numbering scheme is | |
5611 | implemented in dbx64_register_map, and is used for AMD64; see | |
5612 | amd64-tdep.c. | |
5613 | ||
5614 | Currently, each GCC i386 target always uses the same register | |
5615 | numbering scheme across all its supported debugging formats | |
5616 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
5617 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
5618 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
5619 | respective config header in a manner independent of the requested | |
5620 | output debugging format. | |
5621 | ||
5622 | This does not match the arrangement below, which presumes that | |
5623 | the SDB and stabs numbering schemes differ from the DWARF and | |
5624 | DWARF 2 ones. The reason for this arrangement is that it is | |
5625 | likely to get the numbering scheme for the target's | |
5626 | default/native debug format right. For targets where GCC is the | |
5627 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
5628 | targets where the native toolchain uses a different numbering | |
5629 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
5630 | the defaults below will have to be overridden, like | |
5631 | i386_elf_init_abi() does. */ | |
5632 | ||
5633 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
5634 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5635 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5636 | ||
5637 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
5638 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
5639 | ||
5640 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
5641 | be in use on any of the supported i386 targets. */ | |
5642 | ||
5643 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
5644 | ||
5645 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
5646 | ||
5647 | /* Call dummy code. */ | |
5648 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
5649 | ||
5650 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
5651 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
5652 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
5653 | ||
5654 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
5655 | ||
5656 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
5657 | ||
5658 | /* Stack grows downward. */ | |
5659 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
5660 | ||
5661 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
5662 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
5663 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
5664 | ||
5665 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
5666 | ||
7ad10968 HZ |
5667 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
5668 | ||
5669 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
5670 | ||
5671 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
5672 | ||
5673 | /* Add the i386 register groups. */ | |
5674 | i386_add_reggroups (gdbarch); | |
90884b2b | 5675 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 5676 | |
143985b7 AF |
5677 | /* Helper for function argument information. */ |
5678 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
5679 | ||
06da04c6 MS |
5680 | /* Hook the function epilogue frame unwinder. This unwinder is |
5681 | appended to the list first, so that it supercedes the Dwarf | |
5682 | unwinder in function epilogues (where the Dwarf unwinder | |
5683 | currently fails). */ | |
5684 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
5685 | ||
5686 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
5687 | to the list before the prologue-based unwinders, so that Dwarf | |
5688 | CFI info will be used if it is available. */ | |
10458914 | 5689 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 5690 | |
acd5c798 | 5691 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 5692 | |
90884b2b L |
5693 | /* Wire in the MMX registers. */ |
5694 | set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs); | |
5695 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); | |
5696 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
5697 | ||
5698 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
5699 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
5700 | ||
5701 | /* The default ABI includes general-purpose registers, | |
5702 | floating-point registers, and the SSE registers. */ | |
5703 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); | |
5704 | ||
5705 | /* Get the x86 target description from INFO. */ | |
5706 | tdesc = info.target_desc; | |
5707 | if (! tdesc_has_registers (tdesc)) | |
5708 | tdesc = tdesc_i386; | |
5709 | tdep->tdesc = tdesc; | |
5710 | ||
5711 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
5712 | tdep->register_names = i386_register_names; | |
5713 | ||
5714 | tdesc_data = tdesc_data_alloc (); | |
5715 | ||
3ce1502b | 5716 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 5717 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 5718 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 5719 | |
90884b2b L |
5720 | /* Target description may be changed. */ |
5721 | tdesc = tdep->tdesc; | |
5722 | ||
5723 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) | |
5724 | { | |
5725 | tdesc_data_cleanup (tdesc_data); | |
5726 | xfree (tdep); | |
5727 | gdbarch_free (gdbarch); | |
5728 | return NULL; | |
5729 | } | |
5730 | ||
5731 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
5732 | ||
5733 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
5734 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
5735 | ||
06da04c6 | 5736 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
10458914 DJ |
5737 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
5738 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 5739 | |
8446b36a MK |
5740 | /* If we have a register mapping, enable the generic core file |
5741 | support, unless it has already been enabled. */ | |
5742 | if (tdep->gregset_reg_offset | |
5743 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
5744 | set_gdbarch_regset_from_core_section (gdbarch, | |
5745 | i386_regset_from_core_section); | |
5746 | ||
5716833c MK |
5747 | /* Unless support for MMX has been disabled, make %mm0 the first |
5748 | pseudo-register. */ | |
5749 | if (tdep->mm0_regnum == 0) | |
5750 | tdep->mm0_regnum = gdbarch_num_regs (gdbarch); | |
5751 | ||
514f746b AR |
5752 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
5753 | i386_skip_permanent_breakpoint); | |
5754 | ||
7a697b8d SS |
5755 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
5756 | i386_fast_tracepoint_valid_at); | |
5757 | ||
a62cc96e AC |
5758 | return gdbarch; |
5759 | } | |
5760 | ||
8201327c MK |
5761 | static enum gdb_osabi |
5762 | i386_coff_osabi_sniffer (bfd *abfd) | |
5763 | { | |
762c5349 MK |
5764 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
5765 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
5766 | return GDB_OSABI_GO32; |
5767 | ||
5768 | return GDB_OSABI_UNKNOWN; | |
5769 | } | |
8201327c MK |
5770 | \f |
5771 | ||
28e9e0f0 MK |
5772 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
5773 | void _initialize_i386_tdep (void); | |
5774 | ||
c906108c | 5775 | void |
fba45db2 | 5776 | _initialize_i386_tdep (void) |
c906108c | 5777 | { |
a62cc96e AC |
5778 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
5779 | ||
fc338970 | 5780 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
5781 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
5782 | &disassembly_flavor, _("\ | |
5783 | Set the disassembly flavor."), _("\ | |
5784 | Show the disassembly flavor."), _("\ | |
5785 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
5786 | NULL, | |
5787 | NULL, /* FIXME: i18n: */ | |
5788 | &setlist, &showlist); | |
8201327c MK |
5789 | |
5790 | /* Add the variable that controls the convention for returning | |
5791 | structs. */ | |
7ab04401 AC |
5792 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
5793 | &struct_convention, _("\ | |
5794 | Set the convention for returning small structs."), _("\ | |
5795 | Show the convention for returning small structs."), _("\ | |
5796 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
5797 | is \"default\"."), | |
5798 | NULL, | |
5799 | NULL, /* FIXME: i18n: */ | |
5800 | &setlist, &showlist); | |
8201327c MK |
5801 | |
5802 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
5803 | i386_coff_osabi_sniffer); | |
8201327c | 5804 | |
05816f70 | 5805 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 5806 | i386_svr4_init_abi); |
05816f70 | 5807 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 5808 | i386_go32_init_abi); |
38c968cf | 5809 | |
209bd28e | 5810 | /* Initialize the i386-specific register groups. */ |
38c968cf | 5811 | i386_init_reggroups (); |
90884b2b L |
5812 | |
5813 | /* Initialize the standard target descriptions. */ | |
5814 | initialize_tdesc_i386 (); | |
c906108c | 5815 | } |