Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 JB |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
5 | 2010 Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
7a697b8d | 46 | #include "disasm.h" |
c8d5aac9 | 47 | #include "remote.h" |
acd5c798 | 48 | |
3d261580 | 49 | #include "gdb_assert.h" |
acd5c798 | 50 | #include "gdb_string.h" |
3d261580 | 51 | |
d2a7c97a | 52 | #include "i386-tdep.h" |
61113f8b | 53 | #include "i387-tdep.h" |
d2a7c97a | 54 | |
7ad10968 HZ |
55 | #include "record.h" |
56 | #include <stdint.h> | |
57 | ||
90884b2b L |
58 | #include "features/i386/i386.c" |
59 | ||
c4fc7f1b | 60 | /* Register names. */ |
c40e1eab | 61 | |
90884b2b | 62 | static const char *i386_register_names[] = |
fc633446 MK |
63 | { |
64 | "eax", "ecx", "edx", "ebx", | |
65 | "esp", "ebp", "esi", "edi", | |
66 | "eip", "eflags", "cs", "ss", | |
67 | "ds", "es", "fs", "gs", | |
68 | "st0", "st1", "st2", "st3", | |
69 | "st4", "st5", "st6", "st7", | |
70 | "fctrl", "fstat", "ftag", "fiseg", | |
71 | "fioff", "foseg", "fooff", "fop", | |
72 | "xmm0", "xmm1", "xmm2", "xmm3", | |
73 | "xmm4", "xmm5", "xmm6", "xmm7", | |
74 | "mxcsr" | |
75 | }; | |
76 | ||
c4fc7f1b | 77 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 78 | |
90884b2b | 79 | static const char *i386_mmx_names[] = |
28fc6740 AC |
80 | { |
81 | "mm0", "mm1", "mm2", "mm3", | |
82 | "mm4", "mm5", "mm6", "mm7" | |
83 | }; | |
c40e1eab | 84 | |
1ba53b71 L |
85 | /* Register names for byte pseudo-registers. */ |
86 | ||
87 | static const char *i386_byte_names[] = | |
88 | { | |
89 | "al", "cl", "dl", "bl", | |
90 | "ah", "ch", "dh", "bh" | |
91 | }; | |
92 | ||
93 | /* Register names for word pseudo-registers. */ | |
94 | ||
95 | static const char *i386_word_names[] = | |
96 | { | |
97 | "ax", "cx", "dx", "bx", | |
9cad29ac | 98 | "", "bp", "si", "di" |
1ba53b71 L |
99 | }; |
100 | ||
101 | /* MMX register? */ | |
c40e1eab | 102 | |
28fc6740 | 103 | static int |
5716833c | 104 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 105 | { |
1ba53b71 L |
106 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
107 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
108 | |
109 | if (mm0_regnum < 0) | |
110 | return 0; | |
111 | ||
1ba53b71 L |
112 | regnum -= mm0_regnum; |
113 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
114 | } | |
115 | ||
116 | /* Byte register? */ | |
117 | ||
118 | int | |
119 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
120 | { | |
121 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
122 | ||
123 | regnum -= tdep->al_regnum; | |
124 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
125 | } | |
126 | ||
127 | /* Word register? */ | |
128 | ||
129 | int | |
130 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
131 | { | |
132 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
133 | ||
134 | regnum -= tdep->ax_regnum; | |
135 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
136 | } | |
137 | ||
138 | /* Dword register? */ | |
139 | ||
140 | int | |
141 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
142 | { | |
143 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
144 | int eax_regnum = tdep->eax_regnum; | |
145 | ||
146 | if (eax_regnum < 0) | |
147 | return 0; | |
148 | ||
149 | regnum -= eax_regnum; | |
150 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
151 | } |
152 | ||
5716833c | 153 | /* SSE register? */ |
23a34459 | 154 | |
5716833c MK |
155 | static int |
156 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 157 | { |
5716833c MK |
158 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
159 | ||
20a6ec49 | 160 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
161 | return 0; |
162 | ||
20a6ec49 MD |
163 | return (I387_XMM0_REGNUM (tdep) <= regnum |
164 | && regnum < I387_MXCSR_REGNUM (tdep)); | |
23a34459 AC |
165 | } |
166 | ||
5716833c MK |
167 | static int |
168 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 169 | { |
5716833c MK |
170 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
171 | ||
20a6ec49 | 172 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
173 | return 0; |
174 | ||
20a6ec49 | 175 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
176 | } |
177 | ||
5716833c | 178 | /* FP register? */ |
23a34459 AC |
179 | |
180 | int | |
20a6ec49 | 181 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 182 | { |
20a6ec49 MD |
183 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
184 | ||
185 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
186 | return 0; |
187 | ||
20a6ec49 MD |
188 | return (I387_ST0_REGNUM (tdep) <= regnum |
189 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
190 | } |
191 | ||
192 | int | |
20a6ec49 | 193 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 194 | { |
20a6ec49 MD |
195 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
196 | ||
197 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
198 | return 0; |
199 | ||
20a6ec49 MD |
200 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
201 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
202 | } |
203 | ||
30b0e2d8 | 204 | /* Return the name of register REGNUM. */ |
fc633446 | 205 | |
1ba53b71 | 206 | const char * |
90884b2b | 207 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 208 | { |
1ba53b71 L |
209 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
210 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
211 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
212 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
213 | return i386_byte_names[regnum - tdep->al_regnum]; | |
214 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
215 | return i386_word_names[regnum - tdep->ax_regnum]; | |
216 | ||
217 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
218 | } |
219 | ||
c4fc7f1b | 220 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
221 | number used by GDB. */ |
222 | ||
8201327c | 223 | static int |
d3f73121 | 224 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 225 | { |
20a6ec49 MD |
226 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
227 | ||
c4fc7f1b MK |
228 | /* This implements what GCC calls the "default" register map |
229 | (dbx_register_map[]). */ | |
230 | ||
85540d8c MK |
231 | if (reg >= 0 && reg <= 7) |
232 | { | |
9872ad24 JB |
233 | /* General-purpose registers. The debug info calls %ebp |
234 | register 4, and %esp register 5. */ | |
235 | if (reg == 4) | |
236 | return 5; | |
237 | else if (reg == 5) | |
238 | return 4; | |
239 | else return reg; | |
85540d8c MK |
240 | } |
241 | else if (reg >= 12 && reg <= 19) | |
242 | { | |
243 | /* Floating-point registers. */ | |
20a6ec49 | 244 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
245 | } |
246 | else if (reg >= 21 && reg <= 28) | |
247 | { | |
248 | /* SSE registers. */ | |
20a6ec49 | 249 | return reg - 21 + I387_XMM0_REGNUM (tdep); |
85540d8c MK |
250 | } |
251 | else if (reg >= 29 && reg <= 36) | |
252 | { | |
253 | /* MMX registers. */ | |
20a6ec49 | 254 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
255 | } |
256 | ||
257 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 258 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
259 | } |
260 | ||
c4fc7f1b MK |
261 | /* Convert SVR4 register number REG to the appropriate register number |
262 | used by GDB. */ | |
85540d8c | 263 | |
8201327c | 264 | static int |
d3f73121 | 265 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 266 | { |
20a6ec49 MD |
267 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
268 | ||
c4fc7f1b MK |
269 | /* This implements the GCC register map that tries to be compatible |
270 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
271 | ||
272 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
273 | numbers the floating point registers differently. */ |
274 | if (reg >= 0 && reg <= 9) | |
275 | { | |
acd5c798 | 276 | /* General-purpose registers. */ |
85540d8c MK |
277 | return reg; |
278 | } | |
279 | else if (reg >= 11 && reg <= 18) | |
280 | { | |
281 | /* Floating-point registers. */ | |
20a6ec49 | 282 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 283 | } |
c6f4c129 | 284 | else if (reg >= 21 && reg <= 36) |
85540d8c | 285 | { |
c4fc7f1b | 286 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 287 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
288 | } |
289 | ||
c6f4c129 JB |
290 | switch (reg) |
291 | { | |
20a6ec49 MD |
292 | case 37: return I387_FCTRL_REGNUM (tdep); |
293 | case 38: return I387_FSTAT_REGNUM (tdep); | |
294 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
295 | case 40: return I386_ES_REGNUM; |
296 | case 41: return I386_CS_REGNUM; | |
297 | case 42: return I386_SS_REGNUM; | |
298 | case 43: return I386_DS_REGNUM; | |
299 | case 44: return I386_FS_REGNUM; | |
300 | case 45: return I386_GS_REGNUM; | |
301 | } | |
302 | ||
85540d8c | 303 | /* This will hopefully provoke a warning. */ |
d3f73121 | 304 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 305 | } |
5716833c | 306 | |
fc338970 | 307 | \f |
917317f4 | 308 | |
fc338970 MK |
309 | /* This is the variable that is set with "set disassembly-flavor", and |
310 | its legitimate values. */ | |
53904c9e AC |
311 | static const char att_flavor[] = "att"; |
312 | static const char intel_flavor[] = "intel"; | |
313 | static const char *valid_flavors[] = | |
c5aa993b | 314 | { |
c906108c SS |
315 | att_flavor, |
316 | intel_flavor, | |
317 | NULL | |
318 | }; | |
53904c9e | 319 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 320 | \f |
c906108c | 321 | |
acd5c798 MK |
322 | /* Use the program counter to determine the contents and size of a |
323 | breakpoint instruction. Return a pointer to a string of bytes that | |
324 | encode a breakpoint instruction, store the length of the string in | |
325 | *LEN and optionally adjust *PC to point to the correct memory | |
326 | location for inserting the breakpoint. | |
c906108c | 327 | |
acd5c798 MK |
328 | On the i386 we have a single breakpoint that fits in a single byte |
329 | and can be inserted anywhere. | |
c906108c | 330 | |
acd5c798 | 331 | This function is 64-bit safe. */ |
63c0089f MK |
332 | |
333 | static const gdb_byte * | |
67d57894 | 334 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 335 | { |
63c0089f MK |
336 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
337 | ||
acd5c798 MK |
338 | *len = sizeof (break_insn); |
339 | return break_insn; | |
c906108c | 340 | } |
237fc4c9 PA |
341 | \f |
342 | /* Displaced instruction handling. */ | |
343 | ||
1903f0e6 DE |
344 | /* Skip the legacy instruction prefixes in INSN. |
345 | Not all prefixes are valid for any particular insn | |
346 | but we needn't care, the insn will fault if it's invalid. | |
347 | The result is a pointer to the first opcode byte, | |
348 | or NULL if we run off the end of the buffer. */ | |
349 | ||
350 | static gdb_byte * | |
351 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
352 | { | |
353 | gdb_byte *end = insn + max_len; | |
354 | ||
355 | while (insn < end) | |
356 | { | |
357 | switch (*insn) | |
358 | { | |
359 | case DATA_PREFIX_OPCODE: | |
360 | case ADDR_PREFIX_OPCODE: | |
361 | case CS_PREFIX_OPCODE: | |
362 | case DS_PREFIX_OPCODE: | |
363 | case ES_PREFIX_OPCODE: | |
364 | case FS_PREFIX_OPCODE: | |
365 | case GS_PREFIX_OPCODE: | |
366 | case SS_PREFIX_OPCODE: | |
367 | case LOCK_PREFIX_OPCODE: | |
368 | case REPE_PREFIX_OPCODE: | |
369 | case REPNE_PREFIX_OPCODE: | |
370 | ++insn; | |
371 | continue; | |
372 | default: | |
373 | return insn; | |
374 | } | |
375 | } | |
376 | ||
377 | return NULL; | |
378 | } | |
237fc4c9 PA |
379 | |
380 | static int | |
1903f0e6 | 381 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 PA |
382 | { |
383 | /* jmp far (absolute address in operand) */ | |
384 | if (insn[0] == 0xea) | |
385 | return 1; | |
386 | ||
387 | if (insn[0] == 0xff) | |
388 | { | |
389 | /* jump near, absolute indirect (/4) */ | |
390 | if ((insn[1] & 0x38) == 0x20) | |
391 | return 1; | |
392 | ||
393 | /* jump far, absolute indirect (/5) */ | |
394 | if ((insn[1] & 0x38) == 0x28) | |
395 | return 1; | |
396 | } | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static int | |
1903f0e6 | 402 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 PA |
403 | { |
404 | /* call far, absolute */ | |
405 | if (insn[0] == 0x9a) | |
406 | return 1; | |
407 | ||
408 | if (insn[0] == 0xff) | |
409 | { | |
410 | /* Call near, absolute indirect (/2) */ | |
411 | if ((insn[1] & 0x38) == 0x10) | |
412 | return 1; | |
413 | ||
414 | /* Call far, absolute indirect (/3) */ | |
415 | if ((insn[1] & 0x38) == 0x18) | |
416 | return 1; | |
417 | } | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
422 | static int | |
1903f0e6 | 423 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
424 | { |
425 | switch (insn[0]) | |
426 | { | |
427 | case 0xc2: /* ret near, pop N bytes */ | |
428 | case 0xc3: /* ret near */ | |
429 | case 0xca: /* ret far, pop N bytes */ | |
430 | case 0xcb: /* ret far */ | |
431 | case 0xcf: /* iret */ | |
432 | return 1; | |
433 | ||
434 | default: | |
435 | return 0; | |
436 | } | |
437 | } | |
438 | ||
439 | static int | |
1903f0e6 | 440 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
441 | { |
442 | if (i386_absolute_call_p (insn)) | |
443 | return 1; | |
444 | ||
445 | /* call near, relative */ | |
446 | if (insn[0] == 0xe8) | |
447 | return 1; | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
237fc4c9 PA |
452 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
453 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 454 | |
237fc4c9 | 455 | static int |
1903f0e6 | 456 | i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp) |
237fc4c9 PA |
457 | { |
458 | if (insn[0] == 0xcd) | |
459 | { | |
460 | *lengthp = 2; | |
461 | return 1; | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | /* Fix up the state of registers and memory after having single-stepped | |
468 | a displaced instruction. */ | |
1903f0e6 | 469 | |
237fc4c9 PA |
470 | void |
471 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
472 | struct displaced_step_closure *closure, | |
473 | CORE_ADDR from, CORE_ADDR to, | |
474 | struct regcache *regs) | |
475 | { | |
e17a4113 UW |
476 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
477 | ||
237fc4c9 PA |
478 | /* The offset we applied to the instruction's address. |
479 | This could well be negative (when viewed as a signed 32-bit | |
480 | value), but ULONGEST won't reflect that, so take care when | |
481 | applying it. */ | |
482 | ULONGEST insn_offset = to - from; | |
483 | ||
484 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
485 | copy of the instruction. */ | |
486 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
487 | /* The start of the insn, needed in case we see some prefixes. */ |
488 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
489 | |
490 | if (debug_displaced) | |
491 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 492 | "displaced: fixup (%s, %s), " |
237fc4c9 | 493 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
494 | paddress (gdbarch, from), paddress (gdbarch, to), |
495 | insn[0], insn[1]); | |
237fc4c9 PA |
496 | |
497 | /* The list of issues to contend with here is taken from | |
498 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
499 | Yay for Free Software! */ | |
500 | ||
501 | /* Relocate the %eip, if necessary. */ | |
502 | ||
1903f0e6 DE |
503 | /* The instruction recognizers we use assume any leading prefixes |
504 | have been skipped. */ | |
505 | { | |
506 | /* This is the size of the buffer in closure. */ | |
507 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
508 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
509 | /* If there are too many prefixes, just ignore the insn. | |
510 | It will fault when run. */ | |
511 | if (opcode != NULL) | |
512 | insn = opcode; | |
513 | } | |
514 | ||
237fc4c9 PA |
515 | /* Except in the case of absolute or indirect jump or call |
516 | instructions, or a return instruction, the new eip is relative to | |
517 | the displaced instruction; make it relative. Well, signal | |
518 | handler returns don't need relocation either, but we use the | |
519 | value of %eip to recognize those; see below. */ | |
520 | if (! i386_absolute_jmp_p (insn) | |
521 | && ! i386_absolute_call_p (insn) | |
522 | && ! i386_ret_p (insn)) | |
523 | { | |
524 | ULONGEST orig_eip; | |
525 | ULONGEST insn_len; | |
526 | ||
527 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
528 | ||
529 | /* A signal trampoline system call changes the %eip, resuming | |
530 | execution of the main program after the signal handler has | |
531 | returned. That makes them like 'return' instructions; we | |
532 | shouldn't relocate %eip. | |
533 | ||
534 | But most system calls don't, and we do need to relocate %eip. | |
535 | ||
536 | Our heuristic for distinguishing these cases: if stepping | |
537 | over the system call instruction left control directly after | |
538 | the instruction, the we relocate --- control almost certainly | |
539 | doesn't belong in the displaced copy. Otherwise, we assume | |
540 | the instruction has put control where it belongs, and leave | |
541 | it unrelocated. Goodness help us if there are PC-relative | |
542 | system calls. */ | |
543 | if (i386_syscall_p (insn, &insn_len) | |
1903f0e6 | 544 | && orig_eip != to + (insn - insn_start) + insn_len) |
237fc4c9 PA |
545 | { |
546 | if (debug_displaced) | |
547 | fprintf_unfiltered (gdb_stdlog, | |
548 | "displaced: syscall changed %%eip; " | |
549 | "not relocating\n"); | |
550 | } | |
551 | else | |
552 | { | |
553 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
554 | ||
1903f0e6 DE |
555 | /* If we just stepped over a breakpoint insn, we don't backup |
556 | the pc on purpose; this is to match behaviour without | |
557 | stepping. */ | |
237fc4c9 PA |
558 | |
559 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
560 | ||
561 | if (debug_displaced) | |
562 | fprintf_unfiltered (gdb_stdlog, | |
563 | "displaced: " | |
5af949e3 UW |
564 | "relocated %%eip from %s to %s\n", |
565 | paddress (gdbarch, orig_eip), | |
566 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
567 | } |
568 | } | |
569 | ||
570 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
571 | pushed value, and should be cleared. We'll leave this for later, | |
572 | since GDB already messes up the TF flag when stepping over a | |
573 | pushfl. */ | |
574 | ||
575 | /* If the instruction was a call, the return address now atop the | |
576 | stack is the address following the copied instruction. We need | |
577 | to make it the address following the original instruction. */ | |
578 | if (i386_call_p (insn)) | |
579 | { | |
580 | ULONGEST esp; | |
581 | ULONGEST retaddr; | |
582 | const ULONGEST retaddr_len = 4; | |
583 | ||
584 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 585 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 586 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 587 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
588 | |
589 | if (debug_displaced) | |
590 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
591 | "displaced: relocated return addr at %s to %s\n", |
592 | paddress (gdbarch, esp), | |
593 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
594 | } |
595 | } | |
fc338970 | 596 | \f |
acd5c798 MK |
597 | #ifdef I386_REGNO_TO_SYMMETRY |
598 | #error "The Sequent Symmetry is no longer supported." | |
599 | #endif | |
c906108c | 600 | |
acd5c798 MK |
601 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
602 | and %esp "belong" to the calling function. Therefore these | |
603 | registers should be saved if they're going to be modified. */ | |
c906108c | 604 | |
acd5c798 MK |
605 | /* The maximum number of saved registers. This should include all |
606 | registers mentioned above, and %eip. */ | |
a3386186 | 607 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
608 | |
609 | struct i386_frame_cache | |
c906108c | 610 | { |
acd5c798 MK |
611 | /* Base address. */ |
612 | CORE_ADDR base; | |
772562f8 | 613 | LONGEST sp_offset; |
acd5c798 MK |
614 | CORE_ADDR pc; |
615 | ||
fd13a04a AC |
616 | /* Saved registers. */ |
617 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 618 | CORE_ADDR saved_sp; |
e0c62198 | 619 | int saved_sp_reg; |
acd5c798 MK |
620 | int pc_in_eax; |
621 | ||
622 | /* Stack space reserved for local variables. */ | |
623 | long locals; | |
624 | }; | |
625 | ||
626 | /* Allocate and initialize a frame cache. */ | |
627 | ||
628 | static struct i386_frame_cache * | |
fd13a04a | 629 | i386_alloc_frame_cache (void) |
acd5c798 MK |
630 | { |
631 | struct i386_frame_cache *cache; | |
632 | int i; | |
633 | ||
634 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
635 | ||
636 | /* Base address. */ | |
637 | cache->base = 0; | |
638 | cache->sp_offset = -4; | |
639 | cache->pc = 0; | |
640 | ||
fd13a04a AC |
641 | /* Saved registers. We initialize these to -1 since zero is a valid |
642 | offset (that's where %ebp is supposed to be stored). */ | |
643 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
644 | cache->saved_regs[i] = -1; | |
acd5c798 | 645 | cache->saved_sp = 0; |
e0c62198 | 646 | cache->saved_sp_reg = -1; |
acd5c798 MK |
647 | cache->pc_in_eax = 0; |
648 | ||
649 | /* Frameless until proven otherwise. */ | |
650 | cache->locals = -1; | |
651 | ||
652 | return cache; | |
653 | } | |
c906108c | 654 | |
acd5c798 MK |
655 | /* If the instruction at PC is a jump, return the address of its |
656 | target. Otherwise, return PC. */ | |
c906108c | 657 | |
acd5c798 | 658 | static CORE_ADDR |
e17a4113 | 659 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 660 | { |
e17a4113 | 661 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 662 | gdb_byte op; |
acd5c798 MK |
663 | long delta = 0; |
664 | int data16 = 0; | |
c906108c | 665 | |
8defab1a | 666 | target_read_memory (pc, &op, 1); |
acd5c798 | 667 | if (op == 0x66) |
c906108c | 668 | { |
c906108c | 669 | data16 = 1; |
e17a4113 | 670 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
671 | } |
672 | ||
acd5c798 | 673 | switch (op) |
c906108c SS |
674 | { |
675 | case 0xe9: | |
fc338970 | 676 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
677 | if (data16) |
678 | { | |
e17a4113 | 679 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 680 | |
fc338970 MK |
681 | /* Include the size of the jmp instruction (including the |
682 | 0x66 prefix). */ | |
acd5c798 | 683 | delta += 4; |
c906108c SS |
684 | } |
685 | else | |
686 | { | |
e17a4113 | 687 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 688 | |
acd5c798 MK |
689 | /* Include the size of the jmp instruction. */ |
690 | delta += 5; | |
c906108c SS |
691 | } |
692 | break; | |
693 | case 0xeb: | |
fc338970 | 694 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 695 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 696 | |
acd5c798 | 697 | delta += data16 + 2; |
c906108c SS |
698 | break; |
699 | } | |
c906108c | 700 | |
acd5c798 MK |
701 | return pc + delta; |
702 | } | |
fc338970 | 703 | |
acd5c798 MK |
704 | /* Check whether PC points at a prologue for a function returning a |
705 | structure or union. If so, it updates CACHE and returns the | |
706 | address of the first instruction after the code sequence that | |
707 | removes the "hidden" argument from the stack or CURRENT_PC, | |
708 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 709 | |
acd5c798 MK |
710 | static CORE_ADDR |
711 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
712 | struct i386_frame_cache *cache) | |
c906108c | 713 | { |
acd5c798 MK |
714 | /* Functions that return a structure or union start with: |
715 | ||
716 | popl %eax 0x58 | |
717 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
718 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
719 | ||
720 | (the System V compiler puts out the second `xchg' instruction, | |
721 | and the assembler doesn't try to optimize it, so the 'sib' form | |
722 | gets generated). This sequence is used to get the address of the | |
723 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
724 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
725 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
726 | gdb_byte buf[4]; | |
727 | gdb_byte op; | |
c906108c | 728 | |
acd5c798 MK |
729 | if (current_pc <= pc) |
730 | return pc; | |
731 | ||
8defab1a | 732 | target_read_memory (pc, &op, 1); |
c906108c | 733 | |
acd5c798 MK |
734 | if (op != 0x58) /* popl %eax */ |
735 | return pc; | |
c906108c | 736 | |
8defab1a | 737 | target_read_memory (pc + 1, buf, 4); |
acd5c798 MK |
738 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
739 | return pc; | |
c906108c | 740 | |
acd5c798 | 741 | if (current_pc == pc) |
c906108c | 742 | { |
acd5c798 MK |
743 | cache->sp_offset += 4; |
744 | return current_pc; | |
c906108c SS |
745 | } |
746 | ||
acd5c798 | 747 | if (current_pc == pc + 1) |
c906108c | 748 | { |
acd5c798 MK |
749 | cache->pc_in_eax = 1; |
750 | return current_pc; | |
751 | } | |
752 | ||
753 | if (buf[1] == proto1[1]) | |
754 | return pc + 4; | |
755 | else | |
756 | return pc + 5; | |
757 | } | |
758 | ||
759 | static CORE_ADDR | |
760 | i386_skip_probe (CORE_ADDR pc) | |
761 | { | |
762 | /* A function may start with | |
fc338970 | 763 | |
acd5c798 MK |
764 | pushl constant |
765 | call _probe | |
766 | addl $4, %esp | |
fc338970 | 767 | |
acd5c798 MK |
768 | followed by |
769 | ||
770 | pushl %ebp | |
fc338970 | 771 | |
acd5c798 | 772 | etc. */ |
63c0089f MK |
773 | gdb_byte buf[8]; |
774 | gdb_byte op; | |
fc338970 | 775 | |
8defab1a | 776 | target_read_memory (pc, &op, 1); |
acd5c798 MK |
777 | |
778 | if (op == 0x68 || op == 0x6a) | |
779 | { | |
780 | int delta; | |
c906108c | 781 | |
acd5c798 MK |
782 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
783 | four-byte operand, depending on the opcode. */ | |
c906108c | 784 | if (op == 0x68) |
acd5c798 | 785 | delta = 5; |
c906108c | 786 | else |
acd5c798 | 787 | delta = 2; |
c906108c | 788 | |
acd5c798 MK |
789 | /* Read the following 8 bytes, which should be `call _probe' (6 |
790 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
791 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 792 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 793 | pc += delta + sizeof (buf); |
c906108c SS |
794 | } |
795 | ||
acd5c798 MK |
796 | return pc; |
797 | } | |
798 | ||
92dd43fa MK |
799 | /* GCC 4.1 and later, can put code in the prologue to realign the |
800 | stack pointer. Check whether PC points to such code, and update | |
801 | CACHE accordingly. Return the first instruction after the code | |
802 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
803 | recognize the code, return PC. */ | |
804 | ||
805 | static CORE_ADDR | |
806 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
807 | struct i386_frame_cache *cache) | |
808 | { | |
e0c62198 L |
809 | /* There are 2 code sequences to re-align stack before the frame |
810 | gets set up: | |
811 | ||
812 | 1. Use a caller-saved saved register: | |
813 | ||
814 | leal 4(%esp), %reg | |
815 | andl $-XXX, %esp | |
816 | pushl -4(%reg) | |
817 | ||
818 | 2. Use a callee-saved saved register: | |
819 | ||
820 | pushl %reg | |
821 | leal 8(%esp), %reg | |
822 | andl $-XXX, %esp | |
823 | pushl -4(%reg) | |
824 | ||
825 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
826 | ||
827 | 0x83 0xe4 0xf0 andl $-16, %esp | |
828 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
829 | */ | |
830 | ||
831 | gdb_byte buf[14]; | |
832 | int reg; | |
833 | int offset, offset_and; | |
834 | static int regnums[8] = { | |
835 | I386_EAX_REGNUM, /* %eax */ | |
836 | I386_ECX_REGNUM, /* %ecx */ | |
837 | I386_EDX_REGNUM, /* %edx */ | |
838 | I386_EBX_REGNUM, /* %ebx */ | |
839 | I386_ESP_REGNUM, /* %esp */ | |
840 | I386_EBP_REGNUM, /* %ebp */ | |
841 | I386_ESI_REGNUM, /* %esi */ | |
842 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 843 | }; |
92dd43fa | 844 | |
e0c62198 L |
845 | if (target_read_memory (pc, buf, sizeof buf)) |
846 | return pc; | |
847 | ||
848 | /* Check caller-saved saved register. The first instruction has | |
849 | to be "leal 4(%esp), %reg". */ | |
850 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
851 | { | |
852 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
853 | if ((buf[1] & 0xc7) != 0x44) | |
854 | return pc; | |
855 | ||
856 | /* REG has register number. */ | |
857 | reg = (buf[1] >> 3) & 7; | |
858 | offset = 4; | |
859 | } | |
860 | else | |
861 | { | |
862 | /* Check callee-saved saved register. The first instruction | |
863 | has to be "pushl %reg". */ | |
864 | if ((buf[0] & 0xf8) != 0x50) | |
865 | return pc; | |
866 | ||
867 | /* Get register. */ | |
868 | reg = buf[0] & 0x7; | |
869 | ||
870 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
871 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
872 | return pc; | |
873 | ||
874 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
875 | if ((buf[2] & 0xc7) != 0x44) | |
876 | return pc; | |
877 | ||
878 | /* REG has register number. Registers in pushl and leal have to | |
879 | be the same. */ | |
880 | if (reg != ((buf[2] >> 3) & 7)) | |
881 | return pc; | |
882 | ||
883 | offset = 5; | |
884 | } | |
885 | ||
886 | /* Rigister can't be %esp nor %ebp. */ | |
887 | if (reg == 4 || reg == 5) | |
888 | return pc; | |
889 | ||
890 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
891 | if (buf[offset + 1] != 0xe4 | |
892 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
893 | return pc; | |
894 | ||
895 | offset_and = offset; | |
896 | offset += buf[offset] == 0x81 ? 6 : 3; | |
897 | ||
898 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
899 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
900 | if (buf[offset] != 0xff | |
901 | || buf[offset + 2] != 0xfc | |
902 | || (buf[offset + 1] & 0xf8) != 0x70) | |
903 | return pc; | |
904 | ||
905 | /* R/M has register. Registers in leal and pushl have to be the | |
906 | same. */ | |
907 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
908 | return pc; |
909 | ||
e0c62198 L |
910 | if (current_pc > pc + offset_and) |
911 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 912 | |
e0c62198 | 913 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
914 | } |
915 | ||
37bdc87e | 916 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 917 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
918 | |
919 | /* Instruction description. */ | |
920 | struct i386_insn | |
921 | { | |
922 | size_t len; | |
237fc4c9 PA |
923 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
924 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
925 | }; |
926 | ||
927 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
928 | the first instruction description that matches. Otherwise, return | |
929 | NULL. */ | |
930 | ||
931 | static struct i386_insn * | |
932 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
933 | { | |
934 | struct i386_insn *insn; | |
63c0089f | 935 | gdb_byte op; |
37bdc87e | 936 | |
8defab1a | 937 | target_read_memory (pc, &op, 1); |
37bdc87e MK |
938 | |
939 | for (insn = skip_insns; insn->len > 0; insn++) | |
940 | { | |
941 | if ((op & insn->mask[0]) == insn->insn[0]) | |
942 | { | |
237fc4c9 | 943 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
613e8135 | 944 | int insn_matched = 1; |
37bdc87e MK |
945 | size_t i; |
946 | ||
947 | gdb_assert (insn->len > 1); | |
237fc4c9 | 948 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
37bdc87e | 949 | |
8defab1a | 950 | target_read_memory (pc + 1, buf, insn->len - 1); |
37bdc87e MK |
951 | for (i = 1; i < insn->len; i++) |
952 | { | |
953 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 954 | insn_matched = 0; |
37bdc87e | 955 | } |
613e8135 MK |
956 | |
957 | if (insn_matched) | |
958 | return insn; | |
37bdc87e MK |
959 | } |
960 | } | |
961 | ||
962 | return NULL; | |
963 | } | |
964 | ||
965 | /* Some special instructions that might be migrated by GCC into the | |
966 | part of the prologue that sets up the new stack frame. Because the | |
967 | stack frame hasn't been setup yet, no registers have been saved | |
968 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
969 | touched. */ | |
970 | ||
971 | struct i386_insn i386_frame_setup_skip_insns[] = | |
972 | { | |
973 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
974 | ||
975 | ??? Should we handle 16-bit operand-sizes here? */ | |
976 | ||
977 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
978 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
979 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
980 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
981 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
982 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
983 | { 5, { 0xb8 }, { 0xfe } }, | |
984 | /* `movl imm32, %edx' */ | |
985 | { 5, { 0xba }, { 0xff } }, | |
986 | ||
987 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
988 | encoding for `mov m32, %eax'. | |
989 | ||
990 | ??? Should we handle SIB adressing here? | |
991 | ??? Should we handle 16-bit operand-sizes here? */ | |
992 | ||
993 | /* `movl m32, %eax' */ | |
994 | { 5, { 0xa1 }, { 0xff } }, | |
995 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
996 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
997 | /* `movl m32, %edx' */ | |
998 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
999 | ||
1000 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1001 | Because of the symmetry, there are actually two ways to encode | |
1002 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1003 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1004 | ||
1005 | /* `subl %eax, %eax' */ | |
1006 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1007 | /* `subl %ecx, %ecx' */ | |
1008 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1009 | /* `subl %edx, %edx' */ | |
1010 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1011 | /* `xorl %eax, %eax' */ | |
1012 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1013 | /* `xorl %ecx, %ecx' */ | |
1014 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1015 | /* `xorl %edx, %edx' */ | |
1016 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1017 | { 0 } | |
1018 | }; | |
1019 | ||
e11481da PM |
1020 | |
1021 | /* Check whether PC points to a no-op instruction. */ | |
1022 | static CORE_ADDR | |
1023 | i386_skip_noop (CORE_ADDR pc) | |
1024 | { | |
1025 | gdb_byte op; | |
1026 | int check = 1; | |
1027 | ||
8defab1a | 1028 | target_read_memory (pc, &op, 1); |
e11481da PM |
1029 | |
1030 | while (check) | |
1031 | { | |
1032 | check = 0; | |
1033 | /* Ignore `nop' instruction. */ | |
1034 | if (op == 0x90) | |
1035 | { | |
1036 | pc += 1; | |
8defab1a | 1037 | target_read_memory (pc, &op, 1); |
e11481da PM |
1038 | check = 1; |
1039 | } | |
1040 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1041 | Microsoft system dlls often start with | |
1042 | a `mov %edi,%edi' instruction. | |
1043 | The 5 bytes before the function start are | |
1044 | filled with `nop' instructions. | |
1045 | This pattern can be used for hot-patching: | |
1046 | The `mov %edi, %edi' instruction can be replaced by a | |
1047 | near jump to the location of the 5 `nop' instructions | |
1048 | which can be replaced by a 32-bit jump to anywhere | |
1049 | in the 32-bit address space. */ | |
1050 | ||
1051 | else if (op == 0x8b) | |
1052 | { | |
8defab1a | 1053 | target_read_memory (pc + 1, &op, 1); |
e11481da PM |
1054 | if (op == 0xff) |
1055 | { | |
1056 | pc += 2; | |
8defab1a | 1057 | target_read_memory (pc, &op, 1); |
e11481da PM |
1058 | check = 1; |
1059 | } | |
1060 | } | |
1061 | } | |
1062 | return pc; | |
1063 | } | |
1064 | ||
acd5c798 MK |
1065 | /* Check whether PC points at a code that sets up a new stack frame. |
1066 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1067 | instruction after the sequence that sets up the frame or LIMIT, |
1068 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1069 | |
1070 | static CORE_ADDR | |
e17a4113 UW |
1071 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1072 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1073 | struct i386_frame_cache *cache) |
1074 | { | |
e17a4113 | 1075 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1076 | struct i386_insn *insn; |
63c0089f | 1077 | gdb_byte op; |
26604a34 | 1078 | int skip = 0; |
acd5c798 | 1079 | |
37bdc87e MK |
1080 | if (limit <= pc) |
1081 | return limit; | |
acd5c798 | 1082 | |
8defab1a | 1083 | target_read_memory (pc, &op, 1); |
acd5c798 | 1084 | |
c906108c | 1085 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1086 | { |
acd5c798 MK |
1087 | /* Take into account that we've executed the `pushl %ebp' that |
1088 | starts this instruction sequence. */ | |
fd13a04a | 1089 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1090 | cache->sp_offset += 4; |
37bdc87e | 1091 | pc++; |
acd5c798 MK |
1092 | |
1093 | /* If that's all, return now. */ | |
37bdc87e MK |
1094 | if (limit <= pc) |
1095 | return limit; | |
26604a34 | 1096 | |
b4632131 | 1097 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1098 | GCC into the prologue and skip them. At this point in the |
1099 | prologue, code should only touch the scratch registers %eax, | |
1100 | %ecx and %edx, so while the number of posibilities is sheer, | |
1101 | it is limited. | |
5daa5b4e | 1102 | |
26604a34 MK |
1103 | Make sure we only skip these instructions if we later see the |
1104 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1105 | while (pc + skip < limit) |
26604a34 | 1106 | { |
37bdc87e MK |
1107 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1108 | if (insn == NULL) | |
1109 | break; | |
b4632131 | 1110 | |
37bdc87e | 1111 | skip += insn->len; |
26604a34 MK |
1112 | } |
1113 | ||
37bdc87e MK |
1114 | /* If that's all, return now. */ |
1115 | if (limit <= pc + skip) | |
1116 | return limit; | |
1117 | ||
8defab1a | 1118 | target_read_memory (pc + skip, &op, 1); |
37bdc87e | 1119 | |
26604a34 | 1120 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1121 | switch (op) |
c906108c SS |
1122 | { |
1123 | case 0x8b: | |
e17a4113 UW |
1124 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1125 | != 0xec) | |
37bdc87e | 1126 | return pc; |
c906108c SS |
1127 | break; |
1128 | case 0x89: | |
e17a4113 UW |
1129 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1130 | != 0xe5) | |
37bdc87e | 1131 | return pc; |
c906108c SS |
1132 | break; |
1133 | default: | |
37bdc87e | 1134 | return pc; |
c906108c | 1135 | } |
acd5c798 | 1136 | |
26604a34 MK |
1137 | /* OK, we actually have a frame. We just don't know how large |
1138 | it is yet. Set its size to zero. We'll adjust it if | |
1139 | necessary. We also now commit to skipping the special | |
1140 | instructions mentioned before. */ | |
acd5c798 | 1141 | cache->locals = 0; |
37bdc87e | 1142 | pc += (skip + 2); |
acd5c798 MK |
1143 | |
1144 | /* If that's all, return now. */ | |
37bdc87e MK |
1145 | if (limit <= pc) |
1146 | return limit; | |
acd5c798 | 1147 | |
fc338970 MK |
1148 | /* Check for stack adjustment |
1149 | ||
acd5c798 | 1150 | subl $XXX, %esp |
fc338970 | 1151 | |
fd35795f | 1152 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1153 | reg, so we don't have to worry about a data16 prefix. */ |
8defab1a | 1154 | target_read_memory (pc, &op, 1); |
c906108c SS |
1155 | if (op == 0x83) |
1156 | { | |
fd35795f | 1157 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1158 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1159 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1160 | return pc; |
acd5c798 | 1161 | |
37bdc87e MK |
1162 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1163 | make sense to be negative). */ | |
e17a4113 | 1164 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1165 | return pc + 3; |
c906108c SS |
1166 | } |
1167 | else if (op == 0x81) | |
1168 | { | |
fd35795f | 1169 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1170 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1171 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1172 | return pc; |
acd5c798 | 1173 | |
fd35795f | 1174 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1175 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1176 | return pc + 6; |
c906108c SS |
1177 | } |
1178 | else | |
1179 | { | |
acd5c798 | 1180 | /* Some instruction other than `subl'. */ |
37bdc87e | 1181 | return pc; |
c906108c SS |
1182 | } |
1183 | } | |
37bdc87e | 1184 | else if (op == 0xc8) /* enter */ |
c906108c | 1185 | { |
e17a4113 | 1186 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1187 | return pc + 4; |
c906108c | 1188 | } |
21d0e8a4 | 1189 | |
acd5c798 | 1190 | return pc; |
21d0e8a4 MK |
1191 | } |
1192 | ||
acd5c798 MK |
1193 | /* Check whether PC points at code that saves registers on the stack. |
1194 | If so, it updates CACHE and returns the address of the first | |
1195 | instruction after the register saves or CURRENT_PC, whichever is | |
1196 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1197 | |
1198 | static CORE_ADDR | |
acd5c798 MK |
1199 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1200 | struct i386_frame_cache *cache) | |
6bff26de | 1201 | { |
99ab4326 | 1202 | CORE_ADDR offset = 0; |
63c0089f | 1203 | gdb_byte op; |
99ab4326 | 1204 | int i; |
c0d1d883 | 1205 | |
99ab4326 MK |
1206 | if (cache->locals > 0) |
1207 | offset -= cache->locals; | |
1208 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1209 | { | |
8defab1a | 1210 | target_read_memory (pc, &op, 1); |
99ab4326 MK |
1211 | if (op < 0x50 || op > 0x57) |
1212 | break; | |
0d17c81d | 1213 | |
99ab4326 MK |
1214 | offset -= 4; |
1215 | cache->saved_regs[op - 0x50] = offset; | |
1216 | cache->sp_offset += 4; | |
1217 | pc++; | |
6bff26de MK |
1218 | } |
1219 | ||
acd5c798 | 1220 | return pc; |
22797942 AC |
1221 | } |
1222 | ||
acd5c798 MK |
1223 | /* Do a full analysis of the prologue at PC and update CACHE |
1224 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1225 | address where the analysis stopped. | |
ed84f6c1 | 1226 | |
fc338970 MK |
1227 | We handle these cases: |
1228 | ||
1229 | The startup sequence can be at the start of the function, or the | |
1230 | function can start with a branch to startup code at the end. | |
1231 | ||
1232 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1233 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1234 | once used in the System V compiler). | |
1235 | ||
1236 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1237 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1238 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1239 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1240 | |
1241 | Next, the registers used by this function are pushed. With the | |
1242 | System V compiler they will always be in the order: %edi, %esi, | |
1243 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1244 | restore %eax); however, the code below is willing to see the pushes | |
1245 | in any order, and will handle up to 8 of them. | |
1246 | ||
1247 | If the setup sequence is at the end of the function, then the next | |
1248 | instruction will be a branch back to the start. */ | |
c906108c | 1249 | |
acd5c798 | 1250 | static CORE_ADDR |
e17a4113 UW |
1251 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1252 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1253 | struct i386_frame_cache *cache) |
c906108c | 1254 | { |
e11481da | 1255 | pc = i386_skip_noop (pc); |
e17a4113 | 1256 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1257 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1258 | pc = i386_skip_probe (pc); | |
92dd43fa | 1259 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1260 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1261 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1262 | } |
1263 | ||
fc338970 | 1264 | /* Return PC of first real instruction. */ |
c906108c | 1265 | |
3a1e71e3 | 1266 | static CORE_ADDR |
6093d2eb | 1267 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1268 | { |
e17a4113 UW |
1269 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1270 | ||
63c0089f | 1271 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1272 | { |
1273 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1274 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1275 | }; |
acd5c798 MK |
1276 | struct i386_frame_cache cache; |
1277 | CORE_ADDR pc; | |
63c0089f | 1278 | gdb_byte op; |
acd5c798 | 1279 | int i; |
c5aa993b | 1280 | |
acd5c798 | 1281 | cache.locals = -1; |
e17a4113 | 1282 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1283 | if (cache.locals < 0) |
1284 | return start_pc; | |
c5aa993b | 1285 | |
acd5c798 | 1286 | /* Found valid frame setup. */ |
c906108c | 1287 | |
fc338970 MK |
1288 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1289 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1290 | %ebx: |
1291 | ||
fc338970 MK |
1292 | call 0x0 |
1293 | popl %ebx | |
1294 | movl %ebx,x(%ebp) (optional) | |
1295 | addl y,%ebx | |
1296 | ||
c906108c SS |
1297 | This code is with the rest of the prologue (at the end of the |
1298 | function), so we have to skip it to get to the first real | |
1299 | instruction at the start of the function. */ | |
c5aa993b | 1300 | |
c906108c SS |
1301 | for (i = 0; i < 6; i++) |
1302 | { | |
8defab1a | 1303 | target_read_memory (pc + i, &op, 1); |
c5aa993b | 1304 | if (pic_pat[i] != op) |
c906108c SS |
1305 | break; |
1306 | } | |
1307 | if (i == 6) | |
1308 | { | |
acd5c798 MK |
1309 | int delta = 6; |
1310 | ||
8defab1a | 1311 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1312 | |
c5aa993b | 1313 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1314 | { |
e17a4113 | 1315 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1316 | |
fc338970 | 1317 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1318 | delta += 3; |
fc338970 | 1319 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1320 | delta += 6; |
fc338970 | 1321 | else /* Unexpected instruction. */ |
acd5c798 MK |
1322 | delta = 0; |
1323 | ||
8defab1a | 1324 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1325 | } |
acd5c798 | 1326 | |
c5aa993b | 1327 | /* addl y,%ebx */ |
acd5c798 | 1328 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1329 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1330 | == 0xc3) | |
c906108c | 1331 | { |
acd5c798 | 1332 | pc += delta + 6; |
c906108c SS |
1333 | } |
1334 | } | |
c5aa993b | 1335 | |
e63bbc88 MK |
1336 | /* If the function starts with a branch (to startup code at the end) |
1337 | the last instruction should bring us back to the first | |
1338 | instruction of the real code. */ | |
e17a4113 UW |
1339 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1340 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1341 | |
1342 | return pc; | |
c906108c SS |
1343 | } |
1344 | ||
4309257c PM |
1345 | /* Check that the code pointed to by PC corresponds to a call to |
1346 | __main, skip it if so. Return PC otherwise. */ | |
1347 | ||
1348 | CORE_ADDR | |
1349 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1350 | { | |
e17a4113 | 1351 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1352 | gdb_byte op; |
1353 | ||
1354 | target_read_memory (pc, &op, 1); | |
1355 | if (op == 0xe8) | |
1356 | { | |
1357 | gdb_byte buf[4]; | |
1358 | ||
1359 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1360 | { | |
1361 | /* Make sure address is computed correctly as a 32bit | |
1362 | integer even if CORE_ADDR is 64 bit wide. */ | |
1363 | struct minimal_symbol *s; | |
e17a4113 | 1364 | CORE_ADDR call_dest; |
4309257c | 1365 | |
e17a4113 | 1366 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1367 | call_dest = call_dest & 0xffffffffU; |
1368 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1369 | if (s != NULL | |
1370 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1371 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1372 | pc += 5; | |
1373 | } | |
1374 | } | |
1375 | ||
1376 | return pc; | |
1377 | } | |
1378 | ||
acd5c798 | 1379 | /* This function is 64-bit safe. */ |
93924b6b | 1380 | |
acd5c798 MK |
1381 | static CORE_ADDR |
1382 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1383 | { |
63c0089f | 1384 | gdb_byte buf[8]; |
acd5c798 | 1385 | |
875f8d0e | 1386 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1387 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1388 | } |
acd5c798 | 1389 | \f |
93924b6b | 1390 | |
acd5c798 | 1391 | /* Normal frames. */ |
c5aa993b | 1392 | |
acd5c798 | 1393 | static struct i386_frame_cache * |
10458914 | 1394 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
a7769679 | 1395 | { |
e17a4113 UW |
1396 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1397 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1398 | struct i386_frame_cache *cache; |
63c0089f | 1399 | gdb_byte buf[4]; |
acd5c798 MK |
1400 | int i; |
1401 | ||
1402 | if (*this_cache) | |
1403 | return *this_cache; | |
1404 | ||
fd13a04a | 1405 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1406 | *this_cache = cache; |
1407 | ||
1408 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1409 | which holds the base address for the current stack frame. | |
1410 | However, for functions that don't need it, the frame pointer is | |
1411 | optional. For these "frameless" functions the frame pointer is | |
1412 | actually the frame pointer of the calling frame. Signal | |
1413 | trampolines are just a special case of a "frameless" function. | |
1414 | They (usually) share their frame pointer with the frame that was | |
1415 | in progress when the signal occurred. */ | |
1416 | ||
10458914 | 1417 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1418 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 MK |
1419 | if (cache->base == 0) |
1420 | return cache; | |
1421 | ||
1422 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1423 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1424 | |
10458914 | 1425 | cache->pc = get_frame_func (this_frame); |
acd5c798 | 1426 | if (cache->pc != 0) |
e17a4113 UW |
1427 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1428 | cache); | |
acd5c798 | 1429 | |
e0c62198 | 1430 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1431 | { |
e0c62198 L |
1432 | /* Saved stack pointer has been saved. */ |
1433 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
e17a4113 | 1434 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
92dd43fa MK |
1435 | } |
1436 | ||
acd5c798 MK |
1437 | if (cache->locals < 0) |
1438 | { | |
1439 | /* We didn't find a valid frame, which means that CACHE->base | |
1440 | currently holds the frame pointer for our calling frame. If | |
1441 | we're at the start of a function, or somewhere half-way its | |
1442 | prologue, the function's frame probably hasn't been fully | |
1443 | setup yet. Try to reconstruct the base address for the stack | |
1444 | frame by looking at the stack pointer. For truly "frameless" | |
1445 | functions this might work too. */ | |
1446 | ||
e0c62198 | 1447 | if (cache->saved_sp_reg != -1) |
92dd43fa MK |
1448 | { |
1449 | /* We're halfway aligning the stack. */ | |
1450 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1451 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1452 | ||
1453 | /* This will be added back below. */ | |
1454 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1455 | } | |
7618e12b DJ |
1456 | else if (cache->pc != 0 |
1457 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1458 | { |
7618e12b DJ |
1459 | /* We're in a known function, but did not find a frame |
1460 | setup. Assume that the function does not use %ebp. | |
1461 | Alternatively, we may have jumped to an invalid | |
1462 | address; in that case there is definitely no new | |
1463 | frame in %ebp. */ | |
10458914 | 1464 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1465 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1466 | + cache->sp_offset; | |
92dd43fa | 1467 | } |
7618e12b DJ |
1468 | else |
1469 | /* We're in an unknown function. We could not find the start | |
1470 | of the function to analyze the prologue; our best option is | |
1471 | to assume a typical frame layout with the caller's %ebp | |
1472 | saved. */ | |
1473 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1474 | } |
1475 | ||
1476 | /* Now that we have the base address for the stack frame we can | |
1477 | calculate the value of %esp in the calling frame. */ | |
92dd43fa MK |
1478 | if (cache->saved_sp == 0) |
1479 | cache->saved_sp = cache->base + 8; | |
a7769679 | 1480 | |
acd5c798 MK |
1481 | /* Adjust all the saved registers such that they contain addresses |
1482 | instead of offsets. */ | |
1483 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1484 | if (cache->saved_regs[i] != -1) |
1485 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
1486 | |
1487 | return cache; | |
a7769679 MK |
1488 | } |
1489 | ||
3a1e71e3 | 1490 | static void |
10458914 | 1491 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1492 | struct frame_id *this_id) |
c906108c | 1493 | { |
10458914 | 1494 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1495 | |
1496 | /* This marks the outermost frame. */ | |
1497 | if (cache->base == 0) | |
1498 | return; | |
1499 | ||
3e210248 | 1500 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1501 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1502 | } | |
1503 | ||
10458914 DJ |
1504 | static struct value * |
1505 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1506 | int regnum) | |
acd5c798 | 1507 | { |
10458914 | 1508 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1509 | |
1510 | gdb_assert (regnum >= 0); | |
1511 | ||
1512 | /* The System V ABI says that: | |
1513 | ||
1514 | "The flags register contains the system flags, such as the | |
1515 | direction flag and the carry flag. The direction flag must be | |
1516 | set to the forward (that is, zero) direction before entry and | |
1517 | upon exit from a function. Other user flags have no specified | |
1518 | role in the standard calling sequence and are not preserved." | |
1519 | ||
1520 | To guarantee the "upon exit" part of that statement we fake a | |
1521 | saved flags register that has its direction flag cleared. | |
1522 | ||
1523 | Note that GCC doesn't seem to rely on the fact that the direction | |
1524 | flag is cleared after a function return; it always explicitly | |
1525 | clears the flag before operations where it matters. | |
1526 | ||
1527 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1528 | right thing to do. The way we fake the flags register here makes | |
1529 | it impossible to change it. */ | |
1530 | ||
1531 | if (regnum == I386_EFLAGS_REGNUM) | |
1532 | { | |
10458914 | 1533 | ULONGEST val; |
c5aa993b | 1534 | |
10458914 DJ |
1535 | val = get_frame_register_unsigned (this_frame, regnum); |
1536 | val &= ~(1 << 10); | |
1537 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1538 | } |
1211c4e4 | 1539 | |
acd5c798 | 1540 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1541 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 MK |
1542 | |
1543 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
10458914 | 1544 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
acd5c798 | 1545 | |
fd13a04a | 1546 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1547 | return frame_unwind_got_memory (this_frame, regnum, |
1548 | cache->saved_regs[regnum]); | |
fd13a04a | 1549 | |
10458914 | 1550 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1551 | } |
1552 | ||
1553 | static const struct frame_unwind i386_frame_unwind = | |
1554 | { | |
1555 | NORMAL_FRAME, | |
1556 | i386_frame_this_id, | |
10458914 DJ |
1557 | i386_frame_prev_register, |
1558 | NULL, | |
1559 | default_frame_sniffer | |
acd5c798 | 1560 | }; |
06da04c6 MS |
1561 | |
1562 | /* Normal frames, but in a function epilogue. */ | |
1563 | ||
1564 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1565 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1566 | the function's stack frame. */ | |
1567 | ||
1568 | static int | |
1569 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1570 | { | |
1571 | gdb_byte insn; | |
1572 | ||
1573 | if (target_read_memory (pc, &insn, 1)) | |
1574 | return 0; /* Can't read memory at pc. */ | |
1575 | ||
1576 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1577 | return 0; | |
1578 | ||
1579 | return 1; | |
1580 | } | |
1581 | ||
1582 | static int | |
1583 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1584 | struct frame_info *this_frame, | |
1585 | void **this_prologue_cache) | |
1586 | { | |
1587 | if (frame_relative_level (this_frame) == 0) | |
1588 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1589 | get_frame_pc (this_frame)); | |
1590 | else | |
1591 | return 0; | |
1592 | } | |
1593 | ||
1594 | static struct i386_frame_cache * | |
1595 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1596 | { | |
1597 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1598 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1599 | struct i386_frame_cache *cache; | |
1600 | gdb_byte buf[4]; | |
1601 | ||
1602 | if (*this_cache) | |
1603 | return *this_cache; | |
1604 | ||
1605 | cache = i386_alloc_frame_cache (); | |
1606 | *this_cache = cache; | |
1607 | ||
1608 | /* Cache base will be %esp plus cache->sp_offset (-4). */ | |
1609 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); | |
1610 | cache->base = extract_unsigned_integer (buf, 4, | |
1611 | byte_order) + cache->sp_offset; | |
1612 | ||
1613 | /* Cache pc will be the frame func. */ | |
1614 | cache->pc = get_frame_pc (this_frame); | |
1615 | ||
1616 | /* The saved %esp will be at cache->base plus 8. */ | |
1617 | cache->saved_sp = cache->base + 8; | |
1618 | ||
1619 | /* The saved %eip will be at cache->base plus 4. */ | |
1620 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; | |
1621 | ||
1622 | return cache; | |
1623 | } | |
1624 | ||
1625 | static void | |
1626 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1627 | void **this_cache, | |
1628 | struct frame_id *this_id) | |
1629 | { | |
1630 | struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame, | |
1631 | this_cache); | |
1632 | ||
1633 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
1634 | } | |
1635 | ||
1636 | static const struct frame_unwind i386_epilogue_frame_unwind = | |
1637 | { | |
1638 | NORMAL_FRAME, | |
1639 | i386_epilogue_frame_this_id, | |
1640 | i386_frame_prev_register, | |
1641 | NULL, | |
1642 | i386_epilogue_frame_sniffer | |
1643 | }; | |
acd5c798 MK |
1644 | \f |
1645 | ||
1646 | /* Signal trampolines. */ | |
1647 | ||
1648 | static struct i386_frame_cache * | |
10458914 | 1649 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1650 | { |
e17a4113 UW |
1651 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1652 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1653 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1654 | struct i386_frame_cache *cache; |
acd5c798 | 1655 | CORE_ADDR addr; |
63c0089f | 1656 | gdb_byte buf[4]; |
acd5c798 MK |
1657 | |
1658 | if (*this_cache) | |
1659 | return *this_cache; | |
1660 | ||
fd13a04a | 1661 | cache = i386_alloc_frame_cache (); |
acd5c798 | 1662 | |
10458914 | 1663 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1664 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; |
acd5c798 | 1665 | |
10458914 | 1666 | addr = tdep->sigcontext_addr (this_frame); |
a3386186 MK |
1667 | if (tdep->sc_reg_offset) |
1668 | { | |
1669 | int i; | |
1670 | ||
1671 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1672 | ||
1673 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1674 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1675 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1676 | } |
1677 | else | |
1678 | { | |
fd13a04a AC |
1679 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1680 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1681 | } |
acd5c798 MK |
1682 | |
1683 | *this_cache = cache; | |
1684 | return cache; | |
1685 | } | |
1686 | ||
1687 | static void | |
10458914 | 1688 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
1689 | struct frame_id *this_id) |
1690 | { | |
1691 | struct i386_frame_cache *cache = | |
10458914 | 1692 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1693 | |
3e210248 | 1694 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1695 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
1696 | } |
1697 | ||
10458914 DJ |
1698 | static struct value * |
1699 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1700 | void **this_cache, int regnum) | |
acd5c798 MK |
1701 | { |
1702 | /* Make sure we've initialized the cache. */ | |
10458914 | 1703 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1704 | |
10458914 | 1705 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 1706 | } |
c0d1d883 | 1707 | |
10458914 DJ |
1708 | static int |
1709 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1710 | struct frame_info *this_frame, | |
1711 | void **this_prologue_cache) | |
acd5c798 | 1712 | { |
10458914 | 1713 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1714 | |
911bc6ee MK |
1715 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1716 | handler. */ | |
1717 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1718 | return 0; |
1c3545ae | 1719 | |
911bc6ee MK |
1720 | if (tdep->sigtramp_p != NULL) |
1721 | { | |
10458914 DJ |
1722 | if (tdep->sigtramp_p (this_frame)) |
1723 | return 1; | |
911bc6ee MK |
1724 | } |
1725 | ||
1726 | if (tdep->sigtramp_start != 0) | |
1727 | { | |
10458914 | 1728 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
1729 | |
1730 | gdb_assert (tdep->sigtramp_end != 0); | |
1731 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1732 | return 1; |
911bc6ee | 1733 | } |
acd5c798 | 1734 | |
10458914 | 1735 | return 0; |
acd5c798 | 1736 | } |
10458914 DJ |
1737 | |
1738 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
1739 | { | |
1740 | SIGTRAMP_FRAME, | |
1741 | i386_sigtramp_frame_this_id, | |
1742 | i386_sigtramp_frame_prev_register, | |
1743 | NULL, | |
1744 | i386_sigtramp_frame_sniffer | |
1745 | }; | |
acd5c798 MK |
1746 | \f |
1747 | ||
1748 | static CORE_ADDR | |
10458914 | 1749 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1750 | { |
10458914 | 1751 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1752 | |
1753 | return cache->base; | |
1754 | } | |
1755 | ||
1756 | static const struct frame_base i386_frame_base = | |
1757 | { | |
1758 | &i386_frame_unwind, | |
1759 | i386_frame_base_address, | |
1760 | i386_frame_base_address, | |
1761 | i386_frame_base_address | |
1762 | }; | |
1763 | ||
acd5c798 | 1764 | static struct frame_id |
10458914 | 1765 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 1766 | { |
acd5c798 MK |
1767 | CORE_ADDR fp; |
1768 | ||
10458914 | 1769 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 1770 | |
3e210248 | 1771 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1772 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 1773 | } |
fc338970 | 1774 | \f |
c906108c | 1775 | |
fc338970 MK |
1776 | /* Figure out where the longjmp will land. Slurp the args out of the |
1777 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1778 | structure from which we extract the address that we will land at. |
28bcfd30 | 1779 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 1780 | success. */ |
c906108c | 1781 | |
8201327c | 1782 | static int |
60ade65d | 1783 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 1784 | { |
436675d3 | 1785 | gdb_byte buf[4]; |
c906108c | 1786 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 1787 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 1788 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 1789 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 1790 | |
8201327c MK |
1791 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1792 | longjmp will land. */ | |
1793 | if (jb_pc_offset == -1) | |
c906108c SS |
1794 | return 0; |
1795 | ||
436675d3 | 1796 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1797 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1798 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
1799 | return 0; |
1800 | ||
e17a4113 | 1801 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1802 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 1803 | return 0; |
c906108c | 1804 | |
e17a4113 | 1805 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
1806 | return 1; |
1807 | } | |
fc338970 | 1808 | \f |
c906108c | 1809 | |
7ccc1c74 JM |
1810 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
1811 | function argument. 16-byte vectors, _Decimal128 and structures or | |
1812 | unions containing such types must be 16-byte-aligned; other | |
1813 | arguments are 4-byte-aligned. */ | |
1814 | ||
1815 | static int | |
1816 | i386_16_byte_align_p (struct type *type) | |
1817 | { | |
1818 | type = check_typedef (type); | |
1819 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
1820 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
1821 | && TYPE_LENGTH (type) == 16) | |
1822 | return 1; | |
1823 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
1824 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
1825 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1826 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
1827 | { | |
1828 | int i; | |
1829 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
1830 | { | |
1831 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
1832 | return 1; | |
1833 | } | |
1834 | } | |
1835 | return 0; | |
1836 | } | |
1837 | ||
3a1e71e3 | 1838 | static CORE_ADDR |
7d9b040b | 1839 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1840 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1841 | struct value **args, CORE_ADDR sp, int struct_return, | |
1842 | CORE_ADDR struct_addr) | |
22f8ba57 | 1843 | { |
e17a4113 | 1844 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1845 | gdb_byte buf[4]; |
acd5c798 | 1846 | int i; |
7ccc1c74 JM |
1847 | int write_pass; |
1848 | int args_space = 0; | |
acd5c798 | 1849 | |
7ccc1c74 JM |
1850 | /* Determine the total space required for arguments and struct |
1851 | return address in a first pass (allowing for 16-byte-aligned | |
1852 | arguments), then push arguments in a second pass. */ | |
1853 | ||
1854 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 1855 | { |
7ccc1c74 JM |
1856 | int args_space_used = 0; |
1857 | int have_16_byte_aligned_arg = 0; | |
1858 | ||
1859 | if (struct_return) | |
1860 | { | |
1861 | if (write_pass) | |
1862 | { | |
1863 | /* Push value address. */ | |
e17a4113 | 1864 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
1865 | write_memory (sp, buf, 4); |
1866 | args_space_used += 4; | |
1867 | } | |
1868 | else | |
1869 | args_space += 4; | |
1870 | } | |
1871 | ||
1872 | for (i = 0; i < nargs; i++) | |
1873 | { | |
1874 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 1875 | |
7ccc1c74 JM |
1876 | if (write_pass) |
1877 | { | |
1878 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1879 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 1880 | |
7ccc1c74 JM |
1881 | write_memory (sp + args_space_used, |
1882 | value_contents_all (args[i]), len); | |
1883 | /* The System V ABI says that: | |
acd5c798 | 1884 | |
7ccc1c74 JM |
1885 | "An argument's size is increased, if necessary, to make it a |
1886 | multiple of [32-bit] words. This may require tail padding, | |
1887 | depending on the size of the argument." | |
22f8ba57 | 1888 | |
7ccc1c74 JM |
1889 | This makes sure the stack stays word-aligned. */ |
1890 | args_space_used += align_up (len, 4); | |
1891 | } | |
1892 | else | |
1893 | { | |
1894 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1895 | { | |
1896 | args_space = align_up (args_space, 16); | |
1897 | have_16_byte_aligned_arg = 1; | |
1898 | } | |
1899 | args_space += align_up (len, 4); | |
1900 | } | |
1901 | } | |
1902 | ||
1903 | if (!write_pass) | |
1904 | { | |
1905 | if (have_16_byte_aligned_arg) | |
1906 | args_space = align_up (args_space, 16); | |
1907 | sp -= args_space; | |
1908 | } | |
22f8ba57 MK |
1909 | } |
1910 | ||
acd5c798 MK |
1911 | /* Store return address. */ |
1912 | sp -= 4; | |
e17a4113 | 1913 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
1914 | write_memory (sp, buf, 4); |
1915 | ||
1916 | /* Finally, update the stack pointer... */ | |
e17a4113 | 1917 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
1918 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
1919 | ||
1920 | /* ...and fake a frame pointer. */ | |
1921 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
1922 | ||
3e210248 AC |
1923 | /* MarkK wrote: This "+ 8" is all over the place: |
1924 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 1925 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 1926 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
1927 | definition of the stack address of a frame. Otherwise frame id |
1928 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
1929 | stack address *before* the function call as a frame's CFA. On |
1930 | the i386, when %ebp is used as a frame pointer, the offset | |
1931 | between the contents %ebp and the CFA as defined by GCC. */ | |
1932 | return sp + 8; | |
22f8ba57 MK |
1933 | } |
1934 | ||
1a309862 MK |
1935 | /* These registers are used for returning integers (and on some |
1936 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 1937 | size and alignment match an integer type). */ |
acd5c798 MK |
1938 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
1939 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 1940 | |
c5e656c1 MK |
1941 | /* Read, for architecture GDBARCH, a function return value of TYPE |
1942 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 1943 | |
3a1e71e3 | 1944 | static void |
c5e656c1 | 1945 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1946 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 1947 | { |
c5e656c1 | 1948 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 1949 | int len = TYPE_LENGTH (type); |
63c0089f | 1950 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 1951 | |
1e8d0a7b | 1952 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 1953 | { |
5716833c | 1954 | if (tdep->st0_regnum < 0) |
1a309862 | 1955 | { |
8a3fe4f8 | 1956 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 1957 | memset (valbuf, 0, len); |
ef9dff19 | 1958 | return; |
1a309862 MK |
1959 | } |
1960 | ||
c6ba6f0d MK |
1961 | /* Floating-point return values can be found in %st(0). Convert |
1962 | its contents to the desired type. This is probably not | |
1963 | exactly how it would happen on the target itself, but it is | |
1964 | the best we can do. */ | |
acd5c798 | 1965 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 1966 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
1967 | } |
1968 | else | |
c5aa993b | 1969 | { |
875f8d0e UW |
1970 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1971 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
1972 | |
1973 | if (len <= low_size) | |
00f8375e | 1974 | { |
0818c12a | 1975 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
1976 | memcpy (valbuf, buf, len); |
1977 | } | |
d4f3574e SS |
1978 | else if (len <= (low_size + high_size)) |
1979 | { | |
0818c12a | 1980 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 1981 | memcpy (valbuf, buf, low_size); |
0818c12a | 1982 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 1983 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
1984 | } |
1985 | else | |
8e65ff28 | 1986 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1987 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
1988 | } |
1989 | } | |
1990 | ||
c5e656c1 MK |
1991 | /* Write, for architecture GDBARCH, a function return value of TYPE |
1992 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 1993 | |
3a1e71e3 | 1994 | static void |
c5e656c1 | 1995 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1996 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 1997 | { |
c5e656c1 | 1998 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
1999 | int len = TYPE_LENGTH (type); |
2000 | ||
1e8d0a7b | 2001 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2002 | { |
3d7f4f49 | 2003 | ULONGEST fstat; |
63c0089f | 2004 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2005 | |
5716833c | 2006 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2007 | { |
8a3fe4f8 | 2008 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2009 | return; |
2010 | } | |
2011 | ||
635b0cc1 MK |
2012 | /* Returning floating-point values is a bit tricky. Apart from |
2013 | storing the return value in %st(0), we have to simulate the | |
2014 | state of the FPU at function return point. */ | |
2015 | ||
c6ba6f0d MK |
2016 | /* Convert the value found in VALBUF to the extended |
2017 | floating-point format used by the FPU. This is probably | |
2018 | not exactly how it would happen on the target itself, but | |
2019 | it is the best we can do. */ | |
27067745 | 2020 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2021 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2022 | |
635b0cc1 MK |
2023 | /* Set the top of the floating-point register stack to 7. The |
2024 | actual value doesn't really matter, but 7 is what a normal | |
2025 | function return would end up with if the program started out | |
2026 | with a freshly initialized FPU. */ | |
20a6ec49 | 2027 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2028 | fstat |= (7 << 11); |
20a6ec49 | 2029 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2030 | |
635b0cc1 MK |
2031 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2032 | the floating-point register stack to 7, the appropriate value | |
2033 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2034 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2035 | } |
2036 | else | |
2037 | { | |
875f8d0e UW |
2038 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2039 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2040 | |
2041 | if (len <= low_size) | |
3d7f4f49 | 2042 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2043 | else if (len <= (low_size + high_size)) |
2044 | { | |
3d7f4f49 MK |
2045 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2046 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2047 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2048 | } |
2049 | else | |
8e65ff28 | 2050 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2051 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2052 | } |
2053 | } | |
fc338970 | 2054 | \f |
ef9dff19 | 2055 | |
8201327c MK |
2056 | /* This is the variable that is set with "set struct-convention", and |
2057 | its legitimate values. */ | |
2058 | static const char default_struct_convention[] = "default"; | |
2059 | static const char pcc_struct_convention[] = "pcc"; | |
2060 | static const char reg_struct_convention[] = "reg"; | |
2061 | static const char *valid_conventions[] = | |
2062 | { | |
2063 | default_struct_convention, | |
2064 | pcc_struct_convention, | |
2065 | reg_struct_convention, | |
2066 | NULL | |
2067 | }; | |
2068 | static const char *struct_convention = default_struct_convention; | |
2069 | ||
0e4377e1 JB |
2070 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2071 | a union type, or an array type, should be returned in registers | |
2072 | for architecture GDBARCH. */ | |
c5e656c1 | 2073 | |
8201327c | 2074 | static int |
c5e656c1 | 2075 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2076 | { |
c5e656c1 MK |
2077 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2078 | enum type_code code = TYPE_CODE (type); | |
2079 | int len = TYPE_LENGTH (type); | |
8201327c | 2080 | |
0e4377e1 JB |
2081 | gdb_assert (code == TYPE_CODE_STRUCT |
2082 | || code == TYPE_CODE_UNION | |
2083 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2084 | |
2085 | if (struct_convention == pcc_struct_convention | |
2086 | || (struct_convention == default_struct_convention | |
2087 | && tdep->struct_return == pcc_struct_return)) | |
2088 | return 0; | |
2089 | ||
9edde48e MK |
2090 | /* Structures consisting of a single `float', `double' or 'long |
2091 | double' member are returned in %st(0). */ | |
2092 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2093 | { | |
2094 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2095 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2096 | return (len == 4 || len == 8 || len == 12); | |
2097 | } | |
2098 | ||
c5e656c1 MK |
2099 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2100 | } | |
2101 | ||
2102 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2103 | should be returned. If it is supposed to be returned in registers, | |
2104 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2105 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2106 | from WRITEBUF into REGCACHE. */ | |
2107 | ||
2108 | static enum return_value_convention | |
c055b101 CV |
2109 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2110 | struct type *type, struct regcache *regcache, | |
2111 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2112 | { |
2113 | enum type_code code = TYPE_CODE (type); | |
2114 | ||
5daa78cc TJB |
2115 | if (((code == TYPE_CODE_STRUCT |
2116 | || code == TYPE_CODE_UNION | |
2117 | || code == TYPE_CODE_ARRAY) | |
2118 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2119 | /* 128-bit decimal float uses the struct return convention. */ | |
2120 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2121 | { |
2122 | /* The System V ABI says that: | |
2123 | ||
2124 | "A function that returns a structure or union also sets %eax | |
2125 | to the value of the original address of the caller's area | |
2126 | before it returns. Thus when the caller receives control | |
2127 | again, the address of the returned object resides in register | |
2128 | %eax and can be used to access the object." | |
2129 | ||
2130 | So the ABI guarantees that we can always find the return | |
2131 | value just after the function has returned. */ | |
2132 | ||
0e4377e1 JB |
2133 | /* Note that the ABI doesn't mention functions returning arrays, |
2134 | which is something possible in certain languages such as Ada. | |
2135 | In this case, the value is returned as if it was wrapped in | |
2136 | a record, so the convention applied to records also applies | |
2137 | to arrays. */ | |
2138 | ||
31db7b6c MK |
2139 | if (readbuf) |
2140 | { | |
2141 | ULONGEST addr; | |
2142 | ||
2143 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2144 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2145 | } | |
2146 | ||
2147 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2148 | } | |
c5e656c1 MK |
2149 | |
2150 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2151 | `float', `double' or 'long double' member. These structures are |
2152 | returned in %st(0). For these structures, we call ourselves | |
2153 | recursively, changing TYPE into the type of the first member of | |
2154 | the structure. Since that should work for all structures that | |
2155 | have only one member, we don't bother to check the member's type | |
2156 | here. */ | |
c5e656c1 MK |
2157 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2158 | { | |
2159 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2160 | return i386_return_value (gdbarch, func_type, type, regcache, |
2161 | readbuf, writebuf); | |
c5e656c1 MK |
2162 | } |
2163 | ||
2164 | if (readbuf) | |
2165 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2166 | if (writebuf) | |
2167 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2168 | |
c5e656c1 | 2169 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2170 | } |
2171 | \f | |
2172 | ||
27067745 UW |
2173 | struct type * |
2174 | i387_ext_type (struct gdbarch *gdbarch) | |
2175 | { | |
2176 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2177 | ||
2178 | if (!tdep->i387_ext_type) | |
90884b2b L |
2179 | { |
2180 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2181 | gdb_assert (tdep->i387_ext_type != NULL); | |
2182 | } | |
27067745 UW |
2183 | |
2184 | return tdep->i387_ext_type; | |
2185 | } | |
2186 | ||
794ac428 | 2187 | /* Construct vector type for MMX registers. */ |
90884b2b | 2188 | static struct type * |
794ac428 UW |
2189 | i386_mmx_type (struct gdbarch *gdbarch) |
2190 | { | |
2191 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2192 | ||
2193 | if (!tdep->i386_mmx_type) | |
2194 | { | |
df4df182 UW |
2195 | const struct builtin_type *bt = builtin_type (gdbarch); |
2196 | ||
794ac428 UW |
2197 | /* The type we're building is this: */ |
2198 | #if 0 | |
2199 | union __gdb_builtin_type_vec64i | |
2200 | { | |
2201 | int64_t uint64; | |
2202 | int32_t v2_int32[2]; | |
2203 | int16_t v4_int16[4]; | |
2204 | int8_t v8_int8[8]; | |
2205 | }; | |
2206 | #endif | |
2207 | ||
2208 | struct type *t; | |
2209 | ||
e9bb382b UW |
2210 | t = arch_composite_type (gdbarch, |
2211 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2212 | |
2213 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2214 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2215 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2216 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2217 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2218 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2219 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2220 | |
876cecd0 | 2221 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2222 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2223 | tdep->i386_mmx_type = t; | |
2224 | } | |
2225 | ||
2226 | return tdep->i386_mmx_type; | |
2227 | } | |
2228 | ||
d7a0d72c | 2229 | /* Return the GDB type object for the "standard" data type of data in |
90884b2b | 2230 | register REGNUM. */ |
d7a0d72c | 2231 | |
3a1e71e3 | 2232 | static struct type * |
90884b2b | 2233 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2234 | { |
1ba53b71 L |
2235 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2236 | return i386_mmx_type (gdbarch); | |
2237 | else | |
2238 | { | |
2239 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2240 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2241 | return bt->builtin_int8; | |
2242 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2243 | return bt->builtin_int16; | |
2244 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2245 | return bt->builtin_int32; | |
2246 | } | |
2247 | ||
2248 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2249 | } |
2250 | ||
28fc6740 | 2251 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2252 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2253 | |
2254 | static int | |
c86c27af | 2255 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2256 | { |
5716833c MK |
2257 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2258 | int mmxreg, fpreg; | |
28fc6740 AC |
2259 | ULONGEST fstat; |
2260 | int tos; | |
c86c27af | 2261 | |
5716833c | 2262 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2263 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2264 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2265 | fpreg = (mmxreg + tos) % 8; |
2266 | ||
20a6ec49 | 2267 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2268 | } |
2269 | ||
1ba53b71 | 2270 | void |
28fc6740 | 2271 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2272 | int regnum, gdb_byte *buf) |
28fc6740 | 2273 | { |
1ba53b71 L |
2274 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2275 | ||
5716833c | 2276 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2277 | { |
c86c27af MK |
2278 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2279 | ||
28fc6740 | 2280 | /* Extract (always little endian). */ |
1ba53b71 L |
2281 | regcache_raw_read (regcache, fpnum, raw_buf); |
2282 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
2283 | } |
2284 | else | |
1ba53b71 L |
2285 | { |
2286 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2287 | ||
2288 | if (i386_word_regnum_p (gdbarch, regnum)) | |
2289 | { | |
2290 | int gpnum = regnum - tdep->ax_regnum; | |
2291 | ||
2292 | /* Extract (always little endian). */ | |
2293 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2294 | memcpy (buf, raw_buf, 2); | |
2295 | } | |
2296 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2297 | { | |
2298 | /* Check byte pseudo registers last since this function will | |
2299 | be called from amd64_pseudo_register_read, which handles | |
2300 | byte pseudo registers differently. */ | |
2301 | int gpnum = regnum - tdep->al_regnum; | |
2302 | ||
2303 | /* Extract (always little endian). We read both lower and | |
2304 | upper registers. */ | |
2305 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2306 | if (gpnum >= 4) | |
2307 | memcpy (buf, raw_buf + 1, 1); | |
2308 | else | |
2309 | memcpy (buf, raw_buf, 1); | |
2310 | } | |
2311 | else | |
2312 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2313 | } | |
28fc6740 AC |
2314 | } |
2315 | ||
1ba53b71 | 2316 | void |
28fc6740 | 2317 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2318 | int regnum, const gdb_byte *buf) |
28fc6740 | 2319 | { |
1ba53b71 L |
2320 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2321 | ||
5716833c | 2322 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2323 | { |
c86c27af MK |
2324 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2325 | ||
28fc6740 | 2326 | /* Read ... */ |
1ba53b71 | 2327 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 2328 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 2329 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 2330 | /* ... Write. */ |
1ba53b71 | 2331 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
2332 | } |
2333 | else | |
1ba53b71 L |
2334 | { |
2335 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2336 | ||
2337 | if (i386_word_regnum_p (gdbarch, regnum)) | |
2338 | { | |
2339 | int gpnum = regnum - tdep->ax_regnum; | |
2340 | ||
2341 | /* Read ... */ | |
2342 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2343 | /* ... Modify ... (always little endian). */ | |
2344 | memcpy (raw_buf, buf, 2); | |
2345 | /* ... Write. */ | |
2346 | regcache_raw_write (regcache, gpnum, raw_buf); | |
2347 | } | |
2348 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2349 | { | |
2350 | /* Check byte pseudo registers last since this function will | |
2351 | be called from amd64_pseudo_register_read, which handles | |
2352 | byte pseudo registers differently. */ | |
2353 | int gpnum = regnum - tdep->al_regnum; | |
2354 | ||
2355 | /* Read ... We read both lower and upper registers. */ | |
2356 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2357 | /* ... Modify ... (always little endian). */ | |
2358 | if (gpnum >= 4) | |
2359 | memcpy (raw_buf + 1, buf, 1); | |
2360 | else | |
2361 | memcpy (raw_buf, buf, 1); | |
2362 | /* ... Write. */ | |
2363 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
2364 | } | |
2365 | else | |
2366 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2367 | } | |
28fc6740 | 2368 | } |
ff2e87ac AC |
2369 | \f |
2370 | ||
ff2e87ac AC |
2371 | /* Return the register number of the register allocated by GCC after |
2372 | REGNUM, or -1 if there is no such register. */ | |
2373 | ||
2374 | static int | |
2375 | i386_next_regnum (int regnum) | |
2376 | { | |
2377 | /* GCC allocates the registers in the order: | |
2378 | ||
2379 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2380 | ||
2381 | Since storing a variable in %esp doesn't make any sense we return | |
2382 | -1 for %ebp and for %esp itself. */ | |
2383 | static int next_regnum[] = | |
2384 | { | |
2385 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2386 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2387 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2388 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2389 | -1, -1, /* Slots for %esp and %ebp. */ | |
2390 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2391 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2392 | }; | |
2393 | ||
de5b9bb9 | 2394 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2395 | return next_regnum[regnum]; |
28fc6740 | 2396 | |
ff2e87ac AC |
2397 | return -1; |
2398 | } | |
2399 | ||
2400 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2401 | needs any special handling. */ | |
d7a0d72c | 2402 | |
3a1e71e3 | 2403 | static int |
0abe36f5 | 2404 | i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
d7a0d72c | 2405 | { |
de5b9bb9 MK |
2406 | int len = TYPE_LENGTH (type); |
2407 | ||
ff2e87ac AC |
2408 | /* Values may be spread across multiple registers. Most debugging |
2409 | formats aren't expressive enough to specify the locations, so | |
2410 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2411 | have a length that is a multiple of the word size, since GCC |
2412 | doesn't seem to put any other types into registers. */ | |
2413 | if (len > 4 && len % 4 == 0) | |
2414 | { | |
2415 | int last_regnum = regnum; | |
2416 | ||
2417 | while (len > 4) | |
2418 | { | |
2419 | last_regnum = i386_next_regnum (last_regnum); | |
2420 | len -= 4; | |
2421 | } | |
2422 | ||
2423 | if (last_regnum != -1) | |
2424 | return 1; | |
2425 | } | |
ff2e87ac | 2426 | |
0abe36f5 | 2427 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2428 | } |
2429 | ||
ff2e87ac AC |
2430 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2431 | return its contents in TO. */ | |
ac27f131 | 2432 | |
3a1e71e3 | 2433 | static void |
ff2e87ac | 2434 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 2435 | struct type *type, gdb_byte *to) |
ac27f131 | 2436 | { |
20a6ec49 | 2437 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2438 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2439 | |
ff2e87ac AC |
2440 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
2441 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 2442 | |
20a6ec49 | 2443 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8d7f6b4a | 2444 | { |
d532c08f MK |
2445 | i387_register_to_value (frame, regnum, type, to); |
2446 | return; | |
8d7f6b4a | 2447 | } |
ff2e87ac | 2448 | |
fd35795f | 2449 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2450 | |
2451 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2452 | |
de5b9bb9 MK |
2453 | while (len > 0) |
2454 | { | |
2455 | gdb_assert (regnum != -1); | |
20a6ec49 | 2456 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 2457 | |
42835c2b | 2458 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
2459 | regnum = i386_next_regnum (regnum); |
2460 | len -= 4; | |
42835c2b | 2461 | to += 4; |
de5b9bb9 | 2462 | } |
ac27f131 MK |
2463 | } |
2464 | ||
ff2e87ac AC |
2465 | /* Write the contents FROM of a value of type TYPE into register |
2466 | REGNUM in frame FRAME. */ | |
ac27f131 | 2467 | |
3a1e71e3 | 2468 | static void |
ff2e87ac | 2469 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 2470 | struct type *type, const gdb_byte *from) |
ac27f131 | 2471 | { |
de5b9bb9 | 2472 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2473 | |
20a6ec49 | 2474 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 2475 | { |
d532c08f MK |
2476 | i387_value_to_register (frame, regnum, type, from); |
2477 | return; | |
2478 | } | |
3d261580 | 2479 | |
fd35795f | 2480 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
2481 | |
2482 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 2483 | |
de5b9bb9 MK |
2484 | while (len > 0) |
2485 | { | |
2486 | gdb_assert (regnum != -1); | |
875f8d0e | 2487 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 2488 | |
42835c2b | 2489 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
2490 | regnum = i386_next_regnum (regnum); |
2491 | len -= 4; | |
42835c2b | 2492 | from += 4; |
de5b9bb9 | 2493 | } |
ac27f131 | 2494 | } |
ff2e87ac | 2495 | \f |
7fdafb5a MK |
2496 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
2497 | in the general-purpose register set REGSET to register cache | |
2498 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 2499 | |
20187ed5 | 2500 | void |
473f17b0 MK |
2501 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
2502 | int regnum, const void *gregs, size_t len) | |
2503 | { | |
9ea75c57 | 2504 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 2505 | const gdb_byte *regs = gregs; |
473f17b0 MK |
2506 | int i; |
2507 | ||
2508 | gdb_assert (len == tdep->sizeof_gregset); | |
2509 | ||
2510 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2511 | { | |
2512 | if ((regnum == i || regnum == -1) | |
2513 | && tdep->gregset_reg_offset[i] != -1) | |
2514 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2515 | } | |
2516 | } | |
2517 | ||
7fdafb5a MK |
2518 | /* Collect register REGNUM from the register cache REGCACHE and store |
2519 | it in the buffer specified by GREGS and LEN as described by the | |
2520 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
2521 | all registers in REGSET. */ | |
2522 | ||
2523 | void | |
2524 | i386_collect_gregset (const struct regset *regset, | |
2525 | const struct regcache *regcache, | |
2526 | int regnum, void *gregs, size_t len) | |
2527 | { | |
2528 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 2529 | gdb_byte *regs = gregs; |
7fdafb5a MK |
2530 | int i; |
2531 | ||
2532 | gdb_assert (len == tdep->sizeof_gregset); | |
2533 | ||
2534 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2535 | { | |
2536 | if ((regnum == i || regnum == -1) | |
2537 | && tdep->gregset_reg_offset[i] != -1) | |
2538 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2539 | } | |
2540 | } | |
2541 | ||
2542 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
2543 | in the floating-point register set REGSET to register cache | |
2544 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2545 | |
2546 | static void | |
2547 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
2548 | int regnum, const void *fpregs, size_t len) | |
2549 | { | |
9ea75c57 | 2550 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 2551 | |
66a72d25 MK |
2552 | if (len == I387_SIZEOF_FXSAVE) |
2553 | { | |
2554 | i387_supply_fxsave (regcache, regnum, fpregs); | |
2555 | return; | |
2556 | } | |
2557 | ||
473f17b0 MK |
2558 | gdb_assert (len == tdep->sizeof_fpregset); |
2559 | i387_supply_fsave (regcache, regnum, fpregs); | |
2560 | } | |
8446b36a | 2561 | |
2f305df1 MK |
2562 | /* Collect register REGNUM from the register cache REGCACHE and store |
2563 | it in the buffer specified by FPREGS and LEN as described by the | |
2564 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2565 | all registers in REGSET. */ | |
7fdafb5a MK |
2566 | |
2567 | static void | |
2568 | i386_collect_fpregset (const struct regset *regset, | |
2569 | const struct regcache *regcache, | |
2570 | int regnum, void *fpregs, size_t len) | |
2571 | { | |
2572 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2573 | ||
2574 | if (len == I387_SIZEOF_FXSAVE) | |
2575 | { | |
2576 | i387_collect_fxsave (regcache, regnum, fpregs); | |
2577 | return; | |
2578 | } | |
2579 | ||
2580 | gdb_assert (len == tdep->sizeof_fpregset); | |
2581 | i387_collect_fsave (regcache, regnum, fpregs); | |
2582 | } | |
2583 | ||
8446b36a MK |
2584 | /* Return the appropriate register set for the core section identified |
2585 | by SECT_NAME and SECT_SIZE. */ | |
2586 | ||
2587 | const struct regset * | |
2588 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
2589 | const char *sect_name, size_t sect_size) | |
2590 | { | |
2591 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2592 | ||
2593 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
2594 | { | |
2595 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
2596 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
2597 | i386_collect_gregset); | |
8446b36a MK |
2598 | return tdep->gregset; |
2599 | } | |
2600 | ||
66a72d25 MK |
2601 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
2602 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
2603 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
2604 | { |
2605 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
2606 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
2607 | i386_collect_fpregset); | |
8446b36a MK |
2608 | return tdep->fpregset; |
2609 | } | |
2610 | ||
2611 | return NULL; | |
2612 | } | |
473f17b0 | 2613 | \f |
fc338970 | 2614 | |
fc338970 | 2615 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
2616 | |
2617 | CORE_ADDR | |
e17a4113 UW |
2618 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
2619 | CORE_ADDR pc, char *name) | |
c906108c | 2620 | { |
e17a4113 UW |
2621 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2622 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2623 | ||
2624 | /* jmp *(dest) */ | |
2625 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 2626 | { |
e17a4113 UW |
2627 | unsigned long indirect = |
2628 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 2629 | struct minimal_symbol *indsym = |
fc338970 | 2630 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 2631 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 2632 | |
c5aa993b | 2633 | if (symname) |
c906108c | 2634 | { |
c5aa993b JM |
2635 | if (strncmp (symname, "__imp_", 6) == 0 |
2636 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
2637 | return name ? 1 : |
2638 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
2639 | } |
2640 | } | |
fc338970 | 2641 | return 0; /* Not a trampoline. */ |
c906108c | 2642 | } |
fc338970 MK |
2643 | \f |
2644 | ||
10458914 DJ |
2645 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
2646 | routine. */ | |
8201327c | 2647 | |
4bd207ef | 2648 | int |
10458914 | 2649 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 2650 | { |
10458914 | 2651 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2652 | char *name; |
2653 | ||
2654 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
2655 | return (name && strcmp ("_sigtramp", name) == 0); |
2656 | } | |
2657 | \f | |
2658 | ||
fc338970 MK |
2659 | /* We have two flavours of disassembly. The machinery on this page |
2660 | deals with switching between those. */ | |
c906108c SS |
2661 | |
2662 | static int | |
a89aa300 | 2663 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 2664 | { |
5e3397bb MK |
2665 | gdb_assert (disassembly_flavor == att_flavor |
2666 | || disassembly_flavor == intel_flavor); | |
2667 | ||
2668 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
2669 | constified, cast to prevent a compiler warning. */ | |
2670 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
2671 | |
2672 | return print_insn_i386 (pc, info); | |
7a292a7a | 2673 | } |
fc338970 | 2674 | \f |
3ce1502b | 2675 | |
8201327c MK |
2676 | /* There are a few i386 architecture variants that differ only |
2677 | slightly from the generic i386 target. For now, we don't give them | |
2678 | their own source file, but include them here. As a consequence, | |
2679 | they'll always be included. */ | |
3ce1502b | 2680 | |
8201327c | 2681 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2682 | |
10458914 DJ |
2683 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
2684 | routine. */ | |
911bc6ee | 2685 | |
8201327c | 2686 | static int |
10458914 | 2687 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 2688 | { |
10458914 | 2689 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2690 | char *name; |
2691 | ||
acd5c798 MK |
2692 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
2693 | currently unknown. */ | |
911bc6ee | 2694 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
2695 | return (name && (strcmp ("_sigreturn", name) == 0 |
2696 | || strcmp ("_sigacthandler", name) == 0 | |
2697 | || strcmp ("sigvechandler", name) == 0)); | |
2698 | } | |
d2a7c97a | 2699 | |
10458914 DJ |
2700 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
2701 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 2702 | |
3a1e71e3 | 2703 | static CORE_ADDR |
10458914 | 2704 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 2705 | { |
e17a4113 UW |
2706 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2707 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 2708 | gdb_byte buf[4]; |
acd5c798 | 2709 | CORE_ADDR sp; |
3ce1502b | 2710 | |
10458914 | 2711 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2712 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 2713 | |
e17a4113 | 2714 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c MK |
2715 | } |
2716 | \f | |
3ce1502b | 2717 | |
8201327c | 2718 | /* Generic ELF. */ |
d2a7c97a | 2719 | |
8201327c MK |
2720 | void |
2721 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2722 | { | |
c4fc7f1b MK |
2723 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2724 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2725 | } |
3ce1502b | 2726 | |
8201327c | 2727 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2728 | |
8201327c MK |
2729 | void |
2730 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2731 | { | |
2732 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2733 | |
8201327c MK |
2734 | /* System V Release 4 uses ELF. */ |
2735 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2736 | |
dfe01d39 | 2737 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2738 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2739 | ||
911bc6ee | 2740 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2741 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
2742 | tdep->sc_pc_offset = 36 + 14 * 4; |
2743 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 2744 | |
8201327c | 2745 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
2746 | } |
2747 | ||
8201327c | 2748 | /* DJGPP. */ |
3ce1502b | 2749 | |
3a1e71e3 | 2750 | static void |
8201327c | 2751 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2752 | { |
8201327c | 2753 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2754 | |
911bc6ee MK |
2755 | /* DJGPP doesn't have any special frames for signal handlers. */ |
2756 | tdep->sigtramp_p = NULL; | |
3ce1502b | 2757 | |
8201327c | 2758 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
2759 | |
2760 | /* DJGPP does not support the SSE registers. */ | |
2761 | tdep->num_xmm_regs = 0; | |
90884b2b | 2762 | set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I387_NUM_REGS); |
3d22076f EZ |
2763 | |
2764 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
2765 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
2766 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
2767 | set_gdbarch_sdb_reg_to_regnum. */ | |
2768 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
2769 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3ce1502b | 2770 | } |
8201327c | 2771 | \f |
2acceee2 | 2772 | |
38c968cf AC |
2773 | /* i386 register groups. In addition to the normal groups, add "mmx" |
2774 | and "sse". */ | |
2775 | ||
2776 | static struct reggroup *i386_sse_reggroup; | |
2777 | static struct reggroup *i386_mmx_reggroup; | |
2778 | ||
2779 | static void | |
2780 | i386_init_reggroups (void) | |
2781 | { | |
2782 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
2783 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
2784 | } | |
2785 | ||
2786 | static void | |
2787 | i386_add_reggroups (struct gdbarch *gdbarch) | |
2788 | { | |
2789 | reggroup_add (gdbarch, i386_sse_reggroup); | |
2790 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
2791 | reggroup_add (gdbarch, general_reggroup); | |
2792 | reggroup_add (gdbarch, float_reggroup); | |
2793 | reggroup_add (gdbarch, all_reggroup); | |
2794 | reggroup_add (gdbarch, save_reggroup); | |
2795 | reggroup_add (gdbarch, restore_reggroup); | |
2796 | reggroup_add (gdbarch, vector_reggroup); | |
2797 | reggroup_add (gdbarch, system_reggroup); | |
2798 | } | |
2799 | ||
2800 | int | |
2801 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2802 | struct reggroup *group) | |
2803 | { | |
1ba53b71 L |
2804 | int sse_regnum_p, fp_regnum_p, mmx_regnum_p, byte_regnum_p, |
2805 | word_regnum_p, dword_regnum_p; | |
acd5c798 | 2806 | |
1ba53b71 L |
2807 | /* Don't include pseudo registers, except for MMX, in any register |
2808 | groups. */ | |
2809 | byte_regnum_p = i386_byte_regnum_p (gdbarch, regnum); | |
2810 | if (byte_regnum_p) | |
2811 | return 0; | |
2812 | ||
2813 | word_regnum_p = i386_word_regnum_p (gdbarch, regnum); | |
2814 | if (word_regnum_p) | |
2815 | return 0; | |
2816 | ||
2817 | dword_regnum_p = i386_dword_regnum_p (gdbarch, regnum); | |
2818 | if (dword_regnum_p) | |
2819 | return 0; | |
2820 | ||
2821 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
2822 | if (group == i386_mmx_reggroup) |
2823 | return mmx_regnum_p; | |
1ba53b71 L |
2824 | |
2825 | sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) | |
2826 | || i386_mxcsr_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
2827 | if (group == i386_sse_reggroup) |
2828 | return sse_regnum_p; | |
2829 | if (group == vector_reggroup) | |
1ba53b71 L |
2830 | return mmx_regnum_p || sse_regnum_p; |
2831 | ||
2832 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
2833 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
2834 | if (group == float_reggroup) |
2835 | return fp_regnum_p; | |
1ba53b71 | 2836 | |
38c968cf | 2837 | if (group == general_reggroup) |
1ba53b71 L |
2838 | return (!fp_regnum_p |
2839 | && !mmx_regnum_p | |
2840 | && !sse_regnum_p | |
2841 | && !byte_regnum_p | |
2842 | && !word_regnum_p | |
2843 | && !dword_regnum_p); | |
acd5c798 | 2844 | |
38c968cf AC |
2845 | return default_register_reggroup_p (gdbarch, regnum, group); |
2846 | } | |
38c968cf | 2847 | \f |
acd5c798 | 2848 | |
f837910f MK |
2849 | /* Get the ARGIth function argument for the current function. */ |
2850 | ||
42c466d7 | 2851 | static CORE_ADDR |
143985b7 AF |
2852 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
2853 | struct type *type) | |
2854 | { | |
e17a4113 UW |
2855 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2856 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f837910f | 2857 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 2858 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
2859 | } |
2860 | ||
514f746b AR |
2861 | static void |
2862 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
2863 | { | |
2864 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
2865 | ||
2866 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
2867 | adjust the PC in the regcache. */ | |
2868 | current_pc += 1; | |
2869 | regcache_write_pc (regcache, current_pc); | |
2870 | } | |
2871 | ||
2872 | ||
7ad10968 HZ |
2873 | #define PREFIX_REPZ 0x01 |
2874 | #define PREFIX_REPNZ 0x02 | |
2875 | #define PREFIX_LOCK 0x04 | |
2876 | #define PREFIX_DATA 0x08 | |
2877 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 2878 | |
7ad10968 HZ |
2879 | /* operand size */ |
2880 | enum | |
2881 | { | |
2882 | OT_BYTE = 0, | |
2883 | OT_WORD, | |
2884 | OT_LONG, | |
cf648174 | 2885 | OT_QUAD, |
7ad10968 | 2886 | }; |
473f17b0 | 2887 | |
7ad10968 HZ |
2888 | /* i386 arith/logic operations */ |
2889 | enum | |
2890 | { | |
2891 | OP_ADDL, | |
2892 | OP_ORL, | |
2893 | OP_ADCL, | |
2894 | OP_SBBL, | |
2895 | OP_ANDL, | |
2896 | OP_SUBL, | |
2897 | OP_XORL, | |
2898 | OP_CMPL, | |
2899 | }; | |
5716833c | 2900 | |
7ad10968 HZ |
2901 | struct i386_record_s |
2902 | { | |
cf648174 | 2903 | struct gdbarch *gdbarch; |
7ad10968 | 2904 | struct regcache *regcache; |
df61f520 | 2905 | CORE_ADDR orig_addr; |
7ad10968 HZ |
2906 | CORE_ADDR addr; |
2907 | int aflag; | |
2908 | int dflag; | |
2909 | int override; | |
2910 | uint8_t modrm; | |
2911 | uint8_t mod, reg, rm; | |
2912 | int ot; | |
cf648174 HZ |
2913 | uint8_t rex_x; |
2914 | uint8_t rex_b; | |
2915 | int rip_offset; | |
2916 | int popl_esp_hack; | |
2917 | const int *regmap; | |
7ad10968 | 2918 | }; |
5716833c | 2919 | |
7ad10968 HZ |
2920 | /* Parse "modrm" part in current memory address that irp->addr point to |
2921 | Return -1 if something wrong. */ | |
5716833c | 2922 | |
7ad10968 HZ |
2923 | static int |
2924 | i386_record_modrm (struct i386_record_s *irp) | |
2925 | { | |
cf648174 | 2926 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 2927 | |
7ad10968 HZ |
2928 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
2929 | { | |
2930 | if (record_debug) | |
2931 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
2932 | "addr %s len = 1.\n"), |
2933 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2934 | return -1; |
2935 | } | |
2936 | irp->addr++; | |
2937 | irp->mod = (irp->modrm >> 6) & 3; | |
2938 | irp->reg = (irp->modrm >> 3) & 7; | |
2939 | irp->rm = irp->modrm & 7; | |
5716833c | 2940 | |
7ad10968 HZ |
2941 | return 0; |
2942 | } | |
d2a7c97a | 2943 | |
7ad10968 HZ |
2944 | /* Get the memory address that current instruction write to and set it to |
2945 | the argument "addr". | |
2946 | Return -1 if something wrong. */ | |
8201327c | 2947 | |
7ad10968 | 2948 | static int |
cf648174 | 2949 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 2950 | { |
cf648174 | 2951 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
2952 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2953 | gdb_byte buf[4]; | |
2954 | ULONGEST offset64; | |
21d0e8a4 | 2955 | |
7ad10968 HZ |
2956 | *addr = 0; |
2957 | if (irp->aflag) | |
2958 | { | |
2959 | /* 32 bits */ | |
2960 | int havesib = 0; | |
2961 | uint8_t scale = 0; | |
648d0c8b | 2962 | uint8_t byte; |
7ad10968 HZ |
2963 | uint8_t index = 0; |
2964 | uint8_t base = irp->rm; | |
896fb97d | 2965 | |
7ad10968 HZ |
2966 | if (base == 4) |
2967 | { | |
2968 | havesib = 1; | |
648d0c8b | 2969 | if (target_read_memory (irp->addr, &byte, 1)) |
7ad10968 HZ |
2970 | { |
2971 | if (record_debug) | |
2972 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2973 | "at addr %s len = 1.\n"), |
2974 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2975 | return -1; |
2976 | } | |
2977 | irp->addr++; | |
648d0c8b MS |
2978 | scale = (byte >> 6) & 3; |
2979 | index = ((byte >> 3) & 7) | irp->rex_x; | |
2980 | base = (byte & 7); | |
7ad10968 | 2981 | } |
cf648174 | 2982 | base |= irp->rex_b; |
21d0e8a4 | 2983 | |
7ad10968 HZ |
2984 | switch (irp->mod) |
2985 | { | |
2986 | case 0: | |
2987 | if ((base & 7) == 5) | |
2988 | { | |
2989 | base = 0xff; | |
60a1502a | 2990 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
2991 | { |
2992 | if (record_debug) | |
2993 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
2994 | "memory at addr %s len = 4.\n"), |
2995 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2996 | return -1; |
2997 | } | |
2998 | irp->addr += 4; | |
60a1502a | 2999 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
3000 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
3001 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 HZ |
3002 | } |
3003 | else | |
3004 | { | |
3005 | *addr = 0; | |
3006 | } | |
3007 | break; | |
3008 | case 1: | |
60a1502a | 3009 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3010 | { |
3011 | if (record_debug) | |
3012 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3013 | "at addr %s len = 1.\n"), |
3014 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3015 | return -1; |
3016 | } | |
3017 | irp->addr++; | |
60a1502a | 3018 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3019 | break; |
3020 | case 2: | |
60a1502a | 3021 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3022 | { |
3023 | if (record_debug) | |
3024 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3025 | "at addr %s len = 4.\n"), |
3026 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3027 | return -1; |
3028 | } | |
60a1502a | 3029 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
3030 | irp->addr += 4; |
3031 | break; | |
3032 | } | |
356a6b3e | 3033 | |
60a1502a | 3034 | offset64 = 0; |
7ad10968 | 3035 | if (base != 0xff) |
cf648174 HZ |
3036 | { |
3037 | if (base == 4 && irp->popl_esp_hack) | |
3038 | *addr += irp->popl_esp_hack; | |
3039 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 3040 | &offset64); |
7ad10968 | 3041 | } |
cf648174 HZ |
3042 | if (irp->aflag == 2) |
3043 | { | |
60a1502a | 3044 | *addr += offset64; |
cf648174 HZ |
3045 | } |
3046 | else | |
60a1502a | 3047 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 3048 | |
7ad10968 HZ |
3049 | if (havesib && (index != 4 || scale != 0)) |
3050 | { | |
cf648174 | 3051 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 3052 | &offset64); |
cf648174 | 3053 | if (irp->aflag == 2) |
60a1502a | 3054 | *addr += offset64 << scale; |
cf648174 | 3055 | else |
60a1502a | 3056 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 HZ |
3057 | } |
3058 | } | |
3059 | else | |
3060 | { | |
3061 | /* 16 bits */ | |
3062 | switch (irp->mod) | |
3063 | { | |
3064 | case 0: | |
3065 | if (irp->rm == 6) | |
3066 | { | |
60a1502a | 3067 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3068 | { |
3069 | if (record_debug) | |
3070 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3071 | "memory at addr %s len = 2.\n"), |
3072 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3073 | return -1; |
3074 | } | |
3075 | irp->addr += 2; | |
60a1502a | 3076 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3077 | irp->rm = 0; |
3078 | goto no_rm; | |
3079 | } | |
3080 | else | |
3081 | { | |
3082 | *addr = 0; | |
3083 | } | |
3084 | break; | |
3085 | case 1: | |
60a1502a | 3086 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3087 | { |
3088 | if (record_debug) | |
3089 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3090 | "at addr %s len = 1.\n"), |
3091 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3092 | return -1; |
3093 | } | |
3094 | irp->addr++; | |
60a1502a | 3095 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3096 | break; |
3097 | case 2: | |
60a1502a | 3098 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3099 | { |
3100 | if (record_debug) | |
3101 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3102 | "at addr %s len = 2.\n"), |
3103 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3104 | return -1; |
3105 | } | |
3106 | irp->addr += 2; | |
60a1502a | 3107 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3108 | break; |
3109 | } | |
c4fc7f1b | 3110 | |
7ad10968 HZ |
3111 | switch (irp->rm) |
3112 | { | |
3113 | case 0: | |
cf648174 HZ |
3114 | regcache_raw_read_unsigned (irp->regcache, |
3115 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3116 | &offset64); |
3117 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3118 | regcache_raw_read_unsigned (irp->regcache, |
3119 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3120 | &offset64); |
3121 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3122 | break; |
3123 | case 1: | |
cf648174 HZ |
3124 | regcache_raw_read_unsigned (irp->regcache, |
3125 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3126 | &offset64); |
3127 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3128 | regcache_raw_read_unsigned (irp->regcache, |
3129 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3130 | &offset64); |
3131 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3132 | break; |
3133 | case 2: | |
cf648174 HZ |
3134 | regcache_raw_read_unsigned (irp->regcache, |
3135 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3136 | &offset64); |
3137 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3138 | regcache_raw_read_unsigned (irp->regcache, |
3139 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3140 | &offset64); |
3141 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3142 | break; |
3143 | case 3: | |
cf648174 HZ |
3144 | regcache_raw_read_unsigned (irp->regcache, |
3145 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3146 | &offset64); |
3147 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3148 | regcache_raw_read_unsigned (irp->regcache, |
3149 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3150 | &offset64); |
3151 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3152 | break; |
3153 | case 4: | |
cf648174 HZ |
3154 | regcache_raw_read_unsigned (irp->regcache, |
3155 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3156 | &offset64); |
3157 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3158 | break; |
3159 | case 5: | |
cf648174 HZ |
3160 | regcache_raw_read_unsigned (irp->regcache, |
3161 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3162 | &offset64); |
3163 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3164 | break; |
3165 | case 6: | |
cf648174 HZ |
3166 | regcache_raw_read_unsigned (irp->regcache, |
3167 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3168 | &offset64); |
3169 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3170 | break; |
3171 | case 7: | |
cf648174 HZ |
3172 | regcache_raw_read_unsigned (irp->regcache, |
3173 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3174 | &offset64); |
3175 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3176 | break; |
3177 | } | |
3178 | *addr &= 0xffff; | |
3179 | } | |
c4fc7f1b | 3180 | |
01fe1b41 | 3181 | no_rm: |
7ad10968 HZ |
3182 | return 0; |
3183 | } | |
c4fc7f1b | 3184 | |
7ad10968 HZ |
3185 | /* Record the value of the memory that willbe changed in current instruction |
3186 | to "record_arch_list". | |
3187 | Return -1 if something wrong. */ | |
356a6b3e | 3188 | |
7ad10968 HZ |
3189 | static int |
3190 | i386_record_lea_modrm (struct i386_record_s *irp) | |
3191 | { | |
cf648174 HZ |
3192 | struct gdbarch *gdbarch = irp->gdbarch; |
3193 | uint64_t addr; | |
356a6b3e | 3194 | |
d7877f7e | 3195 | if (irp->override >= 0) |
7ad10968 | 3196 | { |
df61f520 HZ |
3197 | warning (_("Process record ignores the memory change " |
3198 | "of instruction at address %s because it " | |
3199 | "can't get the value of the segment register."), | |
3200 | paddress (gdbarch, irp->orig_addr)); | |
7ad10968 HZ |
3201 | return 0; |
3202 | } | |
61113f8b | 3203 | |
7ad10968 HZ |
3204 | if (i386_record_lea_modrm_addr (irp, &addr)) |
3205 | return -1; | |
96297dab | 3206 | |
7ad10968 HZ |
3207 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
3208 | return -1; | |
a62cc96e | 3209 | |
7ad10968 HZ |
3210 | return 0; |
3211 | } | |
b6197528 | 3212 | |
cf648174 HZ |
3213 | /* Record the push operation to "record_arch_list". |
3214 | Return -1 if something wrong. */ | |
3215 | ||
3216 | static int | |
3217 | i386_record_push (struct i386_record_s *irp, int size) | |
3218 | { | |
648d0c8b | 3219 | ULONGEST addr; |
cf648174 HZ |
3220 | |
3221 | if (record_arch_list_add_reg (irp->regcache, | |
3222 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
3223 | return -1; | |
3224 | regcache_raw_read_unsigned (irp->regcache, | |
3225 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b MS |
3226 | &addr); |
3227 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) | |
cf648174 HZ |
3228 | return -1; |
3229 | ||
3230 | return 0; | |
3231 | } | |
3232 | ||
0289bdd7 MS |
3233 | |
3234 | /* Defines contents to record. */ | |
3235 | #define I386_SAVE_FPU_REGS 0xfffd | |
3236 | #define I386_SAVE_FPU_ENV 0xfffe | |
3237 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
3238 | ||
3239 | /* Record the value of floating point registers which will be changed by the | |
3240 | current instruction to "record_arch_list". Return -1 if something is wrong. | |
3241 | */ | |
3242 | ||
3243 | static int i386_record_floats (struct gdbarch *gdbarch, | |
3244 | struct i386_record_s *ir, | |
3245 | uint32_t iregnum) | |
3246 | { | |
3247 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3248 | int i; | |
3249 | ||
3250 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
3251 | happen. Currently we store st0-st7 registers, but we need not store all | |
3252 | registers all the time, in future we use ftag register and record only | |
3253 | those who are not marked as an empty. */ | |
3254 | ||
3255 | if (I386_SAVE_FPU_REGS == iregnum) | |
3256 | { | |
3257 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
3258 | { | |
3259 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3260 | return -1; | |
3261 | } | |
3262 | } | |
3263 | else if (I386_SAVE_FPU_ENV == iregnum) | |
3264 | { | |
3265 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3266 | { | |
3267 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3268 | return -1; | |
3269 | } | |
3270 | } | |
3271 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
3272 | { | |
3273 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3274 | { | |
3275 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3276 | return -1; | |
3277 | } | |
3278 | } | |
3279 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
3280 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
3281 | { | |
3282 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
3283 | return -1; | |
3284 | } | |
3285 | else | |
3286 | { | |
3287 | /* Parameter error. */ | |
3288 | return -1; | |
3289 | } | |
3290 | if(I386_SAVE_FPU_ENV != iregnum) | |
3291 | { | |
3292 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3293 | { | |
3294 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3295 | return -1; | |
3296 | } | |
3297 | } | |
3298 | return 0; | |
3299 | } | |
3300 | ||
7ad10968 HZ |
3301 | /* Parse the current instruction and record the values of the registers and |
3302 | memory that will be changed in current instruction to "record_arch_list". | |
3303 | Return -1 if something wrong. */ | |
8201327c | 3304 | |
cf648174 HZ |
3305 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
3306 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
3307 | ||
a6b808b4 | 3308 | int |
7ad10968 | 3309 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 3310 | CORE_ADDR input_addr) |
7ad10968 | 3311 | { |
60a1502a | 3312 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 3313 | int prefixes = 0; |
580879fc | 3314 | int regnum = 0; |
425b824a MS |
3315 | uint32_t opcode; |
3316 | uint8_t opcode8; | |
648d0c8b | 3317 | ULONGEST addr; |
60a1502a | 3318 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 3319 | struct i386_record_s ir; |
0289bdd7 | 3320 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
3321 | int rex = 0; |
3322 | uint8_t rex_w = -1; | |
3323 | uint8_t rex_r = 0; | |
7ad10968 | 3324 | |
8408d274 | 3325 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 3326 | ir.regcache = regcache; |
648d0c8b MS |
3327 | ir.addr = input_addr; |
3328 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
3329 | ir.aflag = 1; |
3330 | ir.dflag = 1; | |
cf648174 HZ |
3331 | ir.override = -1; |
3332 | ir.popl_esp_hack = 0; | |
3333 | ir.regmap = gdbarch_tdep (gdbarch)->record_regmap; | |
3334 | ir.gdbarch = gdbarch; | |
7ad10968 HZ |
3335 | |
3336 | if (record_debug > 1) | |
3337 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
3338 | "addr = %s\n", |
3339 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3340 | |
3341 | /* prefixes */ | |
3342 | while (1) | |
3343 | { | |
425b824a | 3344 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
3345 | { |
3346 | if (record_debug) | |
3347 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3348 | "addr %s len = 1.\n"), |
3349 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3350 | return -1; |
3351 | } | |
3352 | ir.addr++; | |
425b824a | 3353 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 3354 | { |
01fe1b41 | 3355 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
3356 | prefixes |= PREFIX_REPZ; |
3357 | break; | |
01fe1b41 | 3358 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
3359 | prefixes |= PREFIX_REPNZ; |
3360 | break; | |
01fe1b41 | 3361 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
3362 | prefixes |= PREFIX_LOCK; |
3363 | break; | |
01fe1b41 | 3364 | case CS_PREFIX_OPCODE: |
cf648174 | 3365 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 3366 | break; |
01fe1b41 | 3367 | case SS_PREFIX_OPCODE: |
cf648174 | 3368 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 3369 | break; |
01fe1b41 | 3370 | case DS_PREFIX_OPCODE: |
cf648174 | 3371 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 3372 | break; |
01fe1b41 | 3373 | case ES_PREFIX_OPCODE: |
cf648174 | 3374 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 3375 | break; |
01fe1b41 | 3376 | case FS_PREFIX_OPCODE: |
cf648174 | 3377 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 3378 | break; |
01fe1b41 | 3379 | case GS_PREFIX_OPCODE: |
cf648174 | 3380 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 3381 | break; |
01fe1b41 | 3382 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
3383 | prefixes |= PREFIX_DATA; |
3384 | break; | |
01fe1b41 | 3385 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
3386 | prefixes |= PREFIX_ADDR; |
3387 | break; | |
d691bec7 MS |
3388 | case 0x40: /* i386 inc %eax */ |
3389 | case 0x41: /* i386 inc %ecx */ | |
3390 | case 0x42: /* i386 inc %edx */ | |
3391 | case 0x43: /* i386 inc %ebx */ | |
3392 | case 0x44: /* i386 inc %esp */ | |
3393 | case 0x45: /* i386 inc %ebp */ | |
3394 | case 0x46: /* i386 inc %esi */ | |
3395 | case 0x47: /* i386 inc %edi */ | |
3396 | case 0x48: /* i386 dec %eax */ | |
3397 | case 0x49: /* i386 dec %ecx */ | |
3398 | case 0x4a: /* i386 dec %edx */ | |
3399 | case 0x4b: /* i386 dec %ebx */ | |
3400 | case 0x4c: /* i386 dec %esp */ | |
3401 | case 0x4d: /* i386 dec %ebp */ | |
3402 | case 0x4e: /* i386 dec %esi */ | |
3403 | case 0x4f: /* i386 dec %edi */ | |
3404 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
3405 | { |
3406 | /* REX */ | |
3407 | rex = 1; | |
425b824a MS |
3408 | rex_w = (opcode8 >> 3) & 1; |
3409 | rex_r = (opcode8 & 0x4) << 1; | |
3410 | ir.rex_x = (opcode8 & 0x2) << 2; | |
3411 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 3412 | } |
d691bec7 MS |
3413 | else /* 32 bit target */ |
3414 | goto out_prefixes; | |
cf648174 | 3415 | break; |
7ad10968 HZ |
3416 | default: |
3417 | goto out_prefixes; | |
3418 | break; | |
3419 | } | |
3420 | } | |
01fe1b41 | 3421 | out_prefixes: |
cf648174 HZ |
3422 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
3423 | { | |
3424 | ir.dflag = 2; | |
3425 | } | |
3426 | else | |
3427 | { | |
3428 | if (prefixes & PREFIX_DATA) | |
3429 | ir.dflag ^= 1; | |
3430 | } | |
7ad10968 HZ |
3431 | if (prefixes & PREFIX_ADDR) |
3432 | ir.aflag ^= 1; | |
cf648174 HZ |
3433 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3434 | ir.aflag = 2; | |
7ad10968 HZ |
3435 | |
3436 | /* now check op code */ | |
425b824a | 3437 | opcode = (uint32_t) opcode8; |
01fe1b41 | 3438 | reswitch: |
7ad10968 HZ |
3439 | switch (opcode) |
3440 | { | |
3441 | case 0x0f: | |
425b824a | 3442 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
3443 | { |
3444 | if (record_debug) | |
3445 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3446 | "addr %s len = 1.\n"), |
3447 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3448 | return -1; |
3449 | } | |
3450 | ir.addr++; | |
425b824a | 3451 | opcode = (uint16_t) opcode8 | 0x0f00; |
7ad10968 HZ |
3452 | goto reswitch; |
3453 | break; | |
93924b6b | 3454 | |
a38bba38 | 3455 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
3456 | case 0x01: |
3457 | case 0x02: | |
3458 | case 0x03: | |
3459 | case 0x04: | |
3460 | case 0x05: | |
3461 | case 0x08: | |
3462 | case 0x09: | |
3463 | case 0x0a: | |
3464 | case 0x0b: | |
3465 | case 0x0c: | |
3466 | case 0x0d: | |
3467 | case 0x10: | |
3468 | case 0x11: | |
3469 | case 0x12: | |
3470 | case 0x13: | |
3471 | case 0x14: | |
3472 | case 0x15: | |
3473 | case 0x18: | |
3474 | case 0x19: | |
3475 | case 0x1a: | |
3476 | case 0x1b: | |
3477 | case 0x1c: | |
3478 | case 0x1d: | |
3479 | case 0x20: | |
3480 | case 0x21: | |
3481 | case 0x22: | |
3482 | case 0x23: | |
3483 | case 0x24: | |
3484 | case 0x25: | |
3485 | case 0x28: | |
3486 | case 0x29: | |
3487 | case 0x2a: | |
3488 | case 0x2b: | |
3489 | case 0x2c: | |
3490 | case 0x2d: | |
3491 | case 0x30: | |
3492 | case 0x31: | |
3493 | case 0x32: | |
3494 | case 0x33: | |
3495 | case 0x34: | |
3496 | case 0x35: | |
3497 | case 0x38: | |
3498 | case 0x39: | |
3499 | case 0x3a: | |
3500 | case 0x3b: | |
3501 | case 0x3c: | |
3502 | case 0x3d: | |
3503 | if (((opcode >> 3) & 7) != OP_CMPL) | |
3504 | { | |
3505 | if ((opcode & 1) == 0) | |
3506 | ir.ot = OT_BYTE; | |
3507 | else | |
3508 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 3509 | |
7ad10968 HZ |
3510 | switch ((opcode >> 1) & 3) |
3511 | { | |
a38bba38 | 3512 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
3513 | if (i386_record_modrm (&ir)) |
3514 | return -1; | |
3515 | if (ir.mod != 3) | |
3516 | { | |
3517 | if (i386_record_lea_modrm (&ir)) | |
3518 | return -1; | |
3519 | } | |
3520 | else | |
3521 | { | |
cf648174 HZ |
3522 | ir.rm |= ir.rex_b; |
3523 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3524 | ir.rm &= 0x3; |
cf648174 | 3525 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3526 | } |
3527 | break; | |
a38bba38 | 3528 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
3529 | if (i386_record_modrm (&ir)) |
3530 | return -1; | |
cf648174 HZ |
3531 | ir.reg |= rex_r; |
3532 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3533 | ir.reg &= 0x3; |
cf648174 | 3534 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3535 | break; |
a38bba38 | 3536 | case 2: /* OP A, Iv */ |
cf648174 | 3537 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3538 | break; |
3539 | } | |
3540 | } | |
cf648174 | 3541 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3542 | break; |
42fdc8df | 3543 | |
a38bba38 | 3544 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
3545 | case 0x81: |
3546 | case 0x82: | |
3547 | case 0x83: | |
3548 | if (i386_record_modrm (&ir)) | |
3549 | return -1; | |
8201327c | 3550 | |
7ad10968 HZ |
3551 | if (ir.reg != OP_CMPL) |
3552 | { | |
3553 | if ((opcode & 1) == 0) | |
3554 | ir.ot = OT_BYTE; | |
3555 | else | |
3556 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 3557 | |
7ad10968 HZ |
3558 | if (ir.mod != 3) |
3559 | { | |
cf648174 HZ |
3560 | if (opcode == 0x83) |
3561 | ir.rip_offset = 1; | |
3562 | else | |
3563 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3564 | if (i386_record_lea_modrm (&ir)) |
3565 | return -1; | |
3566 | } | |
3567 | else | |
cf648174 | 3568 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 3569 | } |
cf648174 | 3570 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3571 | break; |
5e3397bb | 3572 | |
a38bba38 | 3573 | case 0x40: /* inc */ |
7ad10968 HZ |
3574 | case 0x41: |
3575 | case 0x42: | |
3576 | case 0x43: | |
3577 | case 0x44: | |
3578 | case 0x45: | |
3579 | case 0x46: | |
3580 | case 0x47: | |
a38bba38 MS |
3581 | |
3582 | case 0x48: /* dec */ | |
7ad10968 HZ |
3583 | case 0x49: |
3584 | case 0x4a: | |
3585 | case 0x4b: | |
3586 | case 0x4c: | |
3587 | case 0x4d: | |
3588 | case 0x4e: | |
3589 | case 0x4f: | |
a38bba38 | 3590 | |
cf648174 HZ |
3591 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
3592 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 3593 | break; |
acd5c798 | 3594 | |
a38bba38 | 3595 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
3596 | case 0xf7: |
3597 | if ((opcode & 1) == 0) | |
3598 | ir.ot = OT_BYTE; | |
3599 | else | |
3600 | ir.ot = ir.dflag + OT_WORD; | |
3601 | if (i386_record_modrm (&ir)) | |
3602 | return -1; | |
acd5c798 | 3603 | |
cf648174 HZ |
3604 | if (ir.mod != 3 && ir.reg == 0) |
3605 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3606 | ||
7ad10968 HZ |
3607 | switch (ir.reg) |
3608 | { | |
a38bba38 | 3609 | case 0: /* test */ |
cf648174 | 3610 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3611 | break; |
a38bba38 MS |
3612 | case 2: /* not */ |
3613 | case 3: /* neg */ | |
7ad10968 HZ |
3614 | if (ir.mod != 3) |
3615 | { | |
3616 | if (i386_record_lea_modrm (&ir)) | |
3617 | return -1; | |
3618 | } | |
3619 | else | |
3620 | { | |
cf648174 HZ |
3621 | ir.rm |= ir.rex_b; |
3622 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3623 | ir.rm &= 0x3; |
cf648174 | 3624 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3625 | } |
a38bba38 | 3626 | if (ir.reg == 3) /* neg */ |
cf648174 | 3627 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3628 | break; |
a38bba38 MS |
3629 | case 4: /* mul */ |
3630 | case 5: /* imul */ | |
3631 | case 6: /* div */ | |
3632 | case 7: /* idiv */ | |
cf648174 | 3633 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 3634 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
3635 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
3636 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3637 | break; |
3638 | default: | |
3639 | ir.addr -= 2; | |
3640 | opcode = opcode << 8 | ir.modrm; | |
3641 | goto no_support; | |
3642 | break; | |
3643 | } | |
3644 | break; | |
3645 | ||
a38bba38 MS |
3646 | case 0xfe: /* GRP4 */ |
3647 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
3648 | if (i386_record_modrm (&ir)) |
3649 | return -1; | |
3650 | if (ir.reg >= 2 && opcode == 0xfe) | |
3651 | { | |
3652 | ir.addr -= 2; | |
3653 | opcode = opcode << 8 | ir.modrm; | |
3654 | goto no_support; | |
3655 | } | |
7ad10968 HZ |
3656 | switch (ir.reg) |
3657 | { | |
a38bba38 MS |
3658 | case 0: /* inc */ |
3659 | case 1: /* dec */ | |
cf648174 HZ |
3660 | if ((opcode & 1) == 0) |
3661 | ir.ot = OT_BYTE; | |
3662 | else | |
3663 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3664 | if (ir.mod != 3) |
3665 | { | |
3666 | if (i386_record_lea_modrm (&ir)) | |
3667 | return -1; | |
3668 | } | |
3669 | else | |
3670 | { | |
cf648174 HZ |
3671 | ir.rm |= ir.rex_b; |
3672 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3673 | ir.rm &= 0x3; |
cf648174 | 3674 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3675 | } |
cf648174 | 3676 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3677 | break; |
a38bba38 | 3678 | case 2: /* call */ |
cf648174 HZ |
3679 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3680 | ir.dflag = 2; | |
3681 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3682 | return -1; |
cf648174 | 3683 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3684 | break; |
a38bba38 | 3685 | case 3: /* lcall */ |
cf648174 HZ |
3686 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
3687 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3688 | return -1; |
cf648174 | 3689 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3690 | break; |
a38bba38 MS |
3691 | case 4: /* jmp */ |
3692 | case 5: /* ljmp */ | |
cf648174 HZ |
3693 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
3694 | break; | |
a38bba38 | 3695 | case 6: /* push */ |
cf648174 HZ |
3696 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3697 | ir.dflag = 2; | |
3698 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3699 | return -1; | |
7ad10968 HZ |
3700 | break; |
3701 | default: | |
3702 | ir.addr -= 2; | |
3703 | opcode = opcode << 8 | ir.modrm; | |
3704 | goto no_support; | |
3705 | break; | |
3706 | } | |
3707 | break; | |
3708 | ||
a38bba38 | 3709 | case 0x84: /* test */ |
7ad10968 HZ |
3710 | case 0x85: |
3711 | case 0xa8: | |
3712 | case 0xa9: | |
cf648174 | 3713 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3714 | break; |
3715 | ||
a38bba38 | 3716 | case 0x98: /* CWDE/CBW */ |
cf648174 | 3717 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3718 | break; |
3719 | ||
a38bba38 | 3720 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
3721 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3722 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3723 | break; |
3724 | ||
a38bba38 | 3725 | case 0x0faf: /* imul */ |
7ad10968 HZ |
3726 | case 0x69: |
3727 | case 0x6b: | |
3728 | ir.ot = ir.dflag + OT_WORD; | |
3729 | if (i386_record_modrm (&ir)) | |
3730 | return -1; | |
cf648174 HZ |
3731 | if (opcode == 0x69) |
3732 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3733 | else if (opcode == 0x6b) | |
3734 | ir.rip_offset = 1; | |
3735 | ir.reg |= rex_r; | |
3736 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3737 | ir.reg &= 0x3; |
cf648174 HZ |
3738 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3739 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3740 | break; |
3741 | ||
a38bba38 | 3742 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
3743 | case 0x0fc1: |
3744 | if ((opcode & 1) == 0) | |
3745 | ir.ot = OT_BYTE; | |
3746 | else | |
3747 | ir.ot = ir.dflag + OT_WORD; | |
3748 | if (i386_record_modrm (&ir)) | |
3749 | return -1; | |
cf648174 | 3750 | ir.reg |= rex_r; |
7ad10968 HZ |
3751 | if (ir.mod == 3) |
3752 | { | |
cf648174 | 3753 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 3754 | ir.reg &= 0x3; |
cf648174 HZ |
3755 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3756 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3757 | ir.rm &= 0x3; |
cf648174 | 3758 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3759 | } |
3760 | else | |
3761 | { | |
3762 | if (i386_record_lea_modrm (&ir)) | |
3763 | return -1; | |
cf648174 | 3764 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 3765 | ir.reg &= 0x3; |
cf648174 | 3766 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3767 | } |
cf648174 | 3768 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3769 | break; |
3770 | ||
a38bba38 | 3771 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
3772 | case 0x0fb1: |
3773 | if ((opcode & 1) == 0) | |
3774 | ir.ot = OT_BYTE; | |
3775 | else | |
3776 | ir.ot = ir.dflag + OT_WORD; | |
3777 | if (i386_record_modrm (&ir)) | |
3778 | return -1; | |
3779 | if (ir.mod == 3) | |
3780 | { | |
cf648174 HZ |
3781 | ir.reg |= rex_r; |
3782 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
3783 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3784 | ir.reg &= 0x3; |
cf648174 | 3785 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
3786 | } |
3787 | else | |
3788 | { | |
cf648174 | 3789 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3790 | if (i386_record_lea_modrm (&ir)) |
3791 | return -1; | |
3792 | } | |
cf648174 | 3793 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3794 | break; |
3795 | ||
a38bba38 | 3796 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
3797 | if (i386_record_modrm (&ir)) |
3798 | return -1; | |
3799 | if (ir.mod == 3) | |
3800 | { | |
3801 | ir.addr -= 2; | |
3802 | opcode = opcode << 8 | ir.modrm; | |
3803 | goto no_support; | |
3804 | } | |
cf648174 HZ |
3805 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3806 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3807 | if (i386_record_lea_modrm (&ir)) |
3808 | return -1; | |
cf648174 | 3809 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3810 | break; |
3811 | ||
a38bba38 | 3812 | case 0x50: /* push */ |
7ad10968 HZ |
3813 | case 0x51: |
3814 | case 0x52: | |
3815 | case 0x53: | |
3816 | case 0x54: | |
3817 | case 0x55: | |
3818 | case 0x56: | |
3819 | case 0x57: | |
3820 | case 0x68: | |
3821 | case 0x6a: | |
cf648174 HZ |
3822 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3823 | ir.dflag = 2; | |
3824 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3825 | return -1; | |
3826 | break; | |
3827 | ||
a38bba38 MS |
3828 | case 0x06: /* push es */ |
3829 | case 0x0e: /* push cs */ | |
3830 | case 0x16: /* push ss */ | |
3831 | case 0x1e: /* push ds */ | |
cf648174 HZ |
3832 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3833 | { | |
3834 | ir.addr -= 1; | |
3835 | goto no_support; | |
3836 | } | |
3837 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3838 | return -1; | |
3839 | break; | |
3840 | ||
a38bba38 MS |
3841 | case 0x0fa0: /* push fs */ |
3842 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
3843 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3844 | { | |
3845 | ir.addr -= 2; | |
3846 | goto no_support; | |
3847 | } | |
3848 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3849 | return -1; |
cf648174 HZ |
3850 | break; |
3851 | ||
a38bba38 | 3852 | case 0x60: /* pusha */ |
cf648174 HZ |
3853 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3854 | { | |
3855 | ir.addr -= 1; | |
3856 | goto no_support; | |
3857 | } | |
3858 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
3859 | return -1; |
3860 | break; | |
3861 | ||
a38bba38 | 3862 | case 0x58: /* pop */ |
7ad10968 HZ |
3863 | case 0x59: |
3864 | case 0x5a: | |
3865 | case 0x5b: | |
3866 | case 0x5c: | |
3867 | case 0x5d: | |
3868 | case 0x5e: | |
3869 | case 0x5f: | |
cf648174 HZ |
3870 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3871 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
3872 | break; |
3873 | ||
a38bba38 | 3874 | case 0x61: /* popa */ |
cf648174 HZ |
3875 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3876 | { | |
3877 | ir.addr -= 1; | |
3878 | goto no_support; | |
7ad10968 | 3879 | } |
425b824a MS |
3880 | for (regnum = X86_RECORD_REAX_REGNUM; |
3881 | regnum <= X86_RECORD_REDI_REGNUM; | |
3882 | regnum++) | |
3883 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); | |
7ad10968 HZ |
3884 | break; |
3885 | ||
a38bba38 | 3886 | case 0x8f: /* pop */ |
cf648174 HZ |
3887 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3888 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
3889 | else | |
3890 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3891 | if (i386_record_modrm (&ir)) |
3892 | return -1; | |
3893 | if (ir.mod == 3) | |
cf648174 | 3894 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
3895 | else |
3896 | { | |
cf648174 | 3897 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
3898 | if (i386_record_lea_modrm (&ir)) |
3899 | return -1; | |
3900 | } | |
cf648174 | 3901 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
3902 | break; |
3903 | ||
a38bba38 | 3904 | case 0xc8: /* enter */ |
cf648174 HZ |
3905 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
3906 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
3907 | ir.dflag = 2; | |
3908 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
3909 | return -1; |
3910 | break; | |
3911 | ||
a38bba38 | 3912 | case 0xc9: /* leave */ |
cf648174 HZ |
3913 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3914 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
3915 | break; |
3916 | ||
a38bba38 | 3917 | case 0x07: /* pop es */ |
cf648174 HZ |
3918 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3919 | { | |
3920 | ir.addr -= 1; | |
3921 | goto no_support; | |
3922 | } | |
3923 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3924 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
3925 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3926 | break; |
3927 | ||
a38bba38 | 3928 | case 0x17: /* pop ss */ |
cf648174 HZ |
3929 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3930 | { | |
3931 | ir.addr -= 1; | |
3932 | goto no_support; | |
3933 | } | |
3934 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3935 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
3936 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3937 | break; |
3938 | ||
a38bba38 | 3939 | case 0x1f: /* pop ds */ |
cf648174 HZ |
3940 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3941 | { | |
3942 | ir.addr -= 1; | |
3943 | goto no_support; | |
3944 | } | |
3945 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3946 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
3947 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3948 | break; |
3949 | ||
a38bba38 | 3950 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
3951 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3952 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
3953 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3954 | break; |
3955 | ||
a38bba38 | 3956 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
3957 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3958 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
3959 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3960 | break; |
3961 | ||
a38bba38 | 3962 | case 0x88: /* mov */ |
7ad10968 HZ |
3963 | case 0x89: |
3964 | case 0xc6: | |
3965 | case 0xc7: | |
3966 | if ((opcode & 1) == 0) | |
3967 | ir.ot = OT_BYTE; | |
3968 | else | |
3969 | ir.ot = ir.dflag + OT_WORD; | |
3970 | ||
3971 | if (i386_record_modrm (&ir)) | |
3972 | return -1; | |
3973 | ||
3974 | if (ir.mod != 3) | |
3975 | { | |
cf648174 HZ |
3976 | if (opcode == 0xc6 || opcode == 0xc7) |
3977 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3978 | if (i386_record_lea_modrm (&ir)) |
3979 | return -1; | |
3980 | } | |
3981 | else | |
3982 | { | |
cf648174 HZ |
3983 | if (opcode == 0xc6 || opcode == 0xc7) |
3984 | ir.rm |= ir.rex_b; | |
3985 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3986 | ir.rm &= 0x3; |
cf648174 | 3987 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3988 | } |
7ad10968 | 3989 | break; |
cf648174 | 3990 | |
a38bba38 | 3991 | case 0x8a: /* mov */ |
7ad10968 HZ |
3992 | case 0x8b: |
3993 | if ((opcode & 1) == 0) | |
3994 | ir.ot = OT_BYTE; | |
3995 | else | |
3996 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3997 | if (i386_record_modrm (&ir)) |
3998 | return -1; | |
cf648174 HZ |
3999 | ir.reg |= rex_r; |
4000 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4001 | ir.reg &= 0x3; |
cf648174 HZ |
4002 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4003 | break; | |
7ad10968 | 4004 | |
a38bba38 | 4005 | case 0x8c: /* mov seg */ |
cf648174 | 4006 | if (i386_record_modrm (&ir)) |
7ad10968 | 4007 | return -1; |
cf648174 HZ |
4008 | if (ir.reg > 5) |
4009 | { | |
4010 | ir.addr -= 2; | |
4011 | opcode = opcode << 8 | ir.modrm; | |
4012 | goto no_support; | |
4013 | } | |
4014 | ||
4015 | if (ir.mod == 3) | |
4016 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
4017 | else | |
4018 | { | |
4019 | ir.ot = OT_WORD; | |
4020 | if (i386_record_lea_modrm (&ir)) | |
4021 | return -1; | |
4022 | } | |
7ad10968 HZ |
4023 | break; |
4024 | ||
a38bba38 | 4025 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
4026 | if (i386_record_modrm (&ir)) |
4027 | return -1; | |
7ad10968 HZ |
4028 | switch (ir.reg) |
4029 | { | |
4030 | case 0: | |
425b824a | 4031 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
4032 | break; |
4033 | case 2: | |
425b824a | 4034 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
4035 | break; |
4036 | case 3: | |
425b824a | 4037 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
4038 | break; |
4039 | case 4: | |
425b824a | 4040 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
4041 | break; |
4042 | case 5: | |
425b824a | 4043 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4044 | break; |
4045 | default: | |
4046 | ir.addr -= 2; | |
4047 | opcode = opcode << 8 | ir.modrm; | |
4048 | goto no_support; | |
4049 | break; | |
4050 | } | |
425b824a | 4051 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 | 4052 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4053 | break; |
4054 | ||
a38bba38 MS |
4055 | case 0x0fb6: /* movzbS */ |
4056 | case 0x0fb7: /* movzwS */ | |
4057 | case 0x0fbe: /* movsbS */ | |
4058 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
4059 | if (i386_record_modrm (&ir)) |
4060 | return -1; | |
cf648174 | 4061 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
4062 | break; |
4063 | ||
a38bba38 | 4064 | case 0x8d: /* lea */ |
7ad10968 HZ |
4065 | if (i386_record_modrm (&ir)) |
4066 | return -1; | |
4067 | if (ir.mod == 3) | |
4068 | { | |
4069 | ir.addr -= 2; | |
4070 | opcode = opcode << 8 | ir.modrm; | |
4071 | goto no_support; | |
4072 | } | |
7ad10968 | 4073 | ir.ot = ir.dflag; |
cf648174 HZ |
4074 | ir.reg |= rex_r; |
4075 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4076 | ir.reg &= 0x3; |
cf648174 | 4077 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4078 | break; |
4079 | ||
a38bba38 | 4080 | case 0xa0: /* mov EAX */ |
7ad10968 | 4081 | case 0xa1: |
a38bba38 MS |
4082 | |
4083 | case 0xd7: /* xlat */ | |
cf648174 | 4084 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4085 | break; |
4086 | ||
a38bba38 | 4087 | case 0xa2: /* mov EAX */ |
7ad10968 | 4088 | case 0xa3: |
d7877f7e | 4089 | if (ir.override >= 0) |
cf648174 | 4090 | { |
df61f520 | 4091 | warning (_("Process record ignores the memory change " |
926569ae | 4092 | "of instruction at address %s because " |
df61f520 HZ |
4093 | "it can't get the value of the segment " |
4094 | "register."), | |
4095 | paddress (gdbarch, ir.orig_addr)); | |
cf648174 HZ |
4096 | } |
4097 | else | |
4098 | { | |
4099 | if ((opcode & 1) == 0) | |
4100 | ir.ot = OT_BYTE; | |
4101 | else | |
4102 | ir.ot = ir.dflag + OT_WORD; | |
4103 | if (ir.aflag == 2) | |
4104 | { | |
60a1502a | 4105 | if (target_read_memory (ir.addr, buf, 8)) |
cf648174 HZ |
4106 | { |
4107 | if (record_debug) | |
4108 | printf_unfiltered (_("Process record: error reading " | |
4109 | "memory at addr 0x%s len = 8.\n"), | |
4110 | paddress (gdbarch, ir.addr)); | |
4111 | return -1; | |
4112 | } | |
4113 | ir.addr += 8; | |
60a1502a | 4114 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
4115 | } |
4116 | else if (ir.aflag) | |
4117 | { | |
60a1502a | 4118 | if (target_read_memory (ir.addr, buf, 4)) |
cf648174 HZ |
4119 | { |
4120 | if (record_debug) | |
4121 | printf_unfiltered (_("Process record: error reading " | |
4122 | "memory at addr 0x%s len = 4.\n"), | |
4123 | paddress (gdbarch, ir.addr)); | |
4124 | return -1; | |
4125 | } | |
4126 | ir.addr += 4; | |
60a1502a | 4127 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
4128 | } |
4129 | else | |
4130 | { | |
60a1502a | 4131 | if (target_read_memory (ir.addr, buf, 2)) |
cf648174 HZ |
4132 | { |
4133 | if (record_debug) | |
4134 | printf_unfiltered (_("Process record: error reading " | |
4135 | "memory at addr 0x%s len = 2.\n"), | |
4136 | paddress (gdbarch, ir.addr)); | |
4137 | return -1; | |
4138 | } | |
4139 | ir.addr += 2; | |
60a1502a | 4140 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 4141 | } |
648d0c8b | 4142 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
4143 | return -1; |
4144 | } | |
7ad10968 HZ |
4145 | break; |
4146 | ||
a38bba38 | 4147 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
4148 | case 0xb1: |
4149 | case 0xb2: | |
4150 | case 0xb3: | |
4151 | case 0xb4: | |
4152 | case 0xb5: | |
4153 | case 0xb6: | |
4154 | case 0xb7: | |
cf648174 HZ |
4155 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
4156 | ? ((opcode & 0x7) | ir.rex_b) | |
4157 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
4158 | break; |
4159 | ||
a38bba38 | 4160 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
4161 | case 0xb9: |
4162 | case 0xba: | |
4163 | case 0xbb: | |
4164 | case 0xbc: | |
4165 | case 0xbd: | |
4166 | case 0xbe: | |
4167 | case 0xbf: | |
cf648174 | 4168 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
4169 | break; |
4170 | ||
a38bba38 | 4171 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
4172 | case 0x92: |
4173 | case 0x93: | |
4174 | case 0x94: | |
4175 | case 0x95: | |
4176 | case 0x96: | |
4177 | case 0x97: | |
cf648174 HZ |
4178 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4179 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
4180 | break; |
4181 | ||
a38bba38 | 4182 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
4183 | case 0x87: |
4184 | if ((opcode & 1) == 0) | |
4185 | ir.ot = OT_BYTE; | |
4186 | else | |
4187 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4188 | if (i386_record_modrm (&ir)) |
4189 | return -1; | |
7ad10968 HZ |
4190 | if (ir.mod == 3) |
4191 | { | |
86839d38 | 4192 | ir.rm |= ir.rex_b; |
cf648174 HZ |
4193 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
4194 | ir.rm &= 0x3; | |
4195 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
4196 | } |
4197 | else | |
4198 | { | |
4199 | if (i386_record_lea_modrm (&ir)) | |
4200 | return -1; | |
4201 | } | |
cf648174 HZ |
4202 | ir.reg |= rex_r; |
4203 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4204 | ir.reg &= 0x3; |
cf648174 | 4205 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4206 | break; |
4207 | ||
a38bba38 MS |
4208 | case 0xc4: /* les Gv */ |
4209 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
4210 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4211 | { | |
4212 | ir.addr -= 1; | |
4213 | goto no_support; | |
4214 | } | |
a38bba38 MS |
4215 | case 0x0fb2: /* lss Gv */ |
4216 | case 0x0fb4: /* lfs Gv */ | |
4217 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
4218 | if (i386_record_modrm (&ir)) |
4219 | return -1; | |
4220 | if (ir.mod == 3) | |
4221 | { | |
4222 | if (opcode > 0xff) | |
4223 | ir.addr -= 3; | |
4224 | else | |
4225 | ir.addr -= 2; | |
4226 | opcode = opcode << 8 | ir.modrm; | |
4227 | goto no_support; | |
4228 | } | |
7ad10968 HZ |
4229 | switch (opcode) |
4230 | { | |
a38bba38 | 4231 | case 0xc4: /* les Gv */ |
425b824a | 4232 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 4233 | break; |
a38bba38 | 4234 | case 0xc5: /* lds Gv */ |
425b824a | 4235 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 4236 | break; |
a38bba38 | 4237 | case 0x0fb2: /* lss Gv */ |
425b824a | 4238 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 4239 | break; |
a38bba38 | 4240 | case 0x0fb4: /* lfs Gv */ |
425b824a | 4241 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 4242 | break; |
a38bba38 | 4243 | case 0x0fb5: /* lgs Gv */ |
425b824a | 4244 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4245 | break; |
4246 | } | |
425b824a | 4247 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 HZ |
4248 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
4249 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4250 | break; |
4251 | ||
a38bba38 | 4252 | case 0xc0: /* shifts */ |
7ad10968 HZ |
4253 | case 0xc1: |
4254 | case 0xd0: | |
4255 | case 0xd1: | |
4256 | case 0xd2: | |
4257 | case 0xd3: | |
4258 | if ((opcode & 1) == 0) | |
4259 | ir.ot = OT_BYTE; | |
4260 | else | |
4261 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4262 | if (i386_record_modrm (&ir)) |
4263 | return -1; | |
7ad10968 HZ |
4264 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
4265 | { | |
4266 | if (i386_record_lea_modrm (&ir)) | |
4267 | return -1; | |
4268 | } | |
4269 | else | |
4270 | { | |
cf648174 HZ |
4271 | ir.rm |= ir.rex_b; |
4272 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4273 | ir.rm &= 0x3; |
cf648174 | 4274 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4275 | } |
cf648174 | 4276 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4277 | break; |
4278 | ||
4279 | case 0x0fa4: | |
4280 | case 0x0fa5: | |
4281 | case 0x0fac: | |
4282 | case 0x0fad: | |
4283 | if (i386_record_modrm (&ir)) | |
4284 | return -1; | |
4285 | if (ir.mod == 3) | |
4286 | { | |
4287 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4288 | return -1; | |
4289 | } | |
4290 | else | |
4291 | { | |
4292 | if (i386_record_lea_modrm (&ir)) | |
4293 | return -1; | |
4294 | } | |
4295 | break; | |
4296 | ||
a38bba38 | 4297 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
4298 | case 0xd9: |
4299 | case 0xda: | |
4300 | case 0xdb: | |
4301 | case 0xdc: | |
4302 | case 0xdd: | |
4303 | case 0xde: | |
4304 | case 0xdf: | |
4305 | if (i386_record_modrm (&ir)) | |
4306 | return -1; | |
4307 | ir.reg |= ((opcode & 7) << 3); | |
4308 | if (ir.mod != 3) | |
4309 | { | |
0289bdd7 | 4310 | /* Memory. */ |
955db0c0 | 4311 | uint64_t addr64; |
7ad10968 | 4312 | |
955db0c0 | 4313 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
4314 | return -1; |
4315 | switch (ir.reg) | |
4316 | { | |
7ad10968 | 4317 | case 0x02: |
0289bdd7 MS |
4318 | case 0x12: |
4319 | case 0x22: | |
4320 | case 0x32: | |
4321 | /* For fcom, ficom nothing to do. */ | |
4322 | break; | |
7ad10968 | 4323 | case 0x03: |
0289bdd7 MS |
4324 | case 0x13: |
4325 | case 0x23: | |
4326 | case 0x33: | |
4327 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
4328 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4329 | return -1; | |
4330 | break; | |
4331 | case 0x00: | |
4332 | case 0x01: | |
7ad10968 HZ |
4333 | case 0x04: |
4334 | case 0x05: | |
4335 | case 0x06: | |
4336 | case 0x07: | |
4337 | case 0x10: | |
4338 | case 0x11: | |
7ad10968 HZ |
4339 | case 0x14: |
4340 | case 0x15: | |
4341 | case 0x16: | |
4342 | case 0x17: | |
4343 | case 0x20: | |
4344 | case 0x21: | |
7ad10968 HZ |
4345 | case 0x24: |
4346 | case 0x25: | |
4347 | case 0x26: | |
4348 | case 0x27: | |
4349 | case 0x30: | |
4350 | case 0x31: | |
7ad10968 HZ |
4351 | case 0x34: |
4352 | case 0x35: | |
4353 | case 0x36: | |
4354 | case 0x37: | |
0289bdd7 MS |
4355 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
4356 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
4357 | of code, always affects st(0) register. */ | |
4358 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4359 | return -1; | |
7ad10968 HZ |
4360 | break; |
4361 | case 0x08: | |
4362 | case 0x0a: | |
4363 | case 0x0b: | |
4364 | case 0x18: | |
4365 | case 0x19: | |
4366 | case 0x1a: | |
4367 | case 0x1b: | |
0289bdd7 | 4368 | case 0x1d: |
7ad10968 HZ |
4369 | case 0x28: |
4370 | case 0x29: | |
4371 | case 0x2a: | |
4372 | case 0x2b: | |
4373 | case 0x38: | |
4374 | case 0x39: | |
4375 | case 0x3a: | |
4376 | case 0x3b: | |
0289bdd7 MS |
4377 | case 0x3c: |
4378 | case 0x3d: | |
7ad10968 HZ |
4379 | switch (ir.reg & 7) |
4380 | { | |
4381 | case 0: | |
0289bdd7 MS |
4382 | /* Handling fld, fild. */ |
4383 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4384 | return -1; | |
7ad10968 HZ |
4385 | break; |
4386 | case 1: | |
4387 | switch (ir.reg >> 4) | |
4388 | { | |
4389 | case 0: | |
955db0c0 | 4390 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
4391 | return -1; |
4392 | break; | |
4393 | case 2: | |
955db0c0 | 4394 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
4395 | return -1; |
4396 | break; | |
4397 | case 3: | |
0289bdd7 | 4398 | break; |
7ad10968 | 4399 | default: |
955db0c0 | 4400 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
4401 | return -1; |
4402 | break; | |
4403 | } | |
4404 | break; | |
4405 | default: | |
4406 | switch (ir.reg >> 4) | |
4407 | { | |
4408 | case 0: | |
955db0c0 | 4409 | if (record_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
4410 | return -1; |
4411 | if (3 == (ir.reg & 7)) | |
4412 | { | |
4413 | /* For fstp m32fp. */ | |
4414 | if (i386_record_floats (gdbarch, &ir, | |
4415 | I386_SAVE_FPU_REGS)) | |
4416 | return -1; | |
4417 | } | |
4418 | break; | |
7ad10968 | 4419 | case 1: |
955db0c0 | 4420 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 | 4421 | return -1; |
0289bdd7 MS |
4422 | if ((3 == (ir.reg & 7)) |
4423 | || (5 == (ir.reg & 7)) | |
4424 | || (7 == (ir.reg & 7))) | |
4425 | { | |
4426 | /* For fstp insn. */ | |
4427 | if (i386_record_floats (gdbarch, &ir, | |
4428 | I386_SAVE_FPU_REGS)) | |
4429 | return -1; | |
4430 | } | |
7ad10968 HZ |
4431 | break; |
4432 | case 2: | |
955db0c0 | 4433 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 4434 | return -1; |
0289bdd7 MS |
4435 | if (3 == (ir.reg & 7)) |
4436 | { | |
4437 | /* For fstp m64fp. */ | |
4438 | if (i386_record_floats (gdbarch, &ir, | |
4439 | I386_SAVE_FPU_REGS)) | |
4440 | return -1; | |
4441 | } | |
7ad10968 HZ |
4442 | break; |
4443 | case 3: | |
0289bdd7 MS |
4444 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
4445 | { | |
4446 | /* For fistp, fbld, fild, fbstp. */ | |
4447 | if (i386_record_floats (gdbarch, &ir, | |
4448 | I386_SAVE_FPU_REGS)) | |
4449 | return -1; | |
4450 | } | |
4451 | /* Fall through */ | |
7ad10968 | 4452 | default: |
955db0c0 | 4453 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
4454 | return -1; |
4455 | break; | |
4456 | } | |
4457 | break; | |
4458 | } | |
4459 | break; | |
4460 | case 0x0c: | |
0289bdd7 MS |
4461 | /* Insn fldenv. */ |
4462 | if (i386_record_floats (gdbarch, &ir, | |
4463 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4464 | return -1; | |
4465 | break; | |
7ad10968 | 4466 | case 0x0d: |
0289bdd7 MS |
4467 | /* Insn fldcw. */ |
4468 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
4469 | return -1; | |
4470 | break; | |
7ad10968 | 4471 | case 0x2c: |
0289bdd7 MS |
4472 | /* Insn frstor. */ |
4473 | if (i386_record_floats (gdbarch, &ir, | |
4474 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4475 | return -1; | |
7ad10968 HZ |
4476 | break; |
4477 | case 0x0e: | |
4478 | if (ir.dflag) | |
4479 | { | |
955db0c0 | 4480 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
4481 | return -1; |
4482 | } | |
4483 | else | |
4484 | { | |
955db0c0 | 4485 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
4486 | return -1; |
4487 | } | |
4488 | break; | |
4489 | case 0x0f: | |
4490 | case 0x2f: | |
955db0c0 | 4491 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 4492 | return -1; |
0289bdd7 MS |
4493 | /* Insn fstp, fbstp. */ |
4494 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4495 | return -1; | |
7ad10968 HZ |
4496 | break; |
4497 | case 0x1f: | |
4498 | case 0x3e: | |
955db0c0 | 4499 | if (record_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
4500 | return -1; |
4501 | break; | |
4502 | case 0x2e: | |
4503 | if (ir.dflag) | |
4504 | { | |
955db0c0 | 4505 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 | 4506 | return -1; |
955db0c0 | 4507 | addr64 += 28; |
7ad10968 HZ |
4508 | } |
4509 | else | |
4510 | { | |
955db0c0 | 4511 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 | 4512 | return -1; |
955db0c0 | 4513 | addr64 += 14; |
7ad10968 | 4514 | } |
955db0c0 | 4515 | if (record_arch_list_add_mem (addr64, 80)) |
7ad10968 | 4516 | return -1; |
0289bdd7 MS |
4517 | /* Insn fsave. */ |
4518 | if (i386_record_floats (gdbarch, &ir, | |
4519 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4520 | return -1; | |
7ad10968 HZ |
4521 | break; |
4522 | case 0x3f: | |
955db0c0 | 4523 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 4524 | return -1; |
0289bdd7 MS |
4525 | /* Insn fistp. */ |
4526 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4527 | return -1; | |
7ad10968 HZ |
4528 | break; |
4529 | default: | |
4530 | ir.addr -= 2; | |
4531 | opcode = opcode << 8 | ir.modrm; | |
4532 | goto no_support; | |
4533 | break; | |
4534 | } | |
4535 | } | |
0289bdd7 MS |
4536 | /* Opcode is an extension of modR/M byte. */ |
4537 | else | |
4538 | { | |
4539 | switch (opcode) | |
4540 | { | |
4541 | case 0xd8: | |
4542 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4543 | return -1; | |
4544 | break; | |
4545 | case 0xd9: | |
4546 | if (0x0c == (ir.modrm >> 4)) | |
4547 | { | |
4548 | if ((ir.modrm & 0x0f) <= 7) | |
4549 | { | |
4550 | if (i386_record_floats (gdbarch, &ir, | |
4551 | I386_SAVE_FPU_REGS)) | |
4552 | return -1; | |
4553 | } | |
4554 | else | |
4555 | { | |
4556 | if (i386_record_floats (gdbarch, &ir, | |
4557 | I387_ST0_REGNUM (tdep))) | |
4558 | return -1; | |
4559 | /* If only st(0) is changing, then we have already | |
4560 | recorded. */ | |
4561 | if ((ir.modrm & 0x0f) - 0x08) | |
4562 | { | |
4563 | if (i386_record_floats (gdbarch, &ir, | |
4564 | I387_ST0_REGNUM (tdep) + | |
4565 | ((ir.modrm & 0x0f) - 0x08))) | |
4566 | return -1; | |
4567 | } | |
4568 | } | |
4569 | } | |
4570 | else | |
4571 | { | |
4572 | switch (ir.modrm) | |
4573 | { | |
4574 | case 0xe0: | |
4575 | case 0xe1: | |
4576 | case 0xf0: | |
4577 | case 0xf5: | |
4578 | case 0xf8: | |
4579 | case 0xfa: | |
4580 | case 0xfc: | |
4581 | case 0xfe: | |
4582 | case 0xff: | |
4583 | if (i386_record_floats (gdbarch, &ir, | |
4584 | I387_ST0_REGNUM (tdep))) | |
4585 | return -1; | |
4586 | break; | |
4587 | case 0xf1: | |
4588 | case 0xf2: | |
4589 | case 0xf3: | |
4590 | case 0xf4: | |
4591 | case 0xf6: | |
4592 | case 0xf7: | |
4593 | case 0xe8: | |
4594 | case 0xe9: | |
4595 | case 0xea: | |
4596 | case 0xeb: | |
4597 | case 0xec: | |
4598 | case 0xed: | |
4599 | case 0xee: | |
4600 | case 0xf9: | |
4601 | case 0xfb: | |
4602 | if (i386_record_floats (gdbarch, &ir, | |
4603 | I386_SAVE_FPU_REGS)) | |
4604 | return -1; | |
4605 | break; | |
4606 | case 0xfd: | |
4607 | if (i386_record_floats (gdbarch, &ir, | |
4608 | I387_ST0_REGNUM (tdep))) | |
4609 | return -1; | |
4610 | if (i386_record_floats (gdbarch, &ir, | |
4611 | I387_ST0_REGNUM (tdep) + 1)) | |
4612 | return -1; | |
4613 | break; | |
4614 | } | |
4615 | } | |
4616 | break; | |
4617 | case 0xda: | |
4618 | if (0xe9 == ir.modrm) | |
4619 | { | |
4620 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4621 | return -1; | |
4622 | } | |
4623 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4624 | { | |
4625 | if (i386_record_floats (gdbarch, &ir, | |
4626 | I387_ST0_REGNUM (tdep))) | |
4627 | return -1; | |
4628 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4629 | { | |
4630 | if (i386_record_floats (gdbarch, &ir, | |
4631 | I387_ST0_REGNUM (tdep) + | |
4632 | (ir.modrm & 0x0f))) | |
4633 | return -1; | |
4634 | } | |
4635 | else if ((ir.modrm & 0x0f) - 0x08) | |
4636 | { | |
4637 | if (i386_record_floats (gdbarch, &ir, | |
4638 | I387_ST0_REGNUM (tdep) + | |
4639 | ((ir.modrm & 0x0f) - 0x08))) | |
4640 | return -1; | |
4641 | } | |
4642 | } | |
4643 | break; | |
4644 | case 0xdb: | |
4645 | if (0xe3 == ir.modrm) | |
4646 | { | |
4647 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
4648 | return -1; | |
4649 | } | |
4650 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4651 | { | |
4652 | if (i386_record_floats (gdbarch, &ir, | |
4653 | I387_ST0_REGNUM (tdep))) | |
4654 | return -1; | |
4655 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4656 | { | |
4657 | if (i386_record_floats (gdbarch, &ir, | |
4658 | I387_ST0_REGNUM (tdep) + | |
4659 | (ir.modrm & 0x0f))) | |
4660 | return -1; | |
4661 | } | |
4662 | else if ((ir.modrm & 0x0f) - 0x08) | |
4663 | { | |
4664 | if (i386_record_floats (gdbarch, &ir, | |
4665 | I387_ST0_REGNUM (tdep) + | |
4666 | ((ir.modrm & 0x0f) - 0x08))) | |
4667 | return -1; | |
4668 | } | |
4669 | } | |
4670 | break; | |
4671 | case 0xdc: | |
4672 | if ((0x0c == ir.modrm >> 4) | |
4673 | || (0x0d == ir.modrm >> 4) | |
4674 | || (0x0f == ir.modrm >> 4)) | |
4675 | { | |
4676 | if ((ir.modrm & 0x0f) <= 7) | |
4677 | { | |
4678 | if (i386_record_floats (gdbarch, &ir, | |
4679 | I387_ST0_REGNUM (tdep) + | |
4680 | (ir.modrm & 0x0f))) | |
4681 | return -1; | |
4682 | } | |
4683 | else | |
4684 | { | |
4685 | if (i386_record_floats (gdbarch, &ir, | |
4686 | I387_ST0_REGNUM (tdep) + | |
4687 | ((ir.modrm & 0x0f) - 0x08))) | |
4688 | return -1; | |
4689 | } | |
4690 | } | |
4691 | break; | |
4692 | case 0xdd: | |
4693 | if (0x0c == ir.modrm >> 4) | |
4694 | { | |
4695 | if (i386_record_floats (gdbarch, &ir, | |
4696 | I387_FTAG_REGNUM (tdep))) | |
4697 | return -1; | |
4698 | } | |
4699 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
4700 | { | |
4701 | if ((ir.modrm & 0x0f) <= 7) | |
4702 | { | |
4703 | if (i386_record_floats (gdbarch, &ir, | |
4704 | I387_ST0_REGNUM (tdep) + | |
4705 | (ir.modrm & 0x0f))) | |
4706 | return -1; | |
4707 | } | |
4708 | else | |
4709 | { | |
4710 | if (i386_record_floats (gdbarch, &ir, | |
4711 | I386_SAVE_FPU_REGS)) | |
4712 | return -1; | |
4713 | } | |
4714 | } | |
4715 | break; | |
4716 | case 0xde: | |
4717 | if ((0x0c == ir.modrm >> 4) | |
4718 | || (0x0e == ir.modrm >> 4) | |
4719 | || (0x0f == ir.modrm >> 4) | |
4720 | || (0xd9 == ir.modrm)) | |
4721 | { | |
4722 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4723 | return -1; | |
4724 | } | |
4725 | break; | |
4726 | case 0xdf: | |
4727 | if (0xe0 == ir.modrm) | |
4728 | { | |
4729 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4730 | return -1; | |
4731 | } | |
4732 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
4733 | { | |
4734 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4735 | return -1; | |
4736 | } | |
4737 | break; | |
4738 | } | |
4739 | } | |
7ad10968 | 4740 | break; |
7ad10968 | 4741 | /* string ops */ |
a38bba38 | 4742 | case 0xa4: /* movsS */ |
7ad10968 | 4743 | case 0xa5: |
a38bba38 | 4744 | case 0xaa: /* stosS */ |
7ad10968 | 4745 | case 0xab: |
a38bba38 | 4746 | case 0x6c: /* insS */ |
7ad10968 | 4747 | case 0x6d: |
cf648174 | 4748 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 4749 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
4750 | &addr); |
4751 | if (addr) | |
cf648174 | 4752 | { |
77d7dc92 HZ |
4753 | ULONGEST es, ds; |
4754 | ||
4755 | if ((opcode & 1) == 0) | |
4756 | ir.ot = OT_BYTE; | |
4757 | else | |
4758 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
4759 | regcache_raw_read_unsigned (ir.regcache, |
4760 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 4761 | &addr); |
77d7dc92 | 4762 | |
d7877f7e HZ |
4763 | regcache_raw_read_unsigned (ir.regcache, |
4764 | ir.regmap[X86_RECORD_ES_REGNUM], | |
4765 | &es); | |
4766 | regcache_raw_read_unsigned (ir.regcache, | |
4767 | ir.regmap[X86_RECORD_DS_REGNUM], | |
4768 | &ds); | |
4769 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
4770 | { |
4771 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
df61f520 | 4772 | warning (_("Process record ignores the memory " |
926569ae | 4773 | "change of instruction at address %s " |
df61f520 HZ |
4774 | "because it can't get the value of the " |
4775 | "ES segment register."), | |
4776 | paddress (gdbarch, ir.orig_addr)); | |
4777 | } | |
4778 | else | |
4779 | { | |
648d0c8b | 4780 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 4781 | return -1; |
77d7dc92 HZ |
4782 | } |
4783 | ||
4784 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4785 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
4786 | if (opcode == 0xa4 || opcode == 0xa5) |
4787 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
4788 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
4789 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4790 | } | |
cf648174 | 4791 | break; |
7ad10968 | 4792 | |
a38bba38 | 4793 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
4794 | case 0xa7: |
4795 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
4796 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
4797 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4798 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
4799 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4800 | break; |
4801 | ||
a38bba38 | 4802 | case 0xac: /* lodsS */ |
7ad10968 | 4803 | case 0xad: |
cf648174 HZ |
4804 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4805 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 4806 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4807 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4808 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4809 | break; |
4810 | ||
a38bba38 | 4811 | case 0xae: /* scasS */ |
7ad10968 | 4812 | case 0xaf: |
cf648174 | 4813 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 4814 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4815 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4816 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4817 | break; |
4818 | ||
a38bba38 | 4819 | case 0x6e: /* outsS */ |
cf648174 HZ |
4820 | case 0x6f: |
4821 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 4822 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4823 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4824 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4825 | break; |
4826 | ||
a38bba38 | 4827 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
4828 | case 0xe5: |
4829 | case 0xec: | |
4830 | case 0xed: | |
cf648174 HZ |
4831 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4832 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
4833 | break; |
4834 | ||
4835 | case 0xe6: | |
4836 | case 0xe7: | |
4837 | case 0xee: | |
4838 | case 0xef: | |
4839 | break; | |
4840 | ||
4841 | /* control */ | |
a38bba38 MS |
4842 | case 0xc2: /* ret im */ |
4843 | case 0xc3: /* ret */ | |
cf648174 HZ |
4844 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4845 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4846 | break; | |
4847 | ||
a38bba38 MS |
4848 | case 0xca: /* lret im */ |
4849 | case 0xcb: /* lret */ | |
4850 | case 0xcf: /* iret */ | |
cf648174 HZ |
4851 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4852 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4853 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4854 | break; |
4855 | ||
a38bba38 | 4856 | case 0xe8: /* call im */ |
cf648174 HZ |
4857 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4858 | ir.dflag = 2; | |
4859 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4860 | return -1; | |
7ad10968 HZ |
4861 | break; |
4862 | ||
a38bba38 | 4863 | case 0x9a: /* lcall im */ |
cf648174 HZ |
4864 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4865 | { | |
4866 | ir.addr -= 1; | |
4867 | goto no_support; | |
4868 | } | |
4869 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
4870 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4871 | return -1; | |
7ad10968 HZ |
4872 | break; |
4873 | ||
a38bba38 MS |
4874 | case 0xe9: /* jmp im */ |
4875 | case 0xea: /* ljmp im */ | |
4876 | case 0xeb: /* jmp Jb */ | |
4877 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
4878 | case 0x71: |
4879 | case 0x72: | |
4880 | case 0x73: | |
4881 | case 0x74: | |
4882 | case 0x75: | |
4883 | case 0x76: | |
4884 | case 0x77: | |
4885 | case 0x78: | |
4886 | case 0x79: | |
4887 | case 0x7a: | |
4888 | case 0x7b: | |
4889 | case 0x7c: | |
4890 | case 0x7d: | |
4891 | case 0x7e: | |
4892 | case 0x7f: | |
a38bba38 | 4893 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
4894 | case 0x0f81: |
4895 | case 0x0f82: | |
4896 | case 0x0f83: | |
4897 | case 0x0f84: | |
4898 | case 0x0f85: | |
4899 | case 0x0f86: | |
4900 | case 0x0f87: | |
4901 | case 0x0f88: | |
4902 | case 0x0f89: | |
4903 | case 0x0f8a: | |
4904 | case 0x0f8b: | |
4905 | case 0x0f8c: | |
4906 | case 0x0f8d: | |
4907 | case 0x0f8e: | |
4908 | case 0x0f8f: | |
4909 | break; | |
4910 | ||
a38bba38 | 4911 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
4912 | case 0x0f91: |
4913 | case 0x0f92: | |
4914 | case 0x0f93: | |
4915 | case 0x0f94: | |
4916 | case 0x0f95: | |
4917 | case 0x0f96: | |
4918 | case 0x0f97: | |
4919 | case 0x0f98: | |
4920 | case 0x0f99: | |
4921 | case 0x0f9a: | |
4922 | case 0x0f9b: | |
4923 | case 0x0f9c: | |
4924 | case 0x0f9d: | |
4925 | case 0x0f9e: | |
4926 | case 0x0f9f: | |
cf648174 | 4927 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4928 | ir.ot = OT_BYTE; |
4929 | if (i386_record_modrm (&ir)) | |
4930 | return -1; | |
4931 | if (ir.mod == 3) | |
cf648174 HZ |
4932 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
4933 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
4934 | else |
4935 | { | |
4936 | if (i386_record_lea_modrm (&ir)) | |
4937 | return -1; | |
4938 | } | |
4939 | break; | |
4940 | ||
a38bba38 | 4941 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
4942 | case 0x0f41: |
4943 | case 0x0f42: | |
4944 | case 0x0f43: | |
4945 | case 0x0f44: | |
4946 | case 0x0f45: | |
4947 | case 0x0f46: | |
4948 | case 0x0f47: | |
4949 | case 0x0f48: | |
4950 | case 0x0f49: | |
4951 | case 0x0f4a: | |
4952 | case 0x0f4b: | |
4953 | case 0x0f4c: | |
4954 | case 0x0f4d: | |
4955 | case 0x0f4e: | |
4956 | case 0x0f4f: | |
4957 | if (i386_record_modrm (&ir)) | |
4958 | return -1; | |
cf648174 | 4959 | ir.reg |= rex_r; |
7ad10968 HZ |
4960 | if (ir.dflag == OT_BYTE) |
4961 | ir.reg &= 0x3; | |
cf648174 | 4962 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4963 | break; |
4964 | ||
4965 | /* flags */ | |
a38bba38 | 4966 | case 0x9c: /* pushf */ |
cf648174 HZ |
4967 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4968 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4969 | ir.dflag = 2; | |
4970 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4971 | return -1; | |
7ad10968 HZ |
4972 | break; |
4973 | ||
a38bba38 | 4974 | case 0x9d: /* popf */ |
cf648174 HZ |
4975 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4976 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4977 | break; |
4978 | ||
a38bba38 | 4979 | case 0x9e: /* sahf */ |
cf648174 HZ |
4980 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4981 | { | |
4982 | ir.addr -= 1; | |
4983 | goto no_support; | |
4984 | } | |
a38bba38 MS |
4985 | case 0xf5: /* cmc */ |
4986 | case 0xf8: /* clc */ | |
4987 | case 0xf9: /* stc */ | |
4988 | case 0xfc: /* cld */ | |
4989 | case 0xfd: /* std */ | |
cf648174 | 4990 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4991 | break; |
4992 | ||
a38bba38 | 4993 | case 0x9f: /* lahf */ |
cf648174 HZ |
4994 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4995 | { | |
4996 | ir.addr -= 1; | |
4997 | goto no_support; | |
4998 | } | |
4999 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5000 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5001 | break; |
5002 | ||
5003 | /* bit operations */ | |
a38bba38 | 5004 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
5005 | ir.ot = ir.dflag + OT_WORD; |
5006 | if (i386_record_modrm (&ir)) | |
5007 | return -1; | |
5008 | if (ir.reg < 4) | |
5009 | { | |
cf648174 | 5010 | ir.addr -= 2; |
7ad10968 HZ |
5011 | opcode = opcode << 8 | ir.modrm; |
5012 | goto no_support; | |
5013 | } | |
cf648174 | 5014 | if (ir.reg != 4) |
7ad10968 | 5015 | { |
cf648174 HZ |
5016 | if (ir.mod == 3) |
5017 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
5018 | else |
5019 | { | |
cf648174 | 5020 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
5021 | return -1; |
5022 | } | |
5023 | } | |
cf648174 | 5024 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5025 | break; |
5026 | ||
a38bba38 | 5027 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
5028 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5029 | break; | |
5030 | ||
a38bba38 MS |
5031 | case 0x0fab: /* bts */ |
5032 | case 0x0fb3: /* btr */ | |
5033 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
5034 | ir.ot = ir.dflag + OT_WORD; |
5035 | if (i386_record_modrm (&ir)) | |
5036 | return -1; | |
5037 | if (ir.mod == 3) | |
5038 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
5039 | else | |
5040 | { | |
955db0c0 MS |
5041 | uint64_t addr64; |
5042 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
5043 | return -1; |
5044 | regcache_raw_read_unsigned (ir.regcache, | |
5045 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 5046 | &addr); |
cf648174 HZ |
5047 | switch (ir.dflag) |
5048 | { | |
5049 | case 0: | |
648d0c8b | 5050 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
5051 | break; |
5052 | case 1: | |
648d0c8b | 5053 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
5054 | break; |
5055 | case 2: | |
648d0c8b | 5056 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
5057 | break; |
5058 | } | |
955db0c0 | 5059 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
5060 | return -1; |
5061 | if (i386_record_lea_modrm (&ir)) | |
5062 | return -1; | |
5063 | } | |
5064 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5065 | break; |
5066 | ||
a38bba38 MS |
5067 | case 0x0fbc: /* bsf */ |
5068 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
5069 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5070 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5071 | break; |
5072 | ||
5073 | /* bcd */ | |
a38bba38 MS |
5074 | case 0x27: /* daa */ |
5075 | case 0x2f: /* das */ | |
5076 | case 0x37: /* aaa */ | |
5077 | case 0x3f: /* aas */ | |
5078 | case 0xd4: /* aam */ | |
5079 | case 0xd5: /* aad */ | |
cf648174 HZ |
5080 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5081 | { | |
5082 | ir.addr -= 1; | |
5083 | goto no_support; | |
5084 | } | |
5085 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5086 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5087 | break; |
5088 | ||
5089 | /* misc */ | |
a38bba38 | 5090 | case 0x90: /* nop */ |
7ad10968 HZ |
5091 | if (prefixes & PREFIX_LOCK) |
5092 | { | |
5093 | ir.addr -= 1; | |
5094 | goto no_support; | |
5095 | } | |
5096 | break; | |
5097 | ||
a38bba38 | 5098 | case 0x9b: /* fwait */ |
425b824a | 5099 | if (target_read_memory (ir.addr, &opcode8, 1)) |
0289bdd7 MS |
5100 | { |
5101 | if (record_debug) | |
5102 | printf_unfiltered (_("Process record: error reading memory at " | |
5103 | "addr 0x%s len = 1.\n"), | |
5104 | paddress (gdbarch, ir.addr)); | |
5105 | return -1; | |
5106 | } | |
425b824a | 5107 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
5108 | ir.addr++; |
5109 | goto reswitch; | |
7ad10968 HZ |
5110 | break; |
5111 | ||
7ad10968 | 5112 | /* XXX */ |
a38bba38 | 5113 | case 0xcc: /* int3 */ |
7ad10968 HZ |
5114 | printf_unfiltered (_("Process record doesn't support instruction " |
5115 | "int3.\n")); | |
5116 | ir.addr -= 1; | |
5117 | goto no_support; | |
5118 | break; | |
5119 | ||
7ad10968 | 5120 | /* XXX */ |
a38bba38 | 5121 | case 0xcd: /* int */ |
7ad10968 HZ |
5122 | { |
5123 | int ret; | |
425b824a MS |
5124 | uint8_t interrupt; |
5125 | if (target_read_memory (ir.addr, &interrupt, 1)) | |
7ad10968 HZ |
5126 | { |
5127 | if (record_debug) | |
5128 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
5129 | "at addr %s len = 1.\n"), |
5130 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5131 | return -1; |
5132 | } | |
5133 | ir.addr++; | |
425b824a | 5134 | if (interrupt != 0x80 |
7ad10968 HZ |
5135 | || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL) |
5136 | { | |
5137 | printf_unfiltered (_("Process record doesn't support " | |
5138 | "instruction int 0x%02x.\n"), | |
425b824a | 5139 | interrupt); |
7ad10968 HZ |
5140 | ir.addr -= 2; |
5141 | goto no_support; | |
5142 | } | |
5143 | ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache); | |
5144 | if (ret) | |
5145 | return ret; | |
5146 | } | |
5147 | break; | |
5148 | ||
7ad10968 | 5149 | /* XXX */ |
a38bba38 | 5150 | case 0xce: /* into */ |
7ad10968 HZ |
5151 | printf_unfiltered (_("Process record doesn't support " |
5152 | "instruction into.\n")); | |
5153 | ir.addr -= 1; | |
5154 | goto no_support; | |
5155 | break; | |
5156 | ||
a38bba38 MS |
5157 | case 0xfa: /* cli */ |
5158 | case 0xfb: /* sti */ | |
7ad10968 HZ |
5159 | break; |
5160 | ||
a38bba38 | 5161 | case 0x62: /* bound */ |
7ad10968 HZ |
5162 | printf_unfiltered (_("Process record doesn't support " |
5163 | "instruction bound.\n")); | |
5164 | ir.addr -= 1; | |
5165 | goto no_support; | |
5166 | break; | |
5167 | ||
a38bba38 | 5168 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
5169 | case 0x0fc9: |
5170 | case 0x0fca: | |
5171 | case 0x0fcb: | |
5172 | case 0x0fcc: | |
5173 | case 0x0fcd: | |
5174 | case 0x0fce: | |
5175 | case 0x0fcf: | |
cf648174 | 5176 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
5177 | break; |
5178 | ||
a38bba38 | 5179 | case 0xd6: /* salc */ |
cf648174 HZ |
5180 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5181 | { | |
5182 | ir.addr -= 1; | |
5183 | goto no_support; | |
5184 | } | |
5185 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5186 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5187 | break; |
5188 | ||
a38bba38 MS |
5189 | case 0xe0: /* loopnz */ |
5190 | case 0xe1: /* loopz */ | |
5191 | case 0xe2: /* loop */ | |
5192 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
5193 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5194 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5195 | break; |
5196 | ||
a38bba38 | 5197 | case 0x0f30: /* wrmsr */ |
7ad10968 HZ |
5198 | printf_unfiltered (_("Process record doesn't support " |
5199 | "instruction wrmsr.\n")); | |
5200 | ir.addr -= 2; | |
5201 | goto no_support; | |
5202 | break; | |
5203 | ||
a38bba38 | 5204 | case 0x0f32: /* rdmsr */ |
7ad10968 HZ |
5205 | printf_unfiltered (_("Process record doesn't support " |
5206 | "instruction rdmsr.\n")); | |
5207 | ir.addr -= 2; | |
5208 | goto no_support; | |
5209 | break; | |
5210 | ||
a38bba38 | 5211 | case 0x0f31: /* rdtsc */ |
7ad10968 HZ |
5212 | printf_unfiltered (_("Process record doesn't support " |
5213 | "instruction rdtsc.\n")); | |
5214 | ir.addr -= 2; | |
5215 | goto no_support; | |
5216 | break; | |
5217 | ||
a38bba38 | 5218 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
5219 | { |
5220 | int ret; | |
cf648174 HZ |
5221 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5222 | { | |
5223 | ir.addr -= 2; | |
5224 | goto no_support; | |
5225 | } | |
7ad10968 HZ |
5226 | if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL) |
5227 | { | |
5228 | printf_unfiltered (_("Process record doesn't support " | |
5229 | "instruction sysenter.\n")); | |
5230 | ir.addr -= 2; | |
5231 | goto no_support; | |
5232 | } | |
5233 | ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache); | |
5234 | if (ret) | |
5235 | return ret; | |
5236 | } | |
5237 | break; | |
5238 | ||
a38bba38 | 5239 | case 0x0f35: /* sysexit */ |
7ad10968 HZ |
5240 | printf_unfiltered (_("Process record doesn't support " |
5241 | "instruction sysexit.\n")); | |
5242 | ir.addr -= 2; | |
5243 | goto no_support; | |
5244 | break; | |
5245 | ||
a38bba38 | 5246 | case 0x0f05: /* syscall */ |
cf648174 HZ |
5247 | { |
5248 | int ret; | |
5249 | if (gdbarch_tdep (gdbarch)->i386_syscall_record == NULL) | |
5250 | { | |
5251 | printf_unfiltered (_("Process record doesn't support " | |
5252 | "instruction syscall.\n")); | |
5253 | ir.addr -= 2; | |
5254 | goto no_support; | |
5255 | } | |
5256 | ret = gdbarch_tdep (gdbarch)->i386_syscall_record (ir.regcache); | |
5257 | if (ret) | |
5258 | return ret; | |
5259 | } | |
5260 | break; | |
5261 | ||
a38bba38 | 5262 | case 0x0f07: /* sysret */ |
cf648174 HZ |
5263 | printf_unfiltered (_("Process record doesn't support " |
5264 | "instruction sysret.\n")); | |
5265 | ir.addr -= 2; | |
5266 | goto no_support; | |
5267 | break; | |
5268 | ||
a38bba38 | 5269 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
5270 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5271 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5272 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5273 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
5274 | break; |
5275 | ||
a38bba38 | 5276 | case 0xf4: /* hlt */ |
7ad10968 HZ |
5277 | printf_unfiltered (_("Process record doesn't support " |
5278 | "instruction hlt.\n")); | |
5279 | ir.addr -= 1; | |
5280 | goto no_support; | |
5281 | break; | |
5282 | ||
5283 | case 0x0f00: | |
5284 | if (i386_record_modrm (&ir)) | |
5285 | return -1; | |
5286 | switch (ir.reg) | |
5287 | { | |
a38bba38 MS |
5288 | case 0: /* sldt */ |
5289 | case 1: /* str */ | |
7ad10968 | 5290 | if (ir.mod == 3) |
cf648174 | 5291 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5292 | else |
5293 | { | |
5294 | ir.ot = OT_WORD; | |
5295 | if (i386_record_lea_modrm (&ir)) | |
5296 | return -1; | |
5297 | } | |
5298 | break; | |
a38bba38 MS |
5299 | case 2: /* lldt */ |
5300 | case 3: /* ltr */ | |
7ad10968 | 5301 | break; |
a38bba38 MS |
5302 | case 4: /* verr */ |
5303 | case 5: /* verw */ | |
cf648174 | 5304 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5305 | break; |
5306 | default: | |
5307 | ir.addr -= 3; | |
5308 | opcode = opcode << 8 | ir.modrm; | |
5309 | goto no_support; | |
5310 | break; | |
5311 | } | |
5312 | break; | |
5313 | ||
5314 | case 0x0f01: | |
5315 | if (i386_record_modrm (&ir)) | |
5316 | return -1; | |
5317 | switch (ir.reg) | |
5318 | { | |
a38bba38 | 5319 | case 0: /* sgdt */ |
7ad10968 | 5320 | { |
955db0c0 | 5321 | uint64_t addr64; |
7ad10968 HZ |
5322 | |
5323 | if (ir.mod == 3) | |
5324 | { | |
5325 | ir.addr -= 3; | |
5326 | opcode = opcode << 8 | ir.modrm; | |
5327 | goto no_support; | |
5328 | } | |
d7877f7e | 5329 | if (ir.override >= 0) |
7ad10968 | 5330 | { |
df61f520 HZ |
5331 | warning (_("Process record ignores the memory " |
5332 | "change of instruction at " | |
5333 | "address %s because it can't get " | |
5334 | "the value of the segment " | |
5335 | "register."), | |
5336 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5337 | } |
5338 | else | |
5339 | { | |
955db0c0 | 5340 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 5341 | return -1; |
955db0c0 | 5342 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5343 | return -1; |
955db0c0 | 5344 | addr64 += 2; |
cf648174 HZ |
5345 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5346 | { | |
955db0c0 | 5347 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
5348 | return -1; |
5349 | } | |
5350 | else | |
5351 | { | |
955db0c0 | 5352 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
5353 | return -1; |
5354 | } | |
7ad10968 HZ |
5355 | } |
5356 | } | |
5357 | break; | |
5358 | case 1: | |
5359 | if (ir.mod == 3) | |
5360 | { | |
5361 | switch (ir.rm) | |
5362 | { | |
a38bba38 | 5363 | case 0: /* monitor */ |
7ad10968 | 5364 | break; |
a38bba38 | 5365 | case 1: /* mwait */ |
cf648174 | 5366 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5367 | break; |
5368 | default: | |
5369 | ir.addr -= 3; | |
5370 | opcode = opcode << 8 | ir.modrm; | |
5371 | goto no_support; | |
5372 | break; | |
5373 | } | |
5374 | } | |
5375 | else | |
5376 | { | |
5377 | /* sidt */ | |
d7877f7e | 5378 | if (ir.override >= 0) |
7ad10968 | 5379 | { |
df61f520 HZ |
5380 | warning (_("Process record ignores the memory " |
5381 | "change of instruction at " | |
5382 | "address %s because it can't get " | |
5383 | "the value of the segment " | |
5384 | "register."), | |
5385 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5386 | } |
5387 | else | |
5388 | { | |
955db0c0 | 5389 | uint64_t addr64; |
7ad10968 | 5390 | |
955db0c0 | 5391 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 5392 | return -1; |
955db0c0 | 5393 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5394 | return -1; |
955db0c0 | 5395 | addr64 += 2; |
cf648174 HZ |
5396 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5397 | { | |
955db0c0 | 5398 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
5399 | return -1; |
5400 | } | |
5401 | else | |
5402 | { | |
955db0c0 | 5403 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
5404 | return -1; |
5405 | } | |
7ad10968 HZ |
5406 | } |
5407 | } | |
5408 | break; | |
a38bba38 | 5409 | case 2: /* lgdt */ |
3800e645 MS |
5410 | if (ir.mod == 3) |
5411 | { | |
5412 | /* xgetbv */ | |
5413 | if (ir.rm == 0) | |
5414 | { | |
5415 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5416 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5417 | break; | |
5418 | } | |
5419 | /* xsetbv */ | |
5420 | else if (ir.rm == 1) | |
5421 | break; | |
5422 | } | |
a38bba38 | 5423 | case 3: /* lidt */ |
7ad10968 HZ |
5424 | if (ir.mod == 3) |
5425 | { | |
5426 | ir.addr -= 3; | |
5427 | opcode = opcode << 8 | ir.modrm; | |
5428 | goto no_support; | |
5429 | } | |
5430 | break; | |
a38bba38 | 5431 | case 4: /* smsw */ |
7ad10968 HZ |
5432 | if (ir.mod == 3) |
5433 | { | |
cf648174 | 5434 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
5435 | return -1; |
5436 | } | |
5437 | else | |
5438 | { | |
5439 | ir.ot = OT_WORD; | |
5440 | if (i386_record_lea_modrm (&ir)) | |
5441 | return -1; | |
5442 | } | |
cf648174 | 5443 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5444 | break; |
a38bba38 | 5445 | case 6: /* lmsw */ |
cf648174 HZ |
5446 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5447 | break; | |
a38bba38 | 5448 | case 7: /* invlpg */ |
cf648174 HZ |
5449 | if (ir.mod == 3) |
5450 | { | |
5451 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
5452 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5453 | else | |
5454 | { | |
5455 | ir.addr -= 3; | |
5456 | opcode = opcode << 8 | ir.modrm; | |
5457 | goto no_support; | |
5458 | } | |
5459 | } | |
5460 | else | |
5461 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5462 | break; | |
5463 | default: | |
5464 | ir.addr -= 3; | |
5465 | opcode = opcode << 8 | ir.modrm; | |
5466 | goto no_support; | |
7ad10968 HZ |
5467 | break; |
5468 | } | |
5469 | break; | |
5470 | ||
a38bba38 MS |
5471 | case 0x0f08: /* invd */ |
5472 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
5473 | break; |
5474 | ||
a38bba38 | 5475 | case 0x63: /* arpl */ |
7ad10968 HZ |
5476 | if (i386_record_modrm (&ir)) |
5477 | return -1; | |
cf648174 HZ |
5478 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
5479 | { | |
5480 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
5481 | ? (ir.reg | rex_r) : ir.rm); | |
5482 | } | |
7ad10968 | 5483 | else |
cf648174 HZ |
5484 | { |
5485 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
5486 | if (i386_record_lea_modrm (&ir)) | |
5487 | return -1; | |
5488 | } | |
5489 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
5490 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5491 | break; |
5492 | ||
a38bba38 MS |
5493 | case 0x0f02: /* lar */ |
5494 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
5495 | if (i386_record_modrm (&ir)) |
5496 | return -1; | |
cf648174 HZ |
5497 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5498 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5499 | break; |
5500 | ||
5501 | case 0x0f18: | |
cf648174 HZ |
5502 | if (i386_record_modrm (&ir)) |
5503 | return -1; | |
5504 | if (ir.mod == 3 && ir.reg == 3) | |
5505 | { | |
5506 | ir.addr -= 3; | |
5507 | opcode = opcode << 8 | ir.modrm; | |
5508 | goto no_support; | |
5509 | } | |
7ad10968 HZ |
5510 | break; |
5511 | ||
7ad10968 HZ |
5512 | case 0x0f19: |
5513 | case 0x0f1a: | |
5514 | case 0x0f1b: | |
5515 | case 0x0f1c: | |
5516 | case 0x0f1d: | |
5517 | case 0x0f1e: | |
5518 | case 0x0f1f: | |
a38bba38 | 5519 | /* nop (multi byte) */ |
7ad10968 HZ |
5520 | break; |
5521 | ||
a38bba38 MS |
5522 | case 0x0f20: /* mov reg, crN */ |
5523 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
5524 | if (i386_record_modrm (&ir)) |
5525 | return -1; | |
5526 | if ((ir.modrm & 0xc0) != 0xc0) | |
5527 | { | |
cf648174 | 5528 | ir.addr -= 3; |
7ad10968 HZ |
5529 | opcode = opcode << 8 | ir.modrm; |
5530 | goto no_support; | |
5531 | } | |
5532 | switch (ir.reg) | |
5533 | { | |
5534 | case 0: | |
5535 | case 2: | |
5536 | case 3: | |
5537 | case 4: | |
5538 | case 8: | |
5539 | if (opcode & 2) | |
cf648174 | 5540 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5541 | else |
cf648174 | 5542 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5543 | break; |
5544 | default: | |
cf648174 | 5545 | ir.addr -= 3; |
7ad10968 HZ |
5546 | opcode = opcode << 8 | ir.modrm; |
5547 | goto no_support; | |
5548 | break; | |
5549 | } | |
5550 | break; | |
5551 | ||
a38bba38 MS |
5552 | case 0x0f21: /* mov reg, drN */ |
5553 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
5554 | if (i386_record_modrm (&ir)) |
5555 | return -1; | |
5556 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
5557 | || ir.reg == 5 || ir.reg >= 8) | |
5558 | { | |
cf648174 | 5559 | ir.addr -= 3; |
7ad10968 HZ |
5560 | opcode = opcode << 8 | ir.modrm; |
5561 | goto no_support; | |
5562 | } | |
5563 | if (opcode & 2) | |
cf648174 | 5564 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5565 | else |
cf648174 | 5566 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5567 | break; |
5568 | ||
a38bba38 | 5569 | case 0x0f06: /* clts */ |
cf648174 | 5570 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5571 | break; |
5572 | ||
5573 | /* MMX/SSE/SSE2/PNI support */ | |
5574 | /* XXX */ | |
5575 | ||
5576 | default: | |
5577 | if (opcode > 0xff) | |
5578 | ir.addr -= 2; | |
5579 | else | |
5580 | ir.addr -= 1; | |
5581 | goto no_support; | |
5582 | break; | |
5583 | } | |
5584 | ||
cf648174 HZ |
5585 | /* In the future, maybe still need to deal with need_dasm. */ |
5586 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
5587 | if (record_arch_list_add_end ()) |
5588 | return -1; | |
5589 | ||
5590 | return 0; | |
5591 | ||
01fe1b41 | 5592 | no_support: |
7ad10968 | 5593 | printf_unfiltered (_("Process record doesn't support instruction 0x%02x " |
5af949e3 UW |
5594 | "at address %s.\n"), |
5595 | (unsigned int) (opcode), paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5596 | return -1; |
5597 | } | |
5598 | ||
cf648174 HZ |
5599 | static const int i386_record_regmap[] = |
5600 | { | |
5601 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
5602 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
5603 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5604 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
5605 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
5606 | }; | |
5607 | ||
7a697b8d SS |
5608 | /* Check that the given address appears suitable for a fast |
5609 | tracepoint, which on x86 means that we need an instruction of at | |
5610 | least 5 bytes, so that we can overwrite it with a 4-byte-offset | |
5611 | jump and not have to worry about program jumps to an address in the | |
5612 | middle of the tracepoint jump. Returns 1 if OK, and writes a size | |
5613 | of instruction to replace, and 0 if not, plus an explanatory | |
5614 | string. */ | |
5615 | ||
5616 | static int | |
5617 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
5618 | CORE_ADDR addr, int *isize, char **msg) | |
5619 | { | |
5620 | int len, jumplen; | |
5621 | static struct ui_file *gdb_null = NULL; | |
5622 | ||
5623 | /* This is based on the target agent using a 4-byte relative jump. | |
5624 | Alternate future possibilities include 8-byte offset for x86-84, | |
5625 | or 3-byte jumps if the program has trampoline space close by. */ | |
5626 | jumplen = 5; | |
5627 | ||
5628 | /* Dummy file descriptor for the disassembler. */ | |
5629 | if (!gdb_null) | |
5630 | gdb_null = ui_file_new (); | |
5631 | ||
5632 | /* Check for fit. */ | |
5633 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
5634 | if (len < jumplen) | |
5635 | { | |
5636 | /* Return a bit of target-specific detail to add to the caller's | |
5637 | generic failure message. */ | |
5638 | if (msg) | |
5639 | *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"), | |
5640 | len, jumplen); | |
5641 | return 0; | |
5642 | } | |
5643 | ||
5644 | if (isize) | |
5645 | *isize = len; | |
5646 | if (msg) | |
5647 | *msg = NULL; | |
5648 | return 1; | |
5649 | } | |
5650 | ||
90884b2b L |
5651 | static int |
5652 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
5653 | struct tdesc_arch_data *tdesc_data) | |
5654 | { | |
5655 | const struct target_desc *tdesc = tdep->tdesc; | |
5656 | const struct tdesc_feature *feature_core, *feature_vector; | |
5657 | int i, num_regs, valid_p; | |
5658 | ||
5659 | if (! tdesc_has_registers (tdesc)) | |
5660 | return 0; | |
5661 | ||
5662 | /* Get core registers. */ | |
5663 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
5664 | ||
5665 | /* Get SSE registers. */ | |
5666 | feature_vector = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); | |
5667 | ||
5668 | if (feature_core == NULL || feature_vector == NULL) | |
5669 | return 0; | |
5670 | ||
5671 | valid_p = 1; | |
5672 | ||
5673 | num_regs = tdep->num_core_regs; | |
5674 | for (i = 0; i < num_regs; i++) | |
5675 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
5676 | tdep->register_names[i]); | |
5677 | ||
5678 | /* Need to include %mxcsr, so add one. */ | |
5679 | num_regs += tdep->num_xmm_regs + 1; | |
5680 | for (; i < num_regs; i++) | |
5681 | valid_p &= tdesc_numbered_register (feature_vector, tdesc_data, i, | |
5682 | tdep->register_names[i]); | |
5683 | ||
5684 | return valid_p; | |
5685 | } | |
5686 | ||
7ad10968 HZ |
5687 | \f |
5688 | static struct gdbarch * | |
5689 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
5690 | { | |
5691 | struct gdbarch_tdep *tdep; | |
5692 | struct gdbarch *gdbarch; | |
90884b2b L |
5693 | struct tdesc_arch_data *tdesc_data; |
5694 | const struct target_desc *tdesc; | |
1ba53b71 | 5695 | int mm0_regnum; |
7ad10968 HZ |
5696 | |
5697 | /* If there is already a candidate, use it. */ | |
5698 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
5699 | if (arches != NULL) | |
5700 | return arches->gdbarch; | |
5701 | ||
5702 | /* Allocate space for the new architecture. */ | |
5703 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
5704 | gdbarch = gdbarch_alloc (&info, tdep); | |
5705 | ||
5706 | /* General-purpose registers. */ | |
5707 | tdep->gregset = NULL; | |
5708 | tdep->gregset_reg_offset = NULL; | |
5709 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
5710 | tdep->sizeof_gregset = 0; | |
5711 | ||
5712 | /* Floating-point registers. */ | |
5713 | tdep->fpregset = NULL; | |
5714 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
5715 | ||
5716 | /* The default settings include the FPU registers, the MMX registers | |
5717 | and the SSE registers. This can be overridden for a specific ABI | |
5718 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
5719 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
5720 | will show up in the output of "info all-registers". Ideally we | |
5721 | should try to autodetect whether they are available, such that we | |
5722 | can prevent "info all-registers" from displaying registers that | |
5723 | aren't available. | |
5724 | ||
5725 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing | |
5726 | [the SSE registers] always (even when they don't exist) or never | |
5727 | showing them to the user (even when they do exist), I prefer the | |
5728 | former over the latter. */ | |
5729 | ||
5730 | tdep->st0_regnum = I386_ST0_REGNUM; | |
5731 | ||
7ad10968 HZ |
5732 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
5733 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
5734 | ||
5735 | tdep->jb_pc_offset = -1; | |
5736 | tdep->struct_return = pcc_struct_return; | |
5737 | tdep->sigtramp_start = 0; | |
5738 | tdep->sigtramp_end = 0; | |
5739 | tdep->sigtramp_p = i386_sigtramp_p; | |
5740 | tdep->sigcontext_addr = NULL; | |
5741 | tdep->sc_reg_offset = NULL; | |
5742 | tdep->sc_pc_offset = -1; | |
5743 | tdep->sc_sp_offset = -1; | |
5744 | ||
cf648174 HZ |
5745 | tdep->record_regmap = i386_record_regmap; |
5746 | ||
7ad10968 HZ |
5747 | /* The format used for `long double' on almost all i386 targets is |
5748 | the i387 extended floating-point format. In fact, of all targets | |
5749 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
5750 | on having a `long double' that's not `long' at all. */ | |
5751 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
5752 | ||
5753 | /* Although the i387 extended floating-point has only 80 significant | |
5754 | bits, a `long double' actually takes up 96, probably to enforce | |
5755 | alignment. */ | |
5756 | set_gdbarch_long_double_bit (gdbarch, 96); | |
5757 | ||
7ad10968 HZ |
5758 | /* Register numbers of various important registers. */ |
5759 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
5760 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
5761 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
5762 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
5763 | ||
5764 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
5765 | numbering schemes on the i386: dbx and SVR4. These schemes | |
5766 | differ in how they number %ebp, %esp, %eflags, and the | |
5767 | floating-point registers, and are implemented by the arrays | |
5768 | dbx_register_map[] and svr4_dbx_register_map in | |
5769 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
5770 | gcc/config/i386.c, which it designates as the "default" register | |
5771 | map used in 64bit mode. This last register numbering scheme is | |
5772 | implemented in dbx64_register_map, and is used for AMD64; see | |
5773 | amd64-tdep.c. | |
5774 | ||
5775 | Currently, each GCC i386 target always uses the same register | |
5776 | numbering scheme across all its supported debugging formats | |
5777 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
5778 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
5779 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
5780 | respective config header in a manner independent of the requested | |
5781 | output debugging format. | |
5782 | ||
5783 | This does not match the arrangement below, which presumes that | |
5784 | the SDB and stabs numbering schemes differ from the DWARF and | |
5785 | DWARF 2 ones. The reason for this arrangement is that it is | |
5786 | likely to get the numbering scheme for the target's | |
5787 | default/native debug format right. For targets where GCC is the | |
5788 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
5789 | targets where the native toolchain uses a different numbering | |
5790 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
5791 | the defaults below will have to be overridden, like | |
5792 | i386_elf_init_abi() does. */ | |
5793 | ||
5794 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
5795 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5796 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5797 | ||
5798 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
5799 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
5800 | ||
5801 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
5802 | be in use on any of the supported i386 targets. */ | |
5803 | ||
5804 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
5805 | ||
5806 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
5807 | ||
5808 | /* Call dummy code. */ | |
5809 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
5810 | ||
5811 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
5812 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
5813 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
5814 | ||
5815 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
5816 | ||
5817 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
5818 | ||
5819 | /* Stack grows downward. */ | |
5820 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
5821 | ||
5822 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
5823 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
5824 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
5825 | ||
5826 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
5827 | ||
7ad10968 HZ |
5828 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
5829 | ||
5830 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
5831 | ||
5832 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
5833 | ||
5834 | /* Add the i386 register groups. */ | |
5835 | i386_add_reggroups (gdbarch); | |
90884b2b | 5836 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 5837 | |
143985b7 AF |
5838 | /* Helper for function argument information. */ |
5839 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
5840 | ||
06da04c6 MS |
5841 | /* Hook the function epilogue frame unwinder. This unwinder is |
5842 | appended to the list first, so that it supercedes the Dwarf | |
5843 | unwinder in function epilogues (where the Dwarf unwinder | |
5844 | currently fails). */ | |
5845 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
5846 | ||
5847 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
5848 | to the list before the prologue-based unwinders, so that Dwarf | |
5849 | CFI info will be used if it is available. */ | |
10458914 | 5850 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 5851 | |
acd5c798 | 5852 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 5853 | |
1ba53b71 | 5854 | /* Pseudo registers may be changed by amd64_init_abi. */ |
90884b2b L |
5855 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); |
5856 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
5857 | ||
5858 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
5859 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
5860 | ||
5861 | /* The default ABI includes general-purpose registers, | |
5862 | floating-point registers, and the SSE registers. */ | |
5863 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); | |
5864 | ||
5865 | /* Get the x86 target description from INFO. */ | |
5866 | tdesc = info.target_desc; | |
5867 | if (! tdesc_has_registers (tdesc)) | |
5868 | tdesc = tdesc_i386; | |
5869 | tdep->tdesc = tdesc; | |
5870 | ||
5871 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
5872 | tdep->register_names = i386_register_names; | |
5873 | ||
1ba53b71 L |
5874 | tdep->num_byte_regs = 8; |
5875 | tdep->num_word_regs = 8; | |
5876 | tdep->num_dword_regs = 0; | |
5877 | tdep->num_mmx_regs = 8; | |
5878 | ||
90884b2b L |
5879 | tdesc_data = tdesc_data_alloc (); |
5880 | ||
3ce1502b | 5881 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 5882 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 5883 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 5884 | |
1ba53b71 L |
5885 | /* Wire in pseudo registers. Number of pseudo registers may be |
5886 | changed. */ | |
5887 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
5888 | + tdep->num_word_regs | |
5889 | + tdep->num_dword_regs | |
5890 | + tdep->num_mmx_regs)); | |
5891 | ||
90884b2b L |
5892 | /* Target description may be changed. */ |
5893 | tdesc = tdep->tdesc; | |
5894 | ||
5895 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) | |
5896 | { | |
5897 | tdesc_data_cleanup (tdesc_data); | |
5898 | xfree (tdep); | |
5899 | gdbarch_free (gdbarch); | |
5900 | return NULL; | |
5901 | } | |
5902 | ||
5903 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
5904 | ||
5905 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
5906 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
5907 | ||
1ba53b71 L |
5908 | /* Make %al the first pseudo-register. */ |
5909 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
5910 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
5911 | ||
5912 | mm0_regnum = tdep->ax_regnum + tdep->num_word_regs; | |
5913 | if (tdep->num_dword_regs) | |
5914 | { | |
5915 | /* Support dword pseudo-registesr if it hasn't been disabled, */ | |
5916 | tdep->eax_regnum = mm0_regnum; | |
5917 | mm0_regnum = tdep->eax_regnum + tdep->num_dword_regs; | |
5918 | } | |
5919 | else | |
5920 | tdep->eax_regnum = -1; | |
5921 | ||
5922 | if (tdep->num_mmx_regs != 0) | |
5923 | { | |
5924 | /* Support MMX pseudo-registesr if MMX hasn't been disabled, */ | |
5925 | tdep->mm0_regnum = mm0_regnum; | |
5926 | } | |
5927 | else | |
5928 | tdep->mm0_regnum = -1; | |
5929 | ||
06da04c6 | 5930 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
10458914 DJ |
5931 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
5932 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 5933 | |
8446b36a MK |
5934 | /* If we have a register mapping, enable the generic core file |
5935 | support, unless it has already been enabled. */ | |
5936 | if (tdep->gregset_reg_offset | |
5937 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
5938 | set_gdbarch_regset_from_core_section (gdbarch, | |
5939 | i386_regset_from_core_section); | |
5940 | ||
514f746b AR |
5941 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
5942 | i386_skip_permanent_breakpoint); | |
5943 | ||
7a697b8d SS |
5944 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
5945 | i386_fast_tracepoint_valid_at); | |
5946 | ||
a62cc96e AC |
5947 | return gdbarch; |
5948 | } | |
5949 | ||
8201327c MK |
5950 | static enum gdb_osabi |
5951 | i386_coff_osabi_sniffer (bfd *abfd) | |
5952 | { | |
762c5349 MK |
5953 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
5954 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
5955 | return GDB_OSABI_GO32; |
5956 | ||
5957 | return GDB_OSABI_UNKNOWN; | |
5958 | } | |
8201327c MK |
5959 | \f |
5960 | ||
28e9e0f0 MK |
5961 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
5962 | void _initialize_i386_tdep (void); | |
5963 | ||
c906108c | 5964 | void |
fba45db2 | 5965 | _initialize_i386_tdep (void) |
c906108c | 5966 | { |
a62cc96e AC |
5967 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
5968 | ||
fc338970 | 5969 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
5970 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
5971 | &disassembly_flavor, _("\ | |
5972 | Set the disassembly flavor."), _("\ | |
5973 | Show the disassembly flavor."), _("\ | |
5974 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
5975 | NULL, | |
5976 | NULL, /* FIXME: i18n: */ | |
5977 | &setlist, &showlist); | |
8201327c MK |
5978 | |
5979 | /* Add the variable that controls the convention for returning | |
5980 | structs. */ | |
7ab04401 AC |
5981 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
5982 | &struct_convention, _("\ | |
5983 | Set the convention for returning small structs."), _("\ | |
5984 | Show the convention for returning small structs."), _("\ | |
5985 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
5986 | is \"default\"."), | |
5987 | NULL, | |
5988 | NULL, /* FIXME: i18n: */ | |
5989 | &setlist, &showlist); | |
8201327c MK |
5990 | |
5991 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
5992 | i386_coff_osabi_sniffer); | |
8201327c | 5993 | |
05816f70 | 5994 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 5995 | i386_svr4_init_abi); |
05816f70 | 5996 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 5997 | i386_go32_init_abi); |
38c968cf | 5998 | |
209bd28e | 5999 | /* Initialize the i386-specific register groups. */ |
38c968cf | 6000 | i386_init_reggroups (); |
90884b2b L |
6001 | |
6002 | /* Initialize the standard target descriptions. */ | |
6003 | initialize_tdesc_i386 (); | |
c8d5aac9 L |
6004 | |
6005 | /* Tell remote stub that we support XML target description. */ | |
6006 | register_remote_support_xml ("i386"); | |
c906108c | 6007 | } |